Philips 74ABTH16374BDL, 74ABTH16374BDGG, 74ABT16374BDL, 74ABT16374BDGG Datasheet

INTEGRATED CIRCUITS

74ABT16374B

74ABTH16374B

16-bit D-type flip-flop; positive-edge trigger (3-State)

Product specification

1998 Feb 27

Supersedes data of 1995 Sep 28

IC23 Data Handbook

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Philips Semiconductors	Product specification
16-bit D-type flip-flop; positive-edge trigger	74ABT16374B
(3-State)	74ABTH16374B

FEATURES

•Two 8-bit positive edge triggered registers

•Live insertion/extraction permitted

•Power-up 3-State

•Power-up reset

•Multiple VCC and GND pins minimize switching noise

•3-State output buffers

•74ABTH16373B incorporates bus-hold data inputs which eliminate the need for external pull-up resistors to hold unused inputs

•Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs

•Output capability: +64mA/±32mA

•Latch-up protection exceeds 500mA per JEDEC Std 17

•ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model

DESCRIPTION

The 74ABT16374B high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.

The 74ABT16374B has two 8-bit, edge triggered registers, with each register coupled to eight 3-State output buffers. The two sections of each register are controlled independently by the clock (nCP) and

Output Enable (nOE) control gates.

Each register is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop's Q output.

The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. Each active-Low Output Enable (nOE) controls all eight 3-State buffers for its register independent of the clock operation.

When nOE is Low, the stored data appears at the outputs for that register. When nOE is High, the outputs for that register are in the High-impedance ªOFFº state, which means they will neither drive nor load the bus.

Two options are available, 74ABT16374B which does not have the bus-hold feature and 74ABTH16374B which incorporates the bus-hold feature.

QUICK REFERENCE DATA

	SYMBOL	PARAMETER	CONDITIONS	TYPICAL	UNIT
			Tamb = 25°C; GND = 0V
	tPLH	Propagation delay	CL = 50pF; VCC = 5V	2.6	ns
	tPHL	nCP to nQx		2.2
	CIN	Input capacitance	VI = 0V or VCC	4	pF
	COUT	Output capacitance	VO = 0V or VCC; 3-State	7	pF
	ICCZ	Quiescent supply current	Outputs disabled; VCC = 5.5V	500	μA
	ICCL		Outputs Low; VCC = 5.5V	8	mA

ORDERING INFORMATION

PACKAGES	TEMPERATURE RANGE	OUTSIDE NORTH AMERICA	NORTH AMERICA	DWG NUMBER
48-Pin Plastic SSOP Type III	±40°C to +85°C	74ABT16374B DL	BT16374B DL	SOT370-1
48-Pin Plastic TSSOP Type II	±40°C to +85°C	74ABT16374B DGG	BT16374B DGG	SOT362-1
48-Pin Plastic SSOP Type III	±40°C to +85°C	74ABTH16374B DL	BH16374B DL	SOT370-1
48-Pin Plastic TSSOP Type II	±40°C to +85°C	74ABTH16374B DGG	BH16374B DGG	SOT362-1

PIN DESCRIPTION								LOGIC SYMBOL
PIN NUMBER	SYMBOL					FUNCTION			47			46		44		43		41		40		38		37
47, 46, 44, 43, 41, 40, 38, 37	1D0 ± 1D7					Data inputs
36, 35, 33, 32, 30, 29, 27, 26	2D0 ± 2D7
										1D0 1D1 1D2 1D3								1D4 1D5 1D6 1D7
2, 3, 5, 6, 8, 9, 11, 12	1Q0 ± 1Q7
						Data outputs		48		1CP
13, 14, 16, 17, 19, 20, 22, 23	2Q0 ± 2Q7
								1		1OE
						Output enable				1Q0 1Q1 1Q2 1Q3								1Q4 1Q5 1Q6 1Q7
1, 24	1OE, 2OE
						inputs (active-Low)
48, 25	1CP, 2CP					Clock pulse inputs
									2			3		5		6		8		9		11		12
						(active rising edge)
									36			35		33		32		30		29		27		26
4, 10, 15, 21, 28, 34, 39, 45		GND				Ground (0V)
						Positive supply
7, 18, 31, 42		VCC								2D0 2D21 2D2 2D3								2D4 2D5 2D6 2D7
						voltage		25		2CP
								24		2OE
										2Q0 2Q1 2Q2 2Q3								2Q4 2Q5 2Q6 2Q7
									13			14		16		17		19		20		22		23
																						SH00078

1998 Feb 27

2

853-1752 19027

Philips Semiconductors	Product specification
16-bit D-type flip-flop; positive-edge trigger	74ABT16374B
(3-State)	74ABTH16374B

LOGIC SYMBOL (IEEE/IEC)															PIN CONFIGURATION
				1											1OE					1				48			1CP
1OE						1EN
				48											1Q0					2			47				1D0
1CP								C1
				24											1Q1					3					46		1D1
2OE						2EN									GND												GND
				25																4					45
2CP								C2							1Q2												1D2
				47								2								5					44
1D0						1D				1			1Q0		1Q3					6			43				1D3
				46							3
1D1													1Q1		VCC					7			42				VCC
				44							5
1D2				43							6		1Q2		1Q4					8			41				1D4
1D3													1Q3		1Q5												1D5
				41							8									9					40
1D4													1Q4		GND												GND
				40							9									10			39
1D5													1Q5		1Q6												1D6
				38								11								11			38
1D6													1Q6		1Q7												1D7
				37							12									12			37
1D7													1Q7		2Q0												2D0
				36							13									13			36
2D0						2D				2			2Q0		2Q1												2D1
				35							14									14			35
2D1													2Q1		GND												GND
				33							16									15			34
2D2													2Q2
				32							17				2Q2					16			33				2D2
2D3													2Q3		2Q3												2D3
																				17				32
				30								19
2D4													2Q4
				29											VCC					18			31				VCC
2D5											20		2Q5
															2Q4												2D4
				27							22									19			30
2D6													2Q6
2D7				26								23	2Q7		2Q5					20			29				2D5
													SH00077		GND					21			28				GND
															2Q6					22					27		2D6
															2Q7					23					26		2D7
															2OE					24				25			2CP
																							SA00326

LOGIC DIAGRAM

nD0

nD1

nD2

nD3

nD4

nD5

nD6

nD7

D

D

D

D

D

D

D

D

CP

Q

CP

Q

CP

Q

CP

Q

CP

Q

CP

Q

CP

Q

CP

Q

nCP

nOE

nQ0

nQ1

nQ2

nQ3

nQ4

nQ5

nQ6

nQ7

SA00327

1998 Feb 27

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