Philips 74ABTH16373BDL, 74ABTH16373BDGG, 74ABT16373BDL, 74ABT16373BDGG Datasheet

INTEGRATED CIRCUITS

74ABT16373B

74ABTH16373B

16-bit transparent latch (3-State)

Product specification

1998 Feb 27

Supersedes data of 1995 Aug 03

IC23 Data Handbook

m n r

	Philips Semiconductors	Product specification
	16-bit transparent latch (3-State)	74ABT16373B
		74ABTH16373B

FEATURES

•16-bit transparent latch

•Multiple VCC and GND pins minimize switching noise

•Power-up 3-State

•Live insertion/extraction permitted

•Power-up reset

•3-State output buffers

•74ABTH16373B incorporates bus-hold data inputs which eliminate the need for external pull-up resistors to hold unused inputs

•Output capability: +64mA/±32mA

•ICCL ±19 mA maximum

•Latch-up protection exceeds 500mA per JEDEC Std 17

•ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model

DESCRIPTION

The 74ABT16373B high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.

The 74ABT16373B device is a dual octal transparent latch coupled to two sets of eight 3-State output buffers. The two sections of the device are controlled independently by Enable (nE) and Output

Enable (nOE) control gates.

The data on each set of D inputs are transferred to the latch outputs when the Latch Enable (nE) input is High. The latch remains transparent to the data inputs while nE is High, and stores the data that is present one setup time before the High-to-Low enable transition.

The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. Each active-Low Output Enable (nOE) controls eight 3-State buffers independent of the latch operation.

When nOE is Low, the latched or transparent data appears at the

outputs. When nOE is High, the outputs are in the High-impedance ªOFFº state, which means they will neither drive nor load the bus.

Two options are available, 74ABT16373B which does not have the bus-hold feature and 74ABTH16373B which incorporates the bus-hold feature.

PIN CONFIGURATION

1OE					1			48		1E
1Q0					2				47	1D0
1Q1										1D1
					3				46
GND										GND
					4				45
1Q2										1D2
					5				44
1Q3										1D3
					6				43
VCC										VCC
					7				42
1Q4					8				41	1D4
1Q5										1D5
					9				40
GND										GND
					10				39
1Q6										1D6
					11				38
1Q7										1D7
					12				37
2Q0										2D0
					13				36
2Q1										2D1
					14			35
GND										GND
					15				34
2Q2					16			33		2D2
2Q3										2D3
					17			32
VCC										VCC
					18			31
2Q4										2D4
					19			30
2Q5										2D5
					20				29
GND					21				28	GND
2Q6					22				27	2D6
2Q7					23				26	2D7
2OE					24			25		2E
									SA00379

QUICK REFERENCE DATA

	SYMBOL	PARAMETER	CONDITIONS	TYPICAL	UNIT
			Tamb = 25°C; GND = 0V
	tPLH	Propagation delay	CL = 50pF; VCC = 5V	2.5	ns
	tPHL	Dn to Qn		2.0
	CIN	Input capacitance	VI = 0V or VCC	4	pF
	COUT	Output capacitance	VO = 0V or VCC; 3-State	7	pF
	ICCZ	Quiescent supply current	Outputs disabled; VCC = 5.5V	500	μA
	ICCL		Outputs low; VCC = 5.5V	8	mA

ORDERING INFORMATION

PACKAGES	TEMPERATURE RANGE	OUTSIDE NORTH AMERICA	NORTH AMERICA	DWG NUMBER
48-Pin SSOP type III	±40°C to +85°C	74ABT16373B DL	BT16373B DL	SOT370-1
48-Pin TSSOP type II	±40°C to +85°C	74ABT16373B DGG	BT16373B DGG	SOT362-1
48-Pin SSOP type III	±40°C to +85°C	74ABTH16373B DL	BH16373B DL	SOT370-1
48-Pin TSSOP type II	±40°C to +85°C	74ABTH16373B DGG	BH16373B DGG	SOT362-1

1998 Feb 27

2

853-1751 19027

	Philips Semiconductors	Product specification
	16-bit transparent latch (3-State)	74ABT16373B
		74ABTH16373B

PIN DESCRIPTION

PIN NUMBER											SYMBOL														FUNCTION
47, 46, 44, 43, 41, 40,											1D0 ± 1D7
38, 37, 36, 35, 33, 32,																									Data inputs
											2D0 ± 2D7
30, 29, 27, 26
2, 3, 5, 6, 8, 9, 11, 12,											1Q0 ± 1Q7
13, 14, 16, 17, 19, 20,																									Data outputs
											2Q0 ± 2Q7
22, 23
																							Output enable inputs
1, 24											1OE, 2OE
																									(active-Low)
48, 25												1E, 2E													Enable inputs
																									(active-High)
4, 10, 15, 21, 28, 34,													GND												Ground (0V)
39, 45
7, 18, 31, 42														VCC											Positive supply
																										voltage
LOGIC SYMBOL
		47						46			44			43				41		40			38		37
		1D0 1D1 1D2 1D3																1D4 1D5 1D6 1D7
48		1LE
1
		1OE
		1Q0 1Q1 1Q2 1Q3																1Q4 1Q5 1Q6 1Q7
		2						3			5			6				8		9			11		12
		36						35			33			32				30		29			27		26
			2D0 2D21 2D2 2D3															2D4 2D5 2D6 2D7
25		2LE
24
		2OE
		2Q0 2Q1 2Q2 2Q3																2Q4 2Q5 2Q6 2Q7
		13						14			16			17				19		20			22		23
																							SA00044

LOGIC SYMBOL (IEEE/IEC)

					1	1EN
1OE
					48	C3
1E
					24	2EN
2OE
2E					25	C4
1D0					47	3D			1		2	1Q0
					46						3
1D1												1Q1
					44						5
1D2												1Q2
					43						6
1D3												1Q3
					41						8
1D4												1Q4
					40						9
1D5												1Q5
					38						11
1D6												1Q6
					37						12
1D7												1Q7
					36						13
2D0						4D			2			2Q0
					35						14
2D1												2Q1
					33						16
2D2												2Q2
					32						17
2D3												2Q3
					30						19
2D4												2Q4
					29						20
2D5												2Q5
					27						22
2D6												2Q6
					26						23
2D7												2Q7
								SA00380

LOGIC DIAGRAM

nD0	nD1	nD2	nD3	nD4	nD5	nD6	nD7
D	D	D	D	D	D	D	D
E Q	E Q	E Q	E Q	E Q	E Q	E Q	E Q
nLE
nOE
nQ0	nQ1	nQ2	nQ3	nQ4	nQ5	nQ6	nQ7
							SA00046
1998 Feb 27			3