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INTEGRATED CIRCUITS
74ABT16373B
74ABTH16373B
16-bit transparent latch (3-State)
Product specification
Supersedes data of 1995 Aug 03
IC23 Data Handbook
1998 Feb 27
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Philips Semiconductors Product specification
16-bit transparent latch (3-State)
FEA TURES
•16-bit transparent latch
•Multiple V
•Power-up 3-State
•Live insertion/extraction permitted
•Power-up reset
•3-State output buffers
•74ABTH16373B incorporates bus-hold data inputs which
eliminate the need for external pull-up resistors to hold unused
inputs
•Output capability: +64mA/–32mA
•I
CCL
•Latch-up protection exceeds 500mA per JEDEC Std 17
•ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
DESCRIPTION
The 74ABT16373B high-performance BiCMOS device combines
low static and dynamic power dissipation with high speed and high
output drive.
The 74ABT16373B device is a dual octal transparent latch coupled
to two sets of eight 3-State output buffers. The two sections of the
device are controlled independently by Enable (nE) and Output
Enable (nOE
The data on each set of D inputs are transferred to the latch outputs
when the Latch Enable (nE) input is High. The latch remains
transparent to the data inputs while nE is High, and stores the data
that is present one setup time before the High-to-Low enable
transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. Each
active-Low Output Enable (nOE
independent of the latch operation.
and GND pins minimize switching noise
CC
–19 mA maximum
) control gates.
) controls eight 3-State buffers
74ABT16373B
74ABTH16373B
When nOE
outputs. When nOE
“OFF” state, which means they will neither drive nor load the bus.
Two options are available, 74ABT16373B which does not have the
bus-hold feature and 74ABTH16373B which incorporates the
bus-hold feature.
PIN CONFIGURATION
is Low, the latched or transparent data appears at the
is High, the outputs are in the High-impedance
1OE
1Q0
1Q1
GND
1Q2
1Q3
V
1Q4
1Q5
GND
1Q6
1Q7
2Q0
2Q1
GND
2Q2
2Q3
V
2Q4
2Q5
GND
2Q6
2Q7
2OE
1
2
3
4
5
6
7
CC
8
9
10
11
12
13
14
15
16
17
18
CC
19
20
21
22
23
24
48
1E
47
1D0
1D1
46
GND
45
1D2
44
43
1D3
42
V
41
1D4
1D5
40
GND
39
1D6
38
1D7
37
2D0
36
2D1
35
GND
34
33
2D2
2D3
32
31
V
2D4
30
29
2D5
28
GND
27
2D6
26
2D7
25
2E
SA00379
CC
CC
QUICK REFERENCE DA TA
SYMBOL PARAMETER
t
PLH
t
PHL
C
IN
C
OUT
I
CCZ
I
CCL
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
48-Pin SSOP type III –40°C to +85°C 74ABT16373B DL BT16373B DL SOT370-1
48-Pin TSSOP type II –40°C to +85°C 74ABT16373B DGG BT16373B DGG SOT362-1
48-Pin SSOP type III –40°C to +85°C 74ABTH16373B DL BH16373B DL SOT370-1
48-Pin TSSOP type II –40°C to +85°C 74ABTH16373B DGG BH16373B DGG SOT362-1
1998 Feb 27 853-1751 19027
CONDITIONS
T
= 25°C; GND = 0V
amb
Propagation delay
Dn to Qn
CL = 50pF; VCC = 5V
Input capacitance VI = 0V or V
CC
TYPICAL UNIT
2.5
2.0
ns
4 pF
Output capacitance VO = 0V or VCC; 3-State 7 pF
pp
Outputs disabled; VCC = 5.5V 500 µA
Outputs low; VCC = 5.5V 8 mA
2
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Philips Semiconductors Product specification
16-bit transparent latch (3-State)
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
47, 46, 44, 43, 41, 40,
38, 37, 36, 35, 33, 32,
30, 29, 27, 26
2, 3, 5, 6, 8, 9, 11, 12,
13, 14, 16, 17, 19, 20,
22, 23
1, 24 1OE, 2OE
48, 25 1E, 2E
4, 10, 15, 21, 28, 34,
39, 45
7, 18, 31, 42 V
LOGIC SYMBOL
48
1
1D0 – 1D7
2D0 – 2D7
1Q0 – 1Q7
2Q0 – 2Q7
GND Ground (0V)
47 46 44 43
1D0 1D1 1D2 1D3
1LE
1OE
1Q0 1Q1 1Q2651Q3
CC
41 40 38 37
1D4 1D5 1D6 1D7
1Q4 1Q5 1Q6
Data inputs
Data outputs
Output enable inputs
(active-Low)
Enable inputs
(active-High)
Positive supply
voltage
1Q7
LOGIC SYMBOL (IEEE/IEC)
1OE
1E
2OE
2E
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
1
48
24
25
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1EN
C3
2EN
C4
3D
4D
74ABT16373B
74ABTH16373B
1 ∇
2 ∇
SA00380
2
1Q0
3
1Q1
5
1Q2
6
1Q3
8
1Q4
9
1Q5
11
1Q6
12
1Q7
13
2Q0
14
2Q1
16
2Q2
17
2Q3
19
2Q4
20
2Q5
22
2Q6
23
2Q7
36 35 33 32
25
24
2D02D212D2 2D3
2LE
2OE
2Q0 2Q1 2Q2 2Q3
LOGIC DIAGRAM
nD0
nLE
32
1413 1716
D
E Q
98
30 29 27 26
2D4 2D5 2D6 2D7
2Q4 2Q5 2Q6 2Q7
2019 2322
SA00044
nD1
D
EQ
1211
nD2
D
EQ
nD3
D
EQ
nD4
D
EQ
nD5
D
EQ
nD6
D
EQ
nD7
D
EQ
nOE
1998 Feb 27
nQ0
nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7
SA00046
3