INTEGRATED CIRCUITS
74ABT16260/74ABTH16260
12-bit to 24-bit multiplexed D-type latches (3-State)
Product specification |
1998 Feb 10 |
Supersedes data of 1996 Nov 20
IC23 Data Handbook
m n r
Philips Semiconductors |
Product specification |
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12-bit to 24-bit multiplexed D-type latches (3-State)
74ABT16260
74ABTH16260
FEATURES
•ESD protection exceeds 2000V per Mil-Std-883C, Method 3015; exceeds 200V using machine model (C = 200pF, R = 0).
•Latch-up performance exceeds 500mA per JEDEC Standard JESD-17.
•Distributed VCC and GND pin configuration minimizes high-speed switching noise.
•Flow-through architecture optimizes PCB layout.
•High-drive outputs (±32mA IOH, 64mA IOL).
•74ABTH16260 incorporates bus-hold inputs which eliminate the need for external pull-up resistors.
•Package options:
±56-pin plastic Shrink Small-Outline Package (SSOP)
±56-pin plastic Thin Shrink Small-Outline Package (TSSOP)
QUICK REFERENCE DATA
DESCRIPTION
The 74ABT16260/74ABTH16260 is a 12-bit to 24-bit multiplexed D-type latch used in applications where two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing and/or demultiplexing of address and data information in microprocessor or bus-interface applications. This device is alto useful in memory-interleaving applications.
Three 12-bit I/O ports (A1±A12, 1B1±1B12, and 2B1±2B12) are available for address and/or data transfer. The output enable (OE1B, OE2B, and OEA) inputs control the bus transceiver functions. The
OE1B and OE2B control signals also allow bank control in the A to B direction.
Address and/or data information can be stored using the internal storage latches. The latch enable (LE1B, LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch enable input is high, the latch is transparent. When the latch enable input goes low, the data present at the inputs is latched and remains latched until the latch enable input is returned high.
To ensure the high-impedance state during power-up or power-down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current sinking capability of the driver.
The 74ABTH incorporates the bus hold feature. The 74ABT does not include bus hold feature. Both parts are available in 56-pin
SSOP and TSSOP.
SYMBOL |
PARAMETER |
CONDITIONS |
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TYPICAL |
UNIT |
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Tamb = 25°C; GND = 0V |
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tPLH |
Propagation delay |
CL = 50 pF |
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2.8 |
ns |
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tPHL |
nAx to nBx nBx to nAx |
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2.5 |
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CIN |
Input capacitance |
VI = 0 V or VCC |
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4 |
pF |
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COUT |
Output capacitance |
VI/O = 0 V or 5.0 |
V |
6 |
pF |
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ICCZ |
Total supply current |
Outputs disabled |
100 |
μA |
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ORDERING INFORMATION
PACKAGES |
TEMPERATURE RANGE |
OUTSIDE NORTH AMERICA |
NORTH AMERICA |
DWG NUMBER |
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56-Pin Plastic SSOP Type III |
±40°C to +85°C |
74ABT16260 DL |
BT16260 DL |
SOT371-1 |
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56-Pin Plastic TSSOP Type II |
±40°C to +85°C |
74ABT16260 DGG |
BT16260 DGG |
SOT364-1 |
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56-Pin Plastic SSOP Type III |
±40°C to +85°C |
74ABTH16260 DL |
BH16260 DL |
SOT371-1 |
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56-Pin Plastic TSSOP Type II |
±40°C to +85°C |
74ABTH16260 DGG |
BH16260 DGG |
SOT364-1 |
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PIN DESCRIPTION
PIN NUMBER |
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SYMBOL |
FUNCTION |
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8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21 |
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An |
Data inputs/outputs (A) |
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23, 24, 26, 31, 33, 34, 36, 37, 38, 40, 41, 42 |
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1Bn |
Data inputs/outputs (B1) |
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6, 5, 3, 54, 52, 51, 49, 48, 47, 45, 44, 43 |
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2Bn |
Data inputs/outputs (B2) |
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1, 29, 56 |
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Output enable input (active low) |
OEA, |
OE1B, |
OE2B |
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2, 27, 30, 55 |
LE1B, LE2B, LEA1B, LEA2B |
Latch enable inputs |
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1998 Feb 10 |
2 |
853-2048-18945 |
Philips Semiconductors |
Product specification |
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12-bit to 24-bit multiplexed D-type latches (3-State)
74ABT16260
74ABTH16260
PIN CONFIGURATION
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OEA |
1 |
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56 |
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OE2B |
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LE1B |
2 |
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55 |
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LEA2B |
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2B3 |
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2B4 |
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3 |
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54 |
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GND |
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GND |
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4 |
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53 |
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2B2 |
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2B5 |
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5 |
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52 |
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2B1 |
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2B6 |
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6 |
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51 |
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VCC |
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VCC |
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7 |
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50 |
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A1 |
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2B7 |
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8 |
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49 |
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A2 |
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2B8 |
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9 |
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48 |
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A3 |
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2B9 |
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10 |
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47 |
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GND |
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46 |
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GND |
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11 |
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A4 |
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2B10 |
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12 |
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45 |
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A5 |
13 |
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44 |
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2B11 |
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A6 |
14 |
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43 |
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2B12 |
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A7 |
15 |
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42 |
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1B12 |
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A8 |
16 |
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41 |
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1B11 |
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A9 |
17 |
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40 |
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1B10 |
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GND |
18 |
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39 |
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GND |
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A10 |
19 |
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38 |
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1B9 |
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A11 |
20 |
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37 |
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1B8 |
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A12 |
21 |
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36 |
1B7 |
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VCC |
22 |
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35 |
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VCC |
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1B1 |
23 |
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34 |
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1B6 |
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1B2 |
24 |
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33 |
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1B5 |
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GND |
25 |
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32 |
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GND |
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1B3 |
26 |
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31 |
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1B4 |
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LE2B |
27 |
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30 |
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LEA1B |
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SEL |
28 |
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29 |
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OE1B |
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FUNCTION TABLES
B to A (OEB = H)
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INPUTS |
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OUTPUT |
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1B |
2B |
SEL |
LE1B |
LE2B |
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OEA |
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A |
H |
X |
H |
H |
X |
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L |
H |
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L |
X |
H |
H |
X |
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L |
L |
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X |
X |
H |
L |
X |
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L |
A0 |
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X |
H |
L |
X |
H |
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L |
H |
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X |
L |
L |
X |
H |
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L |
L |
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X |
X |
L |
X |
L |
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L |
A0 |
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X |
X |
X |
X |
X |
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H |
Z |
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A to B (OEA = H)
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INPUTS |
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OUTPUT |
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A |
LEA1B |
LEA2B |
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OE1B |
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OE2B |
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1B |
2B |
H |
H |
H |
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L |
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L |
H |
H |
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L |
H |
H |
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L |
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L |
L |
L |
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H |
H |
L |
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L |
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L |
H |
2B0 |
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L |
H |
L |
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L |
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L |
L |
2B0 |
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H |
L |
H |
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L |
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L |
1B0 |
H |
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L |
L |
H |
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L |
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L |
1B0 |
L |
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X |
L |
L |
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L |
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L |
1B0 |
2B0 |
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X |
X |
X |
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H |
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H |
Z |
Z |
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X |
X |
X |
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L |
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H |
Active |
Z |
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X |
X |
X |
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H |
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L |
Z |
Active |
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X |
X |
X |
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L |
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L |
Active |
Active |
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SA00435
1998 Feb 10 |
3 |
Philips Semiconductors |
Product specification |
|
|
|
|
12-bit to 24-bit multiplexed D-type latches (3-State)
74ABT16260
74ABTH16260
LOGIC DIAGRAM (POSITIVE LOGIC)
2 |
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LE1B |
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27 |
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LE2B |
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30 |
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LEA1B |
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55 |
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LEA2B |
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56 |
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OE2B |
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29 |
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OE1B |
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1 |
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OEA |
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28 |
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SEL |
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C1 |
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G1 |
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8 |
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23 |
A1 |
1 |
1D |
1B1 |
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1 |
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C1 |
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1D |
6 |
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2B1 |
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C1 |
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1D |
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C1 |
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1D |
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TO 11 OTHER CHANNELS |
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SA00436 |
1998 Feb 10 |
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4 |
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