Philips 74ABTH161543DL, 74ABTH161543DGG, 74ABT161543DL, 74ABT161543DGG Datasheet

INTEGRATED CIRCUITS

74ABT161543

74ABTH161543

16-bit latched transceiver with

dual enable and master reset (3-State)

Product specification

1998 Feb 27

Supersedes data of 1995 Sep 18

IC23 Data Handbook

m n r

Philips Semiconductors	Product specification
16-bit latched transceiver with dual enable	74ABT161543
and master reset (3-State)	74ABTH161543

FEATURES

•Two 8-bit octal transceivers with D-type latch

•Live insertion/extraction permitted

•Power-up 3-State

•Power-up reset

•Multiple VCC and GND pins minimize switching noise

•Back-to-back registers for storage

•Separate controls for data flow in each direction

•74ABTH161543 incorporates Bus hold data inputs which eliminate the need for external pull-up resistors to hold unused inputs

•Output capability: +64mA/±32mA

•Latch-up protection exceeds 500mA per Jedec Std 17

•ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model

•Same function as ABT16543 except for additional Master Reset control pins

QUICK REFERENCE DATA

DESCRIPTION

The 74ABT161543 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.

The 74ABT161543 16-bit registered transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable (nLEAB, nLEBA) and Output

Enable (nOEAB, nOEBA) inputs are provided for each register to permit independent control of data transfer in either direction. Master reset (MR) clears all registers simultaneously and sets them Low. The outputs are guaranteed to sink 64mA.

Two options are available, 74ABT161543 which does not have the Bus hold feature and 74ABTH161543 which inorporates the Bus hold feature.

	SYMBOL	PARAMETER	CONDITIONS	TYPICAL	UNIT
			Tamb = 25°C; GND = 0V
	tPLH	Propagation delay	CL = 50pF; VCC = 5V	2.5	ns
	tPHL	nAx to nBx		2.2
	CIN	Input capacitance	VI = 0V or VCC	3	pF
	CI/O	I/O capacitance	VO = 0V or VCC; 3-State	7	pF
	ICCZ	Quiescent supply current	Outputs disabled; VCC = 5.5V	500	μA
	ICCL		Outputs low; VCC = 5.5V	9	mA

ORDERING INFORMATION

PACKAGES	TEMPERATURE RANGE	ORDER CODE	DRAWING NUMBER
56-pin plastic SSOP Type III	±40°C to +85°C	BT161543DL	SOT371-1
56-pin plastic TSSOP Type II	±40°C to +85°C	BT161543DGG	SOT364-1

ORDERING INFORMATION

PACKAGES	TEMPERATURE RANGE	OUTSIDE NORTH AMERICA	NORTH AMERICA	DWG NUMBER
56-Pin Plastic SSOP Type III	±40°C to +85°C	74ABT161543 DL	BT161543 DL	SOT371-1
56-Pin Plastic TSSOP Type II	±40°C to +85°C	74ABT161543 DGG	BT161543 DGG	SOT364-1
56-Pin Plastic SSOP Type III	±40°C to +85°C	74ABTH161543 DL	BH161543 DL	SOT371-1
56-Pin Plastic TSSOP Type II	±40°C to +85°C	74ABTH161543 DGG	BH161543 DGG	SOT364-1

PIN DESCRIPTION

PIN NUMBER

SYMBOL

NAME AND FUNCTION

5, 6, 8, 9, 10, 12, 13, 14

1A0 ± 1A7,

Data inputs/outputs

15, 16, 17, 19, 20, 21, 23, 24

2A0 ± 2A7

52, 51, 49, 48, 47, 45, 44, 43

1B0 ± 1B7,

Data inputs/outputs

42, 41, 40,38, 37, 36, 34, 33

2B0 ± 2B7

1, 56

1OEAB,

1OEBA,

A to B / B to A Output Enable inputs (active-Low)

28, 29

2OEAB, 2OEBA

3, 54

1EAB,

1EBA,

A to B / B to A Enable inputs (active-Low)

26, 31

2EAB, 2EBA

2, 55

1LEAB,

1LEBA,

A to B / B to A Latch Enable inputs (active-Low)

27, 30

2LEAB, 2LEBA

4, 25

Master reset

MRab, MRba

11, 18, 32, 39, 46, 53

GND

Ground (0V)

7, 22, 35, 50

VCC

Positive supply voltage

1998 Feb 27

2

853-1798 19026

Philips Semiconductors Product specification

16-bit latched transceiver with dual enable		74ABT161543
and master reset (3-State)		74ABTH161543
LOGIC SYMBOL (IEEE/IEC)	PIN CONFIGURATION

MRab 4 1OEAB 1

1EAB 3 1LEAB 2

2OEAB 28 2EAB 26

2LEAB 27 MRba 25

1OEBA 56 1EBA 54

1LEBA 55 2OEBA 29

2EBA 31 2LEBA 30

1A0 5

1A1 6

1A2 8

1A3 9

1A4 10

1A5 12

1A6 13

1A7 14

2A0 15

2A1 16

2A2 17

2A3 19

2A4 20

2A5 21

2A6 23

2A7 24

				1OEAB	1	56	1OEBA
R6/R12				1LEAB	2	55	1LEBA
2EN4				1EAB	3	54	1EBA
G2				MRab	4	53	GND
2C6				1A0	5	52	1B0
8EN10				1A1	6	51	1B1
G8				VCC	7	50	VCC
8C12				1A2	8	49	1B2
R5/R11				1A3	9	48	1B3
1EN3				1A4	10	47	1B4
G1				GND	11	46	GND
1C5				1A5	12	45	1B5
7EN9				1A6	13	44	1B6
G7				1A7	14	43	1B7
7C11				2A0	15	42	2B0
				2A1	16	41	2B1
3	5D	52	1B0	2A2	17	40	2B2
6D	4			GND	18	39	GND
		51	1B1	2A3	19	38	2B3
		49	1B2	2A4	20	37	2B4
		48	1B3	2A5	21	36	2B5
		47	1B4	VCC	22	35	VCC
		45
			1B5	2A6	23	34	2B6
		44	1B6	2A7	24	33	2B7
		43	1B7	MRba	25	32	GND
9	11D	42	2B0	2EAB	26	31	2EBA
12D	10			2LEAB	27	30	2LEBA
		41	2B1	2OEAB	28	29	2OEBA
		40	2B2
						SH00061
		38	2B3
		37	2B4
		36	2B5
		34	2B6
		33	2B7
		SH00060

1998 Feb 27

3

Philips Semiconductors Product specification

16-bit latched transceiver with dual enable																								74ABT161543
and master reset (3-State)																								74ABTH161543
LOGIC SYMBOL															FUNCTIONAL DESCRIPTION
															The 74ABT161543						contains two sets of eight D-type latches, with
															separate control pins for each set. Using data flow from A to B as an
																										input and the A-to-B Latch
															example, when the A-to-B Enable (nEAB)
															Enable					input are Low the A-to-B path is transparent.
																		(nLEAB)
															A subsequent Low-to-High transition of the														signal puts the A
	5			6		8	9	10	12	13	14																nLEAB
															data into the latches where it is stored and the B outputs no longer
															change with the A inputs. With							EAB	and			nOEAB		both Low, the
		1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7													3-State B output buffers are active and display the data present at
															the outputs of the A latches.
3		1EAB									MRab			4	Control of data flow from B to A is similar, but using the
54		1EBA								1OEAB			1																	nEBA,
2		1LEAB								1OEBA			56		nLEBA, and nOEBA inputs.
55		1LEBA									MRba			25
		1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7
	52			51		49	48	47	45	44	43
	15			16		17	19	20	21	23	24
		2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7
26		2EAB									MRab			4
31		2EBA								2OEAB			28
27		2LEAB								2OEBA			29
30		2LEBA									MRba			25
		2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7
	42			41		40	38	37	36	34	33
													SH00064

FUNCTION TABLE

INPUTS

OUTPUTS

STATUS

nOEXX

nMRXX

nEXX

nLEXX

nAx or nBx

nBx or nAx

L

L

L

X

X

L

Clear

H

X

X

X

X

Z

Disabled

X

X

H

X

X

Z

Disabled

L

H

↑

L

h

Z

Disabled + Latch

L

H

↑

L

l

Z

L

H

L

↑

h

H

Latch + Display

L

H

L

↑

l

L

L

H

L

L

H

H

Transparent

L

H

L

L

L

L

L

H

L

H

X

NC

Hold

H

=

High voltage level

h

=

High voltage level one set-up time prior to the Low-to-High transition of

nLEXX

or

nEXX

(XX = AB or BA)

L

=

Low voltage level

or

(XX = AB or BA)

l

=

Low voltage level one set-up time prior to the Low-to-High transition of

nLEXX

nEXX

X

=

Don't care

↑

=

Low-to-High transition of

or

(XX = AB or BA)

nLEXX

nEXX

NC=

No change

Z

=

High impedance or ªoffº state

1998 Feb 27

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