Philips 74ABT899DB, 74ABT899D, 74ABT899A Datasheet

INTEGRATED CIRCUITS

74ABT899

9-bit dual latch transceiver with 8-bit parity generator/checker (3-State)

Product specification

1998 Jan 16

Supersedes data of 1993 Oct 04 IC23 Data Handbook

m n r

Philips Semiconductors	Product specification

9-bit dual latch transceiver with 8-bit parity

74ABT899

generator/checker (3-State)

FEATURES

•Symmetrical (A and B bus functions are identical)

•Selectable generate parity or ºfeed-throughº parity for A-to-B and

B-to-A directions

•Independent transparent latches for A-to-B and B-to-A directions

•Selectable ODD/EVEN parity

•Continuously checks parity of both A bus and B bus latches as ERRA and ERRB

•Ability to simultaneously generate and check parity

•Can simultaneously read/latch A and B bus data

•Output capability: +64 mA/±32mA

•Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17

•ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model

•Power up 3-State

•Power-up reset

•Live insertion/extraction permitted

QUICK REFERENCE DATA

DESCRIPTION

The 74ABT899 is a 9-bit to 9-bit parity transceiver with separate transparent latches for the A bus and B bus. Either bus can generate or check parity. The parity bit can be fed-through with no change or the generated parity can be substituted with the SEL input.

Parity error checking of the A and B bus latches is continuously provided with ERRA and ERRB, even with both buses in 3-State.

The 74ABT899 features independent latch enables for the A and B bus latches, a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity.

FUNCTIONAL DESCRIPTION

The 74ABT899 has three principal modes of operation which are outlined below. All modes apply to both the A-to-B and B-to-A directions.

Transparent latch, Generate parity, Check A and B bus parity:

Bus A (B) communicates to Bus B (A), parity is generated and passed on to the B (A) Bus as BPAR (APAR). If LEA and LEB are High and the Mode Select (SEL) is Low, the parity generated from

A0-A7 and B0-B7 can be checked and monitored by ERRA and ERRB. (Fault detection on both input and output buses.)

Transparent latch, Feed-through parity, Check A and B bus parity:

Bus A (B) communicates to Bus B (A) in a feed-through mode if SEL is High. Parity is still generated and checked as ERRA and ERRB and can be used as an interrupt to signal a data/parity bit error to the

CPU.

Latched input, Generate/Feed-through parity, Check A (and B) bus parity:

Independent latch enables (LEA and LEB) allow other permutations of:

•Transparent latch / 1 bus latched / both buses latched

•Feed-through parity / generate parity

•Check in bus parity / check out bus parity / check in and out bus parity

SYMBOL				PARAMETER	CONDITIONS	TYPICAL	UNIT
					Tamb = 25°C; GND = 0V
tPLH	Propagation delay				CL = 50pF; VCC = 5V	2.9	ns
tPHL	An to Bn or Bn to An
tPLH	Propagation delay				CL = 50pF; VCC = 5V	6.1	ns
tPHL	An to ERRA
CIN	Input capacitance				VI = 0V or VCC	4	pF
CI/O	Output capacitance				Outputs disabled; VO = 0V or VCC	7	pF
ICCZ	Total supply current				Outputs disabled; VCC =5.5V	50	μA

ORDERING INFORMATION

PACKAGES	TEMPERATURE RANGE	OUTSIDE NORTH AMERICA	NORTH AMERICA	DWG NUMBER
28-Pin Plastic PLCC	±40°C to +85°C	74ABT899 A	74ABT899 A	SOT261-3
28-Pin Plastic SOP	±40°C to +85°C	74ABT899 D	74ABT899 D	SOT136-1
28-Pin Plastic SSOP	±40°C to +85°C	74ABT899 DB	74ABT899 DB	SOT341-1

1998 Jan 16

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853-1623 18864

Philips Semiconductors	Product specification

9-bit dual latch transceiver with 8-bit parity

74ABT899

generator/checker (3-State)

PIN CONFIGURATION

ODD/EVEN						1		28	VCC
	ERRA					2		27		OEB
									B0
			LEA			3		26
			A0						B1
						4		25
			A1						B2
						5		24
			A2						B3
						6		23
			A3						B4
						7	TOP VIEW	22
			A4						B5
						8		21
			A5						B6
						9		20
			A6						B7
						10		19
			A7						BPAR
						11		18
		APAR
						12		17	LEB
			OEA			13		16		SEL
		GND				14		15		ERRB
								SA00289

PIN DESCRIPTION

	SYMBOL									PIN	NAME AND FUNCTION
										NUMBER
										4, 5, 6, 7,
	A0 - A7									8, 9, 10,	Latched A bus 3-State inputs/outputs
										11
										19, 20,
	B0 - B7									21, 22,	Latched B bus 3-State inputs/outputs
										23, 24,
										25, 26
			APAR							12	A bus parity 3-State input
			BPAR							18	B bus parity 3-State input
			ODD/							1	Parity select input (Low for EVEN
			EVEN								parity)
											Output enable inputs (gate A to B,
	OEA, OEB									13, 27
											B to A)
										16	Mode select input (Low for generate)
				SEL
	LEA, LEB									3, 17	Latch enable inputs (transparent High)
		ERRA,								2, 15	Error signal outputs (active-Low)
		ERRB
			GND							14	Ground (0V)
				VCC						28	Positive supply voltage

PLCC PIN CONFIGURATION

						B1	B2	B3	B4	B5	B6	B7
					25		24	23	22	21	20	19
			B0 26									18	BPAR
				27								17	LEB
			OEB
			VCC 28									16
													SEL
	ODD/				1							15
													ERRB
EVEN
					2							14	GND
		ERRA
			LEA		3							13
													OEA
			A0		4							12	APAR
							6	7	8	9	10	11
					5
						A1	A2	A3	A4	A5	A6	A7
												SA00291

LOGIC SYMBOL

	4	5	6	7	8	9	10	11	12
	A0	A1	A2	A3	A4	A5	A6	A7 APAR
3	LEA
17	LEB
16	SEL							ERRA		2
1	ODD/EVEN							ERRB		15
27	OEB
13	OEA
	B0	B1	B2	B3	B4	B5	B6	B7 BPAR
	26	25	24	23	22	21	20	19	18
									SA00290

1998 Jan 16

3

Philips Semiconductors	Product specification

9-bit dual latch transceiver with 8-bit parity

74ABT899

generator/checker (3-State)

				OE	27	OEB
			9±bit
			Transparent
			Latch	9±bit
				Output
				Buffer
	LEA	3	LE
	A0	4		1	26	B0
		5	Parity	mux
	A1				25
						B1
		6	Generator	0
	A2				24
						B2
	A3	7			23
						B3
		8
	A4				22
						B4
		9
	A5				21
						B5
		10
	A6				20
						B6
		11
	A7				19
						B7
	APAR	12			18
						BPAR
				9±bit
				Transparent
				Latch
			9±bit
			Output
			Buffer
	OEA	13	OE	LE	17	LEB
			1
			mux	Parity	2
			0			ERRA
				Generator
	SEL	16
					15	ERRB
	ODD/	1
	EVEN					SA00292

FUNCTION TABLE

INPUTS

OPERATING MODE

LEA

LEB

OEB

OEA

SEL

H

H

X

X

X

3-State A bus and B bus (input A & B simultaneously)

H

L

L

L

H

B → A, transparent B latch, generate parity from B0 - B7, check B bus parity

H

L

L

H

H

B → A, transparent A & B latch, generate parity from B0 - B7, check A & B bus parity

H

L

L

X

L

B → A, B bus latched, generate parity from latched B0 - B7 data, check B bus parity

H

L

H

X

H

B → A, transparent B latch, parity feed-through, check B bus parity

H

L

H

H

H

B → A, transparent A & B latch, parity feed-through, check A & B bus parity

L

H

L

H

X

A → B, transparent A latch, generate parity from A0 - A7, check A bus parity

L

H

L

H

H

A → B, transparent A & B latch, generate parity from A0 - A7, check A & B bus parity

L

H

L

L

X

A → B, A bus latched, generate parity from latched A0 - A7 data, check A bus parity

L

H

H

H

L

A → B, transparent A latch, parity feed-through, check A bus parity

L

H

H

H

H

A → B, transparent A & B latch, parity feed-through, check A & B bus parity

L

L

X

X

X

Output to A bus and B bus (NOT ALLOWED)

H

=

High voltage level

L

=

Low voltage level

X

=

Don't care

1998 Jan 16

4

Philips Semiconductors	Product specification

9-bit dual latch transceiver with 8-bit parity

74ABT899

generator/checker (3-State)

PARITY AND ERROR FUNCTION TABLE

INPUTS

OUTPUTS

xPAR

S of High

xPAR

SEL

ODD/EVEN

ERRt

ERRr*

(A or B)

Inputs

(B or A)

PARITY MODES

H

H

H

Even

H

H

H

Odd

H

L

L

Odd

H

H

L

Even

L

L

L

Mode

Feed-through/check parity

Odd

L

H

H

H

L

H

Even

H

L

L

Odd

H

H

H

Even

H

L

L

Even

L

H

H

Mode

Odd

L

L

L

L

H

H

Even

H

H

H

Odd

L

L

H

Odd

L

H

L

Even

H

L

H

Mode

Generate parity

Odd

L

H

H

L

L

H

Even

L

L

H

Odd

H

H

H

Even

L

L

L

Even

L

H

H

Mode

Odd

H

L

H

H

=

High voltage level

L

=

Low voltage level

t

= Transmit±if the data path is from A→ B then

is

ERRt

ERRA

r

= Receive±if the data path is from A→ B then

is

ERRr

ERRB

*Blocked if latch is not transparent

ABSOLUTE MAXIMUM RATINGS1, 2

SYMBOL	PARAMETER	CONDITIONS	RATING	UNIT
VCC	DC supply voltage		±0.5 to +7.0	V
IIK	DC input diode current	VI < 0	±18	mA
VI	DC input voltage3		±1.2 to +7.0	V
IOK	DC output diode current	VO < 0	±50	mA
V	DC output voltage3	output in Off or High state	±0.5 to +5.5	V
OUT
IOUT	DC output current	output in Low state	128	mA
Tstg	Storage temperature range		±65 to 150	°C

NOTES:

1.Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

2.The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 1505C.

3.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

1998 Jan 16

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