Philips 74ABT853PW, 74ABT853N, 74ABT853DB, 74ABT853D Datasheet

Philips Semiconductors	Product specification

8-bit transceiver with 9-bit parity checker/

74ABT853

generator and flag latch (3-State)

FEATURES

•Low static and dynamic power dissipation with high speed and high output drive

•Open-collector ERROR output

•Output capability: +64mA/±32mA

•Latch-up protection exceeds 500mA per Jedec Std 17

•ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model

•Power-up 3-State

•Live insertion/extraction permitted

DESCRIPTION

The 74ABT853 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.

The 74ABT853 is an octal transceiver with a parity generator/checker and is intended for bus±oriented applications.

When Output Enable A (OEA) is High, it will place the A outputs in a high impedance state. Output Enable B (OEB) controls the B outputs in the same way.

The parity generator creates an odd parity output (PARITY) when OEB is Low. When OEA is Low, the parity of the B port, including the PARITY input, is checked for odd parity. When an error is detected, the error data is sent to the input of a latch. The error data can then be passed, stored, cleared, or sampled depending on the ENABLE and CLEAR control signals.

If both OEA and OEB are Low, data will flow from the A bus to the B bus and the part is forced into an error condition which creates an inverted PARITY output. This error condition can be used by the designer for system diagnostics.

QUICK REFERENCE DATA

	SYMBOL	PARAMETER	CONDITIONS	TYPICAL	UNIT
			Tamb = 25°C; GND = 0V
	tPLH	Propagation delay	CL = 50pF; VCC = 5V	3.4	ns
	tPHL	An to Bn or Bn to An
	tPLH	Propagation delay	CL = 50pF; VCC = 5V	7.4	ns
	tPHL	An to PARITY
	CIN	Input capacitance	VI = 0V or VCC	4	pF
	CI/O	I/O capacitance	Outputs disabled; VO = 0V or VCC	7	pF
	ICCZ	Total supply current	Outputs disabled; VCC =5.5V	50	μA

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

OUTSIDE NORTH AMERICA

NORTH AMERICA

DWG NUMBER

24-Pin Plastic DIP

±40°C to +85°C

74ABT853 N

74ABT853 N

SOT222-1

24-Pin plastic SO

±40°C to +85°C

74ABT853 D

74ABT853 D

SOT137-1

24-Pin Plastic SSOP Type II

±40°C to +85°C

74ABT853 DB

74ABT853 DB

SOT340-1

24-Pin Plastic TSSOP Type I

±40°C to +85°C

74ABT853 PW

74ABT853PW DH

SOT355-1

PIN CONFIGURATION

LOGIC SYMBOL

OEA

1

24

VCC

A0

2

23

B0

A1

3

22

B1

2

3

4

5

6

7

8

9

A2

4

21

B2

A3

5

20

B3

A0

A1

A2

A3

A4

A5

A6

A7

14

OEB

A4

6

19

B4

15

A5

1

OEA

PARITY

7

18

B5

11

CLEAR

ERROR

10

A6

8

17

B6

A7

13

ENABLE

9

16

B7

B0

B1

B2

B3

B4

B5

B6

B7

10

15

PARITY

ERROR

CLEAR

11

14

OEB

23

22

21

20

19

18

17

16

GND

12

13

ENABLE

TOP VIEW

SA00262

SA00263

1995 Sep 06

1

853-1672 15702

Philips Semiconductors	Product specification

8-bit transceiver with 9-bit parity checker/

74ABT853

generator and flag latch (3-State)

PIN DESCRIPTION

SYMBOL									PIN NUMBER	NAME AND FUNCTION
		A0 ± A7							2, 3, 4, 5, 6, 7, 8, 9	A port 3±State inputs/outputs
		B0 ± B7							23, 22, 21, 20, 19, 18, 17, 16	B port 3±State inputs/outputs
									1	Enables the A outputs when Low
				OEA
									14	Enables the B outputs when Low
				OEB
		PARITY							15	Parity output/input
									10	Error output (open collector)
		ERROR
									11	Clears the error flag register when Low
			CLEAR
									13	Enable input (active-Low)
	ENABLE
			GND						12	Ground (0V)
				VCC					24	Positive supply voltage

FUNCTION TABLE

INPUTS

OUTPUTS

An

Bn + PARITY

MODE

OEB

OEA

An

Bn

PARITY

Σ OF HIGHS

Σ OF HIGHS

A data to B bus and generate odd parity output

L

H

Odd

(output)

(input)

An

L

Even

H

B data to A bus and check for parity error1

H

L

(output)

X

Bn

(input)

(input)

A bus and B bus disabled2

H

H

X

X

Z

Z

Z

A data to B bus and generate inverted parity output

L

L

Odd

(output)

(input)

An

H

Even

L

NOTES:

1.Error checking is detailed in the Error Flag Function Table below.

2.When ENABLE is Low, ERROR is Low if the sum of A inputs is even or ERROR is High if the sum of A inputs is odd.

ERROR FLAG FUNCTION TABLE

INPUTS

INTERNAL NODE

OUTPUT

Bn + PARITY

PRE±STATE

ERROR

MODE

ENABLE

CLEAR

POINT ºPº

Σ OF HIGHS

ERRORn±1

OUTPUT

Pass

L

L

Odd

H

X

H

Even

L

L

Odd

H

H

H

Sample

L

H

Even

L

X

L

X

X

L

L

Clear

H

L

X

X

X

H

Store

H

H

X

X

L

L

H

H

H

= High voltage level steady state

L

= Low voltage level steady state

X

= Don't care

Z

= High impedance ºoffº state

1995 Sep 06

2

Philips Semiconductors	Product specification

8-bit transceiver with 9-bit parity checker/

74ABT853

generator and flag latch (3-State)

LOGIC DIAGRAM

8				8
A0 ± A7				B0 ± B7
	8
OEB
				PARITY
OEA
8	8
		MUX		9±bit
	}			Odd
		B		Parity
			9	Tree
				ºPº
	} A
	Sel A/B
				ERROR
ENABLE
CLEAR
				SA00264

ABSOLUTE MAXIMUM RATINGS1, 2

SYMBOL	PARAMETER	CONDITIONS	RATING	UNIT
VCC	DC supply voltage		±0.5 to +7.0	V
IIK	DC input diode current	VI < 0	±18	mA
VI	DC input voltage3		±1.2 to +7.0	V
IOK	DC output diode current	VO < 0	±50	mA
V	DC output voltage3	output in Off or High state	±0.5 to +5.5	V
OUT
IOUT	DC output current	output in Low state	128	mA
Tstg	Storage temperature range		±65 to 150	°C

NOTES:

1.Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

2.The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

1995 Sep 06

3