74ABT845N
Philips Semiconductors Product specification
74ABT845
8-bit bus interface latch with set and reset
(3-State)
1
1995 Sep 06 853-1703 15702
FEA TURES
•High speed parallel latches
•Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
•Broadside pinout
•Output capability: +64mA/–32mA
•Power-up 3-State
•Power-up reset
•Latch-up protection exceeds 500mA per Jedec Std 17
•ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
DESCRIPTION
The 74ABT845 consists of eight D-type latches with 3-State outputs.
In addition to the LE, OE
, MR and PRE pins, the 74ABT845 has two
additional OE
pins, making a total of three Output Enable (OE0,
OE
1, OE2) pins. The multiple Output enables allow multiuser control
of the interface, e.g., CS
, DMA, and RD/WR.
QUICK REFERENCE DAT A
SYMBOL PARAMETER
CONDITIONS
T
amb
= 25°C; GND = 0V
TYPICAL UNIT
t
PLH
t
PHL
Propagation delay
Dn to Qn
C
L
= 50pF; V
CC
= 5V 5.4 ns
C
IN
Input capacitance V
I
= 0V or V
CC
4 pF
C
OUT
Output capacitance
Outputs disabled;
V
O
= 0V or V
CC
7 pF
I
CCZ
Total supply current Outputs disabled; V
CC
= 5.5V 500 nA
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
24-Pin Plastic DIP –40°C to +85°C 74ABT845 N 74ABT845 N SOT222-1
24-Pin plastic SO –40°C to +85°C 74ABT845 D 74ABT845 D SOT137-1
24-Pin Plastic SSOP Type II –40°C to +85°C 74ABT845 DB 74ABT845 DB SOT340-1
24-Pin Plastic TSSOP Type I –40°C to +85°C 74ABT845 PW 74ABT845PW DH SOT355-1
PIN CONFIGURA TION
1
2
3
4
5
6
7
8
9
10 15
16
17
18
19
20
21
22
23
24
OE0
OE1
D0
D1
D2
D3
D4
D5
D6 Q6
D7
Q5
Q4
Q3
Q2
Q1
Q0
OE
2
V
CC
Q7
11 14MR
PRE
12 13GND
LE
TOP VIEW
SA00258
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
1, 2, 23 OE0 – OE2
Output enable inputs
(active-Low)
3, 4, 5, 6,
7, 8, 9, 10
D0-D7 Data inputs
22, 21, 20, 19,18,
17, 16, 15
Q0-Q7 Data outputs
11 MR Master reset input (active-Low)
13 LE
Latch enable input
(active-High)
14 PRE Preset input (active-Low)
12 GND Ground (0V)
24 V
CC
Positive supply voltage
Philips Semiconductors Product specification
74ABT845
8-bit bus interface latch with set and reset
(3-State)
1995 Sep 06
2
LOGIC SYMBOL (IEEE/IEC)
3
4
5
6
7
8
9
C1
13
R
11
10
S2
14
23
EN
2
1
&
21D
22
21
20
19
18
17
16
15
SA00260
LOGIC SYMBOL
13
14
LE
PRE
11
1
MR
OE0
2 OE1
23 OE2
345678910
D0 D1 D2 D3 D4 D5 D6 D7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
22 21 20 19 18 17 16 15
SA00259
FUNCTION TABLE
INPUTS
OUTPU
TS
OPERATING
MODE
OE
n
PR
E
MR LE Dn Qn
L L X X X H Preset
L H L X X L Clear
L
L
H
H
H
H
H
H
L
H
L
H
Transparent
L
L
H
H
H
H
↓
↓
l
h
L
H
Latched
H X X X X Z High impedance
L H H L X NC Hold
H = High voltage level
h = High voltage level one set-up time prior to the High-to-Low LE
transition
L = Low voltage level
l = Low voltage level one set-up time prior to the High-to-Low LE
transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↓ = High-to-Low transition
LOGIC DIAGRAM
13
LE
2
OE
1
LQ
D
3
D0
Q0
22
LQ
D
4
D1
Q1
21
LQ
D
5
D2
Q2
20
LQ
D
6
D3
Q3
19
LQ
D
7
D4
Q4
18
LQ
D
8
D5
Q5
17
LQ
D
9
D6
Q6
16
LQ
D
10
D7
Q7
PPPPPPPP
15
C C C C C C C C
11
MR
14
PRE
OE0
OE2
1
23
SA00261
Philips Semiconductors Product specification
74ABT845
8-bit bus interface latch with set and reset
(3-State)
1995 Sep 06
3
ABSOLUTE MAXIMUM RATINGS
1,2
SYMBOL
PARAMETER CONDITIONS RATING UNIT
V
CC
DC supply voltage –0.5 to +7.0 V
I
IK
DC input diode current V
I
< 0 –18 mA
V
I
DC input voltage
3
–1.2 to +7.0 V
I
OK
DC output diode current V
O
< 0 –50 mA
V
OUT
DC output voltage
3
output in Off or High state –0.5 to +5.5 V
I
OUT
DC output current output in Low state 128 mA
T
stg
Storage temperature range –65 to 150 °C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER LIMITS UNIT
Min Max
V
CC
DC supply voltage 4.5 5.5 V
V
I
Input voltage 0 V
CC
V
V
IH
High-level input voltage 2.0 V
V
IL
Low-level input voltage 0.8 V
I
OH
High-level output current –32 mA
I
OL
Low-level output current 64 mA
∆t/∆v Input transition rise or fall rate 0 5 ns/V
T
amb
Operating free-air temperature range –40 +85 °C
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