Philips 74ABT843PW, 74ABT843N, 74ABT843DB, 74ABT843D Datasheet

INTEGRATED CIRCUITS

74ABT843

9-bit interface latch with set and reset (3-State)

Product specification

1998 Jan 16

Supersedes data of 1995 Sep 06 IC23 Data Handbook

m n r

Philips Semiconductors	Product specification

9-bit bus interface latch with set and reset

74ABT843

(3-State)

FEATURES

•High speed parallel latches

•Extra data width for wide address/data paths or buses carrying parity

•Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors

•Slim DIP 300 mil package

•Broadside pinout

•Output capability: +64mA/±32mA

•Latch-up protection exceeds 500mA per Jedec Std 17

•ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model

•Power-up 3-State

•Power-up reset

DESCRIPTION

The 74ABT843 Bus interface latch is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity.

The 74ABT843 consists of nine D-type latches with 3-State outputs. In addition to the LE and OE pins, it has a Master Reset (MR) pin and Preset (PRE) pin. These pins are ideal for parity bus interfacing in high performance systems. When MR is Low, the outputs are Low if OE is Low. When MR is High, data can be entered into the latch.

When PRE is Low, the outputs are High, if OE is Low. PRE overrides MR.

QUICK REFERENCE DATA

	SYMBOL	PARAMETER	CONDITIONS	TYPICAL	UNIT
			Tamb = 25°C; GND = 0V
	tPLH	Propagation delay	CL = 50pF; VCC = 5V	5.0	ns
	tPHL	Dn to Qn
	CIN	Input capacitance	VI = 0V or VCC	4	pF
	COUT	Output capacitance	Outputs disabled;	7	pF
			VO = 0V or VCC
	ICCZ	Total supply current	Outputs disabled; VCC = 5.5V	500	nA

ORDERING INFORMATION

PACKAGES	TEMPERATURE RANGE	OUTSIDE NORTH AMERICA	NORTH AMERICA	DWG NUMBER
24-Pin Plastic DIP	±40°C to +85°C	74ABT843 N	74ABT843 N	SOT222-1
24-Pin plastic SO	±40°C to +85°C	74ABT843 D	74ABT843 D	SOT137-1
24-Pin Plastic SSOP Type II	±40°C to +85°C	74ABT843 DB	74ABT843 DB	SOT340-1
24-Pin Plastic TSSOP Type I	±40°C to +85°C	74ABT843 PW	74ABT843PW DH	SOT355-1

PIN CONFIGURATION								PIN DESCRIPTION
			1	24	VCC			PIN NUMBER	SYMBOL					FUNCTION
	OE
														Output enable input
	D0		2	23	Q0			1			OE
														(active-Low)
	D1		3	22	Q1
								2, 3, 4, 5, 6,	D0-D8					Data inputs
	D2		4	21	Q2
								7, 8, 9, 10
	D3		5	20	Q3
								23, 22, 21, 20,	Q0-Q8					Data outputs
	D4		6	19	Q4			19,18, 17, 16, 15
				TOP VIEW
								11						Master reset input (active-Low)
	D5		7	18	Q5						MR
	D6		8	17	Q6			13			LE			Latch enable input (active rising
	D7		9	16	Q7									edge)
								14						Preset input (active-Low)
	D8		10	15	Q8					PRE
			11	14				12	GND					Ground (0V)
	MR
					PRE
GND			12	13	LE			24		VCC				Positive supply voltage
				SA00250

1998 Jan 16

2

853-1620 18864

Philips Semiconductors	Product specification

9-bit bus interface latch with set and reset

74ABT843

(3-State)

LOGIC SYMBOL																						LOGIC SYMBOL (IEEE/IEC)
																						1				EN
																						11				R
		2		3		4		5		6		7		8		9		10				14				S2
																						13
																										C1
		D0		D1		D2		D3		D4		D5		D6		D7		D8
13		LE																					2			1D	23
14		PRE
																							3					22
11		MR																					4					21
1		OE																					5					20
		Q0		Q1 Q2				Q3 Q4				Q5 Q6				Q7		Q8
																							6					19
																							7					18
		23		22		21		20		19		18		17		16		15					8					17
																							9					16
																SA00251
																							10					15
																												SA00252

FUNCTION TABLE

INPUTS

OUTPUTS

OPERATING MODE

LE

Dn

Qn

OE

PRE

MR

L

L

X

X

X

H

Preset

L

H

L

X

X

L

Clear

L

H

H

H

L

L

Transparent

L

H

H

H

H

H

L

H

H

↓

l

L

Latched

L

H

H

↓

h

H

H

X

X

X

X

Z

High impedance

L

H

H

L

X

NC

Hold

H

=

High voltage level

h

=

High voltage level one set-up time prior to the High-to-Low LE transition

L

=

Low voltage level

l

=

Low voltage level one set-up time prior to the High-to-Low LE transition

NC=

No change

X

=

Don't care

Z

=

High impedance ªoffº state

↓ =

High-to-Low transition

1998 Jan 16

3

Philips Semiconductors	Product specification

9-bit bus interface latch with set and reset

74ABT843

(3-State)

LOGIC DIAGRAM

D0	D1	D2	D3	D4	D5	D6	D7	D8
2	3	4	5	6	7	8	9		10
14
PRE
P	P	P	P	P	P	P	P		P
D	D	D	D	D	D	D	D		D
L Q	L Q	L Q	L Q	L Q	L Q	L Q	L Q		L Q
C	C	C	C	C	C	C	C		C
11
MR
13
LE
1
OE
	23	22	21	20	19	18	17	16	15
	Q0	Q1	Q2	Q3	Q4	Q5	Q6	Q7	Q8
									SA00253

ABSOLUTE MAXIMUM RATINGS1, 2

SYMBOL	PARAMETER	CONDITIONS	RATING	UNIT
VCC	DC supply voltage		±0.5 to +7.0	V
IIK	DC input diode current	VI < 0	±18	mA
VI	DC input voltage3		±1.2 to +7.0	V
IOK	DC output diode current	VO < 0	±50	mA
V	DC output voltage3	output in Off or High state	±0.5 to +5.5	V
OUT
IOUT	DC output current	output in Low state	128	mA
Tstg	Storage temperature range		±65 to 150	°C

NOTES:

1.Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

2.The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

1998 Jan 16

4

Philips Semiconductors	Product specification

9-bit bus interface latch with set and reset

74ABT843

(3-State)

RECOMMENDED OPERATING CONDITIONS

SYMBOL	PARAMETER		LIMITS		UNIT
		Min		Max
VCC	DC supply voltage	4.5		5.5	V
VI	Input voltage	0		VCC	V
VIH	High-level input voltage	2.0			V
VIL	Low-level input voltage			0.8	V
IOH	High-level output current			±32	mA
IOL	Low-level output current			64	mA
t/ v	Input transition rise or fall rate	0		10	ns/V
Tamb	Operating free-air temperature range	±40		+85	°C

DC ELECTRICAL CHARACTERISTICS

								LIMITS
SYMBOL	PARAMETER		TEST CONDITIONS			Tamb = +25°C			Tamb = ±40°C		UNIT
									to +85°C
						Min	Typ	Max	Min	Max
VIK	Input clamp voltage	VCC = 4.5V; IIK = ±18mA					±0.9	±1.2		±1.2	V
		VCC = 4.5V; IOH = ±3mA; VI = VIL or VIH				2.5	2.9		2.5		V
VOH	High±level output voltage	VCC = 5.0V; IOH = ±3mA; VI = VIL or VIH				3.0	3.4		3.0		V
		VCC = 4.5V; IOH = ±32mA; VI = VIL or VIH				2.0	2.4		2.0		V
VOL	Low±level output voltage	VCC = 4.5V; IOL = 64mA; VI = VIL or VIH					0.42	0.55		0.55	V
VRST	Power±up output low	VCC = 5.5V; IO = 1mA; VI = VCC or GND					0.13	0.55		0.55	V
	voltage3
II	Input leakage current	VCC = 5.5V; VI = GND or 5.5V					±0.01	±1.0		±1.0	μA
IOFF	Power-off leakage current	VCC = 0.0V; VO or VI ≤ 4.5V					±5.0	±100		±100	μA
	Power-up/down 3±state	VCC = 2.0V; VO = 0.5V; V			= VCC; VI =
IPU/IPD				OE			±5.0	±50		±50	μA
	output current4	GND or VCC
IOZH	3-State output High current	VCC = 5.5V; VO = 2.7V; VI = VIL or VIH					5.0	50		50	μA
IOZL	3-State output Low current	VCC = 5.5V; VO = 0.5V; VI = VIL or VIH					±5.0	±50		±50	μA
ICEX	Output high leakage current	VCC = 5.5V; VO = 5.5V; VI = GND or VCC					5.0	50		50	μA
I	Output current1	V	= 5.5V; V = 2.5V			±50	±80	±180	±50	±180	mA
O		CC	O
ICCH		VCC = 5.5V; Outputs High, VI = GND or VCC					0.5	250		250	μA
ICCL	Quiescent supply current	VCC = 5.5V; Outputs Low, VI = GND or VCC					25	34		34	mA
ICCZ		VCC = 5.5V; Outputs 3-State;					0.5	250		250	μA
		VI = GND or VCC
ICC	Additional supply current per	VCC = 5.5V; one input at 3.4V,					0.5	1.5		1.5	mA
	input pin2	other inputs at VCC or GND

NOTES:

1.Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

2.This is the increase in supply current for each input at 3.4V.

3.For valid test results, data must not be loaded into the flip±flops (or latches) after applying the power.

4.This parameter is valid for any VCC between 0V and 2.1V with a transition time of up to 10msec. For VCC = 2.1V to VCC = 5V 10%, a transition time of up to 100μsec is permitted.

1998 Jan 16

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