74ABT841PW
Philips Semiconductors Product specification
74ABT84110-bit bus interface latch (3-State)
FEA TURES
•High speed parallel latches
•Extra data width for wide address/data paths or buses carrying
parity
•Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
•Slim DIP 300 mil package
•Broadside pinout
•Output capability: +64mA/–32mA
•Latch-up protection exceeds 500mA per Jedec Std 17
•ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
•Power-up 3-State
•Power-up reset
QUICK REFERENCE DAT A
SYMBOL PARAMETER
C
t
PLH
t
PHL
C
OUT
I
CCZ
IN
Propagation delay
Dn to Qn
Input capacitance VI = 0V or V
Output capacitance
Total supply current Outputs disabled; VCC = 5.5V 500 nA
DESCRIPTION
The 74ABT841 Bus interface register is designed to provide extra
data width for wider data/address paths of buses carrying parity.
The 74ABT841 consists of ten D-type latches with 3-State outputs.
The flip-flops appear transparent to the data when Latch Enable
(LE) is High. This allows asynchronous operation, as the output
transition follows the data in transition. On the LE High-to-Low
transition, the data that meets the setup and hold time is latched.
Data appears on the bus when the Output Enable (OE
When OE
T
is High the output is in the High-impedance state.
CONDITIONS
= 25°C; GND = 0V
amb
TYPICAL UNIT
CL = 50pF; VCC = 5V 4.1 ns
CC
Outputs disabled;
= 0V or V
V
O
CC
4 pF
7 pF
) is Low.
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
24-Pin Plastic DIP –40°C to +85°C 74ABT841 N 74ABT841 N SOT222-1
24-Pin plastic SO –40°C to +85°C 74ABT841 D 74ABT841 D SOT137-1
24-Pin Plastic SSOP Type II –40°C to +85°C 74ABT841 DB 74ABT841 DB SOT340-1
24-Pin Plastic TSSOP Type I –40°C to +85°C 74ABT841 PW 74ABT841PW DH SOT355-1
PIN CONFIGURA TION
1
OE
2
D0
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
9
D7 Q7
10 15
D8
11 14D9
12 13GND
TOP VIEW
24
V
CC
Q0
23
Q1
22
Q2
21
Q3
20
Q4
19
Q5
18
Q6
17
16
Q8
Q9
LE
SA00247
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
1 OE
2, 3, 4, 5, 6,
7, 8, 9, 10, 11
23, 22, 21, 20, 19,
18, 17, 16, 15, 14
D0-D9 Data inputs
Q0-Q9 Data outputs
13 LE
12 GND Ground (0V)
24 V
Output enable input
(active-Low)
Latch enable input (active
falling edge)
Positive supply voltage
CC
1995 Sep 06 853-1628 15703
1
Philips Semiconductors Product specification
10-bit bus interface latch (3-State)
LOGIC SYMBOL
234567891011
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
13 LE
1OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
23 22 21 20 19 18 17 16 15 14
SA00244
74ABT841
FUNCTION TABLE
INPUTS OUTPUTS
OE LE Dn Q0 – Q9
L
L
L
L
H
H
↓
↓
L
H
l
h
L
H
L
H
H X X Z High impedance
L L X NC Hold
H = High voltage level
h = High voltage level one set-up time prior to the High-to-Low LE
transition
L = Low voltage level
l = Low voltage level one set-up time prior to the High-to-Low LE
transition
↓ = High-to-Low LE transition
NC= No change
X = Don’t care
Z = High impedance “off” state
OPERATING
MODE
Transparent
Latched
LOGIC SYMBOL (IEEE/IEC)
1
13
10 15
11 14
EN
C1
223
1D
322
421
520
619
718
817
916
SA00245
1995 Sep 06
2
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