Philips 74abt834 DATASHEETS
Philips Semiconductors Advanced BiCMOS Products Objective specification
74ABT834
Octal inverting transceiver with parity
generator/checker (3–State)
1
June 9, 1992
FEATURES
•Low static and dynamic power dissipation
with high speed and high output drive
•Open–collector ERROR output
•Output capability: +64mA/–32mA
•Latch–up protection exceeds 500mA per
Jedec JC40.2 Std 17
•ESD protection exceeds 2000 V per MIL
STD 883C Method 3015.6 and 200 V per
Machine Model
•Power up/down 3–State
DESCRIPTION
The 74ABT834 high–performance BiCMOS
device combines low static and dynamic
power dissipation with high speed and high
output drive.
The 74ABT834 is an octal inverting
transceiver with a parity generator/checker
and is intended for bus–oriented applications.
When Output Enable A (OEA
) is High, it will
place the A outputs in a high impedance
state. Output Enable B (OEB
) controls the B
outputs in the same way.
The parity generator creates an odd parity
output (PARITY) when OEB
is Low. When
OEA
is Low, the parity of the B port, including
the PARITY input, is checked for odd parity.
When an error is detected, the error data is
sent to the input of a storage register. If a
Low–to–High transition happens at the clock
input (CP), the error data is stored in the
register and the Open–collector error flag
(ERROR
) will go Low. The error flag register
is cleared with a Low pulse on the CLEAR
input.
If both OEA
and OEB are Low, data will flow
from the A bus to the B bus and the part is
forced into an error condition which creates
an inverted PARITY output. This error
condition can be used by the designer for
system diagnostics.
QUICK REFERENCE DATA
SYMBOL PARAMETER
CONDITIONS
T
amb
= 25°C; GND = 0V
TYPICAL UNIT
t
PLH
t
PHL
Propagation delay
An to Bn or Bn to An
CL = 50pF; VCC = 5V 3.4 ns
t
PLH
t
PHL
Propagation delay
An to PARITY
CL = 50pF; VCC = 5V 7.4 ns
C
IN
Input capacitance VI = 0V or V
CC
4 pF
C
OUT
Output capacitance VI = 0V or V
CC
7 pF
I
CCZ
Total supply current Outputs disabled; VCC =5.5V 50 µA
ORDERING INFORMATION
PACKAGES
CONDITIONS
T
amb
= 25°C; GND = 0V
ORDER CODE
24–pin plastic DIP (300mil) –40°C to +85°C 74ABT834N
24–pin plastic SOL (300mil) –40°C to +85°C 74ABT834D
PIN CONFIGURATION LOGIC SYMBOL
24
23
22
21
20
19
18
17
16
15
14
1312
10
11
9
8
7
6
5
4
3
2
1
V
CC
GND
CLEAR
OEA
B0
B1
B2
B3
B6
B7
PARITY
OEB
A0
A1
A2
A3
A4
A5
A6
A7
ERROR
CP
B4
B5
OEB
OEA
CLEAR
14
1
11
15
10
PARITY
ERROR
TOP VIEW
CP13
2 3 4 5 6 7 8 9
A0 A1 A2 A3 A4 A5 A6 A7
B0 B1 B2 B3 B4 B5 B6 B7
23 22 21 20 19 18 17 16
Philips Semiconductors Advanced BiCMOS Products Objective specification
74ABT834
Octal inverting transceiver with parity
generator/checker (3–State)
June 9, 1992
2
PIN DESCRIPTION
SYMBOL PIN NUMBER NAME AND FUNCTION
A0 – A7
2, 3, 4, 5,
6, 7, 8, 9
A port 3–State inputs/outputs
B0 – B7
23, 22, 21, 20,
19, 18, 17, 16
B port 3–State inputs/outputs
OEA 1 Enables the A outputs when Low
OEB 14 Enables the B outputs when Low
PARITY 15 Parity output
ERROR 10 Error output
CLEAR 11 Clears the error flag register when Low
CP 13 Clock input
GND 12 Ground (0V)
V
CC
24 Positive supply voltage
FUNCTION TABLE
INPUTS OUTPUTS
MODE OEB OEA
An
Σ of Highs
Bn + Parity
Σ of Lows
An Bn PARITY
A data to B bus and generate odd parity
output
L H
Odd
Even
NA
(output)
NA
(input)
An
H
L
B data to A bus and check for parity error
1
H L
NA
(output)
Odd
Even
Bn
NA
(input)
NA
(input)
A bus and B bus disabled
2
H H X X Z Z Z
A data to B bus and generate inverted
parity output
L L
Odd
Even
NA
(output)
NA
(input)
An
L
H
NOTES:
1. Error checking is detailed in the Error Flag Function T able below.
2. When clocked, the error output is Low if the sum of A inputs is even or High if the sum of A inputs is odd.
ERROR FLAG FUNCTION TABLE
INPUTS Internal node Output
MODE CLEAR CP
Bn + Parity
Σ of Lows
Point ”P”
Pre–state
ERROR
n–1
ERROR
OUTPUT
Sample
H
H
H
↑
↑
X
Odd
Even
X
H
L
X
H
X
L
H
L
L
Hold H ↑ X X X NC
Clear L X X X X H
H = High voltage level steady state
L = Low voltage level steady state
X = Don’t care
NA = Not applicable
NC = No change
Z = High impedance ”off” state
↑ = Low–to–High clock transition
↑
= Not a Low–to–High clock transition
Philips Semiconductors Advanced BiCMOS Products Objective specification
74ABT834
Octal inverting transceiver with parity
generator/checker (3–State)
June 9, 1992
3
LOGIC DIAGRAM
8 8
8
88
MUX
Sel A/B
}
A
}
B
9
9–bit
Odd
Parity
Tree
”P”
D
R
A0 – A7
OEB
OEA
CP
CLEAR
B0 – B7
PARITY
ERROR
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
PARAMETER CONDITIONS RATING UNIT
V
CC
DC supply voltage –0.5 to +7.0 V
I
IK
DC input diode current VI < 0 –18 mA
V
I
DC input voltage
3
–1.2 to +7.0 V
I
OK
DC output diode current VO < 0 –50 mA
V
OUT
DC output voltage
3
output in Off or High state –0.5 to +5.5 V
I
OUT
DC output current output in Low state 128 mA
T
stg
Storage temperature range –65 to 150 °C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
2. The performance capability of a high–performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
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