Philips 74ABT833PW, 74ABT833N, 74ABT833DB, 74ABT833D Datasheet

INTEGRATED CIRCUITS

74ABT833

Octal transceiver with parity generator/checker (3-State)

Product specification

1993 Jun 21

IC23 Data Handbook

m n r

Philips Semiconductors	Product specification

Octal transceiver with parity generator/checker

74ABT833

(3-State)

FEATURES

•Low static and dynamic power dissipation with high speed and high output drive

•Open-collector ERROR output with flag register

•Output capability: +64mA/±32mA

•Latch-up protection exceeds 500mA per Jedec Std 17

•ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200 V per Machine Model

•Power up/down 3-State

•Live insertion/extraction permitted

DESCRIPTION

The 74ABT833 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.

The 74ABT833 is an octal transceiver with a parity generator/checker and is intended for bus-oriented applications.

When Output Enable A (OEA) is High, it will place the A outputs in a high impedance state. Output Enable B (OEB) controls the B outputs in the same way.

The parity generator creates an odd parity output (PARITY) when OEB is Low. When OEA is Low, the parity of the B port, including the PARITY input, is checked for odd parity. When an error is detected, the error data is sent to the input of a storage register. If a Low-to-High transition happens at the clock input (CP), the error data is stored in the register and the Open-collector error flag (ERROR) will go Low. The error flag register is cleared with a Low pulse on the CLEAR input.

If both OEA and OEB are Low, data will flow from the A bus to the B bus and the part is forced into an error condition which creates an inverted PARITY output. This error condition can be used by the designer for system diagnostics.

QUICK REFERENCE DATA

	SYMBOL	PARAMETER	CONDITIONS	TYPICAL	UNIT
			Tamb = 25°C; GND = 0V
	tPLH	Propagation delay	CL = 50pF; VCC = 5V	3.4	ns
	tPHL	An to Bn or Bn to An
	tPLH	Propagation delay	CL = 50pF; VCC = 5V	7.4	ns
	tPHL	An to PARITY
	CIN	Input capacitance	VI = 0V or VCC	4	pF
	CI/O	I/O capacitance	Outputs disabled;	7	pF
			VO = 0V or VCC
	ICCZ	Total supply current	Outputs disabled; VCC =5.5V	50	μA

ORDERING INFORMATION

PACKAGES	TEMPERATURE RANGE	OUTSIDE NORTH AMERICA	NORTH AMERICA	DWG NUMBER
24-Pin Plastic DIP	±40°C to +85°C	74ABT833 N	74ABT833 N	SOT222-1
24-Pin plastic SO	±40°C to +85°C	74ABT833 D	74ABT833 D	SOT137-1
24-Pin Plastic SSOP Type II	±40°C to +85°C	74ABT833 DB	74ABT833 DB	SOT340-1
24-Pin Plastic TSSOP Type I	±40°C to +85°C	74ABT833 PW	74ABT833PW DH	SOT355-1

PIN CONFIGURATION																	PIN DESCRIPTION
																	SYMBOL					PIN NUMBER	NAME AND FUNCTION
			OEA				1				24		VCC					A0 ± A7				2, 3, 4, 5,	A port 3-State inputs/outputs
																						6, 7, 8, 9
			A0				2				23		B0
																		B0 ± B7				23, 22, 21, 20,	B port 3-State inputs/outputs
			A1				3				22		B1									19, 18, 17, 16
			A2				4				21		B2										Enables the A outputs when
																			OEA			1
																							Low
			A3				5				20		B3
																							Enables the B outputs when
			A4				6				19		B4						OEB			14
																							Low
			A5										B5
							7				18							PARITY				15	Parity output/input
			A6
							8				17		B6									10	Error output (open collector)
																		ERROR
			A7
							9				16		B7										Clears the error flag register
																		CLEAR				11
																							when Low
	ERROR						10				15		PARITY
																			CP			13	Clock input
		CLEAR					11				14		OEB
																		GND				12	Ground (0V)
			GND			12					13		CP
																			VCC			24	Positive supply voltage
								TOP VIEW							SA00212

1993 Jun 21

2

853±1619 10087

Philips Semiconductors	Product specification

Octal transceiver with parity generator/checker

74ABT833

(3-State)

LOGIC SYMBOL

2

3

4

5

6

7

8

9

A0

A1

A2

A3

A4

A5

A6

A7

14

OEB

PARITY

15

1

OEA

11

CLEAR

ERROR

10

13

CP

B0

B1

B2

B3

B4

B5

B6

B7

23

22

21

20

19

18

17

16

SA00213

FUNCTION TABLE

INPUTS

OUTPUTS

An

Bn + Parity

MODE

OEB

OEA

An

Bn

PARITY

S of Highs

S of Highs

A data to B bus and generate odd parity

L

H

Odd

(output)

(input)

An

L

output

Even

H

B data to A bus and check for parity error1

H

L

(output)

X

Bn

(input)

(input)

A bus and B bus disabled2

H

H

X

X

Z

Z

Z

A data to B bus and generate inverted

L

L

Odd

(output)

(input)

An

H

parity output

Even

L

NOTES:

1.Error checking is detailed in the Error Flag Function Table below.

2.When clocked, the error output is Low if the sum of A inputs is even or High if the sum of A inputs is odd.

ERROR FLAG FUNCTION TABLE

INPUTS

Internal node

Output

MODE

CLEAR

CP

Bn + Parity

Point ºPº

Pre±state

ERROR

S of Highs

ERRORn±1

OUTPUT

H

↑

Odd

H

H

H

Sample

H

↑

Even

L

X

L

H

X

X

X

L

L

Hold

H

↑

X

X

X

NC

Clear

L

X

X

X

X

H

H

=

High voltage level steady state

L

=

Low voltage level steady state

X

=

Don't care

NC

=

No change

Z

=

High impedance ºoffº state

↑= Low-to-High clock transition

↑= Not a Low-to-High clock transition

1993 Jun 21

3

Philips Semiconductors	Product specification

Octal transceiver with parity generator/checker

74ABT833

(3-State)

LOGIC DIAGRAM

8				8
A0 ± A7					B0 ± B7
	8
OEB
					PARITY
OEA
8	8
		MUX		9±bit
	}			Odd
		B		Parity
			9	Tree
				ºPº
	} A
	Sel A/B
				D	ERROR
CP
CLEAR				R
					SA00214

ABSOLUTE MAXIMUM RATINGS1, 2

SYMBOL	PARAMETER	CONDITIONS	RATING	UNIT
VCC	DC supply voltage		±0.5 to +7.0	V
IIK	DC input diode current	VI < 0	±18	mA
VI	DC input voltage3		±1.2 to +7.0	V
IOK	DC output diode current	VO < 0	±50	mA
V	DC output voltage3	output in Off or High state	±0.5 to +5.5	V
OUT
IOUT	DC output current	output in Low state	128	mA
Tstg	Storage temperature range		±65 to 150	°C

NOTES:

1.Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

2.The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

1993 Jun 21

4