Philips 74ABT833PW, 74ABT833N, 74ABT833DB, 74ABT833D Datasheet
INTEGRATED CIRCUITS
74ABT833
Octal transceiver with parity
generator/checker (3-State)
Product specification 1993 Jun 21
IC23 Data Handbook
Philips Semiconductors Product specification
Octal transceiver with parity generator/checker
(3-State)
FEA TURES
•Low static and dynamic power dissipation with high speed and
high output drive
•Open-collector ERROR output with flag register
•Output capability: +64mA/–32mA
•Latch-up protection exceeds 500mA per Jedec Std 17
•ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200 V per Machine Model
•Power up/down 3-State
•Live insertion/extraction permitted
DESCRIPTION
The 74ABT833 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
QUICK REFERENCE DATA
SYMBOL PARAMETER
t
PLH
t
PHL
t
PLH
t
PHL
C
C
I
CCZ
IN
I/O
Propagation delay
An to Bn or Bn to An
Propagation delay
An to PARITY
CL = 50pF; VCC = 5V 3.4 ns
CL = 50pF; VCC = 5V 7.4 ns
Input capacitance VI = 0V or V
I/O capacitance
Outputs disabled;
= 0V or V
V
O
Total supply current Outputs disabled; VCC =5.5V 50 µA
The 74ABT833 is an octal transceiver with a parity
generator/checker and is intended for bus-oriented applications.
When Output Enable A (OEA
high impedance state. Output Enable B (OEB
outputs in the same way.
The parity generator creates an odd parity output (PARITY) when
OEB
is Low. When OEA is Low, the parity of the B port, including
the PARITY input, is checked for odd parity. When an error is
detected, the error data is sent to the input of a storage register. If a
Low-to-High transition happens at the clock input (CP), the error
data is stored in the register and the Open-collector error flag
(ERROR
pulse on the CLEAR
If both OEA
bus and the part is forced into an error condition which creates an
inverted PARITY output. This error condition can be used by the
designer for system diagnostics.
CONDITIONS
= 25°C; GND = 0V
T
amb
CC
CC
74ABT833
) is High, it will place the A outputs in a
) controls the B
) will go Low. The error flag register is cleared with a Low
input.
and OEB are Low, data will flow from the A bus to the B
TYPICAL UNIT
4 pF
7 pF
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
24-Pin Plastic DIP –40°C to +85°C 74ABT833 N 74ABT833 N SOT222-1
24-Pin plastic SO –40°C to +85°C 74ABT833 D 74ABT833 D SOT137-1
24-Pin Plastic SSOP Type II –40°C to +85°C 74ABT833 DB 74ABT833 DB SOT340-1
24-Pin Plastic TSSOP Type I –40°C to +85°C 74ABT833 PW 74ABT833PW DH SOT355-1
PIN CONFIGURATION
OEA
A0
A1
A2
A3
A4
A5
A6
A7
ERROR
CLEAR
GND
1
2
3
4
5
6
7
8
9
10
11
TOP VIEW
24
23
22
21
20
19
18
17
16
15
14
1312
V
CC
B0
B1
B2
B3
B4
B5
B6
B7
PARITY
OEB
CP
SA00212
PIN DESCRIPTION
SYMBOL PIN NUMBER NAME AND FUNCTION
A0 – A7
B0 – B7
OEA 1
OEB 14
PARITY 15 Parity output/input
ERROR 10 Error output (open collector)
CLEAR 11
CP 13 Clock input
GND 12 Ground (0V)
V
CC
2, 3, 4, 5,
6, 7, 8, 9
23, 22, 21, 20,
19, 18, 17, 16
A port 3-State inputs/outputs
B port 3-State inputs/outputs
Enables the A outputs when
Low
Enables the B outputs when
Low
Clears the error flag register
when Low
24 Positive supply voltage
1993 Jun 21 853–1619 10087
2
Philips Semiconductors Product specification
Octal transceiver with parity generator/checker
(3-State)
LOGIC SYMBOL
23456789
A0 A1 A2 A3 A4 A5 A6 A7
OEB
14
OEA
1
11
CLEAR
CP13
B0 B1 B2 B3 B4 B5 B6 B7
23 22 21 20 19 18 17 16
PARITY
ERROR
15
10
SA00213
74ABT833
FUNCTION TABLE
INPUTS OUTPUTS
MODE OEB OEA
A data to B bus and generate odd parity
output
B data to A bus and check for parity error
A bus and B bus disabled
2
A data to B bus and generate inverted
parity output
An
Σ of Highs
L H
1
H L (output) X Bn (input) (input)
Odd
Even
H H X X Z Z Z
L L
Odd
Even
Bn + Parity
Σ of Highs
An Bn PARITY
(output) (input) An
(output) (input) An
NOTES:
1. Error checking is detailed in the Error Flag Function T able below.
2. When clocked, the error output is Low if the sum of A inputs is even or High if the sum of A inputs is odd.
ERROR FLAG FUNCTION TABLE
INPUTS Internal node Output
Bn + Parity
Σ of Highs
Odd
Even
X
Point ”P”
H
L
X
Sample
MODE CLEAR CP
H
H
H
↑
↑
X
Hold H ↑ X X X NC
Clear L X X X X H
H = High voltage level steady state
L = Low voltage level steady state
X = Don’t care
NC = No change
Z = High impedance ”off” state
↑ = Low-to-High clock transition
= Not a Low-to-High clock transition
↑
Pre–state
ERROR
H
X
L
n–1
ERROR
OUTPUT
L
H
H
L
H
L
L
1993 Jun 21
3
Philips Semiconductors Product specification
Octal transceiver with parity generator/checker
(3-State)
LOGIC DIAGRAM
8 8
A0 – A7
8
OEB
OEA
88
MUX
B
}
A
}
Sel A/B
74ABT833
B0 – B7
PARITY
9–bit
Odd
Parity
9
Tree
”P”
ERROR
SA00214
CP
CLEAR
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
I
OUT
T
stg
DC supply voltage –0.5 to +7.0 V
DC input diode current VI < 0 –18 mA
DC input voltage
DC output diode current VO < 0 –50 mA
DC output voltage
DC output current output in Low state 128 mA
Storage temperature range –65 to 150 °C
PARAMETER CONDITIONS RATING UNIT
3
3
D
R
1, 2
–1.2 to +7.0 V
output in Off or High state –0.5 to +5.5 V
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1993 Jun 21
4
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