Philips 74ABT74N, 74ABT74DB, 74ABT74D Datasheet

Philips Semiconductors	Product specification
Dual D-type flip-flop	74ABT74

QUICK REFERENCE DATA

CONDITIONS

SYMBOL

PARAMETER

Tamb = 25°C;

TYPICAL

UNIT

GND = 0V

Propagation

tPLH

delay

3.0

ns

tPHL

CPn to

CL = 50pF;

2.5

Qn, Qn

VCC = 5V

tOSLH

Output to

0.5

ns

tOSHL

Output skew

CIN

Input

VI = 0V or VCC

3

pF

capacitance

ICC

Total supply

Outputs disabled;

50

μA

current

VCC = 5.5V

PIN CONFIGURATION

RD1

1

14

VCC

D0

2

13

RD1

CP0

D1

3

12

CP1

SD1

4

11

Q0

5

10

SD1

Q1

Q0

6

9

GND

7

8

Q1

SF00045

PIN DESCRIPTION

PIN NUMBER

SYMBOL

NAME AND FUNCTION

1, 2, 3, 4, 10,

RDn, Dn,

Data inputs

11, 12, 13

CPn, SDn

5, 6, 8, 9

Qn,

Data outputs

Qn

7

GND

Ground (0V)

14

VCC

Positive supply voltage

LOGIC SYMBOL

2 12

D0 D1

3CP0

4 SD0

1 RD0

11 CP1

10 SD1

13 RD1

Q0 Q0 Q1 Q1

VCC = Pin 14

GND = Pin 7

5 6 9 8

SA00359

DESCRIPTION

The 74ABT74 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock input. When set and reset are inactive (high), data at the D input is transferred to the Q and Q outputs on the low-to-high transition of the clock. Data must be stable just one setup time prior to the low-to-high transition of the clock for predictable operation. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. Following the hold time interval, data at the D input may be changed without affecting the levels of the output.

LOGIC SYMBOL (IEEE/IEC)

	4				S	&	5
3
						C1
2					1D		6
1
					R
10
					S		9
11
						C2
12					2D		8
13
					R

SF00047

LOGIC DIAGRAM

SD	4, 10
RD	1, 13	5, 9
		Q
	3, 11	6, 8
CP		Q
D	2, 12
VCC = Pin 14
GND = Pin 7
		SF00048

ORDERING INFORMATION

PACKAGES	TEMPERATURE RANGE	OUTSIDE NORTH AMERICA	NORTH AMERICA	DWG NUMBER
14-Pin Plastic DIP	±40°C to +85°C	74ABT74 N	74ABT74 N	SOT27-1
14-Pin plastic SO	±40°C to +85°C	74ABT74 D	74ABT74 D	SOT108-1
14-Pin Plastic SSOP Type II	±40°C to +85°C	74ABT74 DB	74ABT74 DB	SOT337-1
14-Pin Plastic TSSOP Type I	±40°C to +85°C	74ABT74 PW	74ABT74PW DH	SOT402-1

1995 Sep 22

1

853-1813 15793

Philips Semiconductors	Product specification
Dual D-type flip-flop	74ABT74

FUNCTION TABLE

INPUTS

OUTPUTS

OPERATING

SD

RD

CP

D

Q

Q

MODE

L

H

X

X

H

L

Asynchronous set

H

L

X

X

L

H

Asynchronous

reset

L

L

X

X

H

H

Undetermined*

H

H

↑

h

H

L

Load ª1º

H

H

↑

l

L

H

Load ª0º

H

H

↑

X

NC

NC

Hold

NOTES:

H	=	High voltage level
h	=	High voltage level one setup time prior to low-to-high
		clock transition
L	=	Low voltage level
l	=	Low voltage level one setup time prior to low-to-high
		clock transition
NC=		No change from the previous setup
X	=	Don't care

↑= Low-to-high clock transition

↑= Not low-to-high clock transition

*= This setup is unstable and will change when either set or reset return to the high level.

ABSOLUTE MAXIMUM RATINGS1, 2

SYMBOL	PARAMETER	CONDITIONS	RATING	UNIT
VCC	DC supply voltage		±0.5 to +7.0	V
IIK	DC input diode current	VI < 0	±18	mA
VI	DC input voltage3		±1.2 to +7.0	V
IOK	DC output diode current	VO < 0	±50	mA
V	DC output voltage3	output in Off or High state	±0.5 to +5.5	V
OUT
IOUT	DC output current	output in Low state	40	mA
Tstg	Storage temperature range		±65 to 150	°C

NOTES:

1.Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

2.The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

RECOMMENDED OPERATING CONDITIONS

SYMBOL	PARAMETER		LIMITS		UNIT
		MIN		MAX
VCC	DC supply voltage	4.5		5.5	V
VI	Input voltage	0		VCC	V
VIH	High-level input voltage	2.0			V
VIL	Low-level input voltage			0.8	V
IOH	High-level output current			±15	mA
IOL	Low-level output current			20	mA
Dt/Dv	Input transition rise or fall rate	0		10	ns/V
Tamb	Operating free-air temperature range	±40		+85	°C

1995 Sep 22

2