Philips 74ABT657PW, 74ABT657N, 74ABT657DB, 74ABT657D Datasheet

INTEGRATED CIRCUITS

74ABT657

Octal transceiver with parity generator/checker (3-State)

Product specification

1995 Dec 11

IC23 Data Handbook

m n r

Philips Semiconductors	Product specification

Octal transceiver with parity generator/checker

74ABT657

(3-State)

FEATURES

•Combinational functions in one package

•Low static and dynamic power dissipation with high speed and high output drive

•Output capability: +64mA/±32mA

•Power-up 3-State

•Latch-up protection exceeds 500mA per Jedec Std 17

•ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model

DESCRIPTION

The 74ABT657 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.

The 74ABT657 is an octal transceiver featuring non-inverting buffers with 3-State outputs and an 8-bit parity generator/checker, and is intended for bus-oriented applications. The buffers have a guaranteed current sinking capability of 64mA. The

Transmit/Receive (T/R) input determines the direction of the data flow through the bidirectional transceivers. Transmit (active-High) enables data from A ports to B ports; Receive (active-Low) enables data from B ports to A ports.

The Output Enable (OE) input disables both the A and B ports by

placing them in a high impedance condition when the OE input is High. The parity select (ODD/EVEN) input gives the user the option of odd or even parity systems. The parity (PARITY) pin is an output from the generator/checker when transmitting from the port A to B (T/R = High) and an input when receiving from port B to A port (T/R = Low). When transmitting (T/R = High) the parity select

(ODD/EVEN) input is set, then the A port data is polled to determine the number of High bits. The parity (PARITY) output then goes to the logic state determined by the parity select (ODD/EVEN) setting and by the number of High bits on port A. For example, if the parity select (ODD/EVEN) is set Low (even parity), and the number of High bits on port A is odd, then the parity (PARITY) output will be

High, transmitting even parity. If the number of High bits on port A is even, then the parity (PARITY) output will be Low, keeping even parity. When in receive mode (T/R = Low) the B port is polled to determine the number of High bits. If parity select (ODD/EVEN) is Low (even parity) and the number of Highs on port B is:

(1)odd and the parity (PARITY) input is High, then ERROR will be High, signifying no error.

(2)even and the parity (PARITY) input is High, then ERROR will be asserted Low, indicating an error.

QUICK REFERENCE DATA

	SYMBOL	PARAMETER	CONDITIONS	TYPICAL	UNIT
			Tamb = 25°C; GND = 0V
	tPLH	Propagation delay	CL = 50pF; VCC = 5V	3.3	ns
	tPHL	An to Bn or Bn to An
	CIN	Input capacitance	VI = 0V or VCC	4	pF
	CI/O	I/O capacitance	Outputs disabled;	7	pF
			VO = 0V or VCC
	ICCZ	Total supply current	Outputs disabled; VCC =5.5V	500	nA

ORDERING INFORMATION

PACKAGES	TEMPERATURE RANGE	OUTSIDE NORTH AMERICA	NORTH AMERICA	DWG NUMBER
24-Pin Plastic DIP	±40°C to +85°C	74ABT657 N	74ABT657 N	SOT222-1
24-Pin plastic SO	±40°C to +85°C	74ABT657 D	74ABT657 D	SOT137-1
24-Pin Plastic SSOP Type II	±40°C to +85°C	74ABT657 DB	74ABT657 DB	SOT340-1
24-Pin Plastic TSSOP Type I	±40°C to +85°C	74ABT657 PW	74ABT657PW DH	SOT355-1

PIN CONFIGURATION																			PIN DESCRIPTION
																			SYMBOL	PIN NUMBER								NAME AND FUNCTION
		T/R						1					24		OE				13		PARITY							Parity output
		A0						2					23	B0
																			11	ODD/EVEN								Parity select input
		A1						3					22	B1
																			12	ERROR								Error output
		A2						4					21	B2
																			1		T/R							Transmit/receive input
		A3						5					20	B3					2, 3, 4, 5,		A0 - A7							A port 3-State outputs
																			6, 8, 9, 10
		A4						6					19	GND
										TOP VIEW
																			23, 22, 21, 20,
		VCC						7					18	GND							B0 - B7							B port 3-State outputs
																			17, 16, 15, 14
		A5						8					17	B4
																			24									Output enable input (active-Low)
																						OE
		A6						9					16	B5
																			18, 19		GND							Ground (0V)
		A7						10					15	B6
																			7		VCC							Positive supply voltage
ODD/EVEN								11					14	B7
														PARITY
	ERROR						12						13
																	SA00181

1995 Dec 11

2

853±1615 16106

Philips Semiconductors	Product specification

Octal transceiver with parity generator/checker

74ABT657

(3-State)

LOGIC SYMBOL

LOGIC SYMBOL (IEEE/IEC)

																									1
		2		3			4		5		6		8		9			10							24
																									11
		A0		A1			A2		A3		A4		A5		A6			A7
1
		T/R														PARITY					13
24		OE																					12
11																ERROR
		ODD/EVEN
		B0		B1			B2		B3		B4		B5		B6			B7
																									2
		23		22			21		20		17		16		15			14
																									3
																									4
																							SA00182		5
																									6
																									8
																									9
																									10

	0		0	0 BUS B TO A
				1 BUS A TO B
	1 M
			2 2 HIGH Z
	G3[EVEN]
	G4[ODD]
		2K					=
						1,3[EVEN]
						1,4[ODD]
						0,3[EVEN
						0,4]ODD
	0						2

13

12

23

22

21

20

17

16

15

14

SA00194

FUNCTION TABLE

INPUTS

INPUT/

OUTPUTS

NUMBER OF HIGH INPUTS

OUTPUT

OE

T/R

ODD/EVEN

PARITY

ERROR

OUTPUTS MODE

L

H

H

H

Z

Transmit

L

H

L

L

Z

Transmit

0, 2, 4, 6, 8

L

L

H

H

H

Receive

L

L

H

L

L

Receive

L

L

L

H

L

Receive

L

L

L

L

H

Receive

L

H

H

L

Z

Transmit

L

H

L

H

Z

Transmit

1, 3, 5, 7

L

L

H

H

L

Receive

L

L

H

L

H

Receive

L

L

L

H

H

Receive

L

L

L

L

L

Receive

Don't care

H

X

X

Z

Z

3-State

H

=

High voltage level

L

=

Low voltage level

X

=

Don't care

Z

=

High impedance ºoffº state

1995 Dec 11

3

Philips Semiconductors	Product specification

Octal transceiver with parity generator/checker

74ABT657

(3-State)

LOGIC DIAGRAM

T/R	1
OE	24
A0	2	23	B0
A1	3	22	B1
A2	4	21	B2
A3	5	20	B3
A4	6	17	B4
A5	8	16	B5
A6	9	15	B6
A7	10	14	B7
ODD/EVEN	11		13	PARITY
			12	ERROR
				SA00215
1995 Dec 11		4