Philips 74ABT652AN, 74ABT652ADB, 74ABT652AD Datasheet

Philips Semiconductors	Product specification
Octal transceiver/register, non-inverting (3-State)	74ABT652A

FEATURES

•Independent registers for A and B buses

•Multiplexed real-time and stored data

•3-State outputs

•Live insertion/extraction permitted

•Power-up 3-State

•Power-up reset

•Output capability: +64mA/±32mA

•Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17

•ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model

DESCRIPTION

The 74ABT652A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.

The 74ABT652A transceiver/register consists of bus transceiver circuits with 3-State outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes High. Output Enable (OEAB, OEBA) and Select (SAB, SBA) pins are provided for bus management.

QUICK REFERENCE DATA

	SYMBOL	PARAMETER	CONDITIONS	TYPICAL	UNIT
			Tamb = 25°C; GND = 0V
	tPLH	Propagation delay	CL = 50pF; VCC = 5V	3.7	ns
	tPHL	CPBA to An or CPAB to Bn		4.3
	CIN	Input capacitance	VI = 0V or VCC	4	pF
	CI/O	I/O capacitance	Outputs disabled;	7	pF
			VO = 0V or VCC
	ICCZ	Total supply current	Outputs disabled; VCC =5.5V	110	μA

ORDERING INFORMATION

PACKAGES	TEMPERATURE RANGE	ORDER CODE	DRAWING NUMBER
24-pin plastic DIP	±40°C to +85°C	74ABT652AN	SOT222-1
24-pin plastic SOL	±40°C to +85°C	74ABT652AD	SOT137-1
24-pin plastic SSOP Type II	±40°C to +85°C	74ABT652ADB	SOT340-1
24-pin plastic TSSOP Type I	±40°C to +85°C	74ABT652APW	SOT355-1

PIN CONFIGURATION

PIN DESCRIPTION

PIN NUMBER

SYMBOL

FUNCTION

CPAB

VCC

CPAB /

1

24

1, 23

A to B clock input / B to A clock input

CPBA

SAB

2

23

CPBA

2, 22

SAB /

A to B select input / B to A select

OEAB

SBA

3

22

SBA

input

A0

4

21

OEBA

OEAB /

A to B Output Enable input /

A1

B0

3, 21

B to A Output Enable input

5

20

OEBA

A2

B1

(active±Low)

6

19

4, 5, 6, 7,

A0 ± A7

Data inputs/outputs (A side)

A3

B2

7

18

8, 9, 10, 11

A4

B3

8

17

20, 19, 18, 17,

B0 ± B7

Data inputs/outputs (B side)

A5

B4

16, 15, 14, 13

9

16

A6

B5

12

GND

Ground (0V)

10

15

A7

B6

24

VCC

Positive supply voltage

11

14

GND

B7

12

13

SA00094

1995 Apr 19

1

853-1614 15144

Philips Semiconductors	Product specification
Octal transceiver/register, non-inverting (3-State)	74ABT652A

LOGIC SYMBOL

LOGIC SYMBOL (IEEE/IEC)

	4	5	6	7	8	9	10	11	21	EN1 [BA]
									3	EN2 [AB]
	A0	A1	A2	A3	A4	A5	A6	A7	23	C4
									22	G5
									1	C6
23	CPBA								2	G7
22	SBA						OEAB		3
2	SAB						OEBA		21	1		5	4D	20
1	CPAB								4
										1
												5	1
	B0	B1	B2	B3	B4	B5	B6	B7		6D	7	1
													2
										1	7
	20	19	18	17	16	15	14	13	5					19
									6					18
									SA00095
									7					17
									8					16
									9					15
									10					14
									11					13

SA00096

FUNCTION TABLE

INPUTS

DATA I/O

OPERATING MODE

OEAB

OEBA

CPAB

CPBA

SAB

SBA

An

Bn

L

H

H or L

H or L

X

X

Input

Input

Isolation

L

H

↑

↑

X

X

Store A and B data

X

H

↑

H or L

X

X

Input

Unspecified

Store A, Hold B

H

H

↑

↑

**

X

output*

Store A in both registers

L

X

H or L

↑

X

X

Unspecified

Input

Hold A, Store B

L

L

↑

↑

X

**

output*

Store B in both registers

L

L

X

X

X

L

Output

Input

Real time B data to A bus

L

L

X

H or L

X

H

Stored B data to A bus

H

H

X

X

L

X

Input

Output

Real time A data to B bus

H

H

H or L

X

H

X

Store A data to B bus

H

L

H or L

H or L

H

H

Output

Output

Stored A data to B bus

Stored B data to A bus

H

=

High voltage level

L

=

Low voltage level

X

=

Don't care

↑

=

Low-to-High clock transition

*The data output function may be enabled or disabled by various signals at the OEBA and OEAB inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every Low-to-High transition of the clock.

**If both Select controls (SAB and SBA) are Low, then clocks can occur simultaneously. If either Select control is High, the clocks must be staggered in order to load both registers.

1995 Apr 19

2

Philips Semiconductors	Product specification
Octal transceiver/register, non-inverting (3-State)	74ABT652A

The following examples demonstrate the four fundamental		The select pins determine whether data is stored or transferred
bus-management functions that can be performed with the		through the device in real time.
74ABT652A.		The output enable pins determine the direction of the data flow.
REAL TIME BUS TRANSFER	REAL TIME BUS TRANSFER	STORAGE FROM	TRANSFER STORED DATA
BUS B TO BUS A	BUS A TO BUS B	A, B, OR A AND B	TO A OR B

A

B

A

B

A

B

A

B

}

}

}

}

OEAB

CPAB CPBA SAB

SBA

OEAB

CPAB CPBA SAB

SBA

OEAB

CPAB CPBA SAB

SBA

OEAB

CPAB CPBA SAB

SBA

OEBA

OEBA

OEBA

OEBA

L

L

X

X

X

L

H

H

X

X

L

X

X

H

↑

X

X

X

H

L H | L H | L H

H

L

X

X

↑

X

X

L

H

↑

↑

X

X

SA00097

1995 Apr 19

3