INTEGRATED CIRCUITS
74ABT646A
Octal bus transceiver/register (3-State)
Product specification |
1998 Feb 17 |
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Supersedes data of 1995 Sep 06 |
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IC23 Data Handbook |
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m n r
Philips Semiconductors |
Product specification |
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Octal bus transceiver/register (3-State) |
74ABT646A |
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FEATURES
•Combines 74ABT245 and 74ABT374 type functions in one device
•Independent registers for A and B buses
•Live insertion/extraction permitted
•Power-up 3-State
•Power-up reset
•Multiplexed real-time and stored data
•Output capability: +64mA/±32mA
•Latch-up protection exceeds 500mA per Jedec Std 17
•ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model
DESCRIPTION
The 74ABT646A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.
The 74ABT646A transceiver/register consists of bus transceiver circuits with 3-State outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes High. Output Enable (OE) and DIR pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or B register or both.
The Select (SAB, SBA) pins determine whether data is stored or transferred through the device in real-time. The DIR determines which bus will receive data when the OE is active (Low). In the isolation mode (OE = High), data from Bus A may be stored in the B register and/or data from Bus B may be stored in the A register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. The examples on the next page demonstrate the four fundamental bus management functions that can be performed with the 74ABT646A.
QUICK REFERENCE DATA
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PARAMETER |
CONDITIONS |
TYPICAL |
UNIT |
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Tamb = 25°C; GND = 0V |
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tPLH |
Propagation delay |
CL = 50pF; VCC = 5V |
3.2 |
ns |
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tPHL |
An to Bn or Bn to An |
3.7 |
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CIN |
Input capacitance |
VI = 0V or VCC |
4 |
pF |
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CP, S, |
OE, |
DIR |
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CI/O |
I/O capacitance |
Outputs disabled; |
7 |
pF |
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VO = 0V or VCC |
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ICCZ |
Total supply current |
Outputs disabled; VCC =5.5V |
110 |
μA |
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ORDERING INFORMATION
PACKAGES |
TEMPERATURE RANGE |
OUTSIDE NORTH AMERICA |
NORTH AMERICA |
DWG NUMBER |
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24-Pin Plastic DIP |
±40°C to +85°C |
74ABT646A N |
74ABT646A N |
SOT222-1 |
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24-Pin plastic SO |
±40°C to +85°C |
74ABT646A D |
74ABT646A D |
SOT137-1 |
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24-Pin Plastic SSOP Type II |
±40°C to +85°C |
74ABT646A DB |
74ABT646A DB |
SOT340-1 |
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24-Pin Plastic TSSOP Type I |
±40°C to +85°C |
74ABT646A PW |
7ABT646APW DH |
SOT355-1 |
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PIN CONFIGURATION
CPAB |
1 |
24 |
VCC |
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SAB |
2 |
23 |
CPBA |
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DIR |
3 |
22 |
SBA |
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A0 |
4 |
21 |
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OE |
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A1 |
5 |
20 |
B0 |
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A2 |
6 |
19 |
B1 |
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A3 |
7 |
18 |
B2 |
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A4 |
8 |
17 |
B3 |
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A5 |
9 |
16 |
B4 |
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A6 |
10 |
15 |
B5 |
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A7 |
11 |
14 |
B6 |
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GND |
12 |
13 |
B7 |
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PIN DESCRIPTION
PIN NUMBER |
SYMBOL |
FUNCTION |
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1, 23 |
CPAB / |
A to B clock input / B to A clock |
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CPBA |
input |
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2, 22 |
SAB / SBA |
A to B select input / B to A |
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select input |
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3 |
DIR |
Direction control input |
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4, 5, 6, 7, |
A0 ± A7 |
Data inputs/outputs (A side) |
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8, 9, 10, 11 |
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20, 19, 18, 17, |
B0 ± B7 |
Data inputs/outputs (B side) |
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16, 15, 14, 13 |
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Output enable input |
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21 |
OE |
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(active-Low) |
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12 |
GND |
Ground (0V) |
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24 |
VCC |
Positive supply voltage |
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SA00082
1998 Feb 17 |
2 |
853-1553 18978 |
Philips Semiconductors |
Product specification |
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Octal bus transceiver/register (3-State) |
74ABT646A |
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LOGIC SYMBOL |
LOGIC SYMBOL (IEEE/IEC) |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
A0 A1 A2 A3 A4 A5 A6 A7
1CPAB
2SAB
3DIR
23 |
CPBA |
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22 |
SBA |
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21 |
OE |
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B0 |
B1 |
B2 |
B3 |
B4 |
B5 |
B6 |
B7 |
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20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
SA00083
21G3
3EN1 [BA]
3 |
3EN2 [AB] |
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22 |
G6 |
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2 |
G7 |
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23 |
C4 |
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1 |
C5 |
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4 |
1 |
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6 |
4D |
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1 |
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6 |
1 |
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5D |
7 |
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2 |
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1 |
7 |
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5 |
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19 |
6 |
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18 |
7 |
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17 |
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8 |
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16 |
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9 |
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15 |
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10 |
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14 |
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11 |
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13 |
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SA00084 |
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REAL TIME BUS TRANSFER |
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REAL TIME BUS TRANSFER |
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STORAGE FROM |
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TRANSFER STORED DATA |
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BUS B TO BUS A |
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BUS A TO BUS B |
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A, B, OR A AND B |
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TO A OR B |
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A |
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B |
A |
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B |
A |
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B |
A |
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B |
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} |
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} |
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} |
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} |
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DIR CPAB CPBA SAB |
SBA |
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DIR CPAB CPBA SAB |
SBA |
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DIR CPAB CPBA SAB |
SBA |
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DIR CPAB CPBA SAB |
SBA |
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OE |
OE |
OE |
OE |
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L |
L |
X |
X |
X |
L |
L |
H |
X |
X |
L |
X |
L |
H |
↑ |
X |
X |
X |
L |
L |
X H or L X |
H |
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L |
L |
X |
↑ |
X |
X |
L |
H H or L X |
H |
X |
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H |
X |
↑ |
↑ |
X |
X |
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SA00085
1998 Feb 17 |
3 |
Philips Semiconductors |
Product specification |
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Octal bus transceiver/register (3-State) |
74ABT646A |
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FUNCTION TABLE
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INPUTS |
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DATA I/O |
OPERATING MODE |
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DIR |
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CPAB |
CPBA |
SAB |
SBA |
An |
Bn |
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OE |
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X |
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X |
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↑ |
X |
X |
X |
Input |
Unspecified |
Store A, B unspecified |
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output* |
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X |
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X |
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X |
↑ |
X |
X |
Unspecified |
Input |
Store B, A unspecified |
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output* |
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H |
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X |
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↑ |
↑ |
X |
X |
Input |
Input |
Store A and B data |
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H |
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X |
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H or L |
H or L |
X |
X |
Isolation, hold storage |
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L |
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L |
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X |
X |
X |
L |
Output |
Input |
Real time B data to A bus |
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L |
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L |
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X |
H or L |
X |
H |
Stored B data to A bus |
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L |
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H |
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X |
X |
L |
X |
Input |
Output |
Real time A data to B bus |
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L |
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H |
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H or L |
X |
H |
X |
Stored A data to B bus |
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H |
= |
High voltage level |
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L |
= |
Low voltage level |
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X |
= |
Don't care |
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↑ |
= |
Low-to-High clock transition |
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*The data output function may be enabled or disabled by various signals at the OE input. Data input functions are always enabled, i.e., data at the bus pins will be stored on every Low-to-High transition of the clock.
LOGIC DIAGRAM
21 |
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OE |
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3 |
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DIR |
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23 |
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CPBA |
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22 |
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SBA |
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1 |
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CPAB |
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2 |
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SAB |
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1of 8 Channels |
1D |
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C1 |
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Q |
4 |
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20 |
A0 |
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B0 |
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1D |
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C1 |
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Q |
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5 |
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19 |
A1 |
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B1 |
6 |
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18 |
A2 |
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B2 |
7 |
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17 |
A3 |
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B3 |
8 |
DETAIL A X 7 |
16 |
A4 |
B4 |
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9 |
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15 |
A5 |
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B5 |
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14 |
A6 |
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B6 |
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13 |
A7 |
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B7 |
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SA00086 |
1998 Feb 17 |
4 |
|
Philips Semiconductors |
Product specification |
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Octal bus transceiver/register (3-State) |
74ABT646A |
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ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL |
PARAMETER |
CONDITIONS |
RATING |
UNIT |
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VCC |
DC supply voltage |
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±0.5 to +7.0 |
V |
IIK |
DC input diode current |
VI < 0 |
±18 |
mA |
VI |
DC input voltage3 |
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±1.2 to +7.0 |
V |
IOK |
DC output diode current |
VO < 0 |
±50 |
mA |
V |
DC output voltage3 |
output in Off or High state |
±0.5 to +5.5 |
V |
OUT |
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IOUT |
DC output current |
output in Low state |
128 |
mA |
Tstg |
Storage temperature range |
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±65 to 150 |
°C |
NOTES:
1.Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2.The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL |
PARAMETER |
|
LIMITS |
UNIT |
|
|
|
|
|||
Min |
|
Max |
|||
|
|
|
|
||
|
|
|
|
|
|
VCC |
DC supply voltage |
4.5 |
|
5.5 |
V |
VI |
Input voltage |
0 |
|
VCC |
V |
VIH |
High-level input voltage |
2.0 |
|
|
V |
VIL |
Low-level Input voltage |
|
|
0.8 |
V |
IOH |
High-level output current |
|
|
±32 |
mA |
IOL |
Low-level output current |
|
|
64 |
mA |
t/ v |
Input transition rise or fall rate |
0 |
|
10 |
ns/V |
|
|
|
|
|
|
Tamb |
Operating free-air temperature range |
±40 |
|
+85 |
°C |
1998 Feb 17 |
5 |
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