Philips 74ABTH16652DL, 74ABT16652DL, 74ABT16652DGG Datasheet
74ABT16652
74ABTH16652
16-bit transceiver/register, non-inverting
(3-State)
Product specification
Supersedes data of 1995 Aug 17
IC23 Data Handbook
1998 Feb 27
INTEGRATED CIRCUITS
Philips Semiconductors Product specification
74ABT16652
74ABTH16652
16-bit transceiver/register, non-inverting (3-State)
2
1998 Feb 27 853-1790 19026
FEA TURES
•Independent registers for A and B buses
•Multiple V
CC
and GND pins minimize switching noise
•Power-up 3-State
•74ABTH16652 incorporates bus-hold data inputs which eliminate
the need for external pull-up resistors to hold unused inputs
•Power-up reset
•Live insertion/extraction permitted
•Multiplexed real-time and stored data
•Output capability: +64mA/–32mA
•Latch-up protection exceeds 500mA per JEDEC Std 17
•ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
DESCRIPTION
The 74ABT16652 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT16652 transceiver/register consists of two sets of bus
transceiver circuits with 3-State outputs, D-type flip-flops, and
control circuitry arranged for multiplexed transmission of data
directly from the input bus or the internal registers. Data on the A or
B bus will be clocked into the registers as the appropriate clock pin
goes HIGH. Output Enable (nOEAB, (nOEBA
) and Select (nSAB,
nSBA
) pins are provided for bus management.
Two options are available, 74ABT16652 which does not have the
bus-hold feature and 74ABTH16652 which incorporates the
bus-hold feature.
QUICK REFERENCE DA TA
SYMBOL PARAMETER
CONDITIONS
T
amb
= 25°C; GND = 0V
TYPICAL UNIT
t
PLH
t
PHL
Propagation delay nAx to nBx CL = 50pF; VCC = 5V
2.3
1.8
ns
C
IN
Input capacitance VI = 0V or V
CC
4 pF
C
I/O
I/O capacitance VO = 0V or VCC; 3-State 7 pF
I
CCZ
pp
Outputs disabled; VCC =5.5V 500 µA
I
CCL
Quiescent supply current
Outputs low; VCC = 5.5V 8 mA
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
56-Pin Plastic SSOP Type III –40°C to +85°C 74ABT16652 DL BT16652 DL SOT371-1
56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABT16652 DGG BT16652 DGG SOT364-1
56-Pin Plastic SSOP Type III –40°C to +85°C 74ABTH16652 DL BH16652 DL SOT371-1
56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABTH16652 DGG BH16652 DGG SOT364-1
LOGIC SYMBOL
354255
156
26 3127 30
28 29
5
6
10
12
13
14
8
9
52
51
47
45
44
43
49
48
15
16
20
21
23
24
17
19
42
41
37
36
34
33
40
38
SH00047
1A0
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1B0
1B1
1B2
1B3
1B4
1B5
1B6
1B7
2A0
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2B0
2B1
2B2
2B3
2B4
2B5
2B6
2B7
1CPAB
1SAB
1SBA
1CPBA
1OEAB
1OEBA
2OEAB
2OEBA
2CPAB
2SAB
2SBA
2CPBA
Philips Semiconductors Product specification
74ABT16652
74ABTH16652
16-bit transceiver/register, non-inverting (3-State)
1998 Feb 27
3
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
27
28
30
29
1OEAB
1CPAB
1SAB
GND
1A0
1A1
1A2
1A3
1A4
GND
1A5
1A6
1A7
2A0
2A2
GND
2A3
V
CC
2A1
2A4
2A5
2A6
2A7
2SAB
V
CC
GND
2CPAB
20EAB
1OE
BA
1CPBA
1SBA
GND
1B0
1B1
1B2
1B3
1B4
GND
1B5
1B6
1B7
2B0
2B2
GND
2B3
V
CC
2B1
2B4
2B5
2B6
2B7
2SBA
V
CC
GND
2CPBA
2OE
BA
SH00046
LOGIC SYMBOL (IEEE/IEC)
EN1 [BA]
SH00045
1
28
30
29
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
5D
2
56
55
27
C3
G4
EN7 [BA]
26
EN2 [AB]
C5
G6
EN8 [AB]
C9
G10
C11
G12
1
∇1
6
16
43D
4
1
1
2∇
1
∇7
11D 12
112
1
8∇
10 9D
10 1
1OEBA
1OEAB
1CPBA
1SBA
1CPAB
1SAB
2OEBA
2OEAB
2CPBA
2SBA
2CPAB
2SAB
1AO
1A1
1A2
1A3
1A4
1A5
1A6
1A7
2A0
2A1
2A2
2A3
2A4
2A5
2A6
1B0
1B1
1B2
1B3
1B4
1B5
1B6
1B7
2B0
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2A7
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
2, 55, 27, 30 1CPAB, 1CPBA, 2CPAB, 2CPBA Clock input A to B / Clock input B to A
3, 54, 26, 31 1SAB, 1SBA, 2SAB, 2SBA Select input A to B / Select input B to A
5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24
1A0 – 1A7,
2A0 – 2A7
Data inputs/outputs (A side)
52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33
1B0 – 1B7,
2B0 – 2B7
Data inputs/outputs (B side)
1, 56, 28, 29
1OEAB, 1OEBA,
2OEAB, 2OEBA
Output enable inputs
4, 11, 18, 25, 32, 39, 46, 53 GND Ground (0V)
7, 22, 35, 50 V
CC
Positive supply voltage
Philips Semiconductors Product specification
74ABT16652
74ABTH16652
16-bit transceiver/register, non-inverting (3-State)
1998 Feb 27
4
LOGIC DIAGRAM
1D
C1
Q
DETAIL A X 7
nB0
1D
C1
Q
nA0
1of 8 Channels
nA7
nA6
nA5
nA4
nA3
nA2
nA1 nB1
nB2
nB3
nB4
nB5
nB6
nB7
nOE
BA
nOEAB
nCPBA
nSBA
nCPAB
nSAB
SH00065
FUNCTION TABLE
INPUTS DATA I/O OPERATING MODE
nOEAB nOEBA nCPAB nCPBA nSAB
nSB
A
nAx nBx
L
L
H
H
H or L↑H or L
↑
X
X
X
X
Input Input
Isolation
Store A and B data
X
H
H
H
↑
↑
H or L
↑
X
**
X
X
Input
Unspecified
output*
Store A, Hold B
Store A in both registers
L
L
X
L
H or L
↑
↑
↑
X
X
X**Unspecified
output*
Input
Hold A, Store B
Store B in both registers
L
L
L
L
X
X
X
H or L
X
X
L
H
Output Input
Real time B data to A bus
Stored B data to A bus
H
H
H
H
X
H or L
X
X
L
H
X
X
Input Output
Real time A data to B bus
Store A data to B bus
H L H or L H or L H H Output Output
Stored A data to B bus
Stored B data to A bus
H = High voltage level
L = Low voltage level
X = Don’t care
↑ = Low-to-High clock transition
* The data output function may be enabled or disabled by various signals at the nOEBA
and nOEAB inputs. Data input functions are
always enabled, i.e., data at the bus pins will be stored on every Low-to-High transition of the clock.
** If both Select controls (nSAB and nSBA) are Low, then clocks can occur simultaneously. If either Select control is High, the clocks must
be staggered in order to load both registers.
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