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74ABT161543 |
INTEGRATED CIRCUITS |
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74ABT161543
74ABTH161543
16-bit latched transceiver with
dual enable and master reset (3-State)
Product specification |
1998 Feb 27 |
Supersedes data of 1995 Sep 18
IC23 Data Handbook
m n r
Philips Semiconductors |
Product specification |
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16-bit latched transceiver with dual enable |
74ABT161543 |
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and master reset (3-State) |
74ABTH161543 |
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FEATURES
•Two 8-bit octal transceivers with D-type latch
•Live insertion/extraction permitted
•Power-up 3-State
•Power-up reset
•Multiple VCC and GND pins minimize switching noise
•Back-to-back registers for storage
•Separate controls for data flow in each direction
•74ABTH161543 incorporates Bus hold data inputs which eliminate the need for external pull-up resistors to hold unused inputs
•Output capability: +64mA/±32mA
•Latch-up protection exceeds 500mA per Jedec Std 17
•ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model
•Same function as ABT16543 except for additional Master Reset control pins
QUICK REFERENCE DATA
DESCRIPTION
The 74ABT161543 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.
The 74ABT161543 16-bit registered transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable (nLEAB, nLEBA) and Output
Enable (nOEAB, nOEBA) inputs are provided for each register to permit independent control of data transfer in either direction. Master reset (MR) clears all registers simultaneously and sets them Low. The outputs are guaranteed to sink 64mA.
Two options are available, 74ABT161543 which does not have the
Bus hold feature and 74ABTH161543 which inorporates the Bus hold feature.
SYMBOL |
PARAMETER |
CONDITIONS |
TYPICAL |
UNIT |
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Tamb = 25°C; GND = 0V |
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tPLH |
Propagation delay |
CL = 50pF; VCC = 5V |
2.5 |
ns |
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tPHL |
nAx to nBx |
2.2 |
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CIN |
Input capacitance |
VI = 0V or VCC |
3 |
pF |
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CI/O |
I/O capacitance |
VO = 0V or VCC; 3-State |
7 |
pF |
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ICCZ |
Quiescent supply current |
Outputs disabled; VCC = 5.5V |
500 |
μA |
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ICCL |
Outputs low; VCC = 5.5V |
9 |
mA |
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ORDERING INFORMATION
PACKAGES |
TEMPERATURE RANGE |
ORDER CODE |
DRAWING NUMBER |
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56-pin plastic SSOP Type III |
±40°C to +85°C |
BT161543DL |
SOT371-1 |
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56-pin plastic TSSOP Type II |
±40°C to +85°C |
BT161543DGG |
SOT364-1 |
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ORDERING INFORMATION
PACKAGES |
TEMPERATURE RANGE |
OUTSIDE NORTH AMERICA |
NORTH AMERICA |
DWG NUMBER |
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56-Pin Plastic SSOP Type III |
±40°C to +85°C |
74ABT161543 DL |
BT161543 DL |
SOT371-1 |
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56-Pin Plastic TSSOP Type II |
±40°C to +85°C |
74ABT161543 DGG |
BT161543 DGG |
SOT364-1 |
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56-Pin Plastic SSOP Type III |
±40°C to +85°C |
74ABTH161543 DL |
BH161543 DL |
SOT371-1 |
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56-Pin Plastic TSSOP Type II |
±40°C to +85°C |
74ABTH161543 DGG |
BH161543 DGG |
SOT364-1 |
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PIN DESCRIPTION
PIN NUMBER |
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SYMBOL |
NAME AND FUNCTION |
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5, 6, 8, 9, 10, 12, 13, 14 |
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1A0 ± 1A7, |
Data inputs/outputs |
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15, 16, 17, 19, 20, 21, 23, 24 |
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2A0 ± 2A7 |
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52, 51, 49, 48, 47, 45, 44, 43 |
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1B0 ± 1B7, |
Data inputs/outputs |
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42, 41, 40,38, 37, 36, 34, 33 |
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2B0 ± 2B7 |
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1, 56 |
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1OEAB, |
1OEBA, |
A to B / B to A Output Enable inputs (active-Low) |
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28, 29 |
2OEAB, 2OEBA |
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3, 54 |
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1EAB, |
1EBA, |
A to B / B to A Enable inputs (active-Low) |
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26, 31 |
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2EAB, 2EBA |
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2, 55 |
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1LEAB, |
1LEBA, |
A to B / B to A Latch Enable inputs (active-Low) |
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27, 30 |
2LEAB, 2LEBA |
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4, 25 |
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Master reset |
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MRab, MRba |
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11, 18, 32, 39, 46, 53 |
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GND |
Ground (0V) |
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7, 22, 35, 50 |
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VCC |
Positive supply voltage |
1998 Feb 27 |
2 |
853-1798 19026 |
Philips Semiconductors Product specification
16-bit latched transceiver with dual enable |
74ABT161543 |
|
and master reset (3-State) |
|
74ABTH161543 |
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LOGIC SYMBOL (IEEE/IEC) |
PIN CONFIGURATION |
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MRab 4 1OEAB 1
1EAB 3 1LEAB 2
2OEAB 28 2EAB 26
2LEAB 27 MRba 25
1OEBA 56 1EBA 54
1LEBA 55 2OEBA 29
2EBA 31 2LEBA 30
1A0 5
1A1 6
1A2 8
1A3 9
1A4 10
1A5 12
1A6 13
1A7 14
2A0 15
2A1 16
2A2 17
2A3 19
2A4 20
2A5 21
2A6 23
2A7 24
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1OEAB |
1 |
56 |
1OEBA |
R6/R12 |
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1LEAB |
2 |
55 |
1LEBA |
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2EN4 |
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1EAB |
3 |
54 |
1EBA |
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G2 |
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MRab |
4 |
53 |
GND |
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2C6 |
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1A0 |
5 |
52 |
1B0 |
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8EN10 |
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1A1 |
6 |
51 |
1B1 |
G8 |
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VCC |
7 |
50 |
VCC |
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8C12 |
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1A2 |
8 |
49 |
1B2 |
R5/R11 |
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1A3 |
9 |
48 |
1B3 |
1EN3 |
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1A4 |
10 |
47 |
1B4 |
G1 |
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GND |
11 |
46 |
GND |
1C5 |
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1A5 |
12 |
45 |
1B5 |
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7EN9 |
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1A6 |
13 |
44 |
1B6 |
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G7 |
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1A7 |
14 |
43 |
1B7 |
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7C11 |
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2A0 |
15 |
42 |
2B0 |
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2A1 |
16 |
41 |
2B1 |
3 |
5D |
52 |
1B0 |
2A2 |
17 |
40 |
2B2 |
6D |
4 |
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GND |
18 |
39 |
GND |
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51 |
1B1 |
2A3 |
19 |
38 |
2B3 |
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49 |
1B2 |
2A4 |
20 |
37 |
2B4 |
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48 |
1B3 |
2A5 |
21 |
36 |
2B5 |
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47 |
1B4 |
VCC |
22 |
35 |
VCC |
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45 |
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1B5 |
2A6 |
23 |
34 |
2B6 |
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44 |
1B6 |
2A7 |
24 |
33 |
2B7 |
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43 |
1B7 |
MRba |
25 |
32 |
GND |
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9 |
11D |
42 |
2B0 |
2EAB |
26 |
31 |
2EBA |
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12D |
10 |
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2LEAB |
27 |
30 |
2LEBA |
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41 |
2B1 |
2OEAB |
28 |
29 |
2OEBA |
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40 |
2B2 |
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SH00061 |
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38 |
2B3 |
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37 |
2B4 |
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36 |
2B5 |
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34 |
2B6 |
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33 |
2B7 |
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SH00060 |
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1998 Feb 27 |
3 |
Philips Semiconductors Product specification
16-bit latched transceiver with dual enable |
74ABT161543 |
|
and master reset (3-State) |
|
74ABTH161543 |
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LOGIC SYMBOL |
FUNCTIONAL DESCRIPTION |
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5 |
6 |
8 |
9 |
10 |
12 |
13 |
14 |
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1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7 |
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3 |
1EAB |
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MRab |
4 |
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54 |
1EBA |
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1OEAB |
1 |
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2 |
1LEAB |
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1OEBA |
56 |
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55 |
1LEBA |
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MRba |
25 |
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1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7 |
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52 |
51 |
49 |
48 |
47 |
45 |
44 |
43 |
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15 |
16 |
17 |
19 |
20 |
21 |
23 |
24 |
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2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 |
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26 |
2EAB |
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MRab |
4 |
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31 |
2EBA |
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2OEAB |
28 |
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27 |
2LEAB |
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2OEBA |
29 |
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30 |
2LEBA |
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MRba |
25 |
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2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7 |
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42 |
41 |
40 |
38 |
37 |
36 |
34 |
33 |
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The 74ABT161543 contains two sets of eight D-type latches, with separate control pins for each set. Using data flow from A to B as an example, when the A-to-B Enable (nEAB) input and the A-to-B Latch
Enable (nLEAB) input are Low the A-to-B path is transparent.
A subsequent Low-to-High transition of the nLEAB signal puts the A data into the latches where it is stored and the B outputs no longer change with the A inputs. With EAB and nOEAB both Low, the 3-State B output buffers are active and display the data present at the outputs of the A latches.
Control of data flow from B to A is similar, but using the nEBA,
nLEBA, and nOEBA inputs.
SH00064
FUNCTION TABLE
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INPUTS |
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OUTPUTS |
STATUS |
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nOEXX |
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nMRXX |
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nEXX |
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nLEXX |
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nAx or nBx |
nBx or nAx |
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L |
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L |
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L |
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X |
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X |
L |
Clear |
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H |
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X |
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X |
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X |
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X |
Z |
Disabled |
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X |
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X |
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H |
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X |
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Z |
Disabled |
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L |
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H |
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↑ |
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L |
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h |
Z |
Disabled + Latch |
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H |
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↑ |
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L |
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l |
Z |
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L |
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H |
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L |
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↑ |
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h |
H |
Latch + Display |
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L |
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H |
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↑ |
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l |
L |
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L |
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H |
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L |
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L |
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H |
H |
Transparent |
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L |
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H |
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L |
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L |
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L |
L |
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L |
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H |
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L |
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H |
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X |
NC |
Hold |
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H |
= |
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High voltage level |
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h |
= |
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High voltage level one set-up time prior to the Low-to-High transition of |
nLEXX |
or |
nEXX |
(XX = AB or BA) |
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L |
= |
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Low voltage level |
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or |
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(XX = AB or BA) |
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l |
= |
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Low voltage level one set-up time prior to the Low-to-High transition of |
nLEXX |
nEXX |
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X |
= |
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Don't care |
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↑ |
= |
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Low-to-High transition of |
nLEXX |
or |
nEXX |
(XX = AB or BA) |
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NC= |
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No change |
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Z |
= |
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High impedance or ªoffº state |
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1998 Feb 27 |
4 |