Philips 4910b DATASHEETS

INTEGRATED CIRCUITS

P32P4910B

PRML Read Channel with PR4, 8/9 ENDEC, 4-Burst Servo

Product specification 1997 July 15

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Philips Semiconductors Product specification

PRML Read Channel with PR4, 8/9 ENDEC, 4-Burst Servo

GENERAL DESCRIPTION

The Philips Semiconductors P32P4910B is a high performance BiCMOS read channel IC that provides all of the functions needed to implement an entire Partial Response Class 4 (PR4) read channel for zoned recording hard disk drive systems with data rates from 42 to 125 Mbit/s or 33 to 100 Mbit/s. Functional blocks include AGC, programmable filter, adaptive transversal filter, Viterbi qualifier , 8,9 GCR ENDEC, data synchronizer, time base generator, and 4-burst servo.

Programmable functions such as data rate, filter cutoff, filter boost, etc., are controlled by writing to the serial port registers so no external component changes are required to change zones.

The part requires a single +5V power supply. The Philips Semiconductors P32P4910B utilizes an advanced BiCMOS process technology along with advanced circuit design techniques which result in high performance devices with low power consumption.

FEA TURES General:

•Register programmable data rates from 42 to 125 Mbit/s or

33 to 100 Mbit/s

•Sampled data read channel with Viterbi qualification

•Programmable filter for PR4 equalization

•Five tap transversal filter with adaptive PR4 equalization

•8/9 GCR ENDEC

•Data Scrambler/Descrambler

•Presettable precoder state

•Programmable write precompensation

•Low operating power (0.85 W typical at 5V)

•Register programmable power management

(<5 mW power down mode)

•4-bit nibble and byte-wide bi-directional NRZ data interfaces

•I/O Mapping and In circuit test

•8-bit Direct Write mode automatically configured for

RCLK = VCO/8

•Thermal asperity detection and suppression

•Bi-directional serial interface port for access to internal program

storage registers (read and write capability)

•Single power supply (5V ± 10%)

•Small footprint, 100-lead LQFP package

P32P4910B

Automatic Gain Control:

•Dual mode AGC, analog during acquisition, sampled during data

reads

•Separate AGC level storage pins for data and servo

•Dual rate attack and decay charge pump for rapid AGC recovery

(analog)

•Programmable, symmetric, charge pump currents for data reads

(sampled)

•Charge pump currents track programmable data rate during data

reads (sampled)

•Low drift AGC hold circuitry

•Low-Z circuitry at AGC input provides for rapid external coupling

capacitor recovery

•AGC Amplifier squelch during Low-Z

•Wide bandwidth, precision full-wave rectifier

•Programmable AGC controls

– Separate external input pins for AGC hold, fast recovery, and

Low-Z control

– Internal Low-Z and fast decay timing for rapid transient

recovery and AGC acquisition. Timing set with external resistors (2). Ultra fast decay current set with external resistor. AGC input impedance vs LOWZ = 5:1.

•2-bit DAC to control AGC voltage in servo mode between 1.1

and 1.4 V

Filter/Equalizer:

•Programmable, 7-pole, continuous time filter provides:

– Channel filter and pulse slimming equalization for equalization

to PR4

– Programmable cutoff frequency from 4 to 34 MHz – Programmable boost /equalization of 0 to 13 dB – Programmable “zeros” equalization provides time asymmetry

compensation

– ±0.5 ns group delay variation from 0.3ƒc to ƒc, with

ƒc = 34 MHz

– Minimizes size and power – Low-Z switch at filter output for fast offset recovery – No external coupling capacitors required – DC offset compensation provided at filter output – Five tap transversal filter for fine equalization to PR4 – Self adapting inner taps (symmetric) – Programmable outer taps (symmetric, 4-bits) – Equalization hold input – “Zeros” channel quality output – Amplitude asymmetry factor output

1997 JuL 15 853-1952 18177

Philips Semiconductors Product specification

PRML Read Channel with PR4, 8/9 ENDEC, 4-Burst Servo

Pulse Qualification:

•Sampled Viterbi qualification of signal equalized to PR4

•Register programmable window or hysteresis pulse qualifier for

servo reads

•Selectable RDS pulse width and polarity for servo gray code reads

Time Base Generator:

•Less than 1% frequency resolution

•Up to 141 MHz frequency output

•Independent M and N divide-by registers

•No active external components required

Data Separator:

•Fully integrated data separator includes data synchronizer and

8,9 GCR ENDEC

•Register programmable to 125 Mbit/s operation

•Fast Acquisition, sampled data phase lock loop

•Decision directed clock recovery from data samples

•Adaptive clock recovery thresholds

•Programmable damping ratio for data synchronizer PLL is

constant for all data rates

•Data scrambler/descrambler to reduce fixed pattern effects

•4-bit nibble and byte-wide NRZ data interfaces

•Time base tracking, programmable write precompensation

•Differential PECL write data output

•Integrated sync byte detection, single byte or dual (“or” type)

P32P4910B

•Semi-auto training and sync byte generation available for single

sync byte operation

•Surface defect scan mode

Servo:

•4-burst servo capture with A, B, C, D outputs

•Internal hold capacitors

•“Soft Landing” charge pump architecture

•Separate, automatically selected, registers for servo ƒc, boost,

and threshold

•Programmable charge pump current

•Wide bandwidth, precision full-wave rectifier

•Programmable selection of normal or differentiated filter output to

servo capture block

•Programmable AGC gain in servo mode (2-bits)

•Full wave rectifier observation point

Thermal Asperity:

•Internal TA detector that monitors DP/DN output of continuous

time filter

•Hi-Y input modulation to rapidly attenuate offset due to TA

•AGC and PLL hold that may be triggered by TA event

•EFLAG output is dynamically generated to flag TA corrupted NRZ

data

•TAD input pin allows use of an external TA event detector

1997 JuL 15

Philips Semiconductors Product specification

PRML Read Channel with PR4, 8/9 ENDEC, 4-Burst Servo

BLOCK DIAGRAM

WCLK

NRZ0–7

SYNC

BYTE

DETECTOR

PARALLEL

INTERFACE

DESCRAMBLER

9,8

DECODER

DSCLK

SERIAL

PARALLEL

DUAL BIT

SCRAMBLER

9,8

BOUNDRY

CODE WORD

DB0–DB1

INTERFACE

ENCODER

CWBD

DETECTOR

RCLK

DWI

PRECODER

PARALLEL

MUX

SERIAL

MUX

WRITE

FLIP-FLOP

MUX

WRITE

PRECOMP

MUX

GEN

PATTERN

VCO SYNC

DWR

TBGOUT

NCLK

RCLK

CWBD

DSCLK

CHARGE

DATA SYNCHRONIZER

PHASE

DECISION

DIRECTED

DETECTOR

RCLK

GEN

CLOCK

VCO

PUMP

TBGOUT

FREQ

PHASE/

DAMPING

DETECTOR

ATO

DAC

CONTROL

TEST

ATRN

MUX

TBGOUT

POWER

TIME BASE GENERATOR

DOWN

CONTROL

P32P4910B

AGND3 AGND2 AGND1 DGND2 DGND1

PDWN

VPA3 VPA2 VPA1 VPD2 VPD1

FLTR2– FLTR2+

VCO

FLTR1– FLTR1+

PUMP

CHARGE

FREQ

PHASE/

DETECTOR

1/(N+1)

1/(M+1)

FREF

SM00171

VRDT

TPB– TPB+ TPA– TPA+

PPOL

1/12

REF

3.2V

LOGIC

CONTROL

Philips Semiconductors P32P4910B

MAXREF

STROBE

RESET

SYNC

FIELD

TAD

VREF

COUNTER

REGISTERS

SDATA

LOGIC

DECODE

QUAL

FROM LEVEL

DSCLK

FULLWAVE

RECTIFIER

SFWR

AGC

CONV

PUMP

CHARGE

AGC

CONTROL

AGC

PUMP

CHARGE

SAMPLED

VRC

LOWZ

LOGIC

FASTREC

–

VREF

PORT

SERIAL

CONTROL

SCLK

SDEN

MUX

TEST POINY

VITERBI

DETECTOR

RDS

CP CN DP DN

ON+ ON– OD+ OD–

VRX

To SFC

QUAL

PULSE

LEVEL TYPE

FILTER

LOW PASS

7TH ORDER

PROGRAMMABLE

AGC

AMP

VIA–

VIA+

BYPS

BYP

3–TAP

ADAPTIVE

SAMPLE

EQUALIZER

HOLD

PLL

AGC

HOLD

1997 JuL 15

Philips Semiconductors Product specification

PRML Read Channel with PR4, 8/9 ENDEC, 4-Burst Servo

P32P4910BP Pinout – 100 LQFP

VIA+

NC BYPD BYPS

HOLD LOWZ

FASTREC

VRDT

SCLK

SDATA

SDEN

VPF

FREF

VNF

VPT FLTR1+ FLTR1–

VNT

DWI

WD WD

NC NC NC

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

26 27 28 29 30 31 32 33

VIA–

VRX

VPA

AGCDEL

WRDEL

AGCRST

TPC–

919293949596979899100

TPC+

TPD–

TPD+

TPE

403937 38363534

VNA

PPOL/EFLAG

BURST A

RDS/RDS/TAD

81828384858687888990 80 79 7678 77

44434241

BURST C

BURST B

BURST D

48474645 5049

P32P4910B

TAD

EFLAG

VRC

MAXREF RESET

70 69

STROBE

VPS

VNS

TPA+

TPA–

TPB+

TPB–

VPS

ATO

EQHOLD

VNS

VPP

FLTR2+

FLTR2–

VNP

VNC

1997 JuL 15

WG/WG

SBD

PERRNCNRZP

NRZ0

NRZ1

NRZ2

NRZ3

VND

VPD

NRZ4

NRZ5

NRZ6

NRZ7

WCLK

RCLK

DWR

PDWN

VPC

SM00172

Philips Semiconductors Product specification

PRML Read Channel with PR4, 8/9 ENDEC, 4-Burst Servo

FUNCTIONAL DESCRIPTION

The Philips Semiconductors P32P4910B implements a complete high performance PR4 read channel, including an AGC, programmable filter/equalizer, adaptive transversal filter, Viterbi pulse qualifier, time base generator, data separator with 8,9 ENDEC and scrambler/descrambler , and 4-burst capture servo, that supports data rates from 42 to 125 Mbit/s. Data rates from 33 to 100 Mbit/s are supported by changing a single resistor.

A serial port is provided to write control data to the internal program storage registers.

AGC Circuit

The automatic gain control (AGC) circuit is used to maintain a constant signal amplitude at the input of the pulse detector and sampled data processor while the input to the amplifier varies. The circuit consists of an AGC loop that includes an AGC amplifier, charge pump, programmable continuous time filter, and a precision, wide band, full wave rectifier. Depending on whether the read is of servo or data type, the specific blocks utilized in the loop are slightly different. Both loop paths are fully differential to minimize susceptibility to noise. AGC control can be programmably selected between direct and timed modes.

AGC Operation in Servo Read Mode

During servo reads the loop consists of the AGC amplifier with a continuous dual rate charge pump, the programmable continuous time filter, and the full wave rectifier. The gain of the AGC amplifier is controlled by the voltage stored on the BYPS hold capacitor (C

The dual rate charge pump drives C

BYPS).

drive the differential voltage at DP/DN (internal nodes) to the value programmed by the 2 SAGCLVL bits in the LDS register. These 2 bits allow adjustment of the filter’s normal output voltage from

1.10 to 1.40 Vppd. Attack currents lower the voltage at the BYPS pin which reduces the amplifier gain. Decay currents raise the voltage at the BYPS pin which increases the amplifier gain. The sensitivity of the amplifier gain to changes in the BYPS voltage is approximately 38 dB/V. When the voltage at BYPS is equal to VRC, the gain from the AGC input to DP/DN will be about 24.9 dB. The charge pump is continuously driven by the instantaneous voltage at DP/DN. When the signal at DP/DN is greater than 100% of the programmed AGC level, the normal attack current (I used to reduce the amplifier gain. If the signal is greater than 125% of the programmed level, the fast attack current (I

2.86 mA is used to reduce the gain very quickly. This dual rate approach allows the AGC gain to be quickly decreased when it is too high and minimizes distortion when the proper AGC level has been acquired. The 100% and 125% levels are relative to the selected AGC level in servo mode.

A constant normal decay current (I amplifier gain when the signal at DP/DN is less than 100% of the programmed AGC level. The large ratio (340 µA:20 µA) of the normal attack and normal decay currents enables the AGC loop to respond to the peak amplitudes of the incoming read signal rather than the average value. As a result the AGC loop will not be able to quickly increase its gain if required to do so. A fast recovery mode is provided to allow the gain to be rapidly increased to reduce recovery time between mode switches. In the fast recovery mode, the decay current is increased by a factor of 8 to 160 µA (I the attack current is increased by a factor of 4.18 to 1.42 mA (I This has the effect of speeding up the AGC loop between 4 and 8 times.

) of 20 µA acts to increase the

with currents that

BYPS

) of

CHF

) of 340 µA is

) and

DFR

CHFR

P32P4910B

It is recommended that the fast recovery mode be asserted when the AGC fields from a sector are being read. Typically, this will be just after each transition of SG (Servo Gate), after powerup, and after WG/WG FASTREC is asserted for 0.5 can increase at most by 0.5 µs * 160 µA/500 pF = 160 mV, which will allow the gain to increase by 6 dB in that time. If FASTREC is asserted for 0.5 µs in non-servo mode and C the voltage at BYPD can increase at most by 0.5 µs * 160 µA/1000 pF = 80 mV, which will allow the gain to increase by 3 dB in that time. It is recommended that LOWZ be asserted for 0.5 µs just prior to any assertion of FASTREC in order to null any internal DC offsets. However, it is possible to assert both LOWZ and FASTREC simultaneously to reduce sector overhead. This method should be evaluated under the actual system operating conditions.

The programmable AGC level in servo mode is provided to allow the servo demodulator dynamic range to be adjusted over a narrow range.

AGC Operation in Data Read Mode

For data reads, the loop described above is used until the data synchronizer is locked to the incoming VCO preamble, except that the BYPD hold capacitor (C (C

BYPS

current is 2.86 mA, and the fast attack current is 2.86 mA. The fast recovery mode decay current is 160 µA and the fast recovery mode attack current is 1.42 mA. The above mentioned attack and decay currents are not scaled with the data rate setting. After the data synchronizer PLL is locked (SFC), the AGC loop is switched to include the AGC amplifier with a sampled charge pump, the programmable continuous time filter, full wave rectifier, and the sampling 5-tap equalizer to more accurately control the signal amplitude into the Viterbi qualifier. In this sampled AGC mode, a symmetrical attack and decay charge pump is used. The “1” sample amplitudes are sampled, held and compared to the ideal “1” value of 500 mV to generate the error current. The maximum charge pump current value can be programmed from the Sample Loop Control Register to 0, 34, 68, or 102 µA for maximum data rate and will scale downward with reduced Data Rate Register values.

AGC Control Modes

The AGC control mode is determined by the state of bit 6 (AGCSEL) of the Control Operating Register #1. external AGC control method is selected. For example, AGC uses external signals provided to the FASTREC, LOWZ, and HOLD pins. If bit 6 is a 1, the timed AGC control method is selected for generating the internal hold, fast recovery, squelch, and Low-Z signals.

Direct AGC Control Mode

For maximum application flexibility, all AGC mode control inputs are to be externally provided. When the LOWZ input is High, Low-Z mode is activated. In the Low-Z mode, the AGC amplifier input resistance is reduced to allow quick recovery of the AGC amplifier input AC coupling capacitors. The ratio of Low-Z to non Low-Z resistance can be selected as either 15:1 or 5:1 by programming the LZTC bit in the Data Boost Register. During Low-Z mode, the time constant of the internal AC coupling networks at the filter outputs are also reduced by the ratio determined by the LZTC bit. This time

constant is 300 ns in Low-Z and either 5 µs or 1.5 µs when not in Low-Z mode, depending on the state of the LZTC bit. Low-Z also forces the AGC amplifier gain to be reduced to near 0 V/V . This

is de-asserted. For example, if C

µs in servo mode, the voltage at BYPS

) is used instead of BYPS and

). The normal decay current is 20 µA, the normal attack

BYPD

If this bit is 0, then the direct,

is 500 pF and

BYPS

is 1000 pF, then

BYPD

input

1997 JuL 15

Philips Semiconductors Product specification

PRML Read Channel with PR4, 8/9 ENDEC, 4-Burst Servo

mode should be activated during and for a short time after a write operation. It should also be activated for a short time after each transition of the SG input and on initial power up.

When the HOLD de-activates the AGC loop. The AGC amplifier gain will be held constant at a level set by the voltage at the BYPD or BYPS pins. The value of the capacitor placed at these pins should be selected to give adequate droop performance when in hold mode as well as to insure stability of the AGC loop when it is active.

The signal provided to the FASTREC input pin determines if the AGC is in fast recovery mode. During the fast recovery (FASTREC=1), the attack and decay currents are increased to allow faster recovery to the proper AGC level. If faster recovery than is provided by FASTREC alone is desired, an ultra fast recovery can be effected by connecting a resistor between the AGCRST pin and the positive supply VPA. If this resistor is present, whenever FASTREC is entered, the voltage on the BYPD or BYPS capacitor will be pulled up. This causes an extremely rapid increase in the AGC amplifier gain. The ultra fast current will be disabled the first time that the signal at DP/DN reaches the 125% point. The FASTREC attack and decay currents are used as long as the FASTREC pin is held High.

input is Low, the charge pumps are disabled. This

P32P4910B

Timed AGC Control mode

This timed AGC control mode differs from the direct control mode in that the external control inputs LOWZ, FASTREC, and HOLD typically not used, and therefore, must be deasserted. The equivalent signals are generated internal to the P32P4910B. These internal signals are generated by one-shots that are triggered by various conditions of the WG/WG

, SG, and PDWN inputs. The one-shot timings for the Low-Z and fastrec signals are set by the resistors connected to the WRDEL and AGCDEL input pins, respectively and analog ground.

The time Low-Z period (µs) = 0.1 * [0.5 + R recovery period (µs) = 0.1 * [0.5 + R

AGCDEL

(kΩ)] and the fast

WRDEL

(kΩ)]. The current for the ultra fast decay mode is set by the resistor connected between the AGCRST input pin and VPA. In the timed mode, the AGC shall use the C

BYPD

and C

for non-servo and servo modes

BYPS

respectively. The nominal and fast attack and decay currents are the same in both of the P32P4910B’s AGC control modes. In internally timed mode, the LOWZ, FASTREC, and HOLD are logically OR’ed with their respective internal control signals but do not affect the internal sequencing of the one-shot generated AGC

control signals.

, are

input pins

AGC

INPUT

PDWN

AGC LOWZ

FAST FILTER

OFFSET RECOVERY

AGC HOLD

AGC SQUELCH

AGC FAST RECOVERY

(ATTACK & DECAY)

AGC ULTRA

FAST RECOVERY

(DECAY)

OUTPUT

AGC

POWERED UP

Ultra fast decay current is disabled when signal is greater than 125% of nominal.

–

ULTRA

FAST

DECAY

FAST

ATTACK

NORMAL

ATTACK

125% 100%

SM00173

Figure 1. Power-On Mode Gain Recovery

1997 JuL 15

Philips Semiconductors Product specification

PRML Read Channel with PR4, 8/9 ENDEC, 4-Burst Servo

AGC

INPUT

AGC LOWZ

FAST FILTER

OFFSET RECOVERY

AGC HOLD

SQUELCH

AGC FAST RECOVERY

(ATTACK & DECAY)

AGC ULTRA

FAST RECOVERY

(DECAY)

AGC OUTPUT

–

ULTRA

FAST

DECAY

Figure 2. Servo Mode Gain Recovery

FAST

ATTACK

Ultra fast decay current is disabled when signal is greater than 125% of nominal.

125% 100%

P32P4910B

SM00165

AGC

INPUT

AGC LOWZ

FAST FILTER

OFFSET RECOVERY

AGC HOLD

AGC SQUELCH

AGC FAST RECOVERY

(ATTACK & DECAY)

AGC ULTRA

FAST RECOVERY

(DECAY)

AGC

OUTPUT

–

Ultra fast decay current is disabled when

signal is greater than 125% of nominal.

ULTRA

FAST

DECAY

125% 100%

NORMAL

ATTACK

FAST

ATTACK

SM00166

1997 JuL 15

Figure 3. Write Mode Gain Recovery

Philips Semiconductors Product specification

PRML Read Channel with PR4, 8/9 ENDEC, 4-Burst Servo

Pulse Qualification Circuit

This device utilizes three different types of pulse qualification, one exclusively for servo reads, one primarily for servo reads, and the other for data reads.

Servo Read Mode

For servo gray code reads, either a dual level (window type) qualifier or a hysteresis type level qualifier may be selected. If the PDM bit in the Filter Cutoff Servo Register is set to 0, then the window qualifier is selected, and if the PDM bit equals 1, the hysteresis qualifier is selected. The polarity of the RDS/RDS (Servo Mode Select) in the Data Rate Register. If SMS is set to 0, then RDS is active-Low and if SMS bit equals 1, then RDS is active-High.

Dual Level (Window) Qualifier

During servo reads (SG High) a dual level type of pulse qualifier is used. The level qualification thresholds are set by a 6-bit DAC which is controlled by the Servo Level Threshold Register (LDS). The register value is relative to the peak voltage at the output of the continuous time filter derived off of the same reference voltage internal to the chip. The positive and negative thresholds are equal in magnitude. The state of the adaptive threshold level enable (ALE) bit in the WP/LT Register does not affect this DAC’s reference. The RDS/RDS qualifier indicate a qualified servo pulse and the polarity of the pulse, respectively. The RDS/RDS when the SG input is High.

Hysteresis Qualifier

The hysteresis qualifier performs the same as the window qualifier except that the hysteresis qualifier guarantees that the second of two consecutive pulses of the same polarity will not be qualified. The hysteresis qualifier will only qualify pulses of alternating polarity.

Data Read Mode

In data read mode (RG High), the dual level qualifier used for servo reads, is used during VCO sync field counting. Its qualification thresholds are set by a 6-bit DAC which is controlled by or the Data Level Threshold Register (LD). The register value is relative to the peak voltage at output of the continuous time filter and the DAC both referenced to a fixed band gap voltage. The positive and negative

and the PPOL outputs of the level

and PPOL outputs are only active

is selected by the SMS bit

P32P4910B

thresholds are equal in magnitude. The state of the adaptive threshold level enable (ALE) bit in the WP/LT Register does not affect the DAC’s reference until the sync field count has been achieved. The RDS/RDS qualifier are not active in data read mode.

Viterbi Qualifier

The second type of pulse qualification, the Viterbi qualifier, is only used during data read mode after the sync field count has been achieved. The Viterbi qualifier has two significant blocks, one that feeds the other. The first block is the sampled pulse detector and the second is the Survival Sequence Register.

The sampled pulse detector performs the pulse acquisition/detection in the sampled domain. It acquires pulses by comparing the code clock sampled analog waveform to the positive and negative thresholds established by the programmable Viterbi threshold window. The threshold window is defined to be the dif ference between the positive and negative threshold levels. The threshold window, Vth, is set by a 7-bit DAC which is controlled by the V iterbi Detector Threshold Register (VDT). While the window size is fixed by the programmed Vth value, the actual positive and negative thresholds track the most positive and the most negative samples of the equalized input signal. For example, the Viterbi positive signal threshold, Vpt = Vpeak (+)max if the previous detected level was (+). If the previous detect level was (–), Vpt = Vpeak(–)max + Vth, where Vpeak(–)max is the maximum amplitude of the previously detected negative signal. Normally Vth is set to equal Vpeak (approx. 500 mV).

After the pulses have been detected, they must be further qualified by the Survival Sequence Registers and associated logic. This logic guarantees that for sequential pulses of the same polarity within the maximum run length, only the latest is qualified. In this way, only the pulse of greatest amplitude will be qualified.

The Viterbi qualifier is implemented as two parallel qualifiers that operate on interleaved samples. Each qualifier has a Survival Sequence Register length of 5.

To facilitate media scan testing, the Viterbi Survival Sequence register may be bypassed by setting the BYPSR bit in the Viterbi Detector Threshold (VDT) register.

and the PPOL outputs of the level

1997 JuL 15

Philips Semiconductors Product specification

PRML Read Channel with PR4, 8/9 ENDEC, 4-Burst Servo

+th

Viterbi

Threshold

WIndow

–th

+ pulse detect

– pulse detect

Viterbi

Detector

Output

For sequential pulses of the same polarity, the latest is selected by the Survival Sequence register logic since it is always of greater magnitude.

P32P4910B

SM00032

Figure 4. Viterbi Detection

Programmable Filter Circuit

The on-chip, continuous time, low pass filter has register programmable cutoff and boost settings, and provides both normal and differentiated outputs. It is a 7th order filter that provides a

0.05 phase equiripple response. The group delay is relatively constant up to twice the cutoff frequency. For pulse slimming two zero programmable boost equalization is provided with no degradation to the group delay performance. The differentiated output is created by a single-pole, single-zero differentiator. Both the boost and the filter cutoff frequency for data reads and the filter cutoff frequency for servo reads are programmed through internal 7-bit DACs, which are accessed via the serial port logic. The nominal boost range at the cutoff frequency is 0 to 13 dB for data reads and is controlled by the Data Boost Register. In servo mode, the boost can be programmed in 2 dB steps from 0 to 6 dB by programming the two FBS bits (bits 6 and 7) in the Filter Boost Servo register. The cutoff frequency, ƒc is variable from 4 to 34 MHz and controlled by the Data Cutoff Register or Servo Cutoff Register in the servo mode. The cutoff and boost values for servo reads are automatically switched when servo mode is entered.

 s2–s+1.31703

+1.68495s+1.31703

2.95139

s2+1.54203s+2.95139

The filter zero locations can be programmed asymmetrically about zero to compensate for MR head time asymmetry. The asymmetry is adjusted by programming the 6 FGD bits (bits 0-5) in the Filter Boost Servo register. The asymmetric zeros are not usable while in servo mode.

The normal low pass filter is of a seven-pole two-real-zero type. Figure 5 illustrates the transfer function normalized to 1 rad/s. The response can be denormalized to the cutoff frequency of ƒc (Hz) by replacing s by s/2πƒc, while the boost and group delay equalization are controlled by varying the α and β.

With a zero at the origin, the filter provides a time-differentiated filter output. This is used in time qualification of the peak detection. To ease the timing requirement in peak detection of a signal slightly above the qualification threshold, the time-differentiated output is purposely delayed by 1.2 ns relative to the normal low pass output.

The normal low pass output feeds the data qualifier (DP/DN), and the differentiated output feeds the clock comparator (CP/CN).

5.37034

s2+1.14558s+5.37034

0.86133

s+0.86133

Normal

1997 JuL 15

Figure 5. Programmable Filter Normalized Transfer Function

s+0.86133

Differentiated

SM00010

Philips Semiconductors Product specification

PRML Read Channel with PR4, 8/9 ENDEC, 4-Burst Servo

Five definitions are introduced for the programmable filter control discussion (Figure 6):

Cutoff Frequency—The cutoff frequency is the –3 dB low pass bandwidth with no boost and group delay equalization, i.e.: α=0 and β=0.

Actual Boost—The amount of peaking in magnitude response at the cutoff frequency due to α≠0 and/or β≠0.

Alpha Boost—The amount of peaking in magnitude response at the cutoff frequency due to α≠0 and without group delay equalization. In general, the actual boost with group delay equalization is higher than the alpha boost. However, with >3 dB alpha boost, the difference is minimal.

Actual Boost, same as Alpha Boost with 0%

Magnitude (dB)

–5

–10

–15

–20

Group Delay Change or Alpha Boost is large

–3dB Cutoff Frequency

1 10 100

Cutoff = 10MHz (i) 0dB Alpha Boost & 0% Group Delay Change

(ii) 13dB Alpha Boost & +30% Group Delay Change

Frequency (MHz)

Figure 6. Filter Magnitude Response

P32P4910B

Group Delay ∆%—The group delay ∆% is the percentage change in absolute group delay at DC with respect to that without equalization applied (β=0).

Group Delay Variation—The group delay variation is the change in group delay from DC to the cutoff frequency. This can be expressed as a percentage defined as: (change in group delay ÷ absolute group delay with β=0) * 100%. An alternative is to express the group delay variation in nanoseconds. Because the absolute group delay variation in nanoseconds is scaled by the programmed cutoff frequency, the percentage expression is used in this specification.

Actual –3dB Bandwidth

with Boost & Group

Delay Equalization

(ii)

(i)

SM00011

1997 JuL 15

(ii)

Absolute Group Delay (ns)

1 10 100

DC Group Delay Change

Programmable from

–30% to +30%

(i)

Frequency (MHz)

Cutoff = 10 MHz (i) 0dB Alpha Boost & 0% Group Delay Change

(ii) 13dB Alpha Boost & +30% Group Delay Change

Group Delay Variation from

DC to Cutoff Frequency

Figure 7. Filter Group Delay Response

SM00012

Philips Semiconductors Product specification

Alpha Boost

PRML Read Channel with PR4, 8/9 ENDEC, 4-Burst Servo

Filter Operation

Direct coupled differential signals from the AGC amplifier output are applied to the filter. The programmable bandwidth and equalization characteristics of the filter are controlled by 3 internal DACs. The registers for these DACs (FC, FB, and FGD) are programmed through the serial port. The current reference for the DACs is set using a single external resistor connected from pin VRX to ground. The voltage at pin VRX is proportional to absolute temperature (PTAT), hence the current for the DACs is a PT AT reference current. This establishes the excellent temperature stability for the filter characteristics.

The cutoff frequency can be set independently in the servo mode and the data mode. In the data mode, the cutoff frequency is controlled by the Data Cutoff Register. In the servo mode, the cutoff frequency is controlled by the Servo Cutoff Register.

Table 1. Ratio of Actual –3dB Bandwidth to Cutoff Frequency

±30% ±25% ±20% ±15% ±10% ±5% ±0%

0 dB 1.62 1.47 1.31 1.16 1.06 1.01 1.00 1 1.74 1.62 1.50 1.38 1.28 1.21 1.19 2 1.87 1.79 1.71 1.63 1.56 1.51 1.49 3 2.01 1.96 1.91 1.87 1.83 1.80 1.79 4 2.14 2.11 2.09 2.07 2.05 2.04 2.03 5 2.25 2.24 2.23 2.22 2.21 2.20 2.20 6 2.35 2.34 2.34 2.33 2.33 2.32 2.32 7 2.44 2.44 2.43 2.43 2.42 2.42 2.42 8 2.52 2.52 2.51 2.51 2.51 2.51 2.51 9 2.59 2.59 2.59 2.59 2.59 2.59 2.59 10 2.67 2.66 2.66 2.66 2.66 2.66 2.66 11 2.73 2.73 2.73 2.73 2.73 2.73 2.73 12 2.80 2.80 2.80 2.80 2.80 2.80 2.80 13 2.87 2.87 2.86 2.86 2.86 2.86 2.86

Cutoff Control

The programmable cutoff frequency from 4 to 34 MHz is set by the 7-bit linear FC DAC. The FC register holds the 7-bit DAC control value. The cutoff frequency is set as:

ƒc (MHz) = 0.301 * FC – 1.142 44 ≤ FC ≤ 117 for servo zones

ƒc (MHz) = 0.277 * FCS + 0.08 14 ≤ FCS ≤ 43 The filter cutoff (ƒc) is defined as the –3 dB bandwidth with no boost

applied. When boost/equalization is applied, the actual –3 dB point will move out. The ratio of the actual –3 dB bandwidth to the programmed cutoff is tabulated in Table 1 as a function of applied boost and group delay equalization.

Group Delay ∆%

P32P4910B

Boost Control

The programmable alpha boost from 0 to 13 dB is set by the 7-bit linear FB DAC in data mode or 2-bit linear FBS DAC in servo mode. The FB register holds the 7-bit DAC control value and the FBS register holds the 2-bit control value. The alpha boost in data mode is set as:

Alpha Boost (dB) = 20 log [0.021848 * FB + 0.000046 * FB * FC + 1] 0 ≤ FB ≤ 127

The alpha boost in servo mode is set as: Alpha Boost (dB) = 2 * FBS 0 ≤ FBS ≤ 3

1997 JuL 15

That is, the boost in servo mode can be changed in 2 dB steps from 0 to 6 dB.

The programmed alpha boost is the magnitude gain at the cutoff frequency with no group delay equalization. When finite group delay equalization is applied, the actual boost is higher than the programmed alpha boost. However, the difference becomes negligible when the programmed alpha boost is >3 dB. Table 2 tabulates the actual boost as a function of the applied alpha boost and group delay equalization.

Philips Semiconductors Product specification

Alpha Boost

PRML Read Channel with PR4, 8/9 ENDEC, 4-Burst Servo

Table 2. Actual Boost vs Alpha Boost and Group Delay Change

Group Delays ∆%

±30% ±25% ±20% ±15% ±10% ±5% ±0%

0 dB 2.81 2.12 1.47 .89 0.42 0.11 0.00 1 3.36 2.76 2.21 1.72 1.33 1.09 1.00 2 3.97 3.45 2.99 2.58 2.27 2.07 2.00 3 4.63 4.19 3.80 3.47 3.21 3.05 3.00 4 5.34 4.97 4.65 4.38 4.17 4.07 4.00 5 6.10 5.79 5.52 5.30 5.14 5.03 5.00 6 6.89 6.64 6.42 6.24 6.11 6.03 6.00 7 7.72 7.51 7.34 7.19 7.09 7.02 7.00 8 8.58 8.41 8.27 8.15 8.07 8.02 8.00 9 9.47 9.33 9.22 9.12 9.05 9.01 9.00 10 10.4 10.3 10.2 10.1 10.1 10.0 10.0 11 11.3 11.2 11.1 11.1 11.0 11.0 11.0 12 12.2 12.2 12.1 12.1 12.0 12.0 12.0 13 13.2 13.1 13.1 13.1 13.0 13.0 13.0

P32P4910B

Group Delay Equalization

The group delay ∆% can be programmed between –30% to +30% by the 6-bit linear FGD DAC. The FGD register holds the 6-bit DAC control value. The group delay ∆% is set as:

Group Delay ∆% = 0.9783 * (FGD4:0) – 0.665 0 ≤ FGD4:0 ≤ 31 and FGD5 = sign bit

The group delay ∆% is defined to be the percentage change of the absolute group delay due to equalization from the absolute group delay without equalization at DC.

The current reference for the filter DACs is set using a single

12.1 kΩ resistor, from the VRX pin to ground. The voltage at VRX is proportional-to-absolute-temperature (PTA T).

The outputs of the filter are internally AC coupled to the qualifier inputs and buffers for the filter monitoring test points TPC+/TPC– and TPD+/TPD–.

Internal AC Coupling

The conventional external ac coupling at the filter to qualifier interface has been replaced by a pair of feedback circuits, one for the normal and one for the differentiated outputs of the filter. The offset of the filter outputs are sensed, integrated, and fed back to the filter output stage. The feedback loop forces the filter offset nominally to zero. In the normal read mode, (LOWZ=0), the integration time constant is set to 5 µs until the sync field counter reaches the programmed SFC count. At the SFC count, the offset sensing is switched into sampled mode and the time constant is reduced to 300 ns. In sampled mode the offset correction voltage is generated from the zeros qualified by the quantizer. This ensures that the sampled voltage level, not DP/DN, will be offset free.

Amplitude Asymmetry Detection and Correction

In the presence of amplitude asymmetry, such as that generated by MR heads, the sampled data processor (SDP) will be presented with

zeros generated in one of two ways. The first is due the lack of a magnetic transition and will be referred to as a “real” zero. The second is produced by the superposition of adjacent +1 and –1 magnetic transitions and results in zero samples that shall be referred to as “cancelled” zeros. In the presence of amplitude asymmetry from an MR head, the “real” zeros are zero, but the “cancelled” zeros are offset by the difference between the +1 and –1 samples.

The offset correction circuit forces the ground reference of the sampled data processor to the center of the “real” and “cancelled” zero sample levels.

The integration time constant is increased by a factor of 4 to 1.0 µs, after the sync byte has been detected.

Amplitude Asymmetry Monitor Point

An amplitude asymmetry quality factor “Qasym” may be selected to be output on the AT O output pin by programming the ASEL bits in the Power Down Register. This signal is derived by computing the average distance of the “real” and “canceled” zeros from the sampled data processor’s system ground which was established between the two zeros levels by the offset correction circuit. The average distance is a measure of the asymmetry present in the MR read back signal. A gain of 8 from the sampled values is utilized and is low pass filtered with a time constant that is programmable to one of four different values by programming the two QTC bits in the Control Operating Mode Register 2.

The signal is then buffered and differentially multiplexed to the ATO pin. The signal is referenced to MAXREF/2.

The asymmetry quality factor can be held at the value present at sync byte detect by setting the FREZQ bit in the WP/LT Register. The value will be held for 10 ms and is NOT reset. The ATO output may also be externally filtered to provide time constants that are appropriate for averaging over major portions of, or an entire sector.

1997 JuL 15

Philips Semiconductors Product specification

PRML Read Channel with PR4, 8/9 ENDEC, 4-Burst Servo

The capacitors on externally added filters must be externally reset. Note that any external filtering added to AT O output pin will affect both the amplitude asymmetry monitor signal and the equalization quality monitor signal since they are both muxed to the AT O output pin.

Adaptive Equalizer Circuit

Up to 7 dB of equalization for fine shaping of the incoming read signal to the PR4 waveshape is provided by a 5 tap, sampled analog, transversal filter. This filter provides a self adaptive multiplier coefficient for the inner taps and a programmable coefficient for the outer taps. Both inner taps use the same coefficient (k

For the adaptive inner taps, the value of k “zero” samples to zero volts. A special equalizer training pattern, located after the VCO sync field in the sector format, is used to provide an optimum signal for the equalizer to adapt to. The adaptive property of these taps is enabled or disabled by the AEE bit in the Sample Loop Register. If the adaptive property is enabled, whether adaptation occurs only during the training pattern or both during the training pattern and the user data is controlled by the AED bit in the Sample Loop Register.

The adaptation can be observed when the equalizer control voltage is selected as the TPA+/TPA– output. The equalizer control voltage is approximately related to km1 by:

= 0.009 * Date Rate (Mbit/s) * (TPA+ – TPA–)

The multiplier coefficients for the adaptive taps can be held for up to 10 ms if the EQHOLD input is brought High after sync byte detect

), and both outer taps use the same coefficient (km2).

is adjusted to force

n-1

P32P4910B

has occurred during a previous read in which proper training has occurred. The EQHOLD input pin may be asserted at any time during a read cycle and the adaptive coefficient k time will be held, provided no leakage occurs, until the EQHOLD input is de-asserted.

The multiplier coefficient, k

, for the outer taps is programmable

between +0.1 17 and –0.135 by the 4 km bits (bits 4–7) in the Control Operating Mode Register 2

Equalization Quality Monitor Point

An equalization quality factor “Q” may be selected to be output on the ATO output pin by programming the ATOSEL bits in the Power Down Register and should be used as a guide for selection of the appropriate value for k

This signal is derived by computing the

m2.

absolute distance of the “real” and “canceled” zeros from the sampled data processor’s system ground which was established between the two zeros levels by the offset correction circuit. Then the asymmetry factor (QASYM) is subtracted and the resulting signal is full wave rectified and low pass filtered using one of the four time constants that may be programmed with the two QTC bits in the Control Operating Mode Register 2. The signal is then buffered and differentially multiplexed to the ATO pin. The overall gain to the ATO pin is 4. The signal is referenced to MAXREF/2.

The equalization quality factor can be held at the value present at sync byte detect by setting the FREZQ bit in the WP/LT Register. The value will be held for approximately. 10 ms and is NOT reset. The ATO output may also be externally filtered to provide time constants that are appropriate for averaging over major portions of, or an entire sector. The capacitors on externally added filters must be externally reset.

n-2

n-3

n-4

present at that

0V 0V

yn = k

km1 coefficient adapts to force ’0’ samples to 0V

xn + k

need more boost decrease km

Figure 8. Block Diagram of 5-Tap Equalizer

+ km2 x

n-4

need less boost increase km

SM00026

+ x

+ km1 x

n-1

n-2

n-3

1997 JuL 15

Philips Semiconductors Product specification

PRML Read Channel with PR4, 8/9 ENDEC, 4-Burst Servo

Time Base Generator Circuit

The time base generator (TBG) is a PLL based circuit, that provides a programmable reference frequency to the data separator for constant density recording applications. This time base generator output frequency can be programmed with a less than 1% accuracy via the M, N and DR Registers. The TBG output frequency, Fout, should be programmed as close as possible to ((9/8) * NRZ Data Rate). The time base also supplies the timing reference for write precompensation so that the precompensation tracks the reference time base period.

The time base generator requires an external passive loop filter to control its PLL locking characteristics. This filter is fully-differential and balanced in order to reduce the effects of common mode noise.

In read, write and idle modes, the programmable time base generator is used to provide a stable reference frequency for the data separator. In the write and idle modes, the Time Base Generator output, when selected by the Control Test Mode Register, can be monitored at the TPB+ and TPB– test pins. In the read mode, the TBG output should not be selected for output on the test pins so that the possibility of jitter in the data separator PLL is minimized.

The reference frequency is programmed using the M and N registers of the time base generator via the serial port, and is related to the external reference clock input, FREF, as follows:

= FREF * [(M + 1) B (N + 1)]

TBG

The M and N values should be chosen with the consideration of phase detector update rate and the external passive loop filter design. The Data Rate Register must be set to the correct VCO center frequency. The time base generator PLL responds to any changes to the M and N registers, only after the DR register is updated.

The DR register value, directly affects the following:

•center frequency of the time base generator VCO,

•center frequency of the data separator VCO,

•phase detector gain of the time base generator phase detector,

•phase detector gain of the data separator phase detector,

•write precompensation

The reference current for the DR DAC is set by an external resistor, RR, connected between the RR pin and ground.

RR = 10.0 kΩ for 42 to 125 Mbit/s data rate range RR = 12.1 kΩ for 33 to 100 Mbit/s data rate range

P32P4910B

Data Separator Circuit

The Data Separator circuit provides complete encoding, decoding, and synchronization for 8,9 (0,4,4) GCR data. In data read mode, the circuit performs clock recovery, code word synchronization, decoding, sync byte detection, descrambling, and NRZ interface conversion. In the write mode, the circuit generates the VCO sync field, scrambles and converts the NRZ data into 8,9 (0,4,4) GCR format, precodes the data, and performs write precompensation.

The circuit consists of five major functional blocks; the data synchronizer, 8,9 ENDEC, NRZ scrambler/descrambler, NRZ interface, and write precompensation.

Data Synchronizer

The data synchronizer uses a fully integrated, fast acquisition, PLL to recover the code rate clock from the incoming read data. To achieve fast acquisition, the data synchronizer PLL uses two separate phase detectors to drive the loop. A decision-directed phase detector is used in the read mode and phase-frequency detector is used in the idle, servo, and write modes.

In the read mode the decision-directed timing recovery updates the PLL by comparing amplitudes of adjacent “one” samples or comparing the “zero” sample magnitude to ground for the entire sample period. A special (non IBM) algorithm is used to prevent “hang up” during the acquisition phase. The determination of whether a sample is a “one” or a “zero” is performed by a dedicated, dual mode, threshold comparator. This comparator’s threshold levels are determined by the value, Lth, programmed in the Data Threshold Register. The fixed level threshold before the sync field count (SFC) has been achieved will be 1.4 times the threshold level after SFC since this is the ratio of the peak signal to the sampled “1” signal amplitude for PR4. The dual mode nature of this comparator allows the selection of either symmetric fixed or independent self adapting (+) and (–) thresholds by programming the adaptive level enable (ALE) bit in the WP/LT Register. Also at SFC, the gain of the phase detector is reduced by a factor of 6 or 10, selectable by the GS bit in the Damping Ratio Control register. This gain shift increases the loop’s noise immunity during data tracking by reducing its bandwidth.

The adaptive reference allows the specification of the threshold value to be a percentage of an averaged peak value. When adaptive mode is selected, the fixed thresholds are used until the sync field count (SFC) has been reached, then the adaptive levels are internally enabled. The time constant of a single pole filter that controls the rate of adaptation, is programmable by bits TC2:1 in the WP/LT Register.

1997 JuL 15

Sampled Read Data from Adaptive Equalizer

Reference Frequency from Time Base Generator

VCO

KDS

SAMPLED DATA

PHASE DETECTOR

KDI

PHASE/FREQUENCY

DETECTOR

Figure 9. Data Synchronizer Phase Locked Loop

READ MODE

IDLE/WRITE

MODE

CHARGE

PUMP

Cint

12pF

Cext

KVCO

DSCLK

VCO

SM00033

Philips Semiconductors Product specification

PRML Read Channel with PR4, 8/9 ENDEC, 4-Burst Servo

In the write and idle modes the non-harmonic phase-frequency detector is continuously enabled, thus maintaining both phase and frequency lock to the time base generator’s VCO output signal, F

The polarity and width of the detector’s output current pulses

TBG.

correspond to the direction and magnitude of the phase error. The two phase detectors’ outputs are muxed into a single differential

charge pump which drives the loop filter directly. The loop filter requires an external capacitor. The loop damping ratio is programmed by bits 6-0 in the Damping Ratio Control Register. The programmed damping ratio is independent of data rate.

In write mode, the TBG output is used to clock the encoder, precoder, and write precompensation circuits. The output of the precompensation circuit is then fed to the write data flip-flop which generates the write data (WD, WD

ENDEC

The ENDEC implements an 8,9 (0,4,4) Group Coded Recording (GCR) algorithm. The code has a minimum of no zeros between ones and a maximum of four zeros between ones for the interleaved samples. During write operations the encoder portion of the ENDEC converts 8-bit parallel, scrambled or nonscrambled, data to 9-bit parallel code words that are then converted to serial format. In data read operation, after the code word boundary has been detected in the Viterbi qualified serial data stream, the data is converted to 9-bit parallel form and the decoder portion of the ENDEC converts the 9-bit code words to 8-bit NRZ format.

Sync Byte Detection

The P32P4910B supports two types of sync byte detection; dual byte and single byte.

Dual Sync Byte Detection

The P32P4910B implements a dual “or” type sync byte detection scheme to reduce the probability that a single bit error will lead to the inability to synchronize. The two sync bytes are different and are spaced apart by one byte. The first sync byte is 1FH and the second is 69H. Sync byte detection is considered to have occurred if either of the two sync bytes is found but the sync byte detect output pin (SBD

) is transitioned at the position in time when the

) outputs.

P32P4910B

second sync byte (69H) would have been detected. The data placed on the NRZ outputs when SBD goes Low is always the second sync byte (69H) regardless of which of the two was actually detected.

Single Sync Byte Detection

Since the P32P4910B looks for either of the two sync bytes, the absence of the first sync byte is not an error. This allows for only a single byte to be written and still be able to achieve synchronization. It is recommended that only the 69H be written if single sync byte detection is desired so that when detection occurs, the data output on the NRZ pins at sync byte detect will match the sync byte written.

Single Sync Byte Detection when Semi Automatic Training Is Enabled

When the AUTOTR bit is set in the Control Operating Register, the training/sync byte sequence is generated with an internal state machine. The internal state machine generates the 5-byte equalizer training pattern (93H) followed by the second sync byte (69H); the first sync byte (1FH) is not written by the internal state machine. To initiate the writing of the training pattern and sync byte in this mode, an FFH must be placed on the NRZ bus for 6 byte times prior to the user data. This mode may be desirable if controller state machine space is very limited.

Scrambler/Descrambler

The scrambler/descrambler circuit is provided to reduce fixed pattern effects on the channel’s performance. It is enabled or disabled by bit 2 (SD) of the Control Operating Register. In write mode, if enabled, the circuit scrambles the 8-bit internal NRZ data before passing it to the encoder. Only user data, i.e., the NRZ data following the second sync byte (69H), is scrambled. In data read mode, only the decoded NRZ data after the second sync byte (69H) is descrambled.

The scrambler polynomial is H(X)= 1 ⊕ X7 ⊕ X10. The scrambler block diagram is shown in Figure 10. The scrambler contributes no delay in either the encode or decode paths and therefore there is no difference in path delays whether or not the scrambler is enabled.

1997 JuL 15

XOR

X0 X1 X2 X3 X4 X5 X6 X7 X8 X9

XOR

NRZ0–7

Figure 10. P32P4910B Scrambler Block Diagram

SCRAM0–7

SM00034

Philips Semiconductors Product specification

PRML Read Channel with PR4, 8/9 ENDEC, 4-Burst Servo

NRZ Interface

The NRZ interface circuit provides the ability to interface with either a nibble or byte-wide controller . The NRZ interface type is specified by the programming of bit 4 (NIB) of the Control Operating Register. If byte-wide mode is selected, the circuit does not reformat the data before passing it to and from the internal 8-bit bus. If nibble mode is selected, the NRZ interface circuit converts the 4 LSBs of the external 8-bit bus to the internal 8-bit bus. Only the selected NRZ interface is enabled and the unused bits can be left floating. Both the byte-wide and nibble interfaces define the most significant bit of the interface as the most significant bit of the data and the nibble interface defines the first nibble clocked in or out as the most significant of the pair.

For both byte-wide and nibble operation, the NRZ write data is latched by the P32P4910B on the rising edge of the WCLK input.

RCLK NRZ3 NRZ2

NRZ1 NRZ0

WCLK

bit 7 bit 6 bit 5 bit 4

byte 0 = MSN byte 0 = LSN byte 1 = MSN

Read Mode–Nibble

P32P4910B

The WCLK frequency must be appropriate for the data rate chosen or else overflow/underflow will occur. It is recommended that WCLK be connected to RCLK to prevent this from occurring. In byte-wide mode, as each NRZ byte is input to the P32P4910B, its parity is checked against the controller supplied parity bit NRZP. If an error is detected, the PERR output pin goes High and remains High until WG/WG

goes inactive. The timing is shown in Figure 11.

In data read mode, the NRZ data will be presented to the controller near the falling edge of RCLK so that it can be latched by the controller on the rising edge of RCLK. When RG goes High, the selected NRZ interface will output Low data until the sync byte has been detected. The first non-zero data presented will be the sync byte (69H). The NRZ interface is at a high impedance state when not in data read mode. In byte-wide mode, an even parity bit, NRZP, is generated for each output byte.

bit 3 bit 2 bit 6 bit 1

bit 0

bit 7

bit 5

bit 4

NRZ3

NRZ2

NRZ1

NRZ0

RCLK

NRZ0–7

WCLK

NRZ0–7

bit 7

bit 6

bit 5 bit 4

byte 0 = MSN byte 0 = LSN byte 1 = MSN

Write Mode–Nibble

byte 0 byte 1

Read Mode–Byte Wide

byte 0 byte 1

Write Mode–Byte Wide

bit 3

bit 2 bit 6

bit 1

bit 0

bit 7

bit 5

bit 4

Figure 11. NRZ Timing

SM00035

1997 JuL 15

Philips Semiconductors Product specification

PRML Read Channel with PR4, 8/9 ENDEC, 4-Burst Servo

XOR

CODED DATA

D D

Figure 12. Precoder Block Diagram

Write Precoder

The P32P4910B implements a 1/(1⊕D used to precode the serialized encoder data for PR4. The state of the precoder is preset to 0,0 upon exiting write mode. This guarantees that precoder will begin the next write in the 0,0 state. The state of the precoder is not guaranteed when the write data (WD/WD that one of 2 different write data patterns or their inverses may be written for a particular write. All four of these patterns will decode properly upon read back. As a result of the fact that the write data toggle flip-flop is utilized as part of the precoder, the read/write amplifier connected (AC coupled) to the P32P4910B must not contain a toggle flip-flop. The precoder block diagram is shown in Figure 12.

Write Precompensation

The write precompensation circuitry is provided to compensate for media bit shift caused by magnetic nonlinearities. The circuit recognizes specific write data patterns and can add delays in the time position of write data bits to counteract the magnetic nonlinearity effect. The magnitude of the time shift, WPC, is programmable via the Write Precomp Register and is made proportional to the time base generator’s VCO period (i.e., data rate). The circuit performs write precompensation only on the second of two consecutive “ones” and only shifts in the late direction. If more than two consecutive “ones” are written, all but the first are precompensated in the late direction.

) changes from sync field to encoded data. The result is

Servo Demodulator Circuit

Servo functionality is provided by two separate circuits: the servo demodulator circuit, and the previously described dual level pulse qualifier circuit. T o support embedded servo applications, P32P4910B provides separate programmable registers for servo mode filter cutoff frequency , boost, and qualification threshold. The values programmed in these registers are selected upon entry into servo mode (SG=1). Either the normal or the differentiated filter output can be routed to the servo demodulator by programming the Servo Mode Select (SMS) bit in the Data Rate Register. This bit also determines the polarity of the RDS/RDS RDS/RDS by the RDSPW bit in the Sample Loop Control Register and the SBCC bits in the Data Level Threshold register respectively.

The servo demodulator circuit captures four separate servo bursts and provides an amplified and offset version of the voltages captured for each at the A, B, C, D output pins respectively. The circuit uses a “Soft Landing” charge pump with programmable initial charge current to charge each of the internal 10 pF burst hold capacitors. This “soft landing” charge pump architecture minimizes the overshoot of the hold capacitor beyond the actual instantaneous peak voltage at the full wave rectifier output. Internal burst hold capacitors are provided to support low leakage burst capture and to

pulse width and initial charge pump current is determined

) write precoder which is

output. In addition, the

P32P4910B

WRITE CURRENT

SM00007

reduce external component count. Burst capture control is provided by the STROBE and RESET output pins, the circuit provides a maximum reference voltage at the MAXREF output pin. This reference voltage represents the maximum voltage that can be achieved at the A, B, C, D output pins with a 1.4 Vpp signal at the filter output and is typically used as the reference voltage for an external A/D converter.

Burst Capture

Burst capture is controlled by the signal applied to the STROBE input pin and an internal counter. The first pulse on the STROBE input pin causes the A burst hold capacitor to be charged by the charge pump. The capacitor charges for as long as the STROBE input is High or until the capacitor voltage reaches the peak voltage at the full wave rectifier output. On the falling edge of the STROBE signal, the internal counter is incremented. The next 3 STROBE pulses will charge the B, C, and D, hold capacitors respectively. After the falling edge of the fourth strobe, the counter is reset to zero and the burst capture can be repeated. The counter is also reset when the RESET

The voltage level on each hold capacitor is amplified by a factor of

3.33 and summed with a 0.27V DC reference to create the A, B, C, and D output signals. A 1.40 Vppd voltage at the DP/DN nodes will result in 1.40 * 0.6 * 3.33 = 2.80V peak burst amplitude (i.e., servo gain = 2.0). The MAXREF output pin is a nominal 3.2V and is internally divided by 12 to create the DC baseline of 0.27V .

Either the normal or differentiated filter output may be selected for full wave rectification for servo capture. If the Servo Mode Select (SMS) bit in the Data Rate Register is 0 then the normal filter outputs are used and if it is a 1, the differentiated filter outputs are used. If the differentiated output is selected, the polarity of the RDS/RDS negative true. The magnitude of the captured voltage on the burst hold capacitors is governed by setting of the 2-bit servo AGC DAC. The AGC voltage can be programmed from 1.10 to 1.40 Vppd.

All four of the internal hold capacitors are discharged when the RESET

input is driven Low. The RESET input overrides the

STROBE signal. STROBE and RESET The maximum charge pump current can be selected as 40, 80, 120

or 160 µA by setting the servo burst charge current (SBCC) bits in the Data Level Threshold register. The “Soft Landing” technique reduces the charge pump current as the error between the voltage on the hold capacitor and the full wave rectifier output becomes smaller. This reduces the possibility of overcharging the capacitor during the comparator’s propagation delay period.

A small leakage current is applied to the capacitor being charged during each strobe period to make the captured voltage less sensitive to noise and strobe timing. The magnitude of this current is 1/450 of the charge current.

input transitions Low.

pulse will be positive true, otherwise RDS/RDS is

input pins. In addition to the A, B, C, D

are not gated with SG.

1997 JuL 15

+ 41 hidden pages