Page 1
LA
18941_000_100917.eps
100928
Q551.1L
310431364512 SSB Layout 159
310431364513 SSB Layout 163
J1 310431364342 IR Board Monet 177
J1 310431364821 IR Board Rubens 178
Monet 40" - 46" 179
11. Styling Sheets
2010-Oct-01
Rubens 58" 180
Color Television Chassis
Contents Page Contents Page
72 76
Wiring diagram Monet 40" - 46" 200 Hz 65
Wiring Diagram Rubens 58" 66
Block Diagram Video 67
Block Diagram Audio 68
Block Diagram Control & Clock Signals 69
1. Revision List 2
2. Technical Specifications, and Connections 2
3. Precautions, Notes, and Abbreviation List 5
4. Mechanical Instructions 9
5. Service Modes, Error Codes, and Fault Finding 16
6. Alignments 35
7. Circuit Descriptions 41
8. IC Data Sheets 55
9. Block Diagrams
Block Diagram I2C 70
Supply Lines Overview 71
10. Circuit Diagrams and PWB Layouts Drawing PWB
AL1 820400089786 AmbiLight Common
AL2 820400089703 15 LED LiteOn 74 76
AL1 820400090592 AmbiLight Common 77 81
AL2 820400090621 15 LED Everlight 79 81
B01 820400090812 Tuner, HDMI & CI 82
B01 820400090813 Tuner, HDMI & CI 93
B02 820400090822 PNX85500 104
B02 820400090823 PNX85500 113
B03 820400090892 CLASS D 122
B03 820400090893 CLASS D 130
B04 820400090832 Analog I/O 138
B04 820400090833 Analog I/O 143
B05 820400089535 DDR 148
B06 820400090922 LVDS DVBS 149
B06 820400090923 LVDS DVBS 153
B09 820400090902 Connector Board 157
SRP List Explanation 158
Copyright 2010 Koninklijke Philips Electronics N.V.
©
photocopying, or otherwise without the prior permission of Philips.
Published by ER-MB/EL 1069 BU TV Consumer Care, the Netherlands Subject to modification EN 3122 785 18941
All rights reserved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted, in any form or by any means, electronic, mechanical,
Page 2
.
BBxx (C-balance board)
B14 (TCON-SHP)
B13 (Ambilight)
• All chapters: added CTNs to the manual, see Table 2-1
Revision List
.
• Chapter 5: added section 5.8.3 AV PIP
You can download this information from the following websites:
http://www.philips.com/support
http://www.p4c.philips.com
2.1 Directions for Use
2.2 Technical Specifications
started, user manuals, frequently asked questions and
software & drivers.
For on-line product support please use the CTN links in Table
2-1. Here is product information available, as well as getting
Schematics
Mecha-
nics Descriptions
SSB 2 4 7 9 10
B11 (TCON-LGD)
B09 (non-DVBS-conn.)
B08 (DVBS-Supp.)
B07 (DVBS-FE)
--10-18 ----
- - 10-18 - - - 10-22
B06 (non-DVBS-LVDS)
10-17
10-15 10-16
10-13
10-11
10-9
10-7
10-4 10-5
2.3 4-1 4.4 7.2 7.5.2 7.10 - 9-1 10-1
64512
10-17
10-15 10-16
10-14
10-13
10-14
10-12
10-11
10-12
10-10
10-9
10-10
10-8
10-7
10-8
10-4
10-5
10-2
10-2
2.3 4-1 4.5 7.2 7.5.2 7.10 - 9-2 10-1
64513
64512
64513
B05 (DDR)
B04 (I/O)
B03 (DC/DC / Class D)
B02 (PNX85500)
B01 (Tuner)
ALxx (Ambilight) Everlight
ALxx (Ambilight) LiteOn
Wiring Diagram
TCON
AmbiLight
Tuner
PSU
Assembly Removal
Wire Dressing
Connection Overview
3104 313 xxxxx
back to
div. table
Manual xxxx xxx xxxx.0
• First release.
EN 2 Q551.1L LA1.
1. Revision List
Manual xxxx xxx xxxx.1
11-1
CTN Styling
Index of this chapter:
2.1 Directions for Use
2.2 Technical Specifications
2.3 Connections
2.4 Chassis Overview
Notes:
• Figures can deviate due to the different set executions.
• Specifications are indicative (subject to change).
Table 2-1 Described Model Numbers and Diversity
40PFL9605D/78 Monet
2. Technical Specifications, and Connections
11-2
58PFL9955D/78 Rubens
2010-Oct-01
Page 3
EN 3Q551.1L LA 2.
18940_001_100811.eps
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7
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4
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090121
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Technical Specifications, and Connections
/ 75 ohm jq
PP
/ 75 ohm jq
/ 75 ohm jq
PP
PP
/ 10 kohm jq
/ 10 kohm jq
RMS
RMS
Figure 2-4 Ethernet connector
12 - CLK- Data channel j
13 - Easylink/CEC Control channel jk
14 - n.c.
15 - DDC_SCL DDC clock j
16 - DDC_SDA DDC data jk
17 - Ground Gnd H
18 - +5V j
19 - HPD Hot Plug Detect j
20 - Ground Gnd H
3 - RJ45: Ethernet (optional)
1 -TD+ Transmit signal k
2 - TD- Transmit signal k
3 - RD+ Receive signal j
4 - CT Centre Tap: DC level fixation
5 - CT Centre Tap: DC level fixation
6 - RD- Receive signal j
7 - GND Gnd H
8 - GND Gnd H
4 - CVI2: Cinch: Video YPbPr - In, Audio - In
Gn -Video Y 1 V
Bu - Video Pb 0.7 V
Rd - Video Pr 0.7 V
Rd - Audio - R 0.5 V
Wh - Audio - L 0.5 V
2.3.2 Rear Connections
back to
div. table
Figure 2-1 Connection overview
2.3 Connections
Note: The following connector color abbreviations are used
(acc. to DIN/IEC 757): Bk= Black, Bu= Blue, Gn= Green, Gy=
Grey, Rd= Red, Wh= White, Ye= Yellow.
1 - USB2.0
2.3.1 Side Connections
Figure 2-2 USB (type A)
1-+5V k
2 -Data (-) jk
3 -Data (+) jk
4 -Ground Gnd H
2 - HDMI: Digital Video, Digital Audio - In
Figure 2-3 HDMI (type A) connector
1 -D2+ Data channel j
2 -Shield Gnd H
3 -D2- Data channel j
4 -D1+ Data channel j
5 -Shield Gnd H
6 -D1- Data channel j
7 -D0+ Data channel j
8 -Shield Gnd H
9 -D0- Data channel j
10 - CLK+ Data channel j
11 - Shield Gnd H
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11
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090127
PP
/ 75 ohm j
PP
/ 75 ohm j
PP
10 - CLK+ Data channel j
11 - Shield Gnd H
12 - CLK- Data channel j
13 - Easylink/CEC Control channel jk
14 - ARC Audio Return Channel k
15 - DDC_SCL DDC clock j
16 - DDC_SDA DDC data jk
Technical Specifications, and Connections
/ 75 ohm jq
PP
17 - Ground Gnd H
/ 10 kohm jq
RMS
18 - +5V j
/ 10 kohm jq
RMS
19 - HPD Hot Plug Detect j
Figure 2-6 VGA Connector
20 - Ground Gnd H
13 - 3D (optional)
1 - RXD-MIPS 3V3 level j
2 - 3D-VS 3V3 level k
3 - GND Ground H
4 - +5V supply j
5 - TXD-MIPS 3V3 level k
6 - 3D-LR 3V3 level k
14 - Aerial - In
- - IEC-type (EU) Coax, 75 ohm D
15 - VGA: Video RGB - In
1 - Video Red 0.7 V
2 - Video Green 0.7 V
3 - Video Blue 0.7 V
4-n.c.
5 - Ground Gnd H
6 - Ground Red Gnd H
+5 V j
DC
10 - Ground Sync Gnd H
11 - n.c.
12 - DDC_SDA DDC data j
13 - H-sync 0 - 5 V j
14 - V-sync 0 - 5 V j
7 - Ground Green Gnd H
8 - Ground Blue Gnd H
9-+5V
15 - DDC_SCL DDC clock j
back to
div. table
/ 75 ohm kq
/ 10 kohm jo
/ 10 kohm jo
RMS
RMS
PP
EN 4 Q551.1L LA2.
Figure 2-5 HDMI (type A) connector
Wh - Audio L 0.5 V
Rd - Audio R 0.5 V
7 - Mini Jack: Audio - In (VGA/DVI)
5 - Service Connector (UART)
1 - Ground Gnd H
2 - UART_TX Transmit k
3 - UART_RX Receive j
6 - Cinch: Video CVBS - In, Audio - In
Ye - Video CVBS 1 V
Wh - Audio L 0.5 V
Rd - Audio R 0.5 V
8 - Head phone (Output)
Bk - Head phone 32 - 600 ohm / 10 mW ot
10 - Cinch: S/PDIF - Out
Bk - Coaxial 0.4 - 0.6V
9 - CVI1: Cinch: Video YPbPr - In, Audio - In
See 4 - CVI2: Cinch: Video YPbPr - In, Audio - In
11 - HDMI 2 & 3: Digital Video, Digital Audio - In
2.3.3 Bottom Connections
12 - HDMI 1: Digital Video - In, Digital Audio with ARC - In/
See 2 - HDMI: Digital Video, Digital Audio - In
Out
1 - D2+ Data channel j
2 - Shield Gnd H
3 - D2- Data channel j
4 - D1+ Data channel j
5 - Shield Gnd H
6 - D1- Data channel j
7 - D0+ Data channel j
8 - Shield Gnd H
9 - D0- Data channel j
2.4 Chassis Overview
Refer to chapter Block Diagrams for PWB/CBA locations.
2010-Oct-01
Page 5
EN 5Q551.1L LA 3.
with (D) and without (E) aerial signal. Measure the
voltages in the power supply section both in normal
• Where necessary, measure the waveforms and voltages
operation (G) and in stand-by (F). These values are
indicated by means of the appropriate symbols.
• All resistor values are in ohms, and the value multiplier is
),
-6
often used to indicate the decimal point location (e.g. 2K2
indicates 2.2 k:).
either an “E” or an “R” (e.g. 220E or 220R indicates 220 :).
• Resistor values with no multiplier may be indicated with
• All capacitor values are given in micro-farads (P u10
).
-12
), or pico-farads (p u10
-9
nano-farads (n u10
decimal point indication (e.g. 2p2 indicates 2.2 pF).
to the diversity tables for the correct values.
Spare Parts Web Portal.
• Capacitor values may also use the value multiplier as the
• An “asterisk” (*) indicates component usage varies. Refer
• The correct component values are listed on the Philips
For the latest spare part overview, consult your Philips Spare
Part web portal.
. Select
Introduction
For more information on how to handle BGA devices, visit this
URL: http://www.atyourservice-magazine.com
“Magazine”, then go to “Repair downloads”. Here you will find
Information on how to deal with BGA-ICs.
BGA Temperature Profiles
Where applicable and available, this profile is added to the IC
For BGA-ICs, you must use the correct temperature-profile.
Data Sheet information section in this manual.
required, please contact the manufacturer of your soldering
equipment. In general, use of solder paste within
Due to lead-free technology some rules have to be respected
by the workshop during a repair:
• Use only lead-free soldering tin. If lead-free solder paste is
workshops should be avoided because paste is not easy to
store and to handle.
• Use only adequate solder tools applicable for lead-free
soldering tin. The solder tool must be able:
– To reach a solder-tip temperature of at least 400°C.
– To stabilize the adjusted temperature at the solder-tip.
– To exchange solder-tips for different applications.
360°C - 380°C is reached and stabilized at the solder joint.
• Adjust your solder tool so that a temperature of around
Heating time of the solder-joint should not exceed ~ 4 sec.
Avoid temperatures above 400°C, otherwise wear-out of
tips will increase drastically and flux-fluid will be destroyed.
2010-Oct-01
To avoid wear-out of tips, switch “off” unused equipment or
reduce heat.
tin/parts is possible but PHILIPS recommends strongly to
avoid mixed regimes. If this cannot be avoided, carefully
clear the solder-joint from old tin and re-solder with new tin.
• Mix of lead-free soldering tin/parts with leaded soldering
It should be noted that on the European Service website,
“Alternative BOM” is referred to as “Design variant”.
3.3.2 Schematic Notes
Precautions, Notes, and Abbreviation List
transformer (> 800 VA).
only by components identical to the original ones. Any
other component substitution (other than original type) may
increase risk of fire or electrical shock hazard.
Index of this chapter:
3.1 Safety Instructions
3.2 Warnings
3.3 Notes
3.4 Abbreviation List
3. Precautions, Notes, and Abbreviation List
3.1 Safety Instructions
Safety regulations require the following during a repair:
• Connect the set to the Mains/AC Power via an isolation
• Replace safety components, indicated by the symbol h,
Safety regulations require that after a repair, the set must be
mounted cable clamps.
returned in its original condition. Pay in particular attention to
the following points:
• Route the wire trees correctly and fix them with the
• Check the insulation of the Mains/AC Power lead for
3.3.3 Spare Parts
external damage.
proper function.
• Check the strain relief of the Mains/AC Power cord for
3.3.4 BGA (Ball Grid Array) ICs
Power plug and the secondary side (only for sets that have
a Mains/AC Power isolated power supply):
1. Unplug the Mains/AC Power cord and connect a wire
• Check the electrical DC resistance between the Mains/AC
3.3.5 Lead-free Soldering
between the two pins of the Mains/AC Power plug.
(keep the Mains/AC Power cord unplugged!).
Mains/AC Power plug and the metal shielding of the
tuner or the aerial connection on the set. The reading
should be between 4.5 M: and 12 M:.
two pins of the Mains/AC Power plug.
2. Set the Mains/AC Power switch to the “on” position
3. Measure the resistance value between the pins of the
4. Switch “off” the set, and remove the wire between the
inner parts by the customer.
• Check the cabinet for defects, to prevent touching of any
3.2 Warnings
during repair can reduce life drastically. Make sure that,
during repair, you are connected with the same potential as
electrostatic discharges (ESD w). Careless handling
• All ICs and many other semiconductors are susceptible to
the mass of the set by a wristband with resistance. Keep
components and tools also at this same potential.
section.
is switched “on”.
• Be careful during measurements in the high voltage
• Never replace modules or other components while the unit
This will prevent any short circuits and the danger of a
circuit becoming unstable.
• When you align the set, use plastic rather than metal tools.
3.3 Notes
3.3.1 General
chassis (= tuner) ground (H), or hot ground (I), depending
on the tested area of circuitry. The voltages and waveforms
• Measure the voltages and waveforms with regard to the
3.3.6 Alternative BOM identification
back to
div. table
shown in the diagrams are indicative. Measure them in the
Service Default Mode with a colour bar signal and stereo
sound (L: 3 kHz, R: 1 kHz unless stated otherwise) and
picture carrier at 475.25 MHz for PAL, or 61.25 MHz for
NTSC (channel 3).
Page 6
board. 0 = loop through (AUX to TV),
6 = play 16 : 9 format, 12 = play 4 : 3
format
algorithm that adapts aspect ratio to
remove horizontal black bars; keeps
the original aspect ratio
algorithm that installs TV channels
directly from a cable network by
means of a predefined TXT page
signal used to tune to the correct
frequency
controls the video input of the feature
box
aspect ratio to remove horizontal black
bars without discarding video
information
Committee, the digital TV standard in
the USA
system that measures picture content,
and adapts image parameters in a
dynamic way
carrier distance is 5.5 MHz
Committee. Multiplex FM stereo sound
system, originating from the USA and
used e.g. in LATAM and AP-NTSC
countries
remote control bus on HDMI
connections
connect with an external amplifier
manipulates steepness of chroma
transients
Synchronization
low frequency amplification
referred to as System Card or
Smartcard (for iTV).
carrier distance is 6.5 MHz
0/6/12 SCART switch control signal on A/V
3.4 Abbreviation List
Precautions, Notes, and Abbreviation List
The third digit in the serial number (example:
AG2B0335000001) indicates the number of the alternative
B.O.M. (Bill Of Materials) that has been used for producing the
specific TV set. In general, it is possible that the same TV
AARA Automatic Aspect Ratio Adaptation:
model on the market is produced with e.g. two different types
of displays, coming from two different suppliers. This will then
result in sets which have the same CTN (Commercial Type
Number; e.g. 28PW9515/12) but which have a different B.O.M.
number.
By looking at the third digit of the serial number, one can
ACI Automatic Channel Installation:
identify which B.O.M. is used for the TV set he is working with.
If the third digit of the serial number contains the number “1”
ADC Analogue to Digital Converter
AFC Automatic Frequency Control: control
(example: AG1B033500001), then the TV set has been
manufactured according to B.O.M. number 1. If the third digit is
a “2” (example: AG2B0335000001), then the set has been
produced according to B.O.M. no. 2. This is important for
ordering the correct spare parts!
For the third digit, the numbers 1...9 and the characters A...Z
AGC Automatic Gain Control: algorithm that
can be used, so in total: 9 plus 26= 35 different B.O.M.s can be
AM Amplitude Modulation
AP Asia Pacific
AR Aspect Ratio: 4 by 3 or 16 by 9
ASF Auto Screen Fit: algorithm that adapts
indicated by the third digit of the serial number.
Identification: The bottom line of a type plate gives a 14-digit
serial number. Digits 1 and 2 refer to the production centre (e.g.
AG is Bruges), digit 3 refers to the B.O.M. code, digit 4 refers
to the Service version change code, digits 5 and 6 refer to the
production year, and digits 7 and 8 refer to production week (in
ATSC Advanced Television Systems
MADE IN BELGIUM
example below it is 2006 week 17). The 6 last digits contain the
serial number.
ATV See Auto TV
128W
~
220-240V 50/60Hz
32PF9968/10
MODEL :
Auto TV A hardware and software control
BJ3.0E LA
S
VHF+S+H+UHF
AG 1A0617 000001
PROD.NO:
AV External Audio Video
AVC Audio Video Controller
100105
10000_024_090121.eps
AVIP Audio Video Input Processor
B/G Monochrome TV system. Sound
BDS Business Display Solutions (iTV)
BLR Board-Level Repair
BTSC Broadcast Television Standard
Figure 3-1 Serial number (example)
(CLR)
If a board is defective, consult your repair procedure to decide
if the board has to be exchanged or if it should be repaired on
component level.
If your repair procedure says the board should be exchanged
B-TXT Blue TeleteXT
C Centre channel (audio)
CEC Consumer Electronics Control bus:
completely, do not solder on the defective board. Otherwise, it
cannot be returned to the O.E.M. supplier for back charging!
CL Constant Level: audio output to
CLR Component Level Repair
ComPair Computer aided rePair
CP Connected Planet / Copy Protection
CSM Customer Service Mode
CTI Color Transient Improvement:
While some sources are expected to have a possible
dangerous impact, others of quite high potential are of
limited current and are sometimes held in less regard.
dangerous in themselves, they can cause unexpected
reactions that are best avoided. Before reaching into a
powered TV set, it is best to test the high voltage insulation.
• It makes sense to avoid exposure to electrical shock.
• Always respect voltages. While some may not be
CVBS Composite Video Blanking and
DAC Digital to Analogue Converter
DBE Dynamic Bass Enhancement: extra
DCM Data Communication Module. Also
It is easy to do, and is a good service precaution.
DDC See “E-DDC”
D/K Monochrome TV system. Sound
DFI Dynamic Frame Insertion
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div. table
EN 6 Q551.1L LA3.
3.3.7 Board Level Repair (BLR) or Component Level Repair
3.3.8 Practical Service Precautions
2010-Oct-01
Page 7
EN 7Q551.1L LA 3.
SDI), is a digitized video format used
for broadcast grade video.
Uncompressed digital component or
digital composite signals can be used.
The SDI signal is self-synchronizing,
uses 8 bit or 10 bit data words, and has
a maximum data rate of 270 Mbit/s,
with a minimum bandwidth of 135
MHz.
ITV Institutional TeleVision; TV sets for
hotels, hospitals etc.
by the customer and read and stored
in RAM or in the NVM. They are called
at start-up of the set to configure it
according to the customer's
preferences
LS Last Status; The settings last chosen
LATAM Latin America
LCD Liquid Crystal Display
carrier distance is 6.5 MHz. L' is Band
LED Light Emitting Diode
L/L' Monochrome TV system. Sound
I, L is all bands except for Band I
LPL LG.Philips LCD (supplier)
LS Loudspeaker
carrier distance is 4.5 MHz
related to the presentation of
LVDS Low Voltage Differential Signalling
Mbps Mega bits per second
M/N Monochrome TV system. Sound
MHEG Part of a set of international standards
multimedia information, standardised
by the Multimedia and Hypermedia
Experts Group. It is commonly used as
a language to describe interactive
television services
Pipeline-Stages; A RISC-based
microprocessor
Transistor, switching device
MIPS Microprocessor without Interlocked
MOP Matrix Output Processor
MOSFET Metal Oxide Silicon Field Effect
MPEG Motion Pictures Experts Group
MPIF Multi Platform InterFace
Consumer TV features enabled (iTV)
MUTE MUTE Line
MTV Mainstream TV: TV-mode with
Audio Multiplexing. This is a digital
NC Not Connected
NICAM Near Instantaneous Compounded
sound system, mainly used in Europe.
non-linear resistor
Committee. Color system mainly used
NTC Negative Temperature Coefficient,
NTSC National Television Standard
in North America and Japan. Color
carrier NTSC M/N= 3.579545 MHz,
NTSC 4.43= 4.433619 MHz (this is a
VCR norm, it is not transmitted off-air)
TV related data such as alignments
NVM Non-Volatile Memory: IC containing
O/C Open Circuit
software upgrade via RF transmission.
OSD On Screen Display
OAD Over the Air Download. Method of
Upgrade software is broadcasted in
TS with TV channels.
Control; also called Artistic (SAA5800)
between TV and peripherals
OTC On screen display Teletext and
P50 Project 50: communication protocol
2010-Oct-01
mainly used in West Europe (color
carrier= 4.433619 MHz) and South
America (color carrier PAL M=
PAL Phase Alternating Line. Color system
back to
div. table
Precautions, Notes, and Abbreviation List
reduction feature of the set
DFU Directions For Use: owner's manual
DMR Digital Media Reader: card reader
DMSD Digital Multi Standard Decoding
DNM Digital Natural Motion
DNR Digital Noise Reduction: noise
DRAM Dynamic RAM
control designed for service
DRM Digital Rights Management
DSP Digital Signal Processing
DST Dealer Service Tool: special remote
technicians
Protection; A protocol for protecting
digital audio/video content that is
DTCP Digital Transmission Content
traversing a high speed serial bus,
such as IEEE-1394
DVB-C Digital Video Broadcast - Cable
DVB-T Digital Video Broadcast - Terrestrial
DVD Digital Versatile Disc
DVI(-d) Digital Visual Interface (d= digital only)
E-DDC Enhanced Display Data Channel
(VESA standard for communication
channel and display). Using E-DDC,
the video source can read the EDID
information form the display.
(VESA standard)
EDID Extended Display Identification Data
EEPROM Electrically Erasable and
Programmable Read Only Memory
EMI Electro Magnetic Interference
EPG Electronic Program Guide
EPLD Erasable Programmable Logic Device
EU Europe
EXT EXTernal (source), entering the set by
SCART or by cinches (jacks)
FDS Full Dual Screen (same as FDW)
FDW Full Dual Window (same as FDS)
FLASH FLASH memory
Modulation
FM Field Memory or Frequency
FPGA Field-Programmable Gate Array
FTV Flat TeleVision
Gb/s Giga bits per second
G-TXT Green TeleteXT
H H_sync to the module
HD High Definition
HDD Hard Disk Drive
Protection: A “key” encoded into the
HDMI/DVI signal that prevents video
data piracy. If a source is HDCP coded
HDCP High-bandwidth Digital Content
and connected via HDMI/DVI without
the proper HDCP decoding, the
picture is put into a “snow vision” mode
or changed to a low resolution. For
normal content distribution the source
and the display device must be
enabled for HDCP “software key”
decoding.
HDMI High Definition Multimedia Interface
carrier distance is 6.0 MHz
HP HeadPhone
I Monochrome TV system. Sound
2
C Inter IC bus
I
2
D Inter IC Data bus
S Inter IC Sound bus
2
I
I
IF Intermediate Frequency
(ITU-R) is a standards body
subcommittee of the International
IR Infra Red
IRQ Interrupt Request
ITU-656 The ITU Radio communication Sector
Telecommunication Union relating to
radio communication. ITU-656 (a.k.a.
Page 8
SVHS Super Video Home System
Precautions, Notes, and Abbreviation List
3.575612 MHz and PAL N= 3.582056
Noise reduction
SW Software
SWAN Spatial temporal Weighted Averaging
SXGA 1280 × 1024
TFT Thin Film Transistor
THD Total Harmonic Distortion
MHz)
conditioner)
Signalling
TMDS Transmission Minimized Differential
TS Transport Stream
FST tuning systems. The customer
TXT TeleteXT
can give directly the desired frequency
TXT-DW Dual Window with TeleteXT
UI User Interface
uP Microprocessor
UXGA 1 600 × 1 200 (4:3)
V V-sync to the module
CAM module, implementing the CA
system for a host (e.g. a TV-set)
Association
VESA Video Electronics Standards
backlight with 2D-dimming
output toward external amplifier
method
record selection that follows main
picture and sound
VGA 640 × 480 (4:3)
VL Variable Level out: processed audio
VSB Vestigial Side Band; modulation
WYSIWYR What You See Is What You Record:
drivers
drivers with added Scanning
functionality
non-linear resistor
WXGA 1280 × 768 (15:9)
XTAL Quartz crystal
XGA 1024 × 768 (4:3)
signal
scaled color difference signals (B-Y
and R-Y)
Y Luminance signal
Y/C Luminance (Y) and Chrominance (C)
YPbPr Component video. Luminance and
color signals for TV. By mixing levels
of R, G, and B, all colors (Y/C) are
reproduced.
YUV Component video
back to
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C bus
2
C
2
control receiver
data interface
d'Appareils Radiorécepteurs et
Téléviseurs
C bus
2
C
2
Color system mainly used in France
and East Europe. Color carriers=
4.406250 MHz and 4.250000 MHz
wire synchronous serial data link
standard
reduce the effects of EMI
EN 8 Q551.1L LA3.
PCB Printed Circuit Board (same as “PWB”)
PCM Pulse Code Modulation
PDP Plasma Display Panel
PFC Power Factor Corrector (or Pre-
PIP Picture In Picture
PLL Phase Locked Loop. Used for e.g.
POD Point Of Deployment: a removable
POR Power On Reset, signal to reset the uP
PSDL Power Supply for Direct view LED
PSL Power Supply with integrated LED
PSLS Power Supply with integrated LED
PTC Positive Temperature Coefficient,
PWB Printed Wiring Board (same as “PCB”)
PWM Pulse Width Modulation
QRC Quasi Resonant Converter
QTNR Quality Temporal Noise Reduction
QVCP Quality Video Composition Processor
RAM Random Access Memory
RGB Red, Green, and Blue. The primary
RC Remote Control
RC5 / RC6 Signal protocol from the remote
RESET RESET signal
ROM Read Only Memory
RSDS Reduced Swing Differential Signalling
R-TXT Red TeleteXT
SAM Service Alignment Mode
S/C Short Circuit
SCART Syndicat des Constructeurs
SCL Serial Clock I
SDA-F DAta Signal on Fast I
SCL-F CLock Signal on Fast I
SDI Serial Digital Interface, see “ITU-656”
SD Standard Definition
SDA Serial Data I
SDRAM Synchronous DRAM
SECAM SEequence Couleur Avec Mémoire.
SIF Sound Intermediate Frequency
SMPS Switched Mode Power Supply
SoC System on Chip
SOG Sync On Green
SOPS Self Oscillating Power Supply
SPI Serial Peripheral Interface bus; a 4-
S/PDIF Sony Philips Digital InterFace
SRAM Static RAM
SRP Service Reference Protocol
SSB Small Signal Board
SSC Spread Spectrum Clocking, used to
STB Set Top Box
STBY STand-BY
SVGA 800 × 600 (4:3)
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Mechanical Instructions
2010-Oct-01
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due to the different set executions.
Index of this chapter:
4.1 Cable Dressing Monet Styling (9605-series)
4.2 Cable Dressing Rubens 21:9 Styling (9955-series)
4.3 Service Positions
4.4 Assy/Panel Removal Monet Styling
4.5 Assy/Panel Removal Rubens 21:9 Styling
4.6 Set Re-assembly
Notes:
• Figures below can deviate slightly from the actual situation,
4. Mechanical Instructions
4.1 Cable Dressing Monet Styling (9605-series)
Figure 4-1 Cable dressing 9605-series (Monet styling)
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2
2
2
2
2
1
1
Mechanical Instructions
for details.
for details.
Figure 4-3 Main Power Supply
1. Unplug all connectors [1].
2. Remove the fixation screws [2].
3. Take the board out.
Refer to Figure 4-3
When defective, replace the whole unit.
4.4.4 Main Power Supply
Figure 4-2 Cable dressing 9955-series (Rubens 21:9 styling)
4.4.5 Small Signal Board (SSB)
Refer to Figure 4-4
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flat coils are not damaged while lifting the rear cover from
the set.
The speakers are secured by two bosses.
For easy servicing of a TV set, the set should be put face down
on a soft flat surface, foam buffers or other specific workshop
tools. Ensure that a stable situation is created to perform
measurements and alignments. When using foam bars take
care that these always support the cabinet and never only the
display. Caution: Failure to follow these guidelines can
seriously damage the display!
Note: picture taken from European model with additional
panels.
EN 10 Q551.1L LA4.
4.2 Cable Dressing Rubens 21:9 Styling (9955-series)
4.3 Service Positions
Ensure that ESD safe measures are taken.
The instructions apply to the 37PFL8605K/02.
4.4 Assy/Panel Removal Monet Styling
4.4.1 Rear Cover
Warning: Disconnect the mains power cord before you remove
the rear cover.
1. Remove the stand.
2. Remove all screws of the rear cover.
3. Lift the rear cover from the TV. Make sure that wires and
4.4.2 Speakers
When defective, replace the whole unit.
The mains switch is mounted in the “leading edge” assy. Refer
4.4.3 Mains Switch
to the exploded view in Chapter 11.
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Figure 4-7 IR & LED board [2/2]
the stand support and take the board out.
The IR/LED board is placed inside the stand support (“leading
edge” assy).
1. Remove the screws [1].
2. Remove the screws [2] that secure the IR & LED board in
3. Unplug the connectors.
When defective, replace the whole unit.
4.4.8 Keyboard Control Board
for details.
stand support (“leading edge” assy) and cannot be swapped
When defective, replace the entire assy.
separately. Refer to section 4.4.7
The Keyboard Control Panel is constructed together with the
2010-Oct-01
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Mechanical Instructions
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Figure 4-4 SSB
for details.
and Figure 4-7 for details.
1
1
Figure 4-5 Ambilight units
Figure 4-6 IR & LED board [1/2]
1. Unplug all connectors [1].
2. Remove the fixation screws [2].
3. Slide the side cover sidewards [3].
4. Remove the screws [4].
5. Remove the bottom cover downwards [5].
4.4.6 Ambilight Units
Note: the Ambilight units are to be swapped on PWB level.
Refer to Figure 4-5
1. Unplug the flat foil(s) [1].
2. Release the clips [2] that secure the PWB.
3. Slide the PWB out of the set [3].
Refer to Figure 4-6
4.4.7 IR & LED Board
1 1
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The instructions apply to the 58PFL9955x/xx.
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Note: pictures taken from European model (with additional
panels).
Warning: Disconnect the mains power cord before you remove
the rear cover.
1. Remove the stand.
2. Remove all screws of the rear cover.
flat coils are not damaged while lifting the rear cover from
the set.
3. Lift the rear cover from the TV. Make sure that wires and
The speakers are mounted with four screws.
When defective, replace the whole units.
4.5 Assy/Panel Removal Rubens 21:9 Styling
4.5.1 Rear Cover
1
111 1
Mechanical Instructions
to Figure 4-10 for details.
1
Refer to Figure 4-8
EN 12 Q551.1L LA4.
4.4.9 LCD Panel
1
1
4.5.2 Speakers
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Figure 4-8 LCD board [1/2]
Figure 4-9 LCD board [2/2]
1. Remove all boards as described earlier.
2. Remove the stand support as described earlier.
3. Remove the tweeters as described earlier.
4. Remove the subwoofer as described earlier.
5. Remove all cables.
6. Remove the Vesa stand.
7. Remove the tweeter subframes.
8. Release the clips [1] [2] that secure the LCD panel.
Figure 4-10 LCD board -3-
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When remounting, ensure that the clips are not bent open!
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2010-Oct-01
1. Unplug all connectors [1].
2. Remove the fixation screws [2].
Refer to Figure 4-11 for details.
Mechanical Instructions
3. Take the board out.
When defective, replace the whole unit.
4.5.4 Small Signal Board (SSB)
for details.
Refer to Figure 4-12
Figure 4-12 SSB
1. Unplug all connectors [1].
2. Slide the side cover sidewards [2].
3. Remove the fixation screws [3].
4. Remove the bottom cover downwards [4].
Figure 4-11 Main Power Supply
Figure 4-13 Rim
.
for details.
aside, as shown in Figure 4-13
1. Remove the speaker fiaxtion screws and put the speakers
Refer to Figure 4-13
it out.
2. Release the tape [1].
3. Remove the screws [2] that secure the plastic rim and take
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4.5.3 Main Power Supply
4.5.5 AmbiLight reflector rim
Page 14
for details.
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Figure 4-17 LCD panel
1. Remove the rim as described earlier.
2. Remove the fixation screws [1].
3. Remove the connectors [2] on the board.
Mechanical Instructions
for details.
Refer to Figure 4-14
EN 14 Q551.1L LA4.
4.5.6 Ambilight Units
holder.
4. Release the clips [3] that secures the board to it’s plastic
When defective, replace the whole unit.
Note: the Ambilight units are to be swapped on PWB level.
4.5.10 LCD Panel
Refer to Figure 4-17
Figure 4-14 Ambilight units
1. Remove the rim as described earlier.
2. Unplug the flat foil(s) [1].
3. Release the clips [2] that secure the PWB.
shown in the picture.
1. Remove all boards as described earlier.
2. Remove the speakers as described earlier.
3. Disconnect the Ambilight flat foils as described earlier.
4. Remove the plastic rim as described earlier.
5. Tilt the metal rims [1] on top and both sides of the set as
Now the LCD Panel can be lifted from the front cabinet.
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for details.
Figure 4-15 C-balancer board
4. Slide the PWB out of the set [3].
1. Remove the IR/LED panel as described earlier.
4.5.7 Keyboard Control Board
2. Remove the plastic rim as described earlier.
The Keyboard Control Panel is constructed together with the
stand support (“leading edge” assembly) and cannot be
swapped separately.
When defective, replace the whole assembly.
4.5.8 C-balancer Board
Refer to Figure 4-15
1. Unplug all connectors [1].
2. Remove the screws [2].
3. Take the board out.
When defective, replace the whole unit.
4.5.9 IR/LED Board
for details.
Figure 4-16 IR & LED Board
Refer to Figure 4-16
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EN 15Q551.1L LA 4.
Mechanical Instructions
2010-Oct-01
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and connected in their original position.
set. Ensure that EMC foams are mounted correctly.
To re-assemble the whole set, execute all processes in reverse
order.
Notes:
• While re-assembling, make sure that all cables are placed
• Pay special attention not to damage the EMC foams in the
4.6 Set Re-assembly
Page 16
– (Sleep) timer.
18770_249_100215.eps
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SDM
– Child/parental lock.
– Picture mute (blue mute or black mute).
– Automatic volume levelling (AVL).
– Skip/blank of non-favorite pre-sets.
How to Activate SDM
• All service-unfriendly modes (if present) are disabled, like:
For this chassis there are two kinds of SDM: an analogue SDM
.
in the code “062596”, directly followed by the “MENU” (or
“HOME”) button.
and a digital SDM. Tuning will happen according Table 5-1
• Analogue SDM: use the standard RC-transmitter and key
).
Note: It is possible that, together with the SDM, the main
menu will appear. To switch it “off”, push the “MENU” (or
"HOME") button again.
Analogue SDM can also be activated by grounding for a
moment the solder path on the SSB, with the indication
“SDM” (see Service mode pad
• Digital SDM: use the standard RC-transmitter and key in
the code “062593”, directly followed by the “MENU” (or
"HOME") button.
Note: It is possible that, together with the SDM, the main
menu will appear. To switch it “off”, push the “MENU” (or
"HOME") button again.
Figure 5-1 Service mode pad
”).
After activating this mode, “SDM” will appear in the upper right
corner of the screen (when a picture is available).
How to Navigate
When the “MENU” (or “HOME”) button is pressed on the RC
transmitter, the TV set will toggle between the SDM and the
normal user menu.
How to Exit SDM
Use one of the following methods:
sequence.
• Switch the set to STAND-BY via the RC-transmitter.
• Via a standard customer RC-transmitter: key in “00”-
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Service Modes, Error Codes, and Fault Finding
Index of this chapter:
5.1 Test Points
5.2 Service Modes
5.3 Stepwise Start-up
5.4 Service Tools
5.5 Error Codes
5.6 The Blinking LED Procedure
5.7 Protections
5.8 Fault Finding and Repair Tips
5.9 Software Upgrading
EN 16 Q551.1L LA5.
5. Service Modes, Error Codes, and Fault Finding
As most signals are digital, it will be difficult to measure
5.1 Test Points
waveforms with a standard oscilloscope. However, several key
ICs are capable of generating test patterns, which can be
controlled via ComPair. In this way it is possible to determine
which part is defective.
Perform measurements under the following conditions:
• Service Default Mode.
• Video: Color bar signal.
• Audio: 3 kHz left, 1 kHz right.
5.2 Service Modes
Service Default mode (SDM) and Service Alignment Mode
(SAM) offers several features for the service technician, while
the Customer Service Mode (CSM) is used for communication
between the call centre and the customer.
This chassis also offers the option of using ComPair, a
hardware interface between a computer and the TV chassis. It
offers the abilities of structured troubleshooting, error code
”).
reading, and software version read-out for all chassis.
(see also section “5.4.1 ComPair
Purpose
Note: For the new model range, a new remote control (RC) is
used with some renamed buttons. This has an impact on the
activation of the Service modes. For instance the old “MENU”
button is now called “HOME” (or is indicated by a “house” icon).
5.2.1 Service Default Mode (SDM)
• To create a pre-defined setting, to get the same
measurement results as given in this manual.
• To override SW protections detected by stand-by
”.
processor and make the TV start up to the step just before
protection (a sort of automatic stepwise start-up). See
section “5.3 Stepwise Start-up
errors are displayed. (see also section “5.5 Error Codes
Specifications
• To start the blinking LED procedure where only LAYER 2
Table 5-1 SDM default settings
Default
system
Region Freq. (MHz)
Europe, AP(PAL/Multi) 475.25 PAL B/G
DVB-T
Video: 0B 06 PID
PCR: 0B 06 PID
Europe, AP DVB-T 546.00 PID
Audio: 0B 07
• All picture settings at 50% (brightness, color, contrast).
• Sound volume at 25%.
2010-Oct-01
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EN 17Q551.1L LA 5.
PHILIPS
MODEL:
32PF9968/10
PROD.SERIAL NO:
AG 1A0620 000001
040
39mm
27mm
(CTN Sticker)
Display Option
Code
E_06532_038.eps
240108
button and “XXX” (where XXX is the 3 digit decimal display
code as mentioned on the sticker in the set). Make sure to key
in all three digits, also the leading zero’s. If the above action is
successful, the front LED will go out as an indication that the
RC sequence was correct. After the display option is changed
in the NVM, the TV will go to the Stand-by mode. If the NVM
was corrupted or empty before this action, it will be initialized
first (loaded with default values). This initializing can take up to
2010-Oct-01
development department can ask for this info.
development department can ask for this info :
- Event 26: refers to a power dip, this is logged after
the TV set reboots due to a power dip.
- Event 17: refers to the power OK status, sensed even
before the 3 x retry to generate the error code.
when pressing “cursor right” (or the “OK” button) and then
the “OK”-button.
of operation hours of the screen itself. In case of a display
replacement, reset to “0” or to the consumed operation
hours of the spare display.
– SW Events. In case of specific software problems, the
– HW Events. In case of specific software problems, the
20 seconds.
• Store - go right. All options and alignments are stored
Figure 5-2 Location of Display Option Code sticker
• Operation hours display. Displays the accumulated total
• SW Maintenance.
purposes, this information is only used by the development
• Test settings. For development purposes only.
• Development file versions. Not useful for Service
department.
an USB stick, which is connected to the SSB. The items are
“Channel list”, “Personal settings”, “Option codes”,
“Alignments”, “Identification data” (includes the set type
and prod code + all 12NC like SSB, display, boards),
• Upload to USB. To upload several settings from the TV to
“History list”. The “All” item supports to upload all several
items at once.
First a directory “repair\” has to be created in the root
of the USB stick.
To upload the settings, select each item separately, press
“cursor right” (or the “OK” button), confirm with “OK” and
wait until the message “Done” appears. In case the
download to the USB stick was not successful, “Failure” will
be displayed. In this case, check if the USB stick is
connected properly and if the directory “repair” is present in
the root of the USB stick. Now the settings are stored onto
the USB stick and can be used to download into another TV
or other SSB. Uploading is of course only possible if the
software is running and preferably a picture is available.
This method is created to be able to save the customer’s
TV settings and to store them into another SSB.
the USB stick to the TV, same way of working needs to be
followed as described in “Upload to USB”. To make sure
• Download from USB. To download several settings from
that the download of the channel list from USB to the TV is
executed properly, it is necessary to restart the TV and
tune to a valid preset if necessary. The “All” item supports
to download all several items at once.
)
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for details.
Service Modes, Error Codes, and Fault Finding
5.2.2 Service Alignment Mode (SAM)
Purpose
• To perform (software) alignments.
• To change option settings.
• To easily identify the used software version.
• To view operation hours.
• To display (or clear) the error code buffer.
How to Activate SAM
Via a standard RC transmitter: Key in the code “062596”
directly followed by the “INFO” or “OK” button. After activating
SAM with this method a service warning will appear on the
.
)
.
”).
number (this is no longer the region indication, as
the software is now multi-region).
main version number (different numbers are not
compatible with one another) and Y.W.Z is the sub
version number (a higher number is always
compatible with a lower number).
the Service department an extra possibility for
diagnosis (e.g. when Development asks for this).
main software (example: Q555X-1.2.3.4 =
AAAAB_X.Y.W.Z).
• AAAA= the chassis name.
• B= the SW branch version. This is a sequential
• X.Y.W.Z= the software version, where X is the
– A. SW Version. Displays the software version of the
screen, continue by pressing the “OK” button on the RC.
Contents of SAM (see also Table 6-8
• Hardware Info.
version of the stand-by processor.
the TV, this is the serial number as printed on the back
of the TV set. Note that if an NVM is replaced or is
– B. STBY PROC Version. Displays the software
– C. Production Code. Displays the production code of
initialized after corruption, this production code has to
be re-written to NVM. ComPair will foresee in a
possibility to do this.
• Operation Hours. Displays the accumulated total of
operation hours (not the stand-by hours). Every time the
TV is switched “on/off”, 0.5 hours is added to this number.
error is displayed at the upper left (for an error explanation
see section “5.5 Error Codes
• Reset Error Buffer. When “cursor right” (or “OK” button)
• Errors (followed by maximum 10 errors). The most recent
pressed here, followed by the “OK” button, the error buffer
is reset.
menu. See Chapter 6. Alignments
• Alignments. This will activate the “ALIGNMENTS” sub-
Note that if the option code numbers are changed, these
have to be confirmed with pressing the “OK” button before
the options are stored, otherwise changes will be lost.
regarding option codes, 6. Alignments
• Dealer Options. Extra features for the dealers.
• Options. Extra features for Service. For more info
corrupted NVM, the “initialize NVM” line will be highlighted.
• Initialize NVM. The moment the processor recognizes a
development analysis, before initializing. This will give
Now, two things can be done (dependent of the service
instructions at that moment):
– Save the content of the NVM via ComPair for
– Initialize the NVM.
Note: When the NVM is corrupted, or replaced, there is a high
possibility that no picture appears because the display code is
not correct. So, before initializing the NVM via the SAM, a
picture is necessary and therefore the correct display option
has to be entered. Refer to Chapter 6. Alignments
To adapt this option, it’s advised to use ComPair (the correct
values for the options can be found in Chapter 6. Alignments
or a method via a standard RC (described below).
Changing the display option via a standard RC: Key in the
code “062598” directly followed by the “MENU” (or "HOME")
Page 18
How to Activate CSM Key in the code “123654” via the standard RC transmitter.
Service Modes, Error Codes, and Fault Finding
• NVM editor. For NET TV the set “type number” must be
Note: Activation of the CSM is only possible if there is no (user)
entered correctly.
Also the production code (AG code) can be entered here
via the RC-transmitter.
menu on the screen!
Correct data can be found on the side/rear sticker.
How to Navigate
By means of the “CURSOR-DOWN/UP” knob on the RC-
transmitter, can be navigated through the menus.
Contents of CSM
The contents are reduced to 3 pages: General, Software
versions and Quality items. The group names itself are not
“CURSOR UP/DOWN” key on the RC-transmitter. The
selected item will be highlighted. When not all menu items
fit on the screen, move the “CURSOR UP/DOWN” key to
display the next/previous menu items.
How to Navigate
• In SAM, the menu items can be selected with the
• With the “CURSOR LEFT/RIGHT” keys, it is possible to:
workshop as reference for further diagnosis. In this way, it
is not necessary for the customer to look at the rear of the
TV-set. Note that if an NVM is replaced or is initialized after
shown anywhere in the CSM menu.
General
• Set Type. This information is very helpful for a helpdesk/
– (De) activate the selected menu item.
– (De) activate the selected sub menu.
action.
• With the “OK” key, it is possible to activate the selected
How to Exit SAM
Use one of the following methods:
corruption, this set type has to be re-written to NVM.
ComPair will foresee in a possibility to do this. The update
can also be done via the NVM editor available in SAM.
number) of the TV. Note that if an NVM is replaced or is
initialized after corruption, this production code has to be
re-written to NVM. ComPair will foresee in a possibility to
do this. The update can also be done via the NVM editor
available in SAM.
• Production Code. Displays the production code (the serial
select the “BACK” key.
Purpose
When a customer is having problems with his TV-set, he can
• Switch the TV set to STAND-BY via the RC-transmitter.
• Via a standard RC-transmitter, key in “00” sequence, or
call his dealer or the Customer Helpdesk. The service
the TV. This date is acquired via time extraction.
in SAM (Service Alignment Mode).
in SAM (Service Alignment Mode).
NVM. Note that if an NVM is replaced or is initialized after
corruption, this identification number has to be re-written to
• Installed date. Indicates the date of the first installation of
• Options 1. Gives the option codes of option group 1 as set
• Options 2. Gives the option codes of option group 2 as set
• 12NC SSB. Gives an identification of the SSB as stored in
technician can then ask the customer to activate the CSM, in
order to identify the status of the set. Now, the service
technician can judge the severity of the complaint. In many
cases, he can advise the customer how to solve the problem,
or he can decide if it is necessary to visit the customer.
The CSM is a read only mode; therefore, modifications in this
mode are not possible.
When in this chassis CSM is activated, a test pattern will be
NVM. ComPair will foresee in a possibility to do this. This
identification number is the 12nc number of the SSB.
displayed during 5 seconds (1 second Blue, 1 second Green
and 1 second Red, then again 1 second Blue and 1 second
(when present).
present).
• 12NC display. Shows the 12NC of the display.
• 12NC supply. Shows the 12NC of the power supply.
• 12NC 200Hz board. Shows the 12NC of the 200Hz Panel
• 12NC AV PIP. Shows the 12NC of the AV PIP board (when
Green). This test pattern is generated by the PNX51X0
(located on the 200Hz board as part of the display). So if this
test pattern is shown, it could be determined that the back end
video chain (PNX51X0 and display) is working.For TV sets
without the PNX51X0 inside, every menu from CSM will be
used as check for the back end chain video. When CSM is activated and there is a USB stick connected to
version. In case of field problems related to software,
software can be upgraded. As this software is consumer
upgradeable, it will also be published on the Internet.
Example: Q55xx1.2.3.4
Software versions
• Current main SW. Displays the build-in main software
the TV set, the software will dump the CSM content to the USB
stick. The file (CSM_model number_serial number.txt) will be
• Stand-by SW. Displays the built-in stand-by processor
saved in the root of the USB stick. This info can be handy if no
information is displayed.
When in CSM mode (and a USB stick connected), pressing
Upgrading).
software version. Upgrading this software will be possible
via ComPair or via USB (see section 5.9 Software
“OK” will create an extended CSM dump file on the USB stick.
This file (Extended_CSM_model number_serial number.txt)
contains:
Example: STDBY_88.68.1.2.
version (12NC version number). Most significant number
here is the last digit.
• e-UM version. Displays the electronic user manual SW-
• The normal CSM dump information,
• All items (from SAM “load to USB”, but in readable format),
• AV PIP software.
• 3D dongle software version.
• Operating hours,
• Error codes,
• SW/HW event logs. To have fast feedback from the field, a flashdump can be
address to support the Wi-Fi functionality.
present in the SSB.
Quality items
• Signal quality. Bad / average /good (not for DVB-S).
• Ethernet MAC address. Displays the MAC address
• Wireless MAC address. Displays the wireless MAC
module is detected.
• BDS key. Indicates if the set is in the BDS status.
• CI module. Displays status if the common interface
• CI + protected service. Yes/No.
back to
div. table
).
requested by development. When in CSM, push the “red”
button and key in serial digits ‘2679’ (same keys to form the
word ‘COPY’ with a cellphone). A file “Dump_model
number_serial number.bin” will be written on the connected
USB device. This can take 1/2 minute, depending on the
quantity of data that needs to be dumped. Also when CSM is activated, the LAYER 1 error is displayed via
blinking LED. Only the latest error is displayed (see also
section 5.5 Error Codes
EN 18 Q551.1L LA5.
5.2.3 Customer Service Mode (CSM)
2010-Oct-01
Page 19
EN 19Q551.1L LA 5.
18770_250_100216.eps
100402
Active
Semi
St by
St by
Mains
on
Mains
off
GoToProtection
- WakeUp requested
- Acquisition needed
- Tact switch pushed
- stby requested and
no data Acquisition
required
- St by requested
- tact SW pushed
WakeUp
requested
Protection
WakeUp
requested
(SDM)
GoToProtection
Hibernate
- Tact switch pushed
- last status is hibernate
after mains ON
Tact switch
pushed
2010-Oct-01
Service Modes, Error Codes, and Fault Finding
activated via shortcutting the SDM solder path on the SSB, the
When the TV is in a protection state due to an error detected by
stand-by software (error blinking is displayed) and SDM is
5.3 Stepwise Start-up
TV starts up until it reaches the situation just before protection.
So, this is a kind of automatic stepwise start-up. In combination
with the start-up diagrams below, you can see which supplies
are present at a certain moment. Caution: in case the start-up
in this mode with a faulty FET 7U0X is done, you can destroy
all IC’s supplied by the +1V8 and +1v1, due to overvoltage (12V
on XVX-line). It is recommended to measure first the FET
7U0X or others FET’s on shortcircuit before activating SDM via
the service pads.
Processor.
The abbreviations “SP” and “MP” in the figures stand for:
• SP: protection or error detected by the Stand-by
Processor.
• MP: protection or error detected by the MIPS Main
Figure 5-3 Transition diagram
back to
div. table
EVENT-LOG #(reboots)
S : 0000 000X (number of software events : SW EVENT-
S : 000X 0000(number of software recoveries : SW
• Event counter :
LOG #(events)
H : 000X 0000(number of hardware errors)
H : 0000 000X (number of hardware events : SW EVENT-
LOG #(events).
How to Exit CSM
Press “MENU” (or "HOME") / “Back” key on the RC-transmitter.
Page 20
18770_251_100216.eps
100216
No
EJTAG probe
connected ?
No
Yes
Release AVC system reset
Feed warm boot script
Cold boot?
Yes
No
Set I²C slave address
of Standby μP to (A0h)
An EJTAG probe (e.g. WindPower ICE probe) can be
connected for Linux Kernel debugging purposes.
Detect EJTAG debug probe
(pulling pin of the probe interface to
ground by inserting EJTAG probe)
Release AVC system reset
Feed cold boot script
Release AVC system reset
Feed initializing boot script
disable alive mechanism
Off
Standby Supply starts running.
All standby supply voltages become available.
st-by μP resets
Stand by or
Protection
Mains is applied
- Switch Audio-Reset high.
It is low in the standby mode if the standby
mode lasted longer than 10s.
start keyboard scanning, RC detection. Wake up reasons are
off.
If the protection state was left by short circuiting the
SDM pins, detection of a protection condition during
startup will stall the startup. Protection conditions in a
playing set will be ignored. The protection mode will
not be entered.
Detect2 is moved to an interrupt. To be checked if
the detection on interrupt base is feasible or not or if
we should stick to the standard 40ms interval.
+12V, +24Vs, AL and Bolt-on power
is switched on, followed by the +1V2 DCDC converter
Enable the supply detection algorithm
Switch ON Platform and display supply by switching
LOW the Standby line.
Initialise I/O pins of the st-by μP:
- Switch reset-AVC LOW (reset state)
- Switch reset-system LOW (reset state)
- Switch reset-Ethernet LOW (reset state)
- Switch reset-USB LOW (reset state)
- Switch reset-DVBs LOW (reset state)
- keep Audio-reset and Audio-Mute-Up HIGH
Enable the DCDC converter s
(ENABLE-3V3n LOW)
No
Detect2 high received
within 2 seconds?
12V error :
Layer1: 3
Layer2: 16
Enter protection
Yes
Wait 50ms
Service Modes, Error Codes, and Fault Finding
back to
div. table
Figure 5-4 “Off” to “Semi Stand-by” flowchart (part 1)
EN 20 Q551.1L LA5.
2010-Oct-01
Page 21
EN 21Q551.1L LA 5.
18770_252_100216.eps
100216
Yes
MIPS reads the wake up reason
from standby μP.
Semi-Standby
initialize tuner and channel decoders
Initialize video processing IC’s
Initialize source s election
initialize AutoTV by triggering CHS AutoTV Init interface
3-th try?
No
Blink Code as
error code
Bootscript ready
in 1250 ms?
Yes
No
Enable Alive check mechanism
Wait until AVC starts to
communicat e
SW initialization
succeeded
within 20s?
No
Switch Standby I/O line high
and wait 4 seconds
RPC start (comm. protocol)
Set I²C slave address
of Standby μP to (60h)
Yes
Disable all supply related protections and
switch off the +3V3 +5V DC/DC converter.
switch off the remaining DC/DC
converters
Wait 5ms
Switch AVC PNX85500 in
reset (active low)
Wait 10ms
Flash to Ram
image transfer succeeded
within 30s?
No
Yes
Code =
Layer1: 2
Layer2: 53
Code =
Layer1: 2
Layer2: 15
Initialize Ambilight with Lights off.
Timing need to be updated if
more mature info is available.
Timing needs to
be updated if more
mature info is
available.
Timing needs to be
updated if more
mature info is
available.
Initialize audio
Enter protection
Reset-system is switched HIGH by the
AVC at the end of the bootscript
AVC releases Reset-Ethernet, Reset-USB and
Reset-DVBs when the end of the AVC boot-
script is detected
This cannot be done through the bootscript,
the I/O is on the sta ndby μP
Reset-Audio and Audio-Mute-Up are
switched by MIPS code later on in the
startup process
Reset-system is switched HIGH by the
AVC at the end of the bootscript
Reset-Audio and Audio-Mute-Up are
switched by MIPS code later on in the
startup process
Wake up reason
coldboot & not semi-
standby?
85500 sends out startup screen
Startup screen cfg file
present?
85500 starts up the display.
Startup screen visible
yes
yes
To keep this flowchart readable, the exact
display turn on description is not copied
here. Please see the Semi-standby to On
description for the detailed display startup
sequence.
During the complete display time of the
Startup screen, the preheat condition of
100% PWM is valid.
No
No
Startup screen shall only be visible when there is a coldboot to
an active state end situation. The startup screen shall not be
visible when waking up for reboot reasons or waking up to semi-
standby conditions or waking up to enter Hibernate mode. .
The first time after the option turn on o f the startup screen or
when the set is virgin, the cfg file is not present and hence
the startup screen will not be shown.
AVC releases Reset-Ethernet, Reset-USB and
Reset-DVBs when the end of the AVC boot-
script is detected
200Hz set?
No
yes
85500 sends out startup screen
200Hz Tcon has started up the
display.
Startup screen visible
85500 requests Lamp on
2010-Oct-01
back to
div. table
Figure 5-5 “Off” to “Semi Stand-by” flowchart (part 2)
Service Modes, Error Codes, and Fault Finding
Page 22
18770_253_100216.eps
100216
Active
Semi Standby
Initialize audio and video
processing IC's and functions
according needed use case.
Assert RGB video blanking
and audio mute
Wait until previous on-state is left more than 2
seconds ago. (to prevent LCD display problems)
The assumption here is that a fast toggle (<2s) can
only happen during ON->SEMI ->ON. In these states,
the AVC is still active and can provide the 2s delay. A
transition ON->SEMI->STBY->SEMI->ON cannot be
made in less than 2s, because the standby state will
be maintained for at least 4s.
Switch Audio-Reset low and wait 5ms
Constraints taken into account:
- Display may only be started when valid LVDS output clock can be delivered by the AVC.
- To have a reliable operation of the EEFL backlight, the backlight should be driven with a maximum PWM duty
cycle during the first seconds. Only after this first one or two seconds, the PWM may be set to the requir ed output
level (Note that the PWM output should be present before the backlight is switched on). To minimize the artefacts,
the picture should only be unblanked after these first seconds.
Restore dimming backlight feature, PWM and BOOST output
and unblank the video.
Wait until valid and stable audio and video, corresponding to the
requested output is delivered by the AVC
AND
the backlight has been switched on for at least the time which is
indicated in the display file as preheat time.
The higher level requirement is that audio and video
should be demuted without transient effects and that
the audio should be demuted maximum 1s before or
at the same time as the unblanking of the video.
Release audio mute and wait 100ms before any other audio
handling is done (e.g. volume change)
CPipe already generates a valid output
clock in the semi-standby state: display
startup can start immediately when leaving
the semi-standby state.
Switch on LCD backlight (Lamp-ON)
Switch off the dimming backlight feature, set
the BOOST control to nominal and make sure
PWM output is set to maximum allowed PWM
Switch on the Ambilight functionality according the last status
settings.
Delay Lamp-on with the sum of the LVDS delay and
the Lamp delay indicated in the display file
Switch on the display power by
switching LCD-PWR-ON low
Wait x ms
Switch on LVDS output in the 85500
No
The exact timings to
switch on the
display (LVDS
delay, lamp delay)
are defined in the
display file.
Start POK line
detection algorithm
return
Display already on?
(splash screen)
Yes
Display cfg file present
and up to date, according
correct display option?
Startup screen Option
and Installation setting
Photoscreen ON?
Yes
No
Prepare Start screen Display config
file and copy to Flash
No
Yes
A LED set does not normally need a
preheat time. The preheat remains present
but is set to zero in the display file.
Service Modes, Error Codes, and Fault Finding
back to
div. table
EN 22 Q551.1L LA5.
Figure 5-6 “Semi Stand-by” to “Active” flowchart (EEFL or LED backlight 50/100 Hz only)
2010-Oct-01
Page 23
EN 23Q551.1L LA 5.
18770_254_100216.eps
100216
Active
Semi Standby
Initialize audio and video
processing IC's and functions
according needed use case.
Assert RGB video blanking
and audio mute
Wait until previous on-state is left more than 2
seconds ago. (to prevent LCD display problems)
The assumption here is that a fast toggle (<2s)
can only happen during ON->SEMI ->ON. In
these states, the AVC is still active and can
provide the 2s delay. If the transition ON->SEMI-
>STBY->SEMI->ON can be made in less than 2s,
we have to delay the semi -> stby transition until
the requirement is met.
Switch Audio-Reset low and wait 5ms
unblank the video.
Wait until valid and stable audio and video, corresponding to
the requested output is delivered by the AVC.
The higher level requirement is that audio and
video should be demuted without transient
effects and that the audio should be demuted
maximum 1s before or at the same time as the
unblanking of the video.
Release audio mute and wait 100ms before any other audio
handling is done (e.g. volume change)
Request Tcon to Switch on the backlight in a
direct LED or
set Lamp-on I/O line in case of a side LED
Switch on the Ambilight functionality according the last status
settings.
There is no need to define the
display timings since the timing
implementation is part of the Tcon.
Start POK line
detection algorithm
return
Display cfg file present
and up to date, according
correct display option?
Startup screen Option
and Installation setting
Photoscreen ON?
Yes
No
Prepare Start screen Display config
file and copy to Flash
No
Yes
Backlight already on?
(splash screen)
No
Yes
2010-Oct-01
Service Modes, Error Codes, and Fault Finding
back to
div. table
Figure 5-7 “Semi Stand-by” to “Active” flowchart (LED backlight 200 Hz)
Page 24
18770_255_100216.eps
100216
Semi Standby
Active
Wait x ms (display file)
Mute all sound outputs via softmute
Mute all video outputs
switch off LCD backlight
(I/O or I²C)
Force ext audio outputs to ground
(I/O: audio reset)
And wait 5ms
switch off Ambilight
Set main amplifier mute (I/O: audio-mute)
Wait 100ms
Wait until Ambilight has faded out: Output power
Observer should be zero
Switch off the display power by
switching LCD-PWR-ON high
Wait x ms
Switch off LVDS output in 85500
The exact timings to
switch off the
display (LVDS
delay, lamp delay)
are defined in the
display file.
Switch off POK line
detection algorithm
200Hz set?
No
Yes
Instruct 200Hz
Tcon to turn off
the display
Service Modes, Error Codes, and Fault Finding
back to
div. table
Figure 5-8 “Active” to “Semi Stand-by” flowchart
EN 24 Q551.1L LA5.
2010-Oct-01
Page 25
EN 25Q551.1L LA 5.
18770_256_100216.eps
100216
transfer Wake up reasons to the Stand by μP.
Stand by
Semi Stand by
Disable all supply related protections and switch off
the DC/DC converters (ENABLE-3V3n)
Switch OFF all supplies by switching HIGH the
Standby I/O line
Switch AVC system in reset state (reset-system and
reset-AVC lines)
Switch reset-USB, Reset-Ethernet and Reset-DVBs
LOW
Important remarks:
release reset audio 10 sec after entering
standby to save power
Also here, the standby state has to be
maintained for at least 4s before starting
another state transition.
Wait 5ms
Wait 10ms
Delay transition until ramping down of ambient light is
finished. *)
If ambientlight functionality was used in semi-standby
(lampadaire mode), switch off ambient light (see CHS
ambilight)
*) If this is not performed and the set is
switched to standby when the switch off of
the ambilights is still ongoing, the lights will
switch off abruptly when the supply is cut.
Switch Memories to self-refresh (this creates a more
stable condition when switching off the power).
2010-Oct-01
back to
div. table
Service Modes, Error Codes, and Fault Finding
Figure 5-9 “Semi Stand-by” to “Stand-by” flowchart
Page 26
The error code buffer contains all detected errors since the last
10000_036_090121.eps
091118
TO
UART SERVICE
CONNECTOR
TO
UART SERVICE
CONNECTOR
TO
I
2
C SERVICE
CONNECTOR
TO TV
PC
HDMI
I
2
C only
Optional power
5V DC
ComPair II Developed by Philips Brugge
RC out
RC in
Optional
Switch
Power ModeLink/
Activity
I
2
C
ComPair II
Multi
function
RS232 /UART
5.5 Error Codes
5.5.1 Introduction
time the buffer was erased. The buffer is written from left to
right, new errors are logged at the left side, and all other errors
shift one position to the right.
When an error occurs, it is added to the list of errors, provided
the list is not full. When an error occurs and the error buffer is
full, then the new error is not added, and the error buffer stays
intact (history is maintained).
To prevent that an occasional error stays in the list forever, the
error is removed from the list after more than 50 hrs. of
CSM or SDM. No spacer must be displayed as well.
operation.
When multiple errors occur (errors occurred within a short time
span), there is a high probability that there is some relation
between them. New in this chassis is the way errors can be displayed: • If no errors are there, the LED should not blink at all in
• There is a simple blinking LED procedure for board
).
– LAYER 1 errors are one digit errors.
level repair (home repair) so called LAYER 1 errors
next to the existing errors which are LAYER 2 errors (see
Table 5-2
– LAYER 2 errors are 2 digit errors.
– From consumer mode: LAYER 1.
– From SDM mode: LAYER 2.
CSM and SAM are not selectable.
– From consumer mode: LAYER 1.
• In protection mode.
• Fatal errors, if I2C bus is blocked and the set reboots,
– From SDM mode: LAYER 2.
– When entering CSM: error LAYER 1 will be displayed
• In CSM mode.
by blinking LED. Only the latest error is shown.
hardware pins, LAYER 2 is displayed via blinking LED.
– When SDM is entered via Remote Control code or the
– In CSM no error codes are displayed on screen.
– In SAM the complete error list is shown.
• In SDM mode.
• Error display on screen.
”).
protection. These errors will always lead to protection and
an automatic start of the blinking LED LAYER 1 error.
(see section “5.6 The Blinking LED Procedure
Basically there are three kinds of errors:
• Errors detected by the Stand-by software which lead to
• Errors detected by the Stand-by software which not
, 5.5.4
lead to protection. In this case the front LED should blink
the involved error. See also section “5.5 Error Codes
Error Buffer”. Note that it can take up several minutes
before the TV starts blinking the error (e.g. LAYER 1
error = 2, LAYER 2 error = 15 or 53).
the error will be logged into the error buffer and can be read
• Errors detected by main software (MIPS). In this case
out via ComPair, via blinking LED method LAYER 1-2
error, or in case picture is visible, via SAM.
E.g.:
– 00 00 00 00 00: No errors detected
Use one of the following methods:
• On screen via the SAM (only when a picture is visible).
5.5.2 How to Read the Error Buffer
detected error.
error code 37 is the last detected error.
error buffer.
– 23 00 00 00 00: Error code 23 is the last and only
– 37 23 00 00 00: Error code 23 was first detected and
– Note that no protection errors can be logged in the
back to
div. table
Service Modes, Error Codes, and Fault Finding
EN 26 Q551.1L LA5.
5.4 Service Tools
5.4.1 ComPair
C or UART commands is necessary,
Introduction
ComPair (Computer Aided Repair) is a Service tool for Philips
Consumer Electronics products. and offers the following:
1. ComPair helps to quickly get an understanding on how to
2
repair the chassis in a short and effective way.
capable of accurately indicating problem areas. No
knowledge on I
2. ComPair allows very detailed diagnostics and is therefore
because ComPair takes care of this.
automatically communicate with the chassis (when the μP
is working) and all repair information is directly available.
4. ComPair features TV software up possibilities.
Specifications
ComPair consists of a Windows based fault finding program
and an interface box between PC and the (defective) product.
The ComPair II interface box is connected to the PC via an
USB cable. For the TV chassis, the ComPair interface box and
the TV communicate via a bi-directional cable via the service
connector(s).
The ComPair fault finding program is able to determine the
3. ComPair speeds up the repair time since it can
problem of the defective television, by a combination of
automatic diagnostics and an interactive question/answer
procedure.
How to Connect
This is described in the chassis fault finding database in
Figure 5-10 ComPair II interface connection
ComPair.
Caution: It is compulsory to connect the TV to the PC as
shown in the picture above (with the ComPair interface in
between), as the ComPair interface acts as a level shifter. If
one connects the TV directly to the PC (via UART), ICs can be
blown!
How to Order
ComPair II order codes:
• ComPair II interface: 3122 785 91020.
(using 3.5 mm Mini Jack connector): 3138 188 75051.
• Software is available via the Philips Service web portal.
• ComPair UART interface cable for Q55x.x.
Note: When you encounter problems, contact your local
support desk.
2010-Oct-01
Page 27
EN 27Q551.1L LA 5.
content, as this history can give significant information). This to
ensure that old error codes are no longer present.
If possible, check the entire contents of the error buffer. In
some situations, an error code is only the result of another error
C communication.
2
the PNX85500.
code and not the actual cause (e.g. a fault in the protection
detection circuitry can also lead to a protection).
There are several mechanisms of error detection:
• Via error bits in the status registers of ICs.
• Via polling on I/O pins going to the stand-by processor.
• Via sensing of analog values on the stand-by processor or
• Via a “not acknowledge” of an I
Take notice that some errors need several minutes before they
start blinking or before they will be logged. So in case of
problems wait 2 minutes from start-up onwards, and then
check if the front LED is blinking or if an error is logged.
Error Buffer/
Blinking LED Device Defective Board
Error/
Prot
Other root causes for this error can be due to hardware
problems regarding the DDR’s and the bootscript reading
from the PNX8550.
and results in protection (LAYER 1 error = 3) in case of
absence. When SDM is activated we see blinking LED
• Error 16 (12V). This voltage is made in the power supply
LAYER 2 error = 16.
the “Power OK” is checked by software, no protection will
• Error 17 (Invertor or Display Supply). Here the status of
C
2
C
C communication
2
occur during failure of the invertor or display supply (no
picture), only error logging. LED blinking of LAYER 1
error = 3 in CSM, in SDM this gives LAYER 2 error = 17.
towards the PNX51X0 after start-up, LAYER 2 error = 21
will be logged and displayed via the blinking LED
• Error 21 (PNX51X0). When there is no I
C communication
2
procedure if SDM is switched on. This device is located on
the 200 Hz panel from the display.
• Error 23 (HDMI). When there is no I
2
towards the HDMI mux after start-up, LAYER 2 error = 23
will be logged and displayed via the blinking LED
procedure if SDM is switched on.
• Error 24 (I2C switch). When there is no I
C switch, LAYER 2
2
C controlled screen included.
2
error = 24 will be logged and displayed via the blinking LED
procedure when SDM is switched on. Remark: this only
works for TV sets with an I
communication towards the I
• Error 28 (Channel dec DVB-S). When there is no I
2010-Oct-01
communication towards the DVB-S channel decoder,
back to
div. table
Service Modes, Error Codes, and Fault Finding
Clear the Error Buffer.
• Via the blinking LED procedure. See section 5.5.3 How to
•Via ComPair.
5.5.3 How to Clear the Error Buffer
in the SAM menu.
hours, it resets automatically.
Use one of the following methods:
• By activation of the “RESET ERROR BUFFER” command
• If the content of the error buffer has not changed for 50+
In case of non-intermittent faults, clear the error buffer before
Table 5-2 Error code overview
starting to repair (before clearing the buffer, write down the
5.5.4 Error Buffer
Monitored
by
C3 2 13 MIPS E BL / EB SSB SSB
2
I
Description Layer 1 Layer 2
C2 2 14 MIPS E BL / EB SSB SSB
2
I
C4 2 18 MIPS E BL / EB SSB SSB
2
I
PNX doesn’t boot (HW cause) 2 15 Stby μP P BL PNX8550 SSB
12V 3 16 Stby μP P BL / Supply
Inverter or display supply 3 17 MIPS E EB / Supply
PNX51X0 2/9 21 MIPS E EB PNX51X0 200 Hz board
HDMI mux 2 23 MIPS E EB Sil9x87A SSB
I2C switch 2 24 MIPS E EB PCA9540 SSB
AV-PIP board 8 25 MIPS E EB / AV PIP board
Channel dec DVB-S 2 28 MIPS E EB STV0903 SSB
Lnb controller 2 31 MIPS E EB LNBH23 SSB
Tuner 2 34 MIPS E EB DTT 71300 SSB
Main nvm 2 35 MIPS E EB STM24C64 SSB
Tuner DVB-S 2 36 MIPS E EB STV6110 SSB
T° sensor SSB/set 2 42 MIPS E EB LM 75 T° sensor
T° sensor LED driver/Tcon 7 42 MIPS E EB LM 75 T° sensor
PNX doesn’t boot (SW cause) 2 53 Stby μP P BL PNX8550 SSB
Display 5 64 MIPS E BL / EB Altera Display
, 5.8.7
C bus 3, SSB bus blocked). Current situation:
2
when this error occurs, the TV will constantly reboot due to
by the main software keep continuing. In this case
internal problems, most of the time no errors will be logged
or blinked. This rebooting can be recognized via a ComPair
interface and Hyperterminal (for Hyperterminal settings,
see section “5.8 Fault Finding and Repair Tips
Extra Info
• Rebooting. When a TV is constantly rebooting due to
diagnose has to be done via ComPair.
Logging). It’s shown that the loggings which are generated
• Error 13 (I
C link
2
2
C bus 2, TV set bus blocked). Current
2
the blocked bus. The best way for further diagnosis here, is
to use ComPair.
situation: when this error occurs, the TV will constantly
• Error 14 (I
reboot due to the blocked bus. The best way for further
diagnosis here, is to use ComPair.
C bus 4, Tuner bus blocked). In case this bus
2
is blocked, short the “SDM” solder paths on the SSB during
startup, LAYER error 2 = 18 will be blinked.
• Error 18 (I
between PNX and Stand-by Processor broken, etc...).
processor was not able to read his bootscript. This error will
point to a hardware problem around the PNX8550
(supplies not OK, PNX 8550 completely dead, I
• Error 15 (PNX8550 doesn’t boot). Indicates that the main
C1 bus is
C1 can be indicated in the schematics as
2
follows: SCL-UP-MIPS, SDA-UP-MIPS.
When error 15 occurs it is also possible that I
blocked (NVM). I
Page 28
”).
Tips, 5.8.7 Logging”).
entire content of the LAYER 2 error buffer, this works in
“normal operation” mode or when SDM (via hardware pins)
the latest layer 1 error, this works in “normal operation”
mode or automatically when the error/protection is
monitored by the Stand-by processor.
In case no picture is shown and there is no LED blinking,
read the logging to detect whether “error devices” are
mentioned. (see section “5.8 Fault Finding and Repair
2. Two short blinks of 250 ms followed by a pause of 3 s
3. Eight short blinks followed by a pause of 3 s
4. Six short blinks followed by a pause of 3 s
5. One long blink of 3 s to finish the sequence (spacer).
6. The sequence starts again.
Use one of the following methods:
• Activate the CSM. The blinking front LED will show only
is activated when the tv set is in protection.
• Activate the SDM. The blinking front LED will show the
Most of the protections and errors use either the stand-by
microprocessor or the MIPS controller as detection device.
Since in these cases, checking of observers, polling of ADCs,
and filtering of input values are all heavily software based,
these protections are referred to as software protections.
needs to be measured, no protection triggered here.
There are several types of software related protections, solving
a variety of fault conditions:
• Related to supplies: presence of the +5V, +3V3 and 1V2
• Protections related to breakdown of the safety check
mechanism. E.g. since the protection detections are done
by means of software, failing of the software will have to
initiate a protection mode since safety cannot be
guaranteed any more.
Remark on the Supply Errors
The detection of a supply dip or supply loss during the normal
playing of the set does not lead to a protection, but to a cold
reboot of the set. If the supply is still missing after the reboot,
the TV will go to protection.
Protections during Start-up
During TV start-up, some voltages and IC observers are
actively monitored to be able to optimize the start-up speed,
and to assure good operation of all components. If these
monitors do not respond in a defined way, this indicates a
malfunction of the system and leads to a protection. As the
observers are only used during start-up, they are described in
the start-up flow in detail (see section “5.3 Stepwise Start-up
The only real hardware protection in this chassis appears in
case of an audio problem e.g. DC voltage on the speakers. This
protection will only affect the Class D audio amplifier (item
the Class D amplifier tries to start-up again, the cone of the
loudspeakers will move slowly in one or the other direction
until the initial failure shuts the amplifier down, this cyclus
starts over and over again. The headphone amplifier will
7D10; see diagram B03A) and puts the amplifier in a
continuous burst mode (cyclus approximately 2 seconds).
Repair Tip
• There still will be a picture available but no sound. While
also behaves similar.
Service Modes, Error Codes, and Fault Finding
EN 28 Q551.1L LA5.
C
2
LAYER 2 error = 28 will be logged and displayed via the
blinking LED procedure if SDM is switched on.
• Error 31 (Lnb controller). When there is no I
5.6.2 How to Activate
C
C
2
C communication
2
towards the tuner during start-up, LAYER 2 error = 34 will
be logged and displayed via the blinking LED procedure
communication towards this device, LAYER 2 error = 31
will be logged and displayed via the blinking LED
procedure if SDM is activated.
when SDM is switched on.
communication towards the main NVM during start-up,
LAYER 2 error = 35 will be displayed via the blinking LED
• Error 34 (Tuner). When there is no I
• Error 35 (main NVM). When there is no I
procedure when SDM is switched “on”. All service modes
2
(CSM, SAM and SDM) are accessible during this failure,
communication towards the DVB-S tuner during start-up,
observed in the UART logging as follows: "<< ERRO >>>
PFPOW_.C: First Error (id19, Layer_1= 2 Layer_= 35)".
• Error 36 (Tuner DVB-S). When there is no I
5.7 Protections
5.7.1 Software Protections
LAYER 2 error = 36 will be logged and displayed via the
blinking LED procedure when SDM is switched “on”.
equipped with temperature devices.
read his bootscript (when this would have failed, error 15
would blink) but initialization was never completed because
of hardware problems (NAND flash, ...) or software
• Error 42 (Temp sensor). Only applicable for TV sets
• Error 53. This error will indicate that the PNX8550 has
C controlled
2
initialization problems. Possible cause could be that there
is no valid software loaded (try to upgrade to the latest main
software version). Note that it can take a few minutes
before the TV starts blinking LAYER 1 error = 2 or in SDM,
LAYER 2 error = 53.
screen.
• Error 64. Only applicable for TV sets with an I
5.6 The Blinking LED Procedure
5.6.1 Introduction
error is automatically blinked when the TV is put in CSM.
This will be only one digit error, namely the one that is
referring to the defective board (see table “5-2 Error code
overview”) which causes the failure of the TV. This
approach will especially be used for home repair and call
The blinking LED procedure can be split up into two situations:
• Blinking LED procedure LAYER 1 error. In this case the
”) and will be
displayed when SDM (hardware pins) is activated. This is
especially useful for fault finding and gives more details
centres. The aim here is to have service diagnosis from a
distance.
procedure, the contents of the error buffer can be made
visible via the front LED. In this case the error contains
• Blinking LED procedure LAYER 2 error. Via this
regarding the failure of the defective board.
2 digits (see table “5-2 Error code overview
Important remark:
5.7.2 Hardware Protections
For an empty error buffer, the LED should not blink at all in
CSM or SDM. No spacer will be displayed.
When one of the blinking LED procedures is activated, the front
LED will show (blink) the contents of the error buffer. Error
codes greater then 10 are shown as follows:
finishes with a LED blink of 3 s (spacer).
1. “n” long blinks (where “n” = 1 to 9) indicating decimal digit
2. A pause of 1.5 s
3. “n” short blinks (where “n”= 1 to 9)
4. A pause of approximately 3 s,
5. When all the error codes are displayed, the sequence
6. The sequence starts again.
Example: Error 12 8 6 0 0.
After activation of the SDM, the front LED will show:
1. One long blink of 750 ms (which is an indication of the
back to
div. table
decimal digit) followed by a pause of 1.5 s
2010-Oct-01
Page 29
EN 29Q551.1L LA 5.
2010-Oct-01
amplifier.
• +5V-TUN supply voltage (5V nominal) for tuner and IF
+3V3-STANDY (3V3 nominal) is the permanent voltage,
supplying the Stand-by microprocessor inside PNX85500. Supply voltage +1V1 is started immediately when +12V voltage
Service Modes, Error Codes, and Fault Finding
Read also section “5.5 Error Codes, 5.5.4 Error Buffer, Extra
Info”.
becomes available (+12V is enabled by STANDBY signal when
"low"). Supply voltages +3V3, +2V5, +1V8, +1V2 and +5V-TUN
are switched "on" by signal ENABLE-3V3 when "low", provided
that +12V (detected via 7U40 and 7U41) is present.
+12V is considered OK (=> DETECT2 signal becomes "high",
+12V to +1V8, +12V to +3V3, +12V to +5V DC-DC converter
can be started up) if it rises above 10V and doesn’t drop below
9V5. A small delay of a few milliseconds is introduced between
the start-up of 12V to +1V8 DC-DC converter and the two other
Due to degeneration process of the LED’s fitted on the ambi
module, there can be a difference in the color and/or light
output of the spare ambilight modules in comparison with the
originals ones contained in the TV set. Via SAM => alignments
=> ambilight, the spare module can be adjusted.
The Class D-IC 7D10 has a powerpad for cooling. When the IC
LNB supply generated via the second conversion channel
of 7T03 followed by 7T50 LNB supply control IC. It provides
supply voltage that feeds the outdoor satellite reception
equipment.
DC-DC converters via 7U48 and associated components. Description DVB-S2:
• LNB-RF1 (0V = disabled, 14V or 18V in normal operation)
is replaced it must be ensured that the powerpad is very well
pushed to the PWB while the solder is still liquid. This is needed
to insure that the cooling is guaranteed, otherwise the Class D-
IC could break down in short time.
• +3V3-DVBS (3V3 nominal), +2V5-DVBS (2V5 nominal)
To check the AV PIP board (if present) functionality, a
and +1V-DVBS (1.03V nominal) power supply for the
silicon tuner and channel decoder. +1V-DVBS is generated
via a 5V to 1V DC-DC converter and is stabilized at the
dedicated tespattern can be invoke as follows : select the
“multiview” icon in the User Interface and press the “OK”
button. Apply for the main picture an extended source, e.g.
point of load (channel decoder) by means of feedback
signal SENSE+1V0-DVBS. +3V3-DVBS and +2V5-DVBS
are generated via linear stabilizers from +5V-DVBS that by
itself is generated via the first conversion channel of 7T03.
At start-up, +24V becomes available when STANDBY signal is
"low" (together with +12V for the basic board), when +3V3 from
the basic board is present the two DC-DC converters channels
HDMI input. Proceed by entering CSM (push ‘123654’ on the
remote control) and press the yellow button. A colored
testpattern should appear now, generated by the AV PIP board
(can take a few seconds).
When CSM is activated and there is a USB stick connected to
inside 7T03 are activated. Initially only the 24V to 5V converter
(channel 1 of 7T03 generating +5V-DVBS) will effectively work,
while +V-LNB is held at a level around 11V7 via diode 6T55.
the TV, the software will dump the complete CSM content to the
USB stick. The file (Csm.txt) will be saved in the root of the USB
stick. If this mechanism works it can be concluded that a large
After 7T05 is initialized, the second channel of 7T03 will start
and generates a voltage higher then LNB-RF1 with 0V8. +5V-
DVBS start-up will imply +3V3-DVBS start-up, with a small
delay of a few milliseconds => +2V5-DVBS and +1V-DVBS will
be enabled.
If +24V drops below +15V level then the DVB-S2 supply will
stop, even if +3V3 is still present.
Debugging
The best way to find a failure in the DC/DC converters is to
of PNX85500, stabilized close to the point of load;
part of the operating system is already working (MIPS, USB...)
Description basic board The basic board power supply consists of 4 DC/DC converters
and 5 linear stabilizers. All DC/DC converters have +12V input
voltage and deliver:
• +1V1 supply voltage (1.15V nominal), for the core voltage
check their start-up sequence at power “on” via the mains cord,
presuming that the stand-by microprocessor and the external
supply are operational. Take STANDBY signal "high"-to-"low"
SENSE+1V1 signal provides the DC-DC converter the
needed feedback to achieve this.
• +1V8 supply voltage, for the DDR2 memories and DDR2
be a fast way to locate failures.
should rise within a few milliseconds.
Tips
After ENABLE-3V3 goes "low", all the other supply voltages
transition as time reference.
When +12V becomes available (maximum 1 second after
STANDBY signal goes "low") then +1V1 is started immediately.
interface of PNX85500.
onboard IC’s, for non-5000 series SSB diversities only.
• +3V3 supply voltage (3.30V nominal), overall 3.3 V for
• +5V (5.15V nominal) for USB, WIFI and Conditional
• Behavior comparison with a reference TV550 platform can
Access Module and +5V5-TUN for +5V-TUN tuner
stabilizer.
The linear stabilizers are providing:
• +1V2 supply voltage (1.2V nominal), stabilized close to
and source) of the power MOS-FETs before starting up the
platform in SDM, otherwise many components might be
damaged. Using a ohmmeter can detect short circuits
between any power rail and ground or between +12V and
any other power rail.
(7UC0, 7UD2 or 7UD3) will heat up this device strongly.
12 V to 1.1 V and 12 V to 1.8 V DC-DC converters,
• If +12V stays "low", check the integrity of fuse 1U40.
• Check the integrity (at least no short circuit between drain
PNX85500 device, for various other internal blocks of
PNX85500; SENSE+1V2 signal provides the needed
feedback to achieve this.
various other internal blocks of PNX85500; for 5000 series
• +2V5 supply voltage (2.5V nominal) for LVDS interface and
• Short circuit at the output of an integrated linear stabilizer
• Switching frequencies should be 500 kHz ...600 kHz for
SSB diversities the stabilizer is 7UD2 while for the other
diversities 7UC0 is used.
diversities, provided by 7UD3; in this case the 12V to 3V3
DC-DC converter is not present.
• +3V3 supply voltage (3V3 nominal) for 5000 series SSB
back to
div. table
5.8 Fault Finding and Repair Tips
5.8.1 Ambilight
5.8.2 Audio Amplifier
5.8.3 AV PIP
5.8.4 CSM
5.8.5 DC/DC Converter
Page 30
C bus. => error
2
mentioned in the logging as: *51x0 failed to start by itself*.
instance fatal error on the PNX51x0: check startup of the
back-end processor, supplies..reset, I
UART loggings reporting fault conditions, error messages,
error codes, fatal errors:
• Failure messages should be checked and investigated.For
• Some failures are indicated by error codes in the logging,
C bus 4 blocked”.
2
C bus error mentioned as e.g.: “ I
2
overview”).e.g. => <<<ERROR>>>PLFPOW_MERR.C :
check with error codes table (see Table “5-2 Error code
First Error (id=10,Layer_1=2,Layer_2=23).
fault.For instance root cause can be due to wrong option
codes settings => e.g. “DVBS2Suppoprted : False/True.
• Not all failures or error messages should be interpreted as
• I
In the UART log startup script we can observe and check the
enabled loaded option codes.
Defective sectors (bad blocks) in the Nand Flash can also be
reported in the logging.
Startup in the SW upgrade application and observe the UART
logging:
Starting up the TV set in the Manual Software Upgrade mode
will show access to USB, meant to copy software content from
USB to the DRAM.Progress is shown in the logging as follows:
“cosupgstdcmds_mcmdwritepart: Programming 102400 bytes,
40505344 of 40607744 bytes programmed”.
Startup in Jett Mode:
Check UART logging in Jet mode mentioned as : “JETT UART
READY”.
UART logging changing preset:
=> COMMAND: calling DFB source = RC6, system=0, key = 4”.
Make sure that the volume is set to minimum during
disconnecting the speakers in the ON-state of the TV. The
audio amplifier can be damaged by disconnecting the speakers
during ON-state of the set!
In case of no picture when CSM (test pattern) is activated and
backlight doesn’t light up, it’s recommended first to check the
inverter on the PSL + wiring (LAYER 2 error = 17 is displayed
in SDM).
Attention: In case the tuner is replaced, always check the tuner
options!
Attention: In case the SSB is replaced, always check the
display option code in SAM, even when picture is available.
Performance with the incorrect display option code can lead to
unwanted side-effects for certain conditions.
New in this chassis:
While in the download application (start up in TV mode + “OK”
button pressed), the display option code can be changed via
062598 HOME XXX special SAM command (XXX=display
option in 3 digits).
Service Modes, Error Codes, and Fault Finding
EN 30 Q551.1L LA5.
900 kHz for 12 V to 3.3 V and 12 V to 5 V DC-DC
converters. The DVB-S2 supply 24 V to 5 V and 24 V to +V
LNB DC-DC converters operates at 300 kHz while for 5 V
to 1.1 V DC-DC converter 900 kHz is used.
When an “F” is displayed in the screen’s right corner, this
5.8.6 Exit “Factory Mode”
means the set is in “Factory” mode, and it normally
happens after a new SSB is mounted. To exit this mode, push
the “VOLUME minus” button on the TV’s local keyboard for 10
seconds (this disables the continuous mode).
Then push the “SOURCE” button for 10 seconds until the “F”
disappears from the screen.
When something is wrong with the TV set (f.i. the set is
5.8.7 Logging
Windows application via Programs, Accessories,
rebooting) you can check for more information via the logging
in Hyperterminal. The Hyperterminal is available in every
Communications, Hyperterminal. Connect a “ComPair UART”-
cable (3138 188 75051) from the service connector in the TV to
the “multi function” jack at the front of ComPair II box.
Required settings in ComPair before starting to log:
- Start up the ComPair application.
- Select the correct database (open file “Q55X.X”, this will set
the ComPair interface in the appropriate mode).
- Close ComPair
After start-up of the Hyperterminal, fill in a name (f.i. “logging”)
in the “Connection Description” box, then apply the following
settings:
1. COMx
5.8.9 Loudspeakers
2. Bits per second = 115200
3. Data bits = 8
4. Parity = none
5. Stop bits = 1
6. Flow control = none
During the start-up of the TV set, the logging will be displayed.
This is also the case during rebooting of the TV set (the same
5.8.10 PSL
logging appears time after time). Also available in the logging
is the “Display Option Code” (useful when there is no picture),
look for item “DisplayRawNumber” in the beginning of the
logging. Tip: when there is no picture available during rebooting
you are able to check for “error devices” in the logging (LAYER
2 error) which can be very helpful to determine the failure cause
of the reboot. For protection state, there is no logging.
5.8.8 Guidelines UART logging
5.8.11 Tuner
Description possible cases: UART loggings are displayed:
5.8.12 Display option code
we can make is that the TV set is starting up and
communication with the flash RAM seems to be supported.
The PNX85500 is able to read and write in the DRAMs.
operational/reliable.There still can be errors in the data
• When UART loggings are coming out, the first conclusion
• We can not yet conclude : Flash RAM and DRAMs are fully
back to
div. table
C bus (3 trials to
2
transfers, DRAM errors, read/write speed and timing
control.
startup script can be send over the I
startup) + power supplies are switched on and stable.
LAYER 1 = “2”, error LAYER 2 = “53” (startup with SDM
solder paths short).
No UART logging at all:
• In case there is no UART logging coming out, check if the
• No startup will end up in a blinking LED status : error
• Error LAYER 2 = “15” (hardware cause) is more related to
a supply issue while error LAYER 2 = “53” (software cause)
refers more to boot issues.
2010-Oct-01
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EN 31Q551.1L LA 5.
H_16771_007a.eps
100402
START
C onn ect the US B sti ck to th e set,
go to SAM and save the current TV settings via “Upload to USB”
Set is stil l operating?
Yes
1.
D isco nnect the WiFi modu le fro m the P CI c onnec tor (only for Q549.x SSB)
2. Replace the SSB by a Service SSB.
3. Place the WiFi module in the PCI connector.
4. Mount the Service SSB in the set.
Set behaviour?
Yes
No
No
Instru ction n ote SSB replacemen t Q543.x, Q548.x, Q549.x, and Q55x.x
Before starting:
- prepare a USB memory stick with the latest software
- download the latest Main Software (Fus) from www.p4c.philips.com
- unzip this file
- create a folder ”upgrades” in the root of a USB stick (size > 50 MB) and
save the autorun.upg file in this "upgrades" folder.
Note: it is possible to rename this file, e.g."Q54x_SW_version.upg"; this in
case there are more than one "autorun.upg" files on the USB stick.
No pic ture displayed
Pic tur e displayed
Set is starting up without software
upgrade menu appearing on screen
Pic tur e displayed
Set is starting up with software
upgrade menu appearing on screen
Due to a possible wrong display option code in the received Service
SSB (NVM), it’s possible that no picture is displayed. Due to this
the download application will not be shown either. This tree enables you
to load the main software step-by-step via the UART logging on the PC
(this for visual feedback).
Start-up the set
1) Start up the TV set, equiped with the Service SSB,
and enable the UART logging on the PC.
2) The TV set will start-up automatically in the
download application if main TV software is not loaded.
3) Plug the prepared USB stick into the TV set. Follow the
instructions in the UART log file, press “Right” cursor key to enter
the list. Navigate to the “autorun.upg” file in the UART logging
printout via the cursor keys on the remote control. When the
correct file is selected, press
“Ok”.
4) Press "Down" cursor and “Ok” to start flashing the main
TV software. Printouts like: “L: 1-100%, V: 1-100% and
P: 1-100%” should be visible now in the UART logging.
5) Wait until the message “Operation successful !” is logged in
the UART log and remove all inserted media. Restart the TV set.
1) Plug the USB stick into the TV set and select
the “autorun .upg” file in the displayed browser.
2) Now the main software will be loaded automatically,
supported by a progress bar.
3) Wait until the message “Operation successful !” is displayed
and remove all inserted media. Restart the TV set.
Set the correct “Display code” via “062598 -HOME- xxx” where
“xxx” is the 3 digit display panel code (see sticker on the side
or bottom of the cabinet)
After entering the “Display Option” code, the set is going to
Standby
(= validation of code)
Restart the set
Connect PC via the ComPair interface to Service connector.
Start TV in Jett mode (DVD I + (OSD))
Open ComPair browser Q54x
Program set type number, serial number, and di
splay 12 NC
Program E - DFU if needed.
Go to SAM and reload settings
via “Download from USB” function.
In case of settings reloaded from USB, the set type,
serial number, display 12 NC, are automatically stored
when entering display options.
- Check if correct “display option” code is programmed.
- Verify “option codes” according to sticker inside the set.
- Default settings for “white drive” > see Service Manual.
Q54x.E SSB Board swap – VDS
Updated 22-03-2010
If not already done:
Check latest software on Service website.
Update main and Stand-by software via USB.
Check and perform alignments in SAM according to the
Service Manual. Option codes, colour temperature, etc.
Final check of all menus in CSM.
Special attention for HDMI Keys and Mac address.
Check if E - D F U is present.
End
Attention point for Net TV: If the set type and serial number are not
filled in, the Net TV functionality will not work. It will not be possible
to connect to the internet.
Saved settings
on USB stick?
2010-Oct-01
Service Modes, Error Codes, and Fault Finding
Follow the instructions in the flowchart in case a SSB has to be
exchanged. See figure “SSB replacement flowchart”.
back to
div. table
Figure 5-11 SSB replacement flowchart
5.8.13 SSB Replacement
Page 32
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100322
Restart the set
Set is starting up in Factory mode
Set is starting up in Factory m ode?
Noisy picture with bands/lines is visible and the
RED LED is continuous on.
An “F” is displayed (and the HDMI 1
input is displayed).
- Press the “volume minus” button on the TVs local keyboard for 5 ~10
seconds
- Press the “SOURCE” button for 10 seconds until the “F” disappears
from the screen or the noise on the screen is replaced by “blue mute”
The noise on the screen is replaced
with the
blue mute or the “F” is disappeared!
Unplug the mains cord to verify the correct
disabling of the Factory mode.
Program display option code
via “062598 MENU”, followed by
the 3 digits code of the display
(this code can be found
on a sticker on - or inside - the set).
After entering “display option” code, the set is
going in stand-by mode (= validation of code)
back to
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Service Modes, Error Codes, and Fault Finding
EN 32 Q551.1L LA5.
Figure 5-12 SSB replacement flowchart - Factory mode
2010-Oct-01
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100811
Figure 5-13 SSB start-up
Automatic Software Upgrade
In “normal” conditions, so when there is no major problem with
the TV, the main software and the default software upgrade
application can be upgraded with the “AUTORUN.UPG”
2010-Oct-01
set will restart and the upgrading will start automatically. As
soon as the programming is finished, a message is shown
to remove the USB stick and restart the set.
(FUS part of the one-zip file: e.g. 3104 337 05661 _FUS
_Q555X_ x.x.x.x_prod.zip). This can also be done by the
consumers themselves, but they will have to get their software
from the commercial Philips website or via the Software Update
Assistant in the user menu (see eUM). The “autorun.upg” file
must be placed in the root of the USB stick.
How to upgrade:
1. Copy “AUTORUN.UPG” to the root of the USB stick.
2. Insert USB stick in the set while the set is operational. The
Manual Software Upgrade
In case that the software upgrade application does not start
automatically, it can also be started manually.
How to start the software upgrade application manually:
Philips DVD RC-6 remote control (it is also possible to use
a TV remote in “DVD” mode). Keep the “OK” button
pressed while reconnecting the TV to the Mains/AC Power.
1. Disconnect the TV from the Mains/AC Power.
2. Press the “OK” button on a Philips TV remote control or a
3. The software upgrade application will start.
Attention!
In case the download application has been started manually,
the “autorun.upg” will maybe not be recognized.
What to do in this case:
1. Create a directory “UPGRADES” on the USB stick.
back to
div. table
Service Modes, Error Codes, and Fault Finding
The set software and security keys are stored in a NAND-
Flash, which is connected to the PNX85500.
5.9 Software Upgrading
5.9.1 Introduction
It is possible for the user to upgrade the main software via the
USB port. This allows replacement of a software image in a
stand alone set, without the need of an E-JTAG debugger. A
description on how to upgrade the main software can be found
in the electronic User Manual.
Important: When the NAND-Flash must be replaced, a new
Manual) for instructions.
SSB must be ordered, due to the presence of the security keys!
(CI +, MAC address, ...).
Perform the following actions after SSB replacement:
1. Set the correct option codes (see sticker inside the TV).
2. Update the TV software => see the eUM (electronic User
3. Perform the alignments as described in chapter 6 (section
).
6.5 Reset of Repaired SSB
4. Check in CSM if the CI + key, MAC address.. are valid.
For the correct order number of a new SSB, always refer to the
Spare Parts list!
• The “UpgradeAll.upg” file is only used in the factory.
5.9.2 Main Software Upgrade
Page 34
Service Modes, Error Codes, and Fault Finding
“software.upg”. Do not use long or complicated names,
keep it simple. Make sure that “AUTORUN.UPG” is no
2. Rename the “autorun.upg” to something else, e.g. to
longer present in the root of the USB stick.
3. Copy the renamed “upg” file into this directory.
4. Insert USB stick into the TV.
5. The renamed “upg” file will be visible and selectable in the
back to
div. table
program instruction and software content, needed to
upgrade the ambilight CPLD on the TV550 platform.
BalanceFPGA software in “upg” format.
“autorun.upg” which is needed to upgrade the TV main
software and the software download application.
PNX5130 software in “upg” format.
StandbyFactory software in “upg” format.
content. Must be programmed via ComPair or can be
loaded via USB, be aware that all alignments stored in
• ProcessNVM_Q55XX_x.x.x.x_prod.zip. Default NVM
NVM are overwritten here.
Repair Tips, 5.8.7 Logging)
upgrade application.
Back-up Software Upgrade Application
If the default software upgrade application does not start (could
be due to a corrupted boot sector) via the above described
method, try activating the “back-up software upgrade
application”.
How to start the “back-up software upgrade application”
remote control while reconnecting the TV to the Mains/AC
Power.
manually:
1. Disconnect the TV from the Mains/AC Power.
2. Press the “CURSOR DOWN”-button on a Philips TV
3. The back-up software upgrade application will start.
StandbyFactory_88.0.0.0.upg) into this directory.
In this chassis it is possible to upgrade the Stand-by software
via a USB stick. The method is similar to upgrading the main
software via USB.
Use the following steps:
1. Create a directory “UPGRADES” on the USB stick.
2. Copy the Stand-by software (part of the one-zip file, e.g.
Manual Software Upgrade”.
upgrade.
3. Insert the USB stick into the TV.
4. Start the download application manually (see section “
5. Select the appropriate file and press the “OK” button to
Below the content of the One-Zip file is explained, and
instructions on how and when to use it.
• AmbiCpld_Q55XX_x.x.x.x_prod.zip. Contains the
• BalanceFPGA_Q555X_x.x.x.x_prod.zip. Contains the
• FUS_Q555X_x.x.x.x_prod.zip. Contains the
• PNX5130UPG_Q555X_x.x.x.x_prod.zip. Contains the
• StandbySW_Q555X_x.x.x.x_prod.zip. Contains the
EN 34 Q551.1L LA5.
5.9.3 Stand-by Software Upgrade via USB
5.9.4 Content and Usage of the One-Zip Software File
5.9.5 UART logging 2K10 (see section “5.8 Fault Finding and
2010-Oct-01
Page 35
EN 35Q551.1L LA 6.
For the next alignments, supply the following test signals via a
video generator to the RF input:
• EU/AP-PAL models: a PAL B/G TV-signal with a signal
strength of at least 1 mV and a frequency of 475.25 MHz
signal strength of at least 1 mV and a frequency of 61.25
• US/AP-NTSC models: an NTSC M/N TV-signal with a
MHz (channel 3).
strength of at least 1 mV and a frequency of 61.25 MHz
(channel 3).
• LATAM models: an NTSC M TV-signal with a signal
“Picture” and set picture settings as follows:
Picture Setting
Contrast 100
• Choose “TV menu”, “Setup”, “More TV Settings” and then
Brightness 50
2010-Oct-01
r 0.002.
to be aligned.
(in the SAM root menu) to store the aligned values to the
values CCFL backlight panels, 6-2 White D alignment
values - LED - Minolta CA-210 or 6-3 White D alignment
settings as follows:
Colour 0
Light Sensor Off
Picture format Unscaled
• In menu “Picture”, choose “Pixel Plus HD” and set picture
Picture Setting
Dynamic Contrast Off
Dynamic Backlight Off
Colour Enhancement Off
Gamma 0
• Go to the SAM and select “Alignments”-> “White point”.
following values:
– “Color temperature”: “Normal”.
– All “White point” values to: “127”.
White point alignment LCD screens:
• Use a 90% white screen to the HDMI input and set the
contactless color analyzer (Minolta CA-210 or Minolta CS-
200) in the centre of the screen.
In case you have a color analyzer:
• Measure, in a dark environment, with a calibrated
White point registers R, G or B on 127) by means of
decreasing the value of one or two other white points to the
• Adjust the correct x, y coordinates (while holding one of the
values - LED - Minolta CS-200). Tolerance: dx: r 0.002, dy:
correct x, y coordinates (see Table 6-1 White D alignment
• Repeat this step for the other color temperatures that need
NVM.
Value Cool (11000K) Normal (9000K) Warm (6500K)
x 0.276 0.287 0.313
• When finished press OK on the RC and then press STORE
• Restore the initial picture settings after the alignments.
Table 6-1 White D alignment values CCFL backlight panels
y 0.282 0.296 0.329
Table 6-2 White D alignment values - LED - Minolta CA-210
Value Cool (9420K) Normal (8120K) Warm (6080K)
x 0.282 0.292 0.320
y 0.298 0.311 0.345
Alignments
6. Alignments
Index of this chapter:
6.1 General Alignment Conditions
6.2 Hardware Alignments
6.3 Software Alignments
6.4 Option Settings
6.5 Reset of Repaired SSB
6.6 Total Overview SAM modes
6.1 General Alignment Conditions
6.3.1 White Point
/ 50 Hz (r 10%).
AC
– AP-NTSC: 120 VAC or 230 V
Perform all electrical adjustments under the following
conditions:
• Power supply voltage (depends on region):
/ 50 Hz (r 10%).
AC
/ 50 Hz (r 10%).
AC
– EU: 230 V
– AP-PAL-multi: 120 - 230 V
/ 50 Hz (r 10%).
AC
/ 60 Hz (r 10%).
AC
– LATAM-NTSC: 120 - 230 V
with low internal resistance.
– US: 120 V
• Connect the set to the mains via an isolation transformer
• Allow the set to warm up for approximately 15 minutes.
• Measure voltages and waveforms in relation to correct
ground (e.g. measure audio signals in relation to
AUDIO_GND).
alignments.
Caution: It is not allowed to use heat sinks as ground.
• Test probe: Ri > 10 M:, Ci < 20 pF.
• Use an isolated trimmer/screwdriver to perform
6.1.1 Alignment Sequence
according to the set sticker (see also paragraph 6.4
moved to the left.
Option Settings).
– In SAM, select “Option numbers”.
– Fill in the option settings for “Group 1” and “Group 2”
• First, set the correct options:
OK on the RC.
– Press OK on the remote control before the cursor is
– In submenu “Option numbers” select “Store” and press
•OR:
the RC.
– In main menu, select “Store” again and press OK on
– Switch the set to Stand-by.
• Warming up (>15 minutes).
Not applicable.
6.2 Hardware Alignments
Put the set in SAM mode (see Chapter 5. Service Modes, Error
Codes, and Fault Finding). The SAM menu will now appear on
6.3 Software Alignments
the screen. Select ALIGNMENTS and go to one of the sub
menus. The alignments are explained below.
The following items can be aligned:
• White point
• Ambilight
• TCON Alignment
• Reset TCON Alignment. To store the data:
left
• Press OK on the RC before the cursor is moved to the
• In main menu select “Store” and press OK on the RC
• Switch the set to stand-by mode.
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Page 36
C
2
420
403
443
428
6.3.3 TCON/VCOM alignment
Alignments
Sets with forward integration have the TCON on SSB. The
alignment of this TCON is stored in the SSB, and is related to
the used display. When an SSB or a display is replaced, a new
value must be entered.
A default value (see table below) is copied from the display file
(after entering the correct display code) and is shown in the
SAM menu. But on top of this, the default value can be
overruled manually via the menu item “TCON alignment”.
The current value is shown with 4 digits, and can be changed
by a digit entry. After pressing “OK”, the value is stored.
The menu item "Reset TCON alignment" can be used to return
to the default value from the display file. A notification is shown:
"TCON alignment has been reset".
Table 6-7 TCON/VCOM default settings
Supplier Panel TCON/VCOM Alignment
.
37” CCFL (Rembrandt)
42” CCFL (Rembrandt)
32” LED (Matisse)
37” LED (Matisse) 375
40” LED (Van Gogh) 95
46” LED (Van Gogh) 143
52” LED (Van Gogh) 203
40” LED (da Vinci) 0098
46” LED (da Vinci) 0129
button on the RC before the cursor is moved to the left,
select STORE in the SAM root menu and press OK on the
RC.
switched “off” / “stand-by” and “on” again with the mains
switch (the NVM is then read again).
LGD (max: 1023) 32” CCFL (Rembrandt)
Sharp (max: 255) 32” LED (Van Gogh) 109
6.4 Option Settings
The microprocessor communicates with a large number of I
ICs in the set. To ensure good communication and to make
digital diagnosis possible, the microprocessor has to know
which ICs to address. The presence / absence of these
PNX51XX ICs (back-end advanced video picture improvement
IC which offers motion estimation and compensation features
(commercially called HDNM) plus integrated Ambilight control)
is made known by the option codes. Notes:
6.4.1 Introduction
• After changing the option(s), save them by pressing the OK
• The new option setting is only active after the TV is
For dealer options, in SAM select “Dealer options”.
See Table 6-8 SAM mode overview
6.4.2 Dealer Options
6.4.3 (Service) Options
.
Select the sub menu's to set the initialization codes (options) of
the model number via text menus.
See Table 6-8 SAM mode overview
6.4.4 Opt. No. (Option numbers)
Select this sub menu to set all options at once (expressed in
two long strings of numbers).
An option number (or “option byte”) represents a number of
different options. When you change these numbers directly,
you can set all options very quickly. All options are controlled
via eight option numbers.
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EN 36 Q551.1L LA6.
Value Cool (11000K) Normal (9000K) Warm (6500K)
Table 6-3 White D alignment values - LED - Minolta CS-200
x 0.276 0.287 0.313
y 0.282 0.296 0.329
.
NORMAL, or WARM).
to the values in Table 6-4
the SAM root menu) to store the aligned values to the NVM.
If you do not have a color analyzer, you can use the default
values. This is the next best solution. The default values are
average values coming from production.
• Select a COLOUR TEMPERATURE (e.g. COOL,
• Set the RED, GREEN and BLUE default values according
• When finished press OK on the RC, then press STORE (in
• Restore the initial picture settings after the alignments.
Table 6-4 White tone default setting 40" (Monet)
White Tone e.g. 40PFL9605D/xx
Colour Temp R G B
Normal 127 118 88
Cool 126 126 106
Warm 127 109 54
White Tone e.g. 58PFL9955D/xx
Table 6-5 White tone default setting 58" (Rubens 21:9)
by the ambilight modules.
Module 1 is the first one which will come across according
the wiring path, starting at the small signal panel,
proceeding towards the ambient light modules.The first
module will be attached to the next module 2. Module
number 2 to number 3 etc..as follows the way to define the
ambilight module numbering.
modules. The brightness is automatically stored.
the neighboring modules, “matrix 0” is the factory
alignment and can always be retrieved. (see table “6-6
Overview matrix correction table
Colour Temp R G B
Normal 127 109 115
Cool 126 109 127
Warm 127 104 83
Every ambient light module is aligned by a matrix and by the
brightness. After replacement of a module, the brightness/color
must be aligned with the other modules:
1. Go to SAM.
2. Select “Alignments”.
3. Select “Ambilight”. A white test pattern shall be displayed
4. Select the number of the module that have to be aligned.
5. Align the brightness compared with the neighboring
6. Select one of 10 matrixes which color matches most with
7. The alignment is stored automatically.
6.3.2 Ambilight
Matrix # fR fG fB
Matrix 0 1 1 1
Matrix 1 1 0. 95 0.95
Matrix 2 0.95 1 0.95
Matrix 3 0.95 0.95 1
Matrix 4 0.95 1 1
Matrix 5 1 0.95 1
Matrix 6 1 1 0.95
Matrix 7 1 0. 97 0.95
Matrix 8 0.97 0.95 1
Table 6-6 Overview matrix correction table
Matrix 9 0.95 0.97 1
2010-Oct-01
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090319
Alignments
2010-Oct-01
Figure 6-1 SSB identification
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.
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When the NVM is replaced, all options will require resetting. To
be certain that the factory settings are reproduced exactly, you
must set both option number lines. You can find the correct
option numbers on a sticker inside the TV set.
Example: The options sticker gives the following option
numbers:
• 08192 00133 01387 45160
• 12232 04256 00164 00000
The first line (group 1) indicates hardware options 1 to 4, the
second line (group 2) indicate software options 5 to 8.
Every 5-digit number represents 16 bits (so the maximum value
will be 65536 if all options are set).
When all the correct options are set, the sum of the decimal
values of each Option Byte (OB) will give the option number.
Diversity
Not all sets with the same Commercial Type Number (CTN)
necessarily have the same option code!
Use of Alternative BOM => an alternative BOM number usually
indicates the use of an alternative display or power supply. This
Refer to the sticker in the set for the correct option codes.
Important: after having edited the option numbers as
described above, you must press OK on the remote control
results in another display code thus in another Option code.
Refer to Chapter 2. Technical Specifications, and Connections
6.4.5 Option Code Overview
before the cursor is moved to the left!
A very important issue towards a repaired SSB from a Service
repair shop (SSB repair on component level) implies the reset
of the NVM on the SSB.
6.5 Reset of Repaired SSB
A repaired SSB in Service should get the service Set type
“00PF0000000000” and Production code “00000000000000”.
Also the virgin bit is to be set. To set all this, you can use the
ComPair tool or use the “NVM editor” and “Dealer options”
items in SAM (do not forget to “store”).
After a repaired SSB has been mounted in the set (set repair
on board level), the type number (CTN) and production code of
the TV has to be set according to the type plate of the set. For
this (new in this platform), you can use the NVM editor in
SAM. This action also ensures the correct functioning of the
“Net TV” feature and access to the Net TV portals. The loading
of the CTN and production code can also be done via ComPair
(Model number programming).
In case of a display replacement, reset the “Operation hours
display” to “0”, or to the operation hours of the replacement
display.
6.5.1 SSB identification
Whenever ordering a new SSB, it should be noted that the
correct ordering number (12nc) of a SSB is located on a sticker
on the SSB. The format is <12nc SSB><serial number>. The
ordering number of a “Service” SSB is the same as the ordering
number of an initial “factory” SSB.
Page 38
number
switched “on/off” & every 0.5 hours is increase one
lected
LCD White Point Alignment. For values,
see Table 6-4 White tone default setting 40" (Monet)
and Table 6-5 White tone default set ting 58" (Rubens
21:9)
Warn
Cool
exchange) is keyed-in and if you have alignment
values from production; see Table 6-7 TCON/VCOM
default settings
exchange) is keyed-in and if you do not have
alignment values from production
Select Virgin mode On/Off. TV starts up / does not
start up (once) with a language selection menu after
the mains switch is turned “on” for the first time (virgin
mode)
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Alignments
EN 38 Q551.1L LA6.
6.6 Total Overview SAM modes
White point red
White point green
White point blue
Brightness
Select matrix
B. Stand-by processor version e.g. “STDBY_42.42.0.0”
C. Production code e .g. “see type plate”
Main Menu Sub-menu 1 Sub-menu 2 Sub-menu 3 Description
Hardware Info A. SW version e.g. “Q5521_0.33.0.0 Display TV & Stand-by SW version and CTN serial
Operation hours Displays the accumulated total of operation hours.TV
Errors Displayed the most recent errors
Reset error buffer Clears all content in the error buffer
Table 6-8 SAM mode overview
Alignment White point Colour temperature Normal 3 different modes of colour temperature can be se-
Ambilight Select module
TCON alignment used when a new display code (after a SSB
Reset TCON alignment used when a new display code (after a SSB
Dealer options Virgin mode Off/On
PDC/VPS
TXT page
PDC/VPS/TXT
E-sticker Off/On Select E-sticker On/Off (USP’s on-screen)
Auto store mode None
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EN 39Q551.1L LA 6.
2010-Oct-01
Alignments
DVB - T installation Off/On or Country dependent Select DVB T installation On/Off or by country
DVB - T light Off/On Select DVB T light On/Off
DVB - C Off/On Select DVB C On/Off
DVB - C installation Off/On or Country dependent Select DVB C installation On/Off or by country
DVB - C light Off/On Select DVB C light On/Off
Sensor present Yes/No and in case Yes, where
On SSB
DVB - S Off/On Select DVB S On/Off
Over the air download Off/On or Country dependent Select Over the air download On/Off or by country
8 days EPG Off/On Select 8 day EPG On/Off
Wi-Fi Off/On Select Wi-Fi On/Off
DLNA Off/On Select DLNA On/Off
On-line service On On-line service is On
Videostore SD card slot Off/On Select Videostore SD card slot On/Off
Multiview Off/On Select Multiview On/Off
Internet software update Off Internet software update is Off
LightGuide Off/On Select LightGuide On/Off
Display fans Not present/Present Select Display fans Present/Not present
Temperature sensor No sensor/On backside/In display/
Temperature LUT 0 N.A.
Digital features Ethernet Off/On Select Ethernet On/Off
Display Screen 237 / LCD Sharp D3GA23 46" Displayed the panel code & type model
E-box & monitor Off/On Select E-box & monitor On/Off
Video reproduction Light sensor Off/On Select Light sensor On/Off
Light sensor type 0/1/2/3 Select Light sensor type form 0 to 3 (for difference
styling)
Super resolution Off/On Super resolution Off/On
rameters
equipment
equipment
Perfect Pixel HD
Pixel Precise HD
HD Natural Motion
2 sided 3/3
2 sided 4/4
2 sided 5/5
2 sided 6/6
2 sided 7/7
3 sided 5/5/5
3 sided 6/6/6
3 sided 7/7/7
3 sided 6/9/6
Smart bit enhancement Off/On Smart bit enhancement Off/On
Pixel Plus type Pixel Plus HD Select type of picture improvement
Natural motion type Perfect Natural Motion Natural motion type selection
Ambilight None Select type of Ambilight modules use
Ambilight sunset Off/On Ambilight sunset On/Off
Audio reproduction Acoustic system Cabinet design used for setting dynamic audio pa-
Source selection EXT1/AV1 type SCART CVBS RGB LR Select input source when connected with external
CVBS Y/C YPbPr LR
CVBS Y/C YPbPr HV LR
CVBS LR
EXT2/AV2 type SCART CVBS RGB LR Select input source when connected with external
YPbPr LR
equipment
None
CVBS
CVBS LR
CVBS Y/C LR
YPbPr
YPbPr LR
EXT3/AV3 type None Select input source when connected with external
YPbPr HV LR
SIDE I/O Off/On Select SIDE I/O On/Off
S-VIDEO (Y/C) Off/On Select S-VIDEO (Y/C) On/Off
HDMI 2 Off/On Select HDMI 2 On/Off
HDMI 3 Off/On Select HDMI 3 On/Off
HDMI side Off/On Select HDMI side On/Off
HDMI CEC Viewport 21:9 Off/On Select HDMI CEC Viewport 21:9 On/Off
HDMI CEC OneUX seamless Off/On Select HDMI CEC OneUX seamless On/Off
AP-PAL-Multi
China
Australia
Latam
Russia
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Tuner type Select type of Tuner used
Hotel mode Off Hotel mode is Off
Miscellaneous Region Europe Select Region/country
Options Digital broadcast DVB Off/On Select DVB On/Off
Main Menu Sub-menu 1 Sub-menu 2 Sub-menu 3 Description
Page 40
to 4
5 to 8
Select Store in the SAM root menu after making any
changes
can reset the “”Display operation hours” to “0”. So,
this one does keeps up the lifetime of the display it-
self (mainly to compensate the degeneration behav-
iour)
lation
stick
the TV
code after SSB replacement
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Alignments
Main Menu Sub-menu 1 Sub-menu 2 Sub-menu 3 Description
EN 40 Q551.1L LA6.
Option numbers Group 1 e.g. “00008.01793.15421.08192” The first line (group 1) indicates hardware options 1
Clear
Test reboot
Test cold reboot
Test application crash
Clear
QAM modulation: None Display information is for development purposes
Symbol rate:
Original network ID: 0
Network ID: 0
Transport stream ID: 0
Service ID: 0
Hierarchical modulation: 0
Selected video PID: 0
Selected main audio PID: 0
Selected 2nd audio PID: 0
Group 2 e.g. “44013.34315.00000.00000” The second line (group 2) indicates software options
Store Store after changing
Initialise NVM N.A.
Store
Operation hours display 0003 In case the display must be swapped for repair, you
Software maintenance Software events Display Display information is for development purposes
Hardware events Display Display information is for development purposes
Test setting Digital info Centre frequency: 774605208
Install start frequency 000 Install start frequency from “0” MHz
Digital + Analogue
Acoustics parameters ACSTS
0.39.6.16
PQ - TV550 1.0.22.1
PQS- Profile set
PQF - Fixed settings
PQU - User styles
Ambilight parameters PRFAM 5.0.2.4
Initial main software
NVM version Q55x1_0.3.1.0
Flash units software
Temp com file version none
Install end frequency 999 Install end frequency as “999” MHz
Default install frequency
Installation Digital only Sele ct Digital only or Digital + Analogue before instal-
Development 1 file version Display parameters DISPT6.0.9.8 Display information is for development purposes
Development file ver-
sions
Development 2 file version 12NC one zip software Display information is for development purposes
Upload to USB All To upload several settings from the TV to an USB
Channel list
Personal settings
Option codes
Alignments
Identification data
History list
Channel list
Personal settings
Option codes
Alignments
Identification data
AG code see type plate
Download from USB All To download several settings from the USB stick to
NVM editor Type number see type plate NVM editor; re key-in type number and production
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2010-Oct-01
Circuit Descriptions
7.1 Introduction
The Q551.1L LA is a new chassis launched in 2010. The whole
range is covered by PNX8550x main IC so-called NXP TV550
platform.
The major deltas versus its predecessor Q543/Q548 are the
DVBS, DLNA1.5+, Wireless Laptop Live (WLL-Dongle),
Ethernet, and WiFi Ready (Net-TV) functionality. The Q551.1L LA chassis comes with the following stylings:
• Monet
• Rubens 21:9.
Key components of this chassis are:
• PNX85500 System-On-Chip (SOC) TV Processor
7.1.1 Implementation
.
controller
together with LCD panel on a so-called “200 Hz board”).
• TX31XX Hybrid Tuner (DVB-T/C, analogue)
• STV6110AT DVB-S tuner
• SII9x87 HDMI Switch
• TPA312xD2PWP Class D Power Amplifier
• LAN8710 Dual Port Gigabit Ethernet media access
• PNX51x0 Video back-end Processor (optional; comes
7.1.2 TV550 Architecture Overview
For details about the chassis block diagrams refer to chapter 9.
Block Diagrams. An overview of the TV550 architecture can be
found in Figure 7-1
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Figure 7-1 Architecture of TV550 platform (basic)
Index of this chapter:
7.1 Introduction
7.2 Power Supply
7.3 Backlight Concept
7.4 DC/DC Converters
7.5 Front-End Analogue and DVB-T, DVB-C; ISDB-T reception
7.6 Front-End DVB-S(2) reception
7.7 HDMI
7.8 Video and Audio Processing - PNX85500
7.9 Back-End
7.10 Ambilight
7.11 TCON
7. Circuit Descriptions
are described.
to different set executions.
• Figures can deviate slightly from the actual situation, due
Notes:
•Only new circuits (circuits that are not published recently)
• For a good understanding of the following circuit
descriptions, please use the wiring, block (see chapter
9. Block Diagrams) and circuit diagrams (see chapter
10. Circuit Diagrams and PWB Layouts).Where necessary,
you will find a separate drawing for clarification.
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Tuner
CI
IO
8994x
N-DVBS Connector
8981x
IO
8952 x
DC/DC
Class-D
8951x
PNX85500
8950 x
6451x
DDR4 (512)
8953x
N-DVBS
LVDS
8957x
18770_257_100427.eps
100428
Circuit Descriptions
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Figure 7-2 Architecture of TV550 platform (200 Hz)
Figure 7-3 SSB layout cells (top view) (non-DVBS without TCON)
EN 42 Q551.1L LA7.
7.1.3 SSB Cell Layout
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Circuit Descriptions
- IPB: High voltage to the LCD panel
• Output to the display; in case of
- PSL and PSLS (LED-driver outputs)
- PSDL (high frequent) AC-current.
7.2.2 Diversity
The diversity in power supply units is mainly determined by the
diversity in displays. Refer to the Spare Parts list for the correct
order number.
- side-view LED without scanning: PSL power board
- side-view LED with scanning: PSLS power board
- direct-view LED without 2D-dimming: PSL power board
- direct-view LED with 2D-dimming: PSDL power board.
with added Scanning functionality (added microcontroller).
The following displays can be distinguished:
• CCFL/EEFL backlight: power board is conventional IPB
• LED backlight:
PSLS stands for a Power Supply with integrated LED-drivers
PSL stands for Power Supply with integrated LED-drivers.
with 2D-dimming.
PSDL stands for a Power Supply for Direct-view LED backlight
2010-Oct-01
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Refer to Figure 7-4 for the power architecture of this platform.
7.2 Power Supply
Figure 7-4 Power Architecture TV550 platform
7.2.1 Power Supply Unit
All power supplies are a black box for Service. When defective,
a new board must be ordered and the defective one must be
returned, unless the main fuse of the board is broken. Always
replace a defective fuse with one with the correct
specifications! This part is available in the regular market.
Consult the Philips Service web portal for the order codes of the
boards.
PSDL)
Important delta’s with the TV543 platform are:
• New power architecture for LED backlight (PSL, PSLS,
• “Boost”-signal is now a PWM-signal + continuous variable.
The control signals are:
• Stand-by
• Lamp “on/off”
• DIM (PWM) (not for PSDL)
• Boost (PWM except for IPB)
• Power-OK: indicates that the main converter is functioning
(feedback signal to the SSB).
In this manual, no detailed information is available because of
design protection issues.
The output voltages to the chassis are:
• +3V3-STANDBY (Stand-by mode only)
• +12V (on-mode)
• +Vsnd (+24V) (audio power) (on-mode)
• +24V (bolt-on power) (on-mode)
Page 44
scanning)
18750_202_100415.eps
100423
BacklightBoost
PNX
85500
1M99
BacklightPW M
Lamp
-
ON
PSL
BackLight
SideLED
Current
PWM
1G511G50
Tcon 200 Hz
Sharp
PNX
5120
LVD S spli tter
1G51
PNX
5120
ASIC
SSB TV 550
18750_203_100415.eps
100415
BackLight
DirectLED
scanning
SSB TV 550
BacklightBoost
PNX
85500
1M99
BacklightPW M
Lamp
-
ON
PSLS
Tcon 100Hz
Sharp
Current
PWM
1G5 11G50
1G5 11G50
ASIC
18750_204_100415.eps
100415
BacklightBoost
PNX
85500
1M99
BacklightPW M
Lamp
-
ON
PSL
BackLight
SideLED
Current
PWM
1G511G50
Tcon 20 0H z
LGD
PNX
5120
LVD S spli tter
1G5 1
PNX
5120
ASIC
SSB TV 550
dimming)
Circuit Descriptions
EN 44 Q551.1L LA7.
7.2.3 Connector overview
Connector
Table 7-1 Connector overview
no. 1308 1311 1M95 1M99 1M09 1MP1
Figure 7-6 Backlight application (xxPFL9xxx sets 32" 100 Hz “0D”
for additional
Figure 7-7 Backlight application (xxPFL9xxx sets 37" 200 Hz “0D”
back to
div. table
dimming)
Descr. Mains Mains to SSB to SSB Amb. T-con
Pin CN1 CN2 CN5 CN6 CN7 CN8
1 N L’ 3V3std +12V 24Vb +12V
2 L L” Stndby +12V 24Vb +12V
3 - - GND1 GND1 GND1 n.c.
4 - - GND1 GND1 GND1 GND1
5 - - GND1 BL_ON_OFF - GND1
6--+12V DIM - -
7 - - +12V Boost - -
8--+12V n.c. - -
9--+VsndPOK - -
10 - - GND_SND - - -
11 - - n.c. - - -
12------
The following backlight applications are implemented:
• Basic (xxPFL8xxx sets)
• xxPFL9xxx sets 32" 100 Hz “0D” scanning
• xxPFL9xxx sets 37" 200 Hz “0D” dimming
• xxPFL9xxx sets 40" & 46" 200 Hz “2D” scanning
• xxPFL9xxx sets 58" 21:9 (3-d) 200 Hz “2D” scanning.
7.3 Backlight Concept
The backlight application determines which power board has to
information.
be used. Refer to section 7.2.2 Diversity
Figure 7-5 Backlight application (xxPFL8xxx sets 200 Hz “0D”
2010-Oct-01
Page 45
EN 45Q551.1L LA 7.
18750_205_100415.eps
100423
BL-I2S
Current
BacklightBoost
Lamp
-
ON
PSDL
Tcon 200 Hz
Sharp
1F53
PNX
85500
1M99
1G511G5 0
BackLight
DirectLED
scanning
PWM
2D-D IM
I2S / SPI
PNX
5120
LVD S spli tter
1G51
PNX
5120
ASIC ASIC
SSB TV 550
18750_206_100415.eps
100423
BL-I2S
Current
BacklightBoost
Lamp
-
ON
PSDL
Tcon 200 Hz 3D
Sharp
1F53
PNX
85500
1M99
1G511G5 0
BackLight
DirectLED
scanning
PWM
2D-D IM
I2S / S PI
PNX
5120
LVD S spli tter
1G51
PNX
5120
ASIC ASIC
SSB TV 550
FPGA
18750_209_100415.eps
100416
AC
in
380 to
400 V
DC
Balancing 1
Balancing 2
Balancing 3
Balancing n
Power
Conversion 1
Power
Conversion 2
DC to LED-drivers)
Rectifier
Resonant
topology
Dr iver-part
Backlight-unit
(LED-strings)
Part of Power Supply Part of Display
18750_210_100415.eps
100416
AC
in
380 to
400 V
DC
Balancing 1
Balancing 2
Balancing 3
Balancing n
Power
Conversion 1
Power
Conversion 2b
DC to LED-drivers)
Power
Conversion 2a
DC to LED-drivers)
Rectifier
Resonant
topology
Dr iver-part
Backlight-unit
(LED-strings)
Part of Power Supply Part of Display
2010-Oct-01
and Figure 7-11 for the application.
Circuit Descriptions
Some sets use an alternative “balancing” concept
with the use of
• C-balance drivers, or
• L-balance drivers (currently not implemented).
This introduces the “C-balancer board” for some of the
xxPFL9xxx sets.
controller, LED/IR receiver and controls; connector 1M95
pin 1
(active mode); connector 1M95 pins 6, 7 and 8
mode); connector 1M09 pins 1 and 2
up first and switched "off" last (diagram B03B)
• +1V1, core voltage supply for PNX85500; has to be started
• +1V2, supply voltage for analogue blocks inside
PNX85500
displays in combination with “2D” dimming
C-balancing Concept for LED driving
The advantages of the C-balancing concept are:
• Cost reduction
• Higher efficiency
• Higher reliability, because of less components used.
The C-balance drivers and -components are mounted on a
separate C-balancer board. This PWB is mounted on the LCD
panel by the LCD manufacturer, though developed by Philips.
There are two possible configurations:
• For edge-lit displays & direct-lit displays + “0D” dimming
• For direct-lit displays + “2D” dimming.
Refer to Figure 7-10
Figure 7-10 Balancing LED-drivers application for edge-lit
Figure 7-11 Balancing LED-drivers application for direct-lit
displays & direct-lit displays in combination with “0D” dimming
“2D” scanning)
The on-board DC/DC converters deliver the following voltages
(depending on set execution):
• +3V3-STANDBY, permanent voltage for the Stand-by
• +12V, input from the power supply for TV550 common
• +24V, input from the power supply for DVB-S2 (in active
7.4 DC/DC Converters
PNX85500 (see diagram B03E)
• +3V3, general supply voltage (diagram B03E)
• +1V8, supply voltage for DDR2 (diagram B03B)
• +5V, supply voltage for USB and CAM (diagram B03E)
• +2V5, supply voltage for analogue blocks inside
• +5V-TUN, supply voltage for tuner (diagram B03E)
back to
div. table
200 Hz “2D” scanning)
The traditional concept for the LED drivers uses
• Linear drivers, or
• DC/DC drivers.
Figure 7-8 Backlight application (xxPFL9xxx sets 40" & 46" 200 Hz
Figure 7-9 Backlight application (xxPFL9xxx sets 58" 21:9 (3-d)
7.3.1 LED Drivers
This concept has been explained in previous Service Manuals.
Page 46
+5V-TUN
stab ilizer
+2V5
stab ilizer
+1V2
stab ilizer
18770_227_100127.eps
100426
+24V
+5V
+5V
+3V3 tuner
537.1 mA 777.4 mA 296 mA
+V-LNB +3V3 tuner +2V5
400 mA 90 mA
+V-LNB LNB-RF1
+5V
+1V0
400 mA 1820 m A
+1V0
+3V3
stab ilizer
down
converter
+2V5
stab ilizer
linear
stab ilizer
18770_235_100127.eps
100219
dc-dc
region
+5V
dc-dc
Figure 7-13 DC/DC converters DVB-S2 devices
The Front-End for the European/Asia Pacific region consist of
ISDB-T reception
the following key components:
(8 MHz) (Asia Pacific)
• Hybrid Tuner
• Switchable SAW filter 7/8 MHz (Eur.), or single SAW filter
DVB-C channel decoder and analogue demodulator.
• Bandpass filter
•Amplifier
• PNX85500 SoC TV processor with integrated DVB-T and
Below find a block diagram of the front-end application for this
region.
digital terrestrial TV standard
The Front-End for the Latin American region consist of the
following key components:
• Hybrid Tuner with integrated SAW filter and amplifier
• External ISDB-T channel decoder covering the Brazilian
• Bandpass filter
•Amplifier
• PNX85500 SoC TV with integrated analogue demodulator.
Below find a block diagram of the front-end application for this
region.
Figure 7-14 Front-End block diagram European/Asia Pacific
7.5 Front-End Analogue and DVB-T, DVB-C;
Circuit Descriptions
EN 46 Q551.1L LA7.
• +V-LNB, input voltage for LNB supply IC (item no. 7T50)
• +5V-DVBS, input intermediate supply voltage for DVB-S2
(diagram B08A)
channel decoder
• +3V3-DVBS, clean voltage for silicon tuner and DVB-S2
• +2V5-DVBS, clean voltage for DVB-S2 channel decoder
• +1V-DVBS, core voltage for DVB-S2 channel decoder.
A +12 V under-voltage detector (see diagram B03C) enables
the 12V to 3.3V and 12V to 5V DC/DC converters via the
ENABLE-3V3-5V line, and the 12V to 1.8V DC/DC converter
via the ENABLE-1V8 line. DETECT2 is the signal going to the
Stand-by microcontroller and ENABLE-3V3n is the signal
coming from the Stand-by microcontroller.
Diagram B03D contains the following linear stabilizers:
• +2V5 stabilizer, built around item no. 7UCO
7.5.1 European/Asia Pacific region
item no. 7T04
• +5V-TUN stabilizer, built around items no. 7UA6 and 7UA7
• +1V2 stabilizer, built around items no. 7UA3 and 7UA4.
Diagram B08A contains the DVB-S2-related DC/DC
converters and -stabilizers:
• a +24V under-voltage detection circuitry is built around
• the switching frequency of the 24 to 14...20V switched
mode converter is 350 kHz (item no. 7T03 and +V-LNB
lines)
(item no. 7T50)
the V0-CNTRL line
switched mode converter is 900 kHz (item no. 7T00)
• the output signal on the +V-LNB line goes to the LNBH23Q
• the LNBH23Q (item no. 7T50) sends a feedback signal via
• the switching frequency of the +5V-DVBS to +1-DVBS
• a delay line for the +2V5-DVBS and +1V-DVBS lines is
7.5.2 Latin American region
back to
div. table
100426
18770_226_100127.eps
+5V5-TUN +5V-TUN
196 mA
2179 mA 196 mA
+5V5-TUN
+5V
+5V
created with item no. 3T03 (R=10k) and 2T06 (C=100n)
• a 3.3V to 2.5V linear stabilizer is built around item no. 7T01
• a 5V to 3.3V linear stabilizer is built around item no. 7T02.
Diagram B08B contains the DVB-S2 LNB supply:
• the +V-LNB signal comes from item no. 7T03
• the V0-CTRL signal goes to item no. 7T03
• the LNB-RF1 goes to the LNB.
Figures gives a graphical representation of the DC/DC
converters with its current consumptions:
+3V3 +2V5
dc-dc
+3V3
+12V +3V 3
2919 mA 2371 m A 450 mA
+1V8 +1V2
2450 mA 550 mA
+1V8
dc-dc
+1V8
dc-dc
5100 mA
+1V1
+1V1
dc-dc
Figure 7-12 DC/DC converters non-DVB-S2 devices
2010-Oct-01
Page 47
EN 47Q551.1L LA 7.
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1
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1
8770_243_100203.eps
100203
Circuit Descriptions
2010-Oct-01
C addresses are:
2
Figure 7-17 HDMI input configuration
The following multiplexers can be used:
• Sil9187A (does not support “Instaport” technology for fast
switching between input signals)
switching between input signals).
• Sil9187A: 0xB0/0xB2 (random: software workaround)
• Sil9287B: 0xB2 (fixed).
The Sil9x87 has the following specifications:
• +5V detection mechanism
• Stable clock detection mechanism
• Sil9287B (supports “Instaport” technology for fast
The hardware default I
• Integrated EDID
• RT control
• HPD control
• Sync detection
on the SSB.
• TMDS output control
• CEC control
• EDID stored in Sil9x87, therefore there are no EDID pins
The PNX85500 is the main audio and video processor (or
System-on-Chip) for this platform. It has the following features:
MPEG-4)
• Multi-standard digital video decoder (MPEG-2, H.264,
• Integrated DVB-T/DVB-C channel decoder
• Integrated CI+
• Integrated motion accurate picture processing (MAPP2)
• High definition ME/MC
• 2D LED backlight dimming option
• Embedded HDMI HDCP keys
• Extended color gamut and color booster
• Integrated USB2.0 host controller
PNX8543
• Improved MPEG artefact reduction compared with
• Security for customers own code/settings (secure flash).
The TV550 combines front-end video processing functions,
such as DVB-T channel decoding, MPEG-2/H.264 decode,
analog video decode and HDMI reception, with advanced
back-end video picture improvements. It also includes next
generation Motion Accurate Picture Processing (MAPP2). The
MAPP2 technology provides state-of-the-art motion artifact
reduction with movie judder cancellation, motion sharpness
7.8 Video and Audio Processing - PNX85500
back to
div. table
for
Figure 7-15 Front-End block diagram Latin American region
The Front-End for the DVB-S(2) application consist of the
following key components:
7.6 Front-End DVB-S(2) reception
C address 0x14
2
C address 0xD0
2
C address 0xC6 (bridged via channel
2
decoder)
• Channel decoder; I
• Satellite Tuner; I
• LNB switching regulator; I
DVB-C channel decoder and analogue demodulator.
• Amplifier
• PNX85500 SoC TV processor with integrated DVB-T and
Below find a block diagram of the front-end application for
DVB-S(2) reception.
13V = vertical)
band, tone “off” = “low” band
and DVB-S2 (supporting QPSK, 8PSK, 16APSK and
32APSK encoded signals), introducing LDPC low-density
parity check techniques.
This application supports the following protocols:
• Polarization selection via supply voltage (18V = horizontal,
• Band selection via “toneburst” (22 kHz): tone “on” = “high”
• Satellite (LNB) selection via DiSEqC 1.0 protocol
• Reception of DVB-S (supporting QPSK encoded signals)
In this platform, the Silicon Image Sil9x87 HDMI multiplexer is
implemented. Refer to figure 7-17 HDMI input configuration
the application.
Figure 7-16 Front-End block diagram DVB-S(2) reception
7.7 HDMI
Page 48
18770_241_100201.eps
100219
TS out/in for
TS input
CVBS, Y/C,
LVDS for
analog CVBS
SPDIF
Low-IF
SSIF, LR
HDMI
CI/CA
MPEG
PRIMARY
LVDS
VIDEO
SECONDARY
MEMORY
VIDEO
3D COMB
DIGITAL IF
AUDIO DEMOD
AUDIO IN
HDMI
SCALER,
AUDIO DSP
AUDIO DACS
AUDIO OUT
450 MHz
560 MHz
I
2
C
PWM
GPIO IR ADC UART I
2
C GPIO Flash
analog audio
I
2
S
SPDIF
SYSTEM
USB 2.0
PNX85500x
DVB-T/C
channel decoder
DVB
AV-PIP
SPI
MPEG/H.264
RECEIVER
(8051)
CONTROLLER
AND DECODE
DECODER
PCMCIA
RGB
PROCESSOR
SYSTEM
CONTROLLER
DECODER
VIDEO
24KEf CPU
MIPS32
x 8
AV-DSP
REDUCTION
AND NOISE
DE-INTERLACE
OUTPUT
VIDEO
SUB-PICTURE
ENCODER
OUTPUT
VIDEO
quad channel)
(single, dual or
flat panel display
DRAWING
ENGINE
DMA BLOCK
Motion-accurate
pixel processing
SD
Memory
Card
Ethernet
MAC
support is available for 2D dimming in combination with LED
backlights for optimum contrast and power savings up to 50%.
Circuit Descriptions
.
For a functional diagram of the PNX85500, refer
to Figure 7-18
Figure 7-18 PNX85500 functional diagram
back to
div. table
EN 48 Q551.1L LA7.
and vivid color management. High flat panel screen resolutions
and refresh rates are supported with formats including 1366 ×
768 @ 100Hz/120Hz and 1920 × 1080 @ 100Hz/120Hz. The
combination of Ethernet, CI+ and H.264 supports new TV
experiences with IPTV and VOD. On top of that, optional
2010-Oct-01
Page 49
EN 49Q551.1L LA 7.
18770_209a_100202.eps
100202
1M5
9
1M09
MTK
or
PNX85500
SSB
Glue
logic
1M8
3
1M8
4
AmbiLight
1M8
3
1M8
4
AmbiLight
1M09
PSU
18750_207_100415.eps
100415
1
8770_210_100126.eps
100126
3×6
L
E
D
18
4×6
L
E
D
24
5×6
L
E
D
30
4+5
L
E
D
9
2×6
L
E
D
12
3×5
L
E
D
15
6×6
L
E
D
36
2010-Oct-01
Circuit Descriptions
back-end processor and has to be replaced entirely when
7.9 Back-End
defective (no component level repair). This board is not
described in this manual.
In some sets, a so-called “200 Hz” board is mounted together
with the LCD panel. This board contains the PNX51x0 Video
7.10 Ambilight
Figure 7-21 LED grouping per board
back to
div. table
Figure 7-20 Ambilight architecture 4-sided
Figure 7-19 Ambilight architecture 2- and 3- sided
.
For an overview of the LED grouping per board, refer to figure
Refer to figures 7-19 Ambilight architecture 2- and 3- sided.
7-21 LED grouping per board
Page 50
.
18770_211_100126.eps
100126
CPLD
PNX
SPI SPI + extra
1M59
18770_213_100126.eps
100219
LED
Driver
EEPROM
Buffer
SPI SPI
SPI
SPI
SPI
1M83
1M84
Extra
Tem p
sensor
Tem p
18770_215_100126.eps
100126
-T
+3V3
10n
2B09
FB40
2B08
10n
1K5 1%
36
3B39-2
27
3B39-3
1%1K5
1
3
4
52
LMV331IDCK
7B30
+3V3
1K5 1%
81
3B39-1
3B34
RES
100K
10K
3004
RES
3B11
10K
+3V3
FB41
TEMP-SENSOR
18770_216_100126.eps
100126
S
GND
Q
HOLD
W
VCC
C
D
+3V3
4
1
2
35
7B06
74LVC1G32GW
2B20
100n
4
7
2
1
8
3
+3V3
M95010-WDW6
7B07
(64K)
Φ
6
5
+3V3
10K
3B02-2
27
18
3B02-1
10K
+3V3
SPI-CLOCK-BUF
SPI-DATA-IN-BUF
SPI-DATA-RETURN
SPI-CS
DATA-SWITCH
Figure 7-25 Temperature sensor
The EEPROM (item no. 7B07; diagram AL1A) contains
alignment information about the mounted LEDs and is
programmed during the alignment process in production. Refer
to figure 7-26 EEPROM
.
Figure 7-26 EEPROM
The LED driver is built around item no. 7B26 (diagram AL1A)
and controls the LEDs. Refer to figure 7-27 LED driver
back to
div. table
100p
2B02
PWM-CLOCK-BUF
Circuit Descriptions
EN 50 Q551.1L LA7.
The communication between PNX85500, Complex
Programmable Logic Device (CPLD) and the Ambilight module
uses the SPI protocol; refer to figure 7-22 Communication
protocol outside LED board. Between the CPLD and the LED
driver, as “extra” line is mentioned:
• Non-SPI signals that are required for the LED driver
• Temperature sensor line.
Figure 7-22 Communication protocol outside LED board
Refer to figure for an overview of the communication inside the
LED board.
Figure 7-23 Communication protocol inside LED board
buffer.
The buffer is built around item no. 7B20 (diagram AL1A) and
regenerates the clock signals. Refer to figure 7-24 Ambilight
+3V3
100n
2B17
5
7B20-1
74LVC2G17
8
220R
3B30-1
1
6
2
1
33p
2B00
100R
3B01-2
27
PWM-CLOCK
7B20-2
74LVC2G17
+3V3
SPI-CLOCK-BUF
220R
3B30-43B01-1
45
4
25
3
33p
2B01
100R
18
SPI-CLOCK
100p
2B10
18770_214_100126.eps
.
Figure 7-24 Ambilight buffer
The temperature sensor is built around item no. 7B30 (diagram
AL1A) and indicates overtemperature of the board. Refer to
figure 7-25 Temperature sensor
2010-Oct-01
100126
Page 51
EN 51Q551.1L LA 7.
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100126
OUT
12
11
GSCLK
IREF
MODE
SCLK
SIN
SOUT
XERR
XHALF
XLAT 10
NC
9
8
VCC
012
34567
BLANK
131415
GND GND_HS
VIA
VIA
VIA
VIA
2K0
3B31
FB20
3B21
150R
+3V3
+3V3
25
32
FB35
9
10
11
14
15
1223
27
22
5
1617181920
21
678
31
30
33
24
26
3
121328
29
4
TLC5946RHB
7B26-1
100n
2B11
36
150R
3B00-3
2B04-4
100p
45
36
37
38
39
40
41
42
7B26-2
TLC5946RHB
34
35
3B18
1K8
18
150R
3B00-1
+3V3
18
2B04-1
100p
150R
3B00-4
45
150R
3B00-2
27
2B04-2
100p
27
36
2B04-3
100p
10K
3B22
BLANK
SPI-DATA-IN-BUF
PWM-G1
PWM-R1
PWM-G3
PWM-R3
PWM-R2
PWM-B2
PWM-G2
DATA-SWITCH
PWM-G4
PWM-R4
PWM-B4
PWM-R5
PWM-G5
PWM-B5
LATCH
SPI-DATA-IN
SPI-DATA-OUT
PWM-CLOCK-BUF
SPI-CLOCK-BUF
PROG
PWM-B1
PWM-B3
18770_218_100126.eps
100126
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
FB32
65
21
4
3
99-235/RSBB7C-A24/2D
7005
18
10K
3B07-1
FB30
3B07-3
10K
3645
FB31
10K
3B13-4
1
43
7002
99-235/RSBB7C-A24/2D
65
2
6
5
214
3
6
7004
99-235/RSBB7C-A24/2D
3B03-3
1K5
3
27
3B07-2
10K
+24V
100n
2B03
27
1K5
3B03-2
3B36
270R
+24V
2
6
1
BC847BS(COL)
7B23-1
3B35
270R
3B37
68R
5
3
4
BC847BS(COL)
7B23-2
7B25
BC847BW
1
3
2
36
3B13-3
10K
6
5
21
43
7001
99-235/RSBB7C-A24/2D
45
1K5
3B03-4
45
10K
3B07-4
7003
65
2143
99-235/RSBB7C-A24/2D
18
3B03-1
1K5
+24V
43
99-235/RSBB7C-A24/2D
7000
65
21
+24V
PWM-R1
PWM-G1
PWM-B1
2010-Oct-01
Circuit Descriptions
Figure 7-27 LED driver
.
The Overvoltage Protection Circuit is built around item no.
7B50, 7B51, 7C20 and 7C22 (diagram AL1B). Refer to figure
7-28 Overvoltage Protection Circuit
Figure 7-28 Overvoltage Protection Circuit
For the component placement on the LED PWD, refer to 7-29
back to
div. table
Component placement LED board.
Page 52
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100402
Opening
LED driver
Circuit Descriptions
Input connector
1M83
LED
EEPROM
Buffer
Figure 7-29 Component placement LED board
For the basic application, refer to figure 7-30 TCON
architecture.
Mini - LVDS
EEPROM
Timing
(10 bit)
LVDS
Contr oller
(TCON)
LCD Panel
+16 V
TFT – LCD Panel
Gate Drive IC
back to
div. table
Power
+12 V
(+28 V)
(-6 V)
GH
GL
V
V
TCONMain Platform
Block
Figure 7-30 TCON architecture
Source Drive IC
Control
Signals
Gamma
Refe re nce
Voltage
+3.3 V
+1.8 V
EN 52 Q551.1L LA7.
sensor
Temperature
This section describes the application with the TCON
integrated on the SSB.
7.11 TCON
PNX8550
SSB
diagram.
For the TCON block diagram, refer to figure 7-31 TCON block
2010-Oct-01
Page 53
18770_239_100127.eps
100127
LVD S
Receiver
LVD S
Receiver
Vertical & Horizontal
Timing generation
Data
Path
Block
(Line
Buffer)
M ini-LVDS
Transmitter
M ini-LVDS
Transmitter
OPC
(Optimum
Power
Control)
(Over
Drive
Circuit)
(Dynamic
Contrast
Control)
ODC DCA
Form atter/Serializer
Spread
Spectrum
SDRAM
I
2
C
Slave
I
2
C
Master
ROM
EEPROM
16 bit
H
sync
/
V
sync
DE
SS
CLK
(Spread Spectrum C lo c k)
RLV P/N
Right h alf
data
Gate Driver
Ctrl Signals
Source D riv e r
Ctrl Signals
R1A~E
R1CLK
R2CLK
R2A~E
Mini-
LVDS
Output
LVDS
Input
Control
Signal
Output
Timing Con tro ller IC
18770_240_100128.eps
100128
DC/DC
Controller
+12V
To G ate Drive rs (G ate
Low Voltage)
Tim ing Controller IC
Su p ply Vo ltag e
Tim ing Co ntroller IC
Su p ply Vo ltag e
+15V2
+15V6
Source Driver Supply
Voltage
EN 53Q551.1L LA 7.
2010-Oct-01
Voltage
.
Gate Enable - GOE, Gate Start Pulse - GSP).
column drivers and row drivers (Source Enable - SOE,
• Timing Control Function: generates control signals to
For an overview of the TCON DC/DC converters, refer to figure
7-32 TCON DC/DC converters
LGD SHP Where Used
High Voltage)
To G ate Drive rs (G ate
Gamma Reference
Circuit Descriptions
VGH +28V +35V
VGL -6V -6V
Vcc +3V3 +3V3
Vcc +1V8 +1V2
Vref +16V
Vdd +16V
back to
div. table
Figure 7-31 TCON block diagram
:
data and SYNC signals (Vsync, Hsync, Data Enable - DE)
• LVDS receiver: converts the data stream back into RGB
Notes to figure 7-31 TCON block diagram
block is delayed to align the column driver start pulse with
the column driver data
• ODC: Over Drive Circuit - to improve LC response
• Data Path Block: the video RGB data input to data path
Figure 7-32 TCON DC/DC converters
Page 54
Circuit Descriptions
C communication).
2
For Sharp - TCONs, the data can be flashed with a “SPI
For LGD - TCONs, the EEPROM can be programmed via
ComPair (via I
back to
div. table
Programmer” (via SPI communication). This device has to be
ordered separately.
EN 54 Q551.1L LA7.
7.11.1 TCON Programming
2010-Oct-01
Page 55
EN 55Q551.1L LA 8.
18770_301_100217.eps
100217
Block diagram
Pinning information
Note : The LED port indicators only apply to USB2513i.
To Upstream
V
BUS
3.3 V
Upstream
PHY
Upstream
USB Data
Repeater
Controller
Serial
Interface
Engine
Serial
Interface
To EEPROM or
SMBus Master
SCL
SDA
Port
Controller
Bus-
Power
Detect/
V
bus
Pulse
PHY#1
USB Data
Downstream
OC
Sense
Switch/
LED
Drivers
USB Data
Downstream
Port
Power
3.3 V
PLL
24 MHz
Crystal
Routing & Port Re-Ordering Logic
Regulator
CRFILT
Port
Power
Regulator
PHY#x
Port #x
OC Sense
Switch Driver/
LED Drivers
TT
#x
TT
#1
...
Port #1
OC Sense
Switch Driver/
LED Drivers
OC
Sense
Switch/
LED
Drivers
...
The ‘x’ indicates the number of available downstream ports: 2, 3, 4, or 7.
Ground Pad
(must be connected to VSS)
SMSC
USB2512/12A/12B
USB2512i/12Ai/12Bi
(Top View QFN-36)
26
VDD33
25
RESET_N
24
HS_IND / CFG_SEL[1]
23
SCL / SMBCLK / CFG_SEL[0]
22
SDA / SMBDATA / NON_REM[1]
21
NC
20
NC
19
VBUS_DET
27
NC
18NC17
OCS_N[2]16PRTPWR[2] / BC_EN[2]*
15
OCS_N[1]
14
VDD3313CRFILT12PRTPWR[1] / BC_EN[1]*11TEST10VDD33
SUSP_IND / LOCAL_PWR / NON_REM[0]
28
VDD33
29
USBDP_UP
31
XTALOUT
32
XTALIN / CLKIN
33
RBIAS
36
VDD33
35
PLLFILT
34
USBDM_UP
30
VDD33
1
USBDM_DN[1]
2
USBDP_DN[1]
3
USBDM_DN[2]
4
USBDP_DN[2]
5
NC
6
NC
7
NC
8
NC
9
Indicates pins on the bottom of the device.
electrical diagrams (with the exception of “memory” and “logic”
ICs).
2010-Oct-01
IC Data Sheets
8. IC Data Sheets
This chapter shows the internal block diagrams and pin
configurations of ICs that are drawn as “black boxes” in the
8.1 Diagram B01 820400090812 Tuner, HDMI & CI, USB2513B (IC 7F25)
back to
div. table
Figure 8-1 Internal block diagram and pin configuration
Page 56
18770_300_100217.eps
100217
Block diagram
Pinning information
LM75B
SDA
V
CC
SCLA0
OS
DNG1AA2
BIAS
REFERENCE
BAND GAP
TEMP SENSOR
OSCILLATOR
POWER-ON
RESET
11-BIT
SIGMA-DELTA
A-to-D
CONVERTER
POINTER
REGISTER
TIMER
COMPARATOR/
INTERRUPT
COUNTER
LOGIC CONTROL AND INTERFACE
CONFIGURATION
REGISTER
THYST
REGISTER
TOS
REGISTER
TEMPERATURE
REGISTER
LM75BDP
VADS
CC
0ALCS
1ASO
2ADNG
1
2
3
4
6
5
8
7
IC Data Sheets
Figure 8-2 Pin configuration
back to
div. table
EN 56 Q551.1L LA8.
8.2 Diagram B01 820400090812 Tuner, HDMI & CI, LM75BDP (IC 7FD1)
2010-Oct-01
Page 57
EN 57Q551.1L LA 8.
18770_308_100217.eps
100217
Block diagram
Pinning information
TS out/in for
TS input
CVBS, Y/C,
LVD S fo r
analog CVBS
SPDIF
Low-IF
SSIF, LR
HDMI
CI/CA
MPEG
PRIMARY
LVD S
VIDEO
SECONDARY
MEMORY
VIDEO
3D COMB
DIGITAL IF
AUDIO DEMOD
AUDIO IN
HDMI
SCALER,
AUDIO DSP
AUDIO DACS
AUDIO OUT
450 MHz
500 MHz
I
2
C
PWM
Px_x IR ADC UART I
2
C GPIO Flash
analog audio
I
2
S
SPDIF
SYSTEM
USB 2.0
PNX8550x
DVB-T/C
channel decoder
DVB
AV-PIP
SPI
RECEIVER
(8051)
CONTROLLER
AND DECODE
DECODER
PCMCIA
RGB
PROCESSOR
SYSTEM
CONTROLLER
MULTI-
STANDARD
VIDEO
DECODER
24KEf CPU
MIPS32
x 10
AV-DSP
REDUCTION
AND NOISE
DE-INTERLACE
OUTPUT
VIDEO
SUB-PICTURE
ENCODER
OUTPUT
VIDEO
quad channel)
(single, dual or
flat panel display
DRAWING
ENGINE
Scatter/Gather
TS Demux
Motion-accurate
pixel processing
SD
Memory
Card
Ethernet
MAC
analog Y/C
Direct-IF
PNX8550xE
Transparent top view
24681012
13
14
15 17
16
19
18 20
21
23
22 24
25
26
1357911
ball A1
index area
AB
AD
AA
AC
YWV
U
R
N
T
P
M
L
K
J
H
F
D
G
E
C
B
A
AF
AE
IC Data Sheets
2010-Oct-01
back to
div. table
Figure 8-3 Internal block diagram and pin configuration
8.3 Diagram B02 820400090822 PNX85500, PNX85500 (IC7S00)
Page 58
I_18020_142.eps
100402
Block diagram
Pinning information
1
2
3
4
5
6
7
8
9
101112
2423222120191817161514
13
PVCCLSDPVCCL
MUTE
LIN
RIN
BYPASS
AGND
AGND
PVCCR
VCLAMP
PVCCR
PGNDL
PGNDL
LOUT
BSL
AVCC
AVCC
GAIN0
GAIN1
BSR
ROUT
PGNDR
PGNDR
PWP (TSSOP) PACKAGE
(TOP VIEW)
1F
SD
PVCCL
TPA3120D2
PVCCR
VCLAMP
GAIN1
BYPASS
1F
1F
0.22 F
AGND
}
Control
Shutdown
Control
LIN
RIN
BSR
BSL
PGNDR
PGNDL
0.22 F
22 H
22 H
0.68 F
470 F
0.68 F
1F
470 F
GAIN0
AVCC
MUTE
ROUT
LOUT
IC Data Sheets
back to
div. table
Figure 8-4 Internal block diagram and pin configuration
EN 58 Q551.1L LA8.
8.4 Diagram B03 820400090892 CLASS D, TPA3120D2PWP (IC7D10)
2010-Oct-01
Page 59
EN 59Q551.1L LA 8.
18310_300_090319.eps
100416
Block diagram
Pinning information
VBST1
NC
EN1
VO1
VFB1
NC
GND
TEST1
NC
VFB2
VO2
EN2
NC
VBST2
DRVH1
LL1
DRVL1
PGND1
TRIP1
VIN
VREG5
V5FILT
TEST2
TRIP2
PGND2
DRVL2
LL2
DRVH2
28272625242322212019181716
123456789
1011121314
TPS53124
15
IC Data Sheets
2010-Oct-01
back to
div. table
8.5 Diagram B03 820400090892 CLASS D, TPS53126PW (IC7U03)
Figure 8-5 Internal block diagram and pin configuration
Page 60
I_18010_083.eps
100402
Block diagram
Pinning information
PowerSO-8
DFN8 (4 × 4)
back to
div. table
IC Data Sheets
EN 60 Q551.1L LA8.
Figure 8-6 Internal block diagram and pin configuration
8.6 Diagram B03 820400090892 CLASS D, ST1S10PH (IC 7UD0)
2010-Oct-01
Page 61
EN 61Q551.1L LA 8.
F_15710_166.eps
100402
Block diagram
Pinning information
2010-Oct-01
IC Data Sheets
8.7 Diagram B03 820400090892 CLASS D, LD1117DT25 (IC 7UD2)
LD1117DT
DPAK
Figure 8-7 Internal block diagram and pin configuration
back to
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Page 62
18770_302_100217.eps
100217
Block diagram
Pinning information
10M Rx
Logic
100M Rx
Logic
DSP System:
Clock
Data Recovery
Equalizer
Analog-to-
Digital
100M PLL
Squelch &
Filters
10M PLL
Receive Section
Central
Bias
HP Auto-MDIX
Management
Control
SMI
RMII / MII Logic
TXP / TXN
TXD[0:3]
TXEN
TXER
TXCLK
RXD[0:3]
RXDV
RXER
RXCLK
CRS
COL/CRS_DV
MDC
MDIO
LED1
LED2
LED Circuitry
MODE Control
nINT
nRST
RXP / RXN
10M Tx
Logic
10M
Transmitter
100M Tx
Logic
100M
Transmitter
Transmit Section
PLL
XTAL1/CLKIN
XTAL2
MODE0
MODE1
MODE2
PHY
Address
Latches
PHYAD[0:2]
Auto-
Negotiation
Interrupt
Generator
RMIISEL
MDIX
Control
Reset
Control
RBIAS
VDD2A
LED2/nINTSEL
LED1/REGOFF
XTAL2
XTAL1/CLKIN
VDDCR
RXD3/PHYAD2
RXCLK/PHYAD1
RXD2/RMIISEL
RXD1/MODE1
RXD0/MDE0
VDDIO
RXER/RXD4/PHYAD0
CRS
MDIO
COL/CRS_DV/MODE2
TXD2
MDC
nRST
nINT/TXER/TXD4
TXD0
TXEN
TXCLK
TXD1
RBIAS
TXD3
TXN
RXDV
RXN
VDD1A
TXP
RXP
1
2
3
4
5
6
7
8
SMSC
LAN8710/LAN8710i
32 PIN QFN
(Top View)
9
10
11
12
13
14
15
222120
191817
28
27
26
2516
24
23
32
31
30
29
VSS
IC Data Sheets
back to
div. table
Figure 8-8 Internal block diagram and pin configuration
EN 62 Q551.1L LA8.
8.8 Diagram B04 820400090832 Analog I/O, LAN8710A-EZKH (IC 7E10)
2010-Oct-01
Page 63
EN 63Q551.1L LA 8.
18770_303_100217.eps
100217
Block diagram
Pinning information
IC Data Sheets
2010-Oct-01
back to
div. table
Figure 8-9 Internal block diagram and pin configuration
8.9 Diagram B04 820400090832 Analog I/O, SII9287B (IC 7EC1)
Page 64
18770_309_100217.eps
100217
Block diagram
Pinning information
Bias
Control
8
1
7
4
V
O1
V
O2
V
DD
5
2
3
6
IN1−
BYPASS
SHUTDOWN
V
DD
/2
IN2−
−
+
−
+
1
2
3
4
8
7
6
5
V
O1
IN1−
BYPASS
GND
V
DDVO2
IN2−
SHUTDOWN
D OR DGN PACKAGE
(TOP VIEW)
IC Data Sheets
back to
div. table
Figure 8-10 Internal block diagram and pin configuration
EN 64 Q551.1L LA8.
8.10 Diagram B04 820400090832 Analog I/O, TPA6111A2DGN (IC 7EE1)
2010-Oct-01
Page 65
25P
1M84
(1074)
AL
AMBILIGHT MODULE 30 LED
25P
1M83
100813
18940_400_100810.eps
8584
8510
8151
8583
8120
1G50
1G51
1G51
1M59
1M20
41P
51P
51P
25P
1M09
8P
4P
SSB
3104 313 6451.x
(1011)
B
9P
1M99
11P
1M95
USBUSB
NET
ETHER
4P
1735
TUNER
EXT2
HDMI
VGA
HDMIHDMIHDMI
SPDIF
EXT1
Board Level Repair
Component Level Repair
8735
Only For Authorized Workshop
+ -
(5214)
SPEAKER LEFT
1. +24V
1M09 (B09A)
1. +VDISP
1G51 (B06B)
1735 (B03A)
1. LEFT-SPEAKER
2. +24V
3. GND
4. GND
2. +VDISP
3. +VDISP
4. +VDISP
2. GND-AUDIO
3. GND-AUDIO
4. RIGHT-SPEAKER
|
51. CTRL-DISP
EN 65Q551.1L LA 9.
8301
1M09
1MP1
8399
8395
(1004)
1820
IR/LED BOARD
(1012)
J
1M20
6P
J1
6P
8P
KEYBOARD CONTROL
51P
1G51
8735
LCD DISPLAY
200Hz BOARD
5P
1MP1
TO BACKLIGHT
Board is part of display
81P 81P 81P 81P
8408
1M95
1M99
11P
9P
4P
5P
2P3
8
0
3
1
2P3
1311
+ -
LEADING EDGE
2K10 ASSY
(1110)
INLET
2. GND
1. LIGHT-SENSOR
1M20 (B09A)
1. +12VD
2. +12VD
1M99 (B03C)
1. +3V3-STANDBY
1M95 (B03C)
2. STANDBY
14. N.C.
15. TEMP-SENSOR
3. RC
4. LED-2
3. GND
4. GND
3. GND
4. GND
16. GND
17. GND
5. +3V3-STANDBY
6. LED-1
7. KEYBOARD
5. LAMP-ON
6. BACKLIGHT-PWM_BL-VS
7. BACKLIGHT-BOOST
5. GND
6. +12V
7. +12V
18. GND
19. GND
20. GND
8. +5V
8. 3D-LR
9. POWER-OK
8. +12V
9. +24V-AUDIO-POWER
21. +24V
22. +24V
10. GND-AUDIO
11. MAINS-OK
23. +24V
24. +24V
25. +24V
back to
div. table
2010-Oct-01
8411
(8411)
MAINS
SWITCH
1. SPI-CLOCK-BUF
2. SPI-DATA-OUT
3. SPI-DATA-RETURN
4. GND
5. PWM-CLOCK-BUF
6. +3V3
7. SPI-CS
8. LATCH
9. GND
10. PROG
11. BLANK
12. +3V3
8191
1M84 (AL2A)
13. N.C.
Block Diagrams
9. Block Diagrams
WIRING DIAGRAM 40" 240Hz MONET
9-1 Wiring diagram Monet 40" - 46" 200 Hz
1316
1319
(5213)
SPEAKER RIGHT
6P
MAIN POWER SUPPLY
PSL 40 PLDE-P976AREV.1
(1050)
6P
(1074)
1M83
25P
AL
AMBILIGHT MODULE 30 LED
14. +3V3
15. BLANK
16. PROG
17. GND
18. LATCH
1. +24V
2. +24V
3. +24V
4. +24V
1M83 (AL1A)
1M59 (B13)
5. +24V
15. AMBI-TEMP
16. GND
17. GND
18. GND
19. GND
1. AMBI-SPI-CLK-OUT
2. AMBI-SPI-SDO-OUT
3. AMBI-SPI-SDI-OUT-GI
4. GND
5. AMBI-PWM-CLK_B2
19. SPI-CS
20. +3V3
21. PWM-CLOCK
22. GND
23. SPI-DATA-RETURN
24. SPI-DATA-IN
25. SPI-CLOCK
6. GND
7. GND
8. GND
9. GND
10. GND
11. TEMP-SENSOR
12. N.C.
13. N.C.
20. GND
21. +24V
22. +24V
23. +24V
24. +24V
25. +24V
6. V-AMBI
7. AMBI-SPI-CS-OUTn_R2
8. AMBI-LATCH1_G2
9. GND
10. AMBI-PROG_B1
11. AMBI-BLANK_R1
12. V-AMBI
13. AMBI-LATCH2_DIS
14. AMBI-SPI-CS-EXTLAMPSn
Page 66
25P
1M84
(1073)
AL
AMBILIGHT MODULE 36 LED
25P
1M83
100930
8584
25P
1M83
50P
1L04
50P
1L03
AMBILIGHT MODULE 15 LED
(1070)
AL
50P
1L02
25P
1M84
1L01
C-BALANCE BOARD
50P
(1054)
BB
8735
8151
8583
41P
1G50
51P
1G51
23P
1M59
4P
SSB (NON) DVBS
1M09
8P
1M20
(5212)
SPEAKER
3104 313 6451.x
(1011)
B
9P
1M99
11P
1M95
USBUSB
NET
ETHER
4P
17354P1D38
TUNER
CINCH
HDMI
VGA
HDMI 1ECBHDMIHDMI
SPDIF
CINCH
1. +VDISP
1G51 (B06B)
1. LIGHT-SENSOR
1M20 (B09A)
1M95 (B03C)
1. +3V3-STANDBY
2. +VDISP
3. +VDISP
4. +VDISP
2. GND
3. RC
4. LED-2
2. STANDBY
3. GND
4. GND
|
51. N.C.
5. +3V3-STANDBY
6. LED-1
5. GND
6. +12V
7. KEYBOARD
7. +12V
8. +5V
8. +12V
15. AMBI-TEMP
1. AMBI-SPI-CLK-OUT
1M59 (B09A)
9. +24V-AUDIO-POWER
10. GND-AUDIO
11. MAINS-OK
16. GND
17. GND
18. GND
19. GND
20. GND
21. +24V
22. +24V
2. AMBI-SPI-SDO-OUT
3. AMBI-SPI-SDI-OUT-GI
4. GND
5. AMBI-PWM-CLK_B2
6. V-AMBI
7. AMBI-SPI-CS-OUTn_R2
8. AMBI-LATCH1_G2
1M99 (B03C)
1. +12VD
2. +12VD
3. GND
4. GND
5. LAMP-ON
23. +24V
24. +24V
25. +24V
9. GND
10. AMBI-PROG_B1
11. AMBI-BLANK_R1
6. BACKLIGHT-PWM_BL-VS
7. BACKLIGHT-BOOST
8. 3D-LR
12. V-AMBI
9. POWER-OK
18940_404_100928.EPS
13. AMBI-LATCH2_DIS
14. AMBI-SPI-CS-EXTLAMPSn
1. LEFT-SPEAKER
2. GND-AUDIO
3. GND-AUDIO
4. RIGHT-SPEAKER
1735 (B03A)
EN 66Q551.1L LA 9.
25P
1M83
50P
1L00
25P
1L11
8323
1L12
25P
AMBILIGHT MODULE 15 LED
(1071)
50P
AL
25P
1M84
1L04
1L03
50P
14P
1316
81P
14P
1319
LCD DISPLAY
(1004)
8321
14P
1L16
1F53
1G51
1G51
51P
51P
15P
200 Hz BOARD
Board is part of display
8320
14P
1L19
1F53
8P
8153
CN3
J1
81P
CN3
81P
CN2
81P
CN1
8P
1. GND.
2. PROT-0
3. GND
4. SPI-CS1
5. GND
1L11 (BB9)
KEYBOARD CONTROL
J2
8P
1. GND.
2. PROT-9
3. GND
4. +6VB
5. GND
1L12 (BB9)
1. N.C.
2. N.C.
3. VRES-
4. VRES-
5. VRES-
1L16 (BB9)
(1110)
LEADING EDGE ASSY
1. N.C.
2. N.C.
3. VRES+
4. VRES+
5. VRES+
1L19 (BB9)
6. SPI-DATA1
6. +3V3
6. VRES-
6. VRES+
7. GND
8. SPI-CLK1
7. GND
8. N.C.
7. VRES-
8. VRES-
7. VRES+
8. VRES+
9. GND
9. GND
9. VRES-
9. VRES+
10. SPI-CS2
11. GND
10. GND
11. GND
10. VRES-
11. VRES-
10. VRES+
11. VRES+
12. SPI-DATA2
13. GND
14. SPI-CLK2
13. GND
12. SPI-CLK3
14. SPI-DATA31
12. VRES-
13. VRES-
14. VRES-
12. VRES+
13. VRES+
14. VRES+
15. GND
15. GND
16. N.C.
17. GND
16. SPI-CS3
17. GND
18. N.C.
19. GND
20. +3V3
18. SPI-CLK4
19. GND
20. SPI-DATA4
21. GND
21. GND
22. +6V
23. GND
22. SPI-CS4
23. GND
24. PROT-9
25. GND
24. PROT-5
25. GND
back to
div. table
2010-Oct-01
8735
8684 8683
8395
11P
1M95
(5211)
SPEAKER
8408
(8408)
MAINS
SWITCH
INLET
308
1
3
2P
8191
25P
1M83
Block Diagrams
1L02
1L01
1L00
50P
50P
50P
15P
C-BALANCE BOARD
(1053)
BB
14P
1L10
8301
8P
1MP1
1316
8510
4P
1M09
8399
9P
1M99
8316
14P
8319
8322
1316
1322
1319
MAIN POWER SUPPLY
PSU DPS-300AP-59
3P
14P
(1050)
8P
1B20
AMBILIGHT MODULE 15 LED
(1072)
AL
25P
1M84
14P
1319
3P
1322
14. +3V3
15. BLANK
1. +24V
2. +24V
1M83 (AL1A,AL5A)
1. GND
2. +3V3
1L10 (BB1)
1316 (BB9)
1. VRES- / *N.C.
2. VRES- / *N.C.
3. VRES-
1319 (BB9)
1. VRES+ / *N.C.
2. VRES+ / *N.C.
3. VRES+
1. PROT-0
2. N.C.
3. PROT-9
1322 (BB9)
16. PROG
3. +24V
3. V-SYNC
17. GND
4. +24V
4. GND
4. VRES-
4. VRES+
18. LATCH
19. SPI-CS
20. +3V3
5. +24V
6. GND
7. GND
5. BL-SPI-CSn
6. GND
7. +3V3
5. VRES-
6. VRES-
7. VRES-
8. VRES-
5. VRES+
6. VRES+
7. VRES+
8. VRES+
1B20 (J1)
1. LIGHT-SENSOR
2. GND
21. PWM-CLOCK
22. GND
23. SPI-DATA-RETURN
24. SPI-DATA-IN
8. GND
9. GND
10. GND
11. TEMP-SENSOR
8. GND
9. BL-SPI-MOSI
10. GND
11. BL-SPI-CLK
9. VRES-
10. VRES-
11. VRES-
12. VRES-
9. VRES+
10. VRES+
11. VRES+
12. VRES+
3. RC
4. LED2
5. +3V3-STANDBY
6. LED1
25. SPI-CLOCK
12. N.C.
13. N.C.
12. GND
13. SCL-BL
14. SDA-BL
15. GND
13. VRES-
14. VRES-
13. VRES+
14. VRES+
7. KEYBOARD
8. +5V
*C-balance board on pos (1054)
8685
1M83
25P
WIRING DIAGRAM 58" 400 Hz RUBENS
9-2 Wiring Diagram Rubens 58"
(1075)
AL
AMBILIGHT MODULE 36 LED
IR/LED BOARD
J
(1114)
14. N.C.
15. TEMP-SENSOR
16. GND
1M84 (AL3A,AL8B)
1. SPI-CLOCK-BUF
2. SPI-DATA-OUT(2)
3. SPI-DATA-RETURN
17. GND
4. GND
18. GND
5. PWM-CLOCK-BUF
19. GND
6. +3V3
20. GND
21. +24V
7. SPI-CS
8. LATCH
22. +24V
9. GND
23. +24V
10. PROG
24. +24V
25. +24V
11. BLANK
12. +3V3
13. N.C.
Page 67
1G51
51
N.C.
49
50
SCL-DISP
SDA-DISP
B02E
44
3D-LR
B02E
B06C
40
43
CTRL-DISP
B02G
100813
SIDE USB
1P08
CONNECTOR
213
USB-DP2
USB-DM2
9F25
+1V8
4321
4
DDR2-D(0-31)
7B01
EDE1108AGBG
7B03
EDE1108AGBG
128MB
SDRAM
D(24-31)
128MB
SDRAM
D(16-23)
VREF
VDDL
VREF
VDDL
A1 E2A1 E2A1 E2A1 E2
DDR2-VREF-DDR
DDR2-A(0-13)
18940_401_100810.eps
TO
200Hz BOARD
342
40
1
+5V-USB2
+VDISP
VIDEO OUT - LVDS
B06B
LVD S
B02F
PX3
LVDS OUT
PX4
USB HUB
B01C
CONROL
B02E
9F26
USB-DP
USB-DM
R26
R25
USB_DN
USB_DP
7F20
NAND04GW3B2DN6F
FLASH
B01B
FLASH
B02A
NAND
FLASH
XIO-D(00-07)
XIO_D
512MB
+3V3
12,37
VCC
DDR
B05A
MEMORY
B02B
DQ
7B02
7B00
EDE1108AGBG
EDE1108AGBG
SDRAM
D(8-15)
SDRAM
D(0-7)
128MB
128MB
VREF
VDDL
VREF
VDDL
DDR2-VREF-CTRL3
DDR2-VREF-CTRL2
V1
A
A2
VREF_1
VREF_2
EN 67Q551.1L LA 9.
Block Diagrams
PNX85500
7S00
PNX85507EB
B02
19
7FE0
TC90517FG
VIDEO STREAM
B02A
25M4
1FE0
18
OF DM
DEMODULATOR
30929
IF+
IF-AGC
TNR_SER1_MIVAL
R23
TS-FE-VALID
585961
IF-
TNR_SER1_SOP
TNR_SER1_MICLK
TNR_SER1_DATA
T22
T21
R22
TS-FE-SOP
TS-FE-DATA
TS-FE-CLOCK
60
42
RESET-SYSTEMn
B02E
ANALOG VIDEO
B02I
IF-AGC
3F77
IF_AGC
AD12
AE12
PNX-IF-P
BANDPASS
3F79-1
2F75
AF12
PNX-IF-N
FILTER
3F79-4
2F79
PNX85500
AV1 _R
AC13
AV1 -R
18
1E01
ANALOGUE EXTERNALS A
Pr
B04A
AV1 _G
AE13
AV1 -G
14
EXT 1
AV1 _B
AD13
AVI -B
10
Y
Pb
1E02
PR_R_C2
AC14
AV4-PR
15
Pr
Y_G2
AE14
AV4 -Y
11
Y
EXT 2
PB_B2
AD14
AV4-PB
7
Pb
1E05
VGA
B01I
VGA_R
AF16
R-VGA
1
VGA_G
AD16
G-VGA
2
15
10
5
VGA_B
AE16
B-VGA
3
VSYNC_IN
HSYNC_IN
AB18
AC18
V-SYNC-VGA
H-SYNC-VGA
14
13
11
6
1
CVBS_Y2
AB14
AV2_CVBS
2
1E08
VGA
ANALOGUE EXTERNALS B
CONNECTOR
B04B
VIDEO
EXT 3
HDMI_DV
RX2_A_N
RXC_A_N
RXC_A_P
RX2_A_P
B02C
V26
V25
W26
W25
HDMIA-RX0-
HDMIA-RXC-
HDMIA-RX0+
HDMIA-RXC+
62616059585756
63
RX1_A_N
RX0_A_P
RX1_A_P
T25
U26
U25
HDMIA-RX1-
HDMIA-RX1+
HDMIA-RX2+
RX0_A_N
RREF
T26
W24
3S0W
+3V3
HDMIA-RX2-
back to
div. table
2010-Oct-01
TUNER BRAZIL
B01K
VIDEO
9-3 Block Diagram Video
TUNER
MAIN HYBRID
1T01
TX31XX
HDMI & CI
B01F
IF-AGC
9
4MHZ_REF
9F03
TUN-IF-P
10
IF-OUT1
RF IN
9F02
TUN-IF-N
11
IF-OUT2
HDMI
B04D
HDMI
B01H
7EC1
SII9287BCNU
RXD
90898786848381
DRX2-
DRX1-
DRX2+
DRX1+
6
1
3
4
1P05
1
DRX0-
DRX0+
9
7
10
18 2
19
DRXC+
HDMI
80
DRXC-
12
HDMI SIDE
CONNECTOR
INSTAPORT
SWITCH
23222019171614
ARX2-
ARX2+
1
3
1P04
1
ARX1+
4
RXA
ARX1-
6
7
ARX0-
ARX0+
9
18 2
19
13
ARXC+
10
12
HDMI 3
ARXC-
CONNECTOR
VCC33
42413939363533
9,27,64
BRX2+
1
+3V3-HDMI
1P03
BRX2-
3
1
BRX1+
6
4
RXB
BRX1-
7
BRX0-
BRX0+
9
18 2
19
32
BRXC+
10
12
HDMI 2
BRXC-
CONNECTOR
TX0_P
TX0_N
TXC_P
TXC_N
RXC
72716968666563
CRX2-
CRX1-
CRX2+
CRX1+
6
1
3
4
1P02
1
TX1_P
TX1_N
CRX0-
CRX0+
9
7
CRXC+
10
18 2
19
TX2_P
TX2_N
62
CRXC-
12
HDMI 1
CONNECTOR
Page 68
B01H
HDMI
B04D
HDMI
B02D
PNX85500: AUDIO
B02D
PNX 85500: AUDIO
B03A
AUDI O
B04E
HEADPHONE
B04B
ANALOGUE EXTERNALS B
B04A
ANALOGUE EXTERNALS A
B01J
TEMP SENSOR + HEADPHONE
B02
PNX85500
B01F
HDMI & CI
B05A
DDR
B01C
USB HUB
B01B
FLASH
B01K
TUNER BRAZIL
7S00
PNX85507EB
AUDI O
B02D
STANDBY
B03H
HDMI_DV
B02C
STANDBY
B02G
PNX85500
18940_402_100810.eps
100811
AD7
AE7
1735
1
2
SPEAKER L
3
4
SPEAKER R
SUBWOOFER
(RES)
ADAC(1)
ADAC(2)
+AUDIO-L
-AUDIO-R
RESET-AUDIO
AD1
AC19
ADAC(4)
AMP1
AMP2
ADAC(3)
HEADPHONE
OUT 3.5mm
AF7
AD6
7EE1
TPA6111A2DGN
HEADPHONE
AMPLIFIER
1
7
IN-1
SHUTDOWN
IN-2
2
6
5
A-PLOP
B03A
B03C
B03C
7D10
TPA3123D2PWP
CLASS D
POWER
AMPLIFIER
OUT-L
PVCC_L
PVCC_R
OUT-R
512
10
6
22
15
IN-R
IN-L
MUTE
SD
4
2
AUDIO-MUTE-UP
A-STBY
A-STBY
B04A
STANDBY &
PROTECTION
7D03
MAIN SWITCH
DETECT
7D03
LEFT-SPEAKER
RIGHT-SPEAKER
AE10
AF10
AD10
AC10
1E08
4
6
1E01
2
6
1E02
2
6
AUDIO-IN3-L
AUDIO-IN3-R
AE9
AF9
AUDI O IN
L+R
ADAC_2
PO_7
PO_6
ADAC3
ADAC4
ADAC_1
1328
231
7EE0-1 7EE0-2
1D38
1
2
3
DETECT2
MAINS-OK
AUDIO-IN2-R
AUDIO-IN2-L
AUDIO
AUDIO-IN1-L
AUDIO-IN1-R
5D03
7EC1
SII9287BCNU
HDMI
SWITCH
VCC33
RXC
RXD
RXB
RXA
72716968666563
62
42413939363533
32
23222019171614
13
90898786848381
80
19
1
18 2
1
1P05
347
9
10
12
6
DRX2+
DRX2-
DRX1+
DRX1-
DRX0+
DRX0-
DRXC+
DRXC-
HDMI SIDE
CONNECTOR
19
1
18 2
1
1P02
347
9
10
12
6
CRX2+
CRX2-
CRX1+
CRX1-
CRX0+
CRX0-
CRXC+
CRXC-
HDMI 1
CONNECTOR
1
1P03
347
9
10
12
6
BRX2+
BRX2-
BRX1+
BRX1-
BRX0+
BRX0-
BRXC+
BRXC-
1
1P04
347
9
10
12
6
ARX2+
ARX2-
ARX1+
ARX1-
ARX0+
ARX0-
ARXC+
ARXC-
19
1
18 2
HDMI 2
CONNECTOR
19
1
18 2
HDMI 3
CONNECTOR
14
ARC-eHDMI+
eHDMI+
9,27,64
+3V3-HDMI
8
+3V3
1,3
10,12
+24V-AUDIO-POWER
5D07
5D08
VDD
VO_1
VO_2
AD9
AC9
AUDIO-IN4-L
AUDIO-IN4-R
VGA (OR DVI)
AUDI O
1E09
231
AIN4_L
AIN4_R
AIN1_R
AIN2_L
AIN2_R
AIN3_L
AIN3_R
AIN1_L
VIDEO STREAM
B02A
ANALOG VIDEO
B02I
MEMORY
B02B
V1
DDR2-VREF-CTRL3
A2
DDR2-VREF-CTRL2
VREF_2
VREF_1
7S05
LM324P
14
8
1E07
1
AF5
AF18
DIGITAL
AUDI O
OUT
SPDIF-OUT-PNX
SEL-HDMI-ARC
SPDIF-OUT
214
5
3
8
SPDIF_OUT
P0_4
7S09
&
+3V3
A-PLOP
7D15
A-PLOP
B04E
CONROL
B02E
FLASH
B02A
7F20
NAND04GW3B2DN6F
NAND
FLASH
512MB
4321
USB-DM
USB-DP
USB-DM2
USB-DP2
SIDE USB
CONNECTOR
1P08
R26
R25
12,37
+3V3
VCC
USB_DP
USB_DN
+5V-USB2
XIO_D
213
4
9F26
9F25
XIO-D(00-07)
DDR2-VREF-DDR
A1 E2A1 E2A1 E2A1 E2
+1V8
SDRAM
128MB
7B01
EDE1108AGBG
SDRAM
128MB
7B02
EDE1108AGBG
SDRAM
128MB
7B03
EDE1108AGBG
DQ
A
SDRAM
128MB
7B00
EDE1108AGBG
VREF
VDDL
VREF
VDDL
VREF
VDDL
VREF
VDDL
DDR2-D(0-31)
D(24-31)
D(16-23)
D(8-15)
D(0-7)
DDR2-A(0-13)
5EC2
63
HDMIA-RXC-
HDMIA-RX0+
HDMIA-RX0-
HDMIA-RX1+
HDMIA-RX1-
HDMIA-RX2+
HDMIA-RX2-
62616059585756
HDMIA-RXC+
U26
T25
T26
W24
U25
V26
W26
W25
V25
RREF
+3V3
3S0W
TUNER_P
TUNER_N
AE12
IF_AGC
AD12
AF12
2F75
2F79
3F79-1
3F79-4
1T01
TX31XX
IF-OUT1
4MHZ
IF-OUT2
MAIN HYBRID
TUNER
PNX-IF-P
PNX-IF-N
11
10
RF IN
9
IF+
IF-
RESET-SYSTEMn
IF-AGC
BANDPASS
FILTER
TUN-IF-P
IF-AGC IF-AGC
TUN-IF-N
TNR_SER1_MIVAL
TNR_SER1_SOP
TNR_SER1_MICLK
TNR_SER1_DATA
TS-FE-VALID
TS-FE-SOP
TS-FE-CLOCK
TS-FE-DATA
R23
T22
R22
T21
7FE0
TC90517FG
OF DM
DEMODULATOR
30929
585961
60
42
9F03
9F02
1FE0
25M4
18
19
B02E
3F77
RX1_A_N
RX0_A_P
RX0_A_N
RX1_A_P
RX2_A_N
RXC_A_N
RXC_A_P
RX2_A_P
TXC_N
TXC_P
TX0_N
TX0_P
TX1_N
TX1_P
TX2_N
TX2_P
EN 68Q551.1L LA 9.
Block Diagrams
back to
div. table
2010-Oct-01
9-4 Block Diagram Audio
Page 69
B04D
HDMI
B02A
PNX85500
B09A
NON DVBS CONNECTOR BOARD
B06C
AMBILIGHT CPLD
B04C
ETHERNET + SERVICE
B09A
DVBS CONNECTOR BOARD
B01B
FLASH
B03C
DC / DC
B05A
DDR
B01E
PNX85500-CONTROL
B04C
ETHERNET + SERVICE
B02E
PNX85500: MIPS
B01C
USB HUB
B03C
DC / DC
B02G
PNX85500: STANDBY CONTROLLER
B02G
PNX85500: STANDBY CONTROLLER
CONTROL + CLOCK SIGNALS
B04B
ANALOGUE EXTERNALS B
B02E
ETHERNET
1M99
765
1M95
2
LED1
AD26
AE26
AA22
DETECT2
AA26
AF19
RESET-STBYn
4x HDMI
CONNECTOR
AB22
RESET-SYSTEMn
AD21
ENABLE-3V3n
PNX85500
7S00
PNX85507EB
AC25
LED2
1S02
54M
AF17
AE17
STANDBY
B02G
HDMI_DV
B02C
AD22
AV1 -BL K
AF20
STANDBY
AD19
AD23
KEYBOARD
RC
LIGHT-SENSOR
AB19
RESET-AUDIO
BACKLIGHT-PWM_BL-VS
BACKLIGHT-BOOST
AC21
POWER-OK
B03C
B06C
B01E
7S20
NCP303LSN28G
2
INP
1
OUTP
+3V3-STANDBY
GND
B02E
7EC1
SII9287ACNU
HDMI
SWITCH
P3_0
P3_1
P1_7
P6_4
P2_2
P2_7
P2_6
P0_6
P2_3
XTAL_I
XTAL_O
P5_1
P5_0
P3_2
P3_3
P3_5
P3_4
RESET_IN
P1_2
W24
RREF
HDMI_RX
P1_0
PWM_1
PWM_0
TO
POWER
SUPPLY
B04A
TO
POWER
SUPPLY
+3V3-STANDBY
+5V
B04E
B03C
SDM
SPI-PROG
AF22
AB20
FF04
FF29
18940_403_100811.eps
100930
RXD-UP
TXD-UP
AE21
AF21
LED-2
LED-1
1234567
8
1M20
7U43
ARX-HOTPLUG
AC22
AV2 -BL K
B04A
RESET-STBYn
AB17
B06B
P0_0
CTRL-DISP
AE18
RESET-ETHERNETn
B04C
P0_3
AF18
SEL-HDMI-ARC
B02D
P0_4
AE20
LAMP-ON
AC19
AUDIO-MUTE-UP
P0_7
B03A
V23
BOOST-PWM
GPIO10
B03C
BACKLIGHT-BOOST
9
8
3D-LR
B06C
31
BRX-HOTPLUG
CRX-HOTPLUG41DRX-HOTPLUG
45
35
PCEC-HDMI
CEC-HDMI
1
2
19
18
1P05-19
1P04-19
1P03-19
1P02-19
TO PIN:
1P02-13
1P03-13
1P04-13
1P05-13
FLASH
B02A
7F20
NAND04GW3B2DN6F
NAND
FLASH
512MB
12,37
+3V3
VCC
AA2
ETH-TXCLK
RXCLK
AA3
ETH-RXCLK
TXCLK
SDCD
SDWP
3
SPI_CLK
SPI_CSB
SPI_SDO
SPI_SDI
P6_5
7F52
M25P05-AVMN6P
FLASH
512K
8
+3V3-STANDBY
VCC
6
PNX-SPI-CLK
AF24
3
PNX-SPI-WPn
AE22
1
PNX-SPI-CSBn
AF23
5
PNX-SPI-SDO
AE23
2
PNX-SPI-SDI
AF25
CONTROL
+3V3-STANDBY
+12V
ENABLE -1V8
ENABLE -3V3-5V
DETECT2
ETH-TXD
ETH-RXD
XIO_D
B06C
+3V3
3S0W
TO IR / LED BOARD AND
KEYBOARD CONTROL
9U41
9CH0
B03E
B03B B03D
B02G B03A
EF
7EC0
7
20
19
RES
16
HDMIB-RC
1N00
BACKLIGHT-PWM_BL-VS
B03C B04CB04C
B06B
B03B
7
3D-LR
8
3D-VS-DISP
CONTROL
B02E
Y23
Y24
UART
SERVICE
CONNECTOR
RXD1-MIPS
TXD1-MIPS
1E06
231
AF1
SENSE+1V1
B03B
B02H
POWER
VDD_1V1
AA15
SENSE+1V2
B03D
VDDA_1V2
DDR-CLK_N
DDR-CLK_P
MEMORY
B02B
F8 E8F8 E8F8 E8F8 E8
SDRAM
128MB
SDRAM
128MB
SDRAM
128MB
DQ
A
CLK_N
CLK_P
GPI0_2
RESET-SYSTEMn
AE4
B02G B01K
RESET_SYS
V22
GPI0_7
GPI0_3
SDRAM
128MB
DDR2-D(0-31)
D(24-31)
D(16-23)
D(8-15)
D(0-7)
DDR2-A(0-13)
GPI0_11
SELECT-SAW
U23
B01F
BL_PWM
AD5
BACKLIGHT-PWM
CLK_54_OUT
AC5
PXCLK54
B02G
4321
USB-DM
USB-DP
USB-DM2
USB-DP2
SIDE USB
CONNECTOR
1P08
R26
R25
USB_DP
USB_DN
+5V-U
SB2
213
4
1M59
21358
7
1011141315
9F26
9F25
7GA0
XC9572XL
CPLD
26
VIO
VCCIO
43
3
PNX-SPI-CS-BLn
6
AMBI-SPI-CLK-OUT
22
AMBI-SPI-SDO-OUT
27
AMBI-SPI-SDI-OUT_G1
23
AMBI-PWM-CLK_B2
29
AMBI-SPI-CS-OUTn_R2
30
AMBI-LATCH1_G2
31
AMBI-PROG_B1
19
AMBI-BLANK_R1
20
AMBI-LATCH2_DIS
28
AMBI-SPI-CS-EXTLAMPSn
21
AMBI-TEMP
32
41
40
PNX-SPI-SDI
39
PNX-SPI-SDO
PNX-SPI-CLK
5
PNX-SPI-CSBn
7B01
H5PS1G83EFR
EDE1108AGBG
7B02
H5PS1G83EFR
EDE1108AGBG
7B03
H5PS1G83EFR
EDE1108AGBG
7B00
H5PS1G83EFR
EDE1108AGBG
1ECB
65
3
1
2
4
3D
CONNECTOR
W22
TXD2-MIPS
3D-VS
3D-LR
W21
RXD2-MIPS
GPI0_4
GPI0_5
B06C
+5V
3S4A
3D-VS
*
RESET-ETHERNETn
B02G
1E70
25M
AF17
AE17
XIO-D(00-07)
1F51
13452
LEVEL SHIFTED
FOR
DEBUG USE
ONLY
7E10
LAN8710A-EZK
ETHERNET
ETHERNET
CONNECTOR
RJ45
TO AMBILIGHT
MODULE
SDM
SPI_PROG
back to
div. table
EN 69Q551.1L LA 9.
Block Diagrams
2010-Oct-01
9-5 Block Diagram Control & Clock Signals
Page 70
I²C
PNX85500: MIPS
B02E
DDR
B05A
FLASH
B01B
ETHERNET + SERVICE
B04C
PNX85500: CONTROL
B01E
PNX85500-CONTROL
B01E
PNX85500: STANDBY
CONTROLER
B02G
HDMI
B04D
HDMI
B01H
TEMP SENSOR +
HEADPHONE
B01J
TUNER BRAZIL
B01K
HDMI & CI
B01F
PNX85500: ANALOG VIDEO
B02I
ETHERNET + SERVICE
B04C
VGA
B01I
VIDEO OUT - LVDS
B06B
NON DVBS CONNECTOR BOARD
B09A
1ECB
65
3
1
2
4
1F52
7S00
PNX85507EB
PNX85500
SDA-SSB
SCL-SSB
C25
C26
1_SDA
1_SCL
AC23
AC24
MC_SDA
MC_SCL
B25
A24
3_SDA
3_SCL
SDA-UP-MIPS
SCL-UP-MIPS
CONTROL
STANDBY
1
3
DEBUG
ONLY
18760_406_100810.eps
100813
RES
3F63
3F62
56
7F58
M24C64
EEPROM
(NVM)
3F60
3F59
TUN-P7
TUN-P6
SDA-TUNER
SCL-TUNER
76
1T01
TX31XX
MAIN
TUNER
3S60
3S61
3F75
3F76
53 54
7EC1
SII9287B
HDMI
MUX
3EC5
3EC3
HDMI
CONNECTOR 3
HDMI
CONNECTOR 2
1P04
16
15
29
30
1P03
16
15
33
34
1P02
16
15
39
40
HDMI
CONNECTOR
SIDE
1P05
16
15
3FBF-2
3FBF-1
DIN-5V
43
44
47
48
Y25
Y26
Y23
Y24
GPIO_2
GPIO_3
DDCA-SDA
DDCA-SCL
ARX-DDC-SDA
ARX-DDC-SCL
BRX-DDC-SDA
BRX-DDC-SCL
CRX-DDC-SDA
CRX-DDC-SCL
DRX-DDC-SDA
DRX-DDC-SCL
12
7FD1
LM75BDP
TEMP
SENSOR
3FD3
3FD4
46 45
7FE0
TC90517FG
DEMODULATOR
3FE9
3FE8
3S56
3S57
3S2F
3S2G
3S5Y
3S5Z
3S6D
3S6E
+3V3
3S69
3S6A
+3V3
3S6V
3S6W
+3V3-STANDBY
3S81
3S80
+3V3
1N00
3S83
3S84
+3V3
3S6F
3S6G
+3V3
AD25
AD24
1E05
12
15
VGA-SDA-EDID-HDMI
VGA-SCL-EDID-HDMI
VGA-SDA-EDID
VGA-SCL-EDID
3FC1
3FC2
+5V-VGA
9FC2
9FC4
9FC1
9FC3
RES
3S5V-1
3S5V-3
3EC1-1
3EC1-3
AIN-5V
3ECA-1
3ECA-2
BIN-5V
3ECA-3
3ECA-4
CIN-5V
3ECP-3
3ECP-1
+5V-EDID
3ECU-2
3ECU-4
+3V3
B24
Y5
Y6
AB4
AC1
AA3
11
10
987
A23
4_SDA
4_SCL
AE21
AF21
P3_0
P3_1
1
6
10
11
5
15
VGA
CONNECTOR
RXD1-MIPS
TXD1-MIPS
W21
W22
GPIO_2
GPIO_3
RXD2-MIPS
TXD2-MIPS
UART
SERVICE
CONNECTOR
1E06
321
3E53-3
3E53-1
3E53-4
3E53-2
1F51
1
3
B02E
B02G
MEMORY
B02B
FLASH
B02A
ANALOGUE
VIDEO
VGA_EDID_SDA
VGA_EDID_SCL
B02I
B02I
ERR
35
ERR
15
ERR
53
1M71
1
3
TO
TEMPERATURE
SENSOR
4
5
2D
DIMMING
1F53
2
3
SDA-BL
SCL-BL
LVD S
CONNECTOR
1G51
50
49
SDA-DISP
SCL-DISP
RES
3C83
3C81
3S67
3S65
3S68
3S66
+3V3
B26
A25
2_SDA
2_SCL
SDA-SET
SCL-SET
3S58
3S5W
3S6B
3S6C
+3V3
3S1G
3S1H
+3V3-STANDBY
RES
7
8
9S13
9S10
3C84
3C85
3G2W
3G2Y
uP
LEVEL SHIFTED
FOR DEBUG
USE ONLY
RXD-UP
TXD-UP
3F65
3F64
21
7S01
PCA9540B
2 CHAN.
MULTIPLEX.
ERR
24
ERR
34
ERR
23
ERR
42
9S12
9S11
7E10
LAN8710A-EZK
ETH-RXD(0)
ETH-RXD(3)
ETH-RXCLK
ETH-RXD(1)
ETH-RXD(2)
AA1
AA4
AB1
AB2
AA2
2223242520
ETH-TXD(0)
ETH-TXD(3)
ETH-TXCLK
ETH-TXD(1)
ETH-TXD(2)
RXD_0
RXD_1
RXD_2
RXD_3
RXCLK
TXD_0
TXD_1
TXD_2
TXD_3
TXCLK
XIO_D
DQ
A
ETHERNET
DDC_A_SDA
DDC_A_SCL
HDMI_DV
HDMI
CONNECTOR 1
ETHERNET
CONNECTOR
RJ45
Only for sets Brazil RES
SDRAM
7B01
H5PS1G83EFR
EDE1108AGBG
SDRAM
7B02
H5PS1G83EFR
EDE1108AGBG
NAND
FLASH
512MB
SDRAM
7B03
H5PS1G83EFR
EDE1108AGBG
SDRAM
7B00
H5PS1G83EFR
EDE1108AGBG
DDR2-D(0-31)
XIO-D(00-07)
D(24-31)
D(16-23)
D(8-15)
D(0-7)
DDR2-A(0-13)
19
1
18 2
19
1
18 2
19
1
18 2
19
1
18 2
SPI_CLK
SPI_CSB
SPI_SDO
SPI_SDI
P6_5
7F52
M25P05-AVMN6P
FLASH
512K
8
+3V3-STANDBY
VCC
6
PNX-SPI-CLK
AF24
3
PNX-SPI-WPn
AE22
1
PNX-SPI-CSBn
AF23
5
PNX-SPI-SDO
AE23
2
PNX-SPI-SDI
AF25
7F20
NAND04GW3B2DN6F
ERR
13
ERR
18
ERR
14
ERR
64
STANDBY
SW
MAIN
SW
MAIN NVM
SW
EDID
SW
Programmable via USB
SW
RES
RES
RES
B04B
ANALOGUE
EXTERNALS B
EN 70Q551.1L LA 9.
back to
div. table
2010-Oct-01
Block Diagrams
C
2
9-6 Block Diagram I
Page 71
B01A
COMMON INTERFACE
B01D
SD-CARD
B01F
HDMI & CI
B01K
TUNER BRAZIL
B01C
USB HUB
B02B
PNX85500: SDRAM
B01B
FLASH
B02A
PNX85500: NANDFLASH
CONDITIONAL ACCESS
B02C
PNX85500: DIGITAL VIDEO IN
B02E
PNX85500: MIPS
B02G
PNX85500: STANDBY CONTROLLER
B02H
PNX85500: POWER
B01E
PNX85500: CONTROL
B01G
TOSHIBA SUPPLY
B03D
DC / DC
B03E
DC / DC
B09A
(*NON) DVBS CONNECTOR BOARD
B03G
FAN - CONTROL
B03F
TEMPSENSOR + AMBILIGHT
B06A
DISPLAY INTERFACING-VDISP
B02D
PNX85500: AUDIO
B03B
DC / DC
PSU
B03C
DC / DC
B03H
VDISP - SWITCH
B06B
VIDEO OUT - LVDS
B06D
SPI-BUFFER
B05A
DDR
B06C
.
B04D
HDMI
B04E
HEADPHONE
B04A
ANALOGUE EXTERNALS A
B04C
ETHERNET + SERVICE
B03A
AUDI O
B01H
HDMI
B01I
VGA
B01J
TEMP SENSOR + HEADPHONE
+5V
+5V
+5VCA
3F01
+T
B03e
+3V3
+3V3
B03e
B03e
B03e
+3V3-SD
3F40
+T
+3V3
+3V3
+5V-TUN-PIN
+5V-TUN
+5V-TUN
B03e
+5V
+5V
+5V-USB2
3F32
+T
+5V-USB1
3F25
+T
B03e
+3V3
+3V3
B03e
+1V8
+1V8
DDR2-VREF-CTRL2
DDR2-VREF-CTRL3
B03c
+3V3
+3V3
+3V3
+3V3
+5V
+5V
B03e
+3V3
+3V3
B03e
B03e
B01g
B03e
B03b
+3V3
+3V3
B03e
B03b,d,e,g,
B09a
B01e,B02e,
g,h,B03a,b,h,
B04d,e,B09a,
B03h
B02d,B03a
+3V
3
+3V3
B03e
+3V3-STANDBY
+3V3-STANDBY
B03c
+1V1
+1V1
B03b
+3V3-STANDBY
+3V3-STANDBY
B03c
+1V1
+1V1
B03b
+1V2
+1V2
B03d
+1V8
+1V8
B03b
+2V5
+2V5
B03d
+2V5-AUDIO
+2V5-AUDIO
B02d
+2V5-LVDS
+2V5-LVDS
B03d
+3V3
+3V3
B03e
+3V3-STANDBY
+3V3-STANDBY
B03c
+1V2-BRA-VDDC
+1V2-BRA-VDDC
+1V2-BRA-DR1
+1V2-BRA-DR1
+3V3
+3V3
B03e
+3V3-STANDBY
+3V3-STANDBY
B03c
+5V
+5V
B03e
B03d
B03e
9F71
+3V3-BRA
+3V3
+3V3
+1V2-BRA-VDDC
+3V3+3V3
7FA3
IN OUT
COM
+1V2-BRA-DR1
5FA4
5FE7
5FA3
+3V3
+5V+5V
+2V5-LVDS
+2V5
B03e
+2V5-AUDIO
+3V3-ARC
+3V3+3V3
7S08
IN OUT
COM
+2V5-BRA
+3V3-BRA-FLT
+5V+5V
7FE3
IN OUT
COM
5FE9
5FE4
3S20
3S06
+24V-AUDIO-POWER
+24V-AUDIO-POWER
+24V-AUDIO-VDD
3S0Z
3S11
7U03
TPS53126PW
+12V
+1V8
12
14
+1V1
5U01
23
24
+12V
12V/1V1
COVERSION
12V/1V8
COVERSION
5U02
5U00
B03c
+3V3-STANDBY
+3V3-STANDBY
B03c
Dual
Synchronous
Step-Down
Controller
7U04
7U01
7U02-2
7U02-1
1
1M95
11
66
77
88
1M95
+3V3-STANDBY
Optional 1M99 is 12 pin connector
3V3_ST
+12V
1M99
11
66
77
22
33
44
88
55
LAMP-ON
1M99
BACKLIGHT-BOOST
+12VD
BACKLIGHT-PWM_BL-VS
+12V
99
+24V-AUDIO-POWER
10 10
+12V
+12V
+VSND
GND_SND
BACKLIGHT-PWM-ANA-DISP
BL-SPI-CSn
99
10 10
BL-SPI-SDO
11 11
12 12
BL-SPI-CLK
POWER-OK
22
33
44
55
STANDBY
STANDBY
GND1
GND1
GND1
11 11
N.C.
+12V
BL_ON_OFF
DIM
POK
N.C
N.C.
N.C.
+12V
BOOST
GND1
GND1
N.C.
1U40
T 3.0A
MAINS-OK
CUA0
+1V2
+1V8+1V8
+12V
7UA3
B03b
B03e
B03e
+2V5-REF
+12V+12V
B03c
B03b
B03c
B03e
B03c
3U16
3UA0
7UC0
IN OUT
COM
3U15
7UA0
VOLT.
REG.
+5V-TUN
+5V5-TUN+5V5-TUN
7UA6
ENABLE-1V8
+3V3
+12V+12V
+1V1+1V1
+12V+12V
+3V3+3V3
5UD3 5UD2
+5V
+5V5-TUN
5UD0 5UD1
6UD0
7UD0
IN OUT
COM
7UD1
IN OUT
COM
B03e
B02h
+3V3+3V3
V-AMBI
1UM0
T 1.0A
5UM1
B03h
+VDISP-INT+VDISP-INT
1G00
T 3.0A
+VDISP
1G03
T 3.0A
1C86
*1T86
T 2.0A
5G02
+VDISP-INT
+12VD+12VD
+3V3+3V3
7UU2
LCD-PWR-ONn
7UU1
B03c
B03e
+3V3-STANDBY+3V3-STANDBY
B03c
B02b,h,B03d,
B05a
B03e
B06a
+VDISP+VDISP
+3V3+3V3
+3V3
+3V3
DDR2-VREF-DDR
+1V8+1V8
B03b
B02h
B02h
B01f
3B20
VIO
+3V3+3V3
B03e
B03e
5G01
5GA1
VINT
5GA0
NOT FOR 5000 SERIES
B06a
OR
B03d
B02h
B06b
B03e
B03c
B03e
B03c
+3V3-STANDBY+3V3-STANDBY
+5V+5V
+12V+12V
+3V3+3V3
1M20
8
5
1M59
21
TO
IR/LED
PAN EL
1M09
1
2
+24V
B01,a,c,e,k,
B03c,d,B04a,d,
B09a
B02g,h,
B03e
B01k
B01k
B01g
18760_407_100810.eps
100929
B02G
B02G
B06C
B01E
B02G
B02G
B03A
B01,a,b,c,d,e,
g,j,k,
B02a,c,d,e,h,
B03c,f,g,h,
B04a,c,d,e,
B06b,c,d,
B09a
1P03
18
HDMI 2
CONNECTOR
BIN-5V
1P02
18
HDMI 1
CONNECTOR
+5V-EDID
+3V3-STANDBY
+3V3-STANDBY
+3V3
+3V3
+3V3-HDMI
CIN-5V
1P04
18
HDMI 3
CONNECTOR
AIN-5V
5EC0
B03e
B03c
+5V-VGA
+5V-VGA
+5V
+5V
B01I
B03e
DIN-5VDIN-5V
B01h
B03e
B03c
6EC1
+3V3-STANDBY+3V3-STANDBY
+3V3+3V3
+3V3-ET-ANA
+3V3+3V3
B03e
B03e
B03e
+5V+5V
+3V3+3V3
5E08
B03c
B03c
+3V3-STANDBY+3V3-STANDBY
+24V-AUDIO-POWER
+24V-AUDIO-POWER
+AVCC
3D09
DIN-5V
+3V3
+3V3
B03e
1P05
18
HDMI SIDE
CONNECTOR
B04d
+5V-VGA
1E05
9
VGA
CONNECTOR
B04d
EN 71Q551.1L LA 9.
back to
div. table
2010-Oct-01
Block Diagrams
9-7 Supply Lines Overview
Page 72
18770_600_100212.eps
100218
LiteOn 15 LED Common
AL1A AL1A
8204 000 8978
AL 2K10 LiteOn
15 LED Common
2009-12-0462009-10-2852009-10-0742009-08-2732009-07-03
2
BLUE
GREEN
RED
-T
S
GND
Q
HOLD
W
VCC
C
D
VIA
VIA
VIA
VIA
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
OUT
12
11
GSCLK
IREF
MODE
SCLK
SIN
SOUT
XERR
XHALF
XLAT 10
NC
9
8
VCC
0123456
7
BLANK
131415
GND GND_HS
BLUE
GREEN
RED
BLUE
GREEN
RED
2
G
123
1
4567
34
F
A
H
I
B
C
9 1011121314
E
567
91011121314
D
E
F
8
H
I
A
B
C
D
8
G
3456789
2627
17181922021222324
25
1
10111213141516
FH12-25S-0.5SH(55)
1M83
FB12
FB15
RES
3004
10K
FB06
+3V3
10K
3B11
+24V
3B00-2
150R
27
100p
2B04-2
27
2B04-3
36
43
+3V3
100p
LTW-008RGB
65
21
+24V
7000
3B22
10K
FB41
+3V3
2B00
33p
1K5
3B03-1
18
+3V3
18
100p
2B04-1
3B02-2
10K
27
3B39-1
81
10K
3B02-1
18
1%1K5
FB03
2B10
FB13
100p
100n
2B17
41
42
TLC5946RHB
7B26-2
343536
37
38
39
40
2
1
8
3
7B07
M95010-WDW6
6
5
4
7
3B34
Φ
(64K)
1
3
2
100K
RES
45
BC847BW
7B25
3B00-4
150R
1K8
3B18
10K
3B13-3
36
33p
+3V3
27
2B01
3B01-2
100R
2B02
100p
5
21
43
+3V3
+24V
LTW-008RGB
7001
6
+3V3
3B03-4
1K5
45
FB16
FB05
FB07
FB04
3B07-4
10K
45
652143
7003
LTW-008RGB
2B11
100n
100R
3B01-1
18
7B20-2
74LVC2G17
3
25
4
18
3B00-1
150R
7
3B03-2
1K5
2
270R
3B36
3B39-3
36
1K5 1%
27
1%1K5
25
6
+24V
3B39-2
74LVC2G17
7B20-1
1
7B23-1
BC847BS(COL)
2
6
1
LMV331IDCK
1
3
4
52
7B30
270R
3B35
68R
3B37
7B23-2
BC847BS(COL)
5
3
4
36
3B00-3
150R
100p
2B04-4
45
+3V3
45
+3V3
FB08
3B13-4
10K
3
+3V3
FB31
LTW-008RGB
7002
65214
FB35
15
1223
27
222532
192021
678
9
101114
26
3
121328
29
4
5
161718
7B26-1
TLC5946RHB
31
30
33
24
FB11
214
3
FB10
LTW-008RGB
7004
65
1K5
3B03-3
36
27
FB01
45
10K
3B07-2
3B30-4
220R
+24V
2B03
100n
2B09
10n
3B31
2K0
10n
2B08
+3V3
5
4
74LVC1G32GW
7B06
1
2
3
FB40
18
100n
2B20
3B07-1
10K
FB20
3B21
FB30
18
150R
220R
3B30-1
+3V3
36
10K
3B07-3
FB32
+3V3
5
214
3
+3V3
7005
LTW-008RGB
6
TEMP-SENSOR
BLANK
PROG
SPI-CS
PWM-CLOCK
SPI-DATA-RETURN
SPI-DATA-IN
SPI-CLOCK
LATCH
PWM-CLOCK
BLANK
SPI-DATA-IN-BUF
PWM-R1
PWM-G1
PWM-R1
PWM-G3
PWM-R3
PWM-R2
PWM-B2
PWM-G2
DATA-SWITCH
TEMP-SENSOR
PWM-G4
PWM-R4
PWM-B4
PWM-R5
PWM-G5
PWM-B5
SPI-CLOCK-BUF
SPI-DATA-IN-BUF
SPI-DATA-RETURN
SPI-CS
DATA-SWITCH
LATCH
SPI-DATA-IN
SPI-DATA-OUT
PWM-CLOCK-BUF
SPI-CLOCK-BUF
PROG
SPI-CLOCK-BUF
PWM-CLOCK-BUF
SPI-CLOCK
PWM-G1
PWM-B1
PWM-B1
PWM-B3
2B00 E8
2B01 F8
2B02 E9
2B03 I14
2B04-1 B7
2B04-2 B6
2B04-3 B8
1M83 C1
3B00-4 B6
3B01-1 E7
3B13-4 I3
3B18 A8
3B21 B7
3B22 B8
3B00-3 B6
7B23-1 F4
7B23-2 G4
7B25 H3
7B26-1 A8
7B26-2 C9
3B01-2 D7
3B02-1 E3
3B13-3 H3
3B30-1 D9
3B30-4 E9
2B04-4 B7
2B08 E12
2B09 E12
2B11 A9
2B17 D8
2B20 D4
3004 E12
3B00-1 A6
3B00-2 B6
7002 G8
FB16 C1
FB20 B7
FB30 G3
FB31 H3
FB32 I3
FB35 A8
FB40 D12
7003 G10
7004 G11
7B30 D13
FB01 A1
3B02-2 E5
3B03-1 H14
3B03-2 H14
3B03-4 H14
3B07-1 F3
3B07-2 G3
3B07-3 H3
3B07-4 G3
3B11 E12
FB06 B2
FB07 B1
FB08 B1
FB10 B2
FB11 B1
FB12 B2
FB13 C1
7B20-1 D8
7B20-2 E8
FB15 C1
3B31 B10
3B34 D13
3B35 G14
2B10 F9
3B37 G14
3B39-1 E13
3B39-2 D12
3B39-3 D13
7000 G5
7001 G7
3B36 G14
FB41 E13
FB03 B1
FB04 B1
FB05 B1
3B03-3 H14
7005 G13
7B06 D3
7B07 D4
B007
B001 B002
EN 72Q551.1L LA 10.
back to
div. table
2010-Oct-01
Circuit Diagrams and PWB Layouts
LiteOn LED Common
10. Circuit Diagrams and PWB Layouts
10-1 AL1 820400089786 AmbiLight Common
Page 73
18770_601_100212.eps
100212
LiteOn 15 LED Common 2
AL1B AL1B
2009-12-0462009-10-2852009-10-0742009-08-2732009-07-03
2
8204 000 8978
AL 2K10 LiteOn
15 LED Common
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
3B55-2 B3
3B55-3 A3
3B55-4 A3
7C20-2 F3
8
123
3B57-2 D3
3B57-3 C3
FC03 H3
9101112
A
B
C
7104 B6
7105 B5
F
G
3B50 B7
D
E
7200 F8
3B53-4 C7
3B55-1 C3
11 12
FC02 G3
3C12 F4
C
4
3C15-1 G4
3C15-2 G4
3C15-3 G4
3C15-4 G4
7100 B11
7101 B10
7102 B9
7103 B7
3C10 F4
7C20-1 E3
910
7201 F9
7202 F10
3C00-2 F3
3C00-3 F3
7B51 C3
FB71 C3
FB72 D3
FC01 F3
3C11 F4
D
E
3B53-2 C7
3B53-3 C7
H
2B50 C11
G
H
3C00-4 E3
7C22 G3
FB70 B3
34
3B51 B7
7
3B52 B7
3B53-1 B7
5
3C00-1 G3
78
7B50-1 A3
7B50-2 B3
A
B
21
F
3C06-1 G3
3C06-2 H3
56
6521
43
6
LTW-008RGB
7201
10K
3B55-3
36
100n
2B50
5
3
4
FC01
12
7C20-2
BC847BS(COL)
12
270R
3C10
8
3C11
270R
10K
3B55-1
1
68R
3B52
652143
7104
LTW-008RGB
36
45
3C15-3
1K5
3C15-4
1K5
3C12
68R
BC847BW
7C22
1
3
2
36
+24V
+24V
3B57-3
10K
4
+24V
FB70
BC847BS(COL)
7B50-2
5
3
10K
3B55-4
4527
3
3B57-2
10K
LTW-008RGB
7105
65214
FB71
652143
3
LTW-008RGB
7100
65214
1
43
7101
LTW-008RGB
7200
LTW-008RGB
65
2
10K
3C06-1
18
+24V
27
FC03
1
43
10K
3B55-2
652
65
2143
7103
LTW-008RGB
8
LTW-008RGB
7202
3C15-1
1K5
1
3C15-2
1K5
27
FB72
6
1
+24V
+24V
BC847BS(COL)
7C20-1
2
5
21
43
LTW-008RGB
7102
6
7B50-1
BC847BS(COL)
2
6
1
1
3
2
7B51
BC847BW
3B51
270R
45
270R
3B50
36
1K5
3B53-4
7
1K5
3B53-3
1K5
3B53-2
2
1K5
3B53-1
18
27
FC02
10K
3C06-2 3C00-3
10K
36
3C00-2
10K
27
10K
18 45
3C00-1
+24V
3C00-4
10K
Green
Red
PWM-R2
PWM-G2
PWM-B2
PWM-R3
PWM-G3
PWM-B3
Blue
EN 73Q551.1L LA 10.
back to
div. table
2010-Oct-01
Circuit Diagrams and PWB Layouts
LiteOn LED Common 2
Page 74
18770_620_100212.eps
100218
15 LED LiteOn
AL2A AL2A
8204 000 8970
3104 313 63823
15 LED LiteOn
AL 2K10
2009-12-0732009-10-0722009-07-02
1
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
4567
D
A
56789
B
C
D
1M84 A10
2D01 B6
7203 A3
7204 A4
123
7205 A5
910
A
B
C
8
34 10
FD18 C7
12
100n
2D01
+3V3
+3V3
+24V
3
456
789
26
27
161718
19
2
202122
232425
1
10
111213
14
15
FH12-25S-0.5SH(55)
1M84
FD18
1
4
3
+24V
LTW-008RGB
7205
65
2
5
21
43
7204
LTW-008RGB
665
21
43
7203
LTW-008RGB
B004 B005B003
TEMP-SENSOR
BLANK
PROG
LATCH
SPI-CS
PWM-CLOCK-BUF
SPI-DATA-RETURN
SPI-DATA-OUT
S
PI-CLOCK-BUF
Blue
Green
Red
EN 74Q551.1L LA 10.
back to
div. table
2010-Oct-01
Circuit Diagrams and PWB Layouts
15 LED LiteOn
10-2 AL2 820400089703 15 LED LiteOn
Page 75
18770_621_100212.eps
100219
15 LED LiteOn
AL2B AL2B
2009-12-0732009-10-0722009-07-02
1
8204 000 8970
3104 313 63823
15 LED LiteOn
AL 2K10
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
D
E
3D13-2 C12
F
G
13
9101112
3D02-1 A1
910
7305 B11
7400 F5
7401 F6
12 13
A
B
C
3D10 B12
3D11 B12
3D12 B12
3D13-1 B12
7D01-2 B2
7D02 C2
12
H
3D18-4 G12
7300 B5
7301 B6
678
2D10 C13
2D11 H13
3D02-2 A1
3D02-3 B1
11
7402 F7
7403 F8
7404 F10
7405 F11
7D01-1 A2
FD04 F1
FD05 G1
FD06 H1
3D04-4 F2
3D05-3 C1
3D05-4 D1
E
7D03-1 E2
7D03-2 F2
7D04 G2
FD01 A1
FD02 C1
FD03 D1
453
3D16 F12
3D17 F12
3D18-1 G12
3D18-2 G12
3D18-3 G12
3D02-4 B1
3D03-3 H2
3D03-4 G2
A
B
C
D
7302 B7
12
783456
3D13-3 C12
3D13-4 C12
3D15 F12
3D04-1 F2
3D04-2 G2
3D04-3 E2
7303 B8
7304 B10
F
G
H
65214
3
LTW-008RGB
7300
+24V
270R
3D16
270R
3D15
3D10
270R
52143
7304
LTW-008RGB
6
36
+24V
3D03-3
10K
+24V
FD06
36
FD04
FD02
3D05-3
10K
5
FD01
3D04-4
10K
4
65
21
43
5
3
4
7403
LTW-008RGB
27
BC847BS(COL)
7D01-2
1K5
3D13-2
36
100n
2D10
45
3D13-3
1K5
5
1K5
3D13-4
3D02-4
10K
4
65
214
3
+24V
7400
LTW-008RGB LTW-008RGB
7404
65
214
3
+24V
36
1K5
3D18-3
1K5
3D18-1
18
FD05
FD03
27
10K
3D04-3
36
3D04-2
10K
5
21
43
LTW-008RGB
7402
6
3D12
68R
68R
3D17
27
+24V
+24V
+24V
3
4
3D02-2
10K
7D03-2
BC847BS(COL)
5
3D11
270R
3D18-2
1K5
27
7305
65
2
1
43
18
LTW-008RGB
1
43
10K
3D04-1
LTW-008RGB
65
2
7D02
BC847BW
1
3
2
7301
10K
3D02-1
18
10K
3D03-4
45
65
21
43
LTW-008RGB
7401
10K
3D05-4
45
18
5
3D13-1
1K5
3D18-4
1K5
4
7D04
1
3
2
2
6
1
BC847BW
652143
BC847BS(COL)
7D01-1
LTW-008RGB
7303
65
21
43
7D03-1
BC847BS(COL)
2
6
1
7302
LTW-008RGB
36
10K
3D02-3
4
3
2D11
100n
7405
LTW-008RGB
65
2
1
PWM-R4
PWM-G4
PWM-B5
PWM-B4
PWM-G5
PWM-R5
EN 75Q551.1L LA 10.
back to
div. table
2010-Oct-01
Circuit Diagrams and PWB Layouts
15 LED LiteOn
Page 76
19030_602_100809.eps
100809
AmbiLight LiteOn
3104 313 6383.2
36 LED
1M83 1M84
2B00
2B01
2B02
2B03
2B04
2B08
2B09
2B10
2B11
2B17
2B20
2B50
2C01
2D04
2D10
2D11
2E10
2F10
3004
3B00
3B01
3B02
3B03
3B07
3B11
3B13
3B18
3B21
3B22
3B30
3B31
3B34
3B35
3B36
3B37
3B39
3B50
3B51
3B52
3B53
3B55
3B57
3C00
3C06
3C10
3C11
3C12
3C15
3D00
3D02
3D05
3D10
3D11
3D12
3D13
3D18
3D21
3D22
3E02
3E05
3E10
3E11
3E12
3E13
3F02
3F05
3F10
3F11
3F12
3F13
7000 7001 7002 7003 7004 7005 7100 7101 7102 7103 7104 7105 7200 7201 7202 7203 7204 7205 7300 7301 7302 7303 7304 7305 7400 7401 7402 7403 7404 7405 7500 7501 7502 7503 7504 7505
7B06
7B07
7B20
7B23
7B25
7B26
7B30
7B50
7B51
7C20
7C22
7D01
7D02
7D26
7E01
7E02
7F01
7F02
B001
B002
B003
B004
B005
B006
B007
FB01
FB03
FB04
FB05 FB06
FB07
FB08
FB10
FB11
FB12
FB13
FB15FB16
FB20
FB30
FB31
FB32
FB35
FB40
FB41
FB70
FB71
FB72
FC01
FC02
FC03
FD01 FD02
FD03
FD04
FD05
FD06
FD18
FD19
FF01FF02
FF03
back to
div. table
EN 76Q551.1L LA 10.
2010-Oct-01
Circuit Diagrams and PWB Layouts
Layout AmbiLight LiteOn
10-3 AL1 Layout AmbiLight LiteOn
Page 77
18770_670_100212.eps
100219
Everlight 15 LED Common
AL1A AL1A
8204 000 9059
AL 2K10 Everlight
15 LED Common
2009-11-2722009-11-03
1
BLUE
GREEN
RED
BLUE
GREEN
RED
OUT
12
11
GSCLK
IREF
MODE
SCLK
SIN
SOUT
XERR
XHALF
XLAT 10
NC
9
8
VCC
0123456
7
BLANK
131415
GND GND_HS
BLUE
GREEN
RED
BLUE
GREEN
RED
S
GND
Q
HOLD
W
VCC
C
D
VIA
VIA
VIA
VIA
BLUE
GREEN
RED
BLUE
GREEN
RED
-T
FB07 B1
FB08 B1
FB15 C1
3B37 G14
3B39-1 E13
3B34 D13
3B36 G14
7003 G10
7004 G11
7B30 D13
FB01 A1
3B02-2 E5
3B03-1 H14
3B03-4 H14
3B07-1 F3
FB41 E13
FB03 B1
FB04 B1
FB05 B1
3B03-3 H14
7005 G13
7B06 D3
FB12 B2
FB13 C1
7B20-1 D8
7B20-2 E8
7B07 D4
3B30-1 D9
3B30-4 E9
2B04-4 B7
2B08 E12
3B35 G14
2B10 F9
2B11 A9
2B17 D8
3B39-2 D12
3B39-3 D1
3
7000 G5
7001 G7
FB20 B7
FB30 G3
3B31 B10
FB35 A8
FB40 D12
7B23-1 F4
7B25 H3
7B26-1 A8
7B26-2 C9
3B01-2 D7
3B02-1 E3
D
E
3B03-2 H14
G
H
I
3B07-2 G3
3B07-3 H3
3B07-4 G3
3B11 E12
FB06 B2
FB10 B2
FB11 B1
3B18 A8
3B21 B7
3B22 B8
56
2B09 E12
8910
2B20 D4
3004 E12
3B00-1 A6
3B00-2 B6
7002 G8
FB16 C1
FB31 H3
FB32 I3
7B23-2 G4
3B00-4 B6
3B01-1 E7
B
C
F
8910
A
B
C
D
3B13-3 H3
3B13-4 I3
34
711121314
3B00-3 B6
H
I
1M83 C1
2B02 E9
2B00 E8
11 12 13 14
E
4567
3
1
12
F
A
2
G
2B01 F8
2B03 I14
2B04-1 B7
2B04-2 B6
2B04-3 B8
FB32
65
214
3
+3V3
99-235/RSBB7C-A24/2D
7005
+3V3
10n
2B09
2K0
3B31
4
+3V3
1
2
35
7B06
74LVC1G32GW
FB40
18
2B20
100n
10K
3B07-1
FB20
FB30
8
3B21
150R
3B30-1
220R
1
B002
+3V3
FB08
3B07-3
10K
3645
+3V3
FB31
10K
3B13-4
1
43
+3V3
7002
99-235/RSBB7C-A24/2D
65
2
25
32
FB35
9
101114
15
1223
27
22
5
1617181920
21
678
31
30
33
24263
121328
29
4
TLC5946RHB
7B26-1
FB10
FB11
65214
3
6
7004
99-235/RSBB7C-A24/2D
3B03-3
1K5
3
FB01
27
45
3B07-2
10K
+24V
220R
3B30-4
100n
2B03
100n
2B11
3B01-1
100R
18
2B08
10n
27
1K5
3B03-2
3B36
270R
1K5 1%
36
3B39-2
27
3B39-3
5
6
+24V
1%1K5
7B20-1
74LVC2G17
1
2
2
6
1
1
3
4
52
BC847BS(COL)
7B23-1
LMV331IDCK
7B30
3B35
270R
3B37
68R
5
3
4
B001
36
BC847BS(COL)
7B23-2
150R
3B00-3
2B17
100n
2B04-4
100p
45
36
37
38
39
40
41
42
7B26-2
TLC5946RHB
34
35
4
7
2
1
8
3
+3V3
M95010-WDW6
7B07
(64K)
Φ
6
5
7B25
BC847BW
1
3
2
36
3B18
1K8
+3V3
3B13-3
10K
33p
2B01
100R
3B01-2
27
+24V
100p
2B02
652143
+3V3
+3V3
7001
99-235/RSBB7C-A24/2D
45
FB16
1K5
3B03-4
FB05
FB07
FB04
45
10K
3B07-4
7003
6521
43
99-235/RSBB7C-A24/2D
3
25
4
+3V3
18
74LVC2G17
7B20-2
150R
3B00-1
33p
2B00
18
+3V3
18
3B03-1
1K5
2B04-1
100p
10K
3B02-2
27
1K5 1%
81
18
3B39-1
FB03
3B02-1
10K
FB13
2B10
100p
3B34
RES
100K
150R
3B00-4
45
56789
2627
18
1922021222324
25
3
4
1M83
FH12-25S-0.5SH(55)
1
10111213141516
17
FB12
B007
FB15
10K
3004
RES
FB06
+3V3
3B11
10K
150R
3B00-2
27
+24V
2B04-2
100p
27
36
43
+3V3
2B04-3
100p
99-235/RSBB7C-A24/2D
7000
65
21
+24V
10K
3B22
FB41
TEMP-SENSOR
BLANK
PROG
SPI-CS
PWM-CLOCK
SPI-DATA-RETURN
SPI-DATA-IN
SPI-CLOCK
LATCH
PWM-CLOCK
BLANK
SPI-DATA-IN-BUF
PWM-R1
PWM-G1
PWM-R1
PWM-G3
PWM-R3
PWM-R2
PWM-B2
PWM-G2
DATA-SWITCH
TEMP-SENSOR
PWM-G4
PWM-R4
PWM-B4
PWM-R5
PWM-G5
PWM-B5
SPI-CLOCK-BUF
SPI-DATA-IN-BUF
SPI-DATA-RETURN
SPI-CS
DATA-SWITCH
LATCH
SPI-DATA-IN
SPI-DATA-OUT
PWM-CLOCK-BUF
SPI-CLOCK-BUF
PROG
SPI-CLOCK-BUF
PWM-CLOCK-BUF
SPI-CLOCK
PWM-G1
PWM-B1
PWM-B1
PWM-B3
EN 77Q551.1L LA 10.
back to
div. table
2010-Oct-01
Circuit Diagrams and PWB Layouts
Everlight LED Common
10-4 AL1 820400090592 AmbiLight Common
Page 78
18770_671_100212.eps
100212
Everlight 15 LED Common 2
AL1B AL1B
2009-11-2722009-11-03
1
8204 000 9059
AL 2K10 Everlight
15 LED Common
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
3B57-3 C3
FC03 H3
11 12
A
B
C
7104 B6
7105 B5
F
G
3B55-2 B3
3B55-3 A3
E
7200 F8
3B55-4 A3
7C20-2 F3
8
12
3B53-4 C7
3B55-1 C3
11 12
FC02 G3
3
3B57-2 D3
4
3C15-3 G4
3C15-4 G4
910
7102 B9
7103 B7
3C10 F4
7C20-1 E3
3B50 B7
D
910
7201 F9
7202 F10
7B51 C3
FB71 C3
FB72 D3
FC01 F3
3C11 F4
3C12 F4
C
D
E
H
2B50 C11
3C15-1 G4
3C15-2 G4
7100 B11
7101 B10
3C00-4 E3
7C22 G3
FB70 B3
34
3B51 B7
7
3B52 B7
3B53-1 B7
5
3C00-1 G3
3C00-2 F3
3C00-3 F3
7B50-1 A3
7B50-2 B3
A
B
3B53-2 C7
3B53-3 C7
1
F
G
H
3C06-1 G3
3C06-2 H3
56
678
5
3
4
+24V
2
45
BC847BS(COL)
7B50-2
7
10K
3B55-4
3B57-2
10K
2
21
43
99-235/RSBB7C-A24/2D
7105
65
BC847BS(COL)
2
6
1
65
21
43
7B50-1
99-235/RSBB7C-A24/2D
7100
65214
3
1
43
7101
99-235/RSBB7C-A24/2D
99-235/RSBB7C-A24/2D
65
2
10K
3C06-1
18
7200
1
43
+24V
99-235/RSBB7C-A24/2D
7201
6
5
2
10K
3B55-3
36
100n
2B50
4
FC01
7C20-2
BC847BS(COL)
5
3
270R
3C10
12
270R
12
10K
3B55-1
18
3C11
3B52
68R
21
43
7104
99-235/RSBB7C-A24/2D
65
3
2
FB71
7B51
BC847BW
1
3B51
270R
270R
3B50
1K5
3B53-4
45
1K5
3B53-3
36
3B53-2
27
18
1K5
1K5
3B53-1
27
FC02
36
10K
3C06-2
27
3C00-3
10K
8
3C00-2
10K
5
3C00-1
10K
1
3C00-4
10K
4
+24V
36
45
3C15-3
1K5
3C15-4
1K5
2
3C12
68R
BC847BW
7C22
1
3
36
+24V
+24V
3B57-3
10K
FB72
FB70
FC03
10K
3B55-2
27
65214
3
3
7103
99-235/RSBB7C-A24/2D
99-235/RSBB7C-A24/2D
7202
6
5
214
18
27
3C15-1
1K5
3C15-2
1K5
2
6
1
+24V
+24V
BC847BS(COL)
7C20-1
652143
PWM-R2
PWM-G2
99-235/RSBB7C-A24/2D
7102
PWM-B2
PWM-R3
PWM-G3
PWM-B3
Blue
Green
Red
EN 78Q551.1L LA 10.
back to
div. table
2010-Oct-01
Circuit Diagrams and PWB Layouts
Everlight LED Common 2
Page 79
18770_660_100212.eps
100526
15 LED Everlight
AL2A AL2A
8204 000 9062
3104 313 64211
15 LED Everlight
AL 2K10
2009-11-27
1
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
A
B
C
D
A
B
C
7
6
5421
7205 A5
9108
9
8
7
643 10
3
1M84 A10
2D01 B6
7203 A3
7204 A4
FD18 C7
12
5
D
FD18
43
+24V
99-235/RSBB7C-A24/2D
7205
6
5
21
214
3
7204
99-235/RSBB7C-A24/2D
6
5
65214
3
7203
99-235/RSBB7C-A24/2D
B004 B005B003
100n
2D01
+3V3
+3V3
5
6
789
26
27
+24V
18
19
2
20
212223
24
25
3
4
1
10111213141516
17
1M84
TEMP-SENSOR
BLANK
PROG
LATCH
SPI-CS
PWM-CLOCK-BUF
SPI-DATA-RETURN
SPI-DATA-OUT
SPI-CLOCK-BUF
Blue
Green
Red
back to
div. table
EN 79Q551.1L LA 10.
Circuit Diagrams and PWB Layouts
2010-Oct-01
15 LED Everlight
10-5 AL2 820400090621 15 LED Everlight
Page 80
18770_661_100212.eps
100212
15 LED Everlight
AL2B AL2B
2009-11-27
1
8204 000 9062
3104 313 64211
15 LED Everlight
AL 2K10
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
7305 B11
7400 F5
7403 F8
7404 F10
7405 F11
7D01-1 A2
F
G
H
FD06 H1
7301 B6
3D18-4 G12
7300 B5
7401 F6
7402 F7
91011
3D03-4 G2
3D04-1 F2
3D04-2 G2
3D04-3 E2
12
FD04 F1
FD05 G1
B
C
D
E
123 67
10 11 12 13
3D02-2 A1
3D02-3 B1
3D02-4 B1
3D03-3 H2
3D15 F12
3D04-4 F2
3D05-3 C1
13
A
3D11 B12
3D12 B12
3D13-1 B12
3D13-2 C12
7D01-2 B2
7D02 C2
7D03-1 E2
7D03-2 F2
FD02 C1
FD03 D1
45
12
89
2D10 C13
2D11 H13
3D02-1 A1
3D16 F12
3D18-2 G12
3D18-3 G12
3D13-3 C12
3D13-4 C12
F
G
7302 B7
7303 B8
7304 B10
3D05-4 D1
3D10 B12
H
A
B
C
3456
7D04 G2
FD01 A1
D
E
FD02
78
3D17 F12
3D18-1 G12
45
FD01
3
3D04-4
10K
99-235/RSBB7C-A24/2D
65214
5
3
4
7403
3D13-2
27
BC847BS(COL)
7D01-2
1K5
36
100n
2D10
45
3D13-3
1K5
45
1K5
3D13-4
43
3D02-4
10K
7400
99-235/RSBB7C-A24/2D
65
21
3
4
+24V
+24V
7D03-2
BC847BS(COL)
5
3D11
68R
3D18-2
1K5
27
RES
652
1
43
18
99-235/RSBB7C-A24/2D
7305
1
43
10K
3D04-1
7301
99-235/RSBB7C-A24/2D
65
2
7D02
BC847BW
1
3
2
10K
3D02-1
18
10K
3D03-4
45
65
21
43
45
99-235/RSBB7C-A24/2D
7401
10K
3D05-4
652143
99-235/RSBB7C-A24/2D
7300
+24V
RES
68R
3D16
68R
3D15
3D10
68R
521
43
7304
99-235/RSBB7C-A24/2D
6
36
+24V
3D03-3
10K
FD04
+24V
FD06
10K
36
18
3D05-3
3D13-1
1K5
3D18-4
1K5
45
7D04
1
3
2
2
6
1
BC847BW
7303
65214
3
BC847BS(COL)
7D01-1
1
43
99-235/RSBB7C-A24/2D
7302
99-235/RSBB7C-A24/2D
65
2
7D03-1
BC847BS(COL)
2
6
1
10K
3D02-3
36
2D11
100n
65
214
3
1
43
7405
99-235/RSBB7C-A24/2D
99-235/RSBB7C-A24/2D
7404
6
5
2
1K5
3D18-3
36
FD05
1K5
3D18-1
18
27
FD03
6
3D04-2
10K 10K
3D04-3
3
99-235/RSBB7C-A24/2D
7402
652143
3D12
68R
68R
3D17
+24V
+24V
+24V
27
PWM-R4
PWM-G4
PWM-B5
3D02-2
10K
PWM-B4
PWM-G5
PWM-R5
EN 80Q551.1L LA 10.
back to
div. table
2010-Oct-01
Circuit Diagrams and PWB Layouts
15 LED Everlight
Page 81
18940_672_100809.eps
100809
AmbiLight Everlight
1M83 1M84
2B00
2B01
2B02
2B03
2B04
2B08
2B09
2B10
2B11
2B17
2B20
2B50
2D01
2D10
2D11
3004
3B00
3B01
3B02
3B03
3B07
3B11
3B13
3B18
3B21
3B22
3B30
3B31
3B34
3B35
3B36
3B37
3B39
3B50
3B51
3B52
3B53
3B55
3B57
3C00
3C06
3C10
3C11
3C12
3C15
3D02
3D03
3D04
3D05
3D10
3D11
3D12
3D13
3D15
3D16
3D17
3D18
7000 7001 7002 7003 7004 7005 7100 7101 7102 7103 7104 7105 7200 7201 7202
7203 7204 7205 7300 7301 7302 7303 7304 7305 7400 7401 7402 7403 7404 7405
7B06
7B07
7B207B23
7B25
7B26
7B30
7B50
7B51
7C20
7C22
7D01
7D02
7D03
7D04
B001
B002
B003
B004
B005
B007
FB01
FB03
FB04
FB05 FB06
FB07
FB08
FB10
FB11
FB12
FB13
FB15FB16
FB20
FB30
FB31
FB32
FB35
FB40
FB41
FB70
FB71
FB72
FC01
FC02
FC03
FD01 FD02
FD03
FD04
FD05
FD06
FD18
3104 313 6421.1
30 LED
EN 81Q551.1L LA 10.
back to
div. table
2010-Oct-01
Circuit Diagrams and PWB Layouts
Layout AmbiLight Everlight
10-6 Layout AmbiLight Everlight
Page 82
18770_900_100406.eps
100406
Common Interface
B01A B01A
2010-02-01
2
8204 000 9081
TUNER, HDMI & CI
G3
1
2
3EN2
3EN1
G3
1
2
3EN2
3EN1
G3
1
2
3EN2
3EN1
G3
1
2
3EN2
3EN1
G3
1
2
3EN2
3EN1
+T
G3
1
2
3EN2
3EN1
3F04-3 C4
3F03-1 A4
3F03-2 A4
G
IF06 C5
B
2F00 A6
3F07-4 A9
E
3F08-1 A9
3F08-2 A9
IF03 A4
IF04 B9
3F09-1 B9
3F08-4 B9
7F02 D5
F
1P00-B G10
4
11
3F04-4 C4
3F09-3 B9
IF02 A5
3F05-1 C4
3F04-2 C4
3F05-4 C4
3F11-4 D9
3F02 A4
2F05 G6
7F01 B5
CONTROL
3F09-4 B9
3F11-1 D9
7F03 E5
51
3F12 C9
2F02 B6
3F07-2 A9
7F05 I5
3F07-1 A9
8
D
3F10-1 C9
TRANSPORT STREAM FROM CAM
8-BIT DATA
I
3F09-2 B9
23
2F04 E6
D
3F04-1 C4
11
3F07-3 A9
2F06 H6
IF01 A4
10
2F01 A2
C
10
IF08 D9
2
3F11-3 D9
IF07 C5
3F06 A9
IF05 C4
3F10-2 C9
9
A
8
F
3F11-2 C9
3F01 A2
3F05-3 C4
6
3F05-2 C4
I
H
3F08-3 B9
B
7F04 G5
9
3F10-3 C9
3F10-4 C9
C
A
E
4
615
2F03 D6
3
H
1P00-A D10
7F00 A5
G
7
15-BIT ADDRESS
7
3F11-4
10K
45
7
3F08-2
10K
2
3F05-1 100R
18
3F04-3 100R36
45
3F10-4
10K
45
36
3F08-4
10K
18
3F09-3
10K
3F04-1 100R
+3V3
RES
100n
2F06
36
+3V3
10K
3F08-3
18
3F11-1
10K
100R3F04-4 4 5
19
20
18
17
161514
131211
1
10
74LVC245A
7F03
2345678
9
18
3F03-1
100R
IF02
15
14
13
12
11
1
10
19
20
234
5
6
789
181716
74LVC245A
7F01
3F09-4
45
18
10K
IF03
10K
3F10-1
100R
3F03-2
27
100R3F05-3 3 6
3F12
10K
+3V3
+5VCA
3F02
100R
131211
1
10
19
20
45678
9
18
171615
14
74LVC245A
2
3
IF07
7F04
20
17
1615141312
11
1
10
1923
45678
9
18
7F00
74LVC245A
REF EMC HOLE
1X01
100n
2F04
RES
REF EMC HOLE
1X04
100n
2F02
RES
3F05-4 4 5
+3V3
100R
6
10K
3F11-3
3
IF06
IF01
OE
9
RDY|BSY
16
VCC1
17
VPP1
18
WE|P
15
33
WP|IOIS16
2D43
4
D5
D6
5D76
GND1
1
34
GND2
69
70
23A722
12
A8
A9
11
CE1
7
D030D131D2
32
D3
A1414A1520A16
19
A2
27A326A425A524
A6
A029A1
28
A108A11
10
A12
21
A13
13
10074595-050MLF
ROW_A
1P00-A
3F06
100K
10K
3F10-3
36
100R
3F04-2 2 7
3F07-4
10K
45
+5V
+5VCA
8
10K
3F08-1
1
IF05
2F03
100n
RES
IF04
8
3F09-1
10K
1
16V22u
2F01
RES
51
VCC2
52
VPP2
43
VS1
57
VS2
59
WAIT
68
GND4
60
INPACK
44
IORD
45
IOWR
71
72
61
REG
58
RESET
37
D1138D12
39
D1340D1441D15
64D865
D9
35
GND3
A2456A25
63
BVD1|STSCHG
62
BVD2|SPKR
36
CD1
67
CD2
42
CE2
66
D10
46
A1747A18
48
A1949A20
50
A21
53
A2254A23
55
20
1P00-B
ROW_B
10074595-050MLF
161514
13
12
11
1
10
19
23456
789
18
17
74LVC245A
7F05
7
3F10-2
10K
2
+3V3
3F05-2 100R27
+3V3
+5VCA
27
+3V3
3F11-2
10K
+3V3
10K
3F07-1
18
RES
2F05
100n
10K
3F07-2
27
0R4
3F01
131211
1
10
19
20
456
789
1817161514
7F02
74LVC245A
2
3
+5VCA
IF08
36
27
3F07-3
10K
10K
3F09-2
RES
2F00
100n
CA-DATAENn
+3V3
MDO2
MDO3
MDO4
MDO5
MDO6
MDO7
CA-WAITn
CA-INPACKn
CA-WP
CA-VS1n
CA-RDY
CA-D00
CA-D01
CA-D02
CA-D03
CA-D04
CA-D05
CA-D06
CA-D07
CA-DATADIR
CA-CE2n
CA-CE1n
CA-REGn
CA-MOCLK
CA-MOVAL
CA-MOSTRT
CA-MDO0
CA-MDO1
CA-MDO2
CA-MDO3
CA-MDO4
CA-MDO6
CA-MDO5
CA-MDO7
CA-RST
CA-CD1n
CA-CD2n
CA-DATAENn
CA-DATADIR
CA-ADDENn
MOCLK
MOVAL
MOSTRT
MDO0
MDO1
XIO-D06
XIO-D05
XIO-D04
XIO-D03
XIO-D02
XIO-D01
XIO-D00
CA-ADDENn
CA-WAITn
XIO-D15
XIO-D14
XIO-WEn
XIO-OEn
XIO-D08
XIO-D09
XIO-D11
XIO-D10
CA-IOWRn
CA-IORDn
CA-WEn
CA-OEn
CA-A05
CA-A06
CA-A07
XIO-A00
XIO-A01
XIO-A02
XIO-A03
XIO-A04
XIO-A05
XIO-A06
XIO-A07
CA-ADDENn
CA-A08
CA-A09
CA-A10
CA-A11
CA-A12
CA-A13
CA-A14
XIO-A08
XIO-A09
XIO-A10
XIO-A11
XIO-A12
XIO-A13
XIO-A14
CA-ADDENn
XIO-D07
CA-D07
CA-D06
CA-D05
CA-D04
MOCLK
MOVAL
MOSTRT
CA-D03
MDO0
MDO1
MDO2
MDO3
MDO4
MDO5
MDO6
MDO7
CA-A00
CA-A01
CA-A02
CA-A03
CA-A04
CA-CE2n
MDO7
MDO6
MDO5
MDO4
MDO3
CA-CD1n
CA-WP
CA-D02
CA-D01
CA-D00
CA-A00
CA-A01
CA-A02
CA-A03
CA-A04
CA-A05
CA-A06
CA-A07
CA-A12
CA-MICLK
CA-MIVAL
CA-RDY
CA-WEn
CA-A14
CA-A13
CA-A08
CA-A09
CA-A11
CA-OEn
CA-A10
CA-CE1n
CA-CD2n
MDO2
MDO1
MDO0
MOSTRT
MOVAL
CA-REGn
CA-INPACKn
CA-WAITn
CA-RST
MOCLK
CA-MDI7
CA-MDI6
CA-MDI5
CA-MDI4
CA-MDI3
CA-MDI2
CA-MDI1
CA-MDI0
CA-MISTRT
CA-IOWRn
CA-IORDn
CA-VS1n
EN 82Q551.1L LA 10.
back to
div. table
2010-Oct-01
Circuit Diagrams and PWB Layouts
Common Interface
10-7 B01 820400090812 Tuner, HDMI & CI
Page 83
18770_901_100406.eps
100406
Flash
B01B B01B
2010-02-01
2
8204 000 9081
TUNER, HDMI & CI
WEBR
WP
VCC
VSS
IO
NC
0123456
7
CLE
ALECERE
3F19 D2
3F20-2 B2
3F22-2 C1
42
IF22 D3
3F21-2 C2
3F21-4 C2
A
7F20 B3
1
3F22-3 C2
D
B
423
2F20 A3
3
2C 4-22F31B 3-02F3
3F24 D2
3F21-3 C13F20-1 B1
C
IF21 C3
3F21-1 C12F21 A3
1
+3V3
D
IF23 D3
3F20-4 C2
A
3F22-1 C2
C
B
3F23 C2
273F20-2 100R
3F22-2 2 7
27
100R
6
+3V3
3F21-2 100R
3F21-3 100R3
100R3F21-1 1 8
18
IF23
100R3F20-1
36
2K2
3F24
3F20-3 100R
+3V3
+3V3
2F20
100n
10K
3F19
45
36
18
19
3F22-4 100R
5
6
101114
8
7
12
37
13
35383940454647348
4
21222324252627
28
2
33
34
30313241424344
1
15
20
7F20
NAND04GW3B2DN6F
Φ
[FLASH]
4G × 16
17916
29
36
45
3F22-3 100R
18
100R3F21-4
100R3F22-1
IF22
IF21
10K3F23
100R3F20-4 4 5
100n
2F21
NAND-CE1n
NAND-RDY1n
XIO-D01
XIO-D00
XIO-D03
XIO-D02
XIO-D05
XIO-D04
XIO-D07
XIO-D06
NAND-ALE
NAND-CLE
XIO-OEn
XIO-WEn
NAND-WPn
EN 83Q551.1L LA 10.
back to
div. table
2010-Oct-01
Circuit Diagrams and PWB Layouts
Flash
Page 84
18770_902_100406.eps
100406
USB Hub
B01C B01C
2010-02-01
2
8204 000 9081
TUNER, HDMI & CI
+T
VDD_3V3
CR PLL
FILT
OSC1
OSC3
OSC2
VIA
GND_HS
USBUP
NC
VBUS_DET
RESET
DM
XTALOUT
DP
RBIAS
TEST
+T
2F33 A5
5
3F31-2 C2
3F34-3 D8
E
9
3F26-1 A8
IF33 B2
3F26-3 A8
31
2F26 A2
3F35 B1
9F20 B7
9F25 B8
1F24 E9
9F21 B7
1P07 B9
1P08 D9
2F25 A2
IF43 A3
IF44 A3
3F34-4 D8
78
A
IF34 B2
3F31-3 C2
C C
56
D
FF39 E8
3F25 A8
3F26-2 A8
FF40 A8
IF30 C2
9F26 B8
IF41 C2
IF42 C2
2F34 B1
2F35 B2
IF32 C1
2
FF35 C7
4
8
D
E
IF39 D2
1F25 B1
3F34-2 C8
3F28 B2
3F30 C2
4
FF30 E8
FF31 E9
FF32 E9
SIDE USB BOTTOM
FF37 D7
FF38 E9
3F31-4 D2
3F36 D6
7F25 B2
2
IF31 C1
2F29 A4
6
SIDE USB TOP
2F32 A5
3F34-1 C8
1
2F31 A5
IF40 C2
3F32 C8
B
A
B
IF36 C5
3F26-4 B8
3
FF36 D7
2F30 A4
9
IF45 D9
IF35 B5
IF37 C5
FF33 C97FF34 C7
2F27 A2
2F28 A4
IF32
FF33
IF42
9F26
IF31
+5V
3F26-2
100K
27
+5V
0R4
3F25
100n
2F31
1u0
2F28
2
4
13
1F25
24M
FF30
9F25
2F26
100n
IF34
FF36
IF33
+3V3
10p
2F35
3F36
10K
100n
2F25
IF30
IF39
100n
2F33
+5V
+3V3
56
292303-4
1P07
1
2
3
4
IF41
IF36
36
FF35
3F34-3
100K
FF34
+3V3
3F30
12K
123
4
56
1P08
292303-4
5
IF37
3F26-4
100K
4
FF38
12345
67
1F24
502382-0570
3F35
10K
FF40
100K
3F26-3
36
27
10K
3F31-2
IF40
1
3F34-4
45
3F34-1
100K
0R4
100K
3F32
IF45
100n
2F29
3F34-2
27
100K
+5V-USB2
9F21
2F30
100n
36
38
39
40
41
XTALIN|CLKIN
33
32
2F27
1u0
USBDP_DN2|PRT_DIS_P2
4
USBDP_DN3|PRT_DIS_P3
7
31
27
5
10
29
15
23
24
SDA|SMBDATA|NON_REM1
22
SUSP_IND|LOCAL_PWR|NON_REM0
28
11
USBDM_DN1|PRT_DIS_M1
1
USBDM_DN2|PRT_DIS_M2
3
USBDM_DN3|PRT_DIS_M3
6
30
USBDP_DN1|PRT_DIS_P1
2
9
20
21
13
17
19
34
35
26
SCL|SMBCLK|CFG_SEL0
BC_EN1|PWRTPWR112BC_EN2|PWRTPWR2
16
BC_EN3|PWRTPWR3
18
14
37
HS_IND|CFG_SEL1
25
8
7F25
USB2513B-AEZG
USB HUB
Φ
45
FF37
10K
3F31-4
3F28
1M0
+5V-USB2
IF44
2F32
100n
IF43
FF39
+3V3
+5V-USB1
FF31
6
3F31-3
10K
3
100K
3F26-1
1
9F20
IF35
10p
2F34
FF32
USB-DP1
USB-DP
USB-DM1
USB-DM
RESET-USBn
+5V-USB1
USB-DM2
USB-DP2
USB-DP2
USB-DM2
USB-OC3n
USB-OC2n
USB-OC1n
USB-DM3
USB-DP3
USB-OC1n
USB-OC2n
USB-OC3n
USB-DM1
USB-DM2
USB-DM3
USB-DP1
USB-DP2
USB-DP3
USB-DM
USB-DP
EN 84Q551.1L LA 10.
Circuit Diagrams and PWB Layouts
back to
div. table
2010-Oct-01
USB Hub
Page 85
18770_903_100406.eps
100406
SD Card
B01D B01D
2010-02-01
2
8204 000 9081
TUNER, HDMI & CI
+T
3F41-1 C1
3F41-2 C1
3F44-2 C3
A
D
A
B
FF47 C3
IF47 B11D 2-24F34D 2-90P1
3F42-3 D1
3F43-1 C3 FF50 D3
FF44 D3
3F41-4 C1
3F42-1 C1 3F43-2 C3
3F43-3 C3
2F40 A2
3F40 A2
3
3C 1-44F31C 3-14F3
2
4
1
FF46 C4
B
C
FF49 C3
34
FF48 C3
IF46 D1
FF41 C3
FF42 C3
FF43 C3
C
D
1P09-1 C4 3F44-3 C3
3F45 C1
FF45 A2
12
27
+3V3
18
100R
3F43-2
45
3F42-1
47K
18
3F41-4
47K
6
3F44-1
100R
3F43-3
100R
3
3F44-3
36
100R
3F45
10K
RES
FF42
+3V3 +3V3-SD
11
12
FF41
14
1P09-2
1939115-1
10
123456789
13
1P09-1
1939115-1
FF50
FF48
FF49
FF47
36
27
47K
3F42-3
18
3F42-2
47K
6
3F41-1
47K
47K
3
F41-3
3
3F41-2
27
100R
3F44-2
27
47K
18
+3V3-SD
100R
3F43-1
16V
22u
2F40
0R4
3F40
IF47
IF46
FF46
FF45
FF44
FF43
SDIO-DAT3
SDIO-CMD
SDIO-CLK
SDIO-DAT0
SDIO-DAT1
SDIO-DAT2
SDIO-CDn
SDIO-WP
SDIO-DAT3
SDIO-CMD
SDIO-DAT0
SDIO-DAT1
SDIO-DAT2
SDIO-CDn
SDIO-WP
SDIO-CLK
EN 85Q551.1L LA 10.
back to
div. table
2010-Oct-01
Circuit Diagrams and PWB Layouts
SD Card
Page 86
18770_904_100406.eps
100406
PNX85500 Control
B01E B01E
2010-02-01
2
8204 000 9081
TUNER, HDMI & CI
SCL
ADR
012SDA
WC
D
C
S
W
HOLD
VSS
Q
VCC
B
C
D
89
7F52 B2
7F53 B7
7F54-1 C7
D
E
F
1F51 F8
LEVEL
7F58 D1
9CH0 C7
FF04 C4
3F60 E3
3F62 D5
1
SDA
USE ONLY
1234
MAIN NVM
3F59 E3
FF63 E4
FF64 F7
FF65 F4
3F58 E1
IF50 B3
IF51 B1
IF52 B3
234
3F53 C6
3F54 D7
A
E
F
A
3F66 B7
89
IF59 E1
IF61 C4
IF62 C4
7F54-2 C7
B
C
2F52 B1
2F53 D6
2F58 D2
3F51 B1
3F52 B3
1F52 D8
FF57 E2
567
FF66 F4
567
3F63 E5
3F64 F5
3F65 F5
IF55 C6
3F67 B6
3F68 C7
3F69 D7
IF58 D2
DEBUG / RS232 INTERFACE
SCL
IF53 B3
IF54 C3
DEBUG ONLY
FF29 C4
FF55 E3
FF56 E3
SHIFTED
UP
FF58 C7
FF61 D4
FF62 D7
DEBUG
IF56 C7
IF57 C7
3F53
FOR
IF53
10K
10K
3F66
RES
+3V3-STANDBY
10K
3F67
RES
IF54
FF63
+3V3-STANDBY
FF56
3F63
100R
FF55
10K
3F52
FF29
3F59
100R
100R
3F65
IF58
IF62
IF59
3F60
100R
FF65
2
3
4
5
3F51
10K
1F52
1
IF52
+3V3
+3V3-STANDBY
+3V3
RES
2F58
100n
7F54-1
BC847BPN(COL)
2
6
1
7
FF66
RES
1
2
3
6
5
84
(8K × 8)
Φ
EEPROM
7F58
7F54-2
BC847BPN(COL)
5
3
4
7
RES
1
2
3
4
5
6
1F51
3F58
10K
9CH0
RES
IF51
IF57
RES
RES
1u0
2F53
3F54
1K0
100R
3F64
+5V
+3V3-STANDBY
1
84
3
FF61
FLASH
512K
Φ
6
5
7
2
7F52
M25P05-AVMN6
RES
47K
3F68
FF62
10K
IF61
3F69
RES
FF04
7F53 RES
PDTA114EU
3F62
100R
FF64
+3V3
FF57
RES
IF50
100n
2F52
IF56
IF55
+3V3
BOOST-PWM
BACKLIGHT-BOOST
SDM
SPI-PROG
RESET-STBYn
SPI-PROG
FF58
PNX-SPI-CLK
PNX-SPI-SDO
PNX-SPI-CSBn
PNX-SPI-SDI
PNX-SPI-WPn
SDA-UP-MIPS
SCL-UP-MIPS
SCL-SSB
SDA-SSB
TXD-UP
RXD-UP
EN 86Q551.1L LA 10.
back to
div. table
2010-Oct-01
Circuit Diagrams and PWB Layouts
PNX85500 Control
Page 87
18770_905_100406.eps
100406
HDMI & CI
B01F B01F
2010-02-01
2
8204 000 9081
TUNER, HDMI & CI
IO2IGNDO1GND
AGC CONTROL
IF16 B10
IF72 C5 IF82 C4
IF86 C5
IF87 C2
9F02 A8
9F03 A8
IF75 B6
IF76 B8
IF77 B6
IF78 B8
IF79 C5
IF80 B8
IF81 B6
FF71 A1
FF74 B1 IF88 D2
IF89 D5
IF90 D7
2F94 D7
3F71 C7
FF75 B2
FF76 B1
FF81 C1
FF82 C2
IF10 A5
IF11 A5
IF12 C9
IF13 C9
IF14 C9
IF15 C9
5F66 C10
5F70 D6
A
5F71 B9
5F72 E4
5F76 B10
6F72 C7
IF73 B6
IF74 B8
9F00 A6
9F01 A6
2F73 A9
2F74 B6
9F04 B3
9F05 C4
9F06 C4
9F71 E4
AF70 B3
AF71 B3
AF72 B9
AF73 B9
FF00 B2
FF01 C4
2F86 D1
2F88 E5
2F60 B1
2F92 C7
2F93 C2
23
3F72 C7
3F75 D2
3F76 C2
3F77 C4
3F78 C7
3F79-1 B8
3F79-4 B8
3F80 C9
3F81 C9
3F82 B10
D
E
2F61 B1
5F73 C5
5F74 B10
2F64 C9
2F65 B10
7F70 D8
7F75 A6
2F71 A7
2F72 A9
2F75 B8
2F76 B9
2F77 B9
2F78 B6
2F79 B8
2F80 B9
2F81 B1
2F82 B9
2F84 C1
2F85 C4
B
C
D
E
1F75 B5
1T01 A1
2F59 B1
23 67
2F90 C6
2F91 D6
10
1 45678910
A
B
C
2F62 B10
2F63 C9
2F66 C10
2F70 B10
14589
9F03
15p
27F208F2
15p
FF74
9F01
10n
2F78
7F70
PDTC114EU
IF87
IF88
+5V-TUN-PIN
FF00
IF78
IF82
23
14
4
5
ATB2012
5F73
X7251X
1F75
36M17
312
2F60
100n
AF71
470n
5F70
AF70
2F88
IF72
22u
680n
5F71
9F00
1p0
2F73
+5V-TUN
IF76
3F71
4K7
FF71
2F85
47n
2F70
1p0
+5V-TUN-PIN
FF82
15p
2F84
2p2
2F76
IF77
RES
2F90
10n
IF10
10n
2F63
3F79-4
220R
4
AF72
2F82
1p0
2F62
10p
330n
5F76
IF12
2F75
3F78
3K3
10n
2F94
+5V-TUN-PIN
RES
10n
220R
3F79-1
1
100n
2F93
47R
3F75
IF89
4u7
2F59
9F71
RES
820R
3F82
AF73
IF15
OUTPUT1
6
OUTPUT2
4VAGC
1
VCC
2F61
4u7
8
GND1
5
GND2
2 INPUT1
3 INPUT2
7
IF74
7F75
UPC3221GV-E1
3F77
4K7
RES
5F72
30R
IF73
4n7
2F81
RES
FF75
9F05
2F74
10n
15p
+5V-TUN-PIN
2F86
FF76
IF14
2F79
10n
IF81
IF11
10n
2F91
FF81
RES
IF16
15p
2F65
22p
2F77
IF80
2F66
22p
5F74
820n
10n
2F64
FF01
9F02
3F72
1K0
6F72
BA591
IF75
3F76
47R
9F04
2F92
10n
3F80
220R
IF90
15
16
NC
12
RF_AGC
3
RF_IO
1
TUN
4
8
B+_TUN
I2C_ADR
5
I2C_SCL
6
7
I2C_SDA
10
IF_OUT1
11
IF_OUT2
13
14
9
4MHZ_REF
B+_LNA
2
10n
TUNER
TX31XX
1T01
2F71
5F66
680n
9F06
IF79
3F81
220R
IF86
IF13
PNX-IF-AGC
TUN-P6
TUN-P7
TUN-P1
TUN-IF-P
TUN-P6
SDA-TUNER
SCL-TUNER
TUN-IF-N
TUN-P7
IF-AGC
IF+
IF-
SELECT-SAW
IF-AGC
TUN-IF-N
TUN-IF-P
PNX-IF-P
PNX-IF-N
EN 87Q551.1L LA 10.
back to
div. table
2010-Oct-01
Circuit Diagrams and PWB Layouts
HDMI & CI
Page 88
18770_906_100406.eps
100406
Toshiba Supply
B01G B01G
2010-02-01
2
8204 000 9081
TUNER, HDMI & CI
COM
OUTIN
23
23
D
A
C
D
1
5FA3 B2
5FA4 B3AFFA2 C2
FFAF B2
B
2FA2 C1
7FA3 B2
1
B
C
2FA3 C2
2FA4 C3
30R
5FA4
5FA3
30R
2FA4
10u
100n
2FA3
FFAF
1
32
FFA2
7FA3
LD1117DT12
2FA2
100n
+1V2-BRA-DR1
+1V2-BRA-VDDC
+3V3
EN 88Q551.1L LA 10.
back to
div. table
2010-Oct-01
Circuit Diagrams and PWB Layouts
Toshiba Supply
Page 89
18770_907_100406.eps
100406
HDMI
B01H B01H
2010-02-01
2
8204 000 9081
TUNER, HDMI & CI
1
B
3
C
B
1P05 B1
C
12
FFB1 C2 FFB2 C2 FFB5 C1
HDMI CONNECTOR SIDE
FFB6 C2
A
23
4
4
A
FFB1
FFB3 C2 FFB4 C23FBF-1 C4 3FBF-2 C4
FFB5
FFB6
FFB4
FFB2
FFB3
27
DIN-5V
47K
3FBF-2
18
DIN-5V
3FBF-1
47K
DIN-5V
56789
2021
2223
12131415161718
19
234
1
10
11
1P05
DRX2+
DRXC+
DRXC-
PCEC-HDMI
DRX-DDC-SCL
DRX-DDC-SDA
DRX-HOTPLUG
DRX2-
DRX1+
DRX1-
DRX0+
DRX0-
DRX-DDC-SCL
DRX-DDC-SDA
EN 89Q551.1L LA 10.
back to
div. table
2010-Oct-01
Circuit Diagrams and PWB Layouts
HDMI
Page 90
18770_908_100406.eps
100406
VGA
B01I B01I
2010-02-01
2
8204 000 9081
TUNER, HDMI & CI
261
53
1FC1 B4
6FC5 D5
9
B
3
D
1FC2 B4
1FC3 C4
1
2FC8 F4
2FC1 B4
2FC2 B4
2FC3 C4
8
2FC6 E4
FFC2 B4
1FC6 F4
1E05 B2
VGA
FFC9 E4
7
3FC2 E393FC4 D6
4
7
2FC5 D4
1FC5 D4
F
6FC4 C5
3FC7 C6
6FC6 E5
6FC7 E5
A
C
F
2FC4 C4
B
1FC4 C4
D
3FC1 D3
C
FFC3 C4
FFC4 C3
9FC2 E6
FFC6 D2
FFC7 D4
FFC8 D4
6FC2 B5
2
3FC6 B646FC1 B5
FFC5 C4
8
CONNECTOR
FFC1 A4
9FC1 D6
6FC3 C5
6
FFC1
E
A
9FC6 D6
2FC7 E4
6FC8 F5
3FC5 A6
E
9FC3 E6
9FC4 E6
9FC5 C6
3FC3 C6
5
12V
CDS4C12GTA
6FC7
FFC8
FFC6
6FC5
12V
RES
CDS4C12GTA
47p
2FC8
9FC6
1FC2
9FC3
18R
3FC7
1FC3
6FC6
CDS4C12GTA
12V
3FC3
4K7
2FC7
47p
6FC8
CDS4C12GTA
12V
1FC6
6FC3
CDS4C12GTA
12V
RES
RES
1FC4
10K
3FC2
FFC5
6FC1
CDS4C12GTA
12V
RES
47p
2FC6
4K7
3FC4
9FC1
9FC2
RES
1FC1
FFC9
FFC4
3FC6
18R
18R
3FC5
5
678
9
16
17
1
10
11
12
131415
2
3
4
1216-00D-15S-1EF
1E05
12V
47p
2FC5
RES 6FC2
CDS4C12GTA
12V
1FC5
RES 6FC4
CDS4C12GTA
2FC3
100p
2FC4
47p
FFC7
9FC4
RES
FFC2
9FC5
FFC3
100p
2FC1
100p
2FC2
3FC1
10K
RES
VGA-SCL-EDID
VGA-SDA-EDID
VGA-SDA-EDID-HDMI
VGA-SCL-EDID-HDMI
+5V-VGA
R-VGA
G-VGA
B-VGA
H-SYNC-VGA
V-SYNC-VGA
EN 90Q551.1L LA 10.
back to
div. table
2010-Oct-01
Circuit Diagrams and PWB Layouts
VGA
Page 91
18770_909_100406.eps
100406
Temp Sensor + Headphone
B01J B01J
2010-02-01
2
8204 000 9081
TUNER, HDMI & CI
C
7
6FD2 D4
23
IFD2 B3
IFD3 B4
4
2FD1 A4
2FDC D5
89
B
C
12
3FD1 A3
IFD4 B3
E
A
B
6
3FD6 C4
3FD7 C4
34
5
1FD2 D4
1FD3 D5
6FD1 B3
D
E
3FD4 B2
6FD3 D5
A
2FDD D5
IFD5 B4
3FDG-2 D4
3FD3 B3
3FDG-1 D417FD1 B3
9FD1 A4
9FD2 A4
9FD5 C5
IFD1 B4
1328 D6
1329 C6
100n
2FD1
56789
FFDA D5
FFDB D5
FFDC D6
D
3FD2 B5
3FD2
1K0
RES
9FD5
9FD1
9FD2
FFDB
FFDA
12V
6FD3
CDS4C12GTA
IFD2
RES
1K0
3FD1
3FDG-2
1K0
27
RES
1K0
3FD6
IFD3
1n0
2FDD
IFD1
FFDC
1FD2
18
+3V3
1K0
3FDG-1
RES
6FD1
LTST-C190KGKT
1328
MSJ-035-29D PPO (PHT)
2
1
3
A2
5
4
GND
OS
3
SCL
2
SDA
1
7FD1
+VS
8
A0
7
6
A1
LM75BDP
2FDC
1n0
RES3FD7
1K0
3FD3
100R
100R
5
3FD4
1
2
3
4
IFD4
502382-0370
1329
1FD3
IFD5
SDA-SSB
SCL-SSB
AMP1
AMP2
12V
CDS4C12GTA
6FD2
EN 91Q551.1L LA 10.
back to
div. table
2010-Oct-01
Circuit Diagrams and PWB Layouts
Temp Sensor + Headphone
Page 92
18770_910_100406.eps
100406
Tuner Brazil
B01K B01K
2010-02-01
2
8204 000 9081
TUNER, HDMI & CI
X
XSEL
ADI_AI
ADQ_AI
AD_VREF
TSMD
TN
SLADRS
VSS
DR2VDD
DR1VDD
VDDS
AD_DVDD
AD_AVDD
PLLVDD
VDDC
PBVAL
RERR
RLOCK
RSEORF
SBYTE
SLOCK
SRCK
SRDT
STSFLG1
AGCCNTI
AGCCNTR
STSFLG0
SYRSTN
0
1
SCL
SDA
FIL
AD_AVSS
AD_DVSS
PLLVSS
IO01PNPNPNAD_VREF
DTCLK
DTMB
S_INFO
0
1
AGCI
CKI
SCL
SDA
OUTIN
INH BP
COM
3FE9 F3
3FG2-1 F6
IF48 C12
DFE8 D6
2FG2 D1
2FG3 D2
DFE9 E6
DFF1 E6
9F27-1 E8
IF69 C6
3FG2-2 F7
3FG4-1 F7
3FG4-2 F6
3FG6-2 E7
3FG6-3 E7
IF27 E7
IF28 E7
IF29 F4
5FE3 B3
IF49 F4
IF63 A4
IF64 A5
IF65 B4
IF66 B5
IF67 B4
IF68 B5
DFF2 F6
FF03 C12
IF17 D4
IF18 D4
34
2FG4 D3
2FG6 D3
2FG7 E3
2FG8 E3
2FG9 E3
7FE0 D4
7FE3 C11
2FH5 D6
9F27-2 D8
9F27-4 D8
9F28 E8
BFE2 E4
BFE3 E4
DFE6 D6
DFE7 D6
2FE6 B3
2FE8 C3
2FF0 A6
3FG6-4 D7
3FG7 E7
5FE0 A3
2FF4 B6
5FE4 B7
5FE5 B3
5FE7 C11
5FE8 C7
5FE9 C11
5FG0 E11
5FG2 E11
56789
2FH2 D11
2FH3 D12
2FH4 D12132FH6 E3
2FH7 E3
2FH8 F7
3FE5 E7
3FE6 F3
3FE7 F3
3FE8 F3
2FE0 A3
2FE3 A6
2FE4 A6
2FE5 A6
1234
2FF1 A7
2FF2 B6
2FF3 B682FF5 B6
2FF6 B7
2FF7 C6
2FF8 C6
2FF9 C7
2FG0 C6
2FG1 C7
12 13
12
H
A
B
10 11 12
E
A
B
C
D
E
F
G
C
D
567
F
G
H
1FE0 C2
91011
1u0
2FE8
10n2FG6
2FH7 100n
30R
5FE0
2FG7 100n
IF69
AGND
3FE7 10K
IF66
DFE8
2FF4
100n 100n
2FE5
4K7
3FG4-1
30R
5FE5
3
2
30R
5FE9
15
33
37
44
47
50
57
62
19
18
41
16
36
56
63
13
35
49
64
4
5
52
61
60
513842812
14
1
58
20
17
53
54
55
59
45
46
6
24
9
10
7
11
34
48
43
39
40
21
29
302728
2223
32
31
26
25
Φ
TC90517FG
7FE0
1u0
2FH4
AGND
3FG2-2
10K
3FG7 33R
1u0
2FF6
IF48
DFF2
DFE6
IF27
AGND
IF68
AGND
100n
2FE3
AGND
100n2FG8
5FE3
30R
3FG2-1
10K
3FG6-2 33R
27
100n
2FF7
2FF1
1u0
45
DFE9
1
3
5
9F27-4
LD3985M25
7FE3
4
2
IF29
3FG4-2
4K7
30R
5FE8
2FH3
10n
IF65
9F27-2
27
IF67
100n
2FG0
10K3FE6
100n
2FF3 2FE4
100n
3FE9 100R
18
AGND
9F27-1
18K
3FE5
DFE7
100n
30R
5FG2
2FF2
1u0
2FE0
100n
2FF5
BFE3
2FF0
100n
9F28
IF64
2FH8
10n
1u0
2FG1
IF18
IF28
AGND
2FH6 100n
2FG4 10n
2FF8
100n
2FF9
1u0
AGND
36
5
3FG6-3 33R
3FG6-4 33R
4
IF49
AGND
DFF1
24
13
1FE0
25M4
AGND
100R3FE8
30R
5FG0
100n2FG9
30R
5FE7
AGND
IF63
2FH2
1u0
IF17
BFE2
AGND
18p
2FG2
2FE6
1u0
FF03
1n5
2FH5
5FE4
30R
+3V3-BRA-FLT
TS-DVBS-DATA
TS-DVBS-VALID
TS-FE-SOP
TS-DVBS-SOP
TS-FE-CLOCK
TS-DVBS-CLOCK
2FG3
18p
IF+
RESET-SYSTEMn
+1V2-BRA-VDDC
+1V2-BRA-DR1
+3V3-BRA-FLT
+3V3-BRA-FLT
+3V3-BRA-FLT
+2V5-BRA
+3V3-BRA
+2V5-BRA
SCL-SSB
SDA-SSB
IF-
TS-FE-DATA
IF-AGC
TS-FE-VALID
+2V5-BRA
+5V
+3V3
+3V3-BRA
EN 92Q551.1L LA 10.
Circuit Diagrams and PWB Layouts
back to
div. table
2010-Oct-01
Tuner Brazil
Page 93
18770_760_100728.eps
100728
Common Interface
B01A B01A
2010-03-1232010-02-01
2
8204 000 9081
TUNER, HDMI & CI
G3
1
2
3EN2
3EN1
G3
1
2
3EN2
3EN1
G3
1
2
3EN2
3EN1
G3
1
2
3EN2
3EN1
G3
1
2
3EN2
3EN1
+T
G3
1
2
3EN2
3EN1
2F00 A6
3F07-4 A9
3F09-3 B9
IF02 A5
3F05-1 C4
3F04-2 C4
3F05-4 C4
3F11-4 D9
3F04-3 C4
3F03-1 A4
3F03-2 A4
G
IF06 C5
B
1
3F12 C9
2F02 B6
3F07-2 A9
7F05 I5
3F07-1 A9
8
E
3F08-1 A9
3F08-2 A9
IF03 A4
IF04 B9
3F09-1 B9
3F08-4 B9
7F02 D5
F
1P00-B G10
4
11
3F04-4 C4
11
3F07-3 A9
2F06 H6
IF01 A4
3F02 A4
2F05 G6
7F01 B5
CONTROL
3F09-4 B9
3F11-1 D9
7F03 E5
5
3F11-3 D9
IF07 C5
3F06 A9
D
3F10-1 C9
TRANSPORT STREAM FROM CAM
8-BIT DATA
I
3F09-2 B9
23
2F04 E6
D
3F04-1 C4
F
3F11-2 C9
3F01 A2
10
2F01 A2
C
10
IF08 D9
2
7F04 G5
9
3F10-3 C9
3F10-4 C9
C
A
IF05 C4
3F10-2 C9
9
A
8
G
7
15-BIT ADDRESS
3F05-3 C4
6
3F05-2 C4
I
H
3F08-3 B9
B
27
7
E
4
615
2F03 D6
3
H
1P00-A D10
7F00 A5
8
3F08-2
10K
3F05-1 100R13F04-3 100R36
45
3F10-4
10K
3F08-4
10K
45
10K
36
18
3F09-3
3F04-1 100R
1
8
45
3F11-1
10K
100R3F04-4
11
1
10
19
20
789
18171615141312
74LVC245A
7F03
23456
45
3F11-4
10K
100R
18
3F03-1
IF02
+3V3
100n
2F06
+3V3
RES
10K
3F08-3
36
131211
1
10
19
20
4
5
6
789
181716
15
14
74LVC245A
7F01
2
3
45
18
10K
3F09-4
10K
3F10-1
IF03
100R
3F05-3 3 6
3F12
10K
+3V3
+5VCA
IF07
1
10
19
20
8
9
181716
1514131211
23456
7
7F00
74LVC245A
REF EMC HOLE
1X01
RES
100n
2F04
100R
3F03-2
27
45
+3V3
100R
3F05-4
10K
3F11-3
36
3F02
100R
12
11
1
10
19
20
56789
1817161514
13
74LVC245A
234
7F04
IF06
WE|P
15
33
WP|IOIS16
IF01
GND1
1
34
GND2
6970
OE
9
RDY|BSY
16
VCC1
17
VPP1
18
7
D0
30D131
D2
32
D32D4
3
4
D5
D65D7
6
27A326A425A524A623A722
12
A8
A9
11
CE1
A10
8
A11
10
A12
21
A13
13
A14
14
A1520A16
19
A2
10074595-050MLF
ROW_A
1P00-A
A0
29A128
100K
3F06
REF EMC HOLE
1X04
100n
2F02
RES
45
+5V
3F07-4
10K
+5VCA
RES
IF04
2F03
100n
3F09-1
10K
18
RES
43
VS1
57
VS2
59
WAIT
16V22u
2F01
INPACK
44
IORD
45
IOWR
71
72
61
REG
58
RESET
51
VCC2
52
VPP2
39
D1340D1441D15
64D865
D9
35
GND3
68
GND4
60
BVD1|STSCHG
62
BVD2|SPKR
36
CD1
67
CD2
42
CE2
66
D10
37
D1138D12
47
A1848A1949A2050A2153A2254A2355A2456A25
63
1P00-B
ROW_B
10074595-050MLF
46
A17
141312
11
1
10
19
20
3
45678
9
181716
15
74LVC245A
7F05
2
36
10K
3F10-3
3F04-2 2 7 100R
27
+3V3
+3V3
+5VCA
3F05-2 100R
+3V3
3F11-2
10K
27
8
10K
3F08-1
1
IF05
2F05
100n
RES
3F07-2
27
10K
0R4
3F01
27
3F10-2
10K
3F07-3
10K
36
10K
3F09-2
27
RES
2F00
100n
+3V3
+3V3
10K
3F07-1
18
20
17
161514
131211
1
10
19
2
34567
8
9
18
7F02
74LVC245A
+5VCA
IF08
CA-D03
CA-D04
CA-D05
CA-D06
CA-D07
CA-DATADIR
CA-DATAENn
MOVAL
MOSTRT
MDO0
MDO1
MDO2
MDO3
MDO4
MDO5
MDO6
MDO7
CA-WAITn
CA-INPACKn
CA-WP
CA-VS1n
CA-RDY
CA-D00
CA-D01
CA-D02
CA-WEn
CA-OEn
CA-CE2n
CA-CE1n
CA-REGn
CA-MOCLK
CA-MOVAL
CA-MOSTRT
CA-MDO0
CA-MDO1
CA-MDO2
CA-MDO3
CA-MDO4
CA-MDO6
CA-MDO5
CA-MDO7
CA-RST
CA-CD1n
CA-CD2n
CA-DATAENn
CA-DATADIR
CA-ADDENn
MOCLK
XIO-D07
XIO-D06
XIO-D05
XIO-D04
XIO-D03
XIO-D02
XIO-D01
XIO-D00
CA-ADDENn
CA-WAITn
XIO-D15
XIO-D14
XIO-WEn
XIO-OEn
XIO-D08
XIO-D09
XIO-D11
XIO-D10
CA-IOWRn
CA-IORDn
CA-A03
CA-A04
CA-A05
CA-A06
CA-A07
XIO-A00
XIO-A01
XIO-A02
XIO-A03
XIO-A04
XIO-A05
XIO-A06
XIO-A07
CA-ADDENn
CA-A08
CA-A09
CA-A10
CA-A11
CA-A12
CA-A13
CA-A14
XIO-A08
XIO-A09
XIO-A10
XIO-A11
XIO-A12
XIO-A13
XIO-A14
CA-ADDENn
CA-D07
CA-D06
CA-D05
CA-D04
MOCLK
MOVAL
MOSTRT
CA-D03
MDO0
MDO1
MDO2
MDO3
MDO4
MDO5
MDO6
MDO7
CA-A00
CA-A01
CA-A02
CA-CE2n
MDO7
MDO6
MDO5
MDO4
MDO3
CA-CD1n
CA-WP
CA-D02
CA-D01
CA-D00
CA-A00
CA-A01
CA-A02
CA-A03
CA-A04
CA-A05
CA-A06
CA-A07
CA-A12
CA-MICLK
CA-MIVAL
CA-RDY
CA-WEn
CA-A14
CA-A13
CA-A08
CA-A09
CA-A11
CA-OEn
CA-A10
CA-CE1n
CA-CD2n
MDO2
MDO1
MDO0
MOSTRT
MOVAL
CA-REGn
CA-INPACKn
CA-WAITn
CA-RST
MOCLK
CA-MDI7
CA-MDI6
CA-MDI5
CA-MDI4
CA-MDI3
CA-MDI2
CA-MDI1
CA-MDI0
CA-MISTRT
CA-IOWRn
CA-IORDn
CA-VS1n
EN 93Q551.1L LA 10.
back to
div. table
2010-Oct-01
Circuit Diagrams and PWB Layouts
Common Interface
10-8 B01 820400090813 Tuner, HDMI & CI
Page 94
18770_761_100728.eps
100728
Flash
B01B B01B
2010-03-1232010-02-01
2
8204 000 9081
TUNER, HDMI & CI
WEBR
WP
VCC
VSS
IO
NC
0123456
7
CLE
ALECERE
3F22-2 C1
2
3F21-2 C2
3F21-4 C2
A
7F20 B3
1
3F22-3 C2
D
B
423
2F20 A3
3F19 D2
3F20-2 B2
2C 4-22F31B 3-02F3
3F24 D2
3F21-3 C13F20-1 B1
4
IF22 D3
C
IF21 C3
3F21-1 C12F21 A3
1
D
IF23 D3
3F20-4 C2
A
3F22-1 C2
C
3
100n
2F21
B
3F23 C2
+3V3
27
3F20-2 100R
27
27
100R3F22-2
+3V3
3F21-2 100R
3F21-3 100R36
100R3F21-1 1 8
1 8 100R3F20-1
IF23
6
2K2
3F24
3F20-3 100R3
+3V3
+3V3
2F20
100n
3F19
5
10K
3F22-4 100R4
101114
8
7
12
37
13
36
18
19
404546
47348
456
242526272823334353839
414243
44
1
1520212223
7F20
NAND04GW3B2DN6F
Φ
[FLASH]
4G × 16
17916
293031
32
36
45
3F22-3 100R
100R3F21-4
100R3F22-1 1 8
IF22
IF21
3F23
45
10K
100R3F20-4
NAND-CE1n
NAND-RDY1n
XIO-D01
XIO-D00
XIO-D03
XIO-D02
XIO-D05
XIO-D04
XIO-D07
XIO-D06
NAND-ALE
NAND-CLE
XIO-OEn
XIO-WEn
NAND-WPn
EN 94Q551.1L LA 10.
back to
div. table
2010-Oct-01
Circuit Diagrams and PWB Layouts
Flash
Page 95
18770_762_100728.eps
100728
USB Hub
B01C B01C
2010-03-1232010-02-01
2
8204 000 9081
TUNER, HDMI & CI
+T
VDD_3V3
CR PLL
FILT
OSC1
OSC3
OSC2
VIA
GND_HS
USBUP
NC
VBUS_DET
RESET
DM
XTALOUT
DP
RBIAS
TEST
+T
E
9
3F26-1 A8
IF33 B2
3F26-3 A8
9F21 B7
1P07 B9
1P08 D9
2F25 A2
IF43 A3
IF44 A3
3F34-4 D8
78
A
IF34 B2
2F33 A5
5
3F31-2 C2
3F34-3 D8
FF40 A8
IF30 C2
9F26 B8
IF41 C2
IF42 C2
2F34 B1
31
2F26 A2
3F35 B1
9F20 B7
9F25 B8
1F24 E9
1F25 B1
3F34-2 C8
3F28 B2
3F30 C2
4
FF30 E8
3F31-3 C2
C C
56
D
FF39 E8
3F25 A8
3F26-2 A8
2
IF31 C1
2F29 A4
6
SIDE USB TOP
2F32 A5
3F34-1 C8
1
2F31 A5
IF40 C2
3F32 C8
B
2F35 B2
IF32 C1
2
FF35 C7
4
8
D
E
IF39 D2
3
FF36 D7
2F30 A4
9
IF45 D9
IF35 B5
IF37 C5
FF33 C97FF34 C7
FF31 E9
FF32 E9
SIDE USB BOTTOM
FF37 D7
FF38 E9
3F31-4 D2
3F36 D6
7F25 B2
2F27 A2
2F28 A4
A
B
IF36 C5
3F26-4 B8
+3V3
IF32
FF33
IF42
9F26
+5V
27
IF31
+5V
3F26-2
100K
100n
2F31
0R4
3F25
1u0
2F28
3
24M
2
4
1
FF30
1F25
9F25
36
2F26
100n
100K
3F26-3
27
10K
3F31-2
IF40
IF34
FF36
+3V3
IF33
2F35
10p
3F36
10K
100n
2F25
IF39
IF30
+5V
100n
2F33
23
36
38
39
40
41
XTALIN|CLKIN
33
32
USBDP_DN1|PRT_DIS_P1
2
USBDP_DN2|PRT_DIS_P2
4
USBDP_DN3|PRT_DIS_P3
7
31
27
5
10
29
15
SCL|SMBCLK|CFG_SEL0
24
SDA|SMBDATA|NON_REM1
22
SUSP_IND|LOCAL_PWR|NON_REM0
28
11
USBDM_DN1|PRT_DIS_M1
1
USBDM_DN2|PRT_DIS_M2
3
USBDM_DN3|PRT_DIS_M3
6
30
25
8
9
20
21
13
17
19
34
35
26
BC_EN1|PWRTPWR1
12
BC_EN2|PWRTPWR2
16
BC_EN3|PWRTPWR3
18
14
37
HS_IND|CFG_SEL1
7F25
USB2513B-AEZG
USB HUB
Φ
45
FF37
56
10K
3F31-4
292303-4
1P07
123
4
IF41
IF36
36
3F34-3
100K
FF34
FF35
+3V3
3F30
12K
123
4
56
1P08
292303-4
5
IF37
3F26-4
100K
4
FF38
12345
67
1F24
502382-0570
3F35
10K
FF40
FF32
+5V-USB1
100K
1
100K
3F34-4
45
3F34-1
3F32
0R4
IF45
100n
2F29
100K
3F34-2
27
+5V-USB2
9F21
2F30
100n
2F27
1u0
3F28
1M0
+5V-USB2
IF44
2F32
100n
FF39
+5V-USB1
IF43
+3V3
FF31
3F31-3
10K
36
3F26-1
1
100K
IF35
10p
2F34
9F20
USB-DP1
USB-DP
USB-DM1
USB-DM
RESET-USBn
USB-OC3n
USB-OC2n
USB-OC1n
USB-DM3
USB-DP3
USB-DM2
USB-DP2
USB-DP2
USB-DM2
USB-OC1n
USB-OC2n
USB-OC3n
USB-DM1
USB-DM2
USB-DM3
USB-DP1
USB-DP2
USB-DP3USB-DM
USB-DP
EN 95Q551.1L LA 10.
Circuit Diagrams and PWB Layouts
USB Hub
back to
2010-Oct-01
div. table
Page 96
18770_763_100728.eps
100728
SD Card
B01D B01D
2010-03-1232010-02-01
2
8204 000 9081
TUNER, HDMI & CI
+T
3F41-1 C1
3F41-2 C1
3F44-2 C3
A
D
A
B
FF47 C3
IF47 B1
FF43 C3
C
D
1P09-1 C4
1D 2-24F34D 2-90P1
3F42-3 D1
3F43-1 C3
FF50 D3
FF44 D3
3F41-4 C1
3F42-1 C1 3F43-2 C3
3F43-3 C3
2F40 A2
3F40 A2
3
3C 1-44F31C 3-14F3
2
12 4
1
FF46 C4
B
C
FF49 C3
34
FF48 C3
IF46 D1
FF41 C3
FF42 C3
27
+3V3
3F44-3 C3
3F45 C1
FF45 A2
18
100R
3F43-2
45
3F42-1
47K
18
3F41-4
47K
3F44-1
100R
3F43-3
100R
36
36
100R
3F44-3
3F45
10K
RES
FF42
+3V3 +3V3-SD
11
12
FF41
1P09-2
1939115-1
10
123456789
1314
1P09-1
1939115-1
FF50
FF48
FF49
FF47
18
3F41-1
47K
47K
3F41-3
36
3F41-2
27
100R
3F44-2
27
47K
8
+3V3
-SD
100R
3F43-1
1
16V22u
2F40
0R4
3F40
IF47
IF46
FF45
FF44
FF46
FF43
3F42-3
36
3F42-2
47K
27
47K
SDIO-CLK
SDIO-DAT3
SDIO-CMD
SDIO-CLK
SDIO-DAT0
SDIO-DAT1
SDIO-DAT2
SDIO-CDn
SDIO-WP
SDIO-DAT3
SDIO-CMD
SDIO-DAT0
SDIO-DAT1
SDIO-DAT2
SDIO-CDn
SDIO-WP
EN 96Q551.1L LA 10.
back to
div. table
2010-Oct-01
Circuit Diagrams and PWB Layouts
SD Card
Page 97
18770_764_100728.eps
100728
PNX85500 Control
B01E B01E
2010-03-1232010-02-01
2
8204 000 9081
TUNER, HDMI & CI
D
C
S
W
HOLD
VSS
Q
VCC
SCL
ADR
0
1
2 SDA
WC
USE ONLY
1234
MAIN NVM
3F59 E3
B
C
D
89
7F52 B2
7F53 B7
7F54-1 C7
E
F
A
3F66 B7
89
D
E
F
1F51 F8
LEVEL
7F58 D1
9CH0 C7
FF04 C4
3F60 E3
3F62 D5
1
SDA
1F52 D8
FF57 E2
567
FF63 E4
FF64 F7
FF65 F4
3F58 E1
IF50 B3
IF51 B1
IF52 B3
234
3F53 C6
3F54 D7
A
3F63 E5
3F64 F5
3F65 F5
IF55 C6
3F67 B6
3F68 C7
3F69 D7
IF59 E1
IF61 C4
IF62 C4
7F54-2 C7
B
C
2F52 B1
2F53 D6
2F58 D2
3F51 B1
3F52 B3
FF29 C4
FF55 E3
FF56 E3
SHIFTED
UP
FF66 F4
567
IF57 C7
FOR
IF58 D2
DEBUG / RS232 INTERFACE
SCL
IF53 B3
IF54 C3
DEBUG ONLY
FF58 C7
FF61 D4
FF62 D7
DEBUG
IF56 C7
3F65
IF58
IF62
100R
IF59
3F60
100R
FF65
3
4
5
3F51
10K
1F52
1
2
IF52
+3V3
3F53
IF53
10K
10K
3F66
RES
+3V3-STANDBY
10K
3F67
RES
IF54
+3V3-STANDBY
5
3
4
RES
7F54-2
BC847BPN(COL)
1
234
5
67
1F51
3F58
10K
IF51
9CH0
RES
IF57
RES
1u0
2F53
3F54
1K0
RES
FF63
100R
3F64
100R
FF56
3F63
10K
3F52
FF55
3F59
100R
IF61
FF29
10K
3F69
RES
RES
PDTA114EU
FF04
7F53
FF64
3F62
100R
FF57
+3V3
IF50
100n
2F52
RES
IF55
+3V3
IF56
FF58
+3V3-STANDBY
+3V3
RES
2F58
100n
6
1
RES
7F54-1
BC847BPN(COL)
2
84
7
FF66
7F58
1
2
3
6
5
+3V3-STANDBY
(8K × 8)
Φ
EEPROM
3
FF61
+5V
6
5
7
2
1
84
7F52
M25P05-AVMN6
FLASH
512K
Φ
47K
3F68
FF62
RES
BOOST-PWM
BACKLIGHT-BOOST
SDM
SPI-PROG
RESET-STBYn
SPI-PROG
SCL-UP-MIPS
SCL-SSB
SDA-SSB
TXD-UP
RXD-UP
PNX-SPI-CLK
PNX-SPI-SDO
PNX-SPI-CSBn
PNX-SPI-SDI
PNX-SPI-WPn
SDA-UP-MIPS
EN 97Q551.1L LA 10.
back to
div. table
2010-Oct-01
Circuit Diagrams and PWB Layouts
PNX85500 Control
Page 98
18770_765_100728.eps
100728
HDMI & CI
B01F B01F
2010-03-1232010-02-01
2
8204 000 9081
TUNER, HDMI & CI
IO2IGNDO1GND
AGC CONTROL
IF82 C4
IF86 C5
IF88 D2
IF89 D5
IF90 D7
IF16 B10
IF72 C55F71 B9
5F72 E4
5F76 B10
6F72 C7
IF73 B6
2
C
78FI8B
4
7F
I
9F02 A8
9F03 A8
IF75 B6
IF76 B8
IF77 B6
IF78 B8
IF79 C5
IF80 B8
IF81 B6
FF71 A1
FF74 B1
2F94 D7
3F71 C7
FF75 B2
FF76 B1
FF81 C1
FF82 C2
IF10 A5
IF11 A5
IF12 C9
IF13 C9
IF14 C9
IF15 C9
5F66 C10
5F70 D6
A
2F61 B1
5F73 C5
5F74 B10
2F64 C9
2F65 B10
7F70 D8
7F75 A6
9F00 A6
9F01 A6
2F73 A9
2F74 B6
9F04 B3
9F05 C4
9F06 C4
9F71 E4
AF70 B3
AF71 B3
AF72 B9
AF73 B9
FF00 B2
FF01 C4
2F86 D1
2F88 E5
2F60 B1
1F75 B5
1T01 A1
2F59 B1
23 67
2F90 C6
2F91 D6
2F92 C7
2F93 C2
23
3F72 C7
3F75 D2
3F76 C2
3F77 C4
3F78 C7
3F79-1 B8
3F79-4 B8
3F80 C9
3F81 C9
3F82 B10
D
E
C
2F62 B10
2F63 C9
2F66 C10
2F70 B10
2F71 A7
2F72 A9
2F75 B8
2F76 B9
2F77 B9
2F78 B6
2F79 B8
2F80 B9
2F81 B1
2F82 B9
2F84 C1
2F85 C4
B
C
D
E
1458910
1 45678910
A
B
IF88
+5V-TUN-PIN
FF00
IF78
IF82
23
14
3
1
2
4
5
ATB2012
5F73
X7251X
1F75
36M17
2F60
100n
5F70
AF71
AF70
470n
IF72
22u
2F88
9F00
680n
5F71
1p0
2F73
9F03
2F72
15p15p
2F80
2F85
47n
2F70
1p0
+5V-TUN-PIN
FF82
15p
2F84
2p2
2F76
IF77
RES
2F90
10n
IF10
10n
2F63
3F79-4
220R
4
AF72
2F82
1p0
2F62
10p
330n
5F76
IF12
2F75
3F78
3K3
10n
2F94
+5V-TUN-PIN
RES
10n
9F01
FF74
10n
2F78
7F70
PDTC114EU
IF87
IF89
RES
4u7
2F59
9F71
IF15
820R
3F82
AF73
2F61
4u7
2 INPUT1
3 INPUT2
7OUTPUT1
6
OUTPUT2
4 VAGC
1
VCC
7F75
UPC3221GV-E1
8
GND1
5
GND2
IF74
RES
5F72
30R
3F77
4K7
IF73
RES
4n7
2F81
9F05
FF75
2F74
10n
2F86
15p
IF14
+5V-TUN-PIN
FF76
2F79
10n
+5V-TUN
IF76
3F71
4K7
FF71
RES
10n
2F91
FF81
2F65
IF16
15p
22p
2F77
2F66
22p
IF80
5F74
820n
10n
2F64
FF01
9F02
3F72
1K0
6F72
BA591
220R
3F79-1
1
100n
2F93
47R
3F75
2F92
10n
3F80
220R
IF90
IF_OUT2
13
1415
16
NC
12
RF_AGC
3
RF_IO
1
TUN
4
9
4MHZ_REF
B+_LNA
2
8
B+_TUN
I2C_ADR
5
I2C_SCL
6
7
I2C_SDA
10
IF_OUT1
11
TUNER
TX31XX
1T01
2F71
10n
9F06
5F66
680n
IF79
3F81
220R
IF86
IF13
IF81
IF11
IF75
3F76
47R
TUN-IF-N
TUN-IF-P
PNX-IF-P
PNX-IF-N
9F04
TUN-IF-N
TUN-P7
IF-AGC
IF+
IF-
SELECT-SAW
IF-AGC
PNX-IF-AGC
TUN-P6
TUN-P7
TUN-P1
TUN-IF-P
TUN-P6
SDA-TUNER
SCL-TUNER
EN 98Q551.1L LA 10.
back to
div. table
2010-Oct-01
Circuit Diagrams and PWB Layouts
HDMI & CI
Page 99
18770_766_100728.eps
100728
Toshiba Supply
B01G B01G
2010-03-1232010-02-01
2
8204 000 9081
TUNER, HDMI & CI
COM
OUTIN
1
23
23
D
A
C
D
C
2FA3 C2
2FA4 C3
5FA3 B2
5FA4 B3AFFA2 C2
FFAF B2
B
2FA2 C1
7FA3 B2
1
B
30R
5FA4
5FA3
30R
2FA4
10u
100n
2FA3
FFAF
1
32
FFA2
7FA3
LD1117DT12
+3V3
2FA2
100n
+1V2-BRA-DR1
+1V2-BRA-VDDC
EN 99Q551.1L LA 10.
back to
div. table
2010-Oct-01
Circuit Diagrams and PWB Layouts
Toshiba Supply
Page 100
18770_767_100728.eps
100728
HDMI
B01H B01H
2010-03-1232010-02-01
2
8204 000 9081
TUNER, HDMI & CI
C
FFB1 C2 FFB2 C2 FFB5 C1
HDMI CONNECTOR SIDE
FFB6 C2
1
B
34
4
A
FFB3 C2
B
1P05 B1
C
12
FFB4 C23FBF-1 C4 3FBF-2 C4
A
23
DIN-5V
678
9
2021
2223
1415161718
19
234
5
1
101112
13
1P05
FFB1
FFB5
FFB6
FFB4
FFB2
FFB3
27
DIN-5V
47K
3FBF-2
18
DIN-5V
3FBF-1
47K
DRX-DDC-SCL
DRX-DDC-SDA
DRX2+
DRXC+
DRXC-
PCEC-HDMI
DRX-DDC-SCL
DRX-DDC-SDA
DRX-HOTPLUG
DRX2-
DRX1+
DRX1-
DRX0+
DRX0-
EN 100Q551.1L LA 10.
back to
div. table
2010-Oct-01
Circuit Diagrams and PWB Layouts
HDMI
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