Philips 2N7002F User Guide
查询2N7002F供应商
M3D088
1. Description
2. Features
2N7002F
TrenchMOS™ Logic Level FET
Rev. 01 — 11 February 2002 Product data
N-channel enhancement mode field-effect transistor in a plastic package using
TrenchMOS™1 technology.
Product availability:
2N7002F in SOT23.
■ TrenchMOS™ technology
■ Very fast switching
■ Logic level compatible
■ Subminiature surface mount package.
3. Applications
■ Relay driver
■ High speed line driver
■ Logic level translator.
4. Pinning information
Table 1: Pinning - SOT23, simplified outline and symbol
Pin Description Simplified outline Symbol
1 gate (g)
2 source (s)
3 drain (d)
3
03ab44
12
SOT23
d
g
03ab30
s
1. TrenchMOS is a trademark of Koninklijke Philips Electronics N.V.
Philips Semiconductors
2N7002F
TrenchMOS™ Logic Level FET
5. Quick reference data
Table 2: Quick reference data
Symbol Parameter Conditions Typ Max Unit
V
I
D
P
T
R
DS
tot
j
DSon
drain-source voltage (DC) Tj=25to150°C - 60 V
drain current (DC) Tsp=25°C; VGS= 10 V - 475 mA
total power dissipation Tsp=25°C - 0.83 W
junction temperature - 150 °C
drain-source on-state resistance VGS= 10 V; ID= 500 mA; Tj= 25 1.7 2 Ω
= 4.5 V; ID= 75 mA; Tj= 25 2.25 4 Ω
V
GS
6. Limiting values
Table 3: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DS
V
DGR
V
GS
V
GSM
I
D
I
DM
P
tot
T
stg
T
j
Source-drain diode
I
S
I
SM
drain-source voltage (DC) Tj=25to150°C - 60 V
drain-gate voltage (DC) Tj=25to150°C; RGS=20kΩ -60V
gate-source voltage (DC) - ±30 V
peak gate-source voltage tp≤ 50 µs; pulsed; duty cycle = 25% - ±40 V
drain current (DC) Tsp=25°C; VGS=10V;Figure 2 and 3 - 475 mA
= 100 °C; VGS=10V;Figure 2 - 300 mA
T
sp
peak drain current Tsp=25°C; pulsed; tp≤ 10 µs; Figure 3 - 1.9 A
total power dissipation Tsp=25°C; Figure 1 - 0.83 W
storage temperature −65 +150 °C
operating junction temperature −65 +150 °C
source (diode forward) current (DC) Tsp=25°C - 475 mA
peak source (diode forward) current Tsp=25°C; pulsed; tp≤ 10 µs - 1.9 A
9397 750 09096
Product data Rev. 01 — 11 February 2002 2 of 11
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Philips Semiconductors
2N7002F
TrenchMOS™ Logic Level FET
120
P
der
(%)
80
40
0
0 50 100 150 200
P
tot
P
der
-----------------------
P
tot 25 C°()
100%×=
03aa17
T
(oC)
sp
Fig 1. Normalized total power dissipation as a
function of solder point temperature.
10
120
I
der
(%)
80
40
0
0 50 100 150 200
03aa25
(oC)
T
sp
VGS≥ 4.5 V
I
D
I
-------------------
der
I
D25C
()
100%×=
°
Fig 2. Normalized continuous drain current as a
function of solder point temperature.
03ai11
I
D
(A)
R
= V
DS
/ I
D
DC
(V)
V
DS
1
-1
10
-2
10
1 10 10
DSon
tp = 10 ms
100 ms
1 ms
10 ms
100 ms
2
Tsp=25°C; IDM is single pulse; VGS = 10 V.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 09096
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data Rev. 01 — 11 February 2002 3 of 11
Philips Semiconductors
2N7002F
TrenchMOS™ Logic Level FET
7. Thermal characteristics
Table 4: Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
R
th(j-sp)
R
th(j-a)
thermal resistance from junction to solder point mounted on a metal clad board; Figure 4 - - 150 K/W
thermal resistance from junction to ambient mounted on a printed circuit board;
- - 350 K/W
minimum footprint
7.1 Transient thermal impedance
10
Z
th(j-sp)
K/W
10
10
1
10
3
2
δ = 0.5
0.2
0.1
0.05
0.02
P
single pulse
t
p
-1
10
-5
10
-4
10
-3
10
-2
10
-1
1 10
03ai09
t
p
δ =
T
t
T
(s)
t
p
Mounted on metal clad substrate.
Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration.
9397 750 09096
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data Rev. 01 — 11 February 2002 4 of 11
Loading...