P
26 0.
Power supply (diagram A1)
The switched mode power supply (SMPS is mains isolated The control IC7520 (MC44603AP) gives the pulses for driving FET 7518 with duty cycle control at fixed frequency of nominal 70 kHz in normal operation (in stand-by, slowslat and overload situation the SMPS runs at other fresuppose theory 20 kHz) 107520 is lectured with a slow-start circuitor and has over- and undervoltage-projection of the secondary supply voltages. Unload and overload (short-circuit) protection is also included. In case the load decreases upder a cortain threshold level the SMPS will switch into stand-by-mode (in stand-by SMPS is in the so called "reduced frequency mode": nominal 20 (Hz) The +95V (+VBATT) output gives a stabilised +95V for 14" 20" and 21" in normal operation and approx 102V DC In stand by mode 107541 (TDA9139) having stable regulator o/n +5V and +8V supply and also build in protection circuit for +5V and +8V supply and also build in protection circuit The IC disable the supply, when pill 4 is low (standoy mode) (TDA8373/74) line output is shut "down"). When nin 6 of IC754 Lis low the protection circuit is working +5V & +8V will shut "down" Transistor 7420 & 7421 is a fast discharge arouit (when power switches of
The duty cycle of the power supply depends on T-on of FET TS7518 that is controlled by pin 3 of 1C7520. The 1C detects the variations of the +VBATT (the secondary side of T5545) via sensing-winding 1-2 at the primary side of T5545. The switching period of FET 7518 is divided in three man areas: T-on T-off and T-dead (see Fig. 9.2)
Mains voltage is filtered by L5500, L5501 and L5502 full wave rectified by a diode bridge and smoothed by C2508 to the DC input voltage for the SMPS at pin 7 of T5545 (e.g. 300V DC (or 220V AC mains).
Degaussing.: R3504 is a dual PTC (2PTC's in one housing). After switching "on" the set, the PTC is cold so low-ohmic and so the degaussing current is very high After degaussing, the PTC is heated, so high-ohmic, so in normal operation the degaussing current is very low.
Start-up: Via the start-up circuitry R3530 and R3529 one side of the 220V AC mains is used to start-up IC7520 via the supply pin (Vpin 1). As long as Vpin 1 has not reached 14V5, IC7520 does not start up and only sinks 0.3mA, As soon as Vpin 1 reaches the 14V5, IC7520 starts (FET 7518 into conduction) and pin 1 sinks a typical supply current of 17 mA. This supply current can not be delivered by the start-up circuit, so a take-over circuit has to be available. If no take-over take's place, the voltage on pin 1 will decrease and IC7520 switches off . In that case the restart will start again. Take over of IC7520; During start-up a voltage across winding 1 - 2 is built up. At the moment the voltage across winding 1 - 2 reaches approx. +12V, D6540 start conducting and takes over the supply voltage Vpin 1 of IC7520 (take over current is approx. 17mA)
IC7520 controls the T-on of FET 7518 in all operation modes by 3 mechanisms :
Winding 1 - 2 has the same polarity as the secondary windings that are supplying the load. During T-olf the secondary windings and so winding 1-2 are positive. D6537 conducts and so charges C2537; the DC level across C2537 is a reference for the secondary output voltages (e.g. the +95V) +VBATT. Via R3538, R3539 and potentiometer R3540 for adjusting the +95V (+VBATT) this DC-voltage is bought to the required level for the error amplifier in IC7520 at pin 14. This voltage Vpin 14 is called feedback voltage and is used to control the secondary output voltages.
The current sense voltage Vpin 7 is a measure for the I-prim through FET 7518 The I-prim is converted into a voltage by R3518 The current sense voltage Vpin 7 is used to control both the secondary output voltages and the maximum I-prim(see peak current limiting)
Winding 1 - 2 has the same polarity as the secondary windings that are supplying the load. As a result the voltage across this winding is negative during T-on, positive during T-off and oscillating during T-dead. The so called demagnetisation "DEMAG" in IC7520) function at pin 8 of IC7520 is used for blocking the output Vpin3 during the time that there is still energy in the transformer (Isec not zero). This is realised by delaying the T-on until the demagnetisation Is completely finished in this way the currents and voltages at the moment of switching "on" the FET are controlled.
sique 2.6.6
The error amplifier (block A in Fig. 9.4) compares the feedback voltage Vpin 14 with an internal reference voltage of 2V5 The output voltage Verror-out of this error amplifier is fed to another comparator (block B in Fig. 9.4). This comparator compares the Verror-out and the current sense voltage Vpin 7. As soon as the current sense voltage Vpin 7 becomes higher than the output -voltage of the error amplifier Verror-out, the comparator B gives a spike (the output of comparator B is the so called current sensing output-voltage Vcs out).
Flip flop (block C in Fig. 9.4) drives the output pin 3 (Vpin 3) via a buffer emplifier (block D). The flip flop is set by positive edge of the output of the oscillator (V osc) and reset by the spike Vcs out As a result the pulse Vpin 3 becomes "high" (T-on starts) by the positive edge of Vosc from the internal oscillator and "low" (T-on stops) by the spike of Vcs out (the T-on start will be delayed in case the transformer is not yet demagnetised; see the slow-start procedures).
In case of a stable load, the feedback voltage Vpin 14 (and so also the maximum current sense voltage Vpin 7) remains the same. As a result the T-on and so the duty cycle will remain the same.
In case of an increasing load, the secondary output voltage decreases. The voltage on pin 14 would like to decrease which causes Verror -out to increase. As a result comparator B will give the pulse later: Voin 3 will be "high" for a longer period (longer T-on so the duty cycle increase) and so the secondary output voltages will be increased (corrected). This will give a new balance of feedback voltage Vpin 14 and the internal 2V5 reference voltage, at a new larger duty cycle As a result of the longer T-on, the maximum I-prim increases, so more energy can be stored in the transformer. In this way more energy will be supplied to the load. In case of a decreasing load, the secondary output voltage increases. The voltage on pin 14 would like to increase which causes Verror-out to decrease. As a result comparator B will give the pulse earlier, Vpin 3 will be "high" for a shorter period (shorter T-on so the duty cycle decrease) and so the secondary output voltages will be decreased (corrected). This will give a new balance off feedback voltage Vpin 14 and the internal 2V5 reference voltage, at a new smaller duty cycle.
As a result of the shorter T-on, the maximum I-prim decreases, so less energy can be stored in the transformer. In this way less energy will be supplied to the load. In case the demgnetisation of the transformer is not finished, the positive edge from the oscillator, which will start a new cycle, will be overruled (via buffer block D) as being the starting point of T-on. As a result the T-on will be delayed and so the frequency of the SMPS will go down. This procedure Is used during start-up.
Peak current limiting is realised by an internal clamp at Vpin 7 at 1V DC. Via this clamp the Vpin7 can never exceed 1V DC and so the maximum value of I-prim (maximum current through FET 7518) is determined.
In case the load needs more than the maximum power, by then the I-prim is already at his maximum level so the SMPS will goin overload protection (see foldback principle explained at overload protection).
Chassis L7.2A 26
The T-on control is controlled on a cycle-by-cycle basis (because of the Ilip flop block C in IC7520). This means that in every cycle the T-on is determined again. By doing so the secondary voltages control, peak current limitation and all protections can be very accurate and fast
As soon as Vpin 1 > 14V5 DC the SMPS will start-up. This will be done by a slow-start procedure (both the frequency and the duty cycle will be built up during slow-start). The following 3 phenomena's take place during start-up:
In standby mode the load decreases (see description of standby on the secondary side) under a certain threshold level. The SMPS will determine this threshold level and so switch to the so called "reduced frequency mode" at 20 kHz. This minimal load threshold level is determined by R3532 at pin 12.
9.4.5
D6524 prevents pin 3 of IC7520 from becoming negative (this will destroy the IC) due to stray inductance in the gate part. The safety resistor R3525 limits the drive current to the gate of FET 7518.
In a stable situation Vpin 14 is typical 2V5. Mains Voltage: 110V, 90 - 276V 220 · 240V, 150 - 276V Mains frequency: 50 Hz / 60 Hz Power Consumption: in normal mode 43W +/· 10% 20": 52W +/- 10% 21": 57W +/- 10% < 10W in sland-by mode < 3W option
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signe 260
9.4.1 Over voltage protection of the secondary voltages
After start-up is the supply voltage Vpin 1 taken over by positive winding 1 - 2, and so after start up Vpin 1 is a
measuring point for the secondary output voltages. After startup (via an internal switch) this Vpin 1 is internally tapped (voltage divided) to a voltage which can be measured at pin 6 (so Vpin 6 is also a measuring point for the secondary output voltages). As soon as the voltage Vpin 6 > 2V5 the logic in IC 7520 will shut down the output at pin 3. This 2V5 threshold at Vpin 6 is equivalent to a Vpin1 of 16V DC which is equivalent to a voltage at the supply voltage +VBATT of approx. 95V DC (normal operation) and 102V DC (standby). After switching "off" because of over voltage protection, the IC starts up again (see slow-start).
If the supply vollage Vpin 1 9V DC the output pulse at pin 3 will be shut down. As soon as Vpin 1 7V5, the IC7520 will be totally shut "off" Vpin 1 of 9V DC is equivalent to a voltage at +VBATT of approx. 70V DC (normal operation) and 95V DC (standby). Vpin 1 of 7V5 is equivalent to a voltage at +VBATT of approx. 55V DC (normal operation) and 65V DC (standby).
In case an over voltage situation is sensed at the secondary output voltages, the SMPS will first switch "off" the pulse and then switch "off" the complete IC 7520. In case the IC 7520 is switched "off", the SMPS will switch "off". In case the under voltage situation remains present, the SMPS will give under voltage protection, slow-start, undervoltage protection, slow-start, etc. → a very good audible hick-up mode.
In case the load goes down (e.g. the line goes down because of standby mode or some failure in the line) this is detected by IC7520 via I-prim and secondary output vollages sensing. In case the load decreases below a certain threshold the SMPS will switch in "reduced frequency mode" of 20 kHz (this threshold is determined by the voltage level at pin 12 IC7520);
In case of an unload situation the set will switch to "low (requency mode" or standby mode. Whether this unload situation of the SMPS is caused by the standby command or by a failure (e.g. in the line), can only be determined by switching on the set again which the remote control, in case of standby mode the TV will switch "on" again, in case of unload situation the set will not switch "on".
If the secondary load becomes too high, I-prim becomes too high which is sensed by the current sense voltage Vpin 7. This voltage Vpin 7 is not allowed to exceed 1V DC by IC 7520 and so gives current limiting
As the I-prim is limited, the secondary output voltages will also drop and so supply voltage Vpin 1 will drop. As soon as Vpin 1 < 9V DC the driving pulse at pin 3 will stop. As a result of these 2 mechanism in case of an overload the
secondary voltages will drop very fast. This is called the foldback mechanism, the foldback point can be adjusted by pin 5 IC7520 (for the L7.2 this point is adjusted to a maximum tolerable output power of 85W at 90V AC and 165W at 276VAC. After this foldback, the IC starts up again (see slow-start). In case the overload situation remains present, the SMPS will give foldback again, slow-start, foldback, slow-start, etc;
As a result in case of short-circuit (or overload) the TV will be in a very good audible hick-up mode.
There is a protections available at the secondary & LOT side.
T$7420 and T$7421 forms a fast discharge circuit. When the voltage on the collector of T$7421 is 6V the circuit will switch off the horizontal drive immediately via pin 50 of IC 7225-5D.
In this chip most of the video, audio and sync circuits are integrated. In the diagrams the IC is split up in next 5 parts (5A,5B,5C,5D and 5E).
signe 27 A
The luner 1000 can be a VST or a PLL type. In both cases the luner is controlled by the µC:
Circuit description new circuits
٠ | ||||
---|---|---|---|---|
BS1 | BS2 | |
---|---|---|
VHF1 | 0 | 1 |
VHF2 | 1 | 0 |
UHF | 1 | 1 |
The IF bands pass characteristic is determined by the band pass of the SAW filter 1015.
IF-demodulation is done with reference circuit L5260 at pin 3 and 4 of IC7225-5A AGC control of luner is via pin 54 IC7225-5A to tuner. Top sync level is used for AGC inside IC7225-5A. AGC adjustment is done by 12C control via entry into the SAM service menu. C2202 at pin 53 determines time constant of the AGC. Base band CVBS signal at pin 6 IC7225-5A (normal - 3V2) is fed to the sound trap filters (1206, 1207, 1208, 1209 and 5206) and return to pin 13 IC7225-5B for source selection and video processing (diagram A3). The NTSC_SW signal from the control microprocessor turns on transistors 7216 and 7217 to activate filter 1209 when an NTSC signal is received.
Demodulation for sound IF takes place for the various signals as follows:
For single mono signal, the CVBS_Sound signal goes to filter 1104 for 4.5 MHz and filter 1102 for 5.5 MHz (diagram A5 for Sound_IF detector. The Sound_IF goes to pin 11C7225-5E for demodulation
IC7225-5B contians of source select, PAL/NTSC colour decoder.
The main functions are
Source Selection
The input selector hsa CVBS_INTCVBS_EXT1. Y_CVBSEXT2, C_EXT2 as inputs which can be selected via the 13C but
The main functions are :
PLŁ/VCO
The PLL operates during the burst key period. It synchronises the VCXO oscillator with the frequency and phase of the incoming chroma burst. For alternating burst (PAL standards), a loop filter enables the PLL to synchronise with the average burst (180° phase).
PAL/NTSC lidentification
The 0° and 90° Reference signals from the VCO oscillator are supplied via the HUE phase circuit to the (B-Y)
The demodulated burst from the (B-Y) burst demodulator is supplied both to ACC detector and NTSC ident circuit The NSTC ident circuit is an integrator. Once the Integrator output exceeds the NTSC killer level then an NTSC burst has been identified (ION-t). Therefore the IDN informa-
tion provided the ASM (Automatic System Manager) with NTSC colour ident information.
The demodulated burst from the burst from the (R-Y) burst demodulator is supplied to the PAL ident circuit via a AL switch. The PAL ident circuit is also an integrator Once the integrator output exceed the PAL killer level then a PAL burst has been indentified (IDP=1). The IDP information provides the ASM with PAL-colour ident information. Second Interface
The main functions are
The luminance at pin 27 is internally AC coupled to the luminance clamp, which is operational during burst key period. The luminance signal is supplied to the RGB matrix circuit via the black stretcher. The (B-Y)/(R-Y) signals supplied to pins 31 and 32 respectively are clamped during the burst key period. The signals are then supplied to the colour difference maxtrix to select the desired matrix from either PAL, NTSC or Japanese NTSC matrix. The selected matrix is controlled via the 12C bus. For RGB matrixing the signal outputs from the colour difference matrix are added with the luminance signal
signe 28 A
Chassis L7.2A
RGB signal selection/processing/output stages
Within the RGB signal selection there are three modes to choose from.
Two different microprocessors are used: one with and one without teletext.
In case of TXT, this teletext function is integrated together with the control part in one and the same µC. This µC is drawn in the diagrams with the outer pin numbering.
In case of no TXT another µC is used with fewer pins This µC is used is drawn in the diagrams with the internal pin numbering.
In the description below, the pin numbers mentioned are the numbers mentioned outside the housing of IC 7600 (IC7600 with TXT and IC7601 without TXT), so for the µC with integrated TXT functionally. In case of the µC with integrated leftext function, the CVBS-TXT signal is fed to pin 23 the TXT and OSD- information are combined at pins' 32-33-34.
Before the RGB signal selection the RGB signals are clamped to similar DC level during burst key period.
Selection is controlled by the RGB insertion input voltage at pin 26.
Vollage at pin 26 | selected RGB signals |
---|---|
< 3V | RGB (internal) |
0.9V < V < 3V |
(R_TXT G_TXT 8_TXT
(last insertion on pin 23, 24 and 25) |
> 4V |
OSD can be inserted at the
RGBout pins |
The contrast, brightness and white-point RGB adjustment on the selected RGB signals are controlled by 1°C bus commands. After the adjustment, the three RGB black levels are added to the RGB signals. These three signals are blanked when the RGB blank signal is active. The RGB blanking level tracks with the DC measurement pulse level. The RGB output stages supply the buffered RGB signals the pin 21, 20 and 19 respectively.
The black stretcher circuit, which is only operational during line scan, extends the grey signal level towards the actual black level (that is actual black level measured during burstkey). The amount of extension is dependent upon the difference between actual black level and the darkest part of the incoming video signal. The darkest part of the video signal is registered in the capacitor at pin 39 by means of an internal discharge current approximately 130uA. The black stretcher is made inactive if the voltage at pin 39 is set to ground. This is done by turning on transistor 7220 video the command blackstraw from the microprocessor (when powerchip button on the remote control unit is activated).
The beam current limiter circuit functions as an average while limiter as well as peak white limiter. The average
while limiter needs external circuitry comprising of 7265, and associated components to function. The peak white limiter is an internal detection circuit. The function of the beam current limiter (average white/peak white limiter) reduces the contrast and briobtness of BGB signals.
For beam current limiting, the difference in beam current (1BCL) and an internal charge current (1CHARGE) is stored in capacitor 2460 at pin 22. If 1BCL > 1CHARGE the voltage (VBCL) at pin 22 decreases. For beam current limiter:
contrast reduction begins when VBCL 3.5V
brightness reduction begins when VBCL 2.5V VBCL is normally 4V when beam current limiter is not active. The contrast and/or brightness reduction of the RGBout is proportional to the voltage decrease at pin 22.
9.6.4 Horizontal synchronisation IC 7225-5D and the line output stage (diagram A2)
Start up of the horizontal oscillator via the +8V gives a startup current into pln 37, if the voltage on pin 37 exceeds 5V6 the horizontal oscillator starts running at approx. 25kHz. Only when the supply pin of IC 7225 (pin 12 at IC 7225-5A in diagram A3) becomes 8V the line frequency changes to 15625 Hz.
Horizontal synchronisation separator separates horizontal pulses out of CVBS and so synchronises the free-running horizontal sawtooth generator.
Horizonial oscillator sawtooth is converted into square wave voltage with variable duty cycle. This square wave on pin 40 is led to the line output stage. The time constant of the synchronisation circuit is automatically internally determined by IC 7225-50.
Pin 41 is both SANDCASTLE output and HORIZONTAL FLYBACK input.
In principal the line output stage Pin 40 IC 7225-5D drives the line output stage, TS 7445 and transformer 5445 via drivers TS 7440-7441. The line output stage supplies the deflection current and the following supply vollages (see also the power supply block diagram in chapter 5): Output voltage (Diagram A2)
LOT (5445 Line output transformer) output voltage
PCS 91 584 GB
Chassis L7.2A 29
9.6.4.2 Vertical synchronisation IC 7225-5D and the frame amplifier IC 7401
The vertical oscillator (50Hz) is controlled by the incoming video signal.
The vertical output is driven in anti-phase via the pin 46 and 47. On pin 41 the so called "Sandcastle" puls is present. The sandcastle puls is applied to several parts of the circuits for timing purposes.
In principal the frame output stage IC 7401 (TDA9302) is used for the vertical deflection. This IC is controlled on pins 1 and 3 by the vertical control signal of IC 7225-50 and a deflection current is generated on pin 5. The vertical flyback signal is generated on pin 3 of the IC.
Single FM-mono sound for demodulation takes place in IC7225-5E. No adjustment required as automatic PLL tuning (4.2 to 6.8 Mhz).
Following description explains the functionally of the pC pins anti-clockwise for the outer pinning numbers.
Supply voltage (pin 52) : If this voltage is present and the Power On Reset signal at pin 43 is "low" the µC will start.
Flg. 9.1
(R-Y) OUT R-Y output from chroma demodulator Microcomputer AQUA Aquadag layer on the outside of the picture tube AV MUTE Signal to mute the sound on the Audio-out cinch AVL_AV2/AVL Switching signal from UP to the Auto Volume leveller on the ITT on BTSC Panel or Rear Cinch I/P 2 width CVRS R&L Sound Blue TXT or OSD signal from µC to the video contoller IC7225-5C BASS Beam Current information BG/1_or_BG/0 K Monochrome TV system sound carrier + 5.5Mhz (BG), Sound carrier + 6MHz (I), Sound carrier + 6.5MHz (DK) BI TXT OSD Fast blanking signal to IC7725-5C to display OSD and TXT BLACKSTR SW Black stretch switch BS1 TV band selection 2 signal CHROMA O/NTSC SW Switch on signal for NTSC chroma oscillator (3.575MHz) CHROMA 1/BG/L Switch on signal for BG/L chroma oscillator (3.582MHz) CHROMA_1/STATUS Switch on signal for NTSC chroma oscillator (3.579MHz) CHROMA 2/STATUS Signal to select the correct system in case of trinorma CVBS EXT1 CVBS external 1 input signal CVBS EXT2 CVBS external 2 signal CVBS_IN CVBS internal 1(from tuner) CVBS OUT CVBS output signal CVBS_OUT 1 CVBS output signal 1 CVBS SOUND CVBS for inter carrier sound detector CVBS TXT CVBS for TXT processing in µC DISCHARGE To has a fast drop during after switch off the set FAR Farth Electrical Erasable Programmable Read Only Memory Electrical Static Discharge Filament (heater voltage) from LOT to the picture tube FL Filament voltage for CRT G TXT OSD Green TXT or OSD signal from the µC to IC7225-5C GND Ground GRD LOT HOR.FLYBACK Horizontal flyback pulse used for looking the horizontal oscillator Digital Control bus of the microcomputer Intermediate frequency signal for sound processing Switching signal for Internal or external audio + video switching L EXT1 Audio left external 1 LEFT_OUT Audio right out SCART I/P 1 in left MOD L 1N2 SCART I/P 2 in left MOD_R_1N1 SCART I/P 1 in right SCART I/P 2 in right MONO/STROBE/BG_L Strobe signal for HEF 4094 on multi-mono sound panel MONO_OUT Audio mono out NTSC colour system PAL/SECAM PAL or SECAM colour system Blue TXT or OSD signal from the µC to the video controller IC7225 5C RAM Random Access Memory RESET1 RF_AGC Automatic gain control signal I for tuner RIGHT_OUT Audio right out Read Only Memory Service Alignment Mode; Service mode for doing alignments SANDCASTLE Sand castle signal from IC7225-5D to delay line IC7255 and SECAM chrominance decoder IC7241. SCL Clock line of the 12C-bus Data line of the 12C-bus SDM Service Default Mode; predefined mode for faultfinding SECAM_REF SECAM reference SID/STA/LL Sound identification / stereo available / france system "L" SIF Sound IF signal for FM demodulator STANDBY Switching signal from µC "low" for standby (power supply will be switched to stand-by mode), "high" for normal operation TREBLE Treble control signal Tuning voltage for tuner V_TUNE VFB Vertical flyback pulse VFL 50Hz vertical flyback pulse used to inform the µC that flyback takes place. This is important for OSD and TXT Voltage on grid 2 of the picture tube VOLUME -Control signal (from µC, but on DC level via RC nework) for volume control of sound processing in sound
A ....
Chassis L7.2A 4