PHILIPS
P
26 0.
9. Circuit description new circuits
Power supply (diagram A1)
9.1 Introduction
9.1.1 General
The switched mode power supply (SMPS is mains isolated The control IC7520 (MC44603AP) gives the pulses for driving FET 7518 with duty cycle control at fixed frequency of nominal 70 kHz in normal operation (in stand-by, slowslat and overload situation the SMPS runs at other fresuppose theory 20 kHz) 107520 is lectured with a slow-start circuitor and has over- and undervoltage-projection of the secondary supply voltages. Unload and overload (short-circuit) protection is also included. In case the load decreases upder a cortain threshold level the SMPS will switch into stand-by-mode (in stand-by SMPS is in the so called "reduced frequency mode": nominal 20 (Hz) The +95V (+VBATT) output gives a stabilised +95V for 14" 20" and 21" in normal operation and approx 102V DC In stand by mode 107541 (TDA9139) having stable regulator o/n +5V and +8V supply and also build in protection circuit for +5V and +8V supply and also build in protection circuit The IC disable the supply, when pill 4 is low (standoy mode) (TDA8373/74) line output is shut "down"). When nin 6 of IC754 Lis low the protection circuit is working +5V & +8V will shut "down" Transistor 7420 & 7421 is a fast discharge arouit (when power switches of
9.1.2 Oulput voltage (Diagram A1)
- Power supply Secondary output voltages
- +10V / 14V for the audio amplifier.
- +5V for the control part(is also available in standby)
- +8V for the video processing
- +6V for the video processing +14V for the horizontal synchronisation drive
- +14V for the horizontal synchronisation only +95V (+VBATT) for the line output stage and the tuning system
9.1.3 Duty cycle and T-on, T-olf, T-dead
The duty cycle of the power supply depends on T-on of FET TS7518 that is controlled by pin 3 of 1C7520. The 1C detects the variations of the +VBATT (the secondary side of T5545) via sensing-winding 1-2 at the primary side of T5545. The switching period of FET 7518 is divided in three man areas: T-on T-off and T-dead (see Fig. 9.2)
- main areas; 1-on, 1-on and 1-dead (see Fig. 9.2). During 1-on FET 7518 conducts and so the energy which is extracted from the mains, is stored into the primary winding 4-7 of transformer T5545 with a linear increasing primary current (slope depends on the voltage across C2508). Via T-on regulation by pin 3 IC7520 the duty cycle of the SMPS and so the +VBATT is controlled.
- During T-offFET 7518 does not conduct and so all energy "inside" the transformer is supplied to the load via secondary windings of T5545 and the secondary diodes (D6550, D6560 and D6570) The current through the secondary side of the transformer decreases with a linear slope of T5545).
- During T-dead FET 7518 does not conduct and so no energy is extracted or supplied (Isec is zero).
9.2 Primary side
9.2.1 Mains input and denaussing
Mains voltage is filtered by L5500, L5501 and L5502 full wave rectified by a diode bridge and smoothed by C2508 to the DC input voltage for the SMPS at pin 7 of T5545 (e.g. 300V DC (or 220V AC mains).
Degaussing.: R3504 is a dual PTC (2PTC's in one housing). After switching "on" the set, the PTC is cold so low-ohmic and so the degaussing current is very high After degaussing, the PTC is heated, so high-ohmic, so in normal operation the degaussing current is very low.
9.2.2 Start up and take over
Start-up: Via the start-up circuitry R3530 and R3529 one side of the 220V AC mains is used to start-up IC7520 via the supply pin (Vpin 1). As long as Vpin 1 has not reached 14V5, IC7520 does not start up and only sinks 0.3mA, As soon as Vpin 1 reaches the 14V5, IC7520 starts (FET 7518 into conduction) and pin 1 sinks a typical supply current of 17 mA. This supply current can not be delivered by the start-up circuit, so a take-over circuit has to be available. If no take-over take's place, the voltage on pin 1 will decrease and IC7520 switches off . In that case the restart will start again. Take over of IC7520; During start-up a voltage across winding 1 - 2 is built up. At the moment the voltage across winding 1 - 2 reaches approx. +12V, D6540 start conducting and takes over the supply voltage Vpin 1 of IC7520 (take over current is approx. 17mA)
9.3 Control circuitry
9 3.1 IC7520 control mechanisms
IC7520 controls the T-on of FET 7518 in all operation modes by 3 mechanisms :
- "Secondary-oulput-sensing" controls the secondary output voltages (via the teedback voltage Vpin 1.4)
- "I-prim current sensing" controls both the secondary output voltages and the maximum I-prim (via the current sense voltage Vnin 7).
- "Demagnetisation control" prevents the transformer T5545 from going into saturation via the so called "DEMAG" function at pin 8 (this causes slow-start operation).
- 9.3.2 Secondary output voltages (eedback (pin 14 of IC7520)
Winding 1 - 2 has the same polarity as the secondary windings that are supplying the load. During T-olf the secondary windings and so winding 1-2 are positive. D6537 conducts and so charges C2537; the DC level across C2537 is a reference for the secondary output voltages (e.g. the +95V) +VBATT. Via R3538, R3539 and potentiometer R3540 for adjusting the +95V (+VBATT) this DC-voltage is bought to the required level for the error amplifier in IC7520 at pin 14. This voltage Vpin 14 is called feedback voltage and is used to control the secondary output voltages.
9.3.3 I-prim sensing (pin 7 of IC7520)
The current sense voltage Vpin 7 is a measure for the I-prim through FET 7518 The I-prim is converted into a voltage by R3518 The current sense voltage Vpin 7 is used to control both the secondary output voltages and the maximum I-prim(see peak current limiting)
9.3.4 Demannetisation control (via nin 8.0(10.7520)
Winding 1 - 2 has the same polarity as the secondary windings that are supplying the load. As a result the voltage across this winding is negative during T-on, positive during T-off and oscillating during T-dead. The so called demagnetisation "DEMAG" in IC7520) function at pin 8 of IC7520 is used for blocking the output Vpin3 during the time that there is still energy in the transformer (Isec not zero). This is realised by delaying the T-on until the demagnetisation Is completely finished in this way the currents and voltages at the moment of switching "on" the FET are controlled.
sique 2.6.6
Circuit description new circuits
9.3.5 IC7520 control (see Fig. 9.4 and Fig. 9.3)
The error amplifier (block A in Fig. 9.4) compares the feedback voltage Vpin 14 with an internal reference voltage of 2V5 The output voltage Verror-out of this error amplifier is fed to another comparator (block B in Fig. 9.4). This comparator compares the Verror-out and the current sense voltage Vpin 7. As soon as the current sense voltage Vpin 7 becomes higher than the output -voltage of the error amplifier Verror-out, the comparator B gives a spike (the output of comparator B is the so called current sensing output-voltage Vcs out).
9.3.6 Flip flop
Flip flop (block C in Fig. 9.4) drives the output pin 3 (Vpin 3) via a buffer emplifier (block D). The flip flop is set by positive edge of the output of the oscillator (V osc) and reset by the spike Vcs out As a result the pulse Vpin 3 becomes "high" (T-on starts) by the positive edge of Vosc from the internal oscillator and "low" (T-on stops) by the spike of Vcs out (the T-on start will be delayed in case the transformer is not yet demagnetised; see the slow-start procedures).
9.3.7 Stable load and increasing / decreasing load (see Fig. 9.3)
In case of a stable load, the feedback voltage Vpin 14 (and so also the maximum current sense voltage Vpin 7) remains the same. As a result the T-on and so the duty cycle will remain the same.
In case of an increasing load, the secondary output voltage decreases. The voltage on pin 14 would like to decrease which causes Verror -out to increase. As a result comparator B will give the pulse later: Voin 3 will be "high" for a longer period (longer T-on so the duty cycle increase) and so the secondary output voltages will be increased (corrected). This will give a new balance of feedback voltage Vpin 14 and the internal 2V5 reference voltage, at a new larger duty cycle As a result of the longer T-on, the maximum I-prim increases, so more energy can be stored in the transformer. In this way more energy will be supplied to the load. In case of a decreasing load, the secondary output voltage increases. The voltage on pin 14 would like to increase which causes Verror-out to decrease. As a result comparator B will give the pulse earlier, Vpin 3 will be "high" for a shorter period (shorter T-on so the duty cycle decrease) and so the secondary output voltages will be decreased (corrected). This will give a new balance off feedback voltage Vpin 14 and the internal 2V5 reference voltage, at a new smaller duty cycle.
As a result of the shorter T-on, the maximum I-prim decreases, so less energy can be stored in the transformer. In this way less energy will be supplied to the load. In case the demgnetisation of the transformer is not finished, the positive edge from the oscillator, which will start a new cycle, will be overruled (via buffer block D) as being the starting point of T-on. As a result the T-on will be delayed and so the frequency of the SMPS will go down. This procedure Is used during start-up.
9.3.8 Peak current limiting
Peak current limiting is realised by an internal clamp at Vpin 7 at 1V DC. Via this clamp the Vpin7 can never exceed 1V DC and so the maximum value of I-prim (maximum current through FET 7518) is determined.
In case the load needs more than the maximum power, by then the I-prim is already at his maximum level so the SMPS will goin overload protection (see foldback principle explained at overload protection).
Chassis L7.2A 26
9.3.9 Cycle-by-cycle control
The T-on control is controlled on a cycle-by-cycle basis (because of the Ilip flop block C in IC7520). This means that in every cycle the T-on is determined again. By doing so the secondary voltages control, peak current limitation and all protections can be very accurate and fast
9.3.10 Slow-slart
As soon as Vpin 1 > 14V5 DC the SMPS will start-up. This will be done by a slow-start procedure (both the frequency and the duty cycle will be built up during slow-start). The following 3 phenomena's take place during start-up:
- The following operation and of the place damage and approximate of the place damage and the place damage approximate of the place damage approximately of the place damage dam
- The voltage at pin 5 determines the foldback point. As during start-up this Vpin 5 is gradually built-up, the foldback point will also gradually increase (see foldback principle explained at overload protection).
- The duty cycle will slowly increase beginning at the absolute lowest duty cycle possible. The maximum duty cycle is determined by C2530 at pin 11 IC7520, as C2530 is unchanged at start-up, the power starts up at the lowest possible duty cycle.
- 9.3.11 Standby mode
In standby mode the load decreases (see description of standby on the secondary side) under a certain threshold level. The SMPS will determine this threshold level and so switch to the so called "reduced frequency mode" at 20 kHz. This minimal load threshold level is determined by R3532 at pin 12.
9.4.5
- 70 kHz. In normal operation mode the internal oscillator gives 70 kHz. This frequency is controlled by C2531 at pin 10 IC7520 and by R3537 pin 16 IC7520
- 20 kHz. In standby mode the internal oscillator gives 20 kHz. This frequency is controlled by R3536 at pin 15 IC7520.
9 3.12 FET 7518 gale regulation
D6524 prevents pin 3 of IC7520 from becoming negative (this will destroy the IC) due to stray inductance in the gate part. The safety resistor R3525 limits the drive current to the gate of FET 7518.
9.3.13 Typical values
In a stable situation Vpin 14 is typical 2V5. Mains Voltage: 110V, 90 - 276V 220 · 240V, 150 - 276V Mains frequency: 50 Hz / 60 Hz Power Consumption: in normal mode 43W +/· 10% 20": 52W +/- 10% 21": 57W +/- 10% < 10W in sland-by mode < 3W option
9.4 Protections
.......................................
signe 260
9.4.1 Over voltage protection of the secondary voltages
After start-up is the supply voltage Vpin 1 taken over by positive winding 1 - 2, and so after start up Vpin 1 is a
measuring point for the secondary output voltages. After startup (via an internal switch) this Vpin 1 is internally tapped (voltage divided) to a voltage which can be measured at pin 6 (so Vpin 6 is also a measuring point for the secondary output voltages). As soon as the voltage Vpin 6 > 2V5 the logic in IC 7520 will shut down the output at pin 3. This 2V5 threshold at Vpin 6 is equivalent to a Vpin1 of 16V DC which is equivalent to a voltage at the supply voltage +VBATT of approx. 95V DC (normal operation) and 102V DC (standby). After switching "off" because of over voltage protection, the IC starts up again (see slow-start).
- In case an over voltage situation is sensed at the secondary output voltages, the SMPS will go in over voltage protection. In case the over voltage situation remains present, the SMPS will give over voltage protection slow-start, over voltage protection slow-start, etc. → a very good audible hick-up mode.
- 9.4.2 Under voltage protection of the secondary voltages
If the supply vollage Vpin 1 9V DC the output pulse at pin 3 will be shut down. As soon as Vpin 1 7V5, the IC7520 will be totally shut "off" Vpin 1 of 9V DC is equivalent to a voltage at +VBATT of approx. 70V DC (normal operation) and 95V DC (standby). Vpin 1 of 7V5 is equivalent to a voltage at +VBATT of approx. 55V DC (normal operation) and 65V DC (standby).
In case an over voltage situation is sensed at the secondary output voltages, the SMPS will first switch "off" the pulse and then switch "off" the complete IC 7520. In case the IC 7520 is switched "off", the SMPS will switch "off". In case the under voltage situation remains present, the SMPS will give under voltage protection, slow-start, undervoltage protection, slow-start, etc. → a very good audible hick-up mode.
9.4.3 Unload protection
In case the load goes down (e.g. the line goes down because of standby mode or some failure in the line) this is detected by IC7520 via I-prim and secondary output vollages sensing. In case the load decreases below a certain threshold the SMPS will switch in "reduced frequency mode" of 20 kHz (this threshold is determined by the voltage level at pin 12 IC7520);
In case of an unload situation the set will switch to "low (requency mode" or standby mode. Whether this unload situation of the SMPS is caused by the standby command or by a failure (e.g. in the line), can only be determined by switching on the set again which the remote control, in case of standby mode the TV will switch "on" again, in case of unload situation the set will not switch "on".
9.4.4 Overload (short-circuit) protection (see Fig. 9.1)
If the secondary load becomes too high, I-prim becomes too high which is sensed by the current sense voltage Vpin 7. This voltage Vpin 7 is not allowed to exceed 1V DC by IC 7520 and so gives current limiting
As the I-prim is limited, the secondary output voltages will also drop and so supply voltage Vpin 1 will drop. As soon as Vpin 1 < 9V DC the driving pulse at pin 3 will stop. As a result of these 2 mechanism in case of an overload the
secondary voltages will drop very fast. This is called the foldback mechanism, the foldback point can be adjusted by pin 5 IC7520 (for the L7.2 this point is adjusted to a maximum tolerable output power of 85W at 90V AC and 165W at 276VAC. After this foldback, the IC starts up again (see slow-start). In case the overload situation remains present, the SMPS will give foldback again, slow-start, foldback, slow-start, etc;
As a result in case of short-circuit (or overload) the TV will be in a very good audible hick-up mode.
9.5 Secondary side
9.5.1 Oulput vollages
- +VBATT (95V) for the output stage and the tuning system is made via the positive winding 14 - 16, rectilier diode D6550 and smoothing capacitor C2551.
- +10V / 14V for the audio ampliller is made via the positive winding 10 - 12, rectifier diode D6570 and smoothing capacitor C2571.
- +14V for the horizontal synchronisation drive is made via the positive winding 13 - 15, rectifier diode D6560 and smoothing capacitor C2651.
- +5V for the control circuit (this voltage is also available in standby). The output from pin 9 of IC7541 via the smoothing capacitor C2563. The input +14V come from the same rectifier diode D6560 and smoothing capacitor C2651.
- +8V for the video processing. The output from pin 8 of IC7541, via the smoothing capacitor C2562 And the Input +14V come from the same rectifier diode D6560 and smoothing capacitor C2651. The +8V output is depending of IC 7541 Pin 7 program network 3552 and 3554.
9.5.2 DC Output Voltages Protections
There is a protections available at the secondary & LOT side.
- +5V protection: when any overload at +5V supply the IC7541 Pin 1 6.5V the IC7541 protection circuit will turn on and shut down the output +5V supply, and also shut down the +8V supply.
- +8V protection: when any overload at +8V supply the IC7541 Pin 1 6.5V the IC7541 protection circuit will turn on and shut down the output +8V supply. IC 7541 Pin 7 are depending 3552 and 3554 so called program network of +8V supply. If the voltage 2.4V the +8V will shut down.
- +13V protection: when any overload at +13V supply (5445 LOT +13V) output will shut down by the IC7600 via pin 16 also for the vertical frame protection.
9.5.3 Fast discharge circuit
T$7420 and T$7421 forms a fast discharge circuit. When the voltage on the collector of T$7421 is 6V the circuit will switch off the horizontal drive immediately via pin 50 of IC 7225-5D.
9.6 Single chlp TV-processor IC7225 (TDA8373/74)
Introduction:
In this chip most of the video, audio and sync circuits are integrated. In the diagrams the IC is split up in next 5 parts (5A,5B,5C,5D and 5E).
- IC7225-5A, video delector (see diagram A3)
- IC7225-5B, source select en PAL demodulator (see diagram A3).
- IC7225-5C, video control (see diagram A3).
- IC7225-5D, horizontal and vertical sync (see diagram A2) IC7225-5E, mono sound demodulator (see diagram A5).
- IC/225-5E, mono souno demodulator (see diagram A5).
- 9.6.1 IC7225-5A, IF video delector (see diagram A3)
Tuning system
signe 27 A
The luner 1000 can be a VST or a PLL type. In both cases the luner is controlled by the µC:
- The VST tuner is controlled via V_TUNE, AFC and the BS1 and BS2 band switching signals.
- The PLL tuner is fully PC controlled. IC 7225-5A contains the IF amplifier and the IF detector. The IF signal is present at the output pin 11 of the tuner.
- BS1 and BS2 (pin 17-18): Switching signals used for band switching of a VST luner.
Circuit description new circuits
| ٠ | ||||
|---|---|---|---|---|
Chassis L7.2A 27
| BS1 | BS2 | |
|---|---|---|
| VHF1 | 0 | 1 |
| VHF2 | 1 | 0 |
| UHF | 1 | 1 |
IF bands pass filter
The IF bands pass characteristic is determined by the band pass of the SAW filter 1015.
- For PAL BG sets a SAW filter with 5 5 MHz bandwidth is used (33.4 to 38.9 MHz).
- For PAL 1 sets a SAW (ilter with a bandwidth of 6.0 MHz is used (32.9 to 38.9 MHz).
- For PAL BG/SECAM BG/LL' sets a SAW litter with 6.5 MHz band switch is used to enable BG/I/LL' reception (33.9 to 40.4 MHz).
- For PAL BG/SECAM BG/DK sets a SAW filter with a bandwidth of 6 5 MHz is used (32.4 to 38.9 MHz).
IF-demodulator
IF-demodulation is done with reference circuit L5260 at pin 3 and 4 of IC7225-5A AGC control of luner is via pin 54 IC7225-5A to tuner. Top sync level is used for AGC inside IC7225-5A. AGC adjustment is done by 12C control via entry into the SAM service menu. C2202 at pin 53 determines time constant of the AGC. Base band CVBS signal at pin 6 IC7225-5A (normal - 3V2) is fed to the sound trap filters (1206, 1207, 1208, 1209 and 5206) and return to pin 13 IC7225-5B for source selection and video processing (diagram A3). The NTSC_SW signal from the control microprocessor turns on transistors 7216 and 7217 to activate filter 1209 when an NTSC signal is received.
Demodulation for sound IF takes place for the various signals as follows:
For single mono signal, the CVBS_Sound signal goes to filter 1104 for 4.5 MHz and filter 1102 for 5.5 MHz (diagram A5 for Sound_IF detector. The Sound_IF goes to pin 11C7225-5E for demodulation
9.6.2 PAL/NTSC Processing (IC7225-58 diagram A3)
IC7225-5B contians of source select, PAL/NTSC colour decoder.
The main functions are
- Source selection
- Colour Decoder
Source Selection
The input selector hsa CVBS_INTCVBS_EXT1. Y_CVBSEXT2, C_EXT2 as inputs which can be selected via the 13C but
Colour Decoder
The main functions are :
PLŁ/VCO
The PLL operates during the burst key period. It synchronises the VCXO oscillator with the frequency and phase of the incoming chroma burst. For alternating burst (PAL standards), a loop filter enables the PLL to synchronise with the average burst (180° phase).
PAL/NTSC lidentification
The 0° and 90° Reference signals from the VCO oscillator are supplied via the HUE phase circuit to the (B-Y)
The demodulated burst from the (B-Y) burst demodulator is supplied both to ACC detector and NTSC ident circuit The NSTC ident circuit is an integrator. Once the Integrator output exceeds the NTSC killer level then an NTSC burst has been identified (ION-t). Therefore the IDN informa-
tion provided the ASM (Automatic System Manager) with NTSC colour ident information.
The demodulated burst from the burst from the (R-Y) burst demodulator is supplied to the PAL ident circuit via a AL switch. The PAL ident circuit is also an integrator Once the integrator output exceed the PAL killer level then a PAL burst has been indentified (IDP=1). The IDP information provides the ASM with PAL-colour ident information. Second Interface
- The SECAM interface The SECAM interface allows bi-directional communication between IC7241 (TDA8395) and the ASM for SECAM identification. When the VCO oscillator is oscillating at 4.43 Mhz, the reference frequency of 4.43MHz is superimposed on a DC level and is supplied from pin 33 of IC7225 to pin 1 of IC7241. If PAL/NTSC signals are identified, the reference frequency is continously available at pin 33 and superimposed on a 1.5V DC level. When SECAM is identified by IC7241, the reference signals which is generated in packets form and superimposed on a 5V DC level is supplied to pin 33 of IC7225. Its ident signal (IDSM=1) is supplied to the ASM.
- ASM (Automatic System Manager) The ASM can decode PAL/NTSC colour standards and in combination with IC7241 (TDA8395), multistandard applications can be realised. The different possibilities are controlled by the 1°C bus input commands which are communicated to the ASM via the 1°C bus. The 1°C bus input commands also indicate which crystals must be connected to pins 34 and 35. This is essential for correct calibration of the behavioral oscillator.
- (R-Y)/(B-Y) demodulation For PAL/NTSC standards, the (B-Y)/(R-Y) baseband signals are extracted from the chroma signal by the (B-Y)/(R-Y) demodulators, filtered and supplied via the output switch to pins 29 and 30 respectively. When SECAM is identified by the SECAM decoder IC7241 and no PAL/NTSC is already identified by the ASM, then the ASM sets the (B-Y)/(R-Y) switch open. This implies (B-Y)/(R-Y) signals from the SECAM decoder can be directly connected to pin 29 and 30 respectively without extra loading.
- 9.6.3 Video controller (IC7225-5C, diagram A3)
The main functions are
- Y/(B-Y)/(R-Y) sional processing/matrixing
- RGB signal selection/processing/output stages
- Black stretcher
- Beam current limiter (BCL PW/L)
- Automatic black current stabilisation (ABS)
Y/(B-Y)/(B-Y) signal processing/malgxing
The luminance at pin 27 is internally AC coupled to the luminance clamp, which is operational during burst key period. The luminance signal is supplied to the RGB matrix circuit via the black stretcher. The (B-Y)/(R-Y) signals supplied to pins 31 and 32 respectively are clamped during the burst key period. The signals are then supplied to the colour difference maxtrix to select the desired matrix from either PAL, NTSC or Japanese NTSC matrix. The selected matrix is controlled via the 12C bus. For RGB matrixing the signal outputs from the colour difference matrix are added with the luminance signal
signe 28 A
Chassis L7.2A
Circuit description new circuits
RGB signal selection/processing/output stages
Within the RGB signal selection there are three modes to choose from.
- RGB (internal)
- Fast RGB insertion (R_TXT G_TXT B_TXT on pins 23, 24 and 25 respectively)
- OSD-mode
Teletext
Two different microprocessors are used: one with and one without teletext.
In case of TXT, this teletext function is integrated together with the control part in one and the same µC. This µC is drawn in the diagrams with the outer pin numbering.
In case of no TXT another µC is used with fewer pins This µC is used is drawn in the diagrams with the internal pin numbering.
In the description below, the pin numbers mentioned are the numbers mentioned outside the housing of IC 7600 (IC7600 with TXT and IC7601 without TXT), so for the µC with integrated TXT functionally. In case of the µC with integrated leftext function, the CVBS-TXT signal is fed to pin 23 the TXT and OSD- information are combined at pins' 32-33-34.
Before the RGB signal selection the RGB signals are clamped to similar DC level during burst key period.
Selection is controlled by the RGB insertion input voltage at pin 26.
| Vollage at pin 26 | selected RGB signals |
|---|---|
| < 3V | RGB (internal) |
| 0.9V < V < 3V |
(R_TXT G_TXT 8_TXT
(last insertion on pin 23, 24 and 25) |
| > 4V |
OSD can be inserted at the
RGBout pins |
The contrast, brightness and white-point RGB adjustment on the selected RGB signals are controlled by 1°C bus commands. After the adjustment, the three RGB black levels are added to the RGB signals. These three signals are blanked when the RGB blank signal is active. The RGB blanking level tracks with the DC measurement pulse level. The RGB output stages supply the buffered RGB signals the pin 21, 20 and 19 respectively.
Black Stretcher
The black stretcher circuit, which is only operational during line scan, extends the grey signal level towards the actual black level (that is actual black level measured during burstkey). The amount of extension is dependent upon the difference between actual black level and the darkest part of the incoming video signal. The darkest part of the video signal is registered in the capacitor at pin 39 by means of an internal discharge current approximately 130uA. The black stretcher is made inactive if the voltage at pin 39 is set to ground. This is done by turning on transistor 7220 video the command blackstraw from the microprocessor (when powerchip button on the remote control unit is activated).
Beam Current Limiter
The beam current limiter circuit functions as an average while limiter as well as peak white limiter. The average
while limiter needs external circuitry comprising of 7265, and associated components to function. The peak white limiter is an internal detection circuit. The function of the beam current limiter (average white/peak white limiter) reduces the contrast and briobtness of BGB signals.
For beam current limiting, the difference in beam current (1BCL) and an internal charge current (1CHARGE) is stored in capacitor 2460 at pin 22. If 1BCL > 1CHARGE the voltage (VBCL) at pin 22 decreases. For beam current limiter:
contrast reduction begins when VBCL 3.5V
brightness reduction begins when VBCL 2.5V VBCL is normally 4V when beam current limiter is not active. The contrast and/or brightness reduction of the RGBout is proportional to the voltage decrease at pin 22.
9.6.4 Horizontal synchronisation IC 7225-5D and the line output stage (diagram A2)
Start up of the horizontal oscillator via the +8V gives a startup current into pln 37, if the voltage on pin 37 exceeds 5V6 the horizontal oscillator starts running at approx. 25kHz. Only when the supply pin of IC 7225 (pin 12 at IC 7225-5A in diagram A3) becomes 8V the line frequency changes to 15625 Hz.
Horizontal synchronisation separator separates horizontal pulses out of CVBS and so synchronises the free-running horizontal sawtooth generator.
Horizonial oscillator sawtooth is converted into square wave voltage with variable duty cycle. This square wave on pin 40 is led to the line output stage. The time constant of the synchronisation circuit is automatically internally determined by IC 7225-50.
Pin 41 is both SANDCASTLE output and HORIZONTAL FLYBACK input.
- The SANDCASTLE has an output current a few mA, the amplitudes of sandcastle pulse, burst 5V3, line blanking 3V, frame blanking 2V.
- When the input acts as a HORIZONTAL FLYBACK pulse, the input has a current of 100-300 mA. This horizontal flyback pulse compares phase of flyblack pulse with phase of the horizontal oscillator, if the phase is not correct the duty cycle of horizontal oscillator will be adjusted.
- Flash protection: The BCI into is applied to pin 42 of IC7225-5D. If due to a flash in the picture tube the voltage on pin 42 is 6V, the horizontal drive is switched off inmediately. If the voltage is again V the horizontal drive is switched on agaIn via the slow start procedure
- EHT over voltage protection. The BCI into is also applied to pin 50-IC7225-5D. First the BCI is compensated vertical picture amplitude variations due to beam current variations. The control range is between 1.2V and 2.8V. However if the voltage on pin 50 exceeds 3.9V the EHT overvoltage protection is activated and the horizontal drive is switched off.
9.6.4.1 The line output circuitry
In principal the line output stage Pin 40 IC 7225-5D drives the line output stage, TS 7445 and transformer 5445 via drivers TS 7440-7441. The line output stage supplies the deflection current and the following supply vollages (see also the power supply block diagram in chapter 5): Output voltage (Diagram A2)
LOT (5445 Line output transformer) output voltage
- EHT, +160, Vg2, focus and if for the picture tube.
- 160V for the CRT drive cct.
- +5.5V for the control cct & tuner supply.
- +9V for the tuner supply.
-
+13V for the control & vertical drive output cct.
- -13V for the vertical drive output cct.
PCS 91 584 GB
Circuit description new circuits
Chassis L7.2A 29
9.6.4.2 Vertical synchronisation IC 7225-5D and the frame amplifier IC 7401
The vertical oscillator (50Hz) is controlled by the incoming video signal.
The vertical output is driven in anti-phase via the pin 46 and 47. On pin 41 the so called "Sandcastle" puls is present. The sandcastle puls is applied to several parts of the circuits for timing purposes.
9.6.4.3 Frame amplilier
In principal the frame output stage IC 7401 (TDA9302) is used for the vertical deflection. This IC is controlled on pins 1 and 3 by the vertical control signal of IC 7225-50 and a deflection current is generated on pin 5. The vertical flyback signal is generated on pin 3 of the IC.
- Protection: IC 7401 depending +13V and -13V supply to drive the vertical deflection cct. In case of supply voltage +13V or -13V drawing high current, by then the VFL pin 3 of IC 7401 voltage drop < 6.5V. As a result the VFL will feedback to pin 37 of 7600 micro processor will shut down the supply and at standby mode.
- 9.6.5 Sound delector (IC7225-5E, diagram A5)
Single FM-mono sound for demodulation takes place in IC7225-5E. No adjustment required as automatic PLL tuning (4.2 to 6.8 Mhz).
9.6.6 Control (Diagram A4)
Following description explains the functionally of the pC pins anti-clockwise for the outer pinning numbers.
-
Control-voltage outputs (pin 1.2, pin 4.7 and pin 9-11). These pins are PWM (Pulse Width Modulated) output pins used for volume, bass, treble and tuning control (only for VST).
- → The V-TUNE varies between 0-30V and is derived from the +95V supply from the power supply.
- → Bass and treble functionality is only used in case of sets with the "smart sound" feature.
- INT/EXT (pin 8): Output switching signal "high" for internal CVBS-mode and "low" for external mode (AV-mode so cinch mode).
- Functional switch (pin 15): For U$A sets do not have a main's switch but a (unctional switch. If pin 15 is connected to ground by means of 1064, the set is switched to stand-by
- Protection (pin 16): This pin is an input pin for protections. If this pin is connected to ground, the set is switched in protection. By this protection the voltages +13V is monitored to check if they become too high. If the +13V drops this is monitored by the circuit around 7608. The emitter becomes "tow" (0V7 lower than the base voltage) if the +13V drops. This will force pin 16 of the µC "low" and will switches the set in protection.
- STANDBY (pin 19): Output pin "high" for normal operation and "low" for standby.
-
LED-drive (pin 20): Signal to drive the LEC
- In standby, the LED lights continuously by pulling pin 20 "low"
- → In normal operation the LED does not light by not pulling pin 20 "low"
- → During RC5 reception pin 20 is pulled "low" lime by lime, resulling in a pulsing LED
- Ground (pin 21)' Ground of the power-supply.
- Test pin (pin 22): Used for test purposes in the SAM service mode.
- CVBS-inputs (pin 23): These pins are used as input for teletext-sources.
- TXT/OSD-signals (pin 32-33-34): These output pins are used to create TXT and OSD information in different colours.
- BL-TXT-OSD (pin 35): Output signal (BL_TXT_OSD) used to indicate the video controller that there is OSD) used Teletext information. So this signal blanks the video information
- FLYBACK (pin 36). Pin inform the µC that horizontal llyback takes place. This information is needed to place the TXT and OSD correctly on the picture.
- VFL (pin 37): This pin is used to tell the µC that vertical flyback takes place. This information is needed to place the TXT and OSD correctly on the picture.
-
OSD-generator (pin 38-39-40): The components connected these pins determine the frequency of the OSD-generator. This is approx. 8 MHz.
- → In a non TXT set, the OSD generator is formed by C2680, C2684
- 12 MHz oscillator (pin 41-42): The frequency of the oscillator of the µC is determined by this crystal 1681.
- RESET (pin 43): At switching on the set with the mains switch the signal at pin 43 becomes "high" and holds the μC. The μC wait until the signal at pin 43 becomes "low". In this way the μC knows that the supply voltage is high enough to be to perform well.
- TXT /no TXT (pin 44): In case jumper 4603 is present, the software "knows" as a no TXT set. In case jumper 4602 is not present, the software "knows" as a TXT set.
-
IR-input (pin 45). Input for the remote-control commands
→ Video system selections (pin 46 and 51): These two
- outputs can be used in different ways depending on the region where the set is produced.
- I2C-Bus (pin 49-50): This bus is used to communicate with all used I2C devices.
- → Non Volatile Memory (EEPROM) in which the settings are stored. In case pin 1 of this NVM is shorted while switching on the set with the mains switch, the SDM (Service Default Alignment Mode), see chapter 6.
- → In case of PLL luner, the I2C-Bus is used via the copper tracks of BS1 and BS2 (these copper tracks are used for band switching in a VST set).
Supply voltage (pin 52) : If this voltage is present and the Power On Reset signal at pin 43 is "low" the µC will start.
Flg. 9.1
11. Abbreviations
(R-Y) OUT R-Y output from chroma demodulator Microcomputer AQUA Aquadag layer on the outside of the picture tube AV MUTE Signal to mute the sound on the Audio-out cinch AVL_AV2/AVL Switching signal from UP to the Auto Volume leveller on the ITT on BTSC Panel or Rear Cinch I/P 2 width CVRS R&L Sound Blue TXT or OSD signal from µC to the video contoller IC7225-5C BASS Beam Current information BG/1_or_BG/0 K Monochrome TV system sound carrier + 5.5Mhz (BG), Sound carrier + 6MHz (I), Sound carrier + 6.5MHz (DK) BI TXT OSD Fast blanking signal to IC7725-5C to display OSD and TXT BLACKSTR SW Black stretch switch BS1 TV band selection 2 signal CHROMA O/NTSC SW Switch on signal for NTSC chroma oscillator (3.575MHz) CHROMA 1/BG/L Switch on signal for BG/L chroma oscillator (3.582MHz) CHROMA_1/STATUS Switch on signal for NTSC chroma oscillator (3.579MHz) CHROMA 2/STATUS Signal to select the correct system in case of trinorma CVBS EXT1 CVBS external 1 input signal CVBS EXT2 CVBS external 2 signal CVBS_IN CVBS internal 1(from tuner) CVBS OUT CVBS output signal CVBS_OUT 1 CVBS output signal 1 CVBS SOUND CVBS for inter carrier sound detector CVBS TXT CVBS for TXT processing in µC DISCHARGE To has a fast drop during after switch off the set FAR Farth Electrical Erasable Programmable Read Only Memory Electrical Static Discharge Filament (heater voltage) from LOT to the picture tube FL Filament voltage for CRT G TXT OSD Green TXT or OSD signal from the µC to IC7225-5C GND Ground GRD LOT HOR.FLYBACK Horizontal flyback pulse used for looking the horizontal oscillator Digital Control bus of the microcomputer Intermediate frequency signal for sound processing Switching signal for Internal or external audio + video switching L EXT1 Audio left external 1 LEFT_OUT Audio right out SCART I/P 1 in left MOD L 1N2 SCART I/P 2 in left MOD_R_1N1 SCART I/P 1 in right SCART I/P 2 in right MONO/STROBE/BG_L Strobe signal for HEF 4094 on multi-mono sound panel MONO_OUT Audio mono out NTSC colour system PAL/SECAM PAL or SECAM colour system Blue TXT or OSD signal from the µC to the video controller IC7225 5C RAM Random Access Memory RESET1 RF_AGC Automatic gain control signal I for tuner RIGHT_OUT Audio right out Read Only Memory Service Alignment Mode; Service mode for doing alignments SANDCASTLE Sand castle signal from IC7225-5D to delay line IC7255 and SECAM chrominance decoder IC7241. SCL Clock line of the 12C-bus Data line of the 12C-bus SDM Service Default Mode; predefined mode for faultfinding SECAM_REF SECAM reference SID/STA/LL Sound identification / stereo available / france system "L" SIF Sound IF signal for FM demodulator STANDBY Switching signal from µC "low" for standby (power supply will be switched to stand-by mode), "high" for normal operation TREBLE Treble control signal Tuning voltage for tuner V_TUNE VFB Vertical flyback pulse VFL 50Hz vertical flyback pulse used to inform the µC that flyback takes place. This is important for OSD and TXT Voltage on grid 2 of the picture tube VOLUME -Control signal (from µC, but on DC level via RC nework) for volume control of sound processing in sound
A ....
5. Block diagram
Chassis L7.2A 4
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