PLL500-17
Low Phase Noise VCXO (17MHz to 36MHz)
FEATURES
• VCXO output for the 17MHz to 36MHz range
• Low phase noise (-130 dBc @ 10kHz offset at
35.328MHz).
• CMOS output with OE tri-state control.
• 17 to 36MHz fundamental crystal input.
• Integrated high linearity variable capacitors.
• 12mA drive capability at TTL output.
• +/- 150 ppm pull range, max 5% linearity.
• Low jitter (RMS): 2.5ps period jitter.
• 2.5 to 3.3V operation.
• Available in 8-Pin SOIC, 6-pin SOT23 packages,
or DIE.
DESCRIPTION
The PLL500-17 is a low cost, high performance and
low phase noise VCXO for the 17 to 36MHz range,
providing less than -130dBc at 10kHz offset at
35.328MHz. The very low jitter (2.5 ps RMS period
jitter) makes this chip ideal for applications requiring
voltage controlled frequency sources. Input crystal
can range from 17 to 36MHz (fundamental resonant
mode).
BLOCK DIAGRAM
PIN CONFIGURATION
XIN
VDD*
VIN
GND
^: Denotes internal Pull-up
*: Only one VDD pin needs to be connected
1
PLL500-17
2
3
45
PLL500-17
OUT
GND
CLK
1
2
3
XOUT
8
OE^
7
VDD*
6
CLK
XIN
6
VDD
5
4
VIN
FREQUENCY RANGE
8-pin SOIC
MULTIPLIER FREQUENCY
No PLL 17 – 36 MHz CMOS
OUTPUT
BUFFER
XIN
XOUT
XTAL
OSC
VARICAP
VCON
6-pin SOT
OE
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/29/05 Page 1
PLL500-17
Low Phase Noise VCXO (17MHz to 36MHz)
DIE PAD LAYOUT DIE SPECIFICATIONS
32 mil
(812,986)
8
1 XIN
2
VDD
39 mil
VCON
3
GND
4
DIE ID: PLL500-17: C500A0404-04A
(0,0)
Y
X
Note: ^ denotes internal pull up
XOUT
OE^
VDD
CLK
7
6
5
Name Value
Size 39 x 32 mil
Reverse side GND
Pad dimensions 80 micron x 80 micron
Thickness 10 mil
PIN ASSIGNMENT (8-pin SOIC package) AND PAD DESCRIPTION (8-pin SOIC package)
Name Pin#
Die Pad Position
Type Description
X (µm) Y (µm)
XIN 1 94.183 768.599 I Crystal input pin.
VDD 2 94.157 605.029 P VDD power supply pin. Only one VDD pin is necessary.
VCON 3 94.183 331.756 I Frequency control voltage input pin.
GND 4 94.193 140.379 P Ground pin.
CLK 5 715.472 203.866 O Output clock pin.
VDD 6 715.307 455.726 P VDD power supply pin. Only one VDD pin is necessary.
OE 7 715.472 626.716 I
Output Enable input pin. Disables the output when low. Internal
pull-up enables output by default if pin is not connected to low.
XOUT 8 476.906 888.881 I Crystal output pin. Ref Clock input.
* OE (Output Enable) pin is not available in SOT-26 package, the output will always be enabled by the build in pull-up resister.
PIN ASSIGNMNET AND DESCRIPTION (6-pin SOIC package)
Name Pin# Type Description
XOUT 1 I Crystal Output pin. Ref. Clock input.
GND 2 P Ground pin.
CLK 3 O Output clock pin.
VCON 4 I Frequency control voltage input pin.
VDD 5 P VDD power supply pin.
XIN 6 I Crystal input pin.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/29/05 Page 2
PLL500-17
Low Phase Noise VCXO (17MHz to 36MHz)
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS SYMBOL MIN. MAX. UNITS
Supply Voltage VDD 4.6 V
Input Voltage, dc VI -0.5 VDD+0.5 V
Output Voltage, dc VO -0.5 VDD+0.5 V
Storage Temperature TS -65 150
Ambient Operating Temperature* TA -40 85
Junction Temperature TJ 125
Lead Temperature (soldering, 10s) 260
ESD Protection, Human Body Model 2 kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. AC Electrical Specifications
°C
°C
°C
°C
PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS
Input Crystal Frequency
Output Clock Rise/Fall Time
Output Clock Duty Cycle
Short Circuit Current
3. Voltage Control Crystal Oscillator
PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS
VCXO Stabilization Time * T
VCXO Tuning Range
CLK output pullability
VCXO Tuning Characteristic
Pull range linearity
Power Supply Rejection PWSRR
VCON pin input impedance
VCON modulation BW
From power valid 10 ms
VCXOSTB
17 36 MHz
0.8V ~ 2.0V with 10 pF load 1.15
ns
0.3V ~ 3.0V with 15 pF load 3.7
Measured @ 1.4V 45 50 55 %
F
= 12 – 25MHz;
XIN
XTAL C
0/C1
< 250
±50
mA
300 ppm
0V ≤ VCON ≤ 3.3V
VCON=1.65V, ±1.65V ±150
ppm
100 ppm/V
5 %
Frequency change with
VDD varied +/- 10%
2000
0V ≤ VCON ≤ 3.3V, -3dB
-1 +1 ppm
kΩ
45 kHz
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
4. Jitter and Phase Noise Specifications
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/29/05 Page 3
PLL500-17
Low Phase Noise VCXO (17MHz to 36MHz)
PARAMETERS CONDITIONS MIN. TYP. MAX. UNITS
RMS Period Jitter
(1 sigma – 1000 samples)
With capacitive decoupling between
VDD and GND.
2.5 ps
Phase Noise relative to carrier 36MHz @100Hz offset -80 dBc/Hz
Phase Noise relative to carrier 36MHz @1kHz offset -110 dBc/Hz
Phase Noise relative to carrier 36MHz @10kHz offset -130 dBc/Hz
Phase Noise relative to carrier 36MHz @100kHz offset -138 dBc/Hz
Phase Noise relative to carrier 36MHz @1MHz offset -145 dBc/Hz
5. DC Specifications
PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS
Supply Current, Dynamic,
with Loaded Outputs
Operating Voltage V
Output Low Voltage at
CMOS level
Output High Voltage at
CMOS level
V
V
I
DD
DD
OLC
OHC
Output drive current For VOL<0.4V or VOH>2.4V 8 9.5 mA
Short Circuit Current
VCXO Control Voltage VCON 0 VDD V
F
= 36MHz
XIN
Output load of 15pF
5 6 mA
2.25 3.63 V
I
= +4mA 0.4 V
OL
I
= -4mA V
OH
– 0.4 V
DD
±50
mA
6. Crystal Specifications
PARAMETERS SYMBOL MIN. TYP. MAX. UNITS
Crystal Resonator Frequency F
Crystal Loading Rating (VCON = 1.65V) C
Maximum Sustainable Drive Level 200
Operating Drive Level 50
C0 5 pF
C0/C1 250 -
ESR RS 30
Note: The crystal must be such that it oscillates (parallel resonant) at nominal frequency when presented a C Load as specified above.
If the crystal requires more load to be at nominal frequency, the additional load must be added externally.
This however may reduce the pull range.
17 36 MHz
XIN
8.5 pF
L (xtal)
µW
µW
Ω
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/29/05 Page 4
PLL500-17
Low Phase Noise VCXO (17MHz to 36MHz)
PACKAGE INFORMATION
8 PIN ( dimensions in mm )
Narrow SOIC
Symbol Min. Max.
A 1.47 1.73
A1 0.10 0.25
B 0.33 0.51
C 0.19 0.25
D4.804.95
E 3.80 4.00
H 5.80 6.20
L 0.38 1.27
e
1.27 BSC
D
A
1
B
e
E
H
A
C
L
6-pin SOT (Dimensions in mm)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/29/05 Page 5
PLL500-17
Low Phase Noise VCXO (17MHz to 36MHz)
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PLL500-17 X X R
Part Number
Package
S=SOIC
T= SOT
D=Die
NONE= TUBE
R=TAPE and REEL
Temperature
C=Commercial
I= Industrial
Part / Order Number Marking Package Option
PLL500-17DC
PLL500-17SC P500-17 8-Pin SOIC (Tube)
PLL500-17SC-R P500-17 8-Pin SOIC (Tape and Reel)
PLL500-17SCL P500-17L 8-Pin SOIC (Tube)
PLL500-17SCL-R P500-17L 8-Pin SOIC (Tape and Reel)
PLL500-17TC P500-17 6-Pin SOT (Tube)
PLL500-17TC-R P500-17 6-Pin SOT (Tape and Reel)
PLL500-17TCL P500-17L 6-Pin SOT (Tube)
PLL500-17TCL-R P500-17L 6-Pin SOT (Tape and Reel)
P500-17DC Die (Waffle Pack)
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/21/05 Page 6
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