Pericom PI7C7100 User Manual

Page 1

PI7C7100 3-Port PCI Bridge

The Complete Interface Solution

2380 Bering Drive, San Jose, California 95131 Telephone: 1-877-PERICOM, (1-877-737-4266) Fax: (408) 435-1100, E-mail: nolimits@pericom.com Internet: http://www.pericom.com

Pericom Semiconductor Corporation

Rev 1.1

查询PI7C7100供应商捷多邦，专业PCB打样工厂，24小时加急出货

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PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

LIFE SUPPORT POLICY

Pericom Semiconductor Corporation’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of PSC.

1.Life support devices or systems are devices or systems which: a) are intended for surgical implant into the body or b) support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided

in the labeling, can be reasonably expected to result in a significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably

expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.Pericom Semiconductor Corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry embodied in a Pericom Semiconductor product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Pericom Semiconductor Corporation.

All other trademarks are of their respective companies.

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PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

1. Introduction/Product Features ...............................................................................................................................1

2. PI7C7100 Block Diagram ......................................................................................................................................3

3. Signal Definitions ................................................................................................................................................... 4

3.1 Signal Types ............................................................................................................................................................4

3.2 Signals ......................................................................................................................................................................4

3.2.1 Primary Bus Interface Signals ..................................................................................................................................4

3.2.2 Secondary Bus Interface Signals .............................................................................................................................6

3.2.3 Clock Signals............................................................................................................................................................8

3.2.4 Miscellaneous Signals .............................................................................................................................................8

3.2.5 JTAG Boundary Scan Signals..................................................................................................................................9

3.2.6 Power and Ground....................................................................................................................................................9

3. 3 PI7C7100 PBGA Pin Listing .....................................................................................................................................9

4. PCI Bus Operation ................................................................................................................................................ 13

4.1 Types of Transactions ........................................................................................................................................... 13

4.2 Single Address Phase ............................................................................................................................................ 14

4. 3 Device Select (DEVSEL#) Generation .................................................................................................................... 14

4.4 Data Phase ............................................................................................................................................................. 14

4.5 Write Transactions ................................................................................................................................................ 14

4.5.1 Posted Write Transactions .................................................................................................................................... 14

4.5.2 Memory Write and Invalidate Transactions.......................................................................................................... 15

4.5.3 Delayed Write Transactions .................................................................................................................................. 15

4.5.4 Write Transaction Address Boundaries ................................................................................................................ 16

4.5.5 Buffering Multiple Write Transactions.................................................................................................................. 16

4.5.6 Fast Back-to-Back Write Transactions .................................................................................................................. 16

4.6 Read Transactions ................................................................................................................................................. 17

4.6.1 Prefetchable Read Transactions ............................................................................................................................ 17

4.6.2 Non-prefetchable Read Transactions ....................................................................................................................17

4.6.3 Read Pre-fetch Address Boundaries...................................................................................................................... 17

4.6.4 Delayed Read Requests ......................................................................................................................................... 18

4.6.5 Delayed Read Completion with Target .................................................................................................................. 18

4.6.6 Delayed Read Completion on Initiator Bus ...........................................................................................................18

4.7 Configuration Transactions ................................................................................................................................... 19

4.7.1 Type 0 Access to PI7C7100 ................................................................................................................................... 1 9

4.7.2 Type 1 to Type 0 Conversion ................................................................................................................................20

4.7.3 Type 1 to Type 1 Forwarding ................................................................................................................................21

4.7.4 Special Cycles ........................................................................................................................................................ 2 2

4. 8 Transaction Termination ........................................................................................................................................ 2 2

4.8.1 Master Termination Initiated by PI7C7100 ............................................................................................................ 2 3

4.8.2 Master Abort Received by PI7C7100.....................................................................................................................23

4.8.3 Target Termination Received by PI7C7100 ............................................................................................................ 2 4

4.8.3.1 Delayed Write Target Termination Response ....................................................................................................... 24

4.8.3.2 Posted Write Target Termination Response ......................................................................................................... 24

4.8.3.3 Delayed Read Target Termination Response ........................................................................................................ 25

4.8.4 Target Termination Initiated by PI7C7100 ............................................................................................................. 2 6

4.8.4.1 Target Retry ........................................................................................................................................................... 2 6

4.8.4.2 Target Disconnect.................................................................................................................................................. 27

Table of Contents

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PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

4.8.4.3 Target Abort .......................................................................................................................................................... 27

4.9 Concurrent Mode Operation.................................................................................................................................. 27

5. Address Decoding.................................................................................................................................................. 2 8

5.1 Address Ranges..................................................................................................................................................... 28

5.2 I/O Address Decoding ........................................................................................................................................... 28

5.2.1 I/O Base and Limit Address Registers ................................................................................................................... 2 8

5.2.2 ISA Mode ............................................................................................................................................................... 2 9

5.3 Memory Address Decoding................................................................................................................................... 29

5.3.1 Memory-Mapped I/O Base and Limit Address Registers ......................................................................................30

5.3.2 Prefetchable Memory Base and Limit Address Registers ......................................................................................30

5. 4 VGA Support.......................................................................................................................................................... 31

5.4.1 VGA Mode ............................................................................................................................................................. 31

5.4.2 VGA Snoop Mode.................................................................................................................................................. 3 1

6. Transaction Ordering ........................................................................................................................................... 3 2

6.1 Transactions Governed by Ordering Rules ...........................................................................................................32

6. 2 General Ordering Guidelines .................................................................................................................................. 32

6. 3 Ordering Rules ....................................................................................................................................................... 3 3

6. 4 Data Synchronization............................................................................................................................................. 34

7. Error Handling ...................................................................................................................................................... 3 5

7.1 Address Parity Errors.............................................................................................................................................35

7. 2 Data Parity Errors ................................................................................................................................................... 35

7.2.1 Configuration Write Transactions to Configuration Space ...................................................................................35

7.2.2 Read Transactions ................................................................................................................................................. 36

7.2.3 Delayed Write Transactions .................................................................................................................................. 36

7.2.4 Posted Write Transactions .................................................................................................................................... 38

7. 3 Data Parity Error Reporting Summary .................................................................................................................... 3 9

7. 4 System Error (SERR#) Reporting ...........................................................................................................................4 5

8. Exclusive Access ................................................................................................................................................... 4 6

8. 1 Concurrent Locks................................................................................................................................................... 4 6

8. 2 Acquiring Exclusive Access across PI7C7100....................................................................................................... 4 6

8. 3 Ending Exclusive Access ....................................................................................................................................... 4 7

9. PCI Bus Arbitration .............................................................................................................................................. 4 8

9. 1 Primary PCI Bus Arbitration................................................................................................................................... 4 8

9.2 Secondary PCI Bus Arbitration .............................................................................................................................48

9.2.1 Secondary Bus Arbitration Using the Internal Arbiter..........................................................................................48

9.2.2 Secondary Bus Arbitration Using an External Arbiter........................................................................................... 4 9

9.2.3 Bus Parking ............................................................................................................................................................ 49

10. Clocks .................................................................................................................................................................... 5 0

10.1 Primary Clock Inputs ..............................................................................................................................................5 0

10.2 Secondary Clock Outputs ...................................................................................................................................... 50

11. Reset ...................................................................................................................................................................... 51

11.1 Primary Interface Reset .......................................................................................................................................... 51

11.2 Secondary Interface Reset ..................................................................................................................................... 51

11.3 Chip Reset .............................................................................................................................................................. 5 1

12. Supported Commands ............................................................................................................................................ 5 2

12.1 Primary Interface .................................................................................................................................................... 52

12.2 Secondary Interface ............................................................................................................................................... 54

13. Configuration Registers ....................................................................................................................................... 5 5

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PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

13.1 Config Register 1 .................................................................................................................................................... 5 5

13.2 Config Register 2 .................................................................................................................................................... 5 6

13.2.1 Config Register 1 or 2:Vendor ID Register (read only, bit 15-0; offset 00h) .......................................................... 5 7

13.2.2 Config Register 1: Device ID Register (read only, bit 31-16; offset 00h) ............................................................... 5 7

13.2.3 Config Register 2: Device ID Register (read only, bit 31-16; offset 00h) ............................................................... 5 7

13.2.4 Config Register 1: Command Register (bit 15-0; offset 04h) .................................................................................. 5 7

13.2.5 Config Register 2: Command Register (bit 15-0; offset 04h) .................................................................................. 5 8

13.2.6 Config Register 1 or 2: Status Register (for primary bus, bit 31-16; offset 04h)..................................................... 5 9

13.2.7 Config Register 1 or 2: Revision ID Register (read only, bit 7-0; offset 08h) ......................................................... 6 0

13.2.8 Config Register 1 or 2: Class Code Register (read only, bit 31-8; offset 08h) ........................................................60

13.2.9 Config Register 1 or 2: Cache Line Size Register (read/write, bit 7-0; offset 0Ch) .................................................60

13.2.10 Config Register 1: Primary Latency Timer Register (read/write, bit 15-8; offset 0Ch)............................................60

13.2.11 Config Register 2: Primary Latency Timer Register (read/write, bit 15-8; offset 0Ch)............................................60

13.2.12 Config Register 1: Header Type Register (read only, bit 23-16; offset 0Ch).......................................................... 6 0

13.2.13 Config Register 2: Header Type Register (read only, bit 23-16; offset 0Ch).......................................................... 6 0

13.2.14 Config Register 1: Primary Bus Number Register (read/write, bit 7-0; offset 18h) ................................................. 6 0

13.2.15 Config Register 2: Primary Bus Number Register (read/write, bit 7-0; offset 18h) ................................................. 6 0

13.2.16 Config Register 1 or 2: Secondary Bus Number Register (read/write, bit 15-8; offset 18h) ................................... 6 0

13.2.17 Config Register 1 or 2: Subordinate Bus Number Register (read/write, bit 23-16; offset 18h)............................... 60

13.2.18 Config Register 1 or 2: Secondary Latency Timer (read/write, bit 31-24; offset 18h) ............................................60

13.2.19 Config Register 1 or 2: I/O Base Register (read/write, bit 7-0; offset 1Ch) ............................................................ 6 0

13.2.20 Config Register 1 or 2: I/O Limit Register (read/write, bit 15-8; offset 1Ch)........................................................... 6 0

13.2.21 Config Register 1 or 2: Secondary Status Register (bit 31-16; offset 1Ch) ............................................................ 61

13.2.22 Config Register 1 or 2: Memory Base Register (read/write, bit 15-0; offset 20h)...................................................62

13.2.23 Config Register 1 or 2: Memory Limit Register (read/write, bit 31:16; offset 20h) ................................................. 6 2

13.2.24 Config Register 1 or 2: Prefetchable Memory Base Register (read/write, bit 15-0;offset 24h)............................... 62

13.2.25 Config Register 1 or 2: Prefetchable Memory Limit Register (read/write, bit 31-16; offset 24h) ............................ 6 2

13.2.26 Config Register 1 or 2: I/O Base Address Upper 16 Bits Register (read/write, bit 15-0; offset 30h)...................... 62

13.2.27 Config Register 1 or 2: I/O Limit Address Upper 16 Bits Register (read/write, bit 31-16; offset 30h) .................... 6 2

13.2.28 Config Register 1 or 2: Subsystem Vendor ID (read/write, bit 15-0; offset 34h) .................................................... 6 2

13.2.29 Config Register 1 or 2: Subsystem ID (read/write, bit 31-16; offset 34h)...............................................................62

13.2.30 Config Register 1 or 2: Interrupt Pin Register (read only, bit 15-8; offset 3Ch) .....................................................62

13.2.31 Config Register 1 or 2: Bridge Control Register (bit 31-16; offset 3Ch) .................................................................6 3

13.2.32 Config Register 1 or 2: Diagnostic/Chip Control Register (bit 15-0; offset 40h).................................................... 64

13.2.33 Config Register 1 or 2: Arbiter Control Register (bit 31-16; offset 40h)................................................................. 6 4

13.2.34 Config Register 1: Primary Prefetchable Memory Base Register (Read/Write, bit 15-0; offset 44h) ..................... 65

13.2.35 Config Register 2: Primary Prefetchable Memory Base Register (Read/Write, bit 15-0; offset 44h) ..................... 65

13.2.36 Config Register 1: Primary Prefetchable Memory Limit Register (Read/Write, bit 31-16; offset 44h).................... 6 5

13.2.37 Config Register 2: Primary Prefetchable Memory Limit Register (Read/Write, bit 31-16; offset 44h).................... 6 5

13.2.38 Config Register 1 or 2: P_SERR# Event Disable Register (bit 7-0; offset 64h) ...................................................... 65

13.2.39 Config Register 1: Secondary Clock Control Register (bit 15-0; offset 68h).......................................................... 66

13.2.40 Config Register 2: Secondary Clock Control Register (bit 15-0; offset 68h).......................................................... 66

13.2.41 Config Register 1 or 2: Non-Posted Memory Base Register (read/write, bit 15-0; offset 70h) .............................. 67

13.2.42 Config Register 1 or 2: Non-Posted Memory Limit Register (read/write, bit 31-16; offset 70h)............................. 6 7

13.2.43 Config Register 1: Port Option Register (bit 15-0; offset 74h) ............................................................................... 6 7

13.2.44 Config Register 2: Port Option Register (bit 15-0; offset 74h) ............................................................................... 6 8

13.2.45 Config Register 1 or 2: Master Timeout Counter Register (read/write, bit 31-16; offset 74h)................................ 6 9

13.2.46 Config Register 1 or 2: Retry Counter Register (read/write, bit 31-0; offset 78h) ..................................................69

13.2.47 Config Register 1 or 2: Sampling Timer Register (read/write, bit 31-0; offset 7Ch)................................................6 9

13.2.48 Config Register 1 or 2: Successful I/O Read Count Register (read/write, bit 31-0; offset 80h) .............................6 9

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PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

13.2.49 Config Register 1 or 2: Successful I/O Write Count Register (read/write, bit 31-0; offset 84h)............................. 6 9

13.2.50 Config Register 1 or 2: Successful Memory Read Count Register (read/write, bit 31-0; offset 88h) ..................... 69

13.2.51 Config Register 1 or 2: Successful Memory Write Count Register (read/write, bit 31-0; offset 8Ch).................... 6 9

13.2.52 Config Register 1: Primary Successful I/O Read Count Register (read/write, bit 31-0; offset 90h) .......................6 9

13.2.53 Config Register 1: Primary Successful I/O Write Count Register (read/write, bit 31-0; offset 94h)....................... 6 9

13.2.54 Config Register 1: Primary Successful Memory Read Count Register (read/write, bit 31-0; offset 98h) ............... 69

13.2.55 Config Register 1: Primary Successful Memory Write Count Register (read/write, bit 31-0; offset 9Ch).............. 6 9

14. Bridge Behavior .................................................................................................................................................... 7 0

14.1 Bridge Actions for Various Cycle Types ............................................................................................................... 70

14.2 Transaction Ordering ............................................................................................................................................. 70

14.3 Abnormal Termination (Initiated by Bridge Master) ............................................................................................. 7 1

14.3.1 Master Abort ......................................................................................................................................................... 71

14.3.2 Parity and Error Reporting ..................................................................................................................................... 7 1

14.3.3 Reporting Parity Errors........................................................................................................................................... 71

14.3.4 Secondary IDSEL mapping .................................................................................................................................... 71

15. IEEE 1149.1 Compatible JTAG Controller ........................................................................................................... 72

15.1 Boundary Scan Architecture ................................................................................................................................. 72

15.1.1 TAP Pins ................................................................................................................................................................ 7 2

15.1.2 Instruction Register ...............................................................................................................................................72

15.2 Boundary Scan Instruction Set .............................................................................................................................. 73

15.3 TAP Test Data Registers ....................................................................................................................................... 74

15.4 Bypass Register ..................................................................................................................................................... 74

15.5 Boundary-Scan Register......................................................................................................................................... 74

15.6 TAP Controller ....................................................................................................................................................... 7 4

16. Electrical and Timing Specifications.................................................................................................................... 7 9

16.1 Maximum Ratings ................................................................................................................................................... 7 9

16.2 3.3V DC Specifications ........................................................................................................................................... 79

16.3 3.3V AC Specifications........................................................................................................................................... 80

16.4 Primary and Secondary buses at 33 MHz clock timing .......................................................................................... 80

16.5 Power Consumption ............................................................................................................................................... 8 0

17 . 256-Pin PBGA Package........................................................................................................................................... 8 1

17.1 Part Number Ordering Information........................................................................................................................ 81

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PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

List of Figures

1-1. PI7C7100 on the System Board....................................................................................................................................2

1-2. PI7C7100 in Redundant Applications..........................................................................................................................2

1-3. PI7C7100 on Network Switching Hub..........................................................................................................................2

2-1. PI7C7100 Block Diagram ..............................................................................................................................................3

9-1. Secondary Arbiter Example ....................................................................................................................................... 4 8

15-1. Test Access Port Block Diagram ............................................................................................................................... 7 2

16-1. PCI Signal Timing Measurement Conditions ............................................................................................................ 80

17-1. 256-Pin PBGA Package Drawing................................................................................................................................ 81

List of Tables

4-1. PCI Transaction ......................................................................................................................................................... 13

4-2. Write Transaction Forwarding .................................................................................................................................. 1 4

4-3. Write Transaction Disconnect Address Boundaries ................................................................................................ 16

4-4. Read Pre-fetch Address Boundaries ......................................................................................................................... 17

4-5. Read Transaction Pre-fetching .................................................................................................................................. 1 8

4-6. Device Number to IDSEL S1_AD or S2_AD Pin Mapping ....................................................................................... 21

4-7. Delayed Write Target Termination Response ...........................................................................................................24

4-8. Responses to Posted Write Target Termination ....................................................................................................... 25

4-9. Responses to Delayed Read Target Termination......................................................................................................25

6-1. Summary of Tranaction Ordering .............................................................................................................................. 33

7-1. Setting the Primary Interface Detected Parity Error Bit ............................................................................................. 39

7-2. Setting the Secondary Interface Detected Parity Error Bit ........................................................................................ 4 0

7-3. Setting the Primary Interface Data Parity Detected Bit.............................................................................................. 40

7-4. Setting the Secondary InterfaceData Parity Detected Bit ......................................................................................... 41

7-5. Assertion of P_PERR#............................................................................................................................................... 4 2

7-6. Assertion of S_PERR#............................................................................................................................................... 4 3

7-7. Assertion of P_SERR# for Data Parity Errors ...........................................................................................................44

15-1. TAP Pins .................................................................................................................................................................... 7 3

15-2. JTAG Boundary Register Order ................................................................................................................................ 75

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PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

Appendix A - Timing Diagrams

1 . Configuration Read Transaction .................................................................................................................................A-3

2 . Configuration Write Transaction ................................................................................................................................A-3

3. Type 1 to Type 0 Configuration Read Transaction (P → S) ......................................................................................A-3

4. Type 1 to Type 0 Configuration Write Transaction (P → S) .....................................................................................A-4

5. Upstream Type 1 to Special Cycle Transaction (S → P) .............................................................................................A-4

6. Downstream Type 1 to Special Cycle Transaction (P → S) ........................................................................................A-5

7. Downstream Type 1 to Type 1 Configuration Read Transaction (P → S) ..................................................................A-5

8. Downstream Type 1 to Type 1 Configuration Write Transaction (P → S) .................................................................A-6

9. Upstream Delayed Burst Memory Read Transaction (S → P) ...................................................................................A-6

10. Downstream Delayed Burst Memory Read Transaction (P → S) ..............................................................................A-7

11. Downstream Delayed Memory Read Transaction (P/33MHz → S/33MHz)...............................................................A- 7

12. Downstream Delayed Memory Read Transaction (S2/33MHz → S1/33MHz) ...........................................................A-8

13. Downstream Delayed Memory Read Transaction (S1/33MHz → S2/33MHz) ...........................................................A-8

14. Upstream Delayed Memory Read Transaction (S/33MHz → P/33MHz) ...................................................................A-9

15. Downstream Posted Memory Write Transaction (P/33MHz → S/33MHz) ................................................................A-9

16. Downstream Posted Memory Write Transaction (S2/33MHz → S1/33MHz) ........................................................... A-10

17. Downstream Posted Memory Write Transaction (S1/33MHz → S2/33MHz) ........................................................... A-10

18. Upstream Posted Memory Write Transaction (S/33MHz → P/33MHz) ................................................................... A-11

19. Downstream Flow-Through Posted Memory Write Transaction (P/33MHz →S/33MHz)........................................A-11

20. Downstream Flow-Through Posted Memory Write Transaction (S2/33MHz →S1/33MHz)....................................A-12

21. Downstream Flow-Through Posted Memory Write Transaction (S1/33MHz →S2/33MHz)....................................A-12

22. Upstream Flow-Through Posted Memory Write Transaction (S/33MHz →P/33MHz) ............................................A-13

23. Downstream Delayed I/O Read Transaction (P → S) ...............................................................................................A-13

24 . Downstream Delayed I/O Read Transaction (S2/33MHz → S1/33MHz) .................................................................. A-14

25 . Downstream Delayed I/O Read Transaction (S1/33MHz → S2/33MHz) .................................................................. A-14

26. Downstream Delayed I/O Read Transaction (S/33MHz → P/33MHz) ......................................................................A-15

27. Downstream Delayed I/O Write Transaction (P → S) .............................................................................................. A-15

28 . Downstream Delayed I/O Write Transaction (S2/33MHz → S1/33MHz) ................................................................. A-16

29 . Downstream Delayed I/O Write Transaction (S1/33MHz → S2/33MHz) ................................................................. A-16

30. Upstream Delayed I/O Write Transaction (S → P) ...................................................................................................A-17

Appendix B - Evaluation Board User's Manual

General Information ........................................................................................................................................................... B- 3

Frequently Asked Questions ............................................................................................................................................ B-5

Appendix C - Three-Port PCI Bridge Evaluation Board Schematics

PCI Chip ............................................................................................................................................................................. C- 3

PCI Edge Connector .......................................................................................................................................................... C- 4

Secondary 1 PCI Bus ......................................................................................................................................................... C- 5

Secondary 2 PCI Bus ......................................................................................................................................................... C- 6

Top View............................................................................................................................................................................ C- 7

Appendix D - Representatives and Distributors

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PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

Product Features

• 32-bit Primary & two Secondary Ports run up to 33 MHz

• All three ports compliant with the PCI Local Bus Specification, Revision 2.1

• Compliant with PCI-to-PCI Bridge Architecture Specification, Revision 1.0.

- All I/O and memory commands

- Type 1 to Type 0 configuration conversion

- Type 1 to Type 1 configuration forwarding

- Type 1 configuration-write to special cycle conversion

• Concurrent primary to secondary bus operation and independent intra-secondary port channel to reduce traffic on the primary port

• Provides internal arbitration for two sets of eight secondary bus masters

- Programmable 2-level priority arbiter

- Disable control for use of external arbiter

• Supports posted write buffers on all directions

• Three 128 byte FIFOs for delay transactions

• Three 128 byte FIFOs for posted memory transactions

• Enhanced address decoding

- 32-bit I/O address range

- 32-bit memory-mapped I/O address range

- VGA addressing and VGA palette snooping

- ISA-aware mode for legacy support in the first 64KB

of I/O address range

• Interrupt Handling

- PCI interrupts are routed through an external interrupt concentrator

• Supports system transaction ordering rules

• Hot-plug support on secondary buses

- 3-State control of output buffers

• IEEE 1149.1 JTAG interface support

• 3.3V core; 3.3V PCI I/O interface with 5V I/O Tolerant

• 256-pin plastic BGA package

Product Description

PI7C7100 is the first triple port PCI-to-PCI Bridge device designed to be fully compliant with the 32-bit, 33 MHz implementation of the

PCI Local Bus Specification, Revision 2.1

. PI7C7100 supports only synchronous bus transactions between devices on the primary 33 MHz bus and the secondary buses operating at 33 MHz. The primary and the secondary buses can also operate in concurrent mode, resulting in added increase in system performance. Concurrent bus operation off-loads and isolates unnecessary traffic from the primary bus; thereby enabling a master and a target device on the same secondary PCI bus to communicate even while the primary bus is busy.

1. Introduction

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PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

Figure 1-2. PI7C7100 in Redundant Application

Figure 1-1. PI7C7100 on the System Board

S1 PCI Bus

S2 PCI Bus

PI7C7100

CPU

Slot

System

Memory

PCI

Device

PCI

Device

PI7C7100

System Primary

PCI Bus

PI7C7100

S1 PCI Bus

Master Controller Redundant Controller

S2 PCI Bus

System Primary

PCI Bus

Figure 1-3. PI7C7100 on Network Switching Hub

CPU

PCI Bus 32/33

PI7C7100

PCI Bus 32/33

Core

Logic

Cache

I/O Daughter

Board to

Isolate T raffic

PI7C7100 PI7C7100

Fast

Ethernet

Internal

Slot

Page 11

PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

Configuration

Arbiter

Secondary Interface B

Secondary Interface A

Secondary

PCI Bus A

Transaction

Queue #1

Transaction

Queue #2

Transaction

Queue #3

Configuration

Primary PCI Bus

Secondary

PCI Bus B

Primary

Interface

2. PI7C7100 Block Diagram

Figure 2-1. PI7C7100 Block Diagram

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PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

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3. Signal Definitions

3.1 Signal Types

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,11U,11V,11Y,01V

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,71W,61Y,61W

,81Y,81W,81U,71Y

,02U,91Y,91W,91U

71R,71T,02Y,02V

BP .ataD/sserddAyramirP sisserddA.subataddnasserddadexelpitluM

nehwdilavdnaelbatssiatadetirW.noitressa#EMARF_Pybdetacidni si#YDRT_Pnehwdilavdnaelbatssiataddaerdnadetressasi#YDRI_P dna#YDRI_PhtobnehwsegdekcolcgnisirnoderrefsnartsiataD.detressa dilavaotDA_Psevird0017C7IP,eldisubgniruD.detressaera#YDRT_P

.detressasi#TNG_Pnehwlevelcigol

]0:3[EBC_P91V,61U,21U,9VBP .selbanEetyB/dnammoCyramirP etybdnadleifdnammocdexelpitluM

epytnoitcasnartehtsevirdrotaitinieht,esahpsserddagniruD.dleifelbane atadgnirudselbaneetybehtsevirdrotaitiniehttahtretfA.snipesehtno

levelcigoldilavaot]0:3[EBC_Psevird0017C7IP,eldisubgniruD.sesahp

.detressasi#TNG_Pnehw

RAP_P51UBP .ytiraPyramirP dna,]0:3[EBC_P,]0:13[DA_PssorcanevesiytiraP

dnadilavsidnatupninasiRAP_P.)s'1'forebmunnevena.e.i(RAP_P

fonoitressaybdetacidni(esahpsserddaehtretfaelcycenoelbats tupninasiRAP_P,sesahpatadetirwroF.ytirapsserddarof)#EMARF_P ,esahpataddaerroF.detressasi#YDRI_Pretfakcolcenodilavsidna

.detressasi#YDRT_PretfakcolcenodilavsidnatuptuonasiRAP_P gniruD.detats-3erasenilDAPehtretfaelcycenodetats-irtsiRAP_PlangiS si#TNG_PnehwlevelcigoldilavaotRAPPsevird0017C7IP,eldisub

.detressa

#EMARF_P31WSTSP .)WOLevitcA(EMARFyramirP otnoitcasnartaforotaitiniehtybnevirD

fonoitressa-edehT.sseccanafonoitaruddnagninnigebehtetacidni erofeB.rotaitiniehtybdetseuqeresahpatadlanifehtsetacidni#EMARF_P

.elcycenorofetatsdetressa-edaotnevirdsiti,detats-3gnieb

3.2 Signals (Note: Signal name that ends with character ‘#’ is active LOW.)

3.2.1 Primary Bus Interface Signals

Page 13

PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

emaN#niPepyTnoitpircseD

#YDRI_P31VSTSP otytilibastietacidniotnoitcasnartaforotaitiniehtybnevirD.)WOLevitcA(YDRIyramirP

tonsiti,esahpatadanidetressaecnO.edisyramirpehtnoesahpatadtnerrucetelpmoc

detressa-edaotnevirdsiti,detats-3gnieberofeB.esahpatadfodnelitnudetressa-ed

.elcycenorofetats

#YDRT_P31USTSP otytilibastietacidniotnoitcasnartafotegratehtybnevirD.)WOLevitcA(YDRTyramirP

tonsiti,esahpatadanidetressaecnO.edisyramirpehtnoesahpatadtnerrucetelpmoc

detressa-edaotnevirdsiti,detats-3gnieberofeB.esahpatadfodnelitnudetressa-ed

.elcycenorofetats

#LESVED_P41YSTSP .)WOLevitcA(tceleSeciveDyramirP ecivedehttahtgnitacidnitegratehtybdetressA

langissihtfonoitressaehtrofstiaw0017C7IP,retsamasA.noitcasnartehtgnitpeccasi

erofeB.trobaretsamhtiwetanimret,esiwrehto;noitressa#EMARF_Pfoselcyc5nihtiw

.elcycenorofetatsdetressa-edaotnevirdsiti,detats-3gnieb

#POTS_P41WSTSP .)WOLevitcA(POTSyramirP sitegratehttahtgnitacidnitegratehtybdetressA

nevirdsiti,detats-3gnieberofeB.noitcasnarttnerrucehtpotsotrotaitiniehtgnitseuqer

.elcycenorofetatsdetressa-edaot

#KCOL_P41VSTSP .)WOLevitcA(KCOLyramirP .etelpmocotsnoitcasnartelpitlumrofretsamybdetressA

LESDI_P01YIP .tceleSDIyramirP 0017C7IPotsseccanoitarugifnoc0epyTrofeniltcelespihcsadesU

.ecapsnoitarugifnoc

#RREP_P51YSTSP rorrEytiraPyramirP.)WOLevitcA( rofdetcetedsirorreytirapatadanehwdetressA

-edaotnevirdsiti,detats-3gnieberofeB.ecafretniyramirpehtnodevieceratad

.elcycenorofetatsdetressa

#RRES_P51WDOP .)WOLevitcA(rorrEmetsySyramirP aetacidniotecivedynaybWOLnevirdebnaC

:nonipsihtsevird0017C7IP,noitidnocrorremetsys

rorreytirapsserddA•

subtegratnororreytirapatadetirwdetsoP•

detressa#RRES_2Sro#RRES_1SyradnoceS•

noitcasnartetirwdetsopgnirudtrobaretsaM•

noitcasnartetirwdetsopgnirudtrobategraT•

dedracsidnoitcasnartetirwdetsoP• dedracsidtseuqeretirwdeyaleD• dedracsidtseuqerdaerdeyaleD•

tuoemitretsamnoitcasnartdeyaleD•

.noitareporeporprofrotsiserpu-lluplanretxenaseriuqerlangissihT

#QER_P6WSTP .)WOLevitcA(tseuqeRyramirP stnawtitahtetacidniot0017C7IPybdetressasisihT

ICP2tsaeltarofnipsihtstressa-ed0017C7IP.subyramirpehtnonoitcasnartatratsot

.niagatignitressaerofebselcyckcolc

#TNG_P7UIP )WOLevitcA(tnarGyramirP .subyramirpehtsseccanac0017C7IP,detressanehW.

otRAP_PdnaEBC_P,DA_Pevirdlliw0017C7IP,detressa#TNG_PdnaeldigniruD

.slevelcigoldilav

#TESER_P5YIP .)WOLevitcA(TESERyramirP ebdluohsslangisICPlla,evitcasi#TESER_PnehW

.detats-3ylsuonorhcnysa

#HSULF_P5WIP .)WOLevitcA(HSULFOFIFyramirP )s(OFIFyramirplla,evitcasi#HSULF_PnehW

citatsaotdellupebdluohslangissihT.)snoitcasnartyramirpllaetadilavni(deraelcera

".hgih"

NE66M_P81V– .esUerutuFrofdevreseR .dnuorgotdeitebtsuM

3.2.1 Primary Bus Interface Signals (continued)

Page 14

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PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

emaN#niPepyTnoitpircseD

,]0:13[DA_1S

]0:13[DA_2S

,91C,02C,91B,02B

,71D,91D,02D,81C ,02F,71E,81E,91E ,91G,02G,71F,91F

,02M,81L,91L,02L

,91N,02N,71M,91M ,02R,71P,71N,81N

91T,02T,81R,91R

,1G,4H,3H,2H,1H,4J ,1E,4F,3F,2F,4G,3G

,5B,5C,1B,1C,1D,4E ,7B,7C,6A,6B,6C,6D

,9A,9B,9C,9D,8C,8D

01C,01D

BP .ataD/sserddAyradnoceS .subataddnasserddadexelpitluM

.noitressa#EMARF_2Sro#EMARF_1SybdetacidnisisserddA

si#YDRI_2Sro#YDRI_1SnehwdilavdnaelbatssiatadetirW

ro#YDRT_1Snehwdilavdnaelbatssiataddaerdnadetressa

segdekcolcgnisirnoderrefsnartsiataD.detressasi#YDRT_2S

dna#YDRI_2Sro#YDRT_1Sdna#YDRI_1Shtobnehw

sevird0017C7IP,eldisubgniruD.detressaera#YDRT_2S

ro#TNG_1SehtnehwlevelcigoldilavaotDA_2SroDA_1S

.ylevitcepserdetressasi#TNG_2S

,]0:3[EBC_1S

]0:3[EBC_2S

02P,71K,81G,02E

7A,4A,1A,1F

BP .selbanEetyB/dnammoCyradnoceS dnammocdexelpitluM

rotaitinieht,esahpsserddaehtgniruD.dleifelbaneetybdnadleif

rotaitiniehttahtretfA.snipesehtnoepytnoitcasnartehtsevird

,eldisubgniruD.sesahpatadgnirudselbaneetybehtsevird

cigoldilavaot]0:3[EBC_2Sro]0:3[EBC_1Ssevird0017C7IP

.detressasitnarglanretniehtnehwlevel

,RAP_1S

RAP_2S

,81K

BP .ytiraPyradnoceS ,]0:13[DA_1SssorcanevesiytiraP

dna,]0:3[EBC_2S,]0:13[DA_2SroRAP_1Sdna,]0:3[EBC_1S

nasiRAP_2SroRAP_1S.)s'1'forebmunnevena.e.i(RAP_2S

esahpsserddaehtretfaelcycenoelbatsdnadilavsidnatupni

rof)#EMARF_2Sro#EMARF_1Sfonoitressaybdetacidni(

nasiRAP_2SroRAP_1S,sesahpatadetirwroF.ytirapsserdda

si#YDRI_2Sro#YDRI_1Sretfakcolcenodilavsidnatupni

tuptuonasiRAP_2SroRAP_1S,esahpataddaerroF.detressa

.detressasi#YDRT_2Sro#YDRT_1Sretfakcolcenodilavsidna

DA_1Sehtretfaelcycenodetats-3siRAP_2SroRAP_1SlangiS

sevird0017C7IP,eldisubgniruD.detats-irterasenilDA_2Sro

sitnarglanretniehtnehwlevelcigoldilavaotRAP_2SroRAP_1S

.detressa

,#EMARF_1S

#EMARF_2S

,02H

STSP .)WOLevitcA(EMARFyradnoceS aforotaitiniehtybnevirD

.sseccanafonoitaruddnagninnigebehtetacidniotnoitcasnart

lanifehtsetacidni#EMARF_2Sro#EMARF_1Sfonoitressa-eD

siti,detats-3gnieberofeB.rotaitiniybdetseuqeresahpatad

.elcycenorofetatsdetressa-edaotnevird

,#YDRI_1S

#YDRI_2S

,91H

STSP .)WOLevitcA(YDRIyradnoceS aforotaitiniehtybnevirD

atadtnerrucehtetelpmocotytilibastietacidniotnoitcasnart

siti,esahpatadanidetressaecnO.edisyramirpehtnoesahp

,detats-3gnieberofeB.esahpatadehtfodnelitnudetressa-edton

.elcycenorofetatsdetressa-edaotnevirdsiti

,#YDRT_1S

#YDRT_2S

,81H

STSP .)WOLevitcA(YDRTyradnoceS afotegratehtybnevirD

atadtnerrucehtetelpmocotytilibastietacidniotnoitcasnart

siti,esahpatadanidetressaecnO.edisyramirpehtnoesahp

,detats-3gnieberofeB.esahpatadehtfodnelitnudetressa-edton

.elcycenorofetatsdetressa-edaotnevirdsiti

,#LESVED_1S

#LESVED_2S

,02J

STSP .)WOLevitcA(tceleSeciveDyradnoceS tegratehtybdetressA

asA.noitcasnartehtgnitpeccasiecivedehttahtgnitacidni

5nihtiwlangissihtfonoitressaehtrofstiaw0017C7IP,retsam

,esiwrehto;noitressa#EMARF_2Sro#EMARF_1Sfoselcyc

aotnevirdsiti,detats-3gnieberofeB.trobaretsamhtiwetanimret

.elcycenorofetatsdetressa-ed

3.2.2 Secondary Bus Interface Signals

Page 15

PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

emaN#niPepyTnoitpircseD

,#POTS_1S

#POTS_2S

,91J

STSP .)WOLevitcA(POTSyradnoceS ehttahtgnitacidnitegratehtybdetressA

gnieberofeB.noitcasnarttnerrucehtpotsotrotaitiniehtgnitseuqersitegrat

.elcycenorofetatsdetressa-edaotnevirdsiti,detats-3

,#KCOL_1S

#KCOL_2S

,81J

STSP .)WOLevitcA(KCOLyradnoceS snoitcasnartelpitlumrofretsamybdetressA

.etelpmocot

,#RREP_1S

#RREP_2S

,71J

STSP .)WOLevitcA(rorrEytiraPyradnoceS sirorreytirapatadanehwdetressA

ti,detats-3gnieberofeB.ecafretniyradnocesehtnodevieceratadrofdetceted

.elcycenorofetatsdetressa-edaotnevirdsi

,#RRES_1S

#RRES_2S

,02K

IP .)WOLevitcA(rorrEmetsySyradnoceS otecivedynaybWOLnevirdebnaC

.noitidnocrorremetsysaetacidni

,]0:7[#QER_1S

]0:7[#QER_2S

,21A,11B

,31C,31D

,61A,51C

71B,71C

,2P,3R,2T

,1M,2M,1P

3K,1K

UIP .)WOLevitcA(tseuqeRyradnoceS otecivedlanretxenaybdetressasisihT

situpniehT.subyradnoceSehtnonoitcasnartatratsotstnawtitahtetacidni

.DDVotrotsiserahguorhtpudellupyllanretxe

,]0:7[#TNG_1S

]0:7[#TNG_2S

,21B,11C ,41A,31B

,61B,41D

81B,61D

,1R,4P,1U ,4L,3M,4N

2K,1L

OP .)WOLevitcA(tnarGyradnoceS ehtsseccaotnipsihtstressa0017C7IP

selcyckcolcICP2tsaeltarofnipsihtstressa-ed0017C7IP.subyradnoces

,detressa#TNG_2Sro#TNG_1SdnaeldigniruD.niagatignitressaerofeb

dnaEBC_2S,DA_2SroRAP_1SdnaEBC_1S,DA_1Sevirdlliw0017C7IP

.slevelcigoldilavotRAP_2S

,#TESER_1S

#TESER_2S

,01B

OP .)WOLevitcA(TESERyradnoceS gniwollofehtfoynanehwdetressA

:temerasnoitidnoc

.detressasi#TESER_PlangiS.1

noitarugifnocniretsigerlortnocegdirbnitibteseryradnoceS.2

.tessiecaps

nevirderasorezdnadetats-3eraslangislortnoclla,detressanehW

.RAP_2Sdna,EBC_2S,DA_2SroRAP_1Sdna,EBC_1S,DA_1Sno

,NE_1S

NE_2S

,3W

UIP .)HGIHevitcA(elbanEyradnoceS ,evitcanisiNE_2SroNE_1SnehW

.detats-3ylsuonorhcnysaeblliwsub2Sro1SICPyradnoces

NE66M_S7D– .esUerutuFrofdevreseR .dnuorgotdeitebtsuM

#NFC_S2YUIC .niPlortnoCnoitcnuFlartneCsuByradnoceS selbaneti,WOLdeitnehW

.desuebtsumretibralanretxena,HGIHdeitnehW.retibralanretnieht

,tupnitnargsubyradnocesehtebotderugifnocersi#0QER_2Sro#0QER_1S

tseuqersubyradnocesehtebotderugifnocersi#0TNG_2Sro#0TNG_1Sdna

.tuptuo

3.2.2 Secondary Bus Interface Signals (continued)

Page 16

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PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

emaN#niPepyTnoitpircseD

KLC_P6VIP tupnIkcolCyramirP .ecafretniyramirpnonoitcasnartllarofgnimitsedivorP.

TUOKLC_S

]0:51[

,3P,1T,3T

,2L,3L,4M,3N

,21C,11A,1J ,41B,31A ,61C,51B

91A,81A

STP .tuptuOkcolCyradnoceS htiwsuonorhcnysesahpskcolcyradnocessedivorP

.KLC_Peht

3.2.3 Clock Signals

emaN#niPepyTnoitpircseD

SSAPYB4Y– .esUerutuFrofdevreseR .HGIHdeitebtsuM

MT_LLP3Y– .esUerutuFrofdevreseR .WOLdeitebtsuM

NIKLC_S5VIP .tupnIkcolCtseTyradnoceS oslatI.edomlamronniWOLotdeitebdluohstI

dna#MT_NACShtobfisesubyradnocesehtroftupnikcolcyradnocesaebyam

."1"cigolotdetcennoceraNE_NACS

#MT_NACS4VIC .)WOLevitcA(elbaneedoMtseTnacs-lluF eht,evitcasi#MT_NACSnehW

dnastupninacsehT.KLC_PsikcolcnacsehT.delbaneeblliwsniahcnacsevlewt

:swollofsaerastuptuo

,]2[QER_1S,]3[QER_1S,]4[QER_1S,]5[QER_1S,]6[QER_1S,]7[QER_1S

dna]2[QER_2S,]3[QER_2S,]4[QER_2S,]5[QER_2S,]6[QER_2S,]7[QER_2S

,]2[TNG_1S,]3[TNG_1S,]4[TNG_1S,]5[TNG_1S,]6[TNG_1S,]7[TNG_1S

]2[TNG_2S,]3[TNG_2S,]4[TNG_2S,]5[TNG_2S,]6[TNG_2S,]7[TNG_2S

ylevitcepser

NE_NACS5UUIC .lortnoCelbanEnacs-lluF noitarepotfihsnisinacs-lluf,WOLsiNE_NACSnehW

noitarepolellarapnisinacs-lluf,HGIHsiNE_NACSnehW.evitcasi#MT_NACSfi

fI.edomlamronniWOLdeitebdluohsNE_NACS.evitcasi#MT_NACSfi

kcolcehtsiNIKLC_S,"1"cigolotdetcennoceraNE_NACSdna#MT_NACS

dna"1"cigolotdetcennocsi#MT_NACSfI.kcolcyradnoceslanretniehtrofecruos

lanretniehtrofecruoskcolcehtsiKLC_P,"0"cigolotdetcennocsiNE_NACS

.kcolcyradnoces

:etoN .LLPpihc-noehtroflangisteserehtsiNE_NACS,pu-rewopgniruD

1OPMC6U– .esUerutuFrofdevreseR

devreseR4R devreseR

3.2.4 Miscellaneous Signals

3.2.5 JTAG Boundary Scan Signals

emaN#niPepyTnoitpircseD

KCT2VUIC .kcolCtseT gnirud0017C7IPehtfotuodnaotniataddnanoitamrofnietatskcolcotdesU

.nacsyradnuob SMT1WUIC tceleSedoMtseT .rellortnoctroPsseccAtseTehtfoetatsehtlortnocotdesU. ODT3VOTC .tuptuOataDtseT atadtfihsot)KCThtiwnoitcnujnocni(desusitiHGIHsiNENACSnehW

.maertstiblairesani)PAT(troPsseccAtseTehtfotuo

IDT2WUIC .tupnIataDtseT atadtfihsot)KCThtiwnoitcnujnocni(desusitiHGIHsiNENACSnehW

.maertstiblairesa)PAT(troPsseccAtseTehtotnisnoitcurtsnidna

#TSRT3UUIC .teseRtseT naotnirellortnoc)PAT(troPsseccAtseTehtteserotlangisWOLevitcA

.etatsdezilaitini

Page 17

PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

emaN#niPepyTnoitpircseD

DDV,91P,2N,71L,3J,81F,2E,51D,11D,5D,41C,8B

02W,51V,7V,1V,01U

rewoPlatigiDV3.3+

SSV,81D,21D,2C,02A,71A,51A,01A,8A,5A,3A

,2R,81P,1N,81M,91K,4K,2J,71H,71G,2G,3E

31Y6Y11W71V71U,41U,9U,2U,81T

dnuorGlatigiD

CCVA1Y LLProfV3.3golanA

DNGA4U LLProfdnuorGgolanA

3.2.6 Power and Ground

3.3 PI7C7100 PBGA Pin List

.oNniPemaNepyT.oNniPemaNepyT

1A]2[EBC_2SBP2A#YDRT_2SSTSP 3ASSV– 4A]1[EBC_2SBP 5ASSV– 6A]01[DA_2SBP 7A]0[EBC_2SBP8ASSV– 9A]2[DA_2SBP01ASSV–

11A]7[TUOKLC_SSTP21A]6[#QER_1SUIP 31A]5[TUOKLC_SSTP41A]6[#TNG_1SOP 51ASSV– 61A]2[#QER_1SUIP 71ASSV– 81A]1[TUOKLC_SSTP

91A]0[TUOKLC_SSTP02ASSV– 1B]61[DA_2SBP2B#YDRI_2SSTSP 3B#KCOL_2SSTSP4BRAP_2SBP 5B]41[DA_2SBP6B]11[DA_2SBP 7B]8[DA_2SBP8BDDV– 9B]3[DA_2SBP01B#TESER_1SOP

11B]7[#QER_1SUIP21B]6[#TNG_1SOP 31B]7[#TNG_1SOP41B]4[TUOKLC_SSTP 51B]3[TUOKLC_SSTP61B]2[#TNG_1SOP 71B]0[#QER_1SUIP81B]0[#TNG_1SOP

91B]03[DA_1SBP02B]13[DA_1SBP 1C]71[DA_2SBP2CSSV– 3C#POTS_2SSTSP4C#RES_2SIP 5C]51[DA_2SBP6C]21[DA_2SBP 7C]9[DA_2SBP8C]6[DA_2SBP 9C]4[DA_2SBP01C]0[DA_2SBP

11C]7[#TNG_1SOP21C]6[TUOKLC_SSTP 31C]4[#QER_1SUIP41CDDV– 51C]3[#QER_1SUIP61C]2[TUOKLC_SSTP

Page 18

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PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

.oNniPemaNepyT.oNniPemaNepyT

71C]1[#QER_1SUIP81C]72[DA_1SBP

91C]82[DA_1SBP02C]92[DA_1SBP 1D]81[DA_2SBP2D#EMARF_2SSTSP 3D#LESVED_2SSTSP4D#RREP_2SSTSP 5DDDV– 6D]31[DA_2SBP 7DNE66M_S– 8D]7[DA_2SBP 9D]5[DA_2SBP01D]1[DA_2SBP

11DDDV– 21DSSV– 31D]5[#QER_1SUIP41D]3[#TNG_1SOP 51DDDV– 61D]1[#TNG_1SOP 71D]42[DA_1SBP81DSSV–

91D]52[DA_1SBP02D]62[DA_1SBP 1E]02[DA_2SBP2EDDV– 3ESSV– 4E]91[DA_2SBP

71E]12[DA_1SBP81E]22[DA_1SBP

91E]32[DA_1SBP02E]3[EBC_1SBP 1F]3[EBC_2SBP2F]32[DA_2SBP 3F]22[DA_2SBP4F]12[DA_2SBP

71F]81[DA_1SBP81FDDV–

91F]91[DA_1SBP02F]02[DA_1SBP 1G]62[DA_2SBP2GSSV– 3G]52[DA_2SBP4G]42[DA_2SBP

71GSSV– 81G]2[EBC_1SBP

91G]61[DA_1SBP02G]71[DA_1SBP 1H]03[DA_2SBP2H]92[DA_2SBP 3H]82[DA_2SBP4H]72[DA_2SBP

71HSSV– 81H#YDRT_1SSTSP

91H#YDRI_1SSTSP02H#EMARF_1SSTSP 1J]8[TUOKLC_SSTP2JSSV– 3JDDV– 4J]13[DA_2SBP

71J#RREP_1SSTSP81J#KCOL_1SSTSP 91J#POTS_1SSTSP02J#LESVED_1SSTSP

3.3 PI7C7100 PBGA Pin List (continued)

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.oNniPemaNepyT.oNniPemaNepyT

1K]1[#QER_2SUIP2K]0[#TNG_2SOP 3K]0[#QER_2SUIP4KSSV–

71K]1[EBC_1SBP81KRAP_1SBP

91KSSV– 02K#RRES_1SIP 1L]1[#TNG_2SOP2L]9[TUOKLC_SSTP 3L]01[TUOKLC_SSTP4L]2[#TNG_2SOP

71LDDV– 81L]31[DA_1SBP

91L]41[DA_1SBP02L]51[DA_1SBP 1M]2[#QER_2SUIP2M]3[#QER_2SUIP 3M]3[#TNG_2SOP4M]11[TUOKLC_SSTP

71M]01[DA_1SBP81MSSV–

91M]11[DA_1SBP02M]21[DA_1SBP 1NSSV– 2NDDV– 3N]21[TUOKLC_SSTP4N]4[#TNG_2SOP

71N]6[DA_1SBP81N]7[DA_1SBP

91N]8[DA_1SBP02N]9[DA_1SBP 1P]4[#QER_2SUIP2P]5[#QER_2SUIP 3P]31[TUOKLC_SSTP4P]6[#TNG_2SOP

71P]5[DA_1SBP81PSSV–

91PDDV– 02P]0[EBC_1SBP

1R]5[#TNG_2SOP2RSSV– 3R]6[#QER_2SUIP4RdevreseR–

71R]0[DA_PBP81R]2[DA_1SBP

91R]3[DA_1SBP02R]4[DA_1SBP 1T]41[TUOKLC_SSTP2T]7[#QER_2SUIP 3T]51[TUOKLC_SSTP4T#TESER_2SOP

71T]1[DA_PBP81TSSV–

91T]0[DA_1SBP02T]1[DA_1SBP

1U]7[#TNG_2SOP2USSV– 3U#TSRTUIC4UDNGA– 5UNE_NACSUIC6U1OPMC– 7U#TNG_PIP8U]62[DA_PBP

3.3 PI7C7100 PBGA Pin List (continued)

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.oNniPemaNepyT.oNniPemaNepyT

9USSV– 01UDDV–

11U]91[DA_PBP21U]2[EBC_P 31U#YDRT_PBP41USSV– 51URAP_PBP61U]1[EBC_PBP 71USSV– 81U]01[DA_PBP

91U]7[DA_PBP02U]4[DA_PBP 1VDDV– 2VKCTUIC 3VODTOTC4V#MT_NACSIC 5VNIKLC_SIP6VKLC_PIP 7VDDV– 8V]72[DA_PBP 9V]3[EBC_PBP01V]22[DA_PBP

11V]02[DA_PBP21V]61[DA_PBP

31V#YDRI_PBP41V#KCOL_PSTSP

51VDDV– 61V]51[DA_PBP

71VSSV– 81VNE66M_P–

91V]0[EBC_PBP02V]3[DA_PBP

1WSMTUIC2WIDTUIC 3WNE_1SUIP4WNE_2SUIP 5W#HSULF_PIP6W#QER_PSTP 7W]03[DA_PBP8W]82[DA_PBP 9W]42[DA_PBP01W]32[DA_PBP

11WSSV– 21W]71[DA_PBP 31W#EMARF_PBP41W#POTS_PSTSP 51W#RRES_PDOP61W]41[DA_PBP 71W]21[DA_PBP81W]9[DA_PBP

91W]6[DA_PBP02WDDV– 1YCCVA– 2Y#NFC_SUIC 3YMT_LLP– 4YSSAPYB– 5Y#TESER_PIP6YSSV– 7Y]13[DA_PBP8Y]92[DA_PBP 9Y]52[DA_PBP01YLESDI_PIP

11Y]12[DA_PBP21Y]81[DA_PBP 31YSSV– 41Y#LESVED_PSTSP 51Y#RREP_PSTSP61Y]31[DA_PBP 71Y]11[DA_PBP81Y]8[DA_PBP 91Y]5[DA_PBP02Y]2[DA_PBP

3.3 PI7C7100 PBGA Pin List (continued)

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4. PCI Bus Operation

This chapter offers information about PCI transactions, transaction forwarding across PI7C7100, and transaction termination. The PI7C7100 has three 128-byte buffers for buffering of upstream and downstream transactions. These hold addresses, data, commands, and byte enables and are used for both read and write transactions.

4.1 Types of Transactions

This section provides a summary of PCI transactions performed by PI7C7100. Table 4–1 lists the command code and name of each PCI transaction. The Master and Target columns indicate support for each transaction when PI7C7100 initiates transactions as a master, on the primary (P) and secondary (S1, S2) buses, and when PI7C7100 responds to transactions as a target, on the primary (P) and secondary (S1, S2) buses.

snoitcasnarTfoepyTretsaMsasetaitinItegraTsasdnopseR

yramirPyradnoceSyramirPyradnoceS

0000egdelwonkcatpurretnINNNN

1000elcyclaicepSYYNN

0100daerO/IYYYY

1100etirwO/IYYYY

0010devreseRNNNN

1010devreseRNNNN 0110daeryromeMYYYY 1110etirwyromeMYYYY 0001devreseRNNNN

1001devreseRNNNN 0101daernoitarugifnoCNYYN

1101etirwnoitarugifnoC)ylno1epyT(YYY )ylno1epyT(Y 0011elpitlumdaeryromeMYYYY

1011elcycsserddalauDNNNN 0111enildaeryromeMYYYY 1111etadilavnidnaetirwyromeMNNYY

Table 4-1. PCI Transactions

As indicated in Table 4–1, the following PCI commands are not supported by PI7C7100:

• PI7C7100 never initiates a PCI transaction with a reserved command code and, as a target, PI7C7100 ignores reserved command codes.

• PI7C7100 does not generate interrupt acknowledge transactions. PI7C7100 ignores interrupt acknowledge transactions as a target.

• PI7C7100 does not respond to special cycle transactions. PI7C7100 cannot guarantee delivery of a special cycle transaction to downstream buses because of the broadcast nature of the special cycle command and the inability to control the transaction as a target. To generate special cycle transactions on other PCI buses, either upstream or downstream, Type 1 configuration write must be used.

• PI7C7100 neither generates Type 0 configuration transactions on the primary PCI bus nor responds to Type 0 configuration transactions on the secondary PCI buses.

• PI7C7100 does not support DAC (Dual Address Cycle) transactions.

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4.2 Single Address Phase

A 32-bit address uses a single address phase. This address is driven on P_AD[31:0], and the bus command is driven on P_CBE[3:0]. PI7C7100 supports the linear increment address mode only, which is indicated when the lowest two address bits are equal to zero. If either of the lowest two address bits is nonzero, PI7C7100 automatically disconnects the transaction after the first data transfer.

4.3 Device Select (DEVSEL#) Generation

PI7C7100 always performs positive address decoding (medium decode) when accepting transactions on either the primary or secondary buses. PI7C7100 never does subtractive decode.

4.4 Data Phase

The address phase of a PCI transaction is followed by one or more data phases. A data phase is completed when IRDY# and either TRDY# or STOP# are asserted. A transfer of data occurs only when both IRDY# and TRDY# are asserted during the same PCI clock cycle. The last data phase of a transaction is indicated when FRAME# is de-asserted and both TRDY# and IRDY# are asserted, or when IRDY# and STOP# are asserted. See Section 4.8 for further discussion of transaction termination.

Depending on the command type, PI7C7100 can support multiple data phase PCI transactions. For a detailed description of how PI7C7100 imposes disconnect boundaries, see Section 4.5.4 for write address boundaries and Section 4.6.3 read address boundaries.

4.5 Write Transactions

Write transactions are treated as either posted write or delayed write transactions. Table 4–2 shows the method of forwarding used for each type of write operation.

noitcasnarTfoepyT gnidrawroFfoepyT

etirwyromeM )yromemAGVtpecxe(detsoP

etadilavnidnaetirwyromeMdetsoP

etirwO/IdeyaleD

etirwnoitarugifnoc1epyTdeyaleD

Table 4-2. Write Transaction Forwarding

4.5.1 Posted Write Transactions

Posted write forwarding is used for “Memory Write” and “Memory Write and Invalidate” transactions. When PI7C7100 determines that a memory write transaction is to be forwarded across the bridge, PI7C7100 asserts

DEVSEL# with medium timing and TRDY# in the next cycle, provided that enough buffer space is available in the posted memory write queue for the address and at least one DWORD of data. Under this condition, PI7C7100 accepts write data without obtaining access to the target bus. The PI7C7100 can accept one DWORD of write data every PCI clock cycle. That is, no target wait state is inserted. The write data is stored in an internal posted write buffers and is subsequently delivered to the target.

The PI7C7100 continues to accept write data until one of the following events occurs:

• The initiator terminates the transaction by de-asserting FRAME# and IRDY#.

• An internal write address boundary is reached, such as a cache line boundary or an aligned 4KB boundary, depending on the transaction type.

• The posted write data buffer fills up.

For timing diagrams, see Figures 15-22 and 27-30 in Appendix A

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When one of the last two events occurs, the PI7C7100 returns a target disconnect to the requesting initiator on this data phase to terminate the transaction.

Once the posted write data moves to the head of the posted data queue, PI7C7100 asserts its request on the target bus. This can occur while PI7C7100 is still receiving data on the initiator bus. When the grant for the target bus is received and the target bus is detected in the idle condition, PI7C7100 asserts FRAME# and drives the stored write address out on the target bus. On the following cycle, PI7C7100 drives the first DWORD of write data and continues to transfer write data until all write data corresponding to that transaction is delivered, or until a target termination is received. As long as write data exists in the queue, PI7C7100 can drive one DWORD of write data each PCI clock cycle; that is, no master wait states are inserted. If write data is flowing through PI7C7100 and the initiator stalls, PI7C7100 will signal the last data phase for the current transaction at the target bus if the queue empties. PI7C7100 will restart the follow-on transactions if the queue has new data.

PI7C7100 ends the transaction on the target bus when one of the following conditions is met:

• All posted write data has been delivered to the target.

• The target returns a target disconnect or target retry (PI7C7100 starts another transaction to deliver the rest of write data).

• The target returns a target abort (PI7C7100 discards remaining write data).

• The master latency timer expires, and PI7C7100 no longer has the target bus grant (PI7C7100 starts another transaction to deliver remaining write data).

Section 4.8.3.2 provides detailed information about how PI7C7100 responds to target termination during posted write transactions.

4.5.2 Memory Write and Invalidate Transactions

Posted write forwarding is used for Memory Write and Invalidate transactions. PI7C7100 always converts Memory Write and Invalidate transactions to Memory Write transactions. The PI7C7100 disconnects Memory Write and Invalidate commands at aligned cache line boundaries. The cache line size

value in the cache line size register gives the number of DWORD in a cache line. If the value in the cache line size register does meet the memory write and invalidate conditions, the PI7C7100 returns

a target disconnect to the initiator either on a cache line boundary or when the posted write buffer fills. When the Memory Write and Invalidate transaction is disconnected before a cache line boundary is reached, typically

because the posted write buffer fills, the transaction is converted to Memory Write transaction.

4.5.3 Delayed Write Transactions

Delayed write forwarding is used for I/O write transactions and Type 1 configuration write transactions. A delayed write transaction guarantees that the actual target response is returned back to the initiator without holding the

initiating bus in wait states. A delayed write transaction is limited to a single DWORD data transfer. When a write transaction is first detected on the initiator bus, and PI7C7100 forwards it as a delayed transaction, PI7C7100

claims the access by asserting DEVSEL# and returns a target retry to the initiator. During the address phase, PI7C7100 samples the bus command, address, and address parity one cycle later. After IRDY# is asserted, PI7C7100 also samples the first data DWORD, byte enable bits, and data parity. This information is placed into the delayed transaction queue. The transaction is queued only if no other existing delayed transactions have the same address and command, and if the delayed transaction queue is not full. When the delayed write transaction moves to the head of the delayed transaction queue and all ordering constraints with posted data are satisfied. The PI7C7100 initiates the transaction on the target bus. PI7C7100 transfers the write data to the target. If PI7C7100 receives a target retry in response to the write transaction on the target bus, it continues to repeat the write transaction until the data transfer is completed, or until an error condition is encountered.

If PI7C7100 is unable to deliver write data after 224(default) or 232(maximum) attempts, PI7C7100 will report a system error. PI7C7100 also asserts P_SERR# if the primary SERR# enable bit is set in the command register. See Section 7.4 for information on the assertion of P_SERR#. When the initiator repeats the same write transaction (same command, address, byte enable bits, and data), and the completed delayed transaction is at the head of the queue, the PI7C7100

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3-Port PCI Bridge

ADVANCE INFORMATION

noitcasnarTfoepyTnoitidnoCyradnuoBsserddAdengilA

etirwdeyaleDllA refsnartatadenoretfastcennocsiD

etirwyromemdetsoP 61,8,4,2,1otlauqetonezisenilehcaC yradnuobsserddadengilaBK4 etirwyromemdetsoP61,8,4,2,1=ezisenilehcaC yradnuobenilehcactastcennocsiD

etadilavnidnaetirwyromemdetsoP 61,8,4,2,1otlauqetonezisenilehcaC yradnuobsserddadengilaBK4 etadilavnidnaetirwyromemdetsoP61,8,4,2,1=ezisenilehcaC,yradnuobenilehcaC

Table 4-3. Write Transaction Disconnect Address Boundaries

Note 1. Memory-write-disconnect-control bit is bit 1 of the chip control register at offset 40h in configuration space.

4.5.5 Buffering Multiple Write Transactions

PI7C7100 continues to accept posted memory write transactions as long as space for at least one DWORD of data in the posted write data buffer remains. If the posted write data buffer fills before the initiator terminates the write transaction, PI7C7100 returns a target disconnect to the initiator.

Delayed write transactions are posted as long as at least one open entry in the delayed transaction queue exists. Therefore, several posted and delayed write transactions can exist in data buffers at the same time. See Chapter 6 for information about how multiple posted and delayed write transactions are ordered.

4.5.6 Fast Back-to-Back Write Transactions

PI7C7100 can recognize and post fast back-to-back write transactions. When PI7C7100 cannot accept the second transaction because of buffer space limitations, it returns a target retry to the initiator.

claims the access by asserting DEVSEL# and returns TRDY# to the initiator, to indicate that the write data was transferred. If the initiator requests multiple DWORD, PI7C7100 also asserts STOP# in conjunction with TRDY# to signal a target disconnect. Note that only those bytes of write data with valid byte enable bits are compared. If any of the byte enable bits are turned off (driven HIGH), the corresponding byte of write data is not compared.

If the initiator repeats the write transaction before the data has been transferred to the target, PI7C7100 returns a target retry to the initiator. PI7C7100 continues to return a target retry to the initiator until write data is delivered to the target, or until an error condition is encountered. When the write transaction is repeated, PI7C7100 does not make a new entry into the delayed transaction queue. Section 4.8.3.1 provides detailed information about how PI7C7100 responds to target termination during delayed write transactions.

PI7C7100 implements a discard timer that starts counting when the delayed write completion is at the head of the delayed transaction queue. The initial value of this timer can be set to the retry counter register offset 78h. If the initiator does not repeat the delayed write transaction before the discard timer expires, PI7C7100 discards the delayed write completion from the delayed transaction queue. PI7C7100 also conditionally asserts P_SERR# (see Section 7.4).

4.5.4 Write Transaction Address Boundaries

PI7C7100 imposes internal address boundaries when accepting write data. The aligned address boundaries are used to prevent PI7C7100 from continuing a transaction over a device address boundary and to provide an upper limit on maximum latency. PI7C7100 returns a target disconnect to the initiator when it reaches the aligned address boundaries under conditions shown in Table 4–3.

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4.6 Read Transactions

Delayed read forwarding is used for all read transactions crossing PI7C7100. Delayed read transactions are treated as either prefetchable or non-prefetchable. Table 4-4 shows the rea d b eh avior, prefetchable or non-prefetchable, for each type of read operation. For Timing diagrams, see Figures 11-14 and 23-26 in Appendix A

4.6.1 Prefetchable Read Transactions

A prefetchable read transaction is a read transaction where PI7C7100 performs speculative DWORD reads, transferring data from the target before it is requested from the initiator. This behavior allows a prefetchable read transaction to consist of multiple data transfers. However, byte enable bits cannot be forwarded for all data phases as is done for the single data phase of the non-prefetchable read transaction. For prefetchable read transactions, PI7C7100 forces all byte enable bits to be turned on for all data phases.

Prefetchable behavior is used for memory read line and memory read multiple transactions, as well as for memory read transactions that fall into prefetchable memory space.

The amount of data that is pre-fetched depends on the type of transaction. The amount of pre-fetching may also be affected by the amount of free buffer space available in PI7C7100, and by any read address boundaries encountered.

Pre-fetching should not be used for those read transactions that have side effects in the target device, that is, control and status regi sters , FIFOs, and so on. The target device’s base address register or registers indicate if a memory address region is prefetchable.

4.6.2 Non-prefetchable Read Transactions

A non-prefetchable read transaction is a read transaction where PI7C7100 requests one and only one DWORD from the target and disconnects the initiator after delivery of the first DWORD of read data. Unlike prefetchable read transactions, PI7C7100 forwards the read byte enable information for the data phase.

Non-prefetchable behavior is used for I/O and configuration read transactions, as well as for memory read transactions that fall into non-prefetchable memory space.

If extra read transactions could have side effects, for example, when accessing a FIFO, use non-prefetchable read transactions to those locations. Accordingly, if it is important to retain the value of the byte enable bits during the data phase, use non-prefetchable read transactions. If these locations are mapped in memory space, use the memory read command and map the target into non-prefetchable (memory-mapped I/O) memory space to use non-prefetching behavior.

4.6.3 Read Pre-fetch Address Boundaries

PI7C7100 imposes internal read address boundaries on read pre-fetched data. When a read transaction reaches one of these aligned address boundaries, the PI7C7100 stops pre-fetched data, unless the target signals a target disconnect before the read pre-fetched boundary is reached. When PI7C7100 finishes transferring this read data to the initiator, it returns a target disconnect with the last data transfer, unless the initiator completes the transaction before all pre-fetched read data is delivered. Any leftover pre-fetched data is discarded.

Prefetchable read transactions in flow-through mode pre-fetch to the nearest aligned 4KB address boundary, or until the initiator de-asserts FRAME#. Section 4.6.6 describes flow-through mode during read operations.

Table 4-5 shows the read pre-fetch address boundaries for read transactions during non-flow-through mode.

Table 4-4. Read Pre-fetch Address Boundaries

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daergifnoC-- )hctef-erpon(DROWDenO

daerO/I-- )hctef-erpon(DROWDenO

daeryromeMelbahcteferp-noN- )hctef-erpon(DROWDenO daeryromeMelbahcteferP8,4,2,1otlauqetonSLCyradnuobsserddadengilaDROWD-61 daeryromeMelbahcteferP8,4,2,1=SLCyradnuobsserddaenilehcaC

enildaeryromeM- 8,4,2,1otlauqetonSLCyradnuobsserddadengilaDROWD-61 enildaeryromeM- 8,4,2,1=SLCyradnuobenilehcaC

elpitlumdaeryromeM- 8,4,2,1otlauqetonSLCyradnuobsserddadengilaDROWD-23 elpitlumdaeryromeM- 8,4,2,1=SLCyradnuobenilehcacfosemit2

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4.6.4 Delayed Read Requests

PI7C7100 treats all read transactions as delayed read transactions, which means that the read request from the initiator is posted into a delayed transaction queue. Read data from the target is placed in the read data queue directed toward the initiator bus interface and is transferred to the initiator when the initiator repeats the read transaction.

When PI7C7100 accepts a delayed read request, it first samples the read address, read bus command, and address parity. When IRDY# is asserted, PI7C7100 then samples the byte enable bits for the first data phase. This information is entered into the delayed transaction queue. PI7C7100 terminates the transaction by signaling a target retry to the initiator. Upon reception of the target retry, the initiator is required to continue to repeat the same read transaction until at least one data transfer is completed, or until a target response (target abort or master abort) other than a target retry is received.

4.6.5 Delayed Read Completion with Target

When delayed read request reaches the head of the delayed transaction queue, PI7C7100 arbitrates for the target bus and initiates the read transaction only if all previously queued posted write transactions have been delivered. PI7C7100 uses the exact read address and read command captured from the initiator during the initial delayed read request to initiate the read transaction. If the read transaction is a non-prefetchable read, PI7C7100 drives the captured byte enable bits during the next cycle. If the transaction is a prefetchable read transaction, it drives all byte enable bits to zero for all data phases. If PI7C7100 receives a target retry in response to the read transaction on the target bus, it continues to repeat the read transaction until at least one data transfer is completed, or until an error condition is encountered. If the transaction is terminated via normal master termination or target disconnect after at least one data transfer has been completed, PI7C7100 does not initiate any further attempts to read more data.

If PI7C7100 is unable to obtain read data from the target after 224(default) or 232(maximum) attempts, PI7C7100 will report system error. The number of attempts is programmable. PI7C7100 also asserts P_SERR# if the primary SERR# enable bit is set in the command register. See Section 7.4 for information on the assertion of P_SERR#.

Once PI7C7100 receives DEVSEL# and TRDY# from the target, it transfers the data read to the opposite direction read data queue, pointing toward the opposite interface, before terminating the transaction. For example, read data in response to a downstream read transaction initiated on the primary bus is placed in the upstream read data queue. The PI7C7100 can accept one DWORD of read data each PCI clock cycle; that is, no master wait states are inserted. The number of DWORD transferred during a delayed read transaction depends on the conditions given in Table 4–5 (assuming no disconnect is received from the target).

4.6.6 Delayed Read Completion on Initiator Bus

When the transaction has been completed on the target bus, and the delayed read data is at the head of the read data queue, and all ordering constraints with posted write transactions have been satisfied, the PI7C7100 transfers the data to the initiator when the initiator repeats the transaction. For memory read transactions, PI7C7100 aliases the memory read, memory read line, and memory read multiple bus commands when matching the bus command of the transaction to the bus command in the delayed transaction queue. PI7C7100 returns a target disconnect along with the transfer of the last DWORD of read data to the initiator. If PI7C7100 initiator terminates the transaction before all read data has been transferred, the remaining read data left in data buffers is discarded.

noitcasnarTfoepyTroivaheBdaeR

daerO/Ienodrevengnihctef-erP

daernoitarugifnoCenodrevengnihctef-erP

daeryromeM ecapselbahcteferpnisserddafidesugnihctef-erp:maertsnwoD

desugnihctef-erp:maertspU

enildaeryromeMdesusyawlagnihctef-erP

elpitlumdaeryromeMdesusyawlagnihctef-erP

Table 4-5. Read Transaction Pre-Fetching

See Section 5.3 for detailed information about prefetchable and non-prefetchable address spaces.

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When the master repeats the transaction and starts transferring prefetchable read data from data buffers while the read transaction on the target bus is still in progress and before a read boundary is reached on the target bus, the read transaction starts operating in flow-through mode. Because data is flowing through the data buffers from the target to the initiator, long read bursts can then be sustained. In this case, the read transaction is allowed to continue until the initiator terminates the transaction, or until an aligned 4KB address boundary is reached, or until the buffer fills, whichever comes first. When the buffer empties, PI7C7100 reflects the stalled condition to the initiator by de-asserting TRDY# until more read data is available; otherwise, PI7C7100 does not insert any target wait states. When the initiator terminates the transaction, PI7C7100 de-assertion of FRAME# on the initiator bus is forwarded to the target bus. Any remaining read data is discarded.

PI7C7100 implements a discard timer that starts counting when the delayed read completion is at the head of the delayed transaction queue, and the read data is at the head of the read data queue. The initial value of this timer is programmable through configuration register. If the initiator does not repeat the read transaction and before the discard timer expires (2

default), PI7C7100 discards the read transaction and read data from its queues. PI7C7100 also conditionally asserts P_SERR# (see Section 7.4).

PI7C7100 has the capability to post multiple delayed read requests, up to a maximum of four in each direction. If an initiator starts a read transaction that matches the address and read command of a read transaction that is already queued, the current read command is not posted as it is already contained in the delayed transaction queue.

See Section 6 for a discussion of how delayed read transactions are ordered when crossing PI7C7100.

4.7 Configuration Transactions

Configuration transactions are used to initialize a PCI system. Every PCI device has a configuration space that is accessed by configuration commands. All registers are accessible in configuration space only.

In addition to accepting configuration transactions for initialization of its own configuration space, the PI7C7100 also forwards configuration transactions for device initialization in hierarchical PCI systems, as well as for special cycle generation.

To support hierarchical PCI bus systems, two types of configuration transactions are specified: Type 0 and Type 1. Type 0 configuration transactions are issued when the intended target resides on the same PCI bus as the initiator. A Type

0 configuration transaction is identified by the configuration command and the lowest two bits of the address set to 00b. Type 1 configuration transactions are issued when the intended target resides on another PCI bus, or when a special cycle

is to be generated on another PCI bus. A Type 1 configuration command is identified by the configuration command and the lowest two address bits set to 01b.

The register number is found in both Type 0 and Type 1 formats and gives the DWORD address of the configuration register to be accessed. The function number is also included in both Type 0 and Type 1 formats and indicates which function of a multifunction device is to be accessed. For single-function devices, this value is not decoded. The addresses of Type 1 configuration transaction include a 5-bit field designating the device number that identifies the device on the target PCI bus that is to be accessed. In addition, the bus number in Type 1 transactions specifies the PCI bus to which the transaction is targeted. For timing diagrams, see Figures 1-8 in Appendix A.

4.7.1 Type 0 Access to PI7C7100

The configuration space is accessed by a Type 0 configuration transaction on the primary interface. The configuration space cannot be accessed from the secondary bus. The PI7C7100 responds to a Type 0 configuration transaction by asserting P_DEVSEL# when the following conditions are met during the address phase:

• The bus command is a configuration read or configuration write transaction.

• Lowest two address bits P_AD[1:0] must be 00b.

• Signal P_IDSEL must be asserted.

Function code is either 0 for configuration space of S1, or 1 for configuration space of S2 as PI7C7100 is a multi-function device.

PI7C7100 limits all configuration access to a single DWORD data transfer and returns target-disconnect with the first data transfer if additional data phases are requested. Because read transactions to configuration space do not have side effects, all bytes in the requested DWORD are returned, regardless of the value of the byte enable bits.

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3-Port PCI Bridge

ADVANCE INFORMATION

Type 0 configuration write and read transactions do not use data buffers; that is, these transactions are completed immediately, regardless of the state of the data buffers. The PI7C7100 ignores all Type 0 transactions initiated on the secondary interface.

4.7.2 Type 1 to Type 0 Conversion

Type 1 configuration transactions are used specifically for device configuration in a hierarchical PCI bus system. A PCIto-PCI bridge is the only type of device that should respond to a Type 1 configuration command. Type 1 configuration commands are used when the configuration access is intended for a PCI device that resides on a PCI bus other than the one where the Type 1 transaction is generated.

PI7C7100 performs a Type 1 to Type 0 translation when the Type 1 transaction is generated on the primary bus and is intended for a device attached directly to the secondary bus. PI7C7100 must convert the configuration command to a Type 0 format so that the secondary bus device can respond to it. Type 1 to Type 0 translations are performed only in the downstream direction; that is, PI7C7100 generates a Type 0 transaction only on the secondary bus, and never on the primary bus.

PI7C7100 responds to a Type 1 configuration transaction and translates it into a Type 0 transaction on the secondary bus when the following conditions are met during the address phase:

• The lowest two address bits on P_AD[1:0] are 01b.

• The bus number in address field P_AD[23:16] is equal to the value in the secondary bus number register in

configuration space.

• The bus command on P_CBE[3:0] is a configuration read or configuration write transaction.

• When PI7C7100 translates the Type 1 transaction to a Type 0 transaction on the secondary interface, it

performs the following translations to the address:

• Sets the lowest two address bits on S1_AD[1:0] or S2_AD[1:0] to 00b.

• Decodes the device number and drives the bit pattern specified in Table 4–6 on S1_AD[31:16] or S2_AD[31:16]

for the purpose of asserting the device’s IDSEL signal.

• Sets S1_AD[15:11] or S2_AD[15:11] to 0.

• Leaves unchanged the function number and register number fields. PI7C7100 asserts a unique address line based on the device number. These address lines may be used as secondary bus IDSEL signals. The mapping of the address lines depends on the device number in the Type 1 address bits P_AD[15:11]. Table 4–6 presents the mapping that PI7C7100 uses

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3-Port PCI Bridge

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PI7C7100 can assert up to 16 unique address lines to be used as IDSEL signals for up to 16 devices on the secondary bus, for device numbers ranging from 0 through 15. Because of electrical loading constraints of the PCI bus, more than 16 IDSEL signals should not be necessary. However, if device numbers greater than 15 are desired, some external method of generating IDSEL lines must be used, and no upper address bits are then asserted. The configuration transaction is still translated and passed from the primary bus to the secondary bus. If no IDSEL pin is asserted to a secondary device, the transaction ends in a master abort.

PI7C7100 forwards Type 1 to Type 0 configuration read or write transactions as delayed transactions. Type 1 to Type 0 configuration read or write transactions are limited to a single 32-bit data transfer.

4.7.3 Type 1 to Type 1 Forwarding

Type 1 to Type 1 transaction forwarding provides a hierarchical configuration mechanism when two or more levels of PCIto-PCI bridges are used.

When PI7C7100 detects a Type 1 configuration transaction intended for a PCI bus downstream from the secondary bus, PI7C7100 forwards the transaction unchanged to the secondary bus. Ultimately, this transaction is translated to a Type 0 configuration command or to a special cycle transaction by a downstream PCI-to-PCI bridge. Downstream Type 1 to Type 1 forwarding occurs when the following conditions are met during the address phase:

• The lowest two address bits are equal to 01b.

• The bus number falls in the range defined by the lower limit (exclusive) in the secondary bus number register and the

upper limit (inclusive) in the subordinate bus number register.

• The bus command is a configuration read or write transaction.

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h000000100000000000000061 h110000010000000000000071 h201000001000000000000081 h311000000100000000000091 h400100000010000000000002 h510100000001000000000012 h60110000000100000000022 h711100000000010000000032 h800010000000001000000042 h910010000000000100000052

hA01010000000000010000062 hB11010000000000001000072 hC00110000000000000100082 hD10110000000000000010092 hE01110000000000000001003

hF11110000000000000000113

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Table 4–6. Device Number to IDSEL S1_AD or S2_AD Pin Mapping

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PI7C7100 also supports Type 1 to Type 1 forwarding of configuration write transactions upstream to support upstream special cycle generation. A Type 1 configuration command is forwarded upstream when the following conditions are met:

• The lowest two address bits are equal to 01b.

• The bus number falls outside the range defined by the lower limit (inclusive) in the secondary bus number register and

the upper limit (inclusive) in the subordinate bus number register.

• The device number in address bits AD[15:11] is equal to 11111b.

• The function number in address bits AD[10:8] is equal to 111b.

• The bus command is a configuration write transaction. The PI7C7100 forwards Type 1 to Type 1 configuration write transactions as delayed transactions. Type 1 to Type 1

configuration write transactions are limited to a single data transfer.

4.7.4 Special Cycles

The Type 1 configuration mechanism is used to generate special cycle transactions in hierarchical PCI systems. Special cycle transactions are ignored by acting as a target and are not forwarded across the bridge. Special cycle transactions can be generated from Type 1 configuration write transactions in either the upstream or the downstream direction.

PI7C7100 initiates a special cycle on the target bus when a Type 1 configuration write transaction is being detected on the initiating bus and the following conditions are met during the address phase:

• The lowest two address bits on AD[1:0] are equal to 01b.

• The device number in address bits AD[15:11] is equal to 11111b.

• The function number in address bits AD[10:8] is equal to 111b.

• The register number in address bits AD[7:2] is equal to 000000b.

• The bus number is equal to the value in the secondary bus number register in configuration space for downstream

forwarding or equal to the value in the primary bus number register in configuration space for upstream forwarding.

• The bus command on CBE# is a configuration write command. When PI7C7100 initiates the transaction on the target interface, the bus command is changed from configuration write

to special cycle. The address and data are forwarded unchanged. Devices that use special cycles ignore the address and decode only the bus command. The data phase contains the special cycle message. The transaction is forwarded as a delayed transaction, but in this case the target response is not forwarded back (because special cycles result in a master abort). Once the transaction is completed on the target bus, through detection of the master abort condition, PI7C7100 responds with TRDY# to the next attempt of the configuration transaction from the initiator. If more than one data transfer is requested, PI7C7100 responds with a target disconnect operation during the first data phase.

4.8 Transaction Termination

This section describes how PI7C7100 returns transaction termination conditions back to the initiator. The initiator can terminate transactions with one of the following types of termination:

• Normal termination

Normal termination occurs when the initiator de-asserts FRAME# at the beginning of the last data phase, and deasserts IRDY# at the end of the last data phase in conjunction with either TRDY# or STOP# assertion from the target.

• Master abort

A master abort occurs when no target response is detected. When the initiator does not detect a DEVSEL# from the target within five clock cycles after asserting FRAME#, the initiator terminates the transaction with a master abort. If FRAME# is still asserted, the initiator de-asserts FRAME# on the next cycle, and then de-asserts IRDY# on the following cycle. IRDY# must be asserted in the same cycle in which FRAME# de-asserts. If FRAME# is already de-asserted, IRDY# can be de-asserted on the next clock cycle following detection of the master abort condition.

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The target can terminate transactions with one of the following types of termination:

• Normal termination—TRDY# and DEVSEL# asserted in conjunction with FRAME# de-asserted and IRDY# asserted.

• Target retry—STOP# and DEVSEL# asserted with TRDY# de-asserted during the first data phase. No data transfers

occur during the transaction. This transaction must be repeated.

• Target disconnect with data transfer—STOP#, DEVSEL# and TRDY# asserted. It signals that this is the last data transfer of the transaction.

• Target disconnect without data transfer—STOP# and DEVSEL# asserted with TRDY# de-asserted after previous data transfers have been made. Indicates that no more data transfers will be made during this transaction.

• Target abort—STOP# asserted with DEVSEL# and TRDY# de-asserted.

Indicates that target will never be able to complete this transaction. DEVSEL# must be asserted for at least one cycle during the transaction before the target abort is signaled.

4.8.1 Master Termination Initiated by PI7C7100

PI7C7100, as an initiator, uses normal termination if DEVSEL# is returned by target within five clock cycles of PI7C7100’s assertion of FRAME# on the target bus. As an initiator, PI7C7100 terminates a transaction when the following conditions are met:

• During a delayed write transaction, a single DWORD is delivered.

• During a non-prefetchable read transaction, a single DWORD is transferred from the target.

• During a prefetchable read transaction, a pre-fetch boundary is reached.

• For a posted write transaction, all write data for the transaction is transferred from data buffers to the target.

• For burst transfer, with the exception of “Memory Write and Invalidate” transactions, the master latency timer expires and the PI7C7100’s bus grant is de-asserted.

• The target terminates the transaction with a retry, disconnect, or target abort.

If PI7C7100 is delivering posted write data when it terminates the transaction because the master latency timer expires, it initiates another transaction to deliver the remaining write data. The address of the transaction is updated to reflect the address of the current DWORD to be delivered.

If PI7C7100 is pre-fetching read data when it terminates the transaction because the master latency timer expires, it does not repeat the transaction to obtain more data.

4.8.2 Master Abort Received by PI7C7100

If the initiator initiates a transaction on the target bus and does not detect DEVSEL# returned by the target within five clock cycles of the assertion of FRAME#, PI7C7100 terminates the transaction with a master abort. This sets the receivedmaster-abort bit in the status register corresponding to the target bus.

For delayed read and write transactions, PI7C7100 is able to reflect the master abort condition back to the initiator. When PI7C7100 detects a master abort in response to a delayed transaction, and when the initiator repeats the transaction, PI7C7100 does not respond to the transaction with DEVSEL# which induces the master abort condition back to the initiator. The transaction is then removed from the delayed transaction queue. When a master abort is received in response to a posted write transaction, PI7C7100 discards the posted write data and makes no more attempt to deliver the data. PI7C7100 sets the received-master-abort bit in the status register when the master abort is received on the primary bus, or it sets the received master abort bit in the secondary status register when the master abort is received on the secondary interface. When master abort is detected in posted write transaction with both master-abort-mode bit (bit 5 of bridge control register) and the SERR# enable bit (bit 8 of command register for secondary bus S1 or S2) are set, PI7C7100 asserts P_SERR# if the master-abort-on-posted-write is not set. The master-abort-on-posted-write bit is bit 4 of the P_SERR# event disable register (offset 64h).

Note: When PI7C7100 performs a Type 1 to special cycle conversion, a master abort is the expected termination for the special cycle on the target bus. In this case, the master abort received bit is not set, and the Type 1 configuration transaction is disconnected after the first data phase.

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Table 4-7. Delayed Write Target Termination Response

After the PI7C7100 makes 224(default) attempts of the same delayed write transaction on the target bus, PI7C7100 asserts P_SERR# if the SERR# enable bit (bit 8 of command register for secondary bus S1 or S2) is set and the delayed-writenon-delivery bit is not set. The delayed-write-non-delivery bit is bit 5 of P_SERR# event disable register (offset 64h). PI7C7100 will report system error. See Section 7.4 for a description of system error conditions.

4.8.3.2 Posted Write Target Termination Response

When PI7C7100 initiates a posted write transaction, the target termination cannot be passed back to the initiator. Table 4–8 shows the response to each type of target termination that occurs during a posted write transaction.

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4.8.3 Target Termination Received by PI7C7100

When PI7C7100 initiates a transaction on the target bus and the target responds with DEVSEL#, the target can end the transaction with one of the following types of termination:

• Normal termination (upon de-assertion of FRAME#)

• Target retry

• Target disconnect

• Target abort PI7C7100 handles these terminations in different ways, depending on the type of transaction being performed.

4.8.3.1 Delayed Write Target Termination Response

When PI7C7100 initiates a delayed write transaction, the type of target termination received from the target can be passed back to the initiator. Table 4–7 shows the response to each type of target termination that occurs during a delayed write transaction.

PI7C7100 repeats a delayed write transaction until one of the following conditions is met:

• PI7C7100 completes at least one data transfer.

• PI7C7100 receives a master abort.

• PI7C7100 receives a target abort. PI7C7100 makes 224(default) or 232(maximum) write attempts resulting in a response of target retry.

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3-Port PCI Bridge

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Table 4-8. Responses to Posted Write Target Termination

Note that when a target retry or target disconnect is returned and posted write data associated with that transaction remains in the write buffers, PI7C7100 initiates another write transaction to attempt to deliver the rest of the write data. If there is a target retry, the exact same address will be driven as for the initial write transaction attempt. If a target disconnect is received, the address that is driven on a subsequent write transaction attempt will be updated to reflect the address of the current DWORD. If the initial write transaction is Memory-Write-and-Invalidate transaction, and a partial delivery of write data to the target is performed before a target disconnect is received, PI7C7100 will use the memory write command to deliver the rest of the write data. It is because an incomplete cache line will be transferred in the subsequent write transaction attempt.

After the PI7C7100 makes 224(default) write transaction attempts and fails to deliver all posted write data associated with that transaction, PI7C7100 asserts P_SERR# if the primary SERR# enable bit is set (bit 8 of command register for secondary bus S1 or S2) and posted-write-non-delivery bit is not set. The posted-write-non-delivery bit is the bit 2 of P_SERR# event disable register (offset 64h). PI7C7100 will report system error. See Section 7.4 for a discussion of system error conditions.

4.8.3.3 Delayed Read Target Termination Response

When PI7C7100 initiates a delayed read transaction, the abnormal target responses can be passed back to the initiator. Other target responses depend on how much data the initiator requests. Table 4–9 shows the response to each type of target termination that occurs during a delayed read transaction.

PI7C7100 repeats a delayed read transaction until one of the following conditions is met:

• PI7C7100 completes at least one data transfer.

• PI7C7100 receives a master abort.

• PI7C7100 receives a target abort.

• PI7C7100 makes 224(default) read attempts resulting in a response of target retry.

Table 4-9. Responses to Delayed Read Target Termination

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3-Port PCI Bridge

ADVANCE INFORMATION

After PI7C7100 makes 224(default) attempts of the same delayed read transaction on the target bus, PI7C7100 asserts P_SERR# if the primary SERR# enable bit is set (bit 8 of command register for secondary bus S1 or S2) and the delayedwrite-non-delivery bit is not set. The delayed-write-non-delivery bit is bit 5 of P_SERR# event disable register (offset 64h). PI7C7100 will report system error. See Section 7.4 for a description of system error conditions.

4.8.4 Target Termination Initiated by PI7C7100

PI7C7100 can return a target retry, target disconnect, or target abort to an initiator for reasons other than detection of that condition at the target interface.

4.8.4.1 Target Retry

PI7C7100 returns a target retry to the initiator when it cannot accept write data or return read data as a result of internal conditions. PI7C7100 returns a target retry to an initiator when any of the following conditions is met:

For delayed write transactions:

• The transaction is being entered into the delayed transaction queue.

• Transaction has already been entered into delayed transaction queue, but target response has not yet been

received.

• Target response has been received but has not progressed to the head of the return queue.

• The delayed transaction queue is full, and the transaction cannot be queued.

• A transaction with the same address and command has been queued.

• A locked sequence is being propagated across PI7C7100, and the write transaction is not a locked transaction.

• The target bus is locked and the write transaction is a locked transaction.

• Use more than 16 clocks to accept this transaction.

For delayed read transactions:

• The transaction is being entered into the delayed transaction queue.

• The read request has already been queued, but read data is not yet available.

• Data has been read from target, but it is not yet at head of the read data queue, or a posted write transaction

precedes it.

• The delayed transaction queue is full, and the transaction cannot be queued.

• A delayed read request with the same address and bus command has already been queued.

• A locked sequence is being propagated across PI7C7100, and the read transaction is not a locked transaction.

• PI7C7100 is currently discarding previously pre-fetched read data.

• The target bus is locked and the write transaction is a locked transaction.

• Use more than 16 clocks to accept this transaction.

For posted write transactions:

• The posted write data buffer does not have enough space for address and at least one DWORD of write data.

• A locked sequence is being propagated across PI7C7100, and the write transaction is not a locked transaction. When a target retry is returned to the initiator of a delayed transaction, the initiator must repeat the transaction with the

same address and bus command as well as the data if it is a write transaction, within the time frame specified by the master timeout value. Otherwise, the transaction is discarded from the buffers.

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4.8.4.2 Target Disconnect

PI7C7100 returns a target disconnect to an initiator when one of the following conditions is met:

• PI7C7100 hits an internal address boundary.

• PI7C7100 cannot accept any more write data.

• PI7C7100 has no more read data to deliver.

See Section 4.5.4 for a description of write address boundaries, and Section 4.6.3 for a description of read address boundaries.

4.8.4.3 Target Abort

PI7C7100 returns a target abort to an initiator when one of the following conditions is met:

• PI7C7100 is returning a target abort from the intended target.

When PI7C7100 returns a target abort to the initiator, it sets the signaled target abort bit in the status register corresponding to the initiator interface.

4.9 Concurrent Mode Operation

The Bridge can be configured to run in concurrent operation. Concurrent operation is defined as cycles going from one device on one secondary bus to another device on the same or other secondary bus. This off-loads traffic from the primary bus, allowing other traffic to run on the primary bus concurrently.

The Bridge is already configured to handle concurrent operation. However, the devices themselves need to be configured to do so. Meaning, device drivers for the specific device used will have to be configured to perform the operation. Please contact Pericom for more information.

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5. Address Decoding

PI7C7100 uses three address ranges that control I/O and memory transaction forwarding. These address ranges are defined by base and limit address registers in the configuration space. This chapter describes these address ranges, as well as ISA-mode and VGA-addressing support.

5.1 Address Ranges

PI7C7100 uses the following address ranges that determine which I/O and memory transactions are forwarded from

the primary PCI bus to the secondary PCI bus, and from the secondary bus to the primary bus:

• Two 32-bit I/O address ranges

• Two 32-bit memory-mapped I/O (non-prefetchable memory) ranges

• Two 32-bit prefetchable memory address ranges Transactions falling within these ranges are forwarded downstream from the primary PCI bus to the two secondary PCI

buses. Transactions falling outside these ranges are forwarded upstream from the two secondary PCI buses to the primary PCI bus.

No address translation is required in PI7C7100. The addresses that are not marked for downstream are always forwarded upstream. However, if an address of a transaction initiated from S1 bus is located in the marked address range for downstream in S2 bus and not in the marked address range for downstream in S1 bus, the transaction will be forwarded to S2 bus instead of primary bus. By the same token, if an address of a transaction initiated from S2 bus is located in the marked address range for downstream in S1 bus and not in the marked address range for downstream in S2 bus, the transaction will be forwarded to S1 bus instead of primary bus.

5.2 I/O Address Decoding

PI7C7100 uses the following mechanisms that are defined in the configuration space to specify the I/O address space for downstream and upstream forwarding:

• I/O base and limit address registers

• The ISA enable bit

• The VGA mode bit

• The VGA snoop bit This section provides information on the I/O address registers and ISA mode.

Section 5.4 provides information on the VGA modes. To enable downstream forwarding of I/O transactions, the I/O enable bit must be set in the command register in

configuration space. All I/O transactions initiated on the primary bus will be ignored if the I/O enable bit is not set. To enable upstream forwarding of I/O transactions, the master enable bit must be set in the command register. If the masterenable bit is not set, PI7C7100 ignores all I/O and memory transactions initiated on the secondary bus. The masterenable bit also allows upstream forwarding of memory transactions if it is set.

CAUTION

If any configuration state affecting I/O transaction forwarding is changed by a configuration write operation on the primary bus at the same time that I/O transactions are ongoing on the secondary bus, PI7C7100 response to the secondary bus I/O transactions is not predictable. Configure the I/O base and limit address registers, ISA enable bit, VGA mode bit, and VGA snoop bit before setting I/O enable and master enable bits, and change them subsequently only when the primary and secondary PCI buses are idle.

5.2.1 I/O Base and Limit Address Registers

PI7C7100 implements one set of I/O base and limit address registers in configuration space that define an I/O address range per port downstream forwarding. PI7C7100 supports 32-bit I/O addressing, which allows I/O addresses downstream of PI7C7100 to be mapped anywhere in a 4GB I/O address space.

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I/O transactions with addresses that fall inside the range defined by the I/O base and limit registers are forwarded downstream from the primary PCI bus to the secondary PCI bus. I/O transactions with addresses that fall outside this range are forwarded upstream from the secondary PCI bus to the primary PCI bus.

The I/O range can be turned off by setting the I/O base address to a value greater than that of the I/O limit address. When the I/O range is turned off, all I/O transactions are forwarded upstream, and no I/O transactions are forwarded downstream. The I/O range has a minimum granularity of 4KB and is aligned on a 4KB boundary. The maximum I/O range is 4GB in size. The I/O base register consists of an 8-bit field at configuration address 1Ch, and a 16-bit field at address 30h. The top 4 bits of the 8-bit field define bits [15:12] of the I/O base address. The bottom 4 bits read only as 1h to indicate that PI7C7100 supports 32-bit I/O addressing. Bits [11:0] of the base address are assumed to be 0, which naturally aligns the base address to a 4KB boundary. The 16 bits contained in the I/O base upper 16 bits register at configuration offset 30h define AD[31:16] of the I/O base address. All 16 bits are read/write. After primary bus reset or chip reset, the value of the I/O base address is initialized to 0000 0000h.

The I/O limit register consists of an 8-bit field at configuration offset 1Dh and a 16-bit field at offset 32h. The top 4 bits of the 8-bit field define bits [15:12] of the I/O limit address. The bottom 4 bits read only as 1h to indicate that 32-bit I/O addressing is supported. Bits [11:0] of the limit address are assumed to be FFFh, which naturally aligns the limit address to the top of a 4KB I/O address block. The 16 bits contained in the I/O limit upper 16 bits register at configuration offset 32h define AD[31:16] of the I/O limit address. All 16 bits are read/write. After primary bus reset or chip reset, the value of the I/O limit address is reset to 0000 0FFFh.

Note: The initial states of the I/O base and I/O limit address registers define an I/O range of 0000 0000h to 0000 0FFFh, which is the bottom 4KB of I/O space. Write these registers with their appropriate values before setting either the I/O enable bit or the master enable bit in the command register in configuration space.

5.2.2 ISA Mode

PI7C7100 supports ISA mode by providing an ISA enable bit in the bridge control register in configuration space. ISA mode modifies the response of PI7C7100 inside the I/O address range in order to support mapping of I/O space in the presence of an ISA bus in the system. This bit only affects the response of PI7C7100 when the transaction falls inside the address range defined by the I/O base and limit address registers, and only when this address also falls inside the first 64KB of I/O space (address bits [31:16] are 0000h).

When the ISA enable bit is set, PI7C7100 does not forward downstream any I/O transactions addressing the top 768 bytes of each aligned 1KB block. Only those transactions addressing the bottom 256 bytes of an aligned 1KB block inside the base and limit I/O address range are forwarded downstream. Transactions above the 64KB I/O address boundary are forwarded as defined by the address range defined by the I/O base and limit registers.

Accordingly, if the ISA enable bit is set, PI7C7100 forwards upstream those I/O transactions addressing the top 768 bytes of each aligned 1KB block within the first 64KB of I/O space. The master enable bit in the command configuration register must also be set to enable upstream forwarding. All other I/O transactions initiated on the secondary bus are forwarded upstream only if they fall outside the I/O address range.

When the ISA enable bit is set, devices downstream of PI7C7100 can have I/O space mapped into the first 256 bytes of each 1KB chunk below the 64KB boundary, or anywhere in I/O space above the 64KB boundary.

5.3 Memory Address Decoding

PI7C7100 has three mechanisms for defining memory address ranges for forwarding of memory transactions:

• Memory-mapped I/O base and limit address registers

• Prefetchable memory base and limit address registers

• VGA mode

This section describes the first two mechanisms. Section 5.4.1 describes VGA mode. To enable downstream forwarding of memory transactions, the memory enable bit must be set in the command register

in configuration space. To enable upstream forwarding of memory transactions, the master-enable bit must be set in the command register. The master-enable bit also allows upstream forwarding of I/O transactions if it is set.

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CAUTION

If any configuration state affecting memory transaction forwarding is changed by a configuration write operation on the primary bus at the same time that memory transactions are ongoing on the secondary bus, response to the secondary bus memory transactions is not predictable. Configure the memory-mapped I/ O base and limit address registers, prefetchable memory base and limit address registers, and VGA mode bit before setting the memory enable and master enable bits, and change them subsequently only when the primary and secondary PCI buses are idle.

5.3.1 Memory-Mapped I/O Base and Limit Address Registers

Memory-mapped I/O is also referred to as non-prefetchable memory. Memory addresses that cannot automatically be prefetched but that can be conditionally pre-fetched based on command type should be mapped into this space. Read transactions to non-prefetchable space may exhibit side effects; this space may have non-memory-like behavior. PI7C7100 pre-fetches in this space only if the memory read line or memory read multiple commands are used; transactions using the memory read command are limited to a single data transfer.

The memory-mapped I/O base address and memory-mapped I/O limit address registers define an address range that PI7C7100 uses to determine when to forward memory commands. PI7C7100 forwards a memory transaction from the primary to the secondary interface if the transaction address falls within the memory-mapped I/O address range. PI7C7100 ignores memory transactions initiated on the secondary interface that fall into this address range. Any transactions that fall outside this address range are ignored on the primary interface and are forwarded upstream from the secondary interface (provided that they do not fall into the prefetchable memory range or are not forwarded downstream by the VGA mechanism).

The memory-mapped I/O range supports 32-bit addressing only. The PCI-to-PCI Bridge Architecture Specification does not provide for 64-bit addressing in the memory-mapped I/O space. The memory-mapped I/O address range has a granularity and alignment of 1MB. The maximum memory-mapped I/O address range is 4GB.

The memory-mapped I/O address range is defined by a 16-bit memory-mapped I/O base address register at configuration offset 20h and by a 16-bit memory-mapped I/O limit address register at offset 22h. The top 12 bits of each of these registers correspond to bits [31:20] of the memory address. The low 4 bits are hardwired to 0. The lowest 20 bits of the memorymapped I/O base address are assumed to be 0 0000h, which results in a natural alignment to a 1MB boundary. The lowest 20 bits of the memory-mapped I/O limit address are assumed to be F FFFFh, which results in an alignment to the top of a 1MB block.

Note: The initial state of the memory-mapped I/O base address register is 0000 0000h. The initial state of the memorymapped I/O limit address register is 000F FFFFh. Note that the initial states of these registers define a memory-mapped I/O range at the bottom 1MB block of memory. Write these registers with their appropriate values before setting either the memory enable bit or the master enable bit in the command register in configuration space.

To turn off the memory-mapped I/O address range, write the memory-mapped I/O base address register with a value greater than that of the memory-mapped I/O limit address register.

5.3.2 Prefetchable Memory Base and Limit Address Registers

Locations accessed in the prefetchable memory address range must have true memory-like behavior and must not exhibit side effects when read. This means that extra reads to a prefetchable memory location must have no side effects. PI7C7100 pre-fetches for all types of memory read commands in this address space.

The prefetchable memory base address and prefetchable memory limit address registers define an address range that PI7C7100 uses to determine when to forward memory commands. PI7C7100 forwards a memory transaction from the primary to the secondary interface if the transaction address falls within the prefetchable memory address range. PI7C7100 ignores memory transactions initiated on the secondary interface that fall into this address range. PI7C7100 does not respond to any transactions that fall outside this address range on the primary interface and forwards those transactions upstream from the secondary interface (provided that they do not fall into the memory-mapped I/O range or are not forwarded by the VGA mechanism).

The prefetchable memory range supports 64-bit addressing and provides additional registers to define the upper 32 bits of the memory address range, the prefetchable memory base address upper 32 bits register, and the prefetchable memory limit address upper 32 bits register. For address comparison, a single address cycle (32-bit address) prefetchable memory transaction is treated like a 64-bit address transaction where the upper 32 bits of the address are equal to 0. This upper

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32-bit value of 0 is compared to the prefetchable memory base address upper 32 bits register and the prefetchable memory limit address upper 32 bits register. The prefetchable memory base address upper 32 bits register must be 0 to pass any single address cycle transactions downstream.

Prefetchable memory address range has a granularity and alignment of 1 MB. Maximum memory address range is 4GB when 32-bit addressing is being used.

Prefetchable memory address range is defined by a 16-bit prefetchable memory base address register at configuration offset 24h and by a 16-bit prefetchable memory limit address register at offset 26h. The top 12 bits of each of these registers correspond to bits [31:20] of the memory address. The lowest 4 bits are hardwired to 1h. The lowest 20 bits of the prefetchable memory base address are assumed to be 0 0000h, which results in a natural alignment to a 1MB boundary. The lowest 20 bits of the prefetchable memory limit address are assumed to be FFFFFh, which results in an alignment to the top of a 1MB block.

Note: The initial state of the prefetchable memory base address register is 0000 0000h. The initial state of the prefetchable memory limit address register is 000F FFFFh. Note that the initial states of these registers define a prefetchable memory range at the bottom 1MB block of memory. Write these registers with their appropriate values before setting either the memory enable bit or the master enable bit in the command register in configuration space.

To turn off the prefetchable memory address range, write the prefetchable memory base address register with a value greater than that of the prefetchable memory limit address register. The entire base value must be greater than the entire limit value, meaning that the upper 32 bits must be considered. Therefore, to disable the address range, the upper 32 bits registers can both be set to the same value, while the lower base register is set greater than the lower limit register. Otherwise, the upper 32-bit base must be greater than the upper 32-bit limit.

5.4 VGA Support

PI7C7100 provides two modes for VGA support:

• VGA mode, supporting VGA-compatible addressing

• VGA snoop mode, supporting VGA palette forwarding

5.4.1 VGA Mode

When a VGA-compatible device exists downstream from PI7C7100, set the VGA mode bit in the bridge control register in configuration space to enable VGA mode. When PI7C7100 is operating in VGA mode, it forwards downstream those transactions addressing the VGA frame buffer memory and VGA I/O registers, regardless of the values of the base and limit address registers. PI7C7100 ignores transactions initiated on the secondary interface addressing these locations.

The VGA frame buffer consists of the following memory address range:

000A 0000h–000B FFFFh

Read transactions to frame buffer memory are treated as non-prefetchable. PI7C7100 requests only a single data transfer from the target, and read byte enable bits are forwarded to the target bus.

The VGA I/O addresses are in the range of 3B0h–3BBh and 3C0h–3DFh I/O. These I/O addresses are aliases every 1KB throughout the first 64KB of I/O space. This means that address bits <15:10> are not decoded and can be any value, while address bits [31:16] must be all 0s. VGA BIOS addresses starting at C0000h are not decoded in VGA mode.

5.4.2 VGA Snoop Mode

PI7C7100 provides VGA snoop mode, allowing for VGA palette write transactions to be forwarded downstream. This mode is used when a graphics device downstream from PI7C7100 needs to snoop or respond to VGA palette write transactions. To enable the mode, set the VGA snoop bit in the command register in configuration space. Note that PI7C7100 claims VGA palette write transactions by asserting DEVSEL# in VGA snoop mode.

When VGA snoop bit is set, PI7C7100 forwards downstream transactions within the 3C6h, 3C8h and 3C9h I/O addresses space. Note that these addresses are also forwarded as part of the VGA compatibility mode previously described. Again, address bits <15:10> are not decoded, while address bits <31:16> must be equal to 0, which means that these addresses are aliases every 1KB throughout the first 64KB of I/O space.

Note: If both the VGA mode bit and the VGA snoop bit are set, PI7C7100 behaves in the same way as if only the VGA mode bit were set.

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6. Transaction Ordering

To maintain data coherency and consistency, PI7C7100 complies with the ordering rules set forth in the PCI Local Bus Specification, Revision 2.1, for transactions crossing the bridge. This chapter describes the ordering rules that control transaction forwarding across PI7C7100.

6.1 Transactions Governed by Ordering Rules

Ordering relationships are established for the following classes of transactions crossing PI7C7100:

• Posted write transactions, comprised of memory write and memory write and invalidate transactions.

Posted write transactions complete at the source before they complete at the destination; that is, data is written into intermediate data buffers before it reaches the target.

• Delayed write request transactions, comprised of I/O write and configuration write transactions.

Delayed write requests are terminated by target retry on the initiator bus and are queued in the delayed transaction queue. A delayed write transaction must complete on the target bus before it completes on the initiator bus.

• Delayed write completion transactions, comprised of I/O write and configuration write transactions.

Delayed write completion transactions complete on the target bus, and the target response is queued in the buffers. A delayed write completion transaction proceeds in the direction opposite that of the original delayed write request; that is, a delayed write completion transaction proceeds from the target bus to the initiator bus.

• Delayed read request transactions, comprised of all memory read, I/O read, and configuration read

transactions.

Delayed read requests are terminated by target retry on the initiator bus and are queued in the delayed transaction queue.

• Delayed read completion transactions, comprised of all memory read, I/O read, & configuration read

transactions.

Delayed read completion transactions complete on the target bus, and the read data is queued in the read data buffers. A delayed read completion transaction proceeds in the direction opposite that of the original delayed read request; that is, a delayed read completion transaction proceeds from the target bus to the initiator bus.

PI7C7100 does not combine or merge write transactions:

• PI7C7100 does not combine separate write transactions into a single write transaction—this optimization is best

implemented in the originating master.

• PI7C7100 does not merge bytes on separate masked write transactions to the same DWORD address—this

optimization is also best implemented in the originating master.

• PI7C7100 does not collapse sequential write transactions to the same address into a single write transaction—the

PCI Local Bus Specification does not permit this combining of transactions.

6.2 General Ordering Guidelines

Independent transactions on primary and secondary buses have a relationship only when those transactions cross PI7C7100.

The following general ordering guidelines govern transactions crossing PI7C7100:

• The ordering relationship of a transaction with respect to other transactions is determined when the transaction

completes, that is, when a transaction ends with a termination other than target retry.

• Requests terminated with target retry can be accepted and completed in any order with respect to other transac-

tions that have been terminated with target retry. If the order of completion of delayed requests is important, the initiator should not start a second delayed transaction until the first one has been completed. If more than one delayed transaction is initiated, the initiator should repeat all delayed transaction requests, using some fairness algorithm. Repeating a delayed transaction cannot be contingent on completion of another delayed transaction. Otherwise, a deadlock can occur.

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Note: The superscript accompanying some of the table entries refers to any applicable ordering rule listed in this section. Many entries are not governed by these ordering rules; therefore, the implementation can choose whether or not the transactions pass each other.

The entries without superscripts reflect the PI7C7100’s implementation choices. The following ordering rules describe the transaction relationships. Each ordering rule is followed by an explanation, and

the ordering rules are referred to by number in Table 6–1. These ordering rules apply to posted write transactions, delayed write and read requests, and delayed write and read completion transactions crossing PI7C7100 in the same direction. Note that delayed completion transactions cross PI7C7100 in the direction opposite that of the corresponding delayed requests.

1. Posted write transactions must complete on the target bus in the order in which they were received on the initiator

bus. The subsequent posted write transaction can be setting a flag that covers the data in the first posted write transaction; if the second transaction were to complete before the first transaction, a device checking the flag could subsequently consume stale data.

2. A delayed read request traveling in the same direction as a previously queued posted write transaction must push

the posted write data ahead of it. The posted write transaction must complete on the target bus before the delayed read request can be attempted on the target bus. The read transaction can be to the same location as the write data, so if the read transaction were to pass the write transaction, it would return stale data.

3. A delayed read completion must ‘‘pull’’ ahead of previously queued posted write data traveling in the same direction.

In this case, the read data is traveling in the same direction as the write data, and the initiator of the read transaction is on the same side of PI7C7100 as the target of the write transaction. The posted write transaction must complete to the target before the read data is returned to the initiator. The read transaction can be a reading to a status register of the initiator of the posted write data and therefore should not complete until the write transaction is complete.

4. Delayed write requests cannot pass previously queued posted write data. For posted memory write transactions, the

delayed write transaction can set a flag that covers the data in the posted write transaction. If the delayed write request were to complete before the earlier posted write transaction, a device checking the flag could subsequently consume stale data.

6.3 Ordering Rules

Table 6–1 shows the ordering relationships of all the transactions and refers by number to the ordering rules that follow.

Table 6-1. Summary of Transaction Ordering

• Write transactions flowing in one direction have no ordering requirements with respect to write transactions flowing in the other direction. PI7C7100 can accept posted write transactions on both interfaces at the same time, as well as initiate posted write transactions on both interfaces at the same time.

• The acceptance of a posted memory write transaction as a target can never be contingent on the completion of a non-locked, non-posted transaction as a master. This is true for PI7C7100 and must also be true for other bus agents. Otherwise, a deadlock can occur.

• PI7C7100 accepts posted write transactions, regardless of the state of completion of any delayed transactions being forwarded across PI7C7100.

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5. Posted write transactions must be given opportunities to pass delayed read and write requests and completions. Otherwise, deadlocks may occur when some bridges which support delayed transactions and other bridges which do not support delayed transactions are being used in the same system. A fairness algorithm is used to arbitrate between the posted write queue and the delayed transaction queue.

6.4 Data Synchronization

Data synchronization refers to the relationship between interrupt signaling and data delivery. The PCI Local Bus Specification, Revision 2.1, provides the following alternative methods for synchronizing data and interrupts:

• The device signaling the interrupt performs a read of the data just written (software).

• The device driver performs a read operation to any register in the interrupting device before accessing data

written by the device (software).

• System hardware guarantees that write buffers are flushed before interrupts are forwarded. PI7C7100 does not have a hardware mechanism to guarantee data synchronization for posted write transactions.

Therefore, all posted write transactions must be followed by a read operation, either from the device to the location just written (or some other location along the same path), or from the device driver to one of the device registers.

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7. Error Handling

PI7C7100 checks, forwards, and generates parity on both the primary and secondary interfaces. To maintain transparency, PI7C7100 always tries to forward the existing parity condition on one bus to the other bus, along with address and data. PI7C100 always attempts to be transparent when reporting errors, but this is not always possible, given the presence of posted data and delayed transactions.

To support error reporting on the PCI bus, PI7C7100 implements the following:

• PERR# and SERR# signals on both the primary and secondary interfaces

• Primary status and secondary status registers

• The device-specific P_SERR# event disable register

This chapter provides detailed information about how PI7C7100 handles errors. It also describes error status reporting and error operation disabling.

7.1 Address Parity Errors

PI7C7100 checks address parity for all transactions on both buses, for all address and all bus commands. When PI7C7100 detects an address parity error on the primary interface, the following events occur:

• If the parity error response bit is set in the command register, PI7C7100 does not claim the transaction with

P_DEVSEL#; this may allow the transaction to terminate in a master abort. If parity error response bit is not set, PI7C7100 proceeds normally and accepts the transaction if it is directed to or across PI7C7100.

• PI7C7100 sets the detected parity error bit in the status register.

• PI7C7100 asserts P_SERR# and sets signaled system error bit in the status register, if both the following conditions

are met:

- The SERR# enable bit is set in the command register.

- The parity error response bit is set in the command register.

When PI7C7100 detects an address parity error on the secondary interface, the following events occur:

• If the parity error response bit is set in the bridge control register, PI7C7100 does not claim the transaction with

S1_DEVSEL# or S2_DEVSEL#; this may allow the transaction to terminate in a master abort. If parity error response bit is not set, PI7C7100 proceeds normally and accepts transaction if it is directed to or across PI7C7100.

• PI7C7100 sets the detected parity error bit in the secondary status register.

• PI7C7100 asserts P_SERR# and sets signaled system error bit in status register, if both of the following

conditions are met:

- The SERR# enable bit is set in the command register.

- The parity error response bit is set in the bridge control register.

7.2 Data Parity Errors

When forwarding transactions, PI7C7100 attempts to pass the data parity condition from one interface to the other unchanged, whenever possible, to allow the master and target devices to handle the error condition.

The following sections describe, for each type of transaction, the sequence of events that occurs when a parity error is detected and the way in which the parity condition is forwarded across PI7C7100.

7.2.1 Configuration Write Transactions to Configuration Space

When PI7C7100 detects a data parity error during a Type 0 configuration write transaction to PI7C7100 configuration space, the following events occur:

• If the parity error response bit is set in the command register, PI7C7100 asserts P_TRDY# and writes the data to the configuration register. PI7C7100 also asserts P_PERR#. If the parity error response bit is not set, PI7C7100 does not assert P_PERR#.

• PI7C7100 sets the detected parity error bit in the status register, regardless of the state of the parity error response bit.

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7.2.2 Read Transactions

When PI7C7100 detects a parity error during a read transaction, the target drives data and data parity, and the initiator checks parity and conditionally asserts PERR#.

For downstream transactions, when PI7C7100 detects a read data parity error on the secondary bus, the following events occur:

• PI7C7100 asserts S_PERR# two cycles following the data transfer, if the secondary interface parity error re-

sponse bit is set in the bridge control register.

• PI7C7100 sets the detected parity error bit in the secondary status register.

• PI7C7100 sets the data parity detected bit in the secondary status register, if the secondary interface parity error

response bit is set in the bridge control register.

• PI7C7100 forwards the bad parity with the data back to the initiator on the primary bus.

If the data with the bad parity is pre-fetched and is not read by the initiator on the primary bus, the data is discarded and the data with bad parity is not returned to the initiator.

• PI7C7100 completes the transaction normally. For upstream transactions, when PI7C7100 detects a read data parity error on the primary bus, the following events occur:

• PI7C7100 asserts P_PERR# two cycles following the data transfer, if the primary interface parity error

response bit is set in the command register.

• PI7C7100 sets the detected parity error bit in the primary status register.

• PI7C7100 sets the data parity detected bit in the primary status register, if the primary interface parity-error-

response bit is set in the command register.

• PI7C7100 forwards the bad parity with the data back to the initiator on the secondary bus.

If the data with the bad parity is pre-fetched and is not read by the initiator on the secondary bus, the data is discarded and the data with bad parity is not returned to the initiator.

• PI7C7100 completes the transaction normally.

PI7C7100 returns to the initiator the data and parity that was received from the target. When the initiator detects a parity error on this read data and is enabled to report it, the initiator asserts PERR# two cycles after the data transfer occurs. It is assumed that the initiator takes responsibility for handling a parity error condition; therefore, when PI7C7100 detects PERR# asserted while returning read data to the initiator, PI7C7100 does not take any further action and completes the transaction normally.

7.2.3 Delayed Write Transactions

When PI7C7100 detects a data parity error during a delayed write transaction, the initiator drives data and data parity, and the target checks parity and conditionally asserts PERR#.

For delayed write transactions, a parity error can occur at the following times:

• During the original delayed write request transaction

• When the initiator repeats the delayed write request transaction

• When PI7C7100 completes the delayed write transaction to the target When a delayed write transaction is normally queued, the address, command, address parity, data, byte enable bits,

and data parity are all captured and a target retry is returned to the initiator. When PI7C7100 detects a parity error on the write data for the initial delayed write request transaction, the following events occur:

• If the parity-error-response bit corresponding to the initiator bus is set, PI7C7100 asserts TRDY# to the initiator

and the transaction is not queued. If multiple data phases are requested, STOP# is also asserted to cause a target disconnect. Two cycles after the data transfer, PI7C7100 also asserts PERR#.

If the parity-error-response bit is not set, PI7C7100 returns a target retry. It queues the transaction as usual. PI7C7100 does not assert PERR#. In this case, the initiator repeats the transaction.

• PI7C7100 sets the detected-parity-error bit in the status register corresponding to the initiator bus, regardless

of the state of the parity-error-response bit.

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Note: If parity checking is turned off and data parity errors have occurred for queued or subsequent delayed write

transactions on the initiator bus, it is possible that the initiator’s re-attempts of the write transaction may not match the original queued delayed write information contained in the delayed transaction queue. In this case, a master timeout

condition may occur, possibly resulting in a system error (P_SERR# assertion). For downstream transactions, when PI7C7100 is delivering data to the target on the secondary bus and S_PERR# is

asserted by the target, the following events occur:

• PI7C7100 sets the secondary interface data parity detected bit in the secondary status register, if the

secondary parity error response bit is set in the bridge control register.

• PI7C7100 captures the parity error condition to forward it back to the initiator on the primary bus.

Similarly, for upstream transactions, when PI7C7100 is delivering data to the target on the primary bus and P_PERR# is asserted by the target, the following events occur:

• PI7C7100 sets the primary interface data-parity-detected bit in the status register, if the primary parity-error-

response bit is set in the command register.

• PI7C7100 captures the parity error condition to forward it back to the initiator on the secondary bus.

A delayed write transaction is completed on the initiator bus when the initiator repeats the write transaction with the same address, command, data, and byte enable bits as the delayed write command that is at the head of the posted data queue. Note that the parity bit is not compared when determining whether the transaction matches those in the delayed transaction queues.

Two cases must be considered:

• When parity error is detected on the initiator bus on a subsequent re-attempt of the transaction and was not

detected on the target bus

• When parity error is forwarded back from the target bus

For downstream delayed write transactions, when the parity error is detected on the initiator bus and PI7C7100 has write status to return, the following events occur:

• PI7C7100 first asserts P_TRDY# and then asserts P_PERR# two cycles later, if the primary interface parity-

error-response bit is set in the command register.

• PI7C7100 sets the primary interface parity-error-detected bit in the status register.

• Because there was not an exact data and parity match, the write status is not returned and the transaction

remains in the queue.

Similarly, for upstream delayed write transactions, when the parity error is detected on the initiator bus and PI7C7100 has write status to return, the following events occur:

• PI7C7100 first asserts S1_TRDY# or S2_TRDY# and then asserts S_PERR# two cycles later, if the secondary

interface parity-error-response bit is set in the bridge control register (offset 3Ch).

• PI7C7100 sets the secondary interface parity-error-detected bit in the secondary status register.

• Because there was not an exact data and parity match, the write status is not returned and the transaction

remains in the queue.

For downstream transactions, where the parity error is being passed back from the target bus and the parity error condition was not originally detected on the initiator bus, the following events occur:

• PI7C7100 asserts P_PERR# two cycles after the data transfer, if the following are both true:

- The parity-error-response bit is set in the command register of the primary interface.

- The parity-error-response bit is set in the bridge control register of the secondary interface.

• PI7C7100 completes the transaction normally.

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For upstream transactions, when the parity error is being passed back from the target bus and the parity error condition was not originally detected on the initiator bus, the following events occur:

• PI7C7100 asserts S_PERR# two cycles after the data transfer, if the following are both true:

- The parity error response bit is set in the command register of the primary interface.

- The parity error response bit is set in the bridge control register of the secondary interface.

• PI7C7100 completes the transaction normally.

7.2.4 Posted Write Transactions

During downstream posted write transactions, when PI7C7100 responds as a target, it detects a data parity error on the initiator (primary) bus, the following events occur:

• PI7C7100 asserts P_PERR# two cycles after the data transfer, if the parity error response bit is set in the

command register of primary interface.

• PI7C7100 sets the parity error detected bit in the status register of the primary interface.

• PI7C7100 captures and forwards the bad parity condition to the secondary bus.

• PI7C7100 completes the transaction normally. Similarly, during upstream posted write transactions, when PI7C7100 responds as a target, it detects a data parity error

on the initiator (secondary) bus, the following events occur:

• PI7C7100 asserts S_PERR# two cycles after the data transfer, if the parity error response bit is set in the bridge

control register of the secondary interface.

• PI7C7100 sets the parity error detected bit in the status register of the secondary interface.

• PI7C7100 captures and forwards the bad parity condition to the primary bus.

• PI7C7100 completes the transaction normally. During downstream write transactions, when a data parity error is reported on the target (secondary) bus by the target’s

assertion of S_PERR#, the following events occur:

• PI7C7100 sets the data parity detected bit in the status register of secondary interface, if the parity error

response bit is set in the bridge control register of the secondary interface.

• PI7C7100 asserts P_SERR# and sets the signaled system error bit in the status register, if all the following

conditions are met:

- The SERR# enable bit is set in the command register.

- The posted write parity error bit of P_SERR# event disable register is not set.

- The parity error response bit is set in the bridge control register of the secondary interface.

- The parity error response bit is set in the command register of the primary interface.

- PI7C7100 has not detected the parity error on the primary (initiator) bus which the parity error is not forwarded from the primary bus to the secondary bus.

During upstream write transactions, when a data parity error is reported on the target (primary) bus by the target’s assertion of P_PERR#, the following events occur:

• PI7C7100 sets the data parity detected bit in the status register, if the parity error response bit is set in the

command register of the primary interface.

• PI7C7100 asserts P_SERR# and sets the signaled system error bit in the status register, if all the following

conditions are met:

- The SERR# enable bit is set in the command register.

- The parity error response bit is set in the bridge control register of the secondary interface.

- The parity error response bit is set in the command register of the primary interface.

- PI7C7100 has not detected the parity error on the secondary (initiator) bus which the parity error is not forwarded from the secondary bus to the primary bus.

Assertion of P_SERR# is used to signal the parity error condition when the initiator does not know that the error occurred.

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1etirwdetsoPmaertsnwoDyramirPx/x 0etirwdetsoPmaertsnwoDyradnoceSx/x 0etirwdetsoPmaertspUyramirPx/x 0etirwdetsoPmaertspUyradnoceSx/x

1etirwdeyaleDmaertsnwoDyramirPx/x 0etirwdeyaleDmaertsnwoDyradnoceSx/x 0etirwdeyaleDmaertspUyramirPx/x 0etirwdeyaleDmaertspUyradnoceSx/x

x =don’t care

Table 7–1 shows setting the detected parity error bit in the status register, corresponding to the primary interface. This bit is set when PI7C7100 detects a parity error on the primary interface.

Table 7–1 Setting the Primary Interface Detected Parity Error Bit

Because the data has already been delivered with no errors, there is no other way to signal this information back to the initiator.

If the parity error has forwarded from the initiating bus to the target bus, P_SERR# will not be asserted.

7.3 Data Parity Error Reporting Summary

In the previous sections, the responses of PI7C7100 to data parity errors are presented according to the type of transaction in progress. This section organizes the responses of PI7C7100 to data parity errors according to the status bits that PI7C7100 sets and the signals that it asserts.

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3-Port PCI Bridge

ADVANCE INFORMATION

x =don’t care

Table 7–3 shows setting data parity detected bit in the primary interface’s status register. This bit is set under the following conditions:

• PI7C7100 must be a master on the primary bus.

• The parity error response bit in the command register, corresponding to the primary interface, must be set.

• The P_PERR# signal is detected asserted or a parity error is detected on the primary bus.

atadyramirP

tibytirap

noitcasnarT

epyT

noitceriD

sawrorreerehwsuB

detceted

yradnoceS/yramirP

stibesnopserrorreytirap

0daeRmaertsnwoDyramirPx/x

0daeRmaertsnwoDyradnoceSx/x 1daeRmaertspUyramirPx/1 0daeRmaertspUyradnoceSx/x 0etirwdetsoPmaertsnwoDyramirPx/x 0etirwdetsoPmaertsnwoDyradnoceSx/x 1etirwdetsoPmaertspUyramirPx/1 0etirwdetsoPmaertspUyradnoceSx/x 0etirwdeyaleDmaertsnwoDyramirPx/x 0etirwdeyaleDmaertsnwoDyradnoceSx/x 1etirwdeyaleDmaertspUyramirPx/1 0etirwdeyaleDmaertspUyradnoceSx/x

Table 7–3. Setting Primary Interface Data Parity Detected Bit

detcetedyradnoceS

tibrorreytirap

noitcasnarT

epyT

noitceriD

rorreerehwsuB

detcetedsaw

yradnoceS/yramirP

stibesnopserrorreytirap

0daeRmaertsnwoDyramirPx/x

1daeRmaertsnwoDyradnoceSx/x 0daeRmaertspUyramirPx/x 0daeRmaertspUyradnoceSx/x 0etirwdetsoPmaertsnwoDyramirPx/x 0etirwdetsoPmaertsnwoDyradnoceSx/x 0etirwdetsoPmaertspUyramirPx/x

1etirwdetsoPmaertspUyradnoceSx/x 0etirwdeyaleDmaertsnwoDyramirPx/x 0etirwdeyaleDmaertsnwoDyradnoceSx/x 0etirwdeyaleDmaertspUyramirPx/x

1etirwdeyaleDmaertspUyradnoceSx/x

Table 7–2. Setting Secondary Interface Detected Parity Error Bit

Table 7–2 shows setting the detected parity error bit in the secondary status register, corresponding to the secondary interface. This bit is set when PI7C7100 detects a parity error on the secondary interface.

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3-Port PCI Bridge

ADVANCE INFORMATION

atadyradnoceS

tibdetcetedytirap

noitcasnarT

epyT

noitceriD

sawrorreerehwsuB

detceted

yradnoceS/yramirP

stibesnopserrorreytirap

0daeRmaertsnwoDyramirPx/x

1daeRmaertsnwoDyradnoceS1/x 0daeRmaertspUyramirPx/x 0daeRmaertspUyradnoceSx/x 0etirwdetsoPmaertsnwoDyramirPx/x

1etirwdetsoPmaertsnwoDyradnoceS1/x 0etirwdetsoPmaertspUyramirPx/x 0etirwdetsoPmaertspUyradnoceSx/x 0etirwdeyaleDmaertsnwoDyramirPx/x

1etirwdeyaleDmaertsnwoDyradnoceS1/x 0etirwdeyaleDmaertspUyramirPx/x 0etirwdeyaleDmaertspUyradnoceSx/x

x =don’t care

Table 7–4. Setting Secondary Interface Data Parity Detected Bit

Table 7–4 shows setting the data parity detected bit in the status register of secondary interface. This bit is set under the following conditions:

• The PI7C7100 must be a master on the secondary bus.

• The parity error response bit must be set in the bridge control register of secondary interface.

• The S_PERR# signal is detected asserted or a parity error is detected on the secondary bus.

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3-Port PCI Bridge

ADVANCE INFORMATION

Table 7–5. Assertion of P_PERR#

#RREP_P

noitcasnarT

epyT

noitceriD

sawrorreerehwsuB

detceted

yradnoceS/yramirP

stibesnopserrorreytirap

)detressa-ed(1daeRmaertsnwoDyramirPx/x

1daeRmaertsnwoDyradnoceSx/x

)detressa(0daeRmaertspUyramirPx/1 1daeRmaertspUyradnoceSx/x 0etirwdetsoPmaertsnwoDyramirPx/1 1etirwdetsoPmaertsnwoDyradnoceSx/x 1etirwdetsoPmaertspUyramirPx/x 1etirwdetsoPmaertspUyradnoceSx/x 0etirwdeyaleDmaertsnwoDyramirPx/1

etirwdeyaleDmaertsnwoDyradnoceS1/1 1etirwdeyaleDmaertspUyramirPx/x 1etirwdeyaleDmaertspUyradnoceSx/x

x =don’t care

The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.

Table 7–5 shows assertion of P_PERR#. This signal is set under the following conditions:

• PI7C7100 is either the target of a write transaction or the initiator of a read transaction on the primary bus.

• The parity-error-response bit must be set in the command register of primary interface.

• PI7C7100 detects a data parity error on the primary bus or detects S_PERR# asserted during the completion phase of a downstream delayed write transaction on the target (secondary) bus.

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Table 7–6. Assertion of S_PERR#

#RREP_S

noitcasnarT

epyT

noitceriD

rorreerehwsuB

detcetedsaw

yradnoceS/yramirP

stibesnopserrorreytirap

)detressa-ed(1daeRmaertsnwoDyramirPx/x

)detressa(0daeRmaertsnwoDyradnoceS1/x 1daeRmaertspUyramirPx/x 1daeRmaertspUyradnoceSx/x 1etirwdetsoPmaertsnwoDyramirPx/x 1etirwdetsoPmaertsnwoDyradnoceSx/x 1etirwdetsoPmaertspUyramirPx/x 0etirwdetsoPmaertspUyradnoceS1/x 1etirwdeyaleDmaertsnwoDyramirPx/x 1etirwdeyaleDmaertsnwoDyradnoceSx/x

etirwdeyaleDmaertspUyramirP1/1

0etirwdeyaleDmaertspUyradnoceS1/x

x =don’t care

The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.

Table 7–6 shows assertion of S_PERR# that is set under the following conditions:

• PI7C7100 is either the target of a write transaction or the initiator of a read transaction on the secondary bus.

• The parity error response bit must be set in the bridge control register of secondary interface.

• PI7C7100 detects a data parity error on the secondary bus or detects P_PERR# asserted during the completion phase of an upstream delayed write transaction on the target (primary) bus.

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3-Port PCI Bridge

ADVANCE INFORMATION

Table 7–7 shows assertion of P_SERR#. This signal is set under the following conditions:

• PI7C7100 has detected P_PERR# asserted on an upstream posted write transaction or S_PERR# asserted

on a downstream posted write transaction.

• PI7C7100 did not detect the parity error as a target of the posted write transaction.

• The parity error response bit on the command register and the parity error response bit on the bridge control

• The SERR# enable bit must be set in the command register.

Table 7–7. Assertion of P_SERR# for Data Parity Errors

#RRES_P

noitcasnarT

epyT

noitceriD

sawrorreerehwsuB

detceted

yradnoceS/yramirP

stibesnopserrorreytirap

)detressa-ed(1daeRmaertsnwoDyramirPx/x

1daeRmaertsnwoDyradnoceSx/x 1daeRmaertspUyramirPx/x 1daeRmaertspUyradnoceSx/x 1etirwdetsoPmaertsnwoDyramirPx/x

)detressa(etirwdetsoPmaertsnwoDyradnoceS1/1

etirwdetsoPmaertspUyramirP1/1 1etirwdetsoPmaertspUyradnoceSx/x 1etirwdeyaleDmaertsnwoDyramirPx/x 1etirwdeyaleDmaertsnwoDyradnoceSx/x 1etirwdeyaleDmaertspUyramirPx/x 1etirwdeyaleDmaertspUyradnoceSx/x

x =don’t care

The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.

The parity error was detected on the target (primary) bus but not on the initiator (secondary) bus.

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7.4 System Error (SERR#) Reporting

PI7C7100 uses the P_SERR# signal to report conditionally a number of system error conditions in addition to the special case parity error conditions described in Section 7.2.3.

Whenever assertion of P_SERR# is discussed in this document, it is assumed that the following conditions apply:

• For PI7C7100 to assert P_SERR# for any reason, the SERR# enable bit must be set in the command register.

• Whenever PI7C7100 asserts P_SERR#, PI7C7100 must also set the signaled system error bit in the status register. In compliance with the PCI-to-PCI Bridge Architecture Specification, PI7C7100 asserts P_SERR# when it detects the

secondary SERR# input, S_SERR#, asserted and the SERR# forward enable bit is set in the bridge control register. In addition, PI7C7100 also sets the received system error bit in the secondary status register.

PI7C7100 also conditionally asserts P_SERR# for any of the following reasons:

• Target abort detected during posted write transaction

• Master abort detected during posted write transaction

• Posted write data discarded after 224(default) attempts to deliver (224 target retries received)

• Parity error reported on target bus during posted write transaction (see previous section)

• Delayed write data discarded after 224(default) attempts to deliver (224 target retries received)

• Delayed read data cannot be transferred from target after 224(default) attempts (224 target retries received)

• Master timeout on delayed transaction The device-specific P_SERR# status register reports the reason for the assertion of P_SERR#. Most of these events have additional device-specific disable bits in the P_SERR# event disable register that make it

possible to mask out P_SERR# assertion for specific events. The master timeout condition has a SERR# enable bit for that event in the bridge control register and therefore does not have a device-specific disable bit.

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3-Port PCI Bridge

ADVANCE INFORMATION

8. Exclusive Access

This chapter describes the use of the LOCK# signal to implement exclusive access to a target for transactions that cross PI7C7100.

8.1 Concurrent Locks

The primary and secondary bus lock mechanisms operate concurrently except when a locked transaction crosses PI7C7100. A primary master can lock a primary target without affecting the status of the lock on the secondary bus, and vice versa. This means that a primary master can lock a primary target at the same time that a secondary master locks a secondary target.

8.2 Acquiring Exclusive Access across PI7C7100

For any PCI bus, before acquiring access to the LOCK# signal and starting a series of locked transactions, the initiator must first check that both of the following conditions are met:

• The PCI bus must be idle.

• The LOCK# signal must be de-asserted. The initiator leaves the LOCK# signal de-asserted during the address phase and asserts LOCK# one clock cycle later.

Once a data transfer is completed from the target, the target lock has been achieved. Locked transactions can cross PI7C7100 in the downstream and upstream directions, from the primary bus to the

secondary bus and vice versa. When the target resides on another PCI bus, the master must acquire not only the lock on its own PCI bus but also the

lock on every bus between its bus and the target’s bus. When PI7C7100 detects on the primary bus, an initial locked transaction intended for a target on the secondary bus, PI7C7100 samples the address, transaction type, byte enable bits, and parity, as described in Section 4.6.4. It also samples the lock signal. If there is a lock established between 2 ports or the target bus is already locked by another master, then the current lock cycle is retried without forward. Because a target retry is signaled to the initiator, the initiator must relinquish the lock on the primary bus, and therefore the lock is not yet established.

The first locked transaction must be a read transaction. Subsequent locked transactions can be read or write transactions. Posted memory write transactions that are a part of the locked transaction sequence are still posted. Memory read transactions that are a part of the locked transaction sequence are not pre-fetched.

When the locked delayed read request is queued, PI7C7100 does not queue any more transactions until the locked sequence is finished. PI7C7100 signals a target retry to all transactions initiated subsequent to the locked read transaction that are intended for targets on the other side of PI7C7100. PI7C7100 allows any transactions queued before the locked transaction to complete before initiating the locked transaction.

When the locked delayed read request transaction moves to the head of the delayed transaction queue, PI7C7100 initiates the transaction as a locked read transaction by de-asserting LOCK# on the target bus during the first address phase, and by asserting LOCK# one cycle later. If LOCK# is already asserted (used by another initiator), PI7C7100 waits to request access to the secondary bus until LOCK# is de-asserted when the target bus is idle. Note that the existing lock on the target bus could not have crossed PI7C7100. Otherwise, the pending queued locked transaction would not have been queued. When PI7C7100 is able to complete a data transfer with the locked read transaction, the lock is established on the secondary bus.

When the initiator repeats the locked read transaction on the primary bus with the same address, transaction type, and byte enable bits, PI7C7100 transfers the read data back to the initiator, and the lock is then also established on the primary bus.

For PI7C7100 to recognize and respond to the initiator, the initiator’s subsequent attempts of the read transaction must use the locked transaction sequence (de-assert LOCK# during address phase, and assert LOCK# one cycle later). If the LOCK# sequence is not used in subsequent attempts, a master timeout condition may result. When a master timeout condition occurs, SERR# is conditionally asserted (see Section 7.4), the read data and queued read transaction are discarded, and the LOCK# signal is de-asserted on the target bus.

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Once the intended target has been locked, any subsequent locked transactions initiated on the initiator bus that are forwarded by PI7C7100 are driven as locked transactions on the target bus.

When PI7C7100 receives a target abort or a master abort in response to the delayed locked read transaction, this status is passed back to the initiator, and no locks are established on either the target or the initiator bus. PI7C7100 resumes forwarding unlocked transactions in both directions.

8.3 Ending Exclusive Access

After the lock has been acquired on both initiator and target buses, PI7C7100 must maintain the lock on the target bus for any subsequent locked transactions until the initiator relinquishes the lock.

The only time a target-retry causes the lock to be relinquished is on the first transaction of a locked sequence. On subsequent transactions in the sequence, the target retry has no effect on the status of the lock signal.

An established target lock is maintained until the initiator relinquishes the lock. PI7C7100 does not know whether the current transaction is the last one in a sequence of locked transactions until the initiator de-asserts the LOCK# signal at end of the transaction.

When the last locked transaction is a delayed transaction, PI7C7100 has already completed the transaction on the secondary bus. In this example, as soon as PI7C7100 detects that the initiator has relinquished the LOCK# signal by sampling it in the de-asserted state while FRAME# is de-asserted, PI7C7100 de-asserts the LOCK# signal on the target bus as soon as possible. Because of this behavior, LOCK# may not be de-asserted until several cycles after the last locked transaction has been completed on the target bus. As soon as PI7C7100 has de-asserted LOCK# to indicate the end of a sequence of locked transactions, it resumes forwarding unlocked transactions.

When the last locked transaction is a posted write transaction, PI7C7100 de-asserts LOCK# on the target bus at the end of the transaction because the lock was relinquished at the end of the write transaction on the initiator bus.

When PI7C7100 receives a target abort or a master abort in response to a locked delayed transaction, PI7C7100 returns a target abort or a master abort when the initiator repeats the locked transaction. The initiator must then de-assert LOCK# at the end of the transaction. PI7C7100 sets the appropriate status bits, flagging the abnormal target termination condition (see Section 4.8). Normal forwarding of unlocked posted and delayed transactions is resumed.

When PI7C7100 receives a target abort or a master abort in response to a locked posted write transaction, PI7C7100 cannot pass back that status to the initiator. PI7C7100 asserts SERR# on the initiator bus when a target abort or a master abort is received during a locked posted write transaction, if the SERR# enable bit is set in the command register. Signal SERR# is asserted for the master abort condition if the master abort mode bit is set in the bridge control register (see Section 7.4).

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3-Port PCI Bridge

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9. PCI Bus Arbitration

PI7C7100 must arbitrate for use of the primary bus when forwarding upstream transactions. Also, it must arbitrate for use of the secondary bus when forwarding downstream transactions. The arbiter for the primary bus resides external to PI7C7100, typically on the motherboard. For the secondary PCI bus, PI7C7100 implements an internal arbiter. This arbiter can be disabled, and an external arbiter can be used instead. This chapter describes primary and secondary bus arbitration.

9.1 Primary PCI Bus Arbitration

PI7C7100 implements a request output pin, P_REQ#, and a grant input pin, P_GNT#, for primary PCI bus arbitration. PI7C7100 asserts P_REQ# when forwarding transactions upstream; that is, it acts as initiator on the primary PCI bus. As long as at least one pending transaction resides in the queues in the upstream direction, either posted write data or delayed transaction requests, PI7C7100 keeps P_REQ# asserted. However, if a target retry, target disconnect, or a target abort is received in response to a transaction initiated by PI7C7100 on the primary PCI bus, PI7C7100 de-asserts P_REQ# for two PCI clock cycles.

For all cycles through the bridge, P_REQ# is not asserted until the transaction request has been completely queued. When P_GNT# is asserted LOW by the primary bus arbiter after PI7C7100 has asserted P_REQ#, PI7C7100 initiates a

transaction on the primary bus during the next PCI clock cycle. When P_GNT# is asserted to PI7C7100 when P_REQ# is not asserted, PI7C7100 parks P_AD, P_CBE, and P_PAR by driving them to valid logic levels. When the primary bus is parked at PI7C7100 and PI7C7100 has a transaction to initiate on the primary bus, PI7C7100 starts the transaction if P_GNT# was asserted during the previous cycle.

9.2 Secondary PCI Bus Arbitration

PI7C7100 implements an internal secondary PCI bus arbiter. This arbiter supports two sets of eight external masters in addition to PI7C7100. The internal arbiter can be disabled, and an external arbiter can be used instead for secondary bus arbitration.

9.2.1 Secondary Bus Arbitration Using the Internal Arbiter

To use the internal arbiter, the secondary bus arbiter enable pin, S_CFN#, must be tied LOW. PI7C7100 has two sets of eight secondary bus request input pins, S1_REQ#[7:0], S2_REQ#[7:0], and two sets of eight secondary bus output grant pins, S1_GNT#[7:0], S2_GNT#[7:0], to support external secondary bus masters. The secondary bus request and grant signals are connected internally to the arbiter and are not brought out to external pins when S_CFN# is HIGH.

The secondary arbiter supports a 2-sets programmable 2-level rotating algorithm with each set taking care of 8 requests/ grants. Each set of masters can be assigned to a high priority group and a low priority group. The low priority group as a whole represents one entry in the high priority group; that is, if the high priority group consists of n masters, then in at least every n+1 transactions the highest priority is assigned to the low priority group. Priority rotates evenly among the low priority group. Therefore, members of the high priority group can be serviced n transactions out of n+1, while one member of the low priority group is serviced once every n+1 transactions. Figure 9–1 shows an example of an internal arbiter where four masters, including PI7C7100, are in the high priority group, and five masters are in the low priority group. Using this example, if all requests are always asserted, the highest priority rotates among the masters in the following fashion

lpg

Figure 9-1. Secondary Arbiter Example

(high priority members are given in italics, low priority members, in boldface type):

B, m0, m1, m2

, m3,

B, m0, m1, m2

, m4,

B, m0, m1, m2

, m5,

B, m0, m1, m2

, m6,

B, m0, m1, m2

, m7 and so on.

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Each bus master, including PI7C7100, can be configured to be in either the low priority group or the high priority group by setting the corresponding priority bit in the arbiter-control register. The arbiter-control register is located at offset 40h. Each master has a corresponding bit. If the bit is set to 1, the master is assigned to the high priority group. If the bit is set to 0, the master is assigned to the low priority group. If all the masters are assigned to one group, the algorithm defaults to a straight rotating priority among all the masters. After reset, all external masters are assigned to the low priority group, and PI7C7100 is assigned to the high priority group. PI7C7100 receives highest priority on the target bus every other transaction, and priority rotates evenly among the other masters.

Priorities are re-evaluated every time S1_FRAME# or S2_FRAME# is asserted at the start of each new transaction on the secondary PCI bus. From this point until the time that the next transaction starts, the arbiter asserts the grant signal corresponding to the highest priority request that is asserted. If a grant for a particular request is asserted, and a higher priority request subsequently asserts, the arbiter de-asserts the asserted grant signal and asserts the grant corresponding to the new higher priority request on the next PCI clock cycle. When priorities are re-evaluated, the highest priority is assigned to the next highest priority master relative to the master that initiated the previous transaction. The master that initiated the last transaction now has the lowest priority in its group.

If PI7C7100 detects that an initiator has failed to assert S1_FRAME# or S2_FRAME# after 16 cycles of both grant assertion and a secondary idle bus condition, the arbiter de-asserts the grant. That master does not receive any more grants until it de-asserts its request for at least one PCI clock cycle.

To prevent bus contention, if the secondary PCI bus is idle, the arbiter never asserts one grant signal in the same PCI cycle in which it de-asserts another. It de-asserts one grant and asserts the next grant, no earlier than one PCI clock cycle later. If the secondary PCI bus is busy, that is, either S1_FRAME# (S2_FRAME#) or S1_IRDY# (S2_IRDY#) is asserted, the arbiter can de-assert one grant and assert another grant during the same PCI clock cycle.

9.2.2 Secondary Bus Arbitration Using an External Arbiter

The internal arbiter is disabled when the secondary bus central function control pin, S_CFN#, is tied high. An external arbiter must then be used.

When S_CFN# is tied high, PI7C7100 reconfigures four pins (two per port) to be external request and grant pins. The S1_GNT#[0] and S2_GNT#[0] pins are reconfigured to be the external request pins because they are output. The S1_REQ#[0] and S2_REQ#[0] pins are reconfigured to be the external grant pins because they are input. When an external arbiter is used, PI7C7100 uses the S1_GNT#[0] or S2_GNT#[0] pin to request the secondary bus. When the reconfigured S1_REQ#[0] or S2_REQ#[0] pin is asserted low after PI7C7100 has asserted S1_GNT#[0] or S2_GNT#[0]. PI7C7100 initiates a transaction on the secondary bus one cycle later. If grant is asserted and PI7C7100 has not asserted the request, PI7C7100 parks AD, CBE and PAR pins by driving them to valid logic levels.

The unused secondary bus grant outputs, S1_GNT#[7:1] and S2_GNT#[7:1] are driven high. The unused secondary bus request inputs, S1_REQ#[7:1] and S2_REQ#[7:1], should be pulled high.

9.2.3 Bus Parking

Bus parking refers to driving the AD[31:0], CBE[3:0]#, and PAR lines to a known value while the bus is idle. In general, the device implementing the bus arbiter is responsible for parking the bus or assigning another device to park the bus. A device parks the bus when the bus is idle, its bus grant is asserted, and the device’s request is not asserted. The AD and CBE signals should be driven first, with the PAR signal driven one cycle later.

PI7C7100 parks the primary bus only when P_GNT# is asserted, P_REQ# is de-asserted, and the primary PCI bus is idle. When P_GNT# is de-asserted, PI7C7100 3-states the P_AD, P_CBE, and P_PAR signals on the next PCI clock cycle. If PI7C7100 is parking the primary PCI bus and wants to initiate a transaction on that bus, then PI7C7100 can start the transaction on the next PCI clock cycle by asserting P_FRAME# if P_GNT# is still asserted.

If the internal secondary bus arbiter is enabled, the secondary bus is always parked at the last master that used the PCI bus. That is, PI7C7100 keeps the secondary bus grant asserted to a particular master until a new secondary bus request comes along. After reset, PI7C7100 parks the secondary bus at itself until transactions start occurring on the secondary bus. If the internal arbiter is disabled, PI7C7100 parks the secondary bus only when the reconfigured grant signal, S_REQ#<0>, is asserted and the secondary bus is idle.

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3-Port PCI Bridge

ADVANCE INFORMATION

10. Clocks

This chapter provides information about the clocks.

10.1 Primary Clock Inputs

PI7C7100 implements a primary clock input for the PCI interface. The primary interface is synchronized to the primary clock input, P_CLK, and the secondary interface is synchronized to the secondary clock. The secondary clock is derived internally from the primary clock, P_CLK, through an internal PLL.

PI7C7100 operates at a maximum frequency of 33 MHz.

10.2 Secondary Clock Outputs

PI7C7100 has 16 secondary clock outputs, S_CLKOUT[15:0] that can be used as clock inputs for up to sixteen external secondary bus devices. The S_CLKOUT[15:0] outputs are derived from P_CLK. The secondary clock edges are delayed from P_CLK edges by a minimum of 0ns.

This is the rule for using secondary clocks:

• Each secondary clock output is limited to no more than one load.

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11. Reset

This chapter describes the primary interface, secondary interface, and chip reset mechanisms.

11.1 Primary Interface Reset

PI7C7100 has a reset input, P_RESET#. When P_RESET# is asserted, the following events occur:

• PI7C7100 immediately 3-states all primary and secondary PCI interface signals.

• PI7C7100 performs a chip reset.

• Registers that have default values are reset. P_RESET# asserting and de-asserting edges can be asynchronous to P_CLK and S_CLK.

11.2 Secondary Interface Reset

PI7C7100 is responsible for driving the secondary bus reset signals, S1_RESET# and S2_RESET#. PI7C7100 asserts S1_RESET# or S2_RESET# when any of the following conditions is met:

• Signal P_RESET# is asserted. Signal S1_RESET# or S2_RESET# remains asserted as long as P_RESET# is asserted and does not de-assert until P_RESET# is de-asserted.

• The secondary reset bit in the bridge control register is set. Signal S1_RESET# or S2_RESET# remains asserted until a configuration write operation clears the secondary reset bit.

• S1_RESET# or S2_RESET# pin is asserted. When S1_RESET# or S2_RESET# is asserted, the following events occur: PI7C7100 immediately 3-states all the secondary PCI interface signals associated with the Secondary S1 or S2 port. The S1_RESET# or S2_RESET# in asserting and de-asserting edges can be asynchronous to P_CLK.

• The chip reset bit in the diagnostic control register is set. Signal S1_RESET# or S2_RESET# remains asserted until a configuration write operation clears the secondary reset bit and the secondary clock serial mask has been shifted in.

When S1_RESET# or S2_RESET# is asserted, all secondary PCI interface control signals, including the secondary grant outputs, are immediately 3-stated. Signals S1_AD, S1_CBE[3:0]#, S1_PAR (S2_AD, S2_CBE[3:0]#, S2_PAR) are driven low for the duration of S1_RESET# (S2_RESET#) assertion. All posted write and delayed transaction data buffers are reset. Therefore, any transactions residing inside the buffers at the time of secondary reset are discarded.

When S1_RESET# or S2_RESET# is asserted by means of the secondary reset bit, PI7C7100 remains accessible during secondary interface reset and continues to respond to accesses to its configuration space from the primary interface.

11.3 Chip Reset

The chip reset bit in the diagnostic control register can be used to reset PI7C7100 and the secondary buses. All registers, and chip state machines are reset and all signals are 3-stated when the chip reset is set. In addition, S1_RESET# or S2_RESET# is asserted, and the secondary reset bit is automatically set. Signal S1_RESET# or S2_RESET# remains asserted until a configuration write operation clears the secondary reset bit.

As soon as chip reset completes, within 20 PCI clock cycles after completion of the configuration write operation that sets the chip reset bit, the chip reset bit automatically clears and the chip is ready for configuration.

During chip reset, PI7C7100 is inaccessible.

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PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

12. Supported Commands

The PCI command set is given below for the primary and secondary interfaces.

12.1 Primary Interface

#]0:3[EBC_PdnammoCnoitcA

0000egdelwonkcAtpurretnI.erongI 1000elcyClaicepS.erongI.mialctonoD 0100daeRO/I ssapdnamialc:egnarO/IhguorhtssapnihtiwsisserddafI.1

.hguorht

dnamialc:retsigerlanretniegdirbdeppamO/IotstniopsserddafI.2

.hguorhtssaptonod,retsigerotsseccatimrep

.sseccalanretnirofmialctonoddnahguorhtssaptonod,esiwrehtO.3 1100etirWO/I.daerO/IsaemaS 0010devreseR----1010devreseR----0110daeRyromeM ssapdnamialc:egnaryromemhguorhtssapnihtiwsisserddafI.1

.hguorht

mialc:egnarO/IdeppamyromemhguorhtssapnihtiwsisserddafI.2

.hguorhtssapdna

mialc:retsigerlanretniegdirbdeppamyromemotstniopsserddafI.3

.hguorhtssaptonod,retsigerotsseccatimrepdna

.sseccalanretnirofmialctonoddnahguorhtssaptonod,esiwrehtO.4

1110etirWyromeMdaeRyromeMsaemaS

0001devreseR----1001devreseR----0101noitarugifnoC

daeR

I. :daernoitarugifnoc0epyT

dnaedocednoitcnufmrofrep,detressasienilLESDIs'egdirbehtfI

,demialcfI.erongi,esiwrehto,detnemelpmisinoitcnuftegratfimialc

ssaptonoD.sretsigernoitarugifnocs'noitcnuftegratotsseccatimrep

.secnatsmucricynarednuhguorht

:daernoitarugifnoc1epyT.II

dnamialc:subyradnocess'egdirbehtsisubtegratehtfI.1

.daernoitarugifnoc0epytasahguorhtssap

ehtdnihebstsixetahtsubetanidrobusasisubtegratehtfI.2

dnamialc:)subyradnocesehtotlauqetontub(egdirb

.daernoitarugifnoc1epytasahguorhtssap

.erongi,esiwrehtO.3

Page 61

PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

12.1 Primary Interface (continued)

#]0:3[EBC_PdnammoCnoitcA

1101noitarugifnoC

etirW

.daernoitarugifnocsaemas:etirwnoitarugifnoc0epyT.I

:)tseuqerelcyclaicepston(etirwnoitarugifnoc1epyT.II

ssapdnamialc:subyradnocess'egdirbehtsisubtegratehtfI.1

etirwnoitarugifnoc0epytasahguorht

egdirbehtdnihebstsixetahtsubetanidrobusasisubtegratehtfI.2

hguorhtssapdnamialc:)subyradnocesehtotlauqetontub(

.etirwnoitarugifnoc1epytasadegnahcnu

.erongi,esiwrehtO.3

tseuqerelcyclaicepssaetirwnoitarugifnoC.III

:)h7=noitcnuf,hF1=ecived(

ssapdnamialc:subyradnocess'egdirbehtsisubtegratehtfI.1

elcyclaicepsasahguorht

egdirbehtdnihebstsixetahtsubetanidrobusasisubtegratehtfI.2

hguorhtssapdnamialc:)subyradnocesehtotlauqetontub(

.etirwnoitarugifnoc1epytasadegnahcnu

erongi,esiwrehtO.3

0011daeRyromeM

elpitluM

daeRyromeMsaemaS

1011sserddAlauD

elcyC

detroppuStoN

0111daeRyromeM

eniL

daeRyromeMsaemaS

1111etirWyromeM

etadilavnI&

daeRyromeMsaemaS

Page 62

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PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

#]0:3[EBC_1S #]0:3[EBC_2S

dnammoCnoitcA

0000tpurretnI

egdelwonkcA

.erongI

1000elcyClaicepS.erongI.mialctonoD 0100daeRO/I.ecafretniyramirpsaemaS

1100etirWO/I.daerO/IsaemaS

0010devreseR----1010devreseR-----

0110daeRyromeM.ecafretniyramirpsaemaS 1110etirWyromeM.daeRyromeMsaemaS 0001devreseR----1001devreseR----0101noitarugifnoC

daeR

.erongI

1101noitarugifnoC

etirW

:etirwnoitarugifnoc0epyT.I .erongI

:)tseuqerelcyclaicepston(etirwnoitarugifnoc1epyT.II .erongI

tseuqerelcyclaicepssaetirwnoitarugifnoC.III

:)h7=noitcnuf,hF1=ecived(

hguorhtssapdnamialc:subyramirps'egdirbehtsisubtegratehtfI.1

.elcyclaicepsasa

sesubfoegnarnitisironsubyramirpehtrehtiensisubtegratehtfI.2

mialc:sretsigersubetanidrobusdnayradnocess'egdirbehtybdenifed

.etirwnoitarugifnoc1epytasadegnahcnuhguorhtssapdna

sesubfoegnarnisitub:subyramirps'egdirbehttonsisubtegratehtfI.3

.erongI:sretsigersubetanidrobusdnayradnocess'egdirbehtybdenifed

0011daeRyromeM

elpitluM

daeRyromeMsaemaS

1011sserddAlauD

elcyC

detroppuStoN

0111daeRyromeM

eniL

daeRyromeMsaemaS

1111etirWyromeM

etadilavnI&

daeRyromeMsaemaS

12.2 Secondary Interface

Page 63

PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

13. Configuration Registers

As PI7C7100 supports two secondary interfaces, it has two sets of configuration registers which are almost identical and accessed through different function numbers. The description below is for one set only.

PCI configuration defines a 64-byte space (configuration header) to define various attributes of the PCI-to-PCI Bridge as shown below. All of the registers in bold type are required by the PCI specification and are implemented in this bridge. The others are available for use as control registers for the device. There are two configuration registers: Configuration Register 1 and Configuration Register 2 corresponding to Secondary bus 1 and Secondary bus 2 interfaces respectively. Also, the configuration for the primary interface is implemented through the Configuration Register 1.

42-1361-328-510-7sserddA

DIeciveDDIrodneV h00

sutatSdnammoC h40

edoCssalCDInoisiveR h80

devreseR

epyTredaeHremiTycnetaLyramirPeziSeniLehcaC hC0

devreseRh41-h01

ycnetaLyradnoceS

remiT

suBetanidrobuS

rebmuN

suByradnoceS

rebmuN

suByramirP

rebmuN

h81

sutatSyradnoceStimiLO/IesaBO/I hC1

timiLyromeMesaByromeM h02

timiLyromeMelbahcteferP esaByromeMelbahcteferPh42

devreseRhC2-h82

stiB61reppUtimiLO/I stiB61reppUesaBO/Ih03

DImetsysbuSDIrodneVmetsysbuSh43

devreseRh83

lortnoCegdirB

niPtpurretnIdevreseR

hC3

lortnoCretibrAlortnoCcitsongaiDlortnoCpihCh04

timiLyromeMelbahcteferPyramirP esaByromeMelbahcteferPyramirPh44

devreseRh06-h84

devreseRtnevE#RRES_P

elbasiD

h46

devreseRdevreseRlortnoCkcolCyradnoceSh86

devreseRhC6

timiLyromeMdetsoP-noN esaByromeMdetsoP-noNh07

retnuoCtuoemiTretsaMnoitpOtroPh47

retnuoCyrteRh87

remiTgnilpmaShC7

tnuocdaerO/IlufsseccuSyradnoceS h08 tnuocetirwO/IlufsseccuSyradnoceS h48

tnuocdaeryromemlufsseccuSyradnoceS h88

tnuocetirwyromemlufsseccuSyradnoceS hC8 tnuocdaerO/IlufsseccuSyramirP h09 tnuocetirwO/IlufsseccuSyramirP h49

tnuocdaeryromemlufsseccuSyramirP h89 tnuocetirwyromemlufsseccuSyramirP hC9

devreseRhFF-h0A

13.1 Configuration Register 1

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PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

42-1361-328-510-7sserddA

DIeciveDDIrodneV h00

sutatSdnammoC h40

edoCssalCDInoisiveR h80

devreseR

epyTredaeHremiTycnetaLyramirPeziSeniLehcaC

hC0

devreseRh41-h01

ycnetaLyradnoceS

remiT

suBetanidrobuS

rebmuN

suByradnoceS

rebmuN

suByramirP

rebmuN

h81

sutatSyradnoceStimiLO/IesaBO/I hC1

timiLyromeMesaByromeM h02

timiLyromeMelbahcteferP esaByromeMelbahcteferPh42

devreseRhC2-h82

stiB61reppUtimiLO/IstiB61reppUesaBO/Ih03

DImetsysbuSDIrodneVmetsysbuSh43

devreseRh83

lortnoCegdirB

niPtpurretnIdevreseR

hC3

lortnoCretibrAlortnoCcitsongaiDlortnoCpihCh04

timiLyromeMelbahcteferPyramirP esaByromeMelbahcteferPyramirPh44

devreseRh06-h84 devreseRh46

devreseRdevreseRlortnoCkcolCyradnoceSh86

devreseRhC6

timiLyromeMdetsoP-noN esaByromeMdetsoP-noNh07

devreseRdevreseRh47

devreseRh87

remiTgnilpmaShC7

tnuocdaerO/IlufsseccuSyradnoceSh08

tnuocetirwO/IlufsseccuSyradnoceSh48

tnuocdaeryromemlufsseccuSyradnoceS h88

tnuocetirwyromemlufsseccuSyradnoceS hC8 devreseRh09 devreseRh49 devreseRh89 devreseRhC9 devreseRhFF-h0A

13.2 Configuration Register 2

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PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

13.2.1 Config Register 1 or 2: Vendor ID Register (read only, bit 15-0; offset 00h)

Pericom ID is 12D8h.

13.2.2 Config Register 1: Device ID Register (read only, bit 31-16; offset 00h)

Hardwired to 1B59h (S1)

13.2.3 Config Register 2: Device ID Register (read only, bit 31-16; offset 00h)

Hardwired to 1B5Ah (S2)

13.2.4 Configuration Register 1: Command Register (bit 15-0; offset 04h)

tiBnoitcnuFepyTnoitpircseD

01-51devreseRO/R'000000'otteseR

otkcaBtsaF elbanEkcaB

W/R snoitcasnartkcab-ot-kcabtsafetarenegotytilibas'egdirbslortnoC

.ecafretniyramirpehtnosecivedtnereffidot

noitcasnartkcabotkcabtsafon=0

noitcasnartkcabotkcabtsafelbane=1

0otteseR

elbanE#RRESW/R.nip#RRES_PehtrofelbaneehtslortnoC

revird#RRES_Pehtelbasid=0

revird#RRES_Pehtelbane=1

0otteseR

lortnoCelcyCtiaWO/R.detroppusgnippetsatadoN

0otteseR

elbanErorrEytiraPW/R.srorreytirapotesnopsers'egdirbslortnoC

srorreytirapynaerongi=0

demrofrepgnikcehcytiraplamron=1

0otteseR

elbanEpoonSettelaPAGVW/R .sesseccaettelapelbitapmocAGVotesnopsers'egdirbslortnoC

ecafretniyramirpehtnosesseccaettelapAGVerongi=0

ecafretniyramirpehtnosetirwettelapAGVotesnopserelbane=1

h8C3,h6C3=]0:9[DAsserddaO/I()h9C3dna

0otteseR

dnaetirWyromeM

elbanEetadilavnI

O/RdetroppustonetadilavnIdnaetirWyromeM

0otteseR

elbanEelcyClaicepSO/RnoitatnemelpmielcyclaicepsoN

0otteseR

elbanEretsaMsuBW/Ryramirpehtnoretsamasaetarepootytilibas'egdirbslortnoC

.ecafretni

dnaecafretniyramirpehtnonoitcasnartetaitinitonod=0

yradnocesnosnoitcasnartO/Iroyromemotesnopserelbasid

ecafretni

yramirpehtnoretsamasaetarepootegdirbehtelbane=1

ecafretni

0otteseR

elbanEecapSyromeMW/Ryramirpehtnosesseccayromemotesnopsers'egdirbslortnoC

.ecafretni

noitcasnartyromemllaerongi=0

noitcasnartyromemotesnopserelbane=1

0otteseR

elbanEecapSO/IW/R .ecafretniyramirpehtnosesseccaO/Iotesnopsers'egdirbslortnoC

noitcasnartO/Ierongi=0

noitcasnartO/Iotesnopserelbane=1

0otteseR

Note: R/W - Read/Write, R/O - Read Only, R/WC - Read/ Write 1 to clear

Page 66

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PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

tiBnoitcnuFepyTnoitpircseD

01-51

devreseRO/R

'000000'otteseR

9devreseRW/R 0otteseR 8devreseRW/R 0otteseR

lortnoCelcyCtiaWO/R.detroppusgnippetsatadoN

0otteseR

devreseRW/R 0otteseR

ettelaPAGV

elbanEpoonS

W/R.sesseccaettelapelbitapmocAGVotesnopsers'egdirbslortnoC

ecafretniyramirpehtnosesseccaettelapAGVerongi=0

ecafretniyramirpehtnosetirwettelapAGVotesnopserelbane=1

)h9C3dnah8C3,h6C3=]0:9[DAsserddaO/I(

0otteseR

dnaetirWyromeM

elbanEetadilavnI

O/R.detroppustonetadilavnIdnaetirWyromeM

0otteseR

elcyClaicepS

elbanE

O/R.noitatnemelpmielcyclaicepsoN

0otteseR

retsaMsuB

elbanE

W/R .ecafretniyramirpehtnoretsamasaetarepootytilibas'egdirbslortnoC

elbasiddnaecafretniyramirpehtnonoitcasnartetaitinitonod=0

ecafretniyradnocesnosnoitcasnartO/Iroyromemotesnopser

ecafretniyramirpehtnoretsamasaetarepootegdirbehtelbane=1

0otteseR

elbanEecapSyromeMW/Ryramirpehtnosesseccayromemotesnopsers'egdirbslortnoC

.ecafretni

noitcasnartyromemllaerongi=0

noitcasnartyromemotesnopserelbane=1

0otteseR

elbanEecapSO/IW/R .ecafretniyramirpehtnosesseccaO/Iotesnopsers'egdirbslortnoC

noitcasnartO/Ierongi=0

noitcasnartO/Iotesnopserelbane=1

0otteseR

13.2.5 Configuration Register 2: Command Register (bit 15-0; offset 04h)

Note: R/W - Read/Write, R/O - Read Only, R/WC - Read/ Write 1 to clear

Page 67

PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

13.2.6 Configuration Register 1 or 2: Status Register (for primary bus, bits 31-16; offset 04h)

tiBnoitcnuFepyTnoitpircseD

13rorrEytiraPdetceteDCW/RehtfosseldragerdetcetedsirorreytiraparevenehwtesebdluohS

.retsigerdnammocehtfo6tibfoetats

0otteseR

03rorrEmetsySdelangiSCW/R.detressasi#RRES_PrevenehwtesebdluohS

0otteseR

92trobAretsaMdevieceRCW/Rdetanimreterasnoitcasnartnehw)retsamayb('1'otteS

.trobAretsaMhtiw

0otteseR

82trobAtegraTdevieceRCW/Rdetanimreterasnoitcasnartnehw)ecivedretsamayb('1'otteS

.trobAtegraThtiw

0otteseR

72trobAtegraTdelangiSCW/RtrobAtegraTarevenehw)ecivedtegratayb(tesebdluohS

.sruccoelcyc

0otteseR

52-62gnimiTLESVEDO/R.gnimit#LESVEDmuideM

'10'otteseR

42detceteDrorrEytiraPataDCW/R:temerasnoitidnocgniwollofehtnehwtessitI

detressasi#RREP_P.1

tessiretsigeRdnammoCfo6tiB.2

0otteseR

32elbapaCkcaBotkcaBtsaFO/R.edisyramirpnoelbapacetirwkcab-ot-kcabtsaF

1otteseR

22devreseRO/R 0otteseR 12devreseRO/R 1otteseR 02tsiLseitilibapaCO/R.detroppustonsitsiLseitilibapaC

0otteseR

61-91devreseRO/R 0otteseR

Note: R/W - Read/Write; R/O - Read Only; R/WC - Read/Write1 to clear.

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PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

13.2.7 Config Register 1 or 2: Revision ID Register (read only, bit 7-0; offset 08h)

Hardwired to 01h

13.2.8 Config Register 1 or 2: Class Code Register (read only, bit 31-8; offset 08h)

Hardwired to 060400h

13.2.9 Config Register 1 or 2: Cache Line Size Register (read/write, bit 7-0; offset 0Ch)

This register is used when terminating memory write and invalidate transactions and when pre-fetching. Only cache line sizes (in units of 4-byte) which are power of two are valid (only one bit can be set in this register;

only 00h, 01h, 02h, 04h, 08h, 10h are valid values). Reset to 00h

13.2.10 Config Register 1: Primary Latency Timer Register (read/write, bit 15-8; offset 0Ch)

This register sets the value for Master Latency Timer which starts counting when master asserts FRAME#. Reset to 00h

13.2.11 Config Register 2: Primary Latency Timer Register (read/write, bit 15-8; offset 0Ch)

This register is implemented but not being used internally. Reset to 00h

13.2.12 Config Register 1: Header Type Register (read only, bit 23-16; offset 0Ch)

Hardwired to 81h for function 0 (multiple function PCI-to-PCI bridge, for secondary bus S1)

13.2.13 Config Register 2: Header Type Register (read only, bit 23-16; offset 0Ch)

Hardwired to 01h for function 1 (single function PCI-to-PCI bridge, for secondary bus S2)

13.2.14 Config Register 1: Primary Bus Number Register (read/write, bit 7-0; offset 18h)

Programmed with the number of the PCI bus to which the primary bridge interface is connected. This value is set by software during configuration. Reset to 00h

13.2.15 Config Register 2: Primary Bus Number Register (read/write, bit 7-0; offset 18h)

This register is implemented but not being used internally. Reset to 00h

13.2.16 Config Register 1 or 2: Secondary Bus Number Register (read/write, bit 15-8; offset 18h)

Programmed with the number of the PCI bridge secondary bus interface. This value is set by software during configuration. Reset to 00h

13.2.17 Config Register 1 or 2: Subordinate Bus Number Register (read/write, bit 23-16; offset 18h)

Programmed with the number of the PCI bus with the highest number that is subordinate to the bridge. This value is set by software during configuration. Reset to 00h

13.2.18 Config Register 1 or 2: Secondary Latency Timer (read/write, bit 31-24; offset 18h)

This register is programmed in units of PCI bus clocks.The latency timer checks for master accesses on the secondary bus interfaces that remain unclaimed by any target. Reset to 00h

13.2.19 Config Register 1 or 2: I/O Base Register (read/write, bit 7-0; offset 1Ch)

This register defines the bottom address of the I/O address range for the bridge. The upper four bits define the bottom address range used by the chip to determine when to forward I/O transactions from one interface to the other. These 4 bits correspond to address bits [15:12] and are write-able. The upper 16 bits corresponding to address bits [31:16] are defined in the I/O base upper 16 bits address register. The address bits [11:0] are assumed to be 000h. The lower

four bits (3:0) of this register set to ‘0001’ (read-only) to indicate 32-bit I/O addressing. Reset to 00h

13.2.20 Config Register 1 or 2: I/O Limit Register (read/write, bit 15-8; offset 1Ch)

This register defines the top address of the I/O address range for the bridge. The upper four bits define the top address range used by the chip to determine when to forward I/O transactions from one interface to the other. These 4 bits correspond to address bits [15:12] and are write-able. The upper 16 bits corresponding to address bits [31:16] are defined in the I/O limit upper 16 bits address register. The address bits [11:0] are assumed to be FFFh. The lower four bits (3:0) of this register set to ‘0001’ (read-only) to indicate 32-bit I/O addressing. Reset to 00h.

Page 69

PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

tiBnoitcnuFepyTnoitpircseD

13rorrEytiraPdetceteDCW/RehtfosseldragerdetcetedsirorreytiraparevenehwtesebdluohS

.retsigerdnammocehtfo6tibfoetats

0otteseR

03rorrEmetsySdelangiSCW/R.detcetedsi#RRES_2Sro#RRES_1SrevenehwtesebdluohS

.teserretfa'0'aebdluohS

0otteseR

92trobAretsaMdevieceRCW/Rhtiwdetanimreterasnoitcasnartnehw)retsamayb('1'otteS

.trobAretsaM

0otteseR

82trobAtegraTdevieceRCW/R htiwdetanimreterasnoitcasnartnehw)ecivedretsamayb('1'otteS

.trobAtegraT

0otteseR

72trobAtegraTdelangiSCW/R .sruccoelcyctrobAtegraTarevenehw)ecivedtegratayb(tesebdluohS

.teserretfa'0'ebdluohS

0otteseR

52-62gnimitLESVEDO/R.gnimit#LESVEDmuideM

'10'otteseR

42detceteDrorrEytiraPataDCW/R:temerasnoitidnocgniwollofehtnehwtessitI

detressasi#RREP_2Sro#RREP_1S.1

tessiretsigeRdnammoCfo6tiB.2

0otteseR

32elbapaCkcaB-ot-kcaBtsaFO/R.sesubyradnocesnoelbapacetirwkcab-ot-kcabtsaF

1otteseR

22devreseRO/R 0otteseR 12devreseRO/R 0otteseR

61-02devreseRO/R '00000'otteseR

13.2.21 Configuration Register 1 or 2: Secondary Status Register (bits 31-16; offset 1Ch)

Note: R/W - Read/Write, R/O - Read Only, R/WC - Read/ Write 1 to clear

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PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

13.2.22 Config Register 1 or 2: Memory Base Register (read/write, bit 15-0; offset 20h)

This register defines the base address of the memory-mapped address range for forwarding the cycle through the bridge. The upper twelve bits corresponding to address bits [31:20] are read/write. The twelve bits are reset to 000h.

The lower 20 address bits (19:0) are assumed to be 00000h.

13.2.23 Config Register 1 or 2: Memory Limit Register (read/write, bit 31:16; offset 20h)

This register defines the upper limit address of the memory-mapped address range for forwarding the cycle through the bridge. Upper twelve bits corresponding to address bit [31:20] are read/write. Upper twelve bits are reset to 0000h.

Lower 20 address bits (19:0) are assumed to be FFFFFh.

13.2.24 Config Register 1 or 2: Prefetchable Memory Base Register (read/write, bit 15-0;offset 24h)

This register defines the base address of the prefetchable memory-mapped address range for forwarding the cycle through the bridge. The upper twelve bits corresponding to address bits [31:20] are read/write. The upper twelve bits are reset to 000h. The lower four bits are read only and are set to 0. The lower 20 address bits (19:0) are as-

sumed to be 00000h.

13.2.25 Config Register 1 or 2: Prefetchable Memory Limit Register (read/write, bit 31-16; offset 24h)

This register defines the upper limit address of the memory-mapped address range for forwarding the cycle through the bridge. The upper twelve bits correspond to address bit [31:20] are read/write. The upper twelve bits are reset to 000h.

The lower four bits are read only and are set to 0. The lower 20 address bits (19:0) are assumed to be FFFFFh.

13.2.26 Config Register 1 or 2: I/O Base Address Upper 16 Bits Register (read/write, bit 15-0; offset 30h)

This register defines the upper 16 bits of a 32-bit base I/O address range used for forwarding the cycle through the bridge.

Reset to 0000h.

13.2.27 Config Register 1 or 2: I/O Limit Address Upper 16 Bits Register (read/write, bit 31-16; offset 30h)

This register defines the upper 16 bits of a 32-bit limit I/O address range used for forwarding the cycle through the bridge.

Reset to 0000h.

13.2.28 Config Register 1 or 2: Subsystem Vendor ID (read/write, bit 15-0; offset 34h)

A 16-bit register for add-on cards to distinguish from one another. Reset to 0000h.

13.2.29 Config Register 1 or 2: Subsystem ID (read/write, bit 31-16; offset 34h)

A 16-bit register for add-on cards to distinguish from one another. Reset to 0000h.

13.2.30 Config Register 1 or 2: Interrupt Pin Register (read only, bit 15-8; offset 3Ch)

The register reads as 00h to indicate that PI7C7100 does not use any interrupt pins.

Page 71

PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

tiBnoitcnuFepyTnoitpircseD

82-13devreseRO/R '0000'otteseR 72devreseRW/R 0otteseR 62tuoemiTretsaM

sutatS

CW/R.tuoemitretsamyradnocesroretsamyramirprehtienehw'1'otteS

0otteseR

52devreseRW/R 0otteseR 42devreseRW/R 0otteseR 32kcaB-ot-kcaBtsaF

elbanE

W/R otsnoitcasnartkcab-ot-kcabtsafetarenegotytilibas'egdirbslortnoC tnereffid

yradnocesehtnosecived.ecafretni

noitcasnartkcab-ot-kcabtsafon=0

notcasnartkcab-ot-kcabtsafelbane=1

0otteseR

22ecafretnIyradnoceS

teseR

W/R yradnocesehtnoniplangis#TESER_2Sro#TESER_1SfonoitressaehtsecroF

.ecafretni

nip#TESER_2Sro#TESER_1Sfonoitressaehtecroftonod=0

nip#TESER_2Sro#TESER_1Sfonoitressaehtecrof=1

0otteseR

12edoMtrobAretsaMW/R yradnocesnostrobaretsamotgnidnopserroivahebs'egdirbslortnoC .ecafretni

dnadaernohFFFF_FFFFnruter(strobaretsamtropertonod=0

)etirwnoataddracsid

fonoitressaehtybelbissopfitrobategratgnilangisybstrobaretsamtroper=1

delbanefi#RRES_P

0otteseR

02devreseRO/R 0otteseR 91elbanEAGVW/R.sesserddaelbitapmocAGVotesnopsers'egdirbehtslortnoC

sesserddaO/IdnayromemelbitapmocAGVdrawroftonod=0

yradnocesotyramirpmorf

yradnocesotyramirpmorfsserddaO/IdnayromemelbitapmocAGVdrawrof=1

sgnittesrehtofosseldrager

0otteseR

81elbanEASIW/R .K46tsrifehtotdetimilsihcihwsserddaO/IASIotesnopsers'egdirbslortnoC

BO/IehtybdenifedegnarehtnisesserddaO/Illadrawrof=0 a O/Idnaes

sretsigertimiL ,

ehtybdenifedegnarehtnisesserddaO/IASIfognidrawrofkcolb=1

sserddatahtecapsO/IfoK46tsrifehtnieratahtsretsigertimiLO/IdnaesaBO/I

erasnoitcasnartO/IyradnoceS.kcolbsetybK1hcaenisetyb867tsaleht

ehtnihtiwsllafsserddaehtfimaertspudedrawrof

kcolbetybK1hcaenisetyb867tsal

0otteseR

71ro#RRES_1S

#RRES_2S

elbanE

.ecafretniyramirpehtot#RRES_2Sro#RRES_1SfognidrawrofehtslortnoC

yramirpot#RRES_2Sro#RRES_1Sgnidrawrofehtelbasid=0

.ecafretniyramirpot#RRES_2Sro#RRES_1Sfognidrawrofehtelbane=1

0otteseR

61rorrEytiraP

esnopseR

elbanE

.ecafretniyradnocesehtnosrorreytirapotesnopsers'egdirbehtslortnoC

.ecafretniyradnocesehtnosrorreytirapataddnasserddaerongi=0

.ecafretniyradnocesehtnonoitceteddnagnitroperrorreytirapelbane=1

0otteseR

13.2.31 Configuration Register 1 or 2: Bridge Control Register (bits 31-16; offset 3Ch)

Note: R/W - Read/Write, R/O - Read Only, R/WC - Read/ Write 1 to clear.

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PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

tiBnoitcnuFepyTnoitpircseD

11-51devreseRO/R '00000'otteseR

9-01edoMtseTW/R eraretnuocfostiblla,00nehW.sretnuoclanretnis'pihcfoytilibatsetslortnoC

fo2etyb,01nehW.desicrexesiretnuocfo1etyb,10nehW.desicrexe

.desicrexesiretnuocfo3etyb,11nehW.desicrexesiretnuoc

0otteseR

5-8devreseRO/R '0000'otteseR

4devreseRW/R 0otteseR

2-3devreseRO/R '00'otteseR 1devreseRW/R 0otteseR 0devreseRO/R 0otteseR

tiBnoitcnuFepyTnoitpircseD

82:13devreseRO/R '0000'otteseR

72dirbyHW/R.2dna1subyradnocesmorfsretsamrofnoitartibradexiM

#]0:7[QER_2Sdna#]0:7[QER_1Srofnoitartibraetarapes=0

.noitartibrarof#]0:3[QER_2Shtiwdeximera#]0:3[QER_1S=1

.desusiretibraenoylnO

0otteseR

62devreseRW/R 0otteseR 52foytiroirP

yradnoceS

troP

W/Rytiroirphgihnisi0017C7IPfotropyradnocesehtrehtehwsenifeD

.puorgytiroirpwolehtropuorg

puorgytiroirpwol=0

puorgytiroirphgih=1

1otteseR

42devreseRO/R 0otteseR

61-32retibrA

lortnoC

W/R ytiroirphgihehtotdengissasiretsamsub-yradnocesarehtehwslortnoctibhcaE

stupnitseuqerotdnopserroc]0:7[tiB.puorgytiroirpwolehtropuorg

.#]0:7[QER_2Sro#]0:7[QER_1S

'00000000'otteseR

13.2.32 Configuration Register 1 or 2: Diagnostic/Chip Control Register (bit 15-0, offset 40h)

13.2.33 Configuration Register 1 or 2: Arbiter Control Register (bit 31-16, offset 40h)

Note: R/W - Read/Write, R/O - Read Only, R/WC - Read/ Write 1 to clear.

Page 73

PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

13.2.34 Config Register 1: Primary Prefetchable Memory Base Register (Read/Write, bit 15-0; offset 44h)

This register is implemented but not being used internally.This register defines the base address of the primary prefetchable memory-mapped address range for forwarding the cycle through the bridge. The upper twelve bits corresponding to address bits [31:20] are read/write. The upper twelve bits are reset to 0000h. The lower four bits are read only and are set to 0h. The lower 20 address bits (19:0) are assumed to be 00000h.

13.2.35 Config Register 2: Primary Prefetchable Memory Base Register (Read/Write, bit 15-0; offset 44h)

This register is implemented but not being used internally. The upper twelve bits corresponding to address bits [31:20] are read/write. The upper twelve bits are reset to 0000h. The lower four bits are read only and are set to 0h.

13.2.36 Config Register 1: Primary Prefetchable Memory Limit Register (Read/Write, bit 31-16; offset 44h)

This register is implemented but not being used internally.This register defines the upper limit address of the primary prefetchable memory-mapped address range for forwarding the cycle through the bridge. The upper twelve bits corresponding to address bits [31:20] are read/write. The upper twelve bits are reset to 0000h. The lower four bits are read only and are set to 0h. The lower 20 address bits (19:0) are assumed to be FFFFFh.

13.2.37 Config Register 2: Primary Prefetchable Memory Limit Register (Read/Write, bit 31-16; offset 44h)

tiBnoitcnuFepyTnoitpircseD

7devreseRO/R 0otteseR 6-daerdeyaleD

morfatadon

tegrat

W/R ynarefsnartotelbanusitinehw#RRES_Ptressaot0017C7IPfoytilibaslortnoC

2retfategratehtmorfataddaer

tnevesihtfidetressasi#RRES_P.stpmetta .tessiretsigerdnammocehtnitibelbane#RRESdna0sitibsihtnehwsrucco

0otteseR

5etirwdeyaleD

revilednon

W/R refsnartotelbanusitinehw#RRES_Ptressaot0017C7IPfoytilibaslortnoC

2retfaatadetirwdeyaled

sruccotnevesihtfidetressasi#RRES_P.stpmetta

.tessiretsigerdnammocehtnitibelbane#RRESdna0sitibsihtnehw

0otteseR

4trobaretsaM

detsopno

etirw

W/R trobaretsamaseviecertinehw#RRES_Ptressaot0017C7IPfoytilibaslortnoC

tnevesihtfidetressasi#RRES_P.atadetirwdetsopreviledotgnitpmettanehw

.tessiretsigerdnammocehtnitibelbane#RRESdna0sitibsihtnehwsrucco

0otteseR

3trobategraT

detsopgnirud

etirw

W/R trobategrataseviecertinehw#RRES_Ptressaot0017C7IPfoytilibaslortnoC

tnevesihtfidetressasi#RRES_P.atadetirwdetsopreviledotgnitpmettanehw

.tessiretsigerdnammocehtnitibelbane#RRESdna0sitibsihtnehwsrucco

0otteseR

2etirwdetsoP

yreviled-non

W/R detsopreviledotelbanusitinehw#RRES_Ptressaot0017C7IPfoytilibaslortnoC

2retfaatadetirw

tibsihtnehwsruccotnevesihtfidetressasi#RRES_P.stpmetta

.tessiretsigerdnammocehtnitibelbane#RRESdna0si

0otteseR

1etirwdetsoP

rorreytirap

W/R nodetcetedsirorreytirapanehw#RRES_Ptressaot0017C7IPfoytilibaslortnoC

tnevesihtfidetressasi#RRES_P.noitcasnartetirwdetsopagnirudsubtegrateht

.tessiretsigerdnammocehtnitibelbane#RRESdna0sitibsihtnehwsrucco

0otteseR

0devreseRO/R 0otteseR

13.2.38 Config Register 1 or 2: P_SERR# Event Disable Register (bit 7-0; offset 64h)

Note: R/W - Read/Write, R/O - Read Only, R/WC - Read/ Write 1 to clear.

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PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

tiBnoitcnuFepyTnoitpircseD

41-51

elbasiD7kcolC

W/R

delbanesi]7[TUOKLC_S,0sitibrehtiefI

delbasidsi]7[TUOKLC_S,1erastibhtobnehW

21-31

elbasiD6kcolC

delbanesi]6[TUOKLC_S,0sitibrehtiefI

delbasidsi]6[TUOKLC_S,1erastibhtobnehW

01-11

elbasiD5kcolC

delbanesi]5[TUOKLC_S,0sitibrehtiefI

delbasidsi]5[TUOKLC_S,1erastibhtobnehW

8-9

elbasiD4kcolC

delbanesi]4[TUOKLC_S,0sitibrehtiefI

delbasidsi]4[TUOKLC_S,1erastibhtobnehW

6-7

elbasiD3kcolC

delbanesi]3[TUOKLC_S,0sitibrehtiefI

delbasidsi]3[TUOKLC_S,1erastibhtobnehW

4-5

elbasiD2kcolC

delbanesi]2[TUOKLC_S,0sitibrehtiefI

delbasidsi]2[TUOKLC_S,1erastibhtobnehW

2-3

elbasiD1kcolC

delbanesi]1[TUOKLC_S,0sitibrehtiefI

delbasidsi]1[TUOKLC_S,1erastibhtobnehW

0-1

elbasiD0kcolC

delbanesi]0[TUOKLC_S,0sitibrehtiefI

delbasidsi]0[TUOKLC_S,1erastibhtobnehW

tiBnoitcnuFepyTnoitpircseD

41-51

elbasiD7kcolC

W/R

delbanesi]51[TUOKLC_S,0sitibrehtiefI

delbasidsi]51[TUOKLC_S,1erastibhtobnehW

21-31

elbasiD6kcolC

delbanesi]41[TUOKLC_S,0sitibrehtiefI

delbasidsi]41[TUOKLC_S,1erastibhtobnehW

01-11

elbasiD5kcolC

delbanesi]31[TUOKLC_S,0sitibrehtiefI

delbasidsi]31[TUOKLC_S,1erastibhtobnehW

8-9

elbasiD4kcolC

delbanesi]21[TUOKLC_S,0sitibrehtiefI

delbasidsi]21[TUOKLC_S,1erastibhtobnehW

6-7

elbasiD3kcolC

delbanesi]11[TUOKLC_S,0sitibrehtiefI

delbasidsi]11[TUOKLC_S,1erastibhtobnehW

4-5

elbasiD2kcolC

delbanesi]01[TUOKLC_S,0sitibrehtiefI

delbasidsi]01[TUOKLC_S,1erastibhtobnehW

2-3

elbasiD1kcolC

delbanesi]9[TUOKLC_S,0sitibrehtiefI

delbasidsi]9[TUOKLC_S,1erastibhtobnehW

0-1

elbasiD0kcolC

delbanesi]8[TUOKLC_S,0sitibrehtiefI

delbasidsi]8[TUOKLC_S,1erastibhtobnehW

13.2.39 Configuration Register 1: Secondary Clock Control Register (bit 15-0; offset 68h)

13.2.40 Configuration Register 2: Secondary Clock Control Register (bit 15-0; offset 68h)

Note: R/W - Read/Write.

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PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

13.2.41 Config Register 1 or 2: Non-Posted Memory Base Register (read/write, bit 15-0; offset 70h)

This register defines the base address of the non-posted memory-mapped address range for forwarding the cycle through the bridge. Upper twelve bits corresponding to address bits [31:20] are read/write. Lower 20 bits (19:0) are assumed to be 00000h.

13.2.42 Config Register 1 or 2: Non-Posted Memory Limit Register (read/write, bit 31-16; offset 70h)

This register defines the upper limit address of the non-posted memory-mapped address range for forwarding the cycle through the bridge. Upper twelve bits corresponding to address bits [31:20] are read/write. Lower 20 bits (19:0) are assumed to be FFFFFh.

tiBnoitcnuFepyTnoitpircseD

31-51devreseRO/R

'000'otteseR

daeRerPyramirP

W/R

yramirpnodnammocRMEMrofdaererom1elbanE

elbanE=1

egnahcoN=0

01-11devreseRO/R

'00'otteseR

tseuqeRgnoLelbanE

W/R

elcyckcolroftseuqergnoLelbanE

egnahcoN=0

elbanE=1

EUEUQTDteseR

W/R

eueuQnoitcasnarTdeyaleDyradnoceSteseR

egnahcoN=0

teseR=1

6-7devreseRO/R'00'otteseR

5elbanEetirWDIW/RDIrodneVmetsysbuS,DIeciveD,DIrodneVotetirwwollA

.ecapsnoitarugifnocehtniDImetsysbuSdna

tcetorpetirW=0

elbaneetirW=1

0otteseR

4WMEMyradnoceS

elbanEsailAdnammoC

W/R detsop-nongnihctamrofmsinahcemnoitceteds'egdirbehtslortnoC

.ecafretniyradnocesnorotaitinimorfelcycyrteretirwyromem

tcaxeebotsahdnammoC=0

IWMEMottnelaviuqesiWMEM=1

0otteseR

3RMEMyradnoceS

elbanEsailAdnammoC

W/R daeryromemgnihctamrofmsinahcemnoitceteds'egdirbehtslortnoC

.ecafretniyradnocesnorotaitinimorfelcycyrter

tcaxeebotsahdnammoC=0

MRMEMroLRMEMottnelaviuqesiRMEM=1

0otteseR

2WMEMyramirP

elbanEsailAdnammoC

W/R detsop-nongnihctamrofmsinahcemnoitceteds'egdirbehtslortnoC

.ecafretniyramirpnorotaitinimorfelcycyrteretirwyromem

tcaxeebotsahdnammoC=0

IWMEMottnelaviuqesiWMEM=1

0otteseR

1RMEMyramirP

elbanEsailAdnammoC

W/R daeryromemgnihctamrofmsinahcemnoitceteds'egdirbehtslortnoC

.ecafretniyramirpnorotaitinimorfelcycyrter

tcaxeebotsahdnammoC=0

MRMEMroLRMEMottnelaviuqesiRMEM=1

0otteseR

0yradnoceS

daeRerP

W/R.yradnocesnodnammocRMEMrofdaererom1elbanE

elbasid=0

elbane=1

0otteseR

13.2.43 Configuration Register 1: Port Option Register (bit 15-0; offset74h)

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PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

13.2.44 Configuration Register 2: Port Option Register (bit 15-0; offset74h)

tiBnoitcnuFepyTnoitpircseD

31-51devreseRO/R

'000'otteseR

21devreseRW/R

0otteseR

01-11devreseRO/R

'00'otteseR

8-9devreseRW/R

'00'otteseR

6-7devreseRO/R

'00'otteseR

5elbanEetirWDIW/R,DIrodneVmetsysbuS,DIeciveD,DIrodneVotetirwwollA

.ecapsnoitarugifnocehtniDImetsysbuSdna

tcetorpetirW=0

elbaneetirW=1

0otteseR

4WMEMyradnoceS

dnammoC

elbanEsailA

W/Rdetsop-nongnihctamrofmsinahcemnoitceteds'egdirbehtslortnoC

.ecafretniyradnocesnorotaitinimorfelcycyrteretirwyromem

tcaxeebotsahdnammoC=0

IWMEMottnelaviuqesiWMEM=1

0otteseR

3RMEMyradnoceS

dnammoC

elbanEsailA

W/Ryromemgnihctamrofmsinahcemnoitceteds'egdirbehtslortnoC

.ecafretniyradnocesnorotaitinimorfelcycyrterdaer

tcaxeebotsahdnammoC=0

MRMEMroLRMEMottnelaviuqesiRMEM=1

0otteseR

devreseRW/R

0otteseR

devreseRW/R

0otteseR

0yradnoceS

daeRerP

W/R.yradnocesnodnammocRMEMrofdaererom1elbanE

elbasid=0

elbane=1

0otteseR

Page 77

PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

13.2.45 Config Register 1 or 2: Master Timeout Counter Register (read/write, bit 31-16; offset 74h)

This register holds the maximum number of PCI clocks that PI7C7100 will wait for initiator to retry the same cycle before reporting timeout. Default is 8000h.

13.2.46 Config Register 1 or 2: Retry Counter Register (read/write, bit 31-0; offset 78h)

This register holds the maximum number of attempts that PI7C7100 will try before reporting retry timeout. Default is 0100_0000h.

13.2.47 Config Register 1 or 2: Sampling Timer Register (read/write, bit 31-0; offset 7Ch)

This register set the duration (in PCI clocks) during which PI7C7100 will record the number of successful transactions for performance evaluation. The recording will start right after this register is programmed and will be cleared after the timer expires. The maximum period is 128 seconds. Reset to 0000_0000h.

13.2.48 Config Register 1 or 2: Successful I/O Read Count Register (read/write, bit 31-0; offset 80h)

This register stores the successful I/O read count on the secondary interface which will be updated when the sampling timer is active. Reset to 0000_0000h.

13.2.49 Config Register 1 or 2: Successful I/O Write Count Register (read/write, bit 31-0; offset 84h)

This register stores the successful I/O write count on the secondary interface which will be updated when the sampling timer is active. Reset to 0000_0000h.

13.2.50 Config Register 1 or 2: Successful Memory Read Count Register (read/write, bit 31-0; offset 88h)

This register stores the successful memory read count on the secondary interface which will be updated when the sampling timer is active. Reset to 0000_0000h.

13.2.51 Config Register 1 or 2: Successful Memory Write Count Register (read/write, bit 31-0; offset 8Ch)

This register stores the successful memory write count on the secondary interface which will be updated when the sampling timer is active. Reset to 0000_0000h.

13.2.52 Config Register 1: Primary Successful I/O Read Count Register (read/write, bit 31-0; offset 90h)

This register stores the successful I/O read count on the primary interface which will be updated when the sampling timer is active. Reset to 0000_0000h.

13.2.53 Config Register 1: Primary Successful I/O Write Count Register (read/write, bit 31-0; offset 94h)

This register stores the successful I/O write count on the primary interface which will be updated when the sampling timer is active. Reset to 0000_0000h.

13.2.54 Config Register 1: Primary Successful Memory Read Count Register (read/write, bit 31-0; offset 98h)

This register stores the successful memory read count on the primary interface which will be updated when the sampling timer is active. Reset to 0000_0000h.

13.2.55 Config Register 1: Primary Successful Memory Write Count Register (read/write, bit 31-0; offset 9Ch)

This register stores the successful memory write count on the primary interface which will be updated when the sampling timer is active. Reset to 0000_0000h.

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PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

A target then has up to three cycles to respond before subtractive decoding is initiated. If the target detects an address hit, it should assert its DEVSEL# signal in the cycle corresponding to the values of bits 9 and 10 in the Configuration Status Register.

Termination of a PCI cycle can occur in a number of ways. Normal termination begins by the initiator (master) de-asserting FRAME# with IRDY# being asserted (or remaining asserted) on the same cycle. The cycle completes when TRDY# and IRDY# are both asserted simultaneously. The target should de-assert TRDY# for one cycle following final assertion (sustained 3-state signal).

14.2 Transaction Ordering

To maintain data coherency and consistency, PI7C7100 complies with the ordering rules put forth in the PCI Local Bus Specification, Rev 2.1. The following table summarizes the ordering relationship of all the transactions through the bridge.

PMW - Posted write (either memory write or memory write & invalidate) DRR - Delayed read request (all memory read, I/O read & configuration read) DWR - Delayed write request (I/O write & configuration write) DRC - Delayed read completion (all memory read, I/O read & configuration read) DWC - Delayed write completion (I/O write & configuration write )

14. Bridge Behavior

A PCI cycle is initiated by asserting the FRAME# signal. In a bridge, there are a number of possibilities. Those possibilities are summarized in the table below:

14.1 Bridge Actions for Various Cycle Types

rotaitinItegraTesnopseR

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Page 79

PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

Cycle type shown on each row is the subsequent cycle after the previous shown on the column.

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WMP

1nmuloC

RRD

2nmuloC

RWD

3nmuloC

CRD

4nmuloC

CWD

5nmuloC

)1woR(WMPoNseYseYseYseY

)2woR(RRDoNoNoNseYseY

)3woR(RWDoNoNoNseYseY

)4woR(CRDoNseYseYoNoN

)5woR(CWDseYseYseYoNoN

In Row 1 Column 1, PMW cannot pass the previous PMW and that means they must complete on the target bus in the order in which they were received in the initiator bus.

In Row 2 Column 1, DRR cannot pass the previous PMW and that means the previous PMW heading to the same direction must be completed before the DRR can be attempted on the target bus.

In Row 1 Column 2, PMW can pass the previous DRR as long as the DRR reaches the head of the delayed transaction queue.

14.3 Abnormal Termination (Initiated by Bridge Master)

14.3.1 Master Abort

Master abort indicates that when PI7C7100 acts as a master and receives no response (i.e., no target asserts P_DEVSEL# or S1_DEVSEL# or S2_DEVSEL#) from a target, the bridge de-asserts FRAME# and then de-asserts IRDY#.

14.3.2 Parity and Error Reporting

Parity must be checked for all addresses and write data. Parity is defined on the P_PAR, S1_PAR, and S2_PAR signals. Parity should be even (i.e. an even number of ‘1’s) across AD, CBE, and PAR. Parity information on PAR is valid the cycle after AD and CBE are valid. For reads, even parity must be generated using the initiators CBE signals combined with the read data. Again, the PAR signal corresponds to read data from the previous data phase cycle.

14.3.3 Reporting Parity Errors

For all address phases, if a parity error is detected, the error should be reported on the P_SERR# signal by asserting P_SERR# for one cycle and then 3-stating two cycles after the bad address. P_SERR# can only be asserted if bit 6 and 8 in the Command Register are both set to 1. For write data phases, a parity error should be reported by asserting the P_PERR# signal two cycles after the data phase and should remain asserted for one cycle when bit 8 in the Command register is set to a 1. The target reports any type of data parity errors during write cycles, while the master reports data parity errors during read cycles.

Detection of an address parity error will cause the PCI-to-PCI Bridge target to not claim the bus (P_DEVSEL# remains inactive) and the cycle will then terminate with a Master Abort. When the bridge is acting as master, a data parity error during a read cycle results in the bridge master initiating a Master Abort.

14.3.4 Secondary IDSEL mapping

When PI7C7100 detects a Type 1 configuration transaction for a device connected to the secondary, it translates the Type 1 transaction to Type 0 transaction on the downstream interface. Type 1 configuration format uses a 5-bit field at P_AD[15:11] as a device number. This is translated to S1_AD[31:16] or S2_AD[31:16] by PI7C7100.

Page 80

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PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

15. IEEE 1 149.1 Compatible JTAG Controller

An IEEE 1149.1 compatible Test Access Port (TAP) controller and associated TAP pins are provided to support boundary scan in PI7C7100 for board-level continuity test and diagnostics. The TAP pins assigned are TCK, TDI, TDO, TMS and TRST#. All digital input, output, input/output pins are tested except TAP pins and clock pin.

The IEEE 1149.1 Test Logic consists of a TAP controller, an instruction register, and a group of test data registers including Bypass, Device Identification and Boundary Scan registers. The TAP controller is a synchronous 16 state machine driven by the Test Clock (TCK) and the Test Mode Select (TMS) pins. An independent power on reset circuit is provided to ensure the machine is in TEST_LOGIC_RESET state at power-up. The JTAG signal lines are not active when the PCI resource is operating PCI bus cycles.

PI7C7100 implements 3 basic instructions: BYPASS, SAMPLE/PRELOAD, EXTEST.

15.1 Boundary Scan Architecture

Boundary-scan test logic consists of a boundary-scan register and support logic. These are accessed through a Test Access Port (TAP). The TAP provides a simple serial interface that allows all processor signal pins to be driven and/or sampled, thereby providing direct control and monitoring of processor pins at the system level.

This mode of operation is valuable for design debugging and fault diagnosis since it permits examination of connections not normally accessible to the test system. The following subsections describe the boundary-scan test logic elements: TAP pins, instruction register, test data registers and TAP controller. Figure 15-1 illustrates how these pieces fit together to form the JTAG unit.

15.1.1 TAP Pins

The PI7C7100’s TAP pins form a serial port composed of four input connections (TMS, TCK, TRST# and TDI) and one output connection (TDO). These pins are described in Table 15-1. The TAP pins provide access to the instruction register and the test data registers.

15.1.2 Instruction Register

The Instruction Register (IR) holds instruction codes. These codes are shifted in through the Test Data Input (TDI) pin. The instruction codes are used to select the specific test operation to be performed and the test data register to be accessed.

The instruction register is a parallel-loadable, master/slave-configured 2-bit wide, serial-shift register with latched outputs. Data is shifted into and out of the IR serially through the TDI pin clocked by the rising edge of TCK. The shifted-in instruction becomes active upon latching from the master stage to the slave stage. At that time the IR outputs along with the TAP finite state machine outputs are decoded to select and control the test data register selected by that instruction. Upon latching, all actions caused by any previous instructions terminate.

Boundary-Scan Register

Control and Clock Signals

TAP

Controller

Instruction

Bypass Register

TDO

TDI

TMS

TCK

TRST#

TAP Pins PI7C7100 System Pins

Figure 15-1. Test Access Port Block Diagram

Page 81

PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

The instruction determines the test to be performed, the test data register to be accessed, or both. The IR is two bits wide. When the IR is selected, the most significant bit is connected to TDI, and the least significant bit is connected to TDO. The value presented on the TDI pin is shifted into the IR on each rising edge of TCK. The TAP controller captures fixed parallel data (01 binary ). When a new instruction is shifted in through TDI, the value 01 (binary) is always shifted out through TDO, least significant bit first. This helps identify instructions in a long chain of serial data from several devices.

Upon activation of the TRST# reset pin, the latched instruction asynchronously changes to the idcode instruction. When the TAP controller moves into the test state other than by reset activation, the opcode changes as TDI shifts, and becomes active on the falling edge of TCK.

15.2 Boundary-Scan Instruction Set

The PI7C7100 supports three mandatory boundary-scan instructions (bypass, sample/preload and extest). The table shown below lists the PI7C7100’s boundary-scan instruction codes. The “reserved” code should not be used.

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emaNnoitcurtsnIedoCnoitcurtsnI

)yranib(

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00tsetxe01devreser

10daolerp/elpmas11ssapyb

/noitcurtsnI

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)yranib(noitpircseD

tsetxe

1.9411EEEI

deriuqeR

00 ffodnastcennocretnilevel-draobyllacipyt,yrtiucriclanretxefognitsetsetaitinitsetxE

.ODTdnaIDTneewtebretsigernacs-yradnuobehtstcennoctsetxe.yrtiucricpihc

otnidetfihsseulavybnevirderaseulavniplangistuptuolla,detcelessitsetxEnehW

,oslA.KCTfoegdegnillafehtnoylnoegnahcyamdnaretsigernacs-yradnuobeht

ehtotnidedaolebtsumsetatsniptupnimetsyslla,detcelessitsetxenehw

.KCTfoegde-gnisirehtnoretsigernacs-yradnuob

/elpmas

daolerp

1.9411EEEI

deriuqeR

10:snoitcnufowtsmrofrepdaolerp/elpmaS

tuohtiwKCTfoegdegnisirehtnoderutpacsinoitcurtsnielpmasehtfotohspansA

retsigernacs-yradnuobsesuacnoitcurtsniehT.noitarepolamronhtiwgnirefretni

.nevirdgniebeulavehtelpmasotstuptuohtiwdetaicossasllec

derrefsnartsisllecnacs-yradnuobehtnidlehatadehtKCTfoegdegnillafehtnO•

metsysehtotdeilppasiataddehctalevalsehtyllacipyT.sllecretsigerevalsehtot

.noitcurtsnitsetxeehtaivstuptuo

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1.9411EEEI

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01devreseR

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1.9411EEEI

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11 0.snipODTdnaIDTneewtebretsigerssapybtib-enoehtstcelesnoitcurtsnissapyB

sihtelihW.retsigerssapybehtsesseccatahtnoitcurtsniylnoehtsi)yranib(

metsysnotceffeonevahsretsigeratadtsetrehtolla,tceffenisinoitcurtsni

riehtmrofrepytilanoitcnufmetsysdnatsethtobhtiwsretsigeratadtseT.noitarepo

.detcelessinoitcurtsnisihtnehwsnoitcnufmetsys

Table 15-1. TAP Pins

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PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

15.3 TAP Test Data Registers

The PI7C7100 contains two test data registers (bypass and boundary-scan). Each test data register selected by the TAP controller is connected serially between TDI and TDO. TDI is connected to the test data register’s most significant bit. TDO is connected to the least significant bit. Data is shifted one bit position within the register towards TDO on each rising edge of TCK. While any register is selected, data is transferred from TDI to TDO without inversion. The following sections describe each of the test data registers.

15.4 Bypass Register

The required bypass register, a one-bit shift register, provides the shortest path between TDI and TDO when a bypass instruction is in effect. This allows rapid movement of test data to and from other components on the board. This path can be selected when no test operation is being performed on the PI7C7100.

15.5 Boundary-Scan Register

The boundary-scan register contains a cell for each pin as well as control cells for I/O and the high-impedance pin. Table 15-2 shows the bit order of the PI7C7100 boundary-scan register. All table cells that contain “Control” select the

direction of bidirectional pins or high-impedance output pins. When a “0” is loaded into the control cell, the associated pin(s) are high-impedance or selected as input.

The boundary-scan register is a required set of serial-shiftable register cells, configured in master/slave stages and connected between each of the PI7C7100’s pins and on-chip system logic. The VDD, GND, PLL, AGND, AVDD and JTAG pins are NOT in the boundary-scan chain.

The boundary-scan register cells are dedicated logic and do not have any system function. Data may be loaded into the boundary-scan register master cells from the device input pins and output pin-drivers in parallel by the mandatory sample/ preload and extest instructions. Parallel loading takes place on the rising edge of TCK.

Data may be scanned into the boundary-scan register serially via the TDI serial input pin, clocked by the rising edge of TCK. When the required data has been loaded into the master-cell stages, it can be driven into the system logic at input pins or onto the output pins on the falling edge of TCK state. Data may also be shifted out of the boundary-scan register by means of the TDO serial output pin at the falling edge of TCK.

15.6 TAP Controller

The TAP (Test Access Port) controller is a 4-state synchronous finite state machine that controls the sequence of test logic operations. The TAP can be controlled via a bus master. The bus master can be either automatic test equipment or a component (i.e., PLD) that interfaces to the TAP. The TAP controller changes state only in response to a rising edge of TCK. The value of the test mode state (TMS) input signal at a rising edge of TCK controls the sequence of state changes. The TAP controller is initialized after power-up by applying a low to the TRST# pin. In addition, the TAP controller can be initialized by applying a high signal level on the TMS input for a minimum of five TCK periods.

For greater detail on the behavior of the TAP controller, test logic in each controller state and the state machine and public instructions, refer to the IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture document (available from the IEEE).

Page 83

PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

redrOsemaNniPepyT

1]13-02[DA_2Selbanelortnoc

2]12[DA_2Stuptuo 3]12[DA_2Stupni 4#RREP_2Selbanelortnoc 5#RREP_2Stuptuo 6#RREP_2Stupni 7]91-8[DA_2Selbanelortnoc 8]61[DA_2Stuptuo

9]61[DA_2Stupni

01#EMARF_2Selbanelortnoc 11#EMARF_2Stuptuo 21#EMARF_2Stupni 31#YDRT_2S/#LESVED_2Selbanelortnoc 41#LESVED_2Stuptuo 51#LESVED_2Stupni 61]91[DA_2Stuptuo 71]91[DA_2Stupni 81]71[DA_2Stuptuo 91]71[DA_2Stupni 02]81[DA_2Stuptuo 12]81[DA_2Stupni 22]02[DA_2Stuptuo 32]02[DA_2Stupni 42]22[DA_2Stuptuo 52]22[DA_2Stupni 62]42[DA_2Stuptuo 72]42[DA_2Stupni 82]32[DA_2Stuptuo 92]32[DA_2Stupni 03]3-0[EBC_2Selbanelortnoc 13]3[EBC_2Stuptuo 23]3[EBC_2Stupni 33]52[DA_2Stuptuo 43]52[DA_2Stupni 53]62[DA_2Stuptuo

redrOsemaNniPepyT

63]62[DA_2Stupni 73]82[DA_2Stuptuo 83]82[DA_2Stupni 93]72[DA_2Stuptuo 04]72[DA_2Stupni 14]92[DA_2Stuptuo 24]92[DA_2Stupni 34]03[DA_2Stuptuo

44]03[DA_2Stupni 54]13[DA_2Stuptuo 64]13[DA_2Stupni 74#]0[TNG_2Selbanelortnoc 84#]0[TNG_2Stuptuo 94#]0[QER_2Stupni 05#]1[QER_2Stupni 15#]1[TNG_2Stuptuo 25#]2[TNG_2Stuptuo 35#]2[QER_2Stupni 45#]3[QER_2Stupni 55#]3[TNG_2Stuptuo 65#]4[TNG_2Stuptuo 75#]4[QER_2Stupni 85#]5[QER_2Stupni 95#]5[TNG_2Stuptuo 06#]6[TNG_2Stuptuo 16#]6[QER_2Stupni 26#]7[QER_2Stupni 36#]7[TNG_2Stuptuo 46#TESER_2Stuptuo 56#NFC_Stupni 66#NE_1Stupni 76#NE_2Stupni 86#MT_NACStupni 96NE_NACStupni 07MT_LLPtupni

redrOsemaNniPepyT

17SSAPYBtupni 27#HSULFtupni 37#TESER_Ptupni 47#TNG_Ptupni 57#QER_Pelbanelortnoc 67#QER_Ptuptuo 77]13-02[DA_Pelbanelortnoc

87]03[DA_Ptuptuo 97]03[DA_Ptupni 08]13[DA_Ptuptuo 18]13[DA_Ptupni 28]72[DA_Ptuptuo 38]72[DA_Ptupni 48]62[DA_Ptuptuo 58]62[DA_Ptupni 68]82[DA_Ptuptuo 78]82[DA_Ptupni 88]92[DA_Ptuptuo 98]92[DA_Ptupni 09]3-0[EBC_Pelbanelortnoc 19]3[EBC_Ptuptuo 29]3[EBC_Ptupni 39]42[DA_Ptuptuo 49]42[DA_Ptupni 59]52[DA_Ptuptuo 69]52[DA_Ptupni 79]32[DA_Ptuptuo 89]32[DA_Ptupni 99]22[DA_Ptuptuo

001]22[DA_Ptupni 101LESDI_Ptupni 201]12[DA_Ptuptuo 301]12[DA_Ptupni 401]02[DA_Ptuptuo 501]02[DA_Ptupni

Table 15-2. JTAG Boundary Register Order

Page 84

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PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

redrOsemaNniPepyT

601]91-8[DA_Pelbanelortnoc 701]91[DA_Ptuptuo 801]91[DA_Ptupni

901]81[DA_Ptuptuo 011]81[DA_Ptupni 111]71[DA_Ptuptuo 211]71[DA_Ptupni 311]61[DA_Ptuptuo 411]61[DA_Ptupni 511]2[EBC_Ptuptuo 611]2[EBC_Ptupni 711#EMARF_Pelbanelortnoc 811#EMARF_Ptuptuo 911#EMARF_Ptupni

021#YDRI_Pelbanelortnoc

121#YDRI_Ptuptuo

221#YDRI_Ptupni

321#YDRT_P/LESVED_Pelbanelortnoc

421#YDRT_Ptuptuo

521#YDRT_Ptupni

621#LESVED_Ptuptuo

721#LESVED_Ptupni

821#POTS_Pelbanelortnoc

921#POTS_Ptuptuo

031#POTS_Ptupni

131#RREP_Pelbanelortnoc

231#RREP_Ptuptuo

331#RREP_Ptupni

431#KCOL_Pelbanelortnoc

531#KCOL_Ptuptuo

631#KCOL_Ptupni

731#RRES_Pelbanelortnoc

831#RRES_Ptuptuo

931]31[DA_Ptuptuo

041]31[DA_Ptupni

redrOsemaNniPepyT

141]41[DA_Ptuptuo 241]41[DA_Ptupni 341]11[DA_Ptuptuo 441]11[DA_Ptupni 541]51[DA_Ptuptuo 641]51[DA_Ptupni 741]21[DA_Ptuptuo

841]21[DA_Ptupni 941]8[DA_Ptuptuo 051]8[DA_Ptupni 151]1[EBC_Ptuptuo 251]1[EBC_Ptupni 351]9[DA_Ptuptuo 451]9[DA_Ptupni 551]7-0[DA_Pelbanelortnoc 651]5[DA_Ptuptuo 751]5[DA_Ptupni 851NE66M_Ptupni 951]6[DA_Ptuptuo 061]6[DA_Ptupni 161]2[DA_Ptuptuo 261]2[DA_Ptupni 361RAP_Pelbanelortnoc 461RAP_Ptuptuo 561RAP_Ptupni 661]0[DA_Ptuptuo 761]0[DA_Ptupni 861]0[EBC_Ptuptuo 961]0[EBC_Ptupni 071]7[DA_Ptuptuo 171]7[DA_Ptupni 271]01[DA_Ptuptuo 371]01[DA_Ptupni 471]1[DA_Ptuptuo 571]1[DA_Ptupni

redrOsemaNniPepyT

671]3[DA_Ptuptuo 771]3[DA_Ptupni 871]4[DA_Ptuptuo 971]4[DA_Ptupni 081]7-0[DA_1Selbanelortnoc 181]0[DA_1Stuptuo 281]0[DA_1Stupni

381]1[DA_1Stuptuo 481]1[DA_1Stupni 581]2[DA_1Stuptuo 681]2[DA_1Stupni 781]5[DA_1Stuptuo 881]5[DA_1Stupni 981]3[DA_1Stuptuo 091]3[DA_1Stupni 191]4[DA_1Stuptuo 291]4[DA_1Stupni 391]3-0[EBC_1Selbanelortnoc 491]0[EBC_1Stuptuo 591]0[EBC_1Stupni 691]7[DA_1Stuptuo 791]7[DA_1Stupni 891]6[DA_1Stuptuo 991]6[DA_1Stupni

002]91-8[DA_1Selbanelortnoc 102]8[DA_1Stuptuo 202]8[DA_1Stupni 302]9[DA_1Stuptuo 402]9[DA_1Stupni 502]01[DA_1Stuptuo 602]01[DA_1Stupni 702]11[DA_1Stuptuo 802]11[DA_1Stupni 902]21[DA_1Stuptuo 012]21[DA_1Stupni

Table 15-2. JTAG Boundary Register Order (continued)

Page 85

PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

redrOsemaNniPepyT

112]41[DA_1Stuptuo

212]41[DA_1Stupni 312]31[DA_1Stuptuo 412]31[DA_1Stupni 512]51[DA_1Stuptuo 612]51[DA_1Stupni 712#RRES_1Stupni 812RAP_1Selbanelortnoc 912RAP_1Stuptuo

022RAP_1Stupni 122]1[EBC_1Stuptuo 222]1[EBC_1Stupni 322#YDRT_1S/#LESVED_1Selbanelortnoc 422#LESVED_1Stuptuo 522#LESVED_1Stupni 622#POTS_1Selbanelortnoc 722#POTS_1Stuptuo 822#POTS_1Stupni 922#KCOL_1Selbanelortnoc 032#KCOL_1Stuptuo 132#KCOL_1Stupni 232#RREP_1Selbanelortnoc 332#RREP_1Stuptuo 432#RREP_1Stupni 532#EMARF_1Selbanelortnoc 632#EMARF_1Stuptuo 732#EMARF_1Stupni 832#YDRI_1Selbanelortnoc 932#YDRI_1Stuptuo 042#YDRI_1Stupni 142#YDRT_1Stuptuo 242#YDRT_1Stupni 342#]71[DA_1Stuptuo 442#]71[DA_1Stupni 542#]61[DA_1Stuptuo

redrOsemaNniPepyT

642#]61[DA_1Stupni 742]13-02[DA_1Selbanelortnoc 842]02[DA_1Stuptuo 942]02[DA_1Stupni 052]2[EBC_1Stuptuo 152]2[EBC_1Stupni 252]91[DA_1Stuptuo

352]91[DA_1Stupni 452]3[EBC_1Stuptuo 552]3[EBC_1Stupni 652]32[DA_1Stuptuo 752]32[DA_1Stupni 852]62[DA_1Stuptuo 952]62[DA_1Stupni 062]22[DA_1Stuptuo 162]22[DA_1Stupni 262]52[DA_1Stuptuo 362]52[DA_1Stupni 462]92[DA_1Stuptuo 562]92[DA_1Stupni 662]12[DA_1Stuptuo 762]12[DA_1Stupni 862]82[DA_1Stuptuo 962]82[DA_1Stupni 072]03[DA_1Stuptuo 172]03[DA_1Stupni 272]13[DA_1Stuptuo 372]13[DA_1Stupni 472]72[DA_1Stuptuo 572]72[DA_1Stupni 672]42[DA_1Stuptuo 772]42[DA_1Stupni 872]81[DA_1Stuptuo 972]81[DA_1Stupni 082#]0[TNG_1Selbanelortnoc

redrOsemaNniPepyT

182#]0[TNG_1Stuptuo 282#]0[QER_1Stupni 382#]1[QER_1Stupni 482#]1[TNG_1Stuptuo 582#]2[TNG_1Stuptuo 682#]2[QER_1Stupni 782#]3[QER_1Stupni

882#]3[TNG_1Stuptuo 982#]4[TNG_1Stuptuo 092#]4[QER_1Stupni 192#]5[QER_1Stupni 292#]5[TNG_1Stuptuo 392#]6[TNG_1Stuptuo 492#]6[QER_1Stupni 592#]7[QER_1Stupni 692#]7[TNG_1Stuptuo 792#TESER_1Stuptuo 892]7-0[DA_2Selbanelortnoc 992]0[DA_2Stuptuo 003]0[DA_2Stupni 103]1[DA_2Stuptuo 203]1[DA_2Stupni 303]2[DA_2Stuptuo 403]2[DA_2Stupni 503]3[DA_2Stuptuo 603]3[DA_2Stupni 703]4[DA_2Stuptuo 803]4[DA_2Stupni 903]5[DA_2Stuptuo 013]5[DA_2Stupni 113]6[DA_2Stuptuo 213]6[DA_2Stupni 313]7[DA_2Stuptuo 413]7[DA_2Stupni 513]0[EBC_2Stuptuo

Table 15-2. JTAG Boundary Register Order (continued)

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PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

redrOsemaNniPepyT

613]0[EBC_2Stupni 713]8[DA_2Stuptuo 813]8[DA_2Stupni 913]01[DA_2Stuptuo 023]01[DA_2Stupni 123]9[DA_2Stuptuo 223]9[DA_2Stupni

323]11[DA_2Stuptuo 423]11[DA_2Stupni 523NE66M_Stupni 623]21[DA_2Stuptuo 723]21[DA_2Stupni 823]41[DA_2Stuptuo 923]41[DA_2Stupni 033]1[EBC_2Stuptuo 133]1[EBC_2Stupni 233]51[DA_2Stuptuo 333]51[DA_2Stupni 433RAP_2Selbanelortnoc

redrOsemaNniPepyT

533RAP_2Stuptuo 633RAP_2Stupni 733#RRES_2Stupni 833#KCOL_2Selbanelortnoc 933#KCOL_2Stuptuo 043#KCOL_2Stupni 143#YDRT_2Stuptuo

243#YDRT_2Stupni 343#POTS_2Selbanelortnoc 443#POTS_2Stuptuo 543#POTS_2Stupni 643#YDRI_2Selbanelortnoc 743#YDRI_2Stuptuo 843#YDRI_2Stupni 943]2[EBC_2Stuptuo 053]2[EBC_2Stupni 153]31[DA_2Stuptuo 253]31[DA_2Stupni

Table 15-2. JTAG Boundary Register Order (continued)

Page 87

PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

Note:

Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.

16. Electrical and Timing Specifications

16.1 Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested).

erutarepmeTegarotS C°051+otC°56–

deilpparewoPhtiwerutarepmeTtneibmA C°07+otC°0

VA&stupnI(slaitnetoPdnuorGotegatloVylppuS

)ylnoV6.3+otV3.0–

egatloVtupnICD V6.3+otV5.0–

16.2 3.3V DC Specifications

lobmySretemaraPnoitidnoC.niM.xaMstinUsetoN

,DD

egatloVylppuS36.3

egatloVHGIHtupnIV5.0

5.0+ 3

egatloVWOLtupnI5.0-3.0V

egatloVHGIHtupnISOMCV7.0

5.0+

egatloVWOLtupnISOMC5.0–3.0V

upi

egatloVpu-lluPtupnIV7.0

tnerruCegakaeLtupnIV<0

01±Aµ

egatloVHGIHtuptuOI

tuo

Aµ005–=V9.0

egatloVWOLtuptuOI

tuo

Aµ0051=1.0V

egatloVHGIHtuptuOSOMCI

tuo

Aµ005–=V

5.02

egatloVWOLtuptuOSOMCI

tuo

Aµ0051=5.0

ecnaticapaCniPtupnI 01

klc

ecnaticapaCniPKLC521

LESDI

ecnaticapaCniPLESDI 8

nip

ecnatcudnIniP 02Hn

Notes:

1. CMOS Input pins: S_CFN#, TCK, TMS, TDI, TRST#, SCAN_EN, SCAN_TM#

2. CMOS Output pin: TDO

3. PCI pins: P_AD[31:0], P_CBE[3:0], P_PAR, P_FRAME#, P_IRDY#, P_TRDY#, P_DEVSEL#, P_STOP#, P_LOCK#, PIDSEL#, P_PERR#, P_SERR#, P_REQ#, P_GNT#, P_RESET#, S1_AD[31:0], S2_AD[31:0], S1_CBE[3:0], S2_CBE[3:0], S1_PAR, S2_PAR, S1_FRAME#, S2_FRAME#, S1_IRDY#, S2_IRDY#, S1_TRDY#, S2_TRDY#, S1_DEVSEL#, S2_DEVSEL#, S1_STOP#, S2_STOP#, S1_LOCK#, S2_LOCK#, S1_PERR#, S2_PERR#, S1_SERR#, S2_SERR#, S1_REQ[7:0]#, S2_REQ[7:0]#, S1_GNT[7:0]#, S2_GNT[7:0], S1_RESET#, S2_RESET#, S1_EN, S2_EN, P_FLUSH#.

Page 88

12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456

PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

lobmySretemaraPnoitidnoC.niM.xaMstinU

WEKS

]0:51[TUOKLC_SgnomaWEKS00.1

YALED

]0:51[TUOKLC_SdnaKLCPneewtebYALEDdaolFp02701

ELCYC

emitelcyc]0:51[TUOKLC_S,KLCP03

HGIH

emitHGIH]0:51[TUOKLC_S,KLCP11

WOL

emitWOL]0:51[TUOKLC_S,KLCP11

16.4 Primary and Secondary Buses at 33 MHz Clock Timing

lobmySretemaraP.niM.xaMstinU

slangisdesub-KLCotemitputestupnI

3,2,1

7–

)ptp(us

tniop-ot-tniop-KLCotemitputestupnI

3,2,1

21,01–

KLCmorfemitdlohlangistupnI

2,1

0–

lav

slangisdesub-yaleddilavlangisotKLC

3,2,1

211

)ptp(lav

tniop-ot-tniop-yaleddilavlangisotKLC

3,2,1

221

yaledevitcaottaolF

2,1

2–

ffo

yaledtaolfotevitcA

2,1

–82

test

val

Valid

test

– 1.5V for 5V signals: 0.4 V

for 3.3V signals

Valid

Input

Note:

Output

CLK

off

inval

Figure 16-1. PCI Signal Timing Measurement Conditions

16.5 Power Consumption

retemaraPlacipyTstinU

noitpmusnoCrewoP006Wm

I,tnerruCylppuS

281Am

1. See Figure 16-1 PCI Signal Timing Measurement Conditions.

2. All primary interface signals are synchronized to P_CLK. All secondary interface signals are synchronized to S_CLKOUT.

3. Point-to-point signals are p_req#, s1_req#<7:0>, s2_req#<7:0>, p_gnt#, s1_gnt#<7:0>, and s2_gnt#<7:0>. Bused signals are p_ad, p_cbe#, p_par, p_perr#, p_serr#, p_frame#, p_irdy#, p_trdy#, p_lock#, p_devsel#, p_stop#, p_idsel, s1_ad, s1_cbe#, s1_par, s1_perr#, s1_serr#, s1_frame#, s1_irdy#, s1_trdy#, s1_lock#, s1_devsel#, s1_stop#, s2_ad, s2_cbe#, s3_par, s2_perr#, s2_serr#, s2_frame#, s2_irdy#, s2_trdy#, s2_lock#, s2_devsel#, and s2_stop#.

16.3 3.3V AC Specifications

Page 89

PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

PIN #1 CORNER

0.15

19 18 17 16 15 14 13 12 11 10 9 8 7

65432

B C D E F

H J K L

N P R T U V

8.00

4 x 45° CHAMFER

2.33 Min. / 3.50Max.

27.00 ± 0.15

ø1.0 (3X)

0.60 ± 0.1

30 ± 2°

SEATING PLANE

1.27

1.44

BSC

24.00 ± 0.1

256 x ø0.75 ± 0.15

0.56 ± 0.05

1.17 ± 0.1

0.30 S

0.10 S

S SCCB

27.00 ± 0.15

(4X)

17. 256-Pin PBGA Package

TOP

BOTTOM

17.1 Part Number Ordering Information

traPegakcaP-niPerutarepmeT

ANC0017C7IPAGBP-652C°07+otC°0

Figure 17-1. 256-Pin PBGA Package

Page 90

12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456

PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

Page 91

PI7C7100 3-Port PCI Bridge

Appendix A

Timing Diagrams

Page 92

Appendix A

PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

Page 93

Appendix A

PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

Addr

Data

Byte Enables

012345 6789101112

P_CLK

P_AD [31:0]

P_CBE [3:0]

P_FRAME_L

P_IRDY_L

P_TRDY_L P_STOP_L

P_DEVSEL_L

P_IDSEL

13 14 15 16 17 18 19 20 21 22

Figure 2. Configuration Write Transaction

Addr

Data

Byte Enables

012345 6789101112

P_CLK

P_AD [31:0]

P_CBE [3:0]

P_FRAME_L

P_IRDY_L

P_TRDY_L P_STOP_L

P_DEVSEL_L

P_IDSEL

13 14 15 16 17 18 19 20 21 22

Figure 1. Configuration Read Transaction

Addr

Data

Byte Enables

Addr

Byte Enables

Addr

Data

Byte Enables

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

P_CLK

P_AD [31:0]

P_CBE [3:0]

P_FRAME_L

P_IRDY_L P_TRDY_L

P_STOP_L

P_DEVSEL_L

P_IDSEL

S_CLKOUT[0]

S_AD[31:0]

S_CBE[3:0]

S_FRAME_L

S_IRDY_L S_TRDY_L S_STOP_L

S_DEVSEL_L

S_GNT_L

S_REQ_L

P_GNT_L

P_REQ_L

Figure 3. Type 1 to Type 0 Configuration Read Transaction ( P --> S )

Page 94

Appendix A

PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

Addr

Data

Byte Enables

Addr

Data

Byte Enables

Addr

Data

Byte Enables

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

P_CLK

P_AD [31:0]

P_CBE [3:0]

P_FRAME_L

P_IRDY_L P_TRDY_L

P_STOP_L

P_DEVSEL_L

P_IDSEL

S_CLKOUT[0]

S_AD[31:0]

S_CBE[3:0]

S_FRAME_L

S_IRDY_L S_TRDY_L S_STOP_L

S_DEVSEL_L

S_GNT_L S_REQ_L

P_GNT_L P_REQ_L

Figure 4. Type 1 to Type 0 Configuration Write Transaction ( P --> S )

Addr

Data

Addr

Data

Byte Enables

Addr

Data

Byte Enables

Figure 5. Upstream Type 1 to Special Cycle Transaction

( S --> P )

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

P_CLK

P_AD [31:0]

P_CBE [3:0]

P_FRAME_L

P_IRDY_L

P_TRDY_L P_STOP_L

P_DEVSEL_L

S_CLKOUT[0]

S_AD[31:0]

S_CBE[3:0]

S_FRAME_L

S_IRDY_L

S_TRDY_L S_STOP_L

S_DEVSEL_L

S_GNT_L

S_REQ_L

P_GNT_L

P_REQ_L

Page 95

Appendix A

PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

Addr

Data

Byte Enables

Addr

Data

Byte Enables

Addr

Data

Byte Enables

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

P_CLK

P_AD [31:0]

P_CBE [3:0]

P_FRAME_L

P_IRDY_L

P_TRDY_L P_STOP_L

P_DEVSEL_L

S_CLKOUT[0]

S_AD[31:0]

S_CBE[3:0]

S_FRAME_L

S_IRDY_L S_TRDY_L S_STOP_L

S_DEVSEL_L

S_GNT_L

S_REQ_L

P_GNT_L

P_REQ_L

Figure 6. Downstream Type 1 to Special Cycle Transaction ( P --> S )

Addr Addr

Bytes Enables

Addr Addr Addr Data

Byte EnablesByte EnablesByte EnablesByte Enables

Addr Addr Addr Data

Byte EnablesByte EnablesByte Enables

Figure 7. Downstream Type1 to Type1 Configuration Read Transaction ( P --> S )

0 2 4 6 8 101214161820222426283032343638404244451 3 5 7 9 1113151719 21 2325 2729 3133353739 4143

P_CLK

P_AD [31:0]

P_CBE [3:0] P_FRAME_L

P_IRDY_L P_TRDY_L

P_STOP_L

P_DEVSEL_L

P_IDSEL

S_CLKOUT[0]

S_AD[31:0]

S_CBE[3:0]

S_FRAME_L

S_IRDY_L S_TRDY_L S_STOP_L

S_DEVSEL_L

S_GNT_L S_REQ_L

P_GNT_L P_REQ_L

Page 96

Appendix A

PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

Addr Addr

Addr Addr Addr

Byte Enables

Data

Byte Enables

Data

Byte Enables

Data

Byte Enables

Data

Byte Enables

Data

Byte Enables

Data

Byte Enables

Data

Byte Enables

Data

Figure 8. Downstream Type1 to Type1 Configuration Write Transaction ( P --> S )

0 2 4 6 8 101214161820222426283032343638404244451 3 5 7 9 1113151719 21 2325 2729 3133353739 4143

P_CLK

P_AD [31:0]

P_CBE [3:0] P_FRAME_L

P_IRDY_L

P_TRDY_L P_STOP_L

P_DEVSEL_L

P_IDSEL

S_CLKOUT[0]

S_AD[31:0]

S_CBE[3:0]

S_FRAME_L

S_IRDY_L S_TRDY_L S_STOP_L

S_DEVSEL_L

S_GNT_L S_REQ_L

P_GNT_L P_REQ_L

Byte Enables

Addr

DataData Data

Data

Data Data

Data

Addr Addr Addr

Byte Enables

Addr

DataData

Data

Data Data

Data

Figure 9. Upstream Delayed Burst Memory Read Transaction ( S --> P )

0 2 4 6 8 101214161820222426283032343638404244451 3 5 7 9 111315 1719 21 2325 2729 313335 3739 4143 46

0 2 4 6 8 101214161820222426283032343638404244451 3 5 7 9 111315 1719 21 2325 2729 313335 3739 4143

P_CLK

P_AD [31:0]

P_CBE [3:0]

P_FRAME_L

P_IRDY_L

P_TRDY_L P_STOP_L

P_DEVSEL_L

S_CLKOUT[0]

S_AD[31:0]

S_CBE[3:0]

S_FRAME_L

S_IRDY_L S_TRDY_L S_STOP_L

S_DEVSEL_L

S_GNT_L S_REQ_L

P_GNT_L P_REQ_L

Byte Enables Byte Enables Byte Enables

Page 97

Appendix A

PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

Addr Addr Addr

Byte Enables Byte Enables ByteEnables

Byte Enables

Addr

DataData

Data

Data Data

Data

Byte Enables

Addr

DataData Data

Data

Data Data

Data

Figure 10. Downstream Delayed Burst Memory Read Transaction ( P --> S )

0 2 4 6 8 1012141618 2022 2426 283032 3436 38404244451 3 5 7 9 111315171921232527293133353739 4143

0 2 4 6 8 1012141618202224 26283032343638404244451 3 5 7 9 1113151719 21 2325 2729 313335 3739 4143

P_CLK

P_AD [31:0]

P_CBE [3:0] P_FRAME_L

P_IRDY_L

P_TRDY_L P_STOP_L

P_DEVSEL_L

S_CLKOUT[0]

S_AD[31:0]

S_CBE[3:0]

S_FRAME_L

S_IRDY_L S_TRDY_L S_STOP_L

S_DEVSEL_L

S_GNT_L

S_REQ_L

P_GNT_L

P_REQ_L

Addr

Data

Byte Enables

Addr

Byte Enables

Addr

Data

Byte Enables

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

P_CLK

P_AD [31:0]

P_CBE [3:0]

P_FRAME_L

P_IRDY_L P_TRDY_L

P_STOP_L

P_DEVSEL_L

S_CLKOUT[0]

S_AD[31:0]

S_CBE[3:0]

S_FRAME_L

S_IRDY_L S_TRDY_L S_STOP_L

S_DEVSEL_L

S_GNT_L

S_REQ_L

P_GNT_L

P_REQ_L

Figure 11. Downstream Delayed Memory Read Transaction (P/33MHz-->S/33MHz)

Page 98

Appendix A

PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

Addr

Data

Addr

Data

Byte Enables

Addr

Byte Enables

Figure 12. Downstream Delayed Memory Read Transaction (S2/33MHz-->S1/33MHz)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

S_CLKOUT[0]

S1_AD [31:0]

S1_CBE [3:0]

S1_FRAME_L

S1_IRDY_L

S1_TRDY_L S1_STOP_L

S1_DEVSEL_L

S_CLKOUT[0]

S2_AD[31:0]

S2_CBE[3:0]

S2_FRAME_L

S2_IRDY_L

S2_TRDY_L S2_STOP_L

S2_DEVSEL_L

S2_GNT_L

S2_REQ_L

S1_GNT_L

S1_REQ_L

Addr

Data

Addr

Data

Byte Enables

Addr

Byte Enables

Figure 13. Downstream Delayed Memory Read Transaction (S1/33MHz-->S2/33MHz)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

S_CLKOUT[0]

S2_AD [31:0]

S2_CBE [3:0]

S2_FRAME_L

S2_IRDY_L

S2_TRDY_L S2_STOP_L

S2_DEVSEL_L

S_CLKOUT[0]

S1_AD[31:0]

S1_CBE[3:0]

S1_FRAME_L

S1_IRDY_L

S1_TRDY_L S1_STOP_L

S1_DEVSEL_L

S1_GNT_L

S1_REQ_L

S2_GNT_L

S2_REQ_L

Page 99

Appendix A

PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

Addr

Data

Addr

Data

Byte Enables

Addr

Byte Enables

Figure 14. Upstream Delayed Memory Read Transaction (S/33MHz-->P/33MHz)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

P_CLK

P_AD [31:0]

P_CBE [3:0] P_FRAME_L

P_IRDY_L

P_TRDY_L P_STOP_L

P_DEVSEL_L

S_CLKOUT[0]

S_AD[31:0]

S_CBE[3:0]

S_FRAME_L

S_IRDY_L

S_TRDY_L S_STOP_L

S_DEVSEL_L

S_GNT_L S_REQ_L

P_GNT_L P_REQ_L

Data

Byte Enables

Addr

Data

Byte Enables

Addr

Figure 15. Downstream Posted Memory Write Transaction (P/33MHz-->S/33MHz)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

P_CLK

P_AD [31:0]

P_CBE [3:0] P_FRAME_L

P_IRDY_L P_TRDY_L P_STOP_L

P_DEVSEL_L

S_CLKOUT[0]

S_AD[31:0]

S_CBE[3:0]

S_FRAME_L

S_IRDY_L S_TRDY_L S_STOP_L

S_DEVSEL_L

S_GNT_L S_REQ_L

P_GNT_L P_REQ_L

Page 100

Appendix A

PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

Addr

Data

Byte Enables

Addr

Figure 16. Downstream Posted Memory Write Transaction (S2/33MHz-->S1/33MHz)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

S_CLKOUT[0]

S1_AD [31:0]

S1_CBE [3:0]

S1_FRAME_L

S1_IRDY_L S1_TRDY_L S1_STOP_L

S1_DEVSEL_L

S_CLKOUT[0]

S2_AD[31:0]

S2_CBE[3:0]

S2_FRAME_L

S2_IRDY_L S2_TRDY_L S2_STOP_L

S2_DEVSEL_L

S2_GNT_L

S2_REQ_L

S1_GNT_L

S1_REQ_L

Addr

Data

Byte Enables

Addr

Figure 17. Downstream Posted Memory Write Transaction (S1/33MHz-->S2/33MHz)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

S_CLKOUT[0]

S2_AD [31:0]

S2_CBE [3:0]

S2_FRAME_L

S2_IRDY_L S2_TRDY_L S2_STOP_L

S2_DEVSEL_L

S_CLKOUT[0]

S1_AD[31:0]

S1_CBE[3:0]

S1_FRAME_L

S1_IRDY_L S1_TRDY_L S1_STOP_L

S1_DEVSEL_L

S1_GNT_L

S1_REQ_L

S2_GNT_L

S2_REQ_L