PERICOM PI74SSTU32864A Technical data

PI74SSTU32864A

TO OTHER CHANNELS

CK

CK

RST

1D

C1

R

QCKEA

QCKEB*

QODTA

1D

C1

R

Q1A

Q1B*

QCSB*

QCSA

1D

C1

R

1D

C1

R

QODTB*

V

REF

DCKE

DODT

DCS

CSR

D1

Note: Disabled in 1:1 configuration

0

1

25-Bit 1:1 or 14-Bit 1:2 Congurable

Registered Buffer

Features

• PI74SSTU32864A is designed for low-voltage operation,
V

= 1.8V

DD

• Supports Low Power Standby Operation

• Enhanced Signal Integrity for 1 and 2 Rank Modules

• All Inputs are SSTL_18 Compatible, except RST, C0, C1,
which are LVCMOS.

• Output drivers are optimized to drive DDR2 DIMM loads

• Designed for DDR2 Memory

• Packaging (Pb-free & Green available):

-96 Ball LFBGA (NB)

Block Diagram 1:2 Mode (Positive Logic)

Description

Pericom Semiconductor’s PI74SSTU32864A logic circuit is
produced using advanced CMOS technology. This 25-Bit 1:1 or
14-Bit 1:2 congurable registered buffer is designed for 1.7V to

1.9V VDD operation.

All clock and data inputs are compatible with the JEDEC standard
for SSTL_18. The control inputs are LVCMOS. All outputs are

1.8V LVCMOS drivers that have been optimized to drive the
DDR2 DIMM load.

The SSTU32864A operates from a differential clock (CK and
CK). Data is registered at the crossing of CK going high, and CK
going low.

The C0 input controls the pinout conguration of the 1:2 pinout
from A conguration (when LOW) to B conguration (when
HIGH). The C1 input controls the pinout conguration for 25-Bit
1:1 (when LOW) to 14-Bit 1:2 (when HIGH).

The device supports low-power standby operation. When the reset
input (RST) is low, the differential input receivers are disabled and
undriven (oating) data, clock and reference voltage (V
are allowed. In addition , when RST is low, all registers are reset,
and all outputs are forced low. The LVCMOS RST and Cn inputs
must always be held at a valid logic high or low level.

To ensure dened outputs from the register before a stable clock has
been supplied, RST must be held in the low state during power up.

In the DDR-II RDIMM application, RST is specied to be completely
asynchronous with respect to CK and CK. Therefore, no timing
relationship can be guaranteed between the two. When entering
reset, the register will be cleared and the outputs will be driven
low quickly, relative to the time to disable the differential input
receivers. However, when coming out of reset, the register will
become active quickly, relative to the time to enable the differential
input receivers.

As long as the data inputs are low, and the clock is stable during
the time from the low-to-high transition of RST until the input
receivers are fully enabled, the design of the SSTU32864A must
ensure that the outputs remain low, thus ensuring no glitches on
the output.

The device monitors both DCS and CSR inputs and will gate the
Qn outputs from changing states when both DCS and CSR inputs
are high. If either DCS or CSR input is low, the Qn outputs will
function normally. The RST input has priority over the DCS and CSR
control will force the outputs low. If the DCS control functionality
is not desired, then the CSR input can be hardwired to ground,
in which case, the set-up time requirement for DCS would be the
same as for the other D data inputs.

1

PS8743 08/02/04

REF

) inputs

Pin Conguration 1:1 Register (C0 = 0, C1 = 0)

1 2 3 4 5 6

A

B

DCKE NC V

REF

V

DD

QCKE NC

D2 D15 GND GND Q2 Q15

PI74SSTU32864A

25-Bit 1:1 or 14-Bit 1:2

Congurable Buffer

C

D

E

F

G

H

J

K

L

M

N

P

R

T

D3 D16 V

DD

V

DD

Q3 Q15

DODT NC GND GND QODT NC

D5 D17 V

DD

V

DD

Q5 Q17

D6 D18 GND GND Q6 Q18

NC RST V

DD

V

DD

C1 C0

CK DCS GND GND QCS NC

CK CSR V

DD

V

DD

ZOH ZOL

D8 D19 GND GND Q8 Q19

D9 D20 V

DD

V

DD

Q9 Q20

D10 D21 GND GND Q10 Q21

D11 D22 V

DD

V

DD

Q11 Q22

D12 D23 GND GND Q12 Q23

D13 D24 V

D14 D25 V

DD

REF

V

DD

V

DD

Q13 Q24

Q14 Q25

Pin Conguration 1:2 Register (C0 = 0, C1 = 1)

1 2 3 4 5 6

A

B

DCKE NC V

REF

V

QCKEA QCKEB

DD

D2 NC GND GND Q2A Q2B

C

D

E

F

G

H

K

L

M

N

P

R

T

D3 NC V

DD

V

DD

DODT NC GND GND QODTA Q4B

D5 NC V

DD

V

DD

D6 NC GND GND Q6A Q6B

NC RST V

DD

V

DD

CK DCS GND GND QCSA QCSB

J

CK CSR V

DD

V

DD

D8 NC GND GND Q8A Q8B

D9 NC V

DD

V

DD

D10 NC GND GND Q10A Q10B

D11 NC V

DD

V

DD

D12 NC GND GND Q12A Q12B

D13 NC V

D14 NC V

DD

REF

V

DD

V

DD

Q3A QODTB

Q5A Q5B

C1 C0

ZOH ZOL

Q9A Q9B

Q11A Q11B

Q13A Q13B

Q14A Q14B

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PS8743 08/02/04

Pin Conguration 1:2 Register (C0 = 1, C1 = 1)

1 2 3 4 5 6

A

B

D1 NC V

REF

V

DD

Q1A QB

D2 NC GND GND Q2A Q2B

PI74SSTU32864A

25-Bit 1:1 or 14-Bit 1:2

Congurable Buffer

C

D

E

F

G

H

J

K

L

M

N

P

R

T

D3 NC V

DD

V

DD

D4 NC GND GND Q4A Q4B

D5 NC V

DD

V

DD

D6 NC GND GND Q6A Q6B

NC RST V

DD

V

DD

CK DCS GND GND QCSA QCSB

CK CSR V

DD

V

DD

D8 NC GND GND Q8A Q8B

D9 NC V

DD

V

DD

D10 NC GND GND Q10A Q10B

DODT NC V

DD

V

QODTA QODTB

DD

D12 NC GND GND Q12A Q12B

D13 NC V

DCKE NC V

DD

REF

V

DD

V

QCKEA QCKEB

DD

NB 96-ball LFBGA (MO-205CC) Top View

Q3A Q3B

Q5A Q5B

C1 C0

ZOH ZOL

Q9A Q9B

Q13A Q13B

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PS8743 08/02/04

PI74SSTU32864A

25-Bit 1:1 or 14-Bit 1:2

Congurable Buffer

Terminal Functions

Name Description Characteristics

GND Ground Ground Input

V

DD

V

REF

Z

OH

Z

OL

CK Positive master clock input Differential Clock input

CK Negative master clock input Differential Clock input

C0, C1 Conguration control inputs LVCMOS inputs

RST

CSR, DCS Chip select inputs disables D1-D24 outputs switching when both inputs are high SSTL_18 input

D1, D25

DODT The outputs of this register bit will not be suspended by the DCS and CSR control SSTL_18 input

DCKE The outputs of this register bit will not be suspended by the DCS and CSR control SSTL_18 input

Q1-Q25 Data outputs that are suspended by the DCS and CSR control 1.8V CMOS

QCS Data output that will not be suspended by the DCS and CSR controll 1.8V CMOS

QODT Data output that will not be suspended by the DCS and CSR controll 1.8V CMOS

QCKE Data output that will not be suspended by the DCS and CSR controll 1.8V CMOS

Power Supply 1.8V nominal

Input Reference Voltage 0.9V nominal

Reserved for future use Input

Reserved for future use Input

Asynchronous reset input - resets registers and disables V
tial - input receivers

Data input - clocked in on the crossing of the rising edge of CK and the falling edge
of CK

data and clock differen-

REF

LVCMOS inputs

SSTL_18 input

Function Table (each ip op)

Inputs Outputs

RST DCS CSR CK CK

H L L ↑ ↓ L L L L

H L L ↑ ↓ H H L H

H L L L or H L or H X Q0 Q0 Q0

H L H ↑ ↓ L L L L

H L H ↑ ↓ H H L H

H L H L or H L or H X Q0 Q0 Q0

H H L ↑ ↓ L L H L

H H L ↑ ↓ H H H H

H H L L or H L or H X Q0 Q0 Q0

H H H ↑ ↓ L Q0 H L

H H H ↑ ↓ H Q0 H H

H H H L or H L or H X Q0 Q0 Q0

L X or oating X or oating X or oating X or oating X or oating L L L

Dn, DODT,

DCKE

Qn QCS

QODT,

QCKE

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PS8743 08/02/04

Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)

Storage Temperature ................................................... –65°C to +150°C

Supply Voltage Range, VDD.............................................–0.5V to 2.5V

Input Voltage Range,VI : (See Notes 2 and 3): ................–0.5V to 2.5V

Output Voltage Range, VO (See Notes 2 and 3).... –0.5V to V

Input Clamp current, I

Output Clamp current, I

Continous Output Current, I

Continous Current through each V

IK (VI

OK

< 0 or V

(V

O

(V

O

= VDD ) ......................... –50mA

I

< 0 or V

O

DD

> VDD).................... ±50mA

O

= 0 to VDD) ........................ ±50mA

or GND......................... ±100mA

DD

+ 0.5V

PI74SSTU32864A

25-Bit 1:1 or 14-Bit 1:2

Congurable Buffer

Notes:

1. Stresses greater than those listed under MAXIMUM
RAINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indi­cated in the operational sections of this specication is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.

2. The input and output negative-voltage ratings may be ex­ceeded if the input and output clamp-current ratings are
observed.

3. This value is limited to 2.5V maximum

Recommended Operating Conditions

(1)

Parameters Descrition Min. Nom. Max. Units

V

DD

V

REF

V

TT

V

I

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

ICR

V

ID

I

OH

I

OL

T

A

Notes:

1. The RST and Cn inputs of the device must be held at valid levels (not oating) to ensure proper device operation. The differential inputs must
not be oating, unless RST is low.

Supply Voltage 1.7 1.9

Reference Voltage 0.49 x V

Termination Voltage V

REF

DD

-40mA V

Input Voltage 0 V

AC High - Level Input Voltage

AC Low- Level Input Voltage V

DC High - Level Input Voltage V

Data

Inputs

V

REF

REF

250mV

125mV

DC Low- Level Input Voltage V

High Level Input Voltage

Low Level Input Voltage 0.35 x V

Common-mode input Voltage

Differential Input Voltage 600 mV

RST, CN

CK, CK

0.65 x V

DD

0.675 1.125

High-Level Output Current -8

Low-Level Output Current -8

0.50 x V

REF

DD

0.51 x V

V

-40mA

REF

DD

-250mV

REF

-125mV

REF

DD

V

DD

mA

Operating Free-air Temperature 0 70 ºC

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PS8743 08/02/04

Electrical Characteristics Over Recommended Operating Free Air Temperature range

Parameters Description Test Conditions V

V

OH

V

OL

I

I

I

DD

All inputs VI = VDD or GND ±5

Static Stand-by RST = GND

Static Operating RST = V

Dynamic Operating
Clock only

Dynamic Operating - per

I

DDD

each data input, 1:1 mode

Dynamic Operating - per
each data input, 1:2 mode

Data inputsp VI = V

C

I

CK and CK V

RST VI = VDD or GND 2.5

Notes:

1. The vendor must supply this value for full device description.

IOH = -6 mA 1.7V 1.2

IOL = 6 mA 1.7V 0.5

IH(AC),

or V

or

IL(AC)

DD, VI = VIH(AC)

RST = VDD, VI = V
V

CK and CK switching 50%

IL(AC)

duty cycle

RST = VDD, VI = V
V

CK and CK switching 50%

IL(AC)

IH(AC),

or

IO = 0

duty cycle. One data input switch­ing at half clock frequency, 50%
duty cycle

RST = VDD, VI = V
V

CK and CK switching 50%

IL(AC)

IH(AC),

or

duty cycle. One data input switch­ing at half clock frequency, 50%
duty cycle

±250mV 2.5 3.5

REF

= 0.9V, VID = 600mV 2 3

ICR

DD

1.9V

1.8V

PI74SSTU32864A

25-Bit 1:1 or 14-Bit 1:2

Congurable Buffer

Min. Nom. Max. Units

V

100

40 mA

28

18

36

µA

µA/
clock
MHz

µA/
clock
MHz

data

input

pF

Timing Requirements Over Recommended Operating Free Air Temperature range (See Figure 1)

Parameter Description Min. Max Units

f

clock

t

W

(1)

t

act

(1)

t

inact

t

su

th Hold Time DCS, CSR DODT, CKE adn data before CK↑, CK↓ 0.5

Notes

1. This parameter is not necessarily production tested.

2. Data and V

3. Data and clock inputs must be held at valid levels (not oating) a minimum time of t

Clock frequency 270 MHz

Pulse Duration, CK, CK, High or low 1

Differential inputs active time

Differential inputs inactive time

(1)

(2)

10

15

DCS before CK↑, CK↓, CSR high 0.7

Setup time

DCS before CK↑, CK↓, CSR low 0.5

CSR DODT, CKE anddata before CK↑, CK↓ 0.5

inputs must be a low minimum time of t

REF

max, after RST is taken high.

act

6

max after RST is taken low.

inact

PS8743 08/02/04

ns

25-Bit 1:1 or 14-Bit 1:2

Switching Characteristics Over Recommended Operating Free Air Temperature range (See Figure 1)

Parameters

f

max

t

pdm

tpdmss

(simultaneous switching)

t

RPHL

Note:

1. Includes 350ps test load transmission-line delay.

2. This parameter is not necessarily production tested.

(1, 2)

From

(Input)

CK and CK Q 1.41 2.15

CK and CK Q 2.35

RST Q 0 3

To

(Output)

VDD = 1.8V ± 0.1V

Min. Max.

270 MHz

Output Edge Rates Over Recommended Operating Free Air Temperature range (See Figure 2)

V

= 1.8V ± 0.1V

Parameters

Min. Max.

dV/dt_r 1 4

(1)

dV/dt

DD

Units

V/nsdV/dt_f 1 4

1

PI74SSTU32864A

Congurable Buffer

Units

ns

Notes:

1. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate).

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PS8743 08/02/04

Test Circuit and Switching Waveforms

Output

V

ICR

t

PLH

t

PHL

V

ICR

V

ID

V

OH

V

TT

V

TT

V

OL

CK

CK

LVCMOS

RST

Input

I

DD

(2)

V

DD

VDD/2

t

inact

0V

10%

90%

t

act

VDD/2

LVCMOS

RESET

Input

Output

t

RPHL

VDD/2

V

OH

V

IH

V

IL

V

TT

V

OL

Input

V

ICR

V

ICR

t

w

V

ID

Input

CK

CK

t

h

t

su

V

IL

V

ICR

V

REF

V

REF

V

ID

V

IH

TL= 350ps, 50-ohm

R = 1000-ohm

V

DD

CL= 30pF

(see note 1)

CK
CK

DUT

RL= 100-ohm

Test Point

Test Point

Test Point

CK Inputs

TL= 50-ohm

R = 1000-ohm

Out

PI74SSTU32864A

25-Bit 1:1 or 14-Bit 1:2

Congurable Buffer

Load Circuit

Voltage and Current Waveforms

Input Active and Inactive Times

Voltage Waveforms - Propagation Delay Times

Voltage Waveforms - Pulse Duration

Voltage Waveforms - Propagation Delay Times

Voltage Waveforms - Setup and Hold Times

Figure 1. Parameter Measurement Information (VDD = 1.8V ± 0.1V)

Notes:

1. CL includes probe and jig capacitance

2. I

3. All input pulses are supplied by generators having the following characteristics: Pulse Repertition Rate ≥ 10 MHz, ZO = 50Ω, input slew

4. The outputs are measured one at a time with one transition per measurement.

5. V

6. VIH = V

7. VIL = V

8. VID = 600mV

9. t

tested with clock and data inputs held at VDD or GND and IO = 0mA

DD

rate = 1V/ns ± 20% (unless otherwise specied).

= VDD /2

REF

PLH

+250mV (ac voltage levels) for differential inputs. V

REF

-250mV (ac voltage levels) for differential inputs. V

and t

REF

are the same as t

PHL

pdm.

= V

IH

= GND for LVCMOS input.

IL

for LVCMOS input.

DD

8

PS8743 08/02/04

R = 50-ohm�

V

DD

CL= 10pF

(see note 1)

DUT

Test Point

Out

Output

80%

20%

dt_f

V

OL

V

OH

dv_f

RL = 50-ohm�

CL= 10pF

(see note 1)

DUT

Test Point

Out

Output

80%

20%

V

OL

V

OH

dv_r

dv_r

Load Circuit -High -to- Low Slew Rate Measurement

Voltage Waveforms - High -to- Low Slew Rate Measurement

PI74SSTU32864A

25-Bit 1:1 or 14-Bit 1:2

Congurable Buffer

Load Circuit - Low -to- High Slew Rate Measurement

Voltage Waveforms - Low -to- High Slew Rate Measurement

Figure 2. Output Slew-Rate Measurement Information (VDD = 1.8V ± 0.1V)

Notes:

1. CL includes probe and jig capacitance

2. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10MHz, ZO = 50Ω, input slew rate = 1 V/ns ± 20%
(unless otherwise specied).

9

PS8743 08/02/04

Packaging Mechanical: 96-ball LFBGA (NB)

PI74SSTU32864A

25-Bit 1:1 or 14-Bit 1:2

Congurable Buffer

Ordering Information

Ordering Code Package Code Package Type

PI74SSTU32864ANB NB 96-Ball LFBGA

PI74SSTU32864ANBE NB Pb-free & Green, 96-Ball LFBGA

Notes:

1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/

2. Number of Transistors = TBD

Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com

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PS8743 08/02/04