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PI6C2972
Low Voltage PLL Clock Driver
Features
• Fully Integrated PLL
• Output Frequency up to 125 MHz
• Compatible with PowerPC and Pentium Microprocessors
• 3.3V V
CC
• + 100ps Typical Cycle–to–Cycle Jitter
• Packaging (Pb-free & Green available):
- 52-pin LQFP (FC)
Pin Configuration
GNDO
Qb0
VCCO
Qb1
GND0
Qb2
VCCO
Qb3
Ext_FB
GNDO
QFB
VCCI
fselFB0
fselb1
fselb0
fsela1
fsela0
Qa3
VCCO
Qa2
GNDO
Qa1
VCCO
Qa0
GND0
VCO_Sel
39 38 37 36 35 34 33 32 31 30 29 28 27
40
41
42
43
44
45
46
47
48
49
50
51
52
1 2 3 4 5 6 7 8 9 10 11 12 13
26
25
24
23
22
21
20
19
18
17
16
15
14
fselFB1
QSync
GNDO
Qc0
VCCO
Qc1
fselc0
fselc1
Qc2
VCCO
Qc3
GND0
Inv_Clk
Description
The PI6C2972 are 3.3V compatible, PLL based clock driver devices
targeted for high-performance CISC or RISC processor based systems. With output frequencies of up to 125 MHz and skews of 550ps
the PI6C2972 are ideally suited for most synchronous systems. The
devices offer twelve low skew outputs plus a feedback and sync
output for added flexibility and ease of system implementation.
The PI6C2972 features an extensive level of frequency programmability between the 12 outputs as well as the input vs output
relationships. Using the select lines output frequency ratios of 1:1,
2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 6:1 and 6:5 between outputs can be
realized by pulsing low one clock edge prior to the coincident edges
of the Qa and Qc outputs. The Sync output will indicate when the
coincident rising edges of the above relationships will occur. The
Power–On Reset ensures proper programming if the frequency
select pins are set at power up. If the fselFB2 pin is held high, it may
be necessary to apply a reset after power–up to ensure synchronization between the QFB output and the other outputs. The internal
power–on reset is designed to provide this function, but with
power–up conditions being dependent, it is difficult to guarantee.
All other conditions of the fsel pins will automatically synchronize
during PLL lock acquisition.
The PI6C2972 offers a very flexible output enable/disable scheme.
Note that all of the control inputs on the PI6C2972 have internal pull–
up resistors.
The PI6C2972 is fully 3.3V compatible and requires no external loop
filter components. All inputs accept LVCMOS/LVTTL compatible
levels while the outputs provide LVCMOS levels with the capability
to drive 50-ohm transmission lines. For series terminated lines each
PI6C2972 output can drive two 50-ohm lines in parallel thus effectively doubling the fanout of the device.
GND1
MR/OE
Frz_Clk
fselFB2
Frz_Data
Ref_Sel
PLL_EN
TClk0
TClk_Sel
TClk1
xtal1
xtal2
VCCA
1
PS8590C 09/22/04
Block Diagram
xtal_1
xtal_2
VC0_Sel
PLL_En
REF_Sel
TCLK0
TCLK1
TCLK_Sel
Ext_FB
PI6C2972
Low Voltage PLL Clock Driver
Sync
Q
D
0
1
PHASE
DETECTOR
VCO
0
1
V
V
V
Frz
LPF
Sync
Q
D
Frz
Qa0
Qa1
Qa2
Qa3
Qb0
fselFB2
MR/OE
POWER-ON
fsela0:1
fselb0:1
fselc0:1
fselFBO:1
Frz_Clk
Frz_Data
RESET
V
Qb1
Qb2
Qb3
Q
D
Sync
Frz
Sync
Q
Frz
÷4, ÷6, ÷8, ÷12
÷4, ÷6, ÷8, ÷10
÷2, ÷4, ÷6, ÷8
V
D
V
2
2
2
2
÷4, ÷6, ÷8, ÷10
Sync Pulse
Data Generator
÷2
V
Output Disable
Circuitry
12
0
1
Q
D
V
D
Sync
Q
Frz
V
Qc0
Qc1
Qc2
Qc3
QFB
QSync
Inv_Clk
2
PS8590C 09/22/04
Function Table 1
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PI6C2972
Low Voltage PLL Clock Driver
0
0
1
1
Function Table 2
2BFlesf1BFlesf0BFlesfBFQ
0
0
0
0
1
1
1
1
Function Table 3
niPlortnoC'0'cigoL'1'cigoL
leS_OCV
leS_feR
leS_KLCT
nE_LLP
EO/RM
KLC_vnI
0
1
0
1
0
0
1
1
0
0
1
1
4÷
6÷
8÷
21÷
0
1
0
1
0
1
0
1
0
0
1
1
4÷
6÷
8÷
01÷
8÷
21÷
61÷
02÷
2/OCV
KLCT
0KLCT
LLPssapyB
Z-iHtuptuO/teseRretsaM
3cQ,2cQdetrevnI-noN
0
1
0
1
4÷
6÷
8÷
01÷
OCV
latX
1KLCT
LLPelbanE
stuptuOelbanE
3cQ,2cQdetrevnI
0
0
1
1
0
1
0
1
2÷
4÷
6÷
8÷
Crystal Recommendations
sretemaraPeulaV
tuClatsyrCtuCTAlatnemadnuF
ecnanoseRecnanoseRlellaraP
ecanreloT.qerFC°52@mpp001±
ytilibatS.pmeT.qerF)C°07ot°0(mpp571±
egnaRgnitarepOC°07ot°0
ecnaticapaCtnuhSFp7<
RSEmhO-04<
leveLevirDWm5
gnigA)sraey3tsriF(raeY/mpp5
3
PS8590C 09/22/04
Timing Diagrams
fVCO
Qa
Qc
Sync
Qa
Qc
Sync
Qc(2)
Qa(6)
PI6C2972
Low Voltage PLL Clock Driver
1:1 Mode
2:1 Mode
3:1 Mode
Sync
Qa(4)
Qc(6)
Sync
Qc(2)
Qa(8)
Sync
Qa(6)
Qc(8)
Sync
Qa(12)
3:2 Mode
4:1 Mode
4:3 Mode
1:6 Mode
Qc(2)
Sync
4
PS8590C 09/22/04
Absolute Maximum Ratings
lobmySretemaraP.niM.xaMstinU
PI6C2972
Low Voltage PLL Clock Driver
V
CC
V
I
I
NI
T
ROTS
*Absolute maximum continuous ratings are those values beyond which damage to the device may occur.
Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability.
Functional operation under absolute-maximum-rated conditions is not implied.
DC Characteristics (TA = 0°C to 70°C, VCC = 3.3V ± 5%)
egatloVylppuS3.0–6.4V
egatloVtupnI3.0–V
3.0+V
DD
tnerruCtupnI02±Am
erutarepmeTegarotS04–521C°
(4)
lobmySsnoitidnoCcitsiretcarahC.niM.pyT.xaMstinU
V
HI
V
LI
V
HO
V
LO
I
HO
I
LO
)2(
Am02=
)2(
Am02=
egatloVHGIHtupnI0.26.3
egatloVWOLtupnI8.0
egatloVHGIHtuptuO4.2
egatloVWOLtuptuO5.0
V
I
NI
I
CC
I
ACC
C
NI
C
dp
Notes:
1. V
2. The PI6C2972 outputs can drive series or parallel terminated 50 Ohm (or 50 Ohm to VCC/2) transmission lines on the
3. Inputs have pull–up/pull–down resistors which affect input current.
4. Special thermal handling may be required in some configurations.
is the difference from the most positive side of the differential input signal. Normal operation is obtained when
CMR
the “High” input is within the V
incident edge.
3etoNtnerruCtupnI021±
tnerruCylppuStnecseiuQmumixaM091512
VgolanA
CC
tnerruC5102
ecnaticapaCtupnI4
tuptuOrePecnaticapaCnoitapissiDrewoP52
range and the input lies within the VPP specification.
CMR
Αµ
Am
Fp
5
PS8590C 09/22/04
Low Voltage PLL Clock Driver
PLL Input Reference Characteristic (TA = 0°C to 70°C)
lobmySsnoitidnoCscitsiretcarahC.niM.xaMstinU
ft,rtsllaF/esiRtupnIKLCT0.3sn
ferf5etoNycneuqerFtupnIecnerefeR5etoN5etoN,001zHM
CDferfelcyCytuDtupnIecnerefeR5257%
latxtycneuqerFrotallicsOlatsyrC0152zHM
Notes:
5. Maximum input reference frequency is limited by the VCO lock range and the feedback divider or 100 MHz,
minimum input reference frequency is limited by the VCO lock range and the feedback divider.
AC Characteristics (TA = 0°C to 70°C, VCC = 3.3V ± 5%)
lobmySscitsiretcarahCsnoitidnoC.niM.pyT.xaMstinU
PI6C2972
t,rt
f
t
wp
t
dp
t
so
f
OCV
=BFQ,8,7setoN ÷8
)7etoN(emiTllaF/esiRtuptuOV0.2ot8.051.02.1sn
2/
t
)7etoN(elcyCytuDtuptuO
yaleDnoitagaporP
0KLCT
1KLCT
ELCYC
057–
072–
033–
t
2/
ELCYC
t
005±
031
07
wekStuptuO-ot-tuptuO7etoN055
egnaRkcoLOCV
002084
)2÷(QycneuqerFtuptuOmumixaM
f
xam
)4÷(Q
)6÷(Q
)8÷(Q
7etoN
rettijt)kaeP–ot–kaeP(rettiJelcyC–ot–elcyC 001±sp
t,
t
ZLP
ZHP
t,
t
LZP
HZP
t
kcol
f
XAM
emiTelbasiDtuptuO28
emITelbaNEtuptuO201
emiTkcoLLLPmumixaM 01sm
ycneuqerFklC_zrFmumixaM 02zHM
2/
ELCYC
057+
035
sp
074
521
021
zHM
08
06
sn
Notes:
7. 50 Ohm transmission line terminated into VCC/2
8. tpd is specified for a 50 MHz input reference. The window will shrink/grow proportionally from the minimum limit with shorter/
longer input reference periods. The tpd does not include jitter.
6
PS8590C 09/22/04
tratS
0D1D2D3D4D5D6D7D8D9D01D11D
tiB
D0–D3 are the control bits for Qa0–Qa3, respectively
D4–D7 are the control bits for Qb0–Qb3, respectively
D8–D10 are the control bits for Qc1–Qc3, respectively
D11 is the control bit for QSync
Freeze Data Input Protocol
Packaging Mechanical: 52-Pin LQFP (FC)
12.00 BSC
.472
Square
PI6C2972
Low Voltage PLL Clock Driver
.004
0.10
Seating Plane
X.XX
DENOTES DIMENSIONS
X.XX
IN MILLIMETERS
0.22
0.38
.009
.015
0.65 BSC
.026
Square
1.60
.063
0.05
0.15
.002
.006
10.00 BSC
.394
Max.
1.35
1.45
.053
.057
0.09
0.20
.004
.008
Ordering Information
Ordering Code Package Code Package Type
PI6C2972FC FC 52-pin LQFP
PI6C2972FCE FC Pb-free & Green, 52-pin LQFP
1.00 REF
.039
0.25 mm
GAUGE PLANE
0.45
0.75
.018
.030
0
7
Notes:
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
7
PS8590C 09/22/04
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