Datasheet PI6C133-03 Datasheet (PERICOM)

2

查询PI6C133-03V供应商

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PI6C133-03

133 MHz Clock Generation

for Pentium II/III Processors

Features

 Four copies of CPU Clock @ 133/100 MHz
 Eight copies of PCI Clock (Synchronous w/CPU Clock)

including one free running PCI clock.
 Two copies of fixed frequencies 3.3V Clock @ 66 MHz
 Three copies of APIC Clock @ 16.667 MHz,

synchronous to CPU Clock
 One copy of 48 MHz Clock
 Two copies of Ref. Clock @ 14.13818 MHz
 Ref.14.31818 MHz Xtal Oscillator Input
 CPU Clock Frequency selection pin for selecting

133 MHz or 100 MHz operation
 Power Management Control Input Pins
 Supports Reliance (RCC) chip set
 Spread Spectrum enable/disable pin
 56-pin SSOP (V) package

Description

The PI6C133, a low-skew, low-jitter 133 MHz clock generator,
is specifically designed to meet all the clocking requirements for
133 MHz and 100 MHz desktops with high-performance and
lower-power features.

Split power supplies of 2.5V and 3.3V are used to reduce power
consumption, minimize noise and to ensure CPU independence.
The 2.5V supply is used to power CPUCLK clocks to the processor
module. 2.5V signalling is compliant to JEDEC standard 8-X. The
rest of the circuitry is powered by a 3.3V supply.

Key features, such as power-management and spread-spectrum
functions, are fully supported. PWRDWN# signal will turn off all
internal circuits and keep all outputs to a low state, making the
power consumption less than 100µA. For less stringent power
requirements, CPUSTOP# will turn off CPUCLK and 3V66 outputs
instantaneously. Spread spectrum function can be optionally disabled
by pulling SPREAD# pin to a HIGH state.

Pin Configuration

V

1

SS
REF0 2
REF1 3

VDD3V 4

XTAL_IN 5

XTAL_OUT 6

V

7

SS

PCICLK_F 8

PCICLK1 9

VDD3V 10
PCICLK2 11
PCICLK3 12

V

13

SS
PCICLK4 14
PCICLK5 15

VDD3V 16
PCICLK6 17
PCICLK7 18

V

19

SS

V

20

SS
3V66_0 21
3V66_1 22

VDD3V 23

V

24

SS

NC 25
NC 26

VDD3V 27

SEL133/100# 28

56-Pin

V

56
55
54
53
52
51
50
49
48

47

46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

VDD2V
APIC2
APIC1
APIC0
V

SS
VDD2V
NC
NC
V

SS
VDD2V
CPUCLK3
CPUCLK2
V

SS
VDD2V
CPUCLK1
CPUCLK0

V

SS
VDD3V
V

SS
PCISTOP#
CPUSTOP#
PWRDWN#
SPREAD#
SEL1
SEL0
VDD3V
48MHz
V

SS

2.5V
Supply

Block Diagram

XTAL_IN

XTAL_OUT

SEL0,1

SPREAD#

SEL100/33#

PWRDWN#

REF

OSC

PLL1

PLL2

CPUSTOP#

Div

PCISTOP#

Div

2

REF[0:1]

3

APIC[0:2]

4

CPUCLK[0:3]

7

PCICLK[1:7]

PCICLK_F

2

3V66MHz

48MHz

350

PS8415 07/23/99

Pin Description

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3,2]1:0[FERO tuptuokcolczHM813.41V3.3

5NI_LATXI tupnilatsyrCzHM813.41

6TUO_LATXO tuptuolatsyrCzHM813.41

8F_KLCICPO kcolcICPgninnuReerFV3.3

22,12]1-0[66V3O stuptuOkcolCzHM66dexiFV3.3

PI6C133-03

133 MHz Clock Generation

for Pentium II/III Processors

81,71,51,41,21,11,9]7-1[KLCICPO stuptuOkcolCICPV3.3

82#001/331LESI

03zHM84O tuptuokcolCzHM84dexiFV3.3

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53#NWDRWPI WOLdlehnehwedomnwodrewoPsretnEeciveD.tupnielbitapmocLTTVL3.3

63#POTSUPCI

73#POTSICPI

64,54,24,14]3-0[KLCUPCO

55,45,35]2-0[CIPAO

93,13,72,32,61,01,4V

V3

DD

V3.3

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.#001/331LES

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8/UPC=CIPA,zHM331=UPCfI
6/UPC=CIPA,zHM001=UPCfI

ylppusrewopV3.3

92,42,02,91,31,7,1

25,84,44,04,83

65,15,74,34V

V

SS

V2

DD

V

SS

V5.2

rewoP

05,94,62,52CNdesunU

dnuorG

rewopV5.2

351

PS8415 07/23/99

PI6C133-03

133 MHz Clock Generation

for Pentium II/III Processors

APIC and PCI Clock Outputs Must Be Synchronous with CPUCLK

PCICLK outputs tracks CPUCLK very closely. The CPUCLKs lead the PCICLKs by 1.5 - 4.0ns with assuming they are fully loaded with
the appropriate loads. The frequency of PCICLK is fixed at 33.33MHz. PCICLK is CPUCLK divided by four @ 133.33MHz, or CPUCLK
divided by three @100.0 MHz.

APIC clocks are now synchronous with the CPUCLK outputs. The IOAPIC voltage will track that of the Host bus and will have maximum
frequency of 16.67 MHz. APIC clocks will be derived by dividing the CPUCLK outputs by eight when the Host bus is 133.33 MHz, and
by six when the Host bus is 100 MHz. APIC clocks will lag the Host bus clocks by 1.5 - 4.0ns at the maximum device load of 20pF.

PI6C133-03 Select Functions

#001/331LES1LES0LESnoitcnuF

000 etatS-irTstuptuollA

001 )devreseR(

010 evitcaniLLPzHM84,ZHM001evitcA

011 evitcaLLPzHM84,ZHM001evitcA

100 edoMtseT

101 )devreseR(

110 evitcaniLLPzHM84,ZHM331evitcA

111 evitcaLLPzHM84,ZHM331evitcA

PI6C133-03 Truth Table

LES

#001/331

000 Z-iHZ-iHZ-iHZ-iHZ-iHZ-iH1

001 a/na/na/na/na/na/n

010 zHM001zHM66zHM33Z-iHzHM813.41zHM76.612

011 zHM001zHM66zHM33zHM84zHM813.41zHM76.617,6,3

100 2/KLCT4/KLCT8/KLCT2/KLCTKLCT61/KLCT5,4

101 a/na/na/na/na/na/n

110 zHM331zHM66zHM33Z-iHzHM813.41zHM76.612

111 zHM331zHM66zHM33zHM84zHM813.41zHM76.617,6,3

Notes:

1. Required for board-level bed of nails testing.

2. 48 MHz PLL disabled to reduce component jitter.
48 MHz outputs are held H-Z instead of driven to a LOW state.

3. Normal mode of operation.

4. TCLK is a test clock over driven on the XTAL_IN input during test mode. TCLK mode is based on 133 MHz
CPU select logic.

5. For DC output impedance verification.

6. Range of reference frequency allowed is min = 14.316 nominal = 14.31818 MHz, max = 14.32 MHz.

7. Frequency accuracy of 48 MHz must be +167PPM to match USB default.

1LES0LESUPC66V3ICPzHM84FERCIPAsetoN

352

PS8415 07/23/99

PI6C133-03

133 MHz Clock Generation

for Pentium II/III Processors

The power-down controller provides a signal that is latched with
its own copy of the PCI clock.

Clock sequencing always guarantees full clock timing parameters
after the system has initially powered up, except where noted.
During power-up and power-down operations using the PWRDWN#
select pin, partial clocks are not allowed and all clock timing
parameters are met except for the following: the first clock pulse
coming out of a stopped clock condition could be slightly distorted
because of the other clock network charging requirements: it is also
understood that board routing and signal loading have a large
impact on the initial clock distortion.

VDD3V Power-Down Removal

The PI6C133-03 device meets the following requirement to
allow for a common design across multiple platforms.

To allow for multiple devices in platforms to share voltage regula­tors, the PI6C133-03 allows the removal of power from the VDD3V
voltage pins during the following specific condition. (Leakage
currents from the VDD3V and VDD2V pins are not allowed to violate
existing powerdown# specifications.)

Going to Powerdown Mode:

1. Assert the PWRDWN# signal to the PI6C133-03.

2. Remove power from the 3.3V pins of the PI6C133-03.

3. All input pins of PI6C133-03 will be either powered down
or driven to ground.

4. VDD3 power plane will be pulled to or discharge to < 250mV.

5. The 2.5V pins will remain powered at 2.5V.

To Restore Power:

1. Apply 3.3V to the PI6C133-03.

2. Wait 200-2000ms.

3. De-assert the PWRDWN# signal.

4. Wait 1ms longer than lock time specified for the device.

5. Continue operation as normal

PI6C133-03 Clock Enable Configuration

#POTSUPC#NWDRWP#POTSICPKLCUPCCIPA66V3ICPF_ICPzHM84,FERcsOsOCV

X0XWOLWOLWOLWOLWOLWOLFFOFFO

010WOLNOWOLWOLNONONONO

011WOLNOWOLNONONONONO

110NONONOWOLNONONONO

111NONONONONONONONO

Notes:

1. LOW means outputs held static LOW as per latency requirement below.

2. ON means active.

3. PWRDWN# pulled LOW, impacts all outputs including REF and 48 MHz outputs.

4. All 3V66 as well as all CPU clocks should stop cleanly when CPUSTOP# is pulled LOW.

5. APIC, REF, 48 MHz signals are not controlled by the CPUSTOP# functionality and
are enabled all in all conditions except PWRDWN# = LOW.

353

PS8415 07/23/99

PI6C133-03 Power Management Requirements

PI6C133-03

133 MHz Clock Generation

for Pentium II/III Processors

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#POTSICP

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)noitarepOlamroN(1sm3

#NWDRWP

)nwoDrewoP(0.xam2

Notes:

1. Clock on/off latency is defined in the number of rising edges of free running PCICLKs
between the clock disable goes low/high to the first valid clock comes out of the device.

2. Power up latency is when PWRDWN# goes inactve (high) to when the first valid clocks
are driven from the device.

CPUSTOP# is an input to the clock synthesizer. It is used to turn off the CPU and 3V66 clocks for low power operation. CPUSTOP#
is asserted asynchronously by the external clock control logic with the rising edge of the free running PCI clock (and hence CPU clock)
and must be internally synchronized to the external PCI_F output. All other clocks will continue to run while the CPU clocks are disabled.
The CPU clocks must always be stopped in a low state and started in such a manner as to guarantee that the high pulse width is a full pulse.
ONLY one rising edge of the PCI_F is allowed after the clock control logic switched for both the CPU and 3V66 outputs to become
enabled/disabled.

CPUCLK

(internal)

PCICLK

(internal)

CPUSTOP#

PCISTOP#=H

PWRDWN#=H

PCI_REF

(external)

CPUCLK

(external)

3V66

(external)

PI6C133-03 CPUSTOP# Timing Diagram

Notes:

1. All internal timing is referenced to the CPUCLK

2. The internal label means inside the chip and is a reference only. This in fact may not be the way that the control is designed.

3. CPUSTOP# signal is an input signal that must be made synchronous to free running PCI_F

4. 3V66 clocks also stop/start before

5. PWRDWN# and PCISTOP# are shown in a high state.

6. Diagrams shown with respect to 133 MHz. Similar operation when CPU is 100 MHz.

354

PS8415 07/23/99

PI6C133-03

133 MHz Clock Generation

for Pentium II/III Processors

PCISTOP# is an input to the clock synthesizer and is made synchronous to the clock driver PCI_F output. It is used to turn
off the PCI clocks for low-power operation. PCI clocks are required to be stopped in a low state and started such that a full high pulse
width is guaranteed. ONLY one rising edge of PCI_F is needed after the clock control logic switched for the PCI outputs to become
enabled/disabled.

CPUCLK

(internal)

PCICLK

(internal)

CPUSTOP#=H

PCISTOP#

PWRDWN#=H

PCICLK_F

(external)

PCICLK

(external)

Notes:

PI6C133-03 PCISTOP# Timing Diagram

1. All internal timing is referenced to the CPUCLK

2. PCISTOP# signal is an input signal which is made synchronous to PCI_F output.

3. Internal means inside the chip.

4. All other clocks continue to run undisturbed.

5. PWRDWN# and CPUSTOP# are shown in a high state.

6. Diagrams shown with respect to 133 MHz. Similar operation when CPU is 100 MHz.

The power-down selection is used to put the part into a very low power state without turning off the power to the part. PWRDWN# is an
asynchronous active low input. The signal needs to be synchronized internal to the device prior to powering down the clock synthesizer.
PWRDWN# is an asynchronous function for powering up the system. Internal clocks are not running after the device is put in power down.
When PWRDWN# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and the crystal. The
power-up latency is less than 3ms. The power-down latency is short and conforms to the sequence requirements shown below. PCISTOP#
and CPUSTOP# are considered to be dont cares during power-down operations. REF and 48 MHz clocks are expected to be stopped
in the LOW state as soon as possible. Owing to the state of internal logic stopping and holding REF clock outputs in the LOW state, more
than one clock cycle may be required to complete.

CPUCLK

(internal)

PCICLK

(internal)

PWRDWN#

CPUCLK

(external)

PCICLK

(external)

VCO

Crystal

Notes:

PI6C133-03 PWRDWN# Timing Diagram

1. All internal timing is referenced to the CPUCLK

2. Internal means inside the chip.

3. PWRDWN# is an asynchronous input and metstable conditions could exist.

This signal is required to be synchronized inside the part.

4. The shaded sections on the VCO and the crystal signals indicate an active clock.

5. Diagrams shown with respect to 133 MHz. Similar operation when CPU is 100 MHz.

355

PS8415 07/23/99

DC Specifications

DC parameters must be sustainable under steady state (DC) conditions

PI6C133-03

133 MHz Clock Generation

for Pentium II/III Processors

Absolute Maximum DC Power Supply

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V3ddV
V2ddV

T

S

egatloVylppuS5.0-6.4V

erutarepmeTegarotS56-051Cº

DC Operating Requirements

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V3ddVegatloVylppuS3.3

V2ddVegatloVylppuSV5.2

V

3HI

V

3LI

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)7,3(

tnerruCegakaeLtupnI

Absolute Maximum DC I/O

V

3HI

V

3LI

Notes:

1. Maximum VIH is not to exceed maximum VDD.

2. Human body model.

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LO

356

PS8415 07/23/99

DC Operating Requirements (continued)

lobmySretemaraPnoitidnoC.niM.xaMstinU

PI6C133-03

133 MHz Clock Generation

for Pentium II/III Processors

V

V3DD

V

HOP

V

LOP

C

NI

LATX

C

TUO

L

NIP

T

A

%5±V3.3=

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ecnatcudnIniP7Hn

erutarepmeTtneibmAwolfriAoN007Cº

Notes:

1. Signal edge is required to be monotonic when transitioning through this region.

2. Input leakage Current does not include inputs with Pull-up or Pull-down resistors.

3. No power sequencing is implied or allowed to be required in the system.

4. Conforms to 5V PCI Signaling specification.

5. As seen by the crystal. Device is intended to be used with a 17-20pF AT crystal.

6. All inputs referenced to 3.3V power supply.

Buffer Specifications

V

FpC

emaNreffuBV

CC

)V(egnaR

ecnadepmI

)smhO(

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66V3,ICP564.3-531.355-215epyT

epyTreffuB

357

PS8415 07/23/99

Type 1 Buffer Characteristics
Operating Requirements

lobmySretemaraPnoitidnoC.niM.pyT.xaMstinU

PI6C133-03

133 MHz Clock Generation

for Pentium II/III Processors

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V

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V

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V3.0=03

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I

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I

NIMLO

I

XAMLO

T

HR

T

HF

Notes:

1. Production testing is expected to be a subset of characterization testing.

2. Output Rise and Fall time.

3. Reciever logic thresholds are VIL = 0.7 and VIH = 1.7V

4. RON 13.5-45 Ohm with a 29 Ohm nominal driver impedance.

5. RON = V

OUT/IOH

, V

OUT/IOL

measured at VCC/2.

Type 3 Buffer Characteristics
Operating Requirements

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1/11/4

sn/V

1/11/4

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TUO

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V4.0=72

TUO

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Notes:

1. Production testing is expected to be a subset of characterization testing.

2. Output rise and fall time.

3. Receiver logic thresholds are VIL = 0.8 and VIH = 2.0V.

4. RON 20 -60 Ohm with a 40 Ohm nominal driver impedance.

5. RON = V

OUT/IOH,VOUT/IOL

measured at VCC/2.

Am

5.00.2
sn/V

5.00.2

358

PS8415 07/23/99

Type 5 Buffer Characteristics
Operating Requirements

lobmySretemaraPnoitidnoC.niM.pyT.xaMstinU

PI6C133-03

133 MHz Clock Generation

for Pentium II/III Processors

I

NIMHO

I

XAMHO

I

NIMLO

I

XAMLO

T

HR

T

HF

)1(

tnerruCpU-lluP

)1(

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)1(

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4epyTV3.3

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)2(

etaRegdEesiRtuptuO

)2(

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V

V

TUO

V

TUO

V

V0.1=33

TUO

V531.3=33

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V4.0=83

TUO

%5±V3.3

V4.2V4.0@

%5±V3.3

V4.0V4.2@

1/1

1/1

Notes:

1. Production testing is expected to be a subset of characterization testing.

2. Output Rise and Fall time.

3. Output rise and fall time must be guaranteed across VCC, process and temperature range.

4. Receiver logic thresholds are VIL = 0.8 and VIH = 2.0 Volts

5. RON 12 -55 Ohm with a 30 Ohm nominal driver impedance.

6. RON = V

OUT/IOH

, V

OUT/IOL

measured at VCC/2.

7. See PCI specification for additional PCI details

Am

1/4sn/V

359

PS8415 07/23/99

AC Timing
Host Bus AC Timing Requirements

lobmySretemaraP

PI6C133-03

133 MHz Clock Generation

for Pentium II/III Processors

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0.060.460.060.46

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3.52A/N3.52A/N

4.06.14.06.1

4.06.14.06.1

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sn

sn

T

T

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T

T

T

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)9,5(

emiTwoLKLC66V3

)7(

emiTesiRKLC66V3

)7(

emiTllaFKLC66V3

)8,2,1(

)9,4(

emiThgiHKLCICP

)9,5(

emiTwoLKLCICP

)7(

emiTesiRKLCICP

)7(

emiTllaFKLCICP

50.5A/N50.5A/N

4.06.14.06.1

4.06.14.06.1

0.03A/N0.03A/N

0.21A/N0.21A/N

0.21A/N0.21A/N

5.00.25.00.2

5.00.25.00.2

HZpt,LZpt)stuptuollA(yaleDelbanEtuptuO0.10.010.10.01

HZpt,ZLpt)stuptuollA(yaleDelbasiDtuptuO0.10.010.10.01

elbatst

)6(

pU-rewoP

morfnoitazilibatSkcolCllA

33sm

sn

sn

sn

360

PS8415 07/23/99

PI6C133-03

133 MHz Clock Generation

for Pentium II/III Processors

Notes:

1. Period, jitter, offset and skew measured on rising edge @1.25V for 2.5V clocks and @1.5V for 3.3V clocks.

2. The PCICLK clock is the Host clock divided by four at Host = 133 MHz. 3V66 clock internal VCO frequency
divided by three for Host = 100 MHz

3. 3V66 is internal VCO frequency divided by four for Host = 133 MHz. 3V66 Clock is internal VCO frequency divided
by three for Host = 100 MHz

4. T

5. T

6. The time specified is measured from when V

7. T

8. The average period over any 1µs period of time is greater than the minimum specified period.

9. Calculated at minimum edge rate(1V/ns) to guarantee 45/55% duty-cycle. Pulsewidth is required to be wider at

is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs.

HIGH

is measured at 0.4V for all outputs.

LOW

achieves its nominal operating level (typical condition V

DDQ

until the frequency output is stable and operating with in specification.

and T

RISE

JEDEC Specification.

faster edge-rate to ensure duty cycle specification is met.

are measured as a transition through the threshold region VOL = 0.4V and VOH = 2.0V (1mA)

FAL L

DDQ

= 3.3V)

Group Skew and Jitter Limits

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UPCsp571sp05155/54

CIPAsp005sp05255/54

zHM84A/Nsp00555/54

66V3sp052sp00555/54

ICPsp005sp00555/54

FERA/Nsp000155/54

Group Offset Limits

puorGtesffO)depmuL(sdaoLtnemerusaeMstnioPerusaeM

66V3otUPCsdaeLUPCsn5.1-0.0Fp03@66V3,Fp02@UPCV5.1@66V3,V52.1@UPC

ICPotUPCsdaeLUPCsn0.4-5.1Fp03@UPC,Fp03@66V3V5.1@ICP,V5.1@66V3

CIPAotUPCsdaeLUPCsn0.4-5.1Fp02@CIPA,Fp02@UPCV5.1@CIPA,V52.1@UPC

niP-niP

wekS

elcyC-elcyC

rettiJ

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rettiJ,wekS

tnioPerusaeM

V5.2V52.1

V3.3V5.1

Notes:

1. All offsets are to be measured at rising edges

Only offset specifications listed above are guaranteed/tested. The specification is treated as ANY ouput within the
first specified bank to ANY output of the specified bank. Pin-pin skew is implied within offset specification, jitter
is not. Previous offset specifications such as CPU to PCI offset are no longer required.

361

PS8415 07/23/99

CPU@133 MHz

PI6C133-03

133 MHz Clock Generation

for Pentium II/III Processors

1.25V

3V66@66 MHz

CPU@133 MHz

PCI@33 MHz

CPU@133 MHz

1.25V

APIC@16.6 MHz

CPU leads APIC

1.5V

CPU leads 3V66

1.5V

1.5V

CPU leads PCI

1.25V

Group Offset Waveforms

Test and Measurement
Minimum and Maximum Lumped Capacitive Test Loads

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KLCUPC

KLCICP03stnemeriuqer1.2ICPteemtsuM

66V303sdaol2elbissop,daolecived1

01

kcolCzHM8402daolecived1

FER02daolecived1

CIPA02daolecived1

Notes:

1. Maximum rise/fall times are guaranteed at maximum specified load for each type of output buffer.

2. Minimum rise/fall times are guaranteed at minimum specified load for each type of output buffer.

3. Rise/fall times are specified with pure capacitative load as shown. Testing may be done with an additional

500Ω resistor in parallel, if properly correlated with the capacitive load.

02Fpsdaol2elbissop,daolecived1

362

PS8415 07/23/99

PI6C133-03

133 MHz Clock Generation

for Pentium II/III Processors

2.5V Clocking
Interface

3.3V Clocking

Clock Output

Waveform

2.0

1.25

0.4

Interface

2.4

1.5

0.4

t

RISE

t

RISE

Output

Buffer

tHIGH

Test Load

Tperiod

Duty Cycle

t

FALL

tHIGH

Test Point

t

Tperiod

Duty Cycle

t

FALL

LOW

t

LOW

PI6C133-03 Clock Waveforms

Measurement Points

for Component Output

VOH= 2.0V

V

= 0.4V

OL

Measurement Points

for Component Output

VOH= 2.4V

V

= 0.4V

OL

2.5 Volt Measure Points

Vdd2V

= 1.7V

V

IH

1.25V

V

= 0.7V

IL

V

SS

3.3 Volt Measure Points

Vdd3V

V

= 2.0V

IH

1.5V
= 0.8V

V

IL

V

SS

Measurement Points

for System-Level Inputs

Measurement Points

for System Level Inputs

PI6C133-03 Component versus System Measure Points

363

PS8415 07/23/99

56-pin SSOP Package Data

56

1

18.29

.720

18.54

.730

.025 BSC

0.635

.008
.0135

0.20

0.34

.291
.299

7.39

7.59

.396
.416

10.06

10.56

.008

0.20

Nom.

Gauge Plane

.010

0-8˚

0.25

.015
.025

PI6C133-03

133 MHz Clock Generation

for Pentium II/III Processors

.02
.04

0.51

1.01

0.381

x 45˚

0.635

.110 2.79

.008
.016

Max

0.20

0.40

X.XX

DENOTES DIMENSIONS

X.XX

IN MILLIMETERS

Ordering Information

rebmuNniPnoitpircseD

V30-331C6IPegakcaPPOSSnip-65

Pericom Semiconductor Corporation

2380 Bering Drive • San Jose, California 95131 • 1-800-435-2336 • Fax [phone] • http://www.pericom.com

364

PS8415 07/23/99