3
PS8823B 04/27/07
PI6C10806
1.8V/2.5V Low Skew 1:6 Crystal to LVCMOS Clock Buffer
1.8V I/O DC Characteristics (Over Operating Range: T
A
= -40° to 85°C)
Parameters Description
Test Conditions
(1)
Min.
Typ.
(2)
Max. Units
V
DD
2.5V Core Supply 2.375 2.5 2.625
V
1.8V Core Supply 1.6 1.8 2.0
V
DDO
I/O Supply Voltage 1.6 1.8 2.0
V
IH
Input HIGH Voltage Logic HIGH level 0.65*V
DD
VDD+0.3
V
IL
Input LOW Voltage Logic LOW level -0.3 0.35*Vdd
I
L
Input Current V
DD
= Max, VIN = VDD or GND I pin 15 μA
V
OH
Output High Voltage VDD = Min., VIN = VIH or V
IL
IOH = -2mA 1.2
V
I
OH
= -8mA 1.2
V
OL
Output Low Voltage VDD = Min., VIN = VIH or V
IL
IOL = 2mA 0.35
I
OL
= 8mA 0.35
Notes:
1. For Max. or Min. conditions, use appropriate operating Vdd and Ta values.
2. Typical values are at VCC = 1.8V, +25°C ambient and maximum loading.
Storage Temperature ........................................................... –65°C to +150°C
V
DDO,VDD
Voltage ................................................................–0.5V to +2.5V
Output Voltage (max 2.5V) .......................................... –0.5V to VDD+0.5V
Input Voltage (max 2.5V) ............................................. –0.5V to VDD+0.5V
1.8V Absolute Maximum Ratings (Above which the useful life may be impaired. For user guidelines only, not tested.)
Note:
Stresses greater than those listed under MAXIMUM
RAT INGS may cause permanent damage to the
device. This is a stress rating only and functional op er a tion
of the device at these or any other con di tions above those
indicated in the operational sec tions of this spec i fi ca tion is
not implied. Ex po sure to absolute maximum rating con di tions for extended periods may affect re li abil i ty.
1.8V I/O AC Characteristics (Over Operating Range: V
DDO
= 1.8V ± 0.2V, TA = -40° to 85°C)
Parameters De scrip tion
Test Conditions
(1)
Min. Typ Max. Units
V
DD
2.5V Core Supply 2.375 2.5 2.625
V
1.8V Core Supply 1.6 1.8 2.0
f
OUT
Output Frequency
Using Crystal 10 40
MHz
External Clock
(2)
0 180
t
DC
Output Duty Cycle @ V
DDO
/2 47 53 %
t
R/tF
CLKn Rise/Fall Time 20% to 80% 150 800 ps
t
SK(O)
(3)
Output to Output Skew between any two
outputs of the same device @ same transition
@V
DDO
/2 60 ps
t
DIS,tEN(
4)
Output Enable/Disable @V
DDO\
/2 4 cycles
Notes:
1. Unless noted otherwise, all parameters are tested with xtal @ f <= Fxtal_max,; outputs are terminated @ 50Ω to
V
DDO
/2, see waveforms.
2. External clock source is driving XTAL_IN input
3. Identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade.
4. These parameters are guaranteed, but not tested.
Min & Max delay is 4 cycles.