2
查询PI6C105H供应商
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PI6C105
Precision Clock Synthesizer
for Mobile PCs
Features
• Two copies of CPU clock with V
• 100 MHz or 66 MHz operation
• Six copies PCI clock (synchronous with CPU clock) 3.3V
• One copy of Ref. clock @ 14.31818 MHz (3.3V
• 48 MHz USB Clock, 24 MHz Super I/O clock
2
• I
C Serial Configuration Interface
• Spread Spectrum Modulation for CPUCLK, and PCICLK
• Low-cost 14.31818 MHz crystal oscillator input
• Power management control
• Isolated core V
, VSS pins for noise reduction
DD
• 28-pin SSOP and SOIC package (H)
of 2.5V ±5%
DD
TTL
)
Block Diagram
Description
The PI6C105 is a high-speed, low-noise clock generator designed
to work with the PI6C18x family of clock buffers to meet all clock
needs for Mobile Intel Architecture platforms. CPU and chipset
clock frequencies of 66.6 MHz and 100 MHz are supported.
Split supplies of 3.3V and 2.5V are used. The 3.3V power supply
powers a portion of the I/O and the core. The 2.5V is used to power
the remaining outputs. 2.5V signaling follows JEDEC standard
8-X. Power sequencing of the 3.3V and 2.5V supplies is not
required.
An asynchronous PWR_DWN# signal may be used to power down
(or up) the system in an orderly manner.
Pin Configuration
XTAL_IN
XTAL_OUT
Spread#
SEL100/66#
S
DATA
SCLK
REF
OSC
PLL1
I2C
PLL2
CPU_STOP#
DIV
PCI_STOP#
÷
2
2
5
48 MHz
24 MHz
REF
CPUCLK
[0:1]
PCICLK
[1:5]
PCICLK_F
XTAL_IN
XTAL_OUT
V
SSPCI
PCICLK_F
PCICLK1
PCICLK2
PCICLK3
PCICLK4
V
DDPCI
PCICLK5
V
DDP
48M/SPREAD#
V
SSP
24M/SEL100/66#
1
2
3
4
5
6
7
8
9
10
11
2
12
13
2
14
28-Pin
H
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
SSREF
V
DDREF
REF
V
DDCPU
CPUCLK0
CPUCLK1
V
SSCPU
V
DDCORE
V
SSCORE
PCI_STOP#
CPU_STOP#
PWR_DWN#
S
DATA
SCLK
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Precision Clock Synthesizer for Mobile PCs
Pin Description
niPemaNlangiS.ytQnoitpircseD
1NI_LATX1 tupnilatsyrczHM813.41
2TUO_LATX1 tupnilatsyrczHM813.41
3V
ICPSS
1stuptuokcolcICProfdnuorG
4F_KLCICP1 tuptuokcolcICPgninnureerF
01,8,7,6,5]5:1[KLCICP5 V3.3elbitapmocLTT,stuptuokcolcICP
9V
11V
ICPDD
2PDD
1)01,8,7,6,5,4(stuptuokcolcICPllarofrewoP
1stuptuozHM84dnazHM42rofylppuSrewoP
#DAERPS/zHM84
21
zHM84kcolcBSUroftuptuozHM84
1
#DAERPS
31V
21 zHM84dnazHM42rofdnuorG
PSS
#66/001LES/zHM42
41
zHM42kcolCO/IrepuSroftuptuozHM42
1
#66/001LES
51KLCS1 IrofkcolClaireS
61ATADS1 IrofataDlaireS
pulluplanretnI.tupni#DAERPSrotuptuozHM84
tupninasisihT.elbasidtluafed,edommurtcepSdaerpSelbanEwolevitcA
purewopretfatuptuozHM84semoceB.purewopgniruddelpmas
pulluplanretni,tupni#66/001LESrotuptuozHM42
.esiwrehtotuptuozHM42,tupni#66/001LESsinipsihtpurewopgniruD
zHM001=hgiH,zHM66=woL
2
2
pUlluPlanretnI.ecafretniC
pUlluPlanretnI.ecafretniC
71#NWD_RWP1
81#POTS_UPC1
91#POTS_ICP1
02V
12V
22V
EROCSS
EROCDD
UPCSS
1erocpihcrofdnuorG
1erocpihcrofylppusrewoP
1stuptuokcolcUPCrofdnuorG
42,32]1:0[KLCUPC2 V5.2stuptuokcolctsoHdnaUPC
52V
UPCDD
1V5.2stuptuokcolcUPCrofylppusrewoP
62FER1 tuptuolatsyrcdereffuB
72V
82V
FERDD
FERSS
1stuptuoFERrofylppuSrewoP
1stuptuoFERrofdnuorG
sirotallicsodna,latsyrc,sLLPevitcanehW,nwoDrewoPrewoLevitcA
pUlluPlanretnI.woldleheraskcolcKLCICPdnasKLCUPC.ffo
.etatswolotskcolcUPCllaspotS.woLevitcA
pUlluPlanretnI
roftpecxe,etatswolotskcolcKLCICPllaspotS.woLevitcA
pUlluPlanretnI.F_KLCICP
249
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Precision Clock Synthesizer for Mobile PCs
Select Functions
#66/001LESnoitcnuF
0evitcazHM66
1evitcazHM001
Clock Enable Configuration
#POTS_UPC#POTS_ICP#NWD_RWP]1:0[KLCUPC]5:1[KLCICPF_KLCICPskcolCrehtOlatsyrCs'OCV
XX 0 wolwolwoldeppotsffoffo
00 1 wolwolzHM33gninnurgninnurgninnur
011 wolzHM33zHM33gninnurgninnurgninnur
10 1 zHM66/001wolzHM33gninnurgninnurgninnur
11 1 zHM66/001zHM33zHM33gninnurgninnurgninnur
2-Wire I2C Control
The I2C interface permits individual enable/disable of each clock
output and test mode enable.
The PI6C105 is a slave receiver device. It can not be read back.
Sub addressing is not supported. To change one of the control
bytes, all preceding bytes must be sent.
Every byte put on the SDATA line must be 8-bits long (MSB first),
followed by an acknowledge bit generated by the receiving device.
During normal data transfers, SDATA changes only when SCLK is
LOW. Exceptions: A HIGH-to-LOW transition on SDATA while
SCLK is HIGH indicates a start condition. A LOW-to-HIGH
transition on SDATA, while SCLK is HIGH, is a stop condition
and indicates the end of a data transfer cycle.
PI6C105 I2C Address Assignment
7A6A5A4A3A2A1A0A
11010010
Each data transfer is initiated with a start condition and ended
with a stop condition. The first byte after a start condition is always
a 7-bit address byte followed by a read/write bit. (HIGH = read
from addressed device, LOW= write to addressed device). If the
devices own address is detected, PI6C105 generates an acknowledge by pulling SDATA line LOW during ninth clock pulse, then
accepts the following data bytes until another start or stop condition is detected.
Following acknowledgment of the address byte (D2), two more
bytes must be sent:
1. Command Code byte, and
2. Byte Count byte.
Although the data bits on these two bytes are dont care, they
must be sent and acknowledged.
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Precision Clock Synthesizer for Mobile PCs
Byte 3: Modes
#tiBpuP#niPemaNnoitpircseD
70 DVSRdevreseR
60 1SS1tibtceleSmurtcepSdaerpS
50 0SS0tibtceleSmurtcepSdaerpS
1SS0SSM66M001
00 %6.0-%6.0-tluafeD
01 %2.1-%0.1-
10 %8.1-%5.1-
11 %4.2-%0.2-
40 DVSRdevreseR
30 DVSRdevreseR
20 DVSRdevreseR
10 1EDOM1tibedoM
00 0EDOM0tibedoM
1M0M
00 lamroN
01 edoMtseT
10 devreseR
11 Z-iH
Byte 4: Clock Controls (1 = Enabled, 0 = Disabled)
#tiBpuP#niPemaNnoitpircseD
7
641NEM42elbanEsitluafeD,elbanEzHM42
5DVSRdevreseR
4DVSRdevreseR
1
3DVSRdevreseR
232NE1UPCelbanEsitluafeD,elbanE1KLCUPC
1DVSRdevreseR
0DVSRdevreseR
21NEM84elbanEsitluafeD,elbanEzHM84
251
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Precision Clock Synthesizer for Mobile PCs
Byte 5: PCI Clock Control (1 = Enabled, 0 = Disabled)
#tiBpuP#niPemaNnoitpircseD
7
4NEFICPelbanEsitluafeD,elbanEF_ICP
6devreseR
501NE5ICPelbanEsitluafeD,elbanE5ICP
4devreseR
1
38NE4ICPelbanEsitluafeD,elbanE4ICP
27NE3ICPelbanEsitluafeD,elbanE3ICP
16NE2ICPelbanEsitluafeD,elbanE2ICP
05NE1ICPelbanEsitluafeD,elbanE1ICP
Byte 6: REF Clock Control (1 = Enabled, 0 = Disabled)
#tiBpuP#niPemaNnoitpircseD
7
6
DVSRdevreseR
5
1
4
3421S0UPC1tiBtceleSevirD0UPC
2420S0UPC0tiBtceleSevirD0UPC
1S0UPC0S0UPC
00 elbasiD
01 evirDwoL
10 evirDhgiH
11 tluafeD,evirDmuideM
11621tiBtceleSevirDFER1SFER
01620tiBtceleSevirDFER0SFER
1SFER0SFER
00 elbasiD
01 evirDwoL
Note: Outputs are disabled @ low state
10 evirDhgiH
11 tluafeD,evirDmuideM
252
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PI6C105
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)41nip(#66/001LES]6[3etyB1SS]5[3etyB0SSdaerpSnwoDnoitpircseD
000%6.0-daerpsnwod%6.0-,zHM6.66
001%2.1-daerpsnwod%2.1-,zHM6.66
010%8.1-daerpsnwod%8.1-,zHM6.66
011%4.2-daerpsnwod%4.2-,zHM6.66
100%6.0-daerpsnwod%6.0-,zHM001
101%0.1-daerpsnwod%0.1-,zHM001
110%5.1-daerpsnwod%5.1-,zHM001
111%0.2-daerpsnwod%0.2-,zHM001
Precision Clock Synthesizer for Mobile PCs
Power Management Timing
langiSetatSlangiS
ycnetaL
KLCICPgninnureerffosegdegnisirfo.oN
#POTS_UPC)delbasid(01
)delbane(11
#POTS_ICP)delbasid(01
)delbane(11
#NWD_RWP)noitarepolamron(1sm3
)nwodrewop(0.xam2
Notes:
1. Clock on/off latency is defined as the number of rising edges of free running PCICLKs
between when the clock disable goes low/high to when the first valid clock comes out of
the device.
2. Power-up latency is from when PWR_DWN# goes inactive (HIGH) to when the first valid
clocks are driven from the device.
253
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PI6C105
(
)
(
)
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Precision Clock Synthesizer for Mobile PCs
CPU_STOP#, which is an input signal used to turn off the CPU
clocks for low power operation, is asserted asynchronously by the
external clock control logic with the rising edge of the free running
PCI clock and is internally synchronized to the external PCICLK_F
disabled. The CPU clocks are always stopped in a low state and
started guaranteeing that the high pulse width is a full pulse. CPU
clock on latency is 2 or 3 CPU clocks while the CPU clock off
latency is 2 or 3 CPU clocks.
output. All other clocks continue to run while the CPU clocks are
CPUCLK
(Internal)
CPUCLK
(Internal)
PCICLK_F
(Free-running)
CPU_STOP#
PCI_STOP#
PWR_DWN#
CPUCLK
External
Notes:
1. All timing is referenced to the CPUCLK.
2. The Internal label means inside the chip and is a reference only. This in fact may not be the way that the
control is designed.
3 CPU_STOP# is an input signal that must be made synchronous to the free running PCI_F.
4. ON/OFF latency shown in the diagram is 2 CPU clocks.
5. All other clocks continue to run undisturbed.
6. PWR_DWN# PCI_STOP# are shown in a high state.
7. Diagrams shown with respect to 66 MHz. Similar operation as CPU = 100 MHz.
CPU_STOP# Timing Diagram
PCI_STOP# is an input signal used to turn off the PCI clocks for low power operation. PCI clocks are stopped in the low state and started
with a guaranteed full high pulse width. There is ONLY one rising edge of external PCICLK after the clock control logic.
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK_F
(Free-running)
CPU_STOP#
PCI_STOP#
PWR_DWN#
PCICLK
External
Notes:
1. All timing is referenced to the CPUCLK.
2. PCI_STOP# signal is an input signal which must be made synchronous to PCI_F output.
3 Internal means inside the chip.
4. All other clocks continiue to run undisturbed.
5. PWR_DWN# CPU_STOP# are shown in a high state.
6. Diagrams shown with respect to 66 MHz. Similar operation as CPU = 100 MHz.
PCI_STOP# Timing Diagram
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Precision Clock Synthesizer for Mobile PCs
The PWR_DWN#, which is used to place the device in a very low
power state, is an asynchronous active low input. Internal clocks
are stopped after the device is put in power down mode.
CPUCLK
(Internal)
PCICLK
(Internal)
PWR_DWN#
CPUCLK
(External)
PCICLK
(External)
VCO
Crystal
Notes:
PWR_DWN# Timing Diagram
The power on latency is less than 3ms. PCI_STOP# and
CPU_STOP# are “don’t cares” during the power down operations.
The REF clock is stopped in the LOW state as soon as possible.
1. All timing is referenced to the CPUCLK.
2. The Internal label means inside the chip and is a reference only.
3. PWR_DWN# is an asynchronous input and metastable conditions could exist. The signal is synchronized inside the part.
4. The Shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown wth respect to 66 MHz. Similar operations as CPU = 100 MHz.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............................................................65°C to +150°C
Ambient Temperature with Power Applied ............................. 0°C to +70°C
3.3V Supply Voltage to Ground Potential ............................. 0.5V to +4.6V
2.5V Supply Voltage to Ground Potential ............................. 0.5V to +3.6V
DC Input Voltage ................................................................... 0.5V to +4.6V
DC Electrical Characteristics (T
501C6IP
noitidnoC
edoMnwodrewoP
)0=#NWDRWP(
zHM66evitcA
0=#66/001LES
zHM001evitcA
1=#66/001LES
V
= 0°C to +70°C)
A
noitpmusnoCylppuSV5.2.xaM
,sdaolpacetercsid.xaM
UPCDD
V526.2=
V=stupnicitatsllA
Vro
DD
SS
V
DD
001 µA005 µA
Am27Am071
Am001Am071
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
noitpmusnoCylppuSV3.3.xaM
,sdaolpacetercsid.xaM
V564.3=
V=stupnicitatsllA
Vro
DD
SS
255
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PI6C105
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Precision Clock Synthesizer for Mobile PCs
DC Operating Specifications
lobmySsretemaraPsnoitidnoC.niM.xaMstinU
V
DD
V
3HI
V
3LI
I
LI
V
DD2
V
%5±V3.3=
egatlovhgihtupnIV
DD
egatlovwoltupnIV
tnerrucegakaeltupnIV<0
V<
NI
DD
0.2VDD3.0+
3.0-8.0
SS
5-5+
V
5.2=%5±V
2HO
egatlovhgihtuptuOI
HO
Am1-=0.2
V
V
2LO
V
DD
V
3HO
%5±V3.3=
egatlovwoltuptuOI
egatlovhgihtuptuOI
HO
Am1=4.0
LO
Am1-=0.2
V
V
3LO
V
3.3=%5±V
DD
V
HOP
egatlovwoltuptuOI
egatlovhgihtuptuosuBICPI
LO
HO
Am1=4.0
Am1-=4.2
V
V
LOP
C
NI
C
LATX
egatlovwoltuptuosuBICPI
LO
Am1=55.0
ecnaticapacniptupnI5
ecnaticapacsniplatX5.310.815.22
Fp
C
TUO
L
NIP
T
A
ecnaticapacniptuptuO6
ecnatcudnIniP7Hn
erutarepmeTtneibmAwolfriaoN007C°
256
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PI6C105
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Precision Clock Synthesizer for Mobile PCs
Buffer Specifications
emaNreffuBVDD)V(egnaR(ecnadepmI W)epyTreffuB
UPC526.2-573.254-5.311epyT
zHM42/84,FER564.3-531.306-023epyT
ICP564.3-531.355-215epyT
Type 1: CPU Clock Buffers (2.5V)
lobmySsretemaraPsnoitidnoC.niM.pyT.xaMstinU
I
NIMHO
I
XAMHO
I
NIMLO
I
XAMLO
t
HR
t
HF
tnerrucpu-lluPV
tnerrucpu-lluPV
tnerrucnwod-lluPV
tnerrucnwod-lluPV
Type 3: REF Buffers (3.3V)
lobmySsretemaraPsnoitidnoC.niM.pyT.xaMstinU
I
NIMHO
I
XAMHO
I
NIMLO
I
XAMLO
t
HR
t
HF
tnerrucpu-lluPV
tnerrucpu-lluPV
tnerrucnwod-lluPV
tnerrucnwod-lluPV
V0.1=72-
TUO
TUO
TUO
TUO
V573.2=72-
Am
V2.1=72
V3.0=03
etaregdeesirtuptuo1epyTV5.2V0.2-V4.0@%5±V5.214
sn/V
etaregdellaftuptuo1epyTV5.2V4.0-V0.2@%5±V5.214
V0.1=92-
TUO
TUO
TUO
TUO
V573.2=32-
Am
V2.1=92
V3.0=72
etaregdeesirtuptuo3epyTV3.3V4.2-V4.0@%5±V3.35.02
sn/V
etaregdellaftuptuo3epyTV3.3V4.0-V4.2@%5±V3.35.02
Type 5: PCI Clock Buffers (3.3V)
lobmySsretemaraPsnoitidnoC.niM.pyT.xaMstinU
I
NIMHO
I
XAMHO
I
NIMLO
I
XAMLO
t
HR
t
HF
tnerrucpu-lluPV
tnerrucpu-lluPV
tnerrucnwod-lluPV
tnerrucnwod-lluPV
V0.1=33-
TUO
TUO
TUO
TUO
V531.3=33-
Am
V59.1=03
V4.0=83
etaregdeesirtuptuo5epyTV3.3V4.2-V4.0@%5±V3.314
sn/V
etaregdellaftuptuo5epyTV3.3V4.0-V4.2@%5±V3.314
257
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Precision Clock Synthesizer for Mobile PCs
AC Timing
kcolCtsoH.1erugiF
tesffOKLCICPot
t
t
t
t
t
t
)V5.2(doirepKLCtsoH0.515.510.015.01
PKH
HKH
LKH
)V5.2(emithgihKLCtsoH2.50.3
)V5.2(emitwolKLCtsoH0.58.2
ESIRH
)V5.2(emitesirKLCtsoH4.06.14.06.1
LLAFH
RETTIJ
)V5.2(emitllafKLCtsoH4.06.14.06.1
)V5.2(rettiJKLCtsoH052052sp
sretemaraP
zHM66zHM001
stinU
.niM.xaM.niM.xaM
sn
)V5.2(elcyCytuDV52.1taderusaeM54555455%
t
WKSH
t
t,
LZP
)V5.2(wekSKLCsuBtsoH571571sp
HZP
yaledelbanetuptuO0.10.80.10.8
sn
t
t,
ZLP
ZHP
t
BTSH
t
PKP
t
SPKP
HKPt
yaledelbasidtuptuO0.10.80.10.8
pu-rewopmorfnoitazilibatSKLCtsoH33sm
doirepKLCICP0.03
µ
0.03
ytilibatsdoirepKLCICP005005sp
emithgihKLCICP0.210.21
µ
sn
sn
t
LKP
emitwolKLCICP0.210.21
t
WKSP
t
t
TESFFOPH
BTSP
wekSKLCsuBICP005005sp
tesffOkcolCICPottsoH5.10.45.10.4sn
pu-rewopmorfnoitazilibatSKLCICP33sm
258
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1.25V
Host CLK
t
HSKW
1.25V
Host CLK
t
HPOFFSET
1.5V
PCI CLK
t
PSKW
1.5V
PCI CLK
Precision Clock Synthesizer for Mobile PCs
2.5V
1.25V
V
SS
2.5V
1.25V
V
SS
t
HPOFFSET
3.3V
1.5V
V
SS
3.3V
V
SS
2.5V
Clocking
Interface
Figure 1. Host Clock and PCI CLK Timing
Test Load
tHKP
t
Hfall
tPKP
Test
Point
tHKL
2.0
1.25
0.4
t
Hrise
Output
Buffer
Duty Cycle
tHKH
tPKH
3.3V
Clocking
Interface
(TTL)
2.4
1.5
0.4
t
Prise
t
Pfall
Figure 2. Clock Output Waveforms
259
tPKL
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PI6C105
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Precision Clock Synthesizer for Mobile PCs
Minimum and Maximum Expected Capacitive Loads
kcolCdaoL.niMdaoL.xaMstinUsetoN
)KLCH(skcolCUPC0102
)KLCP(skcolCICP0303stnemeriuqer1.2ICPsteeM
Fp
sdaol2elbissop,daolecived1
zHM84,FER0102daolecived1
Notes:
1. Maximum rise/fall times are guaranteed at maximum specified load for each type of output buffer.
2. Minimum rise/fall times are guaranteed at minimum specified load for each type of output buffer.
3. Rise/fall times are specified with pure capacitive load as shown. Testing is done with an
additional 500Ω resistor in parallel.
Design Guidelines to Reduce EMI
1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value
for CI is 10pF. RS Series resistor value can be increased to reduce EMI provided that the rise and fall time
are still within the specified values.
2. Minimize the number of vias of the clock traces.
3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing clock
traces from plane to plane (refer to rule #2).
4. Position clock signals away from signals that go to any cables or any external connectors.
PI6C105
Rs
CPUCLK
PCICLK
REF
2
1 Device load
CL
Rs
6
Meets PCI2.1 Req.
CL
Rs
1 Device load
CL
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PI6C105
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Precision Clock Synthesizer for Mobile PCs
PCB Layout Suggestion
Note:
This is only a suggested layout. There may be alternate solutions
depending on actual PCB design and layout.
As a general rule, C2-C6 should be placed as close as possible to
their respective VDD.
Recommended capacitor values:
C2-C6 .............. 0.1uF, ceramic
C1, C7 ............ 22uF
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Precision Clock Synthesizer for Mobile PCs
28-Pin SSOP Package Data
Ordering Information
N/PnoitpircseD
H501C6IPegakcaPPOSSnip-82
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
Pericom Semiconductor Corporation
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PS8316 03/15/99
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