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PI2EQX6804-ANJE EvalBoard Rev.A User Guide
Introduction
Pericom Semiconductor’s PI2EQX6804-A is a low power, SAS2, SATA, XAUI signal Re-Driver. The device provides
programmable equalization, am plific at ion, an d em ph asis by using 8 elect bits, to optimize performa n ce over a variety
of physical mediums by reducin g Int er - Symbol Interference.
PI2EQX6804-A supports eight 100-Ohm Differential CML data I/O’s between the Protocol ASIC to a switch fabric,
across a backplane, or to extend the signals across other distant data pathways on the user’s platform.
The integrated equalization circuitry provides fl edibility with signal integrity of the signal before the re-driver, whereas
the integrated emphasis circuitry provides flexibility with signal integrity of the signal after the reDriver.
In addition to providing signal re-conditioning, Pericom’s PI2EQX6804-A also provides power management Stand-by
mode operated by a Power Down pin.
This design guide describes how to use PI2EQX6804-A SATA ReDriver in the demo board. Figure1 shows top view
and bottom view of PI2EQX6804-A demo board. This demo board is just for SAS application using SAS connector.
Figure1a Top View of PI2EQX6804-A demo board
Figure1b Bottom View of PI2EQX6804-A demo board
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Board Operation
z Logical Block Diagram
Figure2 shows the logical block diagram of PI2E QX6804-A.
Figure2. Logical Block Diagram of PI2EQX6804-A
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z Board Circuit
1) Power Supply
On the demo board, the power supply is from one mi ni U S B c o nnector (J1) by +5V power transforming to +1.2V for
PI2EQX6804-A. Figure3 shows the power circuit.
600mA
+1V2
+
C46100u
U2
LM3674
VIN
1
GND
2
EN3FB
4
SW
5
R7
280k
J1
Mini USB 2.0 Type B F em ale
VBUS
1
D-
2
D+
3
ID
4
GND
5
L1
2.2uH
1 2
R10
200K
C47
0.1u
C43
10u
C45
0.1u
C42
4.7u
C48
12pF
R9
510
D5
LED
12
L2
BL1005LL680
1 2
R8 680K
+
EC1
100uF
12
C49
NP
C44
0.1u
D3
B0520LW
+5.0V
Figure3. Power Circuit for PI2EQX6804-A demo board
Figure4 shows the location for J1.
Figure4. J1 location on PI2EQX6804-A demo board
2) Configuration Control
PI2EQX6804-A provides two ways configuration control depending on the state of the MODE input (PIN G5).
MODE determines whether IC configuration status is from the input pins or via I2C control, when MODE is set high,
the configuration input pins set the configuration operating state as stored in configuration registers, changes to these
control registers are disabled and initial condition is protected from any changes to insuring a known operating state.
When MODE pin is low, reprogramming of these control registers via I2C is allowed. NOTE that the MODE pin is not
latched and is always active to enable or disable I2C acces.
During initial power-on, the value at the configuration input pins: LB#, PD#, DE_ [A...B], SEL [0...2] _A, D [0…2] _A,
S0_A, S1_A, SEL [0...2] _B, D [0…2] _B, S0_B, S1_B, will be latched to the configuration registers as initial startup
states. All these pins have internal 100K pull-up resistor.
Figure5 shows the switch and location of these configuration control pins on the demo board.
J1 location
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SW1
CHS-08TA
1234567
8
16
15
14
13
12
11
10
9
MODE
S0_B
S1_B
SW2
CHS-08TA
1234567
8
16
15
14
13
12
11
10
9
LB#
PD#
SEL2_A
SEL1_A
SEL0_A
SEL2_B
SEL1_B
SEL0_B
SW3
CHS-08TA
1234567
8
16
15
14
13
12
11
10
9
D0_B
D0_A
D2_B
D1_B
PRE_B
D2_A
D1_A
PRE_A
S0_A
S1_A
A0
A1
A4
Figure5a Control Pin connecton with SW1, SW2, SW3
Figure5b SW1, SW2 and SW3 location on PI2EQX6804-A demo board
Figure6 shows input equalizer selection table for Channel A and B.
Figure6 Input equalizer selection table for Channel A and B
SW1 location
SW3 location
SW2 location
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Figure7 shows output configuration table for Channel A and B.
Figure6 Output Configuration Table for Channel A and B
For detail I2C configuration function please refer to Page7-13 on the datasheet. There is one connector-JP3 as
Figure7 on the demo board for I2C connection.
Figure7 JP7 location for I2C connection
Also there are three LED lights for power supply, signal detect output for Channel A and B.
D1: signal detect output for Channel A, not available
D2: signal detect output for Channel B, not available
D5: Power supply
JP3 location
SCL SDA
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Appendix A: PCB Schematic
C21 10n
C22 10n
C24 10n
C26 10n
C29 10n
C30 10n
C31 10n
C32 10n
C1 10n
U1A
PI2EQX6804@LFBGA100P
A1RX+B1A1RX-C1A0RX+C4A0RX-B4A2RX+G3A2RX-G2A3RX+K2A3RX-
K3
A1TX+
B10
A1TX-
C10
A0TX+
C7
A0TX-
B7
A2TX+
G8
A2TX-
G9
A3TX+
K9
A3TX-
K8
JP1
SAS CONN
GNDA1
A1
RX0+
A2
RX0-
A3
GNDB1
B1
TX0+
B2
TX0-
B3
GNDA4
A4
RX1+
A5
RX1-
A6
GNDB4
B4
TX1+
B5
TX1-
B6
GNDA7
A7
RX2+
A8
RX2-
A9
GNDB7
B7
TX2+
B8
TX2-
B9
GNDA10
A10
RX3+
A11
RX3-
A12
GNDB10
B10
TX3+
B11
TX3-
B12
GNDA13
A13
GNDB13
B13
GNDD1GNDD2GNDD3GNDD4GNDD5GND
D6
JP2
SAS CONN
GNDA1A1RX0+A2RX0-A3GNDB1B1TX0+B2TX0-B3GNDA4A4RX1+A5RX1-A6GNDB4B4TX1+B5TX1-B6GNDA7A7RX2+A8RX2-A9GNDB7B7TX2+B8TX2-B9GNDA10
A10
RX3+
A11
RX3-
A12
GNDB10
B10
TX3+
B11
TX3-
B12
GNDA13
A13
GNDB13
B13
GNDD1GNDD2GNDD3GNDD4GNDD5GND
D6
U1B
PI2EQX6804@LFBGA100P
B0TX+A3B0TX-A2B1TX+D2B1TX-D3B3TX+J4B3TX-H4B2TX+H1B2TX-
J1
B0RX+
A8
B0RX-
A9
B1RX+
D9
B1RX-
D8
B3RX+
J7
B3RX-
H7
B2RX+
H10
B2RX-
J10
C2 10n
C4 10n
C6 10n
C8 10n
C10 10n
C12 10n
C14 10n
C16 10n
C17 10n
C18 10n
C19 10n
C20 10n
C23 10n
C25 10n
C27 10n
C28 10n
C3 10n
C7 10n
C9 10n
C15 10n
C13 10n
C5 10n
C11 10n
Page 7
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Appendix A: PCB Schematic (cont’d)
R4470
600mA
+1V2
+
C46100u
SW1
CHS-08TA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
R5470
JP3
CONN_4P
1122334
4
C330.1u
C340.1u
C350.1u
C360.1u
C411u
R14.7K
R24.7K
+1V2
R3 470
MODE
+1V2
PD#
S0_B
LB#
S1_B
SEL0_A
C370.1u
+3V3
SEL1_A
Q2
MMBT3904
Q1
MMBT3904
D2
LED
D1
LED
U2
LM3674
VIN1GND2EN
3
FB
4
SW
5
SW2
CHS-08TA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SEL2_A
LB#
PD#
SEL2_A
SEL1_A
SEL0_A
SEL2_B
SEL1_B
SEL0_B
SW3
CHS-08TA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
D0_B
D0_A
D2_B
D1_B
PRE_B
D2_A
D1_A
PRE_A
D2_A
D0_A
D1_A
D0_B
D1_B
D2_B
PRE_A
PRE_B
SEL0_B
S0_A
SEL1_B
U1D PI2EQX6804@LFBGA100P
PD#
C6
PRE_A
B5
LB#
F8
A4K6A1F6A0
H6
Mode
G5
SDA
A6
SCL
A5
SIG_A
E9
D0_AE4D1_AE5D2_A
D5
D0_BG6D1_BJ6D2_B
K5
PRE_B
H5
NC
C5
NC
E7
NC
E10
NC
F1
NC
F4
NC
J5
S0_AE6S1_AE8S0_BF5S1_B
F3
SEL0_AE1SEL1_AE2SEL2_AE3SEL0_B
F10
SEL1_BF9SEL2_B
F7
SIG_B
F2
SEL2_B
U1C
PI2EQX6804@LFBGA100P
GNDB2GNDB3GNDB8GNDB9GNDC2GNDC3GNDC8GNDC9GNDH2GNDH3GNDH8GNDH9GNDJ2GNDJ3GNDJ8GND
J9
VDDA1VDDA4VDDA7VDD
A10
VDDD1VDDD4VDDD7VDD
D10
VDDG1VDDG4VDDG7VDD
G10
VDDK1VDDK4VDDK7VDD
K10
VDD
B6
GND
D6
S1_A
MODE
Q3
2SK3018@SOT-23
Q4
2SK3018@SOT-23
S0_B
A0
C380.1u
S1_B
+1V2
R1210K
R1110K
S0_A
+3V3
C390.1u
R1327K
A1
R14 10K
C50100n
+3V3
S1_A
R6 470
C400.1u
A0
R7
280k
J1
Mini USB 2.0 Ty pe B F emale
VBUS
1
D-
2
D+
3
ID
4
GND
5
L1
2.2uH
1 2
A4
R10
200K
C47
0.1u
C43
10u
C45
0.1u
A1
C42
4.7u
C48
12pF
R9
510
D5
LED
12
L2
BL1005LL680
1 2
R8 680K
+
EC1
100uF
12
C49
NP
A4
C44
0.1u
D3
B0520LW
+5.0V
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History
Version 1.0 Original Version Aug. 4, 2009
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