PERFORMANCE P4C150 Technical data

查询P4C150供应商
P4C150 ULTRA HIGH SPEED 1K X 4 RESETTABLE STATIC CMOS RAM
FEATURES
P4C150
Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25 ns (Commercial) – 15/20/25/35 ns (Military)
Chip Clear Function
Low Power Operation – 713 mW Active –10 ns (Commercial) – 550 mW Active –25 ns (Commercial)
DESCRIPTION
The P4C150 is a 4,096-bit ultra high-speed static RAM organized as 1K x 4 for high speed cache applications. The RAM features a reset control to enable clearing all words to zero within two cycle times. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs and outputs are fully TTL-compat­ible. The RAM operates from a single 5V ± 10% tolerance power supply.
Access times as fast as 10 nanoseconds are available permitting greatly enhanced system operating speeds.
Single 5V ± 10% Power Supply Separate Input and Output Ports Three-State Outputs Fully TTL Compatible Inputs and Outputs Standard Pinout (JEDEC Approved)
– 24-Pin 300 mil DIP – 24-Pin 300 mil SOIC – 28-Pin LCC (350 x 550 mils) – 24-Pin CERPACK
Time required to reset is only 20 ns for the 10 ns SRAM. CMOS is used to reduce power consumption to a low level.
FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS
A
CS
WE
RS OE
A A
ROW
A
SELECT
A
4,096-BIT MEMORY
ARRAY
A
I
1
I
2
I
3
I
4
INPUT
DATA
CONTROL
COLUMN I/O
COLUMN
SELECT
O
1
O
2
O
3
O
4
AAAA
A
1
0
A
2
1
3
A
2
4
A
3
5
A
4
6
A
5
7
A
6
8
I
I
1
9
I
2
10
O
1
11
O
2
12
GND
DIP (P4, D4), SOIC (S4)
CERPACK (F4) SIMILAR
TOP VIEW
25
V
24
CC
A
23
9
A
22
8
A
21
7
RS
20
CS
19
WE
18
OE
17
I
16
4
I
15
3
O
14
4
O
13
3
Means Quality, Service and Speed
CC
0
1
A
A
327
A
4
2
A
5
3
A
6
4
A
7
5
NC
8
A
9
6
I
10
1
I
11
2
12
O
1
13 17
2
O
GND
LCC (L5)
TOP VIEW
9
A
V
NC
26
1
25 24 23 22 21 20 19
152142816
18
4
O3O
NC
A A
RS CS
NC
WE
OE
I I
8 7
4 3
1Q97
P4C150
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
Power Supply Pin with –0.5 to +7 V
(1)
Symbol Parameter Value Unit
T
Respect to GND Terminal Voltage with –0.5 to
V
TERM
Respect to GND VCC +0.5 V (up to 7.0V)
T
A
Operating Temperature –55 to +125 °C
RECOMMENDED OPERATING CONDITIONS
(2)
Grade
Commercial Military
Ambient Temp
0˚C to 70˚C
-55˚C to +125˚C
Gnd
0V 0V
V
CC
5.0V ± 10%
5.0V ± 10%
T P I
OUT
CAPACITANCES
(VCC = 5.0V, TA = 25°C, f = 1.0MHz)
Symbol Parameter Conditions Typ. Unit
C C
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage (2)
Symbol
Parameter
Test Conditions
BIAS
Temperature Under –55 to +125 °C Bias
STG
T
Storage Temperature –65 to +150 °C Power Dissipation 1.0 W DC Output Current 50 mA
IN
OUT
Input Capacitance VIN = 0V 5 pF
Output Capacitance V
(4)
Min.
= 0V 7 pF
OUT
P4C147
Max.
Unit
V
Output High Voltage
OH
IOH = –4 mA, VCC = Min.
(TTL Load)
V
Output Low Voltage
OL
IOL = +8 mA, VCC = Min
(TTL Load)
V
V
I
Input High Voltage
IH
Input Low Voltage
IL
I
Input Leakage Current
LI
Output Leakage Current
LO
VCC = Max., VIN = GND to V
VCC = Max., CS = VIH, V
OUT
CC
= GND to V
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol Parameter
I
CC
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condi­tions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating condi­tions for extended periods may affect reliability.
Dynamic Operating Current
Temperature
Range
Commercial
Military
-10 -12 -15 -20 -25 -35
130 N/A
3. Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
130 N/A
CC
120 145
2.4
2.2
–0.5
–5
–5
115 135
V
0.4
VCC =+0.5
(3)
0.8
+5
+5
V
V V
µA
µA
Unit
100 125
N/A
120
mA mA
26
P4C150
AC CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)
Sym.
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
OE
t
OLZ
t
OHZ
Read Cycle Time Address Access Time Chip Select Access Time Output Hold from
Address Change Chip Enable to
Output in Low Z Chip Disable to
Output in High Z Output Enable to
Data Valid Output Enable to
Output in Low Z Output Disable to
Output in High Z
Parameter
(2)
-10
Min
Max
10
10
8
2
2
4
7 9 10 14 15 20
222222
57 9111316ns
Min
12
2
2
-12 Max
12 10
6
Min
15
2
2
-15 Max
15 12
8
-20 -25 -35
Min
20
2
2
Max
20 14
10
Min
25
2
2
Max
25 15
13
Min
35
2
2
Max
35 35
15
Unit
ns ns ns
ns
ns
ns
ns
ns
TIMING WAVEFORM OF READ CYCLE NO. 1
ADDRESS
t
t
DATA OUT
AA
OH
TIMING WAVEFORM OF READ CYCLE NO. 2 (
t
RC
CS
(7)
t
AC
(8)
t
DATA OUT
OE
LZ
(8)
t
OLZ
t
OE
(5,6)
(8)
t
RC
CSCS
CS CONTROLLED)
CSCS
t
HZ
DATA VALID
(8)
t
OHZ
DATA VALIDPREVIOUS DATA VALID
(5, 7)
(8)
HIGH IMPEDANCE
Notes:
5.WE is HIGH for READ cycle.
6.CS and OE are LOW for READ cycle.
7.ADDRESS must be valid prior to, or concident with, CS transition LOW, tAA must still be met.
8. Transition is measured ±200 mV from steady state volt­age prior to change, with loading as specified in Figure 1.
9. Read Cycle Time is measured from the last valid address to the first transitioning address.
27
P4C150
TIMING WAVEFORM OF READ CYCLE NO. 3 (
(9)
t
RC
ADDRESS
t
AA
OE
t
OE
(8)
t
OLZ
CS
DATA OUT
t
AC
(8) (8)
t
LZ
AC CHARACTERISTICS—RESET CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)
Symbol
t
RRC
t
WER
Parameter
Reset Cycle Time
Write Enable High to Beginning of Reset
(2)
-10
Min Max
20
0
-12 -15 -20 -25 -35
Min Max Min Max
24
0
OEOE
OE Controlled)
OEOE
Min Max
30
0
40
0
(5)
t
OH
(8)
t
OHZ
t
HZ
1521 05
Min Max Min Max
50
0
70
0
Unit
ns ns
t
CR
Chip Select Low to
0
0
Beginning of Reset
t
RP
t
HCR
Reset Pulse Width Chip Select Hold
10
0
12
0
after End of Reset
t
HWR
Write Enable Hold
10
12
after End of Reset
t
t
RLZ
RHZ
Reset High to Ourput in Low Z
Reset Low to
00
0 8 0 10 0 12 0 16 0 20 0 ns
Output in High Z
TIMING WAVEFORM OF RESET CYCLE
ADDRESS
WE
CS
t
WER
t
CR
0
15
0
15
0
t
RRC
t
HCR
0
20
0
20
0
00 ns
t
HWR
25
0
25
0
30
0
35
0
ns ns
ns
ns
O1–O
(DATA OUTPUT)
RS
t
RP
t
RHZ
4
HIGH IMPEDANCE
t
RLZ
OUTPUT VALID ZERO
28
P4C150
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)
Sym.
t
Write Cycle Time
WC
t
Chip Enable Time to End of Write
CW
t
Address Valid to End of Write
AW
t
Address Set-up Time
AS
t
Write Pulse Width
WP
Address Hold Time from
t
AH
End of Write
t
Data Valid to End of Write
DW
t
Data Hold Time
DH
Write Enable to Output in High Z
t
WZ
Output Active from End of Write
t
OW
Parameter
(2)
Min
10
8 8 0 8
0 5
0
-10 Max
-12
Min
12 10
10
1
10
1
8 1
5
2
2
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
-15
Min
Max
Max
15 11
13
1
11
1
11
1
8
12
2
WEWE
WE CONTROLLED)
WEWE
(12)
t
WC
Min
20 13 16
1
13
1
13
1
3
-20 Max
15
(10)
Min
25 15 20
2
15
2
15
2
3
-25 Max
20
Min
35 20
25
2
20
2
20
2
3
-35 Max
25
Unit
ns ns
ns ns
ns ns
ns ns
ns ns
ADDRESS
t
CW
CS
t
AW
WE
t
AS
DATA IN
(8)
t
WZ
DATA OUT DATA UNDEFINED
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
ADDRESS
t
AS
CS
t
AW
WE
DATA IN
t
t
WP
t
DW
DATA VALID
HIGH IMPEDANCE
CSCS
CS CONTROLLED)
CSCS
(12)
t
WC
t
CW
t
WP
t
DW
DATA VALID
WR
t
AH
t
DH
t
OW
t
AH
t
WR
(8, 11)
t
(10)
DH
DATA OUT
Notes:
10. CS and WE must be LOW for WRITE cycle.
11. If CS goes HIGH simultaneously with WE high, the output remains in a high impedance state.
HIGH IMPEDANCE
12. Write Cycle Time is measured from the last valid address to the first transition address.
29
P4C150
AC TEST CONDITIONS
Input Pulse Levels GND to 3.0V Input Rise and Fall Times 3ns Input Timing Reference Level 1.5V Output Timing Reference Level 1.5V Output Load See Figures 1 and 2
+5
480
D
OUT
255
Figure 1. Output Load Figure 2. Thevenin Equivalent
* including scope and test fixture.
300pF(5pF* for tHZ, tLZ, t
t
, tWZ and tOW)
OLZ
OHZ
TRUTH TABLE
CSCS
Mode
Not Selected RESET
Output Disabled READ WRITE
D
OUT
,
RSRS
RS
RSRS
X
L H H
H
R
30pF(5pF* for tHZ, tLZ, t
CS
CSCS
H
L L L
L
TH
t
OLZ
166.5 =
OEOE
WEWE
OE
WE
OEOE
WEWE
X X
H
L
X
VTH = 1.73 V
, tWZ and t
Output
X
High Z
High Z
H H
High Z
H
L
OW
D
High Z
OHZ
)
OUT
,
Note:
Due to the ultra-high speed of the P4C150, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between VCC and ground. To avoid signal reflections,
proper termination must be used; for example, a 50 test environment should be terminated into a 50 load with 1.73V (Thevenin Voltage) at the comparator input, and a 116 resistor must be used in series with D
to match 166 (Thevenin Resistance).
OUT
30
PACKAGE SUFFIX TEMPERATURE RANGE SUFFIX
P4C150
Package
Suffix
P D L F S
Description
Plastic DIP, 300 mil wide standard CERDIP, 300 mil wide LCC CERPACK SOIC
ORDERING INFORMATION
P4C150 xxxx
Device Type Package Processing
Speed
Temperature Range Suffix
C
M
MB
C 0˚C to +70˚C M –55°C to +125°C MB Mil . Te mp. with MIL-STD-883 Class B Co mpliance
P Plastic DIP (300 mil) D CERDIP (300 mil) S Plastic SOIC (300 mil) L Ceramic LCC F CERPACK
Description
Commercial Temperature Range, 0°C to +70°C. Military Temperature Range, –55°C to +125°C. Mil. Temp. with MIL-STD-883 Class B Compliance.
10, 12, 15, 20, 25, 35 ns
1K x 4 SRAM
The P4C150 is also available to SMD-5962-88588
SELECTION GUIDE
The P4C150 is available in the following temperature, speed and package options.
Temperature Range
Commercial
Package 10
Plastic DIP SOIC
Military Temp.
CERDIP (300 mil) LCC CERPACK
Military Processed*
CERDIP (300 mil) LCC CERPACK
* Military temperature range with MIL-STD-883, Class B processing.
Speed (ns)
–10PC
– 10SC
N/A N/A N/A
N/A N/A N/A
12
–12PC –12SC
N/A N/A N/A
N/A N/A N/A
15
–15PC –15SC
–15DM
–15LM
–15FM
–15DMB
–15LMB
–15FMB
20
–20PC –20SC
–20DM
–20LM
–20FM
–20DMB
–20LMB
–20FMB
25
–25PC –25SC
–25DM
–25LM –25FM
–25DMB
–25LMB
–25FMB
35
N/A N/A
–35DM
–35LM
–35FM
–35DMB
–35LMB
–35FMB
N/A = Not Available
31
P4C150
32
Loading...