The PE4283 RF Switch is designed to cover a broad r an ge
of applications from DC through 4000 MHz. This reflective
switch integrates on-board CMOS control logic with a low
voltage CMOS-compatible control interface, and can be
controlled using either single-pin or complementary control
inputs. The PE4 28 3 operates usi ng a +3 volt power supply .
The PE4283 SPDT High Power RF Switch is manufactured
on Peregrine’s UltraCMOS™ process, a patented variation
of silicon-on-insulato r (SOI ) technology on a sapphire
substrat e, offering th e per f or m ance of GaAs with the
economy an d in te gr ation of conve nti o nal CMOS.
Figure 1. Functional Diagram
RFC
RF1RF2
SPDT High Power UltraCMOS™
DC – 4.0 GHz RF Switch
Features
• Single-pin or complementary CMOS
logic control inputs
• 1.5 kV ESD toleranc e
• Low insertion loss: 0.65 dB at
1000 MHz, 0.70 dB at 2500 MHz
• RFC-RF1/RF 2 isolation of 33. 5 dB at
1000 MHz, 21.5 dB at 2500 MHz
• RF1-RF2 isol ation of 37.5 dB at
1000 MHz, 22 dB at 2500 MHz
• Typical input 1 dB compression point
of +32 dBm
• Ultra-small SC-70 package
Figure 2. Package Typ e SC-7 0
6-lead SC-70
CMOS
Control
Driver
V1V2
Table 1. Electrical Specifications @ +25 °C, VDD = 3 V (Z
Parameter Conditions Typical Units
Operation Frequency1 DC - 4000 MHz
Insertio n Los s
Isolation: RFC - RF1/RF2
Isolation: RF1 - RF2
Return Loss
‘ON’ Switching Time 50% CTRL to 0.1 dB of final value, 1 GHz 0.725
‘OFF’ Switching Time 50% CTRL to 25 dB isolation, 1 GHz 0.625
Input 1 dB Co mpressio n 1000 MHz +32 dBm
physically short and connected to ground
plane for best performance.
RF Port2
RF Common
2
2
2
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Electrostatic Discharge (ESD) Precautions
When ha ndling this UltraCMOS™ devi ce, obse rve
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
This pin su pp orts two interf ac e options:
Single-pin control mode. A nomina l 3- v ol t
6 V2
Complementary-pin control mode. A
supply connection is required.
compl ementary CMOS control signal
to V1 is supplied to this pin.
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 3.
Figure 4. Maximum Operating Input Power
Note: 2. All RF pins must be DC blocked with an external series
capacitor or held at 0 VDC.
Parameter Min Typ Max Units
VDD Power Supply Voltage 2.0 3.0 3.3 V
I
Power Supply Current
DD
(V1
= 3V, V2 = 3V)
Control Voltage High 0.7x V
Control Voltage Low 0.3x V
8 50 µA
V
DD
V
DD
3
Table 3. Absolute Maximum Ratings
Symbol Parameter/Conditions Min Max Units
VDD
V
T
T
P
V
ESD
ST
OP
IN
Power supply voltage -0.3 4.0 V
Voltage on any input -0.3
I
Storage temperature
range
Operating temperature
range
Input power (50) +34 dBm
ESD Voltage (HBM,
ML_STD 883 Method
3015.7)
ESD Voltage (MM,
JEDEC, JESD22-A114-B)
-65 150 °C
-40 85 °C
1500 V
100 V
V
DD
0.3
+
V
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause perma nent devi ce damage.
Functional operation should be restricted to the
limits in the DC Electrical Specifications table.
Exposure to absolute maximum rat ings for
extended periods may affect device reliability.
Table 6. Complementary-pin Control Logic
Truth Table
Control Voltages Signal Path
Pin 6 (V2 ) = Low
Pin 4 (V1) = High
Pin 6 (V2) = High
Pin 4 (V1) = Low
RFC to RF1
RFC to RF2
Control Logic Input
The PE4283 is a versatile RF CMOS switch that
supports two operating control modes; single-pin
control mode and complementary-pin control
mode.
Single- pin c o ntr ol m od e enables the switch to
operate with a single control pin (pin 4) supporting
a +3-volt CMOS logic input, and requires a
dedicated +3-volt power supply connection (pin 6).
This mode of op er ation reduces the num ber of
control lines required and simplifies the switch
control interface typically derived from a CMOS
µProcessor I/O port.
Complementary-pin control mode allows the
switch to operate using complementary control
pins V1 and V2 (pi ns 4 & 6), that can be dir ectl y
driven by +3-volt CMOS logic or a suitable
µProcessor I/O port. This enables the PE4283 to
operate in positive control voltage mode within the
PE4283 op er ating limits.
The SPDT swit ch EK Board was designed to ease
customer evaluation of Peregrine’s PE4283. The
RF common (RFC) port is connected through a
50 transmission line via the top SMA connector,
J1. RF1 and RF2 are connected through 50
transmission lines via SMA connectors J2 and J3,
respectively. A through 50 transmission is
available via SMA connectors J4 and J5. This
transmission line can be used to estimate the loss
of the PCB over the environmental conditions
being evaluated.
The board is constructed of a two metal layer FR4
material with a total thickness of 0.031”. The
bottom layer provides ground for the RF
transmission lines. The transmission lines were
designed using a coplanar waveguide with ground
plane model using a trace width of 0.0476”, trace
gaps of 0.030”, dielectric thickness of 0.028”,
metal thickness of 0.0021” and
J6 and J7 provide a means for controlling DC and
digital inputs to the device. J6-1 is connected to
the device V2 input. J7-1 is connected to the
device V1 input. Series resistors (R1 and R2) are
provided to reduce the package resonance
between RF and DC lines.
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Data Sheet Identification
AdvanceInformation
The product is in a formative or design stage. The data
sheet contains design target specifications for product
development. Specifications and features may change in
any manner without notice.
Preliminary Specification
The data sheet contains preliminary data. Additional data
may be added at a later date. Peregrine reserves the right
to change specifications at any time without notice in order
to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine
decides to change the sp ec ific a tions, Peregrine will notify
customers of the intended changes by issuing a DCN
(Document Change Notice).
The information in this data sheet is believed to be reliable.
However, Peregrine ass umes no liability for the use of this
information. Use shall be entirely at the user’s own risk.
No patent rights or licenses to any circuits described in this
data sheet are implied or granted to any third party.
Peregrine’s products are not designed or intended for use in
devices or systems intended for surgical implant, or in other
applications intended to support or sustain life, or in any
application in which the failure of the Peregrine product could
create a situation in which personal injury or death might occur.
Peregrine assumes no liability for damages, including
consequential or incidental damages, arising out of the use of
its products in such applications.
The Peregrine name, logo, and UTSi are registered trademarks
and UltraCMOS and HaRP are trademarks of Peregrine
Semiconductor Corp.