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PE42672 DIE
SP7T UltraCMOS™ 2.75 V Sw itch
100 – 3000 MHz, +68 dBM IIP3
Figure 1. Functional Diagram
WCDMA
GSM/EDGE
GSM/EDGE
TX1
TX2
TX3
CMOS
Control/Driver
and ESD
V1 V2 V3
Figure 2. Die Top View*
TX1
GND
TX2
1206 µm
* Dimensions shown are drawn die size.
GND
TX3
GND
GND V
V3 GN
DD
1006 µm
ANT RX1
GND
RX2
GND
RX3
GND
RX4
GND
V2 V1 GND
RX1
RX2
RX3
RX4
Features
• Dedicated TX1 port for WCDMA, TX2
and TX3 ports for GSM / ED GE
• Three pin CMOS logic control with
integral decoder/driver
• Exceptional har m o nic per f or m ance:
= -84 dBc and 3fo = -77 dBc
2f
o
• Low TX insertion loss: 0.50 dB at
900 MHz, 0.70 dB at 1900 MHz
• TX – RX Isolation of 44 dB at 900 MHz,
38 dB at 1900 MHz
• 1500 V HBM ESD tolerance all ports
• +68 dBm IIP3
• -111 dBm IMD3
• No blocking capacitors required
Product Description
The PE42672 is a HaRP™-enhanced SP7T
RF Switch developed on the UltraCMOS™
process technology. It addresses the specific
design needs of the Quad-Band GSM Handset
Antenna Switch Module Market for use in
GSM/EDGE/PCS/DCS/WCDMA handsets.
The switch is comprised of three TX ports and
four RX ports. TX1 is designed for WCDMA
and TX2 and TX 3 ar e designed for GSM /
EDGE. The four symmetric RX ports can be
used for GSM/EDGE/PCS RX. On-chip CMOS
decoder logic facilitates three -pin low voltage
CMOS control, while high ESD tolerance of
1500 V at all por ts, no bloc king capaci t or
requirements, and on-chip SAW filter overvoltage protection devices make this the
ultimate in integration and ruggedness.
Peregrine’s HaRP™ technology
enhancements deliver high linearity and
exceptional harmonics performance. It is an
innovative feature of the UltraCMOS™
process , pr ov iding perfor m ance superi or to
GaAs with the ec o nom y an d in te gr ation of
conventional CMOS.
Document No. 70-0197-01 │ www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved.
Contact sales@psemi.com for full version of datasheet
Page 1 of 4
Table 1. Target Electrical Specifications @ 25 °C, VDD = 2.75 V
Parameter Condition Typ Units
PE42672
Advance Information
Insertio n loss
TX - Ant (850 / 900)
TX - Ant (1800 / 1900)
1
TX - Ant ( 2200 UMTS )
RX - Ant (850 / 900)
RX - Ant (1800 / 1900)
0.5
0.7
0.8
0.8
1.0
dB
dB
dB
dB
dB
Return Loss Port under test in on state 20 dB
TX - RX (850 / 900)
TX - RX (1800 / 1900)
Isolation
TX - TX (850 / 900)
TX - TX (1800 / 1900)
TX1 - RX (1900 / 2200)
2nd Harmonic
3rd Harmonic
IMD3 distortion at 2.14 GHz
Note: 1. Insertion loss specified with optimal impedance matching.
TX 850 / 900 MHz, +35 dBm output power, 50 Ω
TX 1800 / 1900 MHz, +33 dBm output power, 50 Ω
TX 850 / 900 MHz, +35 dBm output power, 50 Ω
TX 1800 / 1900 MHz, +33 dBm output power, 50 Ω
TX1 Measured at 2.14 GHz at Ant port, input +20 dBm CW signal
at 1.95 GHz and -15 dBm CW signal at 1.76 GHz
44
38
29
23
37
-84
-80
-77
-73
dB
dB
dB
dB
dB
dBc
dBc
dBc
dBc
-111 dBm
Table 2. Operating Ranges
Parameter Symbol Min Typ Max Units
Temperature range T
V
Supply Voltage VDD
DD
Power Supply Current
I
DD
(V
= 2.75 V)
DD
2
TX input power
(VSWR ≤ 3:1)
RX input power
(VSWR =1:1)
Control Voltage High V
Control Voltage Low V
Note: 2. Assum es RF in p ut period of 4620 µs and duty cycle of 50%.
2
-40 +85 °C
OP
2.65 2.75 2.85
I
DD
P
+35 dBm
IN
P
+20 dBm
IN
1.4 V
IH
0.4 V
IL
13 50
V
µA
Table 3. Absolute Maximum Ratings
Symbol Parameter/Conditions Min Max Units
V
Power supply voltage -0.3 4.0 V
DD
Voltage on any input -0.3 VDD+ 0.3 V
V
I
Storage temperature range -65 +150 °C
T
ST
P
IN
P
Note: 3. Assum es RF in p ut period of 4620 µs and duty cycle of 50%.
4. V
TX input power (50 Ω)
(50 Ω)
RX input power (50 Ω)
(∞:1) TX input power (VSWR = ∞:1)
IN
ESD Voltage (HBM, MIL_STD
883 Metho d 30 15.7)
V
ESD
ESD Voltage at ANT Port
(IEC 61000-4-2)
within operating range specified in Table 2.
DD
3,4
3,4
+38
+23
3,4
+35 dBm
1500 V
1700 V
dBm
Part perfor m ance is not guar an te ed under these
cond itions. Exposure to absolute maximum
conditio ns for exte nded periods of ti m e ma y
adversely affect reliability. Stresses in excess of
absolute maximum ratings may cause permanent
damage.
©2005 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0197-01 │ UltraCMOS™ RFIC Solutions
Page 2 of 4
Contact sales@psemi.com for full version of datasheet
PE42672
Advance Information
Table 4. Pin Descriptions
Pin No. Pin Name Description
1 ANT RF Common – Antenna
6
2
TX1 RF I/O - TX1
5
GND Ground (Requires two bo nd wir es )
3
6
TX2 RF I/O – TX2
4
5
GND Ground
5
5
TX3 RF I/O – TX3
6
5
GND Ground
7
5
GND Ground
8
9 V
10 V3 Switch control input, CMOS logic level
5
GND Ground
11
12 V2 Switch control input, CMOS logic level
13 V1 Switch control input, CMOS logic level
5
GND Ground
14
5
GND Ground
15
6
RX4 RF I/O – RX4
16
175 GND Ground
186 RX3 RF I/O – RX3
195 GND Ground
6
RX2 RF I/O – RX2
20
5
GND Ground
21
6
RX1 RF I/O – RX1
22
Notes: 5. Bond wires should be physically short and connected to
ground plan e for bes t perform anc e .
6. Blocking capacitors needed only when non-zero DC
voltage present.
Supply
DD
Figure 3. Pad Configuration (Top View)
ANT
V2
V1
22
RX1
21
GND
20
RX2
19
GND
18
RX3
17
GND
16
RX4
15
GND
GND
TX1
GND
TX2
GND
TX3
GND
GND
2
3
4
5
6
7
6
9
8
DD
V
1
PE42672
Die
10
V3
111213 14
GND
Table 5. Truth Table
Path V1 V2 V3
RX1 - ANT
0 0 0
RX2 - ANT 1 0 0
RX3 - ANT 0 1 0
RX4 - ANT
TX1 - ANT
1 1 0
0 0 1
TX2 - ANT 1 0 1
TX3 - ANT 0 1 1
All Off
1 1 1
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS ™
devices are immune to latch-up.
Table 6. Ordering Information
Order Code Description Package Shipping Method
42672-90 PE42672-DIE-D
42672-99 PE42672-DIE-400G Waffle Pack 400 Dice / Waffle Pack
42672-00 PE42672-DIE-1H Evaluation Kit 1/ box
Document No. 70-0197-01 │ www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved.
Contact sales@psemi.com for full version of datasheet
Film Frame
Wafer (Gross Die / Wafer Quantity)
Page 3 of 4
Sales Offices
PE42672
Advance Information
The Americas
Peregrine Semiconductor Corp.
9450 Carroll Park Drive
San Diego, CA 92121
Tel 858-731-9400
Fax 858-731-9499
Europe
Peregrine Semiconductor Europe
Commercial Products:
Bâtiment Maine
13-15 rue des Quatre Vents
F- 92380 Garches, France
Tel: +33-1-47-41-91-73
Fax : +33-1-47-41-91-73
Space and Defense Products:
180 Rue Jean de Guiramand
13852 Aix-En-Provence cedex 3, France
Tel: +33(0) 4 4239 3361
Fax: +33(0) 4 4239 7227
North Asia Pacific
Peregrine Semiconductor K.K.
5A-5, 5F Imperial Tower
1-1-1 Uchisaiwaicho, Chiyoda-ku
Tokyo 100-0011 Japan
Tel: +81-3-3502-5211
Fax: +81-3-3502-5213
South Asia Pacific
Peregrine Semiconductor
28G, Times Square,
No. 500 Zhangyang Road,
Shanghai, 200122, P.R. China
Tel: +86-21-5836-8276
Fax: +86-21-5836-7652
For a list of representatives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data
sheet contains design target specifications for product
development. Specifications and features may change in
any manner without notice.
Preliminary Specification
The data sheet contains preliminary data. Additional data
may be added at a later date. Peregrine reserves the right
to change specifications at any time without notice in order
to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine
decides to change the sp ec ific a tions, Peregrine will notify
customers of the intended changes by issuing a DCN
(Document Change Notice).
The information in this data sheet is believed to be reliable.
However, Peregrine ass umes no liability for the use of this
information. Use shall be entirely at the user’s own risk.
No patent rights or licenses to any circuits described in this
data sheet are implied or granted to any third party.
Peregrine’s products are not designed or intended for use in
devices or systems intended for surgical implant, or in other
applications intended to support or sustain life, or in any
application in which the failure of the Peregrine product could
create a situation in which personal injury or death might occur.
Peregrine assumes no liability for damages, including
consequential or incidental damages, arising out of the use of
its products in such applications.
The Peregrine name, logo, and UTSi are registered trademarks
and UltraCMOS and HaRP are trademarks of Peregrine
Semiconductor Corp.
©2005 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0197-01 │ UltraCMOS™ RFIC Solutions
Page 4 of 4
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