Peregrine PE42660 DIE Specification

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Product Description

Preliminary Specification

PE42660 DIE

SP6T UltraCM OS™ 2.75 V Switch 100 – 3000 MHz

The PE42660 is a HaRP™-enhanced SP6T RF Switch developed on the UltraCMOS™ process technology. It addresses the specific design needs of the Quad-Band GSM Handset Antenna Switch Module Market. On-chip CMOS decode logic facilitates three -pin low voltage CMOS control, while high ESD toleranc e of 15 00 V at all por ts , no block ing capacitor r eq ui r em e nts, an d on- chip SAW filt er ov er - vol ta ge protection devices make this the ultimate in integration and ruggedness.

Peregrine’s HaRP™ technology enhancements deliver high linearity an d ex ce pti o n al har m oni cs p er for m a nce. It is an innovative feature of the UltraCMOS™ process, providing performance superior to GaAs with the economy and

Features

• Three pin CMOS logic control with

integral decoder/driver

• Exceptional harmonics performance:

2f

= -88 dBc and 3fo = -85 dBc

o

• Low TX insertion loss: 0.55 dB at

900 MHz, 0.65 dB at 1900 MHz

• TX – RX Isolation of 48 dB at 900 MHz,

40 dB at 1900 MHz

• 1500 V HBM ESD tolerance all ports

• 41 dBm P1dB

• No blocking capacitors required

integration of conventional CMOS.

Figure 1. Functional Diagram Figure 2. Die Top View

TX1

TX2

CMOS

Control/Driver

and ESD

V2 V3

V1

RX1

RX2

RX3

RX4

GND GND

TX2 GND

GND V

ANT TX1

DD

V3 GND V2 V1 GND

RX1

GND RX2

GND RX3

GND RX4

GND

Page 1 of 9

Table 1. Electrical Specifications @ +25 °C, VDD = 2.75 V (ZS = ZL = 50 )

Parameter Conditions Typical Units

Operational Frequency 100-3000 MHz

PE42660

Preliminary Specification

ANT - TX - 850 / 900 MHz

Insertio n Los s

ANT - TX - 1800 / 1900 MHz ANT - RX - 850 / 900 MHz ANT - RX - 1800 / 1900 MHz

TX - RX - 850 / 900 MHz TX - RX - 1800 / 1900 MHz

Isolation

TX - TX - 850 / 900 MHz TX - TX - 1800 / 1900 MHz ANT - TX - 850 / 900 MHz ANT - TX - 1800 / 1900 MHz

Return Loss

2nd Harmonic

3rd Harmonic

850 / 900 MHz 1800 / 1900 MH z

35 dBm TX Input - 850 / 900 MHz 33 dBm TX Input - 1800 / 1900 MHz

Switching Time (10-90%) (90-10%) RF 2

Table 2. Operating Ranges

0.55

0.65

0.90

1.00

48 40 29 25 31 25

22 23

-88

-85

-84

dB dB dB dB

dB dB dB dB dB dB

dB

dBc

µs

Parameter Symbol Min Typ Max Units

Temperature range TOP -40 +85 °C V

Supply Voltage VDD

DD

Power Supply Current

I

DD

(V

= 2.75 V)

DD

TX input power

1

(VSWR  3:1)

1

RX input power (VSWR 1:1)

Control Voltage High V

Control Voltage Low V

P

2.65 2.75 2.85

I

DD

+35 dBm

IN

+20 dBm

IN

IH

IL

0.7 x V

DD

13 20

V

0.3 x V

Note: 1. Assum es RF in p ut period of 4620 µs and duty cycle of 50%.

Page 2 of 9

V

µA

V

DD

PE42660

Preliminary Specification

Figure 3. Pin Configuration (Top View)

ANT

2

TX1

GND

3

GND

4

TX2

5

GND

6 7 8 9 1 0 11 12

DD

V

GND

1

PE42660

Die

V3

20

RX1

19

GND

18

RX2

17

GND

16

RX3

15

GND

14

RX4

13

GND

V2

V1

GND

Table 3. Pin Descriptions

Pin No. Pin Name Description

13 ANT RF Common – Antenna

3

TX1 RF I/O - TX1

2

GND Ground (Requ ires tw o bo nd wires)

3

T X2 R F I/O – TX 2

4

2

GND Ground

5

2

GND Ground

6

7 V 8 V3 Switch control input, CMOS logic level

2

GND Ground

9 10 V2 Switch control input, CMOS logic level 11 V1 Switch control input, CMOS logic level

2

GND Ground

12

2

13

GND Ground

3

RX4 RF I/O – RX4

14

2

GND Ground

15

3

RX3 RF I/O – RX3

16

2

GND Ground

17

3

RX2 RF I/O – RX2

18

2

GND Ground

19

3

20

RX1 RF I/O – RX1

Supply

DD

Table 4. Absolute Maximum Ratings

Symbol Parameter/Cond itions Min Max Units

VDD Power supply voltage -0.3 4.0 V

V

Voltage on any input -0.3 VDD+ 0.3 V

I

T

Storage temperature range -65 +150 °C

ST

P

IN

P

IN

TX input power (50 )

(50 )

RX input power (50 )

(:1) TX input power (VSWR :1)

4,5

ESD Voltage (HBM, MIL_STD 883 Metho d 30 15.7)

V

ESD

ESD Voltage at ANT Port (IEC 61000-4-2)

Notes: 4. Assumes RF input period of 4620 µs and duty cycle of 50%.

5. V

within operating range specified in Table 2.

DD

+38 +23

4,5

+35 dBm

1500 V

1700 V

dBm

Part perfor m ance is not guar an te ed under these cond itions. Exposure to absolute maximum conditio ns for exte nded periods of ti m e ma y adversely affect reliability. Stresses in excess of absolute maximum ratings may cause permanent damage.

Table 5. Truth Table

Path V3 V2 V1

ANT – RX1 0 0 0 ANT – RX2 0 0 1 ANT – RX3 0 1 0 ANT – RX4 0 1 1

ANT - TX1 1 0 x ANT - TX2 1 1 x

Electrostatic Discharge (ESD) Precautions

When ha ndling this UltraCMOS™ devi ce, obse rve the same precautions that you would use with othe r ESD-sensitive devices . Although this de vice contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the specified rating.

Notes: 2. Bond wires should be physically short and connected to

Latch-Up Avoidance

ground plan e f or bes t performanc e.

3. Blocking capacitors needed only when non-zero DC voltage present.

Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up.

Page 3 of 9

PE42660

Preliminary Specification

Evaluation Kit

The SP6T Evaluation Kit board was designed to ease customer evaluation of the PE42660 RF switch.

The PE42660 has two high power TX ports and four high isolation RX ports. The TX ports are symmetric and are designed as paths for the 850, 900, 1800, or 1900 MHz bands. The RX ports are also symmetric and can be assigned to any of these frequency bands.

The ANT port connects through a 50  transmission line to the top SMA connector, J1. The RX and TX ports connect through 50  transmission lines to SMA connectors J2 – J7. A through 50  transmission line between SMA connectors J9 and J10 allows estimation of the PCB losses over environmental conditions. An open transmission line connected to J11 is also provided.

J8 supplies DC power to the pin marked V bottom row of pins, which is GND. 1 M pull-up resistors are connected from V

to each of the three

DD

control logic inputs: V1, V2, and V3. These pull-up resistors are provided for ease of evaluation on this board and are not required for the PE42660 to operate.

Adding a jumper between a control pin and the adjacent GND pin on the botto m row of J8 will set a logic-0 on that co nt rol pin. Removing the jumper will set a logic-1. To evaluate the PE42660, add or remove jumpers according to the truth table in Table 5.

and the

DD

Figure 4. Evaluation Board Layout

Peregrine Specification 101/0205

ANT RX1

TX1

TX2

RX4

Open Line

Figure 5. Evaluation Board Schematic

Peregrine Specification 102/0267

RX2

RX3

Through- Line

Page 4 of 9

 UltraCMOS™ RFIC Solutions

PE42660

Preliminary Specification

Electrical Test and Performance Specifications

PE42660 dice are 100% electric ally tested for the parameters list ed below from Table 1 and Table 2. All other parameter s ar e guar anteed through design and characterization.

• Inser tion Loss (all ports)

• TX1 & TX 2 Harmonics

• TX – RX Isolation

supply current

• I

DD

• Control pin leak ages

Wafer and Die Packaging

Peregrine Semiconductor has two methods for shipping dice to our customers . T he s hipping option used is based on the customer’s requirements and the number of dice.

Peregrine offers product dice in two packaging options: Standard Die Carrier P ac k ages ( waff le pac k ) and dice on Film Frames.

Wafer Mount/Dicing

In preparation for dicing, wafers are thinned and polished and 100% electric ally probed prior to mounting on film fr ame tape and rings. Figure 6 shows a wafer mounted on film frame using PVC backed mounting tape. In preparation for shipment, wafer s are visually inspected af ter singulation and shipped with an electronic map file pr oviding good dice locations.

Figure 6. Wafer on Film Frame

Figure 7. Dice and Wafer Processing Flow

Wafer

Processing

Visual

Inspection

Process Control

Moni tor (PCM )

Wafer Level

Reliabili ty (WLR)

Backgrind and Polish

100%

Electrical Test

Ink Reject Die or Electronic Wafer

Map

Outgoing QA

Inspection

Wafer

Singulation

100% Visual

Inspection

Pack and Ship

Wafers

Figure 8. Waf f le Pa ck

Dice Picking

Carrier Loading

Pack and Ship

Dic e

Storage and Preservation

Proper storage c onditions are necessary to prevent product contamination and/or degradation after shipment.

Product should be st ored in the original unopened packaging or, once opened, in a nitrogen purged cabinet at room temper ature (45% + 15% relative humidity controlled env ironment).

Singulated wafers mounted on film frames are intended for immediate use and hav e a limited s helf life. This is primarily due to the nature of the adhesive tape used for mounting the pr oduct. This product can be stored up to 30 days. This applies whet her or not the material has remained in its original sealed c ontainer. To reduce the risk of contam ination or degradation, it is recommended that pr oduc t not being us ed in the assembly process be returned to their original containers and resealed with a vacuum seal process.

Document No. 70-0192-02

Standard Die Carrier Package/Waffle Pack

Waffle packs are av ailable to customers during product development and protot yping phase only. Orders will move to film frames at production launch or for large quantity requirements.

Dice have been 100% electrically probed, singulated, visually inspected and ar e pac k aged in a 2” x 2” waffle pack (400 dice per waffle pack).

Page 5 of 9

PE42660

Preliminary Specification

Die Handling

All die products must be handled only at ESD safe workstations us ing standard ESD precautions. It is recommended that the die be handled only in a class 10,000 or better des ignated clean room environment.

Singulated dice are not t o be handled with tweezers. A vacuum wand with a non-met allic E SD protected tip must be used.

Recommended Dice Assembly Procedure

Cleaning

Dice do not require cleaning prior to assembly.

Die Attach

The PE42660 die substr ate is sapphire – the recommended die attach operation for sapphire is epoxy die attach adhesiv e. An eutectic die attach method does not work with s apphir e s ubs trates.

Bonding

Thermo com pression gold ball or aluminum ultrasonic bonding may be used. The ball should cover the bonding pad, but not excessively, or it may short out the surrounding metallizat ion. Aluminum or gold 1-mil wir e is recommended. Note the bonding pad material is aluminum.

Shipping Method

Standard die carrier pac k ages and wafer film frames are placed in a wafer container and then vacuumsealed inside an ESD shielded bag. S ealed pr oduc t is then placed inside a corrugated cardboard box surrounded by bubble wrap or f oam for maximum protection during s hipm ent.

Page 6 of 9

 UltraCMOS™ RFIC Solutions

PE42660

Preliminary Specification

Table 6. Mechanical Specifications

Parameter Minimum

Die Size (x,y)

Die Size (x,y) 1.25 x 1.21 mm

Wafer Thic k n es s 180 200 220 µm Wafer Size

Typical

1.146 x 1.106

150

Maximum Units Test Conditions

mm As drawn

Including exce ss sapphire, max. tole rance

= ±0.1mm in either dimension

mm

Table 7. Pad Coordinates

All pad locations originate from the die center and refer to the center of the pad.

All pad open in gs ar e 60 x 60 µm ex c ept for Pad # 3 wh ic h is 140 x 60 µm . Minimu m pa d pitch is 80 µm.

Note 1. - Double pad, requires two bond wires.

Pad # Pad Name

1 ANT 2 TX1 3 GND1 4 TX2 5 GND 6 GND 7 VDD 8 V3 9 GND

Pad Center (µm)

X Y

488.1

1.9

491.3

-511.3

168.9

-511.3

-153.5

-511.3

-233.5

-511.3

-491.3

-511.3

-491.3

-337.7

-491.3

25.7

-491.3

160.9

Figure 9. Pad Numbering

2

TX1

GND

3

GND

1.21 mm

TX2

GND

4

5

1.25 mm

ANT

1

PE42660

Die

20

RX1

19

GND

18

RX2

17

GND

16

RX3

15

GND

14

RX4

13

GND

10 V2 11 V1 12 GND 13 GND 14 RX4 15 GND 16 RX3 17 GND 18 RX2 19 GND 20 RX1

Document No. 70-0192-02

-491.3

296.1

-491.3

376.1

-491.3

511.3

-223.7

511.3

-105.1

511.3

-25.1

511.3

93.5

511.3

173.5

511.3

292.1

511.3

372.1

511.3

511.3 490.7

6 7 8 9 10 11 12

VDD

GND

V3

V2

GND

V1

Page 7 of 9

GND

PE42660

Preliminary Specification

ESD Protection Circuit

Handset products must tolerate large ESD surges at the antenna interface without damage. The IEC 61000-4-2 standard specifies both 8 kV contact and 16 kV air discharges that typical handsets must survive. By itself, the PE42660 offers protection to 1.5 kV but with the addition of two inexpensive passive components, the switch can meet the levels as specified in the IEC spec. Figure 10 is the suggested solution for compliance with the IEC standards.

Table 8. PE42660 Antenna Application Test Results

C=150 pF, R=330 Ω, IEC 61000-4-2 Stand ard)

(

Test Condition Results

+8 kV contact discharge, 10 times with 1s intervals Pass

Figure 10. ESD Protection Circuit

PE42660

ESD Protection

L = 27 nH (muRat a: LQG1127NJ00) ,

C = 33 pF (muRat a: GRM33C0G330J50)

-8 kV contact discharge, 10 times with 1s intervals Pass +16 kV air discharge, 10 times with 1s intervals Pass

-16 kV air discharge, 10 times with 1s intervals Pass

Table 9. Ordering Information

Order Code Die ID Description Package Shipping Method

42660-90 C9807_01 PE42660-DIE-D 42660-99 C9807_01 PE42660-DIE-400G Waffle Pack 400 Dice / Waffle Pack

42660-00 C9807_01 PE42660-DIE-1H Evaluation Kit 1/ box

Film Frame

Wafer (Gross Die / Wafer Quantity)

Page 8 of 9

 UltraCMOS™ RFIC Solutions

PE42660

Preliminary Specification

Sales Offices

The Americas

Peregrine Semiconductor Corp.

9450 Carroll Park Drive San Diego, CA 92121 Tel 858-731-9400 Fax 858-731-9499

Europe

Peregrine Semiconductor Europe

Commercial Products:

Bâtiment Maine 13-15 rue des Quatre Vents F- 92380 Garches, France Tel: +33-1-47-41-91-73 Fax : +33-1-47-41-91-73

Space and Defense Products:

180 Rue Jean de Guiramand 13852 Aix-En-Provence cedex 3, France Tel: +33(0) 4 4239 3361 Fax: +33(0) 4 4239 7227

North Asia Pacific

Peregrine Semiconductor K.K.

5A-5, 5F Imperial Tower 1-1-1 Uchisaiwaicho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213

South Asia Pacific

Peregrine Semiconductor

28G, Times Square, No. 500 Zhangyang Road, Shanghai, 200122, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652

For a list of representatives in your area, please refer to our Web site at: www.psemi.com

Data Sheet Identification

Advance Information

The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice.

Preliminary Specification

The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product.

Product Specification

The data sheet contains final data. In the event Peregrine decides to change the sp ec ific a tions, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice).

The information in this data sheet is believed to be reliable. However, Peregrine ass umes no liability for the use of this information. Use shall be entirely at the user’s own risk.

No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party.

Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications.

The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS and HaRP are trademarks of Peregrine Semiconductor Corp.

Document No. 70-0192-02

Page 9 of 9

Peregrine PE42660 DIE Specification

Specifications and Main Features

Frequently Asked Questions

User Manual