Pentek 6210 Operating Manual

Download

Page 1

Pentek Model 6210 Operating Manual Page 1

OPERATING MANUAL

PENTEK MODEL 6210

Dual A/D Converter and Digital Receiver

VIM Module for Pentek VIM Motherboards

Pentek, Inc.

One Park Way

Upper Saddle River, NJ 07458

(201) 818−5900

http://www.pentek.com/

Manual Part #: 800.62100 Rev.: C − April 5, 2001

Page 2

Page 2 Pentek Model 6210 Operating Manual

Pentek Model 6210 Operating Manual − Revision History

Date Rev Applicable Serial #’s Comments

08/14/98 Preliminary 9841001 − Forward 11/16/98 Preliminary 9841001 − Forward

2/18/99 Preliminary 9841001 − Forward

3/24/99 Preliminary 9841001 − Forward

6/24/99 Preliminary 9841001 − Forward

3/6/00 A 9841001 − Forward

3/9/00 A.1 9841001 − Forward

3/17/00 B 98041001 − Forward

3/21/00 B.1 98041001 − Forward

10/24/00 B.2 98041001 − Forward

4/5/01 C 98041001 − Forward

Initial release.

Added bit D04 to the Control Register. Added Table 2−4 to explain PRCLK source and freq. when the 6210 is a master. Added Figure 2−4 to show Sync and Clock signal sources.

Added table 3−12 on loading DAC. Added Section 3.8.1 explaining Gain Amplifier. Added EEPROM format (Appendix A). Added sample code in Appendix B.

Replaced installation instructions, they now reflect the currently shipping product. Replaced the Front Panel with the currently shipping product. Added Table 3−13 about full scale values.

Corrected Figure 2−4, the sync lines were connected to the wrong place. Added note to Fig− ure 2−4 about which Harris Chip is connected to which DSP on the Model 4290/4291. Cor− rected figure 2−1, the Front Panel labeling changed slightly. Corrected option 102 (gain), which was called option 101 throughout the manual. Added option 101 to the specs. Replaced Harris addendum with current version.

Complete re−format − many tables removed & replaced w/ text. All references to 4290/91 changed to VIM motherboard, and non−address specific references to ‘C6x changed to VIM motherboard processor. Updated & corrected Block Diagram. Sec. 1.7. Corrected supply currents. Internal Oscillator is 64 MH z, not 65. Further corrections to Fig. 2−4. Note that Gain values given in Table 3−6 for PGA do not account for filter insertion loss. Add Table 3− 9 describing format/packing of output data. Improved description of signal levels/limits for EXT CLK IN. Improved description of control interface to HSP50214. Re−arrange Appendices − Move EEPROM format to Appendix D; Replace Harris’s Data Sheet for HSP50214 with Intersil’s & make it Appendix A; Add AD603 Data Sheet as Appendix B; LTC1451 Data Sheet is Appendix C; Add bandwidth / sample rate calculation Application Note as Appendix E; Old Appendix B (Programming Example) now covered in ReadyFlow Manual for 6210 (Pentek part # 801.62100)

Add Options 020, 021, 030 & 101 to Specifications. Add AD6640 Data Sheet as Appendix B. Bum p all foll owing Appendix name s up 1 lett er. Cor rect DDR part # in F ig. F .1 & TOC li st− ing for the figure. Also corrected another typo in Appendix F.

Copy Table 2−4 (PRCLK Divider) into Sec. 3.4.1, where the divider bit is discussed, as Table 3−3. Added Table 3−11 (A/D Output Data Coding) in Sec. 3.8.2. Other Table #’s changed appropriately.

Logic was reversed for BIFO_Disable bit, D3 in Control Reg. Corrected in Table 3−2 and Sec.

3.4.2. Sect 1.2 and 1.7, clarified the descriptions of Options 030 and 102.

Sec. 1.3 − Changed Option 101 in NOTE to Option 020. Sec. 2.3.1 − recommend that Ext. Clock In be 2V p−p in amplitude. Add Sec. 2.3.1.1, on Duty Cycle Sensitivity. Sec. 2.4 − add part #’s for Sync Bus − Serial I/O mating connector. Sec 2.4.1 − mention that Sync Bus can support 8 units, & Model 9190 can sync up to 80 units. Also correct NOTE below Fig. 2−5 − DDR2 is controlled by Proc. B or D. Add Sec. 2.4.1.6, on Sync Bus Compatibility. Sec. 2.4.2 − Better description of how Serial Port signals are passed from Motherboard to FP connector, less text in subsections. Sec. 2.4.3 − TTL−SYNC

pulse must be at least 2 sample clocks wide.

WARRANTY

Pentek warrants that all products manufactured by Pentek conform to published Pentek specifications and are free from defects in materials and workmanship for a period of one year from the date of delivery when used under normal operating conditions and within the service conditions for which they were furnished.

The obligation of Pentek arising from a warranty claim shall be limited to repairing or at its option, replacing without charge, any product which in Pentek’s sole opinion proves to be defective within the scope of the warranty.

Pentek must be notified in writing of the defect or nonconformity within the warranty period and the affected product returned to Pentek within thirty days after discovery of such defect or nonconformity.

Buyer shall prepay shipping charges, taxes, duties and insurance for products returned to Pentek for warranty service. Pentek shall pay for the return of products to buyer except for products returned from another country.

Pentek shall have no responsibility for any defect or damage caused by improper installation, unauthorized modification, misuse, neglect, inadequate maintenance, accident or for any product which has been repaired or altered by anyone other than Pentek or its authorized representatives.

The warranty described above is buyer’s sole and exclusive remedy and no other warranty, whether written or oral, is expressed or implied. Pentek specifically disclaims fitness for a particular purpose. Under no circumstances shall Pentek be liable for any direct, indirect, special, incidental or consequential damages, expenses, losses or delays (including loss of profits) based on contract, tort, or any other legal theory.

COPYRIGHT INFORMATION

Appendices B & C, AD6640 and AD603 Data Sheets, are the copyrighted property of Analog Devices, Inc., Norwood MA, and are used with their kind permission.

Appendix A, HSP50214B Data Sheet, is the copyrighted property of Intersil Corp., Palm Bay, FL, and is used with their kind permission.

Appendix D, LTC1451 Data Sheet, is the copyrighted property of Linear Technology Corp., Milpitas, CA, and is used with their kind permission.

Page 3

Pentek Model 6210 Operating Manual Page 3

Table of Contents

Page

Chapter 1: Overview

1.1 General Description..............................................................................................................................7

1.2 Input Section ...................................................................................................................................7

1.3 A/D Converters....................................................................................................................................8

1.4 Digital Drop Receivers.........................................................................................................................8

1.5 Connection to VIM Motherboard.......................................................................................................8

1.6 Simplified Block Diagram ...................................................................................................................9

Figure 1−1: Simplified Block Diagram ...........................................................................................9

1.7 Specifications .......................................................................................................................................10

Chapter 2: Installation and Connections

2.1 Inspection.............................................................................................................................................13

2.2 Jumper Blocks......................................................................................................................................13

Table 2−1: Factory Jumper Settings...............................................................................................13

Figure 2−1: Model 6210 PC Board, Showing Jumper Blocks & Mounting Holes................14

2.2.1 External Clock Function Select Jumper ..........................................................................13

Table 2−2: External Clock ..............................................................................................13

2.3 Model 6210 Front Panel Features .....................................................................................................15

Figure 2−2: Model 6210 Front Panel..............................................................................................15

2.3.1 External Clock Input − EXT CLK ....................................................................................15

Figure 2−3: External Clock Input Circuit ....................................................................16

2.3.1.1 Duty Cycle Sensitivity ...................................................................................15

2.3.2 Analog Inputs − CH1 IN, CH2 IN....................................................................................17

2.3.3 Indicator LEDs ...................................................................................................................17

2.3.3.1 Sync Bus Master LED − MAS.......................................................................18

2.3.3.2 Sync Bus Terminator LED − TRM ...............................................................18

2.3.3.3 Motherboard LEDs − 0, 1, 2 & 3 ..................................................................18

2.4 Sync Bus − Serial I/O Connector .....................................................................................................19

Figure 2−4: Front Panel Sync Bus − Serial I/O Connector Pin Numbering..........................19

2.4.1 Signals for Synchronizing Multiple Boards ...................................................................19

Table 2−3: Sync Bus − Serial I/O Pinouts ...................................................................19

Figure 2−5: Block Diagram of Clock and Sync Signal Sources ..............................20

2.4.1.1 MCLK, MCLK

2.4.1.2 PRCLK, PRCLK

Table 2−4: Master PRCLK Signal Source & Frequency........................22

2.4.1.3 MSYNC, MSYNC

2.4.1.4 SYNC1, SYNC1

2.4.1.5 SYNC2, SYNC2

2.4.1.6 Compatibility with Other Products’ Sync Buses ......................................23

.................................................................................................21

..............................................................................................21

...........................................................................................22

...............................................................................................22

...............................................................................................23

Rev.: C

Page 4

Page 4 Pentek Model 6210 Operating Manual

Table of Contents

Page

Chapter 2: Installation and Connections (continued)

2.4 Sync Bus − Serial I/O Connector

2.4.2 Serial Port Signals.............................................................................................................. 24

2.4.2.1 P0−CLKR1, P1−CLKR1................................................................................. 24

2.4.2.2 P0−FSR1, P1−FSR1 ........................................................................................ 24

2.4.2.3 P0−CLKS1, P1−CLKS1 .................................................................................. 24

2.4.2.4 P0−DR1, P1−DR1 ........................................................................................... 24

2.4.2.5 P0−CLKX1, P1−CLKX1................................................................................. 25

2.4.2.6 P0−FSX1, P1−FSX1 ........................................................................................ 25

2.4.2.7 P0−DX1, P1−DX1........................................................................................... 25

2.4.3 TTL−SYNC

2.5 Installing the Model 6210 on a VIM Motherboard........................................................................26

2.5.1 Preparing the VIM Module for Installation................................................................... 26

Figure 2−6: VIM Module Countersunk Screws ........................................................26

Figure 2−7: VIM Module Nylon Spacer...................................................................... 27

2.5.2 Installing the VIM Module on the VIM Motherboard................................................. 28

Figure 2−8: Model 4290 VIM Motherboard − Connectors & Mounting Holes ... 29

......................................................................................................................... 25

(continued)

Chapter 3: Memory Map and Register Descriptions

3.1 Overview ............................................................................................................................................. 31

3.2 Model 6210 Memory Map ................................................................................................................. 31

Table 3−1: Model 6210 Memory Map........................................................................................... 31

3.3 ID EEPROM Readout Register ............................................................................................................. 32

3.4 Control Register.................................................................................................................................. 32

Table 3−2: Control Register .......................................................................................................32

3.4.1 PROCCLK Frequency Divider ........................................................................................ 32

Table 3−3: Master PROCCCLK Signal Source & Frequency..................................33

3.4.2 BIFO Disable..................................................................................................................33

3.4.3 External Clock Enable....................................................................................................... 33

3.4.4 Termination Enable........................................................................................................... 33

3.4.5 Master / Slave

3.5 Master Clock Divider......................................................................................................................... 34

Table 3−4: Master Clock Divider ..............................................................................................34

3.6 BIFO Decimation Register................................................................................................................. 35

Table 3−5: Motherboard BIFO Decimation Register ............................................................... 35

3.7 Programmable Gain Amplifier............................................................................................................. 36

Table 3−6: Programmable Gain Amplifier Register.................................................................. 36

3.7.1 Loading the 12−bit Gain Control Word ......................................................................... 36

Table 3−7: Gain Control Word vs. Full Scale Input Amplitude ............................ 37

Table 3−8: Sequence for Loading Gain Control Word ............................................ 37

.................................................................................................................... 34

Rev.: C

Page 5

Pentek Model 6210 Operating Manual Page 5

Table of Contents

Page

Chapter 3: Memory Map and Register Descriptions (continued)

3.8 Data Format / Signal Path Register ...................................................................................................... 38

Table 3−9: Data Format / Signal Path Register ...........................................................................38

3.8.1 Decimate DDR Input by 2 ................................................................................................38

3.8.2 Pack Mode ..........................................................................................................................38

Table 3−10: Output Data to Motherboard BIFO − Packing Formats........................ 39

Table 3−11: A/D Output Data Coding .........................................................................40

3.8.3 Programmable−Gain Amplifier & Low−Pass Filter Bypass .......................................40

3.8.4 DDR Bypass........................................................................................................................41

3.9 SYNC Generate Register ....................................................................................................................41

3.10 Serial Port 0 Connection Register .......................................................................................................... 42

Table 3−12: Serial Port 0 Connection Register ............................................................................42

3.10.1 The Other Processor’s Serial Port 0 Transmit Section ..................................................42

3.10.2 The Other Processor’s DDR .............................................................................................42

3.10.3 The Processor’s Own DDR ...............................................................................................42

3.10.4 Not Connected ...................................................................................................................43

3.11 CIC Gain Adjust Register ..................................................................................................................43

Table 3−13: CIC Gain Adjust Register .........................................................................................43

3.12 Processor Interface the HSP50214 DDR ..........................................................................................43

Table 3−14: DDR Interface Resources ..........................................................................................44

Table 3−15: DDR Read Source Definitions .................................................................................45

Table 3−16: DDR Status Read Register ........................................................................................45

Appendix A: Intersil HSP50214B − Programmable Downconverter

Appendix B: Analog Devices AD6640 − 12−Bit, 65 MSPS IF Sampling A/D Converter

Appendix C: Analog Devices AD603 − Variable Gain Amplifier

Appendix D: Linear Technology LTC1451 − 12−bit Rail to Rail DAC

Rev.: C

Page 6

Page 6 Pentek Model 6210 Operating Manual

Table of Contents

Page

Appendix E: Configuration EEPROM Format

E.1 Introduction ..................................................................................................................................... E−1

Table E−1: VIM ID EEPROM Register ..................................................................................... E−1

E.2 EEPROM Format Example ............................................................................................................ E−1

Table E−2: EEPROM Example (Model 6210 shown) .............................................................. E−2

Appendix F: Application Note

F.1 Introduction ..................................................................................................................................... F−1

Figure F−1: HSP50214 Simplified Block Diagram.................................................................. F−1

F.2 Output Sample Rate and Bandwidth Specifications .................................................................. F−1

F.3 Calculating the Low Pass Bandwidth .......................................................................................... F−2

F.4 Calculating the Output Rate Using the Standard 64 MHz Clock ............................................ F−2

F.5 Calculating the Low Pass Bandwidth Using the Standard 64 MHz Clock............................. F−2

F.6 Additional Information/References............................................................................................. F−3

Rev.: C

Page 7

Pentek Model 6210 Operating Manual Page 7

Chapter 1: Overview

1.1 General Description

Pentek’s Model 6210 is a VIM−2 Digital Drop Receiver (DDR) module (devices of this type are also often referred to as Digital Down Converters, or DDCs), designed to be attached directly to any of Pentek’s DSP− or RISC−based VIM motherboards, such as Pentek Models 4290, 4291 and 4292. It forms a complete 2−channel software radio system including tuning, filtering and demodulation.

Two Model 6210s may be attached to any VIM−compatible processor board to form a 4−channel software radio which utilizes all four processors while occupying only one VMEbus slot. Alternately, the Model 6210 may be combined with another VIM−2 module to provide additional I/O functions.

1.2 Input Section

Each channel includes an analog front end which employs a wideband input ampli− fier followed by a programmable gain amplifier. It accommodates wideband analog inputs between 5 kHz and 80 MHz, at full−scale levels of −20 dBm to +10 dBm. Ana− log inputs are accepted through front panel SMA connectors.

An anti−aliasing filter removes out−of−band frequency components and can be tai− lored for specific signal types. The standard factory−supplied lowpass filter has a cutoff frequency of 25 MHz. The programmable−gain amp and filter may be bypassed to support undersampling applications.

Option 030 provides a filter cut−off frequency of 30 MHz. Option 102 provides full scale levels of −30 dBm to 0 dBm. Both option Option 030 and Option 102 may be combined.

Rev.: C

Page 8

Pa ge 8 Pentek Model 6210 Operating Manual

1.3 A/D Converters

Each channel employs an Analog Devices AD6640 12−bit A/D converter capable of sampling rates up to 65 MHz. The A/D sample clock can be derived from an internal 64 MHz crystal oscillator or from an external reference supplied to another front panel SMA connector.

1) Due to packaging constraints the internal oscillator is not user-replaceable. If other clock frequencies are required, contact Pentek for custom oscillators.

Note

Both A/D converters operate synchronously from the same sampling clock to support multi−channel applications (such as direction finding) where phase between channels must be maintained.

(2)The maximum sampling rate can only be achieved using an external

reference signal, unless the internal oscillator is replaced (Option 020 provides a 65 MHz oscillator)

1.4 Digital Drop Receivers

The output of each A/D converter feeds the Intersil HSP50214B, which represents a new generation of complex digital down converters and communication signal pro− cessors.

Included in the HSP50214B are an input numerically−controlled local oscillator (NCO) and mixer to translate input signals down to baseband. The mixer is followed by multistage digital filters, including a comb filter, half−band filters and an FIR filter with programmable coefficients. Together, they support decimation factors from 4 to 16,384, and a maximum output bandwidth of 929 kHz with an 84 dB SFDR at an out− put sampling rate of 12.24 MHz.

A second processing section consists of a resampling polyphase filter which operates asynchronously, with a second clock signal. The output section includes direct I and Q complex outputs, a hardware cartesian−to−polar converter, a frequency discrimi− nator with programmable FIR filter, a timing error signal for symbol tracking, and AGC outputs.

A digital multiplexer allows either the digital receiver output or the A/D output to be sent into the ’C6x BI−FIFO, to support direct, wideband input data capture. A front panel ribbon cable bus allows multiple 6210s to share a common sample clock and synchronize the phase of the digital receivers across modules.

1.5 Connection to VIM Motherboard

Both 16−bit parallel output data ports (ports A and B) from the Model 6210 flow into the FIFO structures on the VIM motherboard. A control path from each motherboard processor permits direct programming of the HSP50214B functions including tuning, decimation, output formatting, filter control and filter coefficients.

Rev.: C

Page 9

Pentek Model 6210 Operating Manual Page 9

1.6 Simplified Block Diagram

Figure 1−1, below, provides a simplified block diagram of the Model 6210.

Front

Panel

SYNC/

SERIAL

Sample Clock

Clock

Generator

Synchronization

Interrupts and

Control

In/Out

64 MHz

Crystal

Oscillator

RF In

Programmable

Gain Amplifier

Low Pass

Filter

Bypass

LPF

AD6640

65 MHz

12−bit A/D

Sync

HSP50214

Digital Down

Converter

Proc

r l

OutBOut

(I)

Ser

Out A

Sync Control Bus

(Q)

DDR

Bypass

MUX

RF In

Programmable

Gain Amplifier

Low Pass

Filter

Bypas s

LPF

AD6640

65 MHz

12−bit A/D

Sync

HSP50214

Digital Down

Converter

Proc

t r l

OutBOut

(I)

Ser

Out A

(Q)

DDR

Bypass

MUX

Model 6210

VIM Motherboard

Figure 1−1: Model 6210 − Simplified Block Diagram

−Rx −Tx

SP1 SP1

SP0

'C6x DSP

A or C

XCVR XCVRBi−FIFO Bi−FIFO

'C6x DSP

B or D

−Rx −Tx

SP0

Rev.: C

Page 10

Page 10 Pentek Model 6210 Operating Manual

1.7 Specifications

The specifications below are typical, at 25°C ambient temperature, with + 5 V supplies within ± 1 % of nominal, unless otherwise specified.

and ± 12 VDC power

Input Channels

Quantity: 2 Input Type: Single−ended, non inverting Input Impedance:

Standard: 50 Ω Option 101: 650 kΩ

Full Scale Voltage: ± 1.0 Volts

Input Amp/Filter

Quantity: 2 (one per A/D Channel) Amplifier #1

Type: Fixed gain Burr Brown OPA642 Bandwidth: 80 MHz Bypass: None

Amplifier #2

Type: Analog Devices AD603* Programmable Gain Amp

controlled by 12−bit D/A (Linear Technology LTC1451 Bandwidth: 25 MHz Bypass: Programmable (includes filter) Gain (full scale):

Standard: 10 dBm to −20 dBm Option 102: 0 dBm to −30 dBm

* − Data Sheet included as Appendix C, courtesy of Analog Devices Inc., Norwood, MA.

†

− Data Sheet included as Appendix D, courtesy of Linear Technology Corp., Milpitas, CA.

†

)

Rev.: C

Anti−Aliasing Filter

Type: Fixed frequency low pass − 5 pole Chebyshev Passband (−3 dB):

Standard: 25 MHz

Option 030: 30 MHz Passband Flatness: ± 1 dB Stopband: 80 MHz Stopband Attenuation: > 60 dB Bypass: Programmable (includes P. G. Amp)

A/D Converter:

Device: Analog Devices AD6640** Quantity: 2 Sampling Rate: 6.5 MHz min, 65 MHz max. Coupling: AC, 5 kHz cut in Clock Source: Selectable − Onboard crystal oscillator or

front panel external clock.

Resolution: 12 bits

** − Data Sheet included as Appendix B, courtesy of Analog Devices Inc., Norwood, MA.

Page 11

Pentek Model 6210 Operating Manual Page 11

1.7 Specifications (continued)

Signal Purity

Front End Performance w/ Programmable Amp

Harmonic Distortion: −60 dB

Signal/Noise Ratio (30 MHz) −50 dB

Spur Free Dynamic Range: −65 dB

Crosstalk: −60 dB @ 1 MHz

Front End Performance w/o Programmable Amp

Harmonic Distortion: −70 dB

Signal/Noise Ratio (30 MHz) −60 dB

Spur Free Dynamic Range: −70 dB

Crosstalk: −60 dB @ 1 MHz

Sample Rate Control

Clock Source:

Internal: Onboard crystal oscillator

Standard: 64 MHz Option 020: 65 MHz Oprion 021: 53.125 MHz

External: Front Panel Low−Voltage Differential Signal (LVDS)

65 MHz max.

Sample Rate Divider: internal or external source can be divided by

1, 2, 4, 8, or 10 .

Digital Receiver

Device: Intersil HSP50214* Quantity: 2 Data Source: Associated A/D (A/D 1 to DDR 1, A/D 2 to DDR 2) Clock Source: Same as associated A/D source. Bypass: Under software control, each DDR can be bypassed

individually to provide A/D output to the BI−FIFO interface.

Sync: Provided through VIM motherboard−driven

control register or via front panel connector.

* − Data Sheet included as Appendix A, courtesy of Intersil Corp., Palm Bay, FL.

Front Panel

Analog Input: 2 SMA Connectors (1 per channel) Sample Clock: Multipin connector (programmable as input or output

− differential LVDS compatible only) and 1 SMA connector (also LVDS only)

Sync: Multipin connector (programmable as input or

output − differential LVDS compatible only) and one TTL input

VIM Motherboard Functions Provides access to VIM Motherboard XDS connec−

tor and status LEDs

VIM Motherboard Reset: Front panel control

Rev.: C

Page 12

Page 12 Pentek Model 6210 Operating Manual

1.7 Specifications (continued)

Power Requirements: +5 V

Min. (idle): 760 mA

Max. (loaded):2000 mA

+12 V

Min. (idle): 750 mA Max. (loaded):750 mA

−12 V

Min. (idle): 500 mA Max. (loaded):500 mA

Dimensions:

VIM−2 Module Height: 114 mm (4.5−in.) Depth: 82 mm (3.25−in.) Width: 20 mm (0.8−in.)

Rev.: C

Page 13

Pentek Model 6210 Operating Manual Page 13

Chapter 2: Installation and Connections

2.1 Inspection

After unpacking the unit, inspect it carefully for possible damage to connectors or components. If any damage is discovered, please contact Pentek immediately at (201) 818−5900. Also, please save the original shipping container and packing material in case reshipment is required.

2.2 Jumper Blocks

The Model 6210 PC board contains several jumper blocks. Figure 2−1, on the next page, shows all jumper block locations. Please be aware that all of the jumpers are config− ured at the factory for proper operation and, with the exception of JB2 (see Section 2.2.1 and Table 2−2, at the bottom of this page) should not be moved. Table 2−1, below, pro− vides the factory jumper settings for reference, or in case you suspect that they have been tampered with.

Table 2−1: Model 6210 − Factory Jumper Settings

Jumper Block Factory Setting

JB1 Pins 1−2

JB2 Pins 2−3

JB3 Jumper ON (pins 1−2)

JB4 Pins 2−3

2.2.1 External Clock Function Select Jumper − JB2

Install a jumper between pins 2 and 3 of JB2 to use a signal applied to the front panel EXT CLK input connector as the source of the sample clock signal for the A/D converter. To use the EXT CLK input as the reference clock signal for the DDR, place a jumper between pins 1 & 2 of JB2. For a description of the signals that can be applied to the EXT CLK input connector, please refer to Section 2.3.1.

Table 2−2: Model 6210 − External Clock

Jumper

Position

1 − 2 DDR Reference Clock

2 − 3* A/D Sample Clock*

* − Factory Default Setting

External Clock Function

Rev.: C

Page 14

Page 14 Pentek Model 6210 Operating Manual

JB2





Baseboard M ounting Holes

(a) Component Side

Baseboard Mounting Holes





Rev.: C

JB4 JB3 JB1

(b) Solder Side

Figure 2−1: Model 6210 PC Board, Showing Jumper Blocks & Mounting Holes

Page 15

Pentek Model 6210 Operating Manual Page 15

2.3 Model 6210 Front Panel Features

The Model 6210’s front panel is shown in Figure 2−2, at the ri ght. This panel occupies one of the VIM module positions available on a VIM motherboard’s front panel. If the Model 6210 is the only mezzanine board installed, the other half of the mother− board’s panel may be filled with a blank, supplied with the motherboard. Available on the Model 6210’s front panel are three SMA connectors, one for each channel’s analog input sig− nal and a third for an external clock signal. Two indicator LEDs associated with the 6210’s Sync Bus interface are visible between the two analog input connectors, and four LED’s associated with each motherboard processor that can access the module can be seen through cutouts on the left side of the panel. The panel’s most prominent feature is the 36−pin Sync Bus − Serial I/O con− nector, which will be covered in Section 2.4. The other panel features discussed will all be discussed in the subsections that begin below.

2.3.1 External Clock Input − EXT CLK

The threaded, coaxial SMA connector nearest the top of the Model 6210’s front panel is provided for the application of an external clock signal. This signal can be used either as the sample clock signal for the 6210’s A/D converters, or as the reference clock signal for its DDR.

Model 6210

EXT

CLK

N C

S E R

CH1

R M

CH2

Figure 2−2:

Model 6210 −

Front Panel

The External Clock Input circuit used on Pentek's Model 6210 is designed to accept Low−Voltage Differential Signals (LVDS). The impedance presented by the external clock input is 50 Ω. The applied signal is AC coupled via 0.1µF to the + input of an LVDS line receiver. This input is diode−protected to ground and +3.3 V, and biased at +1.65 V (the − input of the receiver is also biased at +1.65 V). LVDS devices can typically react to differential input sig− nal swings as low as 250 mV, or, when used in a single−ended manner (as in this case), to signal levels as low as 100 mV above, or 20 mV below, the bias voltage. For most applications, Pentek recommends that the signal applied to this connector be a square or sine wave, with 2 V p−p amplitude, at frequen− cies up to 65 MHz. Figure 2−3, at the top of the next page, shows the equiva− lent circuit for the Model 6210’s EXT CLK input.

2.3.1.1 Duty Cycle Sensitivity

The A/D converter used on the Model 6210 is the AD6640, from Analog Devices. The graphs presented in the AD6640 Data Sheet (see

Appendix B) indicate that the ADC is relatively insensitive to duty

cycle variations between 40% and 65%. Figure 17 in the AD6640 Data

Sheet shows the SNR and Spurious performance at varying duty

cycles for a 2.2 MHz analog input signal sampled at 65 MHz. Under these conditions, the performance seems quite good.

Rev.: C

Page 16

Page 16 Pentek Model 6210 Operating Manual

Ω

2.3 Model 6210 Front Panel Features (continued)

2.3.1 External Clock Input (continued)

+ 3.3 V

10 k

Ω

1 k

Ω

EXT CLK

0.1 F

Ω

1 k

Ω

0.1 F

10 k

Figure 2−3: Model 6210 − External Clock Input Circuit

2.3.1.1 Duty Cycle Sensitivity (continued)

Our experience with this device under different conditions, how− ever, has not been quite so favorable. We have found that if the device is operated at sample rates of 60 MHz or more, with an input signal that is offset slightly from the sample rate (e. g., sam− pling a 60.05 MHz signal at a 60 MHz sample rate), significant conversion errors can occur at the ADC’s output if the duty cycle varies even marginally from 50%.

Referring to the AD6640’s switching specifications for the ENCODE input (this is where the sample clock signal is delivered), we see that the minimum high and low pulse widths at that input are both 6.5 nsec. Bearing that in mind, consider that a perfect square wave at 65 MHz has a half−cycle time slightly less than

7.7 nsec. Now bring that perfect square wave into the real world, where such things as rise and fall time exist, and you can see how it might become difficult NOT to violate the 6.5 nsec pulse width specification at the maximum sample rate.

DS90LV032A

–

Clock

Select MUX

There is a significant amount of signal conditioning and selection circuitry between the 6210’s EXT CLK input and the AD6640’s ENCODE input. This tends to cause a small amount of difference between the duty cycle of the signal you deliver to the front panel connector and the duty cycle of the signal we deliver to the ADC. So, even if you know that your EXT CLK input signal has a duty cycle of 50% +

Rev.: C

0.00001%, that’s probably not what the ADC sees.

Page 17

Pentek Model 6210 Operating Manual Page 17

2.3 Model 6210 Front Panel Features (continued)

2.3.1 External Clock Input (continued)

2.3.1.1 Duty Cycle Sensitivity (continued)

Now that we’ve given you what seems to be some bad news, we’ll follow with the good news. We have ONLY seen the AD6640’s duty cycle sensitivity become a problem in the very specific situa− tion where the sample rate is relatively high (> 60 MHz), AND the analog input signal’s frequency is very close to the absolute sample rate or a multiple thereof. In such cases, the apparent output signal from the A/D is an alias of the difference frequency, and contains a relatively high number of samples per cycle. The problem is easily visible in real−time plots of the A/D output, as glitches in the out− put signal. Should your application require that you operate your 6210 in this manner, we make the following recommendations:

1) DO NOT use the internal oscillator as your clock source, as there is no way to control the internal clock’s duty cycle. Instead, apply and select an external clock signal with a variable duty cycle.

2) Before attempting any serious data acquisition, monitor and plot the A/D output in real time, and adjust the duty cycle of the clock input until the glitches disappear.

2.3.2 Analog Inputs − CH1 IN, CH2 IN

The two threaded, coaxial SMA connectors nearest the bottom of the Model 6210’s front panel are the Analog Input Connectors. The analog inputs are terminated in 50 9, and directly coupled to the non−inverting inputs of OPA642 Operational Amplifiers. The maximum input signal swing for linear operation is ± 1 V (i.e., 2 V because the Model 6210’s maximum sample rate is 65 MHz (64 MHz if the internal crystal oscillator is used as the sample clock), the bandwidth of sig− nals applied to these inputs should be limited to 32.5 MHz (32 MHz if the internal crystal oscillator is used as the sample clock), or to one half of the programmed sample rate, unless your application requires undersampling.

). The amplifier’s bandwidth is 80 MHz, but

P−P

2.3.3 Indicator LEDs

A total of ten LED’s are visible through the front panel of the Model 6210. Two of these are associated with the 6210’s Sync Bus interface. These are located between the Analog Input Connectors, slightly to the right of the cen− ter of the panel. The other eight are general purpose indicators controlled by the processors on the VIM motherboard, and are visible through the cutouts at the left side of the 6210’s front panel. These will all be discussed in the sub− sections that begin at the top of the next page.

Rev.: C

Page 18

Page 18 Pentek Model 6210 Operating Manual

2.3 Model 6210 Front Panel Features (continued)

2.3.3 Indicator LEDs (continued)

2.3.3.1 Sync Bus Master LED − MAS

The red MAS LED, the leftmost one near the panel’s center, indi− cates that the Sync Bus master function has been enabled for the 6210 in question. This means that the 6210 on whose panel this LED is lit will be the one that provides the Sync signals to all other VIM modules connected to the Sync Bus. Any Sync Bus MUST have one and only one master, and it should physically be located at the opposite end of the Sync Cable from the Sync Terminator (see Section 2.3.3.2, below). This LED will be illuminated when− ever the D0 bit in the 6210’s Control Register (see Section 3.4) is set to the logic ‘1’ state. It will be turned off when that bit is cleared to the logic ‘0’ state.

2.3.3.2 Sync Bus Terminator LED − TRM

The red TRM LED, the rightmost one near the panel’s center, indi− cates that the Sync Bus Master termination has been enabled for the 6210 in question. This means that the 6210 on whose panel this LED is lit will be the one that provides the terminating resistors for the Sync signals generated by the Sync Bus master. Any Sync Bus MUST have one and only one terminator, and it should physically be located at the opposite end of the Sync Cable from the Sync master (see Section 2.3.3.1, above). This LED will be illuminated whenever the D1 bit in the 6210’s Control Register (see Section 3.4) is set to the logic ‘1’ state. It will be turned off when that bit is cleared to the logic ‘0’ state.

2.3.3.3 Motherboard LEDs − 0, 1, 2 & 3

Visible through cutouts at the left side of the Model 6210’s front panel are two groups of four LEDs controlled by the processors on the VIM motherboard. Each group of four LEDs contains one red LED (labeled 0) and 3 green LEDs (labeled 1, 2 & 3), and they are under the control of one of the motherboard’s processors. Depending upon the position in which the VIM module is installed on the motherboard, the four LEDs nearest the top of the panel are controlled by either Processor A or Processor C, and the four at the bottom are controlled by either Processor B or Processor D. For further details about these indicators, please refer to your VIM motherboard’s Operating Manual.

Rev.: C

Page 19

Pentek Model 6210 Operating Manual Page 19

222426283032343

2.4 Sync Bus − Serial I/O Connector

Accessible through each Model 6210’s front panel is a 36− pin serial connector (3M part #81036−500203, Pentek part # 354.03610), several pins of which are connected to (and driven by) the VIM motherboard’s serial ports. The mating connector is 3M part # 83036−6006 or an equivalent, Pentek part # 353.03605. Also included on this connector are signals used for synchronizing multiple units. Table 2−3, at the bottom of this page, contains the pinouts and description of this con− nector, whose pin numbering scheme is shown in Figure 2−4, at the right.

2.4.1 Signals for Synchronizing Multiple Boards

The following LVDS (Low−Voltage Differential Sig− naling) signals make up the sync bus; MCLK, PRCLK, MSYNC, SYNC1, and SYNC2. The sub−sections that begin on the page after next describe each of these sig− nals. Figure 2−5, on the next page, shows a block dia− gram of the Sync and Clock signal sources.

1 3 5 7

9 11

13 15 17 19 21 23 25 27 29 31 33 35

2 4 6

8 10 12

14 16 18

Figure 2−4:

Model 6210 −

Front Panel

Sync Bus −

Serial I/O

Connector

Pin Numbering

Table 2−3: Model 6210 − Sync Bus − Serial I/O Pinouts

Pin Signal Pin Signal

1Ground2 MCLK 3MCLK 5 MSYNC 6 MSYNC 7 SYNC1 8 SYNC1

9 SYNC2 10 SYNC2 11 Ground 12 PRCLK 13 PRCLK 15 TTL−SYNC 17 P0−CLKR1 18 Ground 19 P0−FSR1 20 P0−DR1 21 P0−CLKS1 22 Ground 23 P0−CLKX1 24 Ground 25 P0−FSX1 26 P0−DX1 27 P1−CLKR1 28 Ground 29 P1−FSR1 30 P1−DR1 31 P1−CLKS1 32 Ground 33 P1−CLKX1 34 Ground 35 P1−FSX1 36 P1−DX1

4Ground

14 Ground 16 Ground

Up to eight (8) 6210’s can be operated synchronously by cabling these connec− tors together. Further details about how this is accomplished are provided in the subsections beginning on the page after next, and in Sections 3.4 and 3.9. If your application requires more than 8 units synchronized units, Pentek’s Model 9190 can be used to synchronize up to eighty (80) 6210s.

Rev.: C

Page 20

Pa ge 20 Pentek Model 6210 Operating Manual

2.4 Sync Bus − Serial I/O Connector (continued)

2.4.1 Signals for Synchronizing Multiple Boards (continued)

AD6640

CLK IN

A/D 1

MCLK

MSYNC

SYNC1 SYNC2 PRCLK

LVDS

Receiver

LVDS

Driver

Master / Slave

(Cont rol Reg., D0)

Divide

by N

Master Clock

Divider Regist er

(DIV0)

CLK IN MSYNC In SYNC1 SYNC2

DDR 2

HSP 50214B

AD6640

CLK IN

A/D 2

CLK IN MSYNC In SYNC1 SYNC2

DDR 1

HSP 50214B

PRCLK

MSYNC Out

SYNC Out

PRCLK

MSYNC Out

SYNC Out

Note

Rev.: C

Divide

by 2

EXT CLK

Input

Clock Select

(Cont rol Reg., D2)

PRCLK Freq.

(Cont rol Reg., D4)

64 MHz

Oscillator

Figure 2−5: Model 6210 − Block Diagram of Clock and Sync Signal Sources

DDR 1 is controlled by VIM Motherboard Processor A or C, and DDR2 is controlled by Processor B or D, depending where the VIM module is installed on the motherboard.

Page 21

Pentek Model 6210 Operating Manual Page 21

2.4 Sync Bus − Serial I/O Connector (continued)

2.4.1 Signals for Synchronizing Multiple Boards (continued)

2.4.1.1 MCLK, MCLK

This signal is used as both the sample clock for the A/D con− verters, and the front−end processing clock for the DDRs. When the Model 6210 is configured as a master, this is an LVDS output at the A/D sample clock rate. If the board is configured for an external clock, then the original source for this signal is the EXT CLK SMA input connector. Otherwise, the on−board crystal oscillator is used as the frequency source. The frequency of MCLK is equal to the external or crystal fre− quency divided by the contents of the Master Clock Divider register (see Section 3.5).

When configured as a slave, this signal is a differential LDVS input and will be used as the A/D sample clock and the front− end processing clock for the DDRs, instead of the board’s own external clock input or on−board oscillator. This is how several boards are able to sample synchronously from the same reference clock source.

2.4.1.2 PRCLK, PRCLK

This signal is the clock used by the back−end processing of the HSP50214B DDR chips, referred to as PROCCLK in the DDR’s

Data Sheet in Appendix A of this manual. When the Model 6210 is

configured as a Sync master, this is a differential LVDS output.

Table 2−4, at the top of the next page, contains a list of possible

PRCLK sources and their frequency limits, when the Model 6210 is configured as a Sync master. PRCLK MUST BE LESS THAN 55 MHz, regardless of the clock source.

When configured as slave, this is a differential LVDS input used by the HSP50214B DDR in place of the on−board generated PRCLK. In this way, the DDRs of several boards may all be synchronized to the same PRCLK source.

When bypassing the HSP50214B chips, and using the 6210 as an A/ D converter only, these signals are ignored.

Rev.: C

Page 22

Page 22 Pentek Model 6210 Operating Manual

2.4 Sync Bus − Serial I/O Connector (continued)

2.4.1 Signals for Synchronizing Multiple Boards (continued)

2.4.1.2 PRCLK, PRCLK (continued)

Table 2−4: Model 6210 − Master PRCLK Signal Source & Frequency

Mode

A/D Clock

Frequency

Clock

Source*

PRCLK_Divider Setting

(Control Reg., D4)

Description

Master

(Control Reg., D0 = 1)

* − The clock source is selected by the Ext_Clk Enable bit (D2, Control Register).

†

− This selection is only valid if the standard, 64 MHz internal oscillator is replaced by one whose

< 55 MHz

> 55 MHz

frequency is 55 MHz or less (e.g., Option 021).

EXT. CLK 1 PRCLK = Ext. CLK

INT. OSC

EXT. CLK 0 PRCLK = EXT CLK/2

INT. OSC 0 PRCLK = INT. OSC/2

†

2.4.1.3 MSYNC, MSYNC

This signal is the reset pulse used by the HSP50214B DDRs to synchronize their front− and back−end processing. If the board is configured as a master, then this is a differential LVDS out− put. If the board is configured as slave, this signal is a differen− tial LVDS input. MSYNC’s quiescent state is low, and synchronization occurs on the rising edge of this signal (or the falling edge of the normally−high MSYNC

2.4.1.4 SYNC1, SYNC1

†

PRCLK = INT. OSC.

†

Rev.: C

This signal is the reset pulse for HSP50214B DDR front−end pro− cessing. It resets all DDR processing associated with MCLK, including the VIM motherboard’s input Bi−FIFOs and the Bi−FIFO write rate dividers across multiple channels and/or boards. SYNC1’s quiescent state is low, and synchronization occurs on the rising edge of this signal (or the falling edge of the nor− mally−high SYNC1

If the Model 6210 is configured as a Sync bus master, this is a dif− ferential LVDS output. SYNC OUT of Channel 2’s HSP50214B DDR is used as the source for the differential LVDS output. For proper operation, the Syncout CLK Select bit (D3) of DDR2’s Con− trol Word 0 should be cleared to the logic ‘0’ state. This configures DDR2 such that its SYNC OUT signal is derived from CLKIN (i.e., the Sync bus MCLK signal − see Figure 2−5, and the Control Word 0 description in the HSP50214 Data Sheet, Appendix A o f this manual). If the Model 6210 is configured as a Sync bus slave, this is a differ− ential LVDS input.

Page 23

Pentek Model 6210 Operating Manual Page 23

2.4 Sync Bus − Serial I/O Connector (continued)

2.4.1 Signals for Synchronizing Multiple Boards (continued)

2.4.1.5 SYNC2, SYNC2

This signal is the same as SYNC1 except its source is Channel 1’s DDR SYNC OUT and is used to synchronize all back−end DDR processing associated with PRCLK. Channel 1’s DDR control reg− ister should be configured for SYNC OUT to be derived from PRCLK for proper operation. SYNC2’s quiescent state is low, and synchronization occurs on the rising edge of this signal (or the falling edge of the normally−high SYNC2

2.4.1.6 Compatibility with Other Products’ Sync Buses

At the time of this manual’s publication, Pentek manufactures four devices that use the same physical connector to implement a Sync bus and Serial I/O port. These are the Models 6210 and 6216 Dig− ital Reciver/ADCs, the Model 6211 A/D Converter, and the Model 6229 Digital Transmitter/DAC. The serial port implementations are identical across these four products. However, if you simply take a length of 36−wire ribbon cable and crimp a 36−pin insula− tion−displacement connector at either end, you’ll be connecting the serial port transmitters to other transmitters, and the receivers to other reveivers. Such configurations are clearly to be avoided, so any required serial port interconnections will have to be made via some sort of breakout box or board, reminiscent of the RS−232 implementations that we all remember from the good(?) old days.

Cables that are intended to connect only the Sync busses of these devices can b e constructed using two or more 36−pin IDC con− nectors (3M part # 83036−6006 or an equivalent, Pentek part #

353.03605), and a 16−wire ribbon cable connecting pins 1 − 16 on all connectors. One should be aware, however, that there are some differences in the Sync bus implementations across these devices. The paragraphs that follow will comment on the interoperability of the Sync busses among these four products.

The Models 6211 is essentially identical the Model 6210, except that it lacks a Digital Receiver stage. The 6211 can generate and receive the differentially−paired MCLK and SYNC1 signals. It can neither generate nor receive the differentially−paired MSYNC, SYNC2 and PRCLK signals, but the pins used for these signals are left unconnected on the Model 6211, so it will not interfere with the propagation of these signals. The Model 6210 can generate and receive all five of these differential pairs. Thus, if a synchronized system using both 6210s and 6211s were to be assembled, one of the 6210s should be the SYNC bus master.

Rev.: C

Page 24

Page 24 Pentek Model 6210 Operating Manual

2.4 Sync Bus − Serial I/O Connector (continued)

2.4.1 Signals for Synchronizing Multiple Boards (continued)

2.4.1.6 Compatibility with Other Products’ Sync Buses (continued)

The Model 6216 is a Wideband Digital Receiver and A/D con− verter. Its ADC stage is also identical to the Model 6210’s , but it uses Graychip’s GC1012 Down−Converter instead of the Intersil HSP50214 used in this product. There are several differences between the synchronizing features of these two devices, most notably that synchronization occurs on the rising edge of the sync signals on the 6210, and on the falling edge of these signals on the

6216. Thus, 6210s and 6216s CANNOT be synchronized with one another. Finally, the Model 6229’s Sync bus is compatible with the 6216’s , and therefore not compatible with the 6210’s.

2.4.2 Serial Port Signals

The signals listed in the subsections below are associated with the VIM moth− erboard’s Serial Ports. If the Model 6210 is installed above (i. e., controlled by) Processors A & B on the VIM motherboard, then Processor A’s serial port 1 is P0, and Processor B’s serial port 1 is P1. If the Model 6210 is installed above VIM motherboard Processors C & D, then Processor C’s serial port 1 is P0, and Processor D’s serial port 1 is P1. All these signals are delivered directly from the 6210’s VIM Motherboard connector to the front panel Sync Bus − Serial I/O Connector via a small series resistor (47 9), and are pulled up to +5 V via 8.2 k9 on the I/O connector side of the series resistor.

2.4.2.1 P0−CLKR1, P1−CLKR1

These are the Serial Port Receive Clock Signals from the VIM motherboard.

2.4.2.2 P0−FSR1, P1−FSR1

These are the Serial Port Receive Frame Sync signals from the VIM motherboard.

2.4.2.3 P0−CLKS1, P1−CLKS1

These are the Serial Port External Clock Source signals from the VIM motherboard.

Rev.: C

2.4.2.4 P0−DR1, P1−DR1

These are the Serial Port Receive Data signals from the VIM motherboard.

Page 25

Pentek Model 6210 Operating Manual Page 25

2.4 Sync Bus − Serial I/O Connector (continued)

2.4.2 Serial Port Signals (continued)

2.4.2.5 P0−CLKX1, P1−CLKX1

These are the Serial Port Transmit Clock signals from the VIM motherboard.

2.4.2.6 P0−FSX1, P1−FSX1

These are the Serial Port Transmit Frame Sync signals from the VIM motherboard.

2.4.2.7 P0−DX1, P1−DX1

These are the Serial Port Transmit Data signals from the VIM motherboard.

2.4.3 TTL−SYNC

This signal is a single−ended, TTL compatible sync input. SYNC1 and SYNC2 pulses will be created in slave units on the rising edge of this signal. The sig− nal applied to this input must be a logic high in its quiescent state, and the negative−going sync pulse applied here must be at least two sample clock periods wide. If left unconnected, this pin is pulled to a high logic level.

Rev.: C

Page 26

Page 26 Pentek Model 6210 Operating Manual

2.5 Installing the Model 6210 on a VIM Motherboard

Pentek’s VIM motherboard ship with two blank panels where optional VIM modules, such as the Model 6210, can be installed. This section provides directions for removing blank panels, and installing the Model 6210, or other VIM modules.

P e r f o r m a l l a s s e m b l y s t e p s a t a n

a n t i s t a t i c w o r k s t a t i o n !

WARNING

Tools required for all procedures:

1) #1 Phillips screwdriver

2) flat−blade screwdriver (blade width 5/16−in. or less)

2.5.1 Preparing the VIM Module for Installation

1) Remove the blank insert from the position in which your VIM module will be installed by removing the two countersunk Phillips screws from the top & bottom of the insert.

2) Remove the front panel from the VIM module by removing the two countersunk Phillips screws from the top & bottom of the panel.

Rev.: C

Remove

Figure 2−6: VIM Module Countersunk Screws

Page 27

Pentek Model 6210 Operating Manual Page 27

2.5 Installing the Model 6210 on a VIM Motherboard (continued)

2.5.1 Preparing the VIM Module for Installation (continued)

3) Remove the two shipping brackets that were used to mount the front

panel to the VIM module, by removing the two pan−head Phillips screws from the solder side of the VIM module. These brackets may be discarded or saved to use to store the panel on the VIM module if and when it is removed from the VIM motherboard.

4) At the rear of the VIM module, on the component side, is a nylon spacer

with a nylon screw threaded into it.

Figure 2−7: VIM Module Nylon Spacer

a) Remove the nylon screw threaded into the spacer from the component

side. Set this screw aside, as it will be used when installing the VIM module on the motherboard.

b) The spacer should be installed in the hole BEHIND the VIM connectors

(i.e., farthest from the front panel’s location). If the spacer is installed in the front hole, reposition it by removing the nylon screw on the SOLDER side of the VIM module, and threading it back into the spacer through the rear−most hole.

Rev.: C

Page 28

Page 28 Pentek Model 6210 Operating Manual

2.5 Installing the Model 6210 on a VIM Motherboard (continued)

2.5.2 Installing the VIM Module on the VIM Motherboard

1) With the VIM motherboard’s component side (the one with the mezzanine connectors) up, and the connectors on the VIM module face down, align the P1 and P2 connectors on the VIM module with the pair of connectors corresponding to the desired location on the motherboard (e.g., P11 and P14 at the top of the 4290, or P8 and P4, at the bottom).

2) GENTLY but firmly, press down on the areas of the VIM module opposite both connectors, to fully seat the VIM module’s connectors in the motherboard’s. If you meet with significant resistance, check the connector alignment. Misalignment can cause bent pins or break connector housings, so NEVER APPLY EXCESSIVE FORCE.

3) After seating the connectors, secure the front of the VIM module to the motherboard by threading two pan−head Phillips screws through the holes in the front of the solder side of the VIM module into the threaded holes in motherboard’s panel brackets.

4) Turn the assembly over, such that the mezzanine board is on the work surface and the solder side of the VIM motherboard is face up.

5) Secure the rear of the VIM module to the motherboard using the nylon screw you removed earlier through the rear mounting hole on the motherboard, threaded into the nylon spacer on the VIM module.

6) Attach the VIM module’s front panel to the motherboard using two countersunk Phillips screws, passed through the holes at the top and bottom of the VIM panel and threading them into the threaded holes in the motherboard’s panel brackets.

7) If an additional VIM module is to be installed, repeat this procedure in the other module location on the motherboard.

Rev.: C

Page 29

Pentek Model 6210 Operating Manual Page 29

Ejector Handle Screw

Slotted Screw

(a)

P11

'C6x A

(f)

Top Position

Mounting Holes

To p Po si t io n

VIM Connectors

(b)

(c)

(d)

'C6x B

'C6x C

Bottom Position

Mounting Holes

'C6x D

P11

(e)

Bottom Position

VIM Connectors

Ejector Handle Screw

Slotted Screw

Figure 2−8: Model 4290 VIM Motherboard − Connectors & Mounting Holes

Rev.: C

Page 30

Page 30 Pentek Model 6210 Operating Manual

This page is intentionally blank

Rev.: C

Page 31

Pentek Model 6210 Operating Manual Page 31

Chapter 3: Memory Map and Register Descriptions

3.1 Overview

This section covers access to the Model 6210 from the VIM motherboard. Memory maps to VIM module resources are given from the motherboard processor’s viewpoint, and details are provided describing the use of each resource.

3.2 Model 6210 Memory Map

Table 3−1, below, provides a complete memory map for the Model 6210 mezzanine

board. The subsections that follow the table provide detailed information about each register.

Table 3−1: Model 6210 Memory Map

‘C6X Address Register Description Mnemonic Access Additional Info

0x0032 0000 ID EEPROM Readout EEPROM R. O. Appendix E

0x0032 0004 −

0x0032 001C 0x0032 0020* Control Register* CONTROL R/W Section 3.4 0x0032 0024* Master Clock Divider* MCLKDIV R/W Section 3.5

0x0032 0028 BIFO Decimation Register BIFODIV R/W Section 3.6

0x0032 002C Programmable Gain Amplifier GAIN R/W Section 3.7

0x0032 0030 Data Format / Signal Path Register DATA_CONTROL R/W Section 3.8

0x0032 0034* SYNC Generate Register* SYNC W.O. Section 3.9

0x0032 0038 Serial Port 0 Connection Register SPORT_CONTROL R/W Section 3.10

0x0032 003C CIC Gain Adjust Register CIC_GAIN_ADJ R/W Section 3.11

0x0032 0040 DDR Holding Register 0 DDR0 R/W 0x0032 0044 DDR Holding Register 1 DDR1 R/W 0x0032 0048 DDR Holding Register 2 DDR2 R/W

0x0032 004C DDR Holding Register 3 DDR3 R/W

0x0032 0050 DDR Write Destination Address Register DDR4 R/W 0x0032 0054 DDR Read Source Register DDR5 R/W 0x0032 0058 Reserved — N/A N/A

0x0032 005C DDR Status Read Register DDR6 R/W Section 3.12

* − These registers are accessible only to Processor A or Processor C on the VIM motherboard,

depending upon the position in which the VIM module is installed.

Reserved — N/A N/A

Section 3.12

Rev.: C

Page 32

Page 32 Pentek Model 6210 Operating Manual

3.3 ID EEPROM Readout Register − R. O. @ ‘C6x Address 0x0032 0000

The format for the code stored by Pentek in this EEPROM is listed in Appendix E of this manual. The format is provided for VIM module designers. Neither the format nor this register is intended for general use.

3.4 Control Register − R/W @ ‘C6x Address 0x0032 0020

The Control Register allows you to configure the Model 6210 as a master or slave on the sync bus and to toggle the on−board sync bus termination. It also provides a bit that selects the source of the clock as internal or external, a bit to divide the frequency of the signal that will be used as the PROCCLK for the DDR by 2 (this is necessary if that sig− nal’s frequency exceeds 55 MHz), and a bit to synchronize the operation of the BIFO on the motherboard. All bits in the Control Register default to the logic ‘0’ state. The Control Register is accessible only to Processor A or Processor C on the VIM mother− board, depending upon the position in which the module is installed. Neither Proces− sor B nor Processor D on a VIM motherboard can ever access this register. Table 3−2, below, shows the contents of the Model 6210’s Control Register. The subsections that begin below the table give detailed descriptions of the bits in this register.

Table 3−2: Model 6210 − Control Register − R/W @ ‘C6x Address 0x0032 0020

Bit # D 3 1 − D 8

BitName R e s e r v e d

Function W r i t e w i t h 0 ’ s , M a s k w h e n R e a d i n g

Bit # D7 D6 D5 D4 D3 D2 D1 D0

Bit

Name

Bit

Function

R e s e r v e d

W r i t e w i t h 0 ’ s

M a s k w h e n R e a d i n g

All bits default to the logic ‘0’ state at power−up and resets.

PRCLK_

Divider

1 = ÷ 1 0 = ÷ 2

BIFO_

Disable

1 = Disable

0 = Enable

Ext_Clk

_Enable

1 = Ext Clk 0 = Crystal

Term_

Enable

1 = Term

0 = No Term

3.4.1 PROCCLK Frequency Divider − Bit D4

This bit is allows the user to ensure that the frequency of the signal that drives the PROCCLK input of the HSP50214 never exceeds 55 MHz. This signal is called PRCLK on the 6210’s Sync bus. If, for example, the 64 MHz on−card crystal oscillator is the original source of the PRCLK signal, the divider can be enabled by clearing this bit to the logic ‘0’ state (which is the default). If an external clock signal, or the Sync bus’s PRCLK, is the source for PROCCLK, and the frequency of that signal is below 55 MHz, the divider can be disabled by setting this bit to the logic ‘1’ state. Table 3−3, at the top of the next page, shows how this bit should be set dependent upon clock source selection and frequency.

Master/

Slave

1 = Master

0 = Slave

Rev.: C

Page 33

Pentek Model 6210 Operating Manual Page 33

3.4 Control Register (continued)

3.4.1 PROCCLK Frequency Divider (continued)

Table 3−3: Model 6210 − Master PROCCCLK Signal Source & Frequency

Mode

Master

(Control Reg., D0 = 1)

* − The clock source is selected by the Ext_Clk Enable bit (D2, Control Register).

†

− This selection is only valid if the standard, 64 MHz internal oscillator is replaced by one whose

A/D Clock

Frequency

< 55 MHz

> 55 MHz

frequency is 55 MHz or less (e.g., Option. 021).

Clock

Source*

EXT. CLK 1 PRCLK = Ext. CLK

INT. OSC

EXT. CLK 0 PRCLK = EXT CLK/2

INT. OSC 0 PRCLK = INT. OSC/2

PROCCLK_Divider

Setting

†

Description

†

PRCLK = INT. OSC.

†

3.4.2 BIFO Disable − Bit D3

This bit is used to synchronize the mezzanine BIFOs on VIM motherboards across multiple channels. This is accomplished by first setting this bit on each channel to be synchronized to the logic ‘1’ state, then resetting the motherboard’s BIFO. When this bit is subsequently cleared to the logic ‘0’ state (its default condition), no data is written to the BIFO until the next rising edge of the SYNC1 signal (see Section 2.4.1.4, on page 22). In this manner, data acquisition in all channels connected to the Sync Bus is started simultaneously. This bit MUST be cleared to the logic ‘0’ state for normal operation.

3.4.3 External Clock Enable − Bit D2

This bit determines which signal will drive the Model 6210’s Master Clock Divider (see Section 3.5). When this bit is set to the logic ‘1’ state, the sig− nal applied to the front panel EXT CLK connector is selected. When this bit is cleared to the logic ‘0’ state (its default condition), the on−board, 64 MHz crystal oscillator is selected.

3.4.4 Termination Enable − Bit D1

This bit is set to the logic ‘1’ state to connect termination resistors to the Model 6210’s Sync bus. This should be done ONLY on the slave Model 6210 that is at the opposite end of the Sync Bus from the Sync Bus master, or on a stand−alone device that is not connected to the external Sync Bus. On all other devices, clear this bit to the logic ‘0’ state (the default), to disconnect the terminators.

Rev.: C

Page 34

Page 34 Pentek Model 6210 Operating Manual

3.4 Control Register (continued)

3.4.5 Master / Slave − Bit D0

Set this bit to the logic ‘1’ state to configure a Model 6210 as a Sync bus mas− ter. This bit must also be set to the logic ‘1’ state on any Model 6210 that will not be connected to a Sync Bus. To configure a Model 6210 as a Sync Bus slave, clear this bit to the logic ‘0’ state (its default condition).

3.5 Master Clock Divider − R/W @ ‘C6x Address 0x0032 0024

The Master Clock Divider register divides the master clock signal (provided by the on− card, 64 MHz oscillator or the front panel EXT CLK connector, see Section 3.4.3) by the quantity written to the lower byte (D7 − D0) of this register, plus one. This register should ONLY be written with all zeros (the register’s default condition) or odd numbers, such that the actual number that the master clock frequency is divided by is either 1 or an even number. The output of this divider is applied to the ENCODE inputs of the AD6640 A/D converter, and to the front end of the HSP50214 DDR. For example, when the low byte of this register contains all zeros (their default condition), the master clock signal will be passed to the A/D’s ENCODE inputs and the DDR front end unaltered (i.e., divided by 1). However, if the internal oscillator is selected, and the low byte of this register contains the quantity 7, the A/D’s ENCODE frequency (and the DDR’s front− end processing frequency) will be 8MHz (64 MHz

÷ (7+1)).

Like the Control Register, the Master Clock Divider is only accessible from Processor A or Processor C on the VIM motherboard, depending upon the position in which the module is installed. Neither Processor B nor Processor D on a VIM motherboard can ever access this register. Table 3−4, below, illustrates the contents of the Model 6210’s Master Clock Divider Register.

Table 3−4: Model 6210 − Master Clock Divider − R/W @ ‘C6x Address 0x0032 0024

Bit # D 3 1 − D 8

Name N o t U s e d

Function W r i t e w i t h 0 ’ s , M a s k w h e n R e a d i n g

Bit # D7 D6 D5 D4 D3 D2 D1 D0

Name M S B − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − −L S B

Function

Main Clock is divided by the quantity in this field +1 to produce the Master clock for the ADC &

DDR front end. This field MUST be written with either an odd number, or zero.

All bits default to the logic ‘0’ state at power−up and resets.

Rev.: C

Page 35

Pentek Model 6210 Operating Manual Page 35

3.6 BIFO Decimation Register − R/W @ ‘C6x address 0x0032 0028

The Master Clock, described in Section 3.5, on the previous page, may be further divided to create the Write Enable signal for the VIM motherboard’s mezzanine BIFO. 8 bits are provided for this frequency division, in this register. Each channel (i.e., each processor on the motherboard that can access this module) has its own unique version of this regis− ter, to allow the two channels to operate at different rates. This divider works in a man− ner similar to the Master Clock Divider. The BIFO Write Rate is equal to the Master Clock rate divided by the 8−bit value in this register plus one. Also, the valid data values for this 8−bit field are restricted to odd numbers (which will result in even divisors) and zero (which gives a divisor of one, and is the register’s default condition). Table 3−5, below, shows the contents of this register.

Table 3−5: Model 6210 − Motherboard BIFO Decimation Register −

R/W @ ‘C6x Address 0x0032 0028

Bit # D 3 1 − D 8

Name N o t U s e d

Function W r i t e w i t h 0 ’ s , M a s k w h e n R e a d i n g

Bit # D7 D6 D5 D4 D3 D2 D1 D0

Name MSB− − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − −LSB

Function B I F O W r i t e R a t e d i v i s o r

All bits default to the logic ‘0’ state at power−up and resets.

The Reference Clock is divided by the quantity in this register +1

to produce the Write Enable for the Motherboard’s BIFO.

This 8−bit field MUST be written with either an odd number, or zero.

All bits default to the logic ‘0’ state at power−up and resets.

Rev.: C

Page 36

Page 36 Pentek Model 6210 Operating Manual

3.7 Programmable Gain Amplifier (GAIN) − R/W @ ‘C6x Address 0x0032 002C

This register controls the Model 6210’s Pragrammable−Gain Amplifier (PGAmp), shown in Figure 1−1, on page 9. This register is only functional if the PGAmp has not been bypassed (see Section 3.8.3). The amplifier is the Analog Devices Model AD603, and its gain control voltage is provided by a D/A converter, specifically the LTC1451, from Linear Technology. Appendix C of this manual is the data sheet for the amplifier, and Appendix D contains the data sheet for the D/A. Both provide complete block diagrams, specifications and other pertinent information. The DAC is programmed by serially shifting in a 12−bit data word. As shown in Table 3−6, below, the 3 active bits in this register provide a chip select for the DAC, a bit to toggle to create the serial shift clock, and a data bit. When reset, and when powered on, all 3 of these bits default to the logic ‘0’ state.

Table 3−6: Model 6210 − Programmable Gain Amplifier Register − R/W @ ‘C6x 0x0032 002C

Bit # D 3 1 − D 3 D2 D1 D0

Bit

Name

Bit

Function

R e s e r v e d

W r i t e w i t h Z e r o s,

M a s k w h e n R e a d i n g

All bits default to the logic ‘0’ state at power−up and resets.

3.7.1 Loading the 12−bit Gain Control Word

The Gain Control Register is used to serially load the 12−bit gain control word (GCW) into the LTC1451 DAC, which provides a gain control voltage for the input amplifier. The gain control word is loaded into the DAC, MSB first, by first clearing the Chip Select bit (D2) to the logic ‘0’ state, then toggling the Serial_Clock bit (D0) for each bit of the gain control word, stored in this regis− ter’s Input_Data bit, D1. The bits that comprise the gain control word are latched on the rising edge (i. e., the logic ‘1’ to logic ‘0’ transition) of the Serial_Clock bit. The DAC’s output voltage is updated on the rising edge (i.e., the logic ‘0’ to logic ‘1’ transition) of the Chip_Select bit. The complete sequence for writing the 12−bit word to the DAC involves 26 write operations to this register. A complete write sequence is shown in Table 3−8, at the bot− tom of the next page.

Chip_

Select

1 = Not Selected

0 = Load Data

Data_

Data to

be shifted

Serial

_Clock

Toggle for shift clock

Rev.: C

A sample program for loading the control word into the DAC is provided in the ReadyFlow Board Support Package for the Model 6210. The Gain Control Word for 0 dB gain is 250 (decimal), or 0xFA (hex). The gain control resolution is approximately 0.04 dB per LSB of the control word. Thus, incrementing or dec− remeting the control word by 25 decimal changes the gain of the amplifier by 1 dB. Table 3−7, at the top of the next page, shows the Gain Control Word value that should be loaded into the LTC1451 for full scale input amplitudes of +10 dBm to −20 dBm (or with option 102, 0 to −30 dBm) in 10 dBm increments.

When calculating the required gain for your application, remember to take into account the input low−pass filter, which may have an insertion loss of up to 5 dB.

Page 37

Pentek Model 6210 Operating Manual Page 37

3.7 Programmable Amplifier Gain (continued)

3.7.1 Loading the 12−bit Gain Control Word (continued)

Table 3−7: Model 6210 − Gain Control Word vs. Full Scale Input Amplitude

Gain Control Word

Decimal Hex

250 0x00FA 10 dBm 0 dBm

500 0x01F4 0 dBm −10 dBm

750 0x02EE −10 dBm −20 dBm

1000 0x03E8 −20 dBm −30 dBm

NOTE: The values given in this table DO NOT

which may be as high as 5 dB.

Table 3−8: Model 6210 − Sequence for Loading Gain Control Word

Write # Description D2 D1 D0

− Initial state. Chip select asserted (default power−up state). 0 0 0

1 De−assert chip select. 1 0 0

2 Assert chip select & setup bit 11, MSB of the GCW. 0 (GCW bit 11) 0

3 Latch bit 11, MSB of the GCW. 0 (GCW bit 11) 1

4 Setup bit 10 of the GCW. 0 (GCW bit 10) 0

5 Latch bit 10 of the GCW. 0 (GCW bit 10) 1

6 Setup bit 09 of the GCW. 0 (GCW bit 9) 0

7 Latch bit 09 of the GCW. 0 (GCW bit 9) 1

8 Setup bit 08 of the GCW. 0 (GCW bit 8) 0

9 Latch bit 08 of the GCW. 0 (GCW bit 8) 1

10 Setup bit 07 of the GCW. 0 (GCW bit 7) 0

11 Latch bit 07 of the GCW. 0 (GCW bit 7) 1

12 Setup bit 06 of the GCW. 0 (GCW bit 6) 0

13 Latch bit 06 of the GCW. 0 (GCW bit 6) 1

14 Setup bit 05 of the GCW. 0 (GCW bit 5) 0

15 Latch bit 05 of the GCW. 0 (GCW bit 5) 1

16 Setup bit 04 of the GCW. 0 (GCW bit 4) 0

17 Latch bit 04 of the GCW. 0 (GCW bit 4) 1

18 Setup bit 03 of the GCW. 0 (GCW bit 3) 0

19 Latch bit 03 of the GCW. 0 (GCW bit 3) 1

20 Setup bit 02 of the GCW. 0 (GCW bit 2) 0

21 Latch bit 02 of the GCW. 0 (GCW bit 2) 1

22 Setup bit 01 of the GCW. 0 (GCW bit 1) 0

23 Latch bit 01 of the GCW. 0 (GCW bit 1) 1

24 Setup bit 00, LSB of the GCW. 0 (GCW bit 0) 0

25 Latch bit 00, LSB of the GCW. 0 (GCW bit 0) 1

26 De−assert chip select. 1 0 0

Full Scale Input Amplitude

(Standard)

account for insertion loss of the low−pass input filter,

Full Scale Input Amplitude

(Option 102)

Rev.: C

Page 38

Page 38 Pentek Model 6210 Operating Manual

3.8 Data Format / Signal Path Register (DATA) − R/W @ ‘C6x Address 0x0032 0030

Each Motherboard Processor that can access this module has a separate version of this register, which contains four active bits. There are bits used to determine whether the data delivered to the motherboard is from the A/D or the DDR and whether the pro− grammable gain amplifier and low−pass, anti aliasing filter are in the signal path before the A/D. The other two bits determine whether or not the data applied to the DDR input is pre−decimated by a factor of two, and (if the DDR is bypassed) whether or not the A/D’s output data is packed. Table 3−9, below, shows the layout of the Model 6210’s Data Format/Signal Path Register, and the subsections that begin below the table describe how the bits are used.

Table 3−9: Model 6210 − Data Format / Signal Path Register − R/W @ ‘C6x 0x0032 0030

Bit # D 3 1 − D 4 D3 D2 D1 D0

Bit

Name

Bit

Function

R e s e r v e d

W r i t e w i t h Z e r o s,

M a s k w h e n R e a d i n g

All bits default to the logic ‘0’ state at power−up and resets.

DDR_In_

Dec_x2

1 = Decimate

0 = No Dec

3.8.1 Decimate DDR Input by 2 − Bit D3

When this bit is set to the logic ‘1’ state, the data delivered to the DDR by the A/D converter is decimated by a factor of 2 (i.e., all even−numbered samples are dropped). This is required if the HSP50214’s internal Cascaded Integra− tor−Comb (CIC) filter is bypassed (i.e., if bit D6 in the Control Word 0 Register in the DDR is set to the logic ‘1’ state). When this bit is cleared to the logic ‘0’ state (its default condition), all data converted by the A/D is delivered to the DDR (i.e., no samples are dropped).

3.8.2 Pack Mode − Bit D2

This bit is functional ONLY if the DDR is bypassed, and the 6210 is delivering raw A/D data to the VIM motherboard (i.e., if the D0 bit in this register is cleared to the logic ‘0’ state). If the preceding statement is true, then when this bit is set to the logic ‘1’ state, each 32−bit longword delivered to the mother− board’s BIFO by the 6210’s A/D will contain two consecutive 12−bit data samples, left−justified in each 16−bit field. In this case, the low word of each longword contains the earlier sample.

Pack_

Mode

1 = Pack

0 = No Pack

LPF/PGAmp

Bypass

1 = Bypass

0 = Use

DDR_

Bypass

1 = Use DDR

0 = A/D Only

Rev.: C

If the DDR is bypassed (D0 in this register contains a ‘0’) and this bit is cleared to the logic ‘0’ state (the default condition), then each 32−bit word delivered to the VIM motherboard by the 6210 will contain a single 12−bit A/D sample, left justified in the lower 16−bit word.

Page 39

Pentek Model 6210 Operating Manual Page 39

3.8 Data Format / Signal Path Register (continued)

3.8.2 Pack Mode (continued)

If the DDR is in the 6210’s data path between the A/D and the VIM mother− board (i.e., if D0 in this register is set to the logic ‘1’ state), then the state of this bit is ignored, and the operating mode of the HSP50214 determines the output data format (see Appendix A, the HSP50214 data sheet, for details about set− ting the operating mode of the DDR). If the DDR operates in Complex mode, each 32−bit word delivered from the 6210’s DDR to the motherboard BIFO contains a 16−bit Q (quadrature or imaginary) sample in the upper word (D31

− D16), and a 16 bit I (in−phase or real) sample in the lower word (D15 − D0). If the DDR operates in Real−Only mode, each 32−bit word delivered from the 6210’s DDR to the motherboard BIFO contains only one 16−bit I sample, in the low word. In all unpacked formats, the data in the upper word is indetermi− nate.

All data delivered to the motherboard BIFO by the 6210 is in signed 2’s com− plement format, with the MSB of the data sample set to the logic ‘1‘ state to indicate negative data values. Table 3−10, below, illustrates the available for− mats for output data from the Model 6210.

Table 3−10: Model 6210 − Output Data to Motherboard BIFO − Packing Formats

Packed A/D Data (D2 = 1, D0 = 0)

O/P Word # D31 − − − − − − − − − − − − − D20 D19 − D16 D15 − − − − − − − − − − − − − D4 D3 − D0

(MSB) A/D Sample #2 (LSB)

(MSB) A/D Sample #4 (LSB)

(MSB) A/D Sample #1 (LSB)

? ?

(MSB) A/D Sample #3 (LSB)

? ?

Unpacked A/D Data (D2 = 0, D0 = 0)

O/P Word # D31 − − − − − − − − − − − − − − − − − − D16 D15 − − − − − − − − − − − − − D4 D3 − D0

1 I n d e t e r m i n a t e

2 I n d e t e r m i n a t e

(MSB) A/D Sample #1 (LSB)

(MSB) A/D Sample #2 (LSB)

Complex DDR Data (D2 = X, D0 = 1)

O/P Word # D31 − − − − − − − − − − − − − − − − − − D16 D 15 − − − − − − − − − − − − − − − − D0

(MSB) DDR Q Sample #1 (LSB) (MSB) DDR I Sample #1 (LSB)

(MSB) DDR Q Sample #2 (LSB) (MSB) DDR I Sample #2 (LSB)

Real DDR Data (D2 = X, D0 = 1)

O/P Word # D31 − − − − − − − − − − − − − − − − − − D16 D 15 − − − − − − − − − − − − − − − − D0

1 I n d e t e r m i n a t e

2 I n d e t e r m i n a t e

? ? = I n d e t e r m i n a t e , X = D o n ’ t C a r e

(MSB) DDR I Sample #1 (LSB)

(MSB) DDR I Sample #2 (LSB)

Rev.: C

Page 40

Page 40 Pentek Model 6210 Operating Manual

3.8 Data Format / Signal Path Register (continued)

3.8.2 Pack Mode (continued)

When the DDR’s are bypassed, output data by the Model 6210’s A/D con− verters is encoded in true 12−bit 2’s complement format, with the remaining 4 bits of the 16−bit word in which the sample resides indeterminate. The MSB (D15) is used as a sign bit and indicates a negative input voltage when set to the logic ‘1’ state. The maximum negative input voltage (−1 V dard input signal range) results in an output data code of 1000 0000 0000 xxxx (0x800x), while an input exactly one step above half−scale (( + 490 mV produces an output code of all 12 active bits cleared to the logic ‘0’ state. A full−scale positive input voltage (+1 V

) produces an output data code of

0111 1111 1111 xxxx (0x7FFx). Table 3−11, below, provides the output data coding scheme used by the Model 6211.

Table 3−11: Model 6210 − A/D Output Data Coding

Step

(Decimal)

0 −1.00000 V 1000 0000 0000 xxxx 0x800x 1 −0.99951 V 1000 0000 0001 xxxx 0x801x 2 −0.99902 V 1000 0000 0010 xxxx 0x802x

Input

Voltage (DC,

Nominal)

Binary Output Code

(D15 − D0)

Hexadecimal

Output Code

for the stan−

)

…

2046 −0.00049 V 1111 1111 1110 xxxx 0xFFEx 2047 0.00000 V 1111 1111 1111 xxxx 0xFFFx 2048 +0.00049 V 0000 0000 0000 xxxx 0x000x 2049 +0.00098 V 0000 0000 0001 xxxx 0x001x

…

4093 +0.99902 V 0111 1111 1101 xxxx 0x7FDx 4094 +0.99951 V 0111 1111 1110 xxxx 0x7FEx 4095 +1.00000 V 0111 1111 1111 xxxx 0x7FFx

…

x = Indeterminate

…

3.8.3 Programmable−Gain Amplifier & Low−Pass Filter Bypass − Bit D1

When this bit is set to the logic ‘1’ state, the analog input signal is routed around the programmable−gain amplifier and the low−pass, anti aliasing fil− ter. This allows the full bandwidth of the input signal to be delivered to the A/D converter, which is necessary in undersampling applications. For appli− cations where undersampling is not required and it is desirable to eliminate frequency components above the Nyquist limit that may be present in the input signal, clear this bit to the logic ‘0’ state to place the low−pass filter and programmable−gain amplifier in the signal path.

Rev.: C

Page 41

Pentek Model 6210 Operating Manual Page 41

3.8 Data Format / Signal Path Register (continued)

3.8.4 DDR Bypass − Bit D0

This bit allows the Model 6210 to function as a simple A/D converter, by routing the output data directly to the BIFO on the VIM motherboard. A/D data will bypass the Intersil HSP50214 DDR chip when this bit is cleared to the logic ‘0’ state (its default condition). When this bit is set to the logic ‘1’ state, the DDR is placed in the data path between the A/D converter and the moth− erboard’s BIFO, and all of the Model 6210’s digital receiver functions are available.

3.9 SYNC Generate Register (SYNC) − W.O. @ ‘C6x Address 0x0032 0034

Any write operation to this register will cause the generation of a SYNC1 pulse. The data associated with the write operation is neither used nor stored and is therefore trivial. The ability to generate a SYNC1 pulse via a write operation is provided for applications in which the DDR is bypassed, because the SYNC1 pulse is usually gener− ated by the HSP50214B DDR. This register along with the BIFO Disable bit (D3 in the Control Register, see Section 3.4.2) allow a 6210 in which the DDR is unused to become a Sync bus master.

This register is accessible only to Processor A or Processor C on the VIM motherboard, depending upon the position in which the module is installed. Neither Processor B nor Processor D on a VIM motherboard can ever access this register.

Rev.: C

Page 42

Page 42 Pentek Model 6210 Operating Manual

3.10 Serial Port 0 Connection Register (SPORT) − R/W @ ‘C6x Address 0x0032 0038

The Serial Port 0 Connection Register (SPORT) controls which device provides serial input to the receive section of Serial Port 0 for a processor on the VIM motherboard. The two active bits in this register comprise a field that determines the source of the serial connection. Each processor on the VIM motherboard that can access a given 6210 has a separate version of this register, whose power−up default state is both bits cleared to the logic ‘0’ state.

Figure 1−1, on page 9 contains the block diagram of the Model 6210 and shows the various

serial connections possible using this register. Table 3−12, below, shows the register’s layout & summarizes the function of its lone bit−field. The connections made by the states of the bits are defined in more detail in the subsections beginning below the table.

Table 3−12: Model 6210 − Serial Port 0 Connection Register − R/W @ ‘C6x 0x0032 0038

Bit # D 3 1 − D 2 D1 D0

Bit

Name

Bit

Function

R e s e r v e d SPort_Source_1 SPort_Source_0

W r i t e w i t h Z e r o s,

M a s k w h e n R e a d i n g

All bits default to the logic ‘0’ state at power−up and resets.

1, 1 = Other Processor

1, 0 = Other DDR

0, 1 = Own DDR

0, 0 = Not Connected

3.10.1 The Other Processor’s Serial Port 0 Transmit Section (D1 = 1, D0 = 1)

When a processor on the VIM motherboard sets both bits in this register to the logic ‘1’ state, the receiver portion of that processor’s Serial Port 0 will be con− nected to the transmit section other processor’s Serial Port 0.

3.10.2 The Other Processor’s DDR (D1 = 1, D0 = 0)

When a processor on the VIM motherboard sets D1 in this register to the logic ‘1’ state and clears D0 to the logic ‘0’ state, Serial Output A on the receiver− normally associated with the other processor (i.e., receiver 2 for processor A or C, or receiver 1 for processor B or D) will be connected to the receiver sec− tion of that processor’s serial port 0.

Rev.: C

3.10.3 The Processor’s Own DDR (D1 = 0, D0 = 1)

When a processor on the VIM motherboard clears D1 in this register to the logic ‘0’ state and sets D0 to the logic ‘1’ state, Serial Output A on the receiver normally associated with that processor (i.e., receiver 1 for processor A or C, or receiver 2 for processor B or D) will be connected to the receiver section of that processor’s serial port 0.

Page 43

Pentek Model 6210 Operating Manual Page 43

3.10 Serial Port Connection Register (continued)

3.10.4 Not Connected (D1 = 0, D0 = 0)

When a processor on the VIM motherboard clears both bits in this register to the logic ‘0’ state, the receiver section of that processor’s Serial Port 0 is not connected to any other device.

3.11 CIC Gain Adjust Register− R/W @ ‘C6x Address 00x0032 003C

The three active bits in this register drive the three GAINADJ pins the HSP50214B DDR chip. The GAINADJ function adds an offset to the gain via a shifter between the mixer and CIC filter (internal to the HSP50214B chip), . GAINADJ value is added to the shift code in the DDR’s Control Word 0 Register, bits D16 − D13. The actual gain that can be provided in this section reaches its maximum value when the sum of the 4 CIC shift gain bits (CW0, D16 − D13), and these three Gain Adjust bits is equal to 15 (0xF). The gain adjustment provided by these 3 bits is equal to 6dB/LSB (i.e., a 1−bit change in the value stored in this register will result in a 6 dB change in the gain, thus code 002 would give 12 dB gain, code 111 would result in 42dB of gain). For additional information, please see the section entitled “Using the Input Gain Adjust Control Signals” in the Intersil HSP50214B data sheet, Appendix A of this manual.

Table 3−13: Model 6210 − CIC Gain Adjust Register − R/W @ ‘C6x 0x0032 003C

Bit # D 3 1 − D 4 D2 D1 D0

Bit

Name

Bit

Function

R e s e r v e d

W r i t e w i t h Z e r o s,

M a s k w h e n R e a d i n g

All bits default to the logic ‘0’ state at power−up and resets.

Gain

Adj_2

Gain applied before CIC filter is

changed by 6dB/LSB in this field.

Gain

Adj_1

3.12 Processor Interface the HSP50214 DDR

The remaining registers in the Model 6210’s memory map provide the means by which processors on the VIM motherboard can write control information to, and read status data from, the HSP50214 DDR chip. These resources include four holding registers for temporary storage of write/read data, a destination address register for writes, a source address register for reads and a dedicated register for the data returned by sta− tus reads. Table 3−14, at the top of the next page, summarizes the functions & addresses of these registers. The text that follows the table describes how these resources are used to communicate with the DDR.

Gain

Adj_1

Rev.: C

Page 44

Page 44 Pentek Model 6210 Operating Manual

3.12 Processor Interface the HSP50214 DDR (continued)

Table 3−14: Model 6210 − DDR Interface Resources

‘C6X Address Register Description Mnemonic Access Function

0x0032 0040 DDR Holding Register 0 DDR0 R/W Control Word D0:D7 0x0032 0044 DDR Holding Register 1 DDR1 R/W Control Word D8:D15 0x0032 0048 DDR Holding Register 2 DDR2 R/W Control Word D16:D23

0x0032 004C DDR Holding Register 3 DDR3 R/W Control Word D24:D31

0x0032 0050 DDR Write Destination Address Register DDR4 R/W Control Register to Write 0x0032 0054 DDR Read Source Register DDR5 R/W Source of Read Data

0x0032 005C DDR Status Read Register DDR6 R. O. Status Register

The 6210’s write interface to the HSP50214 uses an indirect addressing scheme wherein a 32−bit data word is first loaded into four 8−bit master registers internal to the DDR chip from the 8 LSB's of the four DDR Holding Registers on the 6210 (DDR0 − DDR3). The address of the desired destination register in the DDR is then written to the 6210’s DDR Write Destination Address Register (DDR4). Writing this address triggers a circuit that generates a pulse, synchronous to a clock, that loads the HSP 50214’s internal Destination Register. The sync circuits and data words are synchronized to different clocks (CLKIN or PROCCLK) depending on the registers affected by a given write operation. For additional

information, you may refer to the “Microprocessor Write” section of the

HSP50214 data sheet, in Appendix A of this manual.

The 6210’s read interface to the HSP50214 uses both read and write operations to obtain data from the DDR. First, a 3−bit “read code” must be written must to the 6210’s DDR Read Source Register to select the source of data to be read. The data sources selected by the various read codes are listed in Table 3−15, at the top of the next page. Writing to the Read Source register will cause the 6210 to initiate a readout cycle, which will transfer the requested data from the selected source to the 8 LSBs of some or all of the 6210’s four DDR holding registers (DDR0 − DDR3), depending upon the specific data

source. For additional information, please refer to the “Microprocessor Read” section

of the HSP50214 data sheet, in Appendix A of this manual.

An additional register has been provided to allow the user to easily obtain status infor− mation from the HSP50214. Reading the DDR Status Read Register (DDR6), will return the status bits shown in Table 3−16, at the bottom of the next page. This topic is also

covered in the “Microprocessor Read” section of Appendix A.

Rev.: C

Page 45

Pentek Model 6210 Operating Manual Page 45

3.12 Processor Interface the HSP50214 DDR (continued)

Table 3−15: Model 6210 − DDR Read Source Definitions

Read Code Data Data Returned

(D2 : D0) Source Type Where

I (LSB) DDR0

000 I & Q Buffer RAM

001

010 Buffered Frequency

011 N o t U s e d N o t A p p l i c a b l e

100 Input Level Detector

101

111

Magnitude & Phase Buffer

RAM

N o t U s e d N o t A p p l i c a b l e110

I (MSB) DDR1

Q (LSB) DDR2

Q (MSB) DDR3

Mag (LSB) DDR0

Mag (MSB) DDR1

Phase (LSB) DDR2

Phase (MSB) DDR3

Freq (LSB) DDR0

Freq (MSB) DDR1

Input AGC (LSB) DDR0

Input AGC (NSB) DDR1

Input AGC (MSB) DDR2

Table 3−16: Model 6210 − DDR Status Read Register − R/W @ ‘C6x 0x0032 003C

Bit # D31 − D7 D6 D5 D4 D3 D2 D1 D0

Bit

Name

Bit

Function

Reserved

Mask on

Reads

Internal_FIFO_Depth

# of 80−bit (16−bit I, Q, |r|, φ & ƒ)

samples in Internal FIFO

All bits default to the logic ‘0’ state at power−up and resets.

Internal_

FIFO_Empty

1 = T r u e

0 = F a l s e

Internal_

FIFO_Full

Buffer_

Ready

1 = Not Ready

0 = Ready

Integration_

1 = Complete

0 = Incomplete

Complete

Rev.: C

Page 46

Page 46 Pentek Model 6210 Operating Manual

This page is intentionally blank

Rev.: C

Page 47

Pentek Model 6210 Operating Manual Intersil HSP50214B Page A−1

Appendix A: Intersil HSP50214B − Programmable Downconverter

Included for your reference on the following pages is the data sheet for the HSP50214B Programmable Downconverter, provided by the courtesy of Intersil Corp., Palm Bay FL. Please note that this device is referred to as a Digital Drop Receiver (DDR) in the body of this manual, whreras the manufacturer uses the term Programmable Downconverter (PDC). These are application−oriented terms, used to refer to devices that perform essen− tially identical functions.

Rev.: C

Page 48

Page A−2 Intersil HSP50214B Pentek Model 6210 Operating Manual

This page is intentionally blank

Rev.: C

Page 49

HSP50214B

Data Sheet May 2000 File Number 4450.3

[ /Title (HSP5 0214B) /Subject (Programmable Downconverter) /Autho r () /Keywords (Intersil Corporation, Downconverter, Down Converter, Programmable Downconverter, DSP, AMPS, TDMA , North American TDMA ,GSM,

Programmable Downconverter

The HSP50214B Programmable Downconverter converts digitized IF data into ﬁltered baseband data which can be processed by a standard DSP microprocessor. The Programmable Downconverter (PDC) performs down conversion, decimation, narrowband low pass ﬁltering, gain scaling, resampling, and Cartesian to Polar coordinate conversion.

The 14-bit sampled IF input is down converted to baseband by digital mixers and a quadrature NCO, as shown in the Block Diagram. A decimating (4 to 32) ﬁfth order Cascaded Integrator-Comb (CIC) ﬁlter can be applied to the data before it is processed by up to 5 decimate-by-2 halfband ﬁlters. The halfband ﬁlters are followed by a 255-tap programmable FIR ﬁlter. The output data from the programmable FIR ﬁlter is scaled by a digital AGC before being re-sampled in a polyphase FIR ﬁlter. The output section can provide seven types of data: Cartesian (I, Q), polar (R,θ), ﬁlteredfrequency (dθ/dt), Timing Error (TE),and AGC level in either parallel or serial format.

Ordering Information

PART

NUMBER

HSP50214BVC 0 to 70 120 Ld MQFP Q120.28x28 HSP50214BVI -40 to 85 120 Ld MQFP Q120.28x28

TEMP.

RANGE (oC) PACKAGE PKG. NO.

Block Diagram

MICROPROCESSOR

C(7:0)

IN(13:0)

GAIN

ADJ

(2:0)

COF

SOF

CLKIN

PROCCLK

REFCLK

READ/WRITE

LEVEL DETECT

INPUT

SECTION

CARRIER

NCO

CONTROL

ORDER

CIC

FILTER

ORDER

CIC

FILTER

HALFBAND

FILTERS

255-TAP

FIR FILTER

255-TAP

FIR FILTER

RESAMPLING

NCO

Features

• Up to 65 MSPS Front-End Processing Rates (CLKIN) and 55MHz Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous

• Processing Capable of >100dB SFDR

• Up to 255-Tap Programmable FIR

• Overall Decimation Factor Ranging from 4 to 16384

• Output Samples Rates to ≅12.94 MSPS with Output Bandwidths to ≅ 982kHz Lowpass

• 32-Bit Programmable NCO for Channel Selection and Carrier Tracking

• Digital Resampling Filter for Symbol Tracking Loops and Incommensurate Sample-to-Output Clock Ratios

• Digital AGC with Programmable Limits and Slew Rate to Optimize Output Signal Resolution; Fixed or Auto Gain Adjust

• Serial, Parallel, and FIFO 16-Bit Output Modes

• Cartesian toPolar Converter and Frequency Discriminator for AFC Loops and Demodulation of AM, FM, FSK, and DPSK

• Input Level Detector for External I.F. AGC Support

Applications

• Single Channel Digital Software Radio Receivers

• Base Station Rx’s: AMPS, NA TDMA, GSM, and CDMA

• Compatible with HSP50210 Digital Costas Loop for PSK Reception

• Evaluation Platform Available

AGC LOOP FILTER

AGC

POLYPHASE

FIR AND

HALFBAND

FILTERS

POLYPHASE

FIR AND

HALFBAND

FILTERS

DISCRIMINATOR

∆

I OUT

CARTESIAN

POLAR

COORDINATE CONVERTER

Q OUT

TIMING ERROR

MAG.

PHASE

FREQ

SEROUTA SEROUTB AOUT(15:0)

BOUT(15:0)

OUTPUT FORMATTER

3-1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Page 50

HSP50214B

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

FIGURE 1. FUNCTIONAL BLOCK DIAGRAM OF THE HSP50214B PROGRAMMABLE DOWNCONVERTER . . . . . . . . . . . . . . . . . . . . . . . . 3-7

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

PDC Applications Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

FDM Based Standards and Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

TDM Based Standards and Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

CDMA Based Standards and Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

Traditional Modulation Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

Resampling and Interpolation Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

14-Bit Input and Processing Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

Multiple Chip Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

FIGURE 2. SYNCHRONIZATION CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

Input Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

Interpolation Example: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

Input Level Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

FIGURE 3. BLOCK DIAGRAM OF THE INPUT SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

FIGURE 4. STATEMENT OF THE PROBLEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

FIGURE 5. BLOCK DIAGRAM OF THE INTERPOLATION APPROACH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

FIGURE 6. INTERPOLATION SPECTRUM: INTERPOLATE BY 8 THE INPUT DATA WITH ZERO STUFFING; SAMPLE AT RATE R = f’s. . . . . 3-12

FIGURE 7. ALIAS PROFILE AND THE 85dB DYNAMIC RANGE BANDWIDTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12

FIGURE 8. PROCESSOR BASED EXTERNAL IF AGC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12

FIGURE 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13

FIGURE 10. INPUT THRESHOLD DETECTOR BIT WEIGHTING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13

FIGURE 11. SIGNAL PROCESSING WITHIN LEVEL DETECTOR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14

Carrier Synthesizer/Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14

FIGURE 12. BLOCK DIAGRAM OF NCO SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14

FIGURE 13. SERIAL INPUT TIMING FOR COF AND SOF INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15

FIGURE 14. HOLDING REGISTERS LOAD SEQUENCE FOR COF AND SOF SERIAL OFFSET FREQUENCY DATA . . . . . . . . . . . . . . . . . . 3-15

CIC Decimation Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

FIGURE 15. CIC SHIFT GAIN VALUES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

CIC Gain Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

Using the Input Gain Adjust Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17

Halfband Decimating Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17

FIGURE 16. CIC FILTER BIT WEIGHTING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17

FIGURE 17. BLOCK DIAGRAM OF HALFBAND FILTER SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

FIGURE 18. HALFBAND FILTER FREQUENCY RESPONSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

FIGURE 19. HALFBAND FILTER ALIAS CONSIDERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

Examples of PROCCLK Rate Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19

255-Tap Programmable FIR Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19

FIGURE 20. DEMONSTRATION OF DIFFERENT TYPES OF DIGITAL FIR FILTERS CONFIGURED IN THE

PROGRAMMABLE DOWNCONVERTER

Automatic Gain Control (AGC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20

FIGURE 21. AGC MULTIPLIER LINEAR AND dB TRANSFER FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21

FIGURE 22. AGC GAIN CONTROL TRANSFER FUNCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21

FIGURE 23. AGC BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23

Re-Sampler/Halfband Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25

FIGURE 24A. POLYPHASE RESAMPLER FILTER BROADBAND FREQUENCY RESPONSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25

FIGURE 24B. POLYPHASE RESAMPLER FILTER PASS BAND FREQUENCY RESPONSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25

FIGURE 24C. POLYPHASE RESAMPLER FILTER EXPANDED RESOLUTION PASSBAND FREQUENCY RESPONSE . . . . . . . . . . . . . . . . . 3-28

FIGURE 25. GENERATING DATA READY PULSES FOR OUTPUT DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28

Timing NCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28

FIGURE 26. TIMING NCO BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29

FIGURE 27. TIMING ERROR GENERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29

FIGURE 27A. TIMING ERROR APPLICATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20

3-2

Page 51

HSP50214B

PAGE

Cartesian to Polar Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30

FIGURE 28. PHASE BIT MAPPING OF COORDINATE CONVERTER OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30

Frequency Discriminator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31

FIGURE 29. FREQUENCY DISCRIMINATOR BLOCK DIAGRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31

Output Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32

Parallel Direct Output Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32

Data Transitions:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32

FIGURE 30. PARALLEL OUTPUT BLOCK DIAGRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32

Data Ready Signal Assertion Rate: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33

FIGURE 31. DATARDY WAVEFORMS WHEN I (READ DATA) IS SELECTED AS AOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33

FIGURE 32. DATARDY WAVEFORMS WHEN |r| (MAGNITUDE) IS SELECTED AS AOUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33

FIGURE 33. DATARDY WAVEFORMS WHEN f (FREQUENCY) IS SELECTED AS AOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33

Serial Direct Output Port Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34

FIGURE 34. SERIAL OUTPUT FORMATTER BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35

Serial Output Conﬁguration Example 1: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36

Serial Output Conﬁguration Example 2:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36

FIGURE 35. EXAMPLE 2 SERIAL OUTPUT DATA STREAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37

FIGURE 36. VALID SERSYNC CONFIGURATION OPTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37

Buffer RAM Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37

FIFO Operation via 16-Bit µProcessor Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38

FIGURE 37. 16-BIT MICROPROCESSOR INTERFACE BUFFER RAM MODE BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38

FIGURE 38. INTERFACE BETWEEN A 16-BIT MICROPROCESSOR AND PDC IN FIFO BUFFER RAM MODE . . . . . . . . . . . . . . . . . . . . . . 3-39

FIGURE 39. TIMING DIAGRAM FOR PDC IN FIFO MODE WITH OUTPUTS I, Q, AND FREQUENCY SENT TO AOUT(7:0) AND BOUT(7:0) . . 3-39

FIGURE 40. FIFO REGISTER OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40

FIFO Operation via 8-Bit µProcessor Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40

FIGURE 41. 8-BIT MICROPROCESSOR INTERFACE BUFFER RAM MODE BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41

FIGURE 42. RAM LOAD SEQUENCE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41

Snap Shot Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41

FIGURE 43. SNAP SHOT SAMPLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41

Avoiding Timing Pitfalls When Using the Buffer RAM Output Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42

FIGURE 44. AVOIDING FALSE INTRRP ASSERTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42

Microprocessor Write Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42

FIGURE 45. LOADING THE CONTROL REGISTERS WITH 32-BIT CONTROL WORDS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43

Microprocessor Read Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43

FIGURE 46. READING THE CONTROL REGISTERS USING A LATCH CODE EQUAL TO A 5, A READ ADDRESS AND A READ CODE . . . . 3-43

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44

Composite Filter Response Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44

FIGURE 47. RECEIVE SIGNAL FREQUENCY SPECTRUM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44

RF/IF Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44

PDC Conﬁguration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45

FIGURE 48A. CIC FILTER RESPONSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46

FIGURE 48B. HB3 FILTER RESPONSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46

FIGURE 49A. HB5 FILTER RESPONSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46

FIGURE 49B. 255 FIR TAP FILTER RESPONSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46

FIGURE 49C. COMPOSITE FILTER RESPONSE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46

FIGURE 49D. PDC FILTER FREQUENCY SPECTRUMS EXAMPLE (NORMALIZED TO SAME SCALE). . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46

Conﬁguration Control Word Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47

AC Test Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-59

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-60

FIGURE 50. TIMING RELATIVE TO WR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-60

FIGURE 51. TIMING RELATIVE TO RD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-60

FIGURE 52. OUTPUT RISE AND FALL TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-60

FIGURE 53. TIMING RELATIVE TO CLKIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-60

FIGURE 54. OUTPUT ENABLE/DISABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-60

FIGURE 55. TIMING RELATIVE TO PROCCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-60

FIGURE 56. REFCLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-60

3-3

Page 52

Pinout

IN11

IN12

IN13

REFCLK

VCCAGCGNSEL

GND

AOUT15

OEAH

HSP50214B

120 LEAD MQFP

TOP VIEW

AOUT10

AOUT11

AOUT12

AOUT13

AOUT14

GND

AOUT8

AOUT9

AOUT6

AOUT7

VCCAOUT5

AOUT3

AOUT4

AOUT1

AOUT2

GND

AOUT0

OEAL

IN10

IN9 IN8

GND

IN7

NC IN6 IN5 IN4 IN3 IN2

GND

IN1 IN0

CLKIN

GND

ENI GAINADJ2 GAINADJ1 GAINADJ0

COF

COFSYNC

GND

SOF

SOFSYNC

SYNCIN1 SYNCIN2

103

102

101

100

114

113

112

111

117

118

119

120 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

115

116

333435363738394041424344454647484950515253545556575859

105

104

106

107

108

109

110

90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73

72 71 70 69 68 67 66 65 64 63 62 61

DATARDY OEBH BOUT15 BOUT14 V

NC BOUT13 BOUT12 BOUT11 BOUT10 BOUT9 BOUT8 GND GND PROCCLK V

MSYNCI MSYNCO GND BOUT7 BOUT6 BOUT5 GND BOUT4 NC BOUT3 BOUT2 BOUT1 BOUT0 OEBL

SYNCOUT

3-4

INTRRP

GND

C6NCC5

C3C2C1NCC0A2A1

GND

SEL2

SEL1

GND

SEL0

SEROUTA

SERSYNC

SEROUTB

SEROE

SERCLK

Page 53

HSP50214B

Pin Descriptions

NAME TYPE DESCRIPTION

GND - Ground.

CLKIN I Input Clock.This clockshould bea multiple of theinput sample rate.All inputsection processingoccurs on therising

IN(13:0) I InputData. The formatof the inputdata may beset tooffset binary or2’s complement. IN13is theMSB (seeControl

ENI I InputEnable. Active Low. This pinenables the inputto the part in oneof twomodes, gatedor interpolated (see Con-

GAINADJ(2:0) I GAINADJ Input. Adds an offset to the gain via the shifter following the mixer. GAINADJ value is added to the shift

PROCCLK I Processing Clock. PROCCLK is theclock forall processing functions following the CIC Section. Processing is per-

AGCGNSEL I AGC Gain Select. This pin selects between two AGCloop gains. This input is setup and held relativeto PROCCLK.

COF I Carrier Offset Frequency Input. This serial input pin is used to load the carrier offset frequency into the Carrier NCO

COFSYNC I Carrier Offset Frequency Sync. This signal is asserted one CLK before the most signiﬁcant bit (MSB) of the offset

SOF I Re-Sampler Offset Frequency Input. This serial input pin is used to load the offset frequency into the Re-Sampler

SOFSYNC I Re-Sampler Offset FrequencySync. This signal is asserted one CLK before the MSB of the offset frequency word

AOUT(15:0) O Parallel OutputBus A.Two parallel outputmodes are available on theHSP50214B. The ﬁrstis calledthe DirectOut-

BOUT(15:0) O Parallel OutputBus B.Two parallel outputmodes are available onthe HSP50214B. Theﬁrst iscalled theDirect Out-

- Positive Power Supply Voltage.

edge of CLKIN. The frequency of CLKIN is designated f

Word 0).

trol Word 0). In gated mode,one sample is taken per CLKIN whenENI is asserted. The input sample rate is designated fS, which can be different from f

code from the microprocessor(µP) interface. Theshift codeis saturatedto amaximum code of F. Thegain isoffset by (6dB)(GAINADJ); (000 = 0dB gain adjust;111 = 42dB gain adjust)GAINADJ2 is the MSB. See “Using the Input Gain Adjust Control Signals” Section.

formed on PROCCLK’s rising edge. All output timing is derived from this clock.

NOTE: This clock may be asynchronous to CLKIN.

Gain setting 1 is selected when AGCGNSEL = 1.

(see Serial Interface Section).The offsetmay be8, 16, 24, or 32 bits. The setup and hold times are relativeto CLKIN. This input is compatible with the output of the HSP50210 Costas loop [1].

frequency word (see Serial Interface Section). The setup and hold times are relative to CLKIN. This input is compatible with the output of the HSP50210 Costas loop [1].

NCO (see Serial Interface Section). The offset may be 8, 16, 24, or 32 bits. The setup and hold times are relative to PROCCLK. This input is compatible with the output of the HSP50210 Costas loop [1].

(see Serial Interface Section).The setupand holdtimes arerelative to PROCCLK. This inputis compatiblewith the output of the HSP50210 Costas loop [1].

put Port, where the source is selected through Control Word 20 (see the Microprocessor Write Section) and comes directly fromthe Output MUX Section (see Output ControlSection). The most signiﬁcant byte of AOUT alwaysoutputs the most signiﬁcant byte of the Parallel Direct Output Port whose data type is selected via µP interface. AOUT15 is the MSB. In this mode, the AOUT(15:0) bus is updated as soon as data is available. DATARDYisasserted to indicatenew data. For this mode, the outputchoices are: I,|r|, or f. The format is 2’s complement, except for magnitude, which is unsigned binary with a zero as the MSB.

The second mode for parallel data is called the Buffer RAM Output Port. The Buffer RAM Output Port acts like a FIFO for blocksof information called data sets. Within a data setis I, Q, magnitude, phase, and frequencyinformation;a datatype isselected usingSEL(2:0). Upto 7data setsare stored inthe Buffer RAM OutputPort.The LSBytes of the AOUT and BOUT busses form the 16 bits for the buffered output mode and can be used for buffered mode while the MSBytes are outputting data in the direct output mode. For thismode, theoutput formats are the same as the Direct Output Port mode.

put Port, where the source is selected through Control Word 20 (see the Microprocessor Write Section) and comes directly fromthe Output MUX Section (see Output ControlSection). The most signiﬁcant byte of BOUT always outputs the most signiﬁcant byte of the Parallel Direct Output Port whose data type is selected via µP interface. BOUT15 is the MSB. In this mode, the BOUT(15:0) bus is updated as soon as data is available. DATARDY is asserted toindicate new data.For this mode,the outputchoices are: Q, φ, or|r|. The format is 2’s complement,except for magnitude which is unsigned binary with a zero as the MSB.

The second mode for parallel data is called the Buffer RAM Output Port. The Buffer RAM Output Port acts like a FIFO for blocksof information called data sets. Within a data setis I, Q, magnitude, phase, and frequencyinformation; a particular information is selected using SEL(2:0). Up to 7 data sets is stored in the Buffer RAMOutput Port. The least signiﬁcant byte of BOUT can be used to either output the least signiﬁcant byte of the B Parallel Direct Output Port orthe leastsigniﬁcant byte ofthe BufferRAM OutputPort. See OutputSection. Forthis modethe output formats are the same as the Direct Output Port mode.

when ENI is used.

CLKIN

3-5

Page 54

HSP50214B

Pin Descriptions (Continued)

NAME TYPE DESCRIPTION

DATARDY O Output Strobe Signal. Active Low. Indicates when new data from the Direct Output Port Section is available. DA-

TARDYis asserted forone PROCCLK cycleduring the ﬁrst clockcycle thatdata isavailableon theparallel outbusses. See Output Section.

OEAH I Output enable for the MSByte of the AOUT bus. Active Low. The AOUT MSByte outputs are three-stated when

OEAH is high.

OEAL I Output enable for the LSByte of the AOUT bus. Active Low. The AOUT LSByte outputs are three-stated when

OEAL is high.

OEBH I Output enable for the MSByte of the BOUT bus. Active Low. The BOUT MSByte outputs are three-stated when

OEBH is high.

OEBL I Output enable for the LSByte of the BOUT bus. Active Low. The BOUT LSByte outputs are three-stated when

OEBL is high.

SEL(2:0) I Select Address is used to choose which information in a data set from the Buffer RAM Output Port is sent to the

least signiﬁcant bytes of AOUT and BOUT. SEL2 is the MSB.

INTRRP O Interrupt Output. Active Low. This output is asserted for 8 PROCCLK cycles when the Buffer RAM Output Port is

ready for reading.

SEROUTA O Serial Output Bus A Data. I, Q, magnitude, phase, frequency, timing error and AGCinformation can be sequenced

in programmable order. See Output Section and Microprocessor Write Section.

SEROUTB O Serial Output Bus B Data. Contents may be related to SEROUTA. I, Q, magnitude, phase, frequency, timing error

and AGC information can be sequenced in programmable order. See Output Section and Microprocessor Write Section.

SERCLK O Output Clock forSerial DataOut. Derived fromPROCCLK as givenby Control Word20 inthe Microprocessor Write

Section.

SERSYNC O Serial Output Sync Signal. Serves as serial data strobes. See Output Section and Microprocessor Write Section.

SEROE I Serial Output Enable. When high, the SEROUTA, SEROUTB, SERCLK, and SERSYNC signals are set to a high

impedance. C(7:0) I/O Processor Interface Data Bus. See Microprocessor Write Section. C7 is the MSB. A(2:0) I Processor Interface Address Bus. See Microprocessor Write Section. A2 is the MSB.

WR I Processor Interface Write Strobe. C(7:0) is written to Control Words selected by A(2:0) in theProgrammable Down

Converter on the rising edge of this signal. See Microprocessor Write Section.

RD I Processor Interface Read Strobe. C(7:0) is read from output or status locations selected by A(2:0) in the Pro-

grammable Down Converter on the falling edge of this signal. See Microprocessor Read Section.

REFCLK I Reference Clock.Used asan inputclock for the timing error detector. Thetiming erroris computedrelative toREF-

CLK. REFCLK frequency must be less than or equal to PROCCLK/2.

MSYNCO O Multiple Chip Sync Output. Provided for synchronizing multiple parts when CLKIN and PROCCLK are asynchro-

nous. MSYNCO is the synchronization signal between the input section operating under CLKIN and the back end

processing operating under PROCCLK. This output sync signal from one part is connected to the MSYNCI signal

of all the HSP50214Bs.

MSYNCI I Multiple Chip Sync Input. The MSYNCI pin of all the parts should be tied to the MSYNCO of one part.

NOTE: MSYNCI must be connected to an MSYNCO signal for operation.

SYNCIN1 I CIC Decimation/Carrier NCO Update Sync. Can be used to synchronize the CIC Section, carrier NCO update, or

both. See theMultiple ChipSynchronization Sectionand Control Word 0 inthe Microprocessor WriteSection. Active

High.

SYNCIN2 I FIR/TimingNCO Update/AGC Gain Update Sync. Can be used to synchronize the FIR, Timing NCO update, AGC

gain update, or any combination of the above. Seethe MultipleChip SynchronizationSection andControl Words 7,

8, and 10 in the Microprocessor Write Section. Active High.

SYNCOUT O Strobe Output. This synchronization signal is generated by the µP interface for synchronizing multiple parts. Can

be generated by PROCLK orCLKIN (seeControl Word 0 andControl Word 24 inthe Microprocessor WriteSection).

Active High.

3-6

Page 55

ERROR

DETECT

LOOP

FILTER

LIMIT

POLAR

CARTESIAN

HSP50214B

AOUT(15:0)

BOUT(15:0)

OEAH

OEAL

OEBH

INTRRP

DATARDY

QI----





POLYPHASE

atan

BY 2/4

FILTERS

HALFBAND

INTERPOLATE

RE-SAMPLER

FILTER

OEBL

INTRRP

OUTPUT FORMATTER

DISCRIMINATOR

FILTER

POLYPHASE

SEROUTA

SEL(2:0)

63-TAP

FIR FILTER

PROGRAMMABLE

dθ

SEROUTB

SERCLK

SERSYNC

SEROE

AGCOUT

TIMING ERROR

DIFFERENCE

MSYNCI

SYNCOUT

CHIP

CIRCUITRY

SYNCHRONIZATION

CLKIN

MSYNCO

BACK END

PROCCLK

SYNCIN2

CIRCUITRY

SYNCHRONIZATION

SYNCIN1

CIRCUITRY

FRONT END

SYNCHRONIZATION

AGCOUT

AND MICROPROCESSOR

TO OUTPUT FORMATTER

PROCCLK

AGCGNSEL

INTERFACE

CLKIN

ENI

SHIFT

= 1;

SECTION

INPUT

= 0)

255-TAP

5TH ORDER

AGC

FIR FILTER

PROGRAMMABLE

(DECIMATE UP TO 16)

DECIMATION UP TO 32

0 TO 5 HALFBAND FILTER;

CIC

DECIMATE

FROM 4-32

MIXER

DETECT

LEVEL

INTERFACE

µPROCESSOR

SHIFT

= 1;

COS

SIN

= 0)

COF

NCO

(SYMBOL TRACKING)

(CARRIER TRACKING)

COFSYNC

NCO

SOF

SOFSYNC

REFCLK

OUTPUT SECTION

DISCRIMINATOR SECTION

READ/WRITE

MICROPROCESSOR

CARRIER NCO SECTIONS

INPUT SECTION

SYNCHRONIZATION SECTION

LEVEL DETECT SECTION

SECTION

CONTROL

A(2:0)

CIC, HALFBAND FILTER, AND FIR SECTIONS

DIGITAL AGC SECTION

RE-SAMPLER/INTERPOLATION HALFBAND SECTION

TIMING NCO

FIGURE 1. FUNCTIONAL BLOCK DIAGRAM OF THE HSP50214B PROGRAMMABLE DOWNCONVERTER

C(7:0)

GAINADJ(2:0)

3-7

IN(13:0)

Page 56

HSP50214B

Functional Description

The HSP50214BProgrammableDownconverter (PDC)is an agile digital tuner designed to meet the requirements of a wide variety of communications industry standards. The PDC contains the processing functions needed to convert sampled IF signals to baseband digital samples. These functions include LO generation/mixing,decimation ﬁltering, programmable FIR shaping/bandlimiting ﬁltering, resampling, Automatic Gain Control (AGC), frequency discrimination and detection as well as multi-chip synchronization. The HSP50214B interfaces directly with a DSP microprocessor to pass baseband and status data.

A top level functional block diagram of the HSP50214B is shown inFigure 1. The diagramshows the major blocks and multiplexers used to reconﬁgure the data path for various architectures. The HSP50214B can be broken into 13 sections: Synchronization, Input, Input Level Detector, Carrier Mixer/Numerically Control Oscillator (NCO), CIC Decimating Filter, Halfband Decimating Filter, 255-Tap Programmable FIR Filter, Automatic Gain Control (AGC), Re-sampler/Halfband Filter, Timing NCO, Cartesian to Polar Converter, Discriminator, and Output Sections. All of these sections are conﬁgured through a microprocessor interface.

The HSP50214Bhas three clockinputs; two arerequired and one isoptional. Theinput leveldetector,carrier NCO,and CIC decimating filter sections operate on the rising edge of the input clock, CLKIN. The halfband filter, prog r ammable FIR filter, A GC, Re-Sampler/Halfband filters, timing NCO, discriminator, and output sections operate on the rising edge of PROCCLK. The third clock, REFCLK, is used to generate timing error information.

NOTE: All of the clocks may be asynchronous.

PDC Applications Overview

This section highlights the motivation behind the key programmable features from a comm unications system le vel perspective.These motiv ationswill bedefined in terms ofability to provide DSP processing capability for specific modulation formats and communication applications. The versatility of the Programmable Downcon v erter can be intimidating because of the many Control Words required f or chip configuration. This section provides system level insight to help allay reservations about this versatile DSP product. It should help the designer capitalize on the greatest feature of the PDC -VERSATILITY THROUGH PROGRAMMABILITY. It is this feature, when fully understood, that brings the greatest return on design investmentby offering asingle receiverdesign thatcan process the many wav ef orms required in the communications marketplace.

FDM Based Standards and Applications

Table 1 provides an ov erview of some common frequency division multiplex (FDM)base stationapplications towhich the PDC can be applied. The PDC provides excellent selectivity

for frequency division multiple access (FDMA) signals. This high selectivity isachieved with 0.012Hz resolution frequency control of the NCO and the sharp filter responses capable with a 255-tap, 22-bit coefficient FIR filter. The 16-bit resolution out of the Cartesian to Polar Coordinate Converter are routed to the frequency detector, which is f ollowed by a 63-tap, 22-bit coefficient FIR filter structure for f acilitating FM and FSK detection. The 14-bit input resolution is the smallest bit resolution found throughout the conv ersion and filtering sections, providing excellent dynamic range in the DSP processing. A unique input gain scaler adds an additional 42dB of range to the input level variation, to compensate for changes in the analog RF front end receive equipment. Synchronization circuitry allows precise timing control of the base station reconfiguration for all receive channels simultaneously. Portions of this table were corroborated with reference [2].

TABLE 1. CELLULAR PHONE BASE STATION APPLICA-

TIONS USING FDMA

NMT-

400

STANDARD

RX BAND

(MHz)

CHANNEL

BW (kHz)

# TRAFFIC

CHANNELS

VOICE

MODULA-

TION

PEAK

DEVIA TION

(kHz)

CONTROL

MODULA-

TION

PEAK

DEVIA TION

(kHz)

CONTROL CHANNEL

RA TE

(Kbps)

AMPS

(IS-91)

824-849 925-940 453-458

FSK FSK FSK FSK FSK

MCS-L1 MCS-L2

30 25.0

12.5

832 600

1200

FM FM FM FM FM

12 5 5 4 9.5

8 4.5 3.5 2.5 6.4

10 0.3 1.2 5.3 8

NMT-

900 C450

451-456 871-904

890-915

12.5 200

1999

20.0

10.0 222

444

ETACS NTACS

915-925

25.0

12.5

1240

800

TDM Based Standards and Applications

Table 2provides an overviewof some common TimeDivision Multiplexed(TDM) basestation applicationsto which the PDC can be applied. For time division multiple access (TDMA) applications, such as North American TDMA (IS136), where 30kHz is the received band of interest for the PCS basestation, the PDC offers 0.012Hz frequency resolution in downconversion in addition toα = 0.35 matched (programmable) filtering capability. The π/4 DPSK modulation can be processed using the PDC Cartesian to Polar coordinate converter and dφ/dt detector circuitry or by

3-8

Page 57

HSP50214B

processing theI/Q samples inthe DSP µP. The PDC provides the ability to change the received signal gain and frequency, synchronous with burst timing. The synchronous gain adjustment allo wsthe userto measurethe powerof thesignal at theA/D atthe endof a burst, and synchronously reload that same gain value at the arrival of the next user burst.

For applications other than cellular phones (where the preambles are not changed), the PDC frequency discriminator output canbe used to obtaincorrelation on the preamble pattern to aid in burst acquisition.

TABLE 2. CELLULAR BASESTATION APPLICATIONS USING

TDMA

STANDARD GSM PCN IS-54

TYPE Cellular Cellular Cellular

BASESTATION RX

BAND (MHz)

CHANNEL BW (kHz) 200 200 30

# TRAFFIC CHANNELS 8163

VOICE MODULATION GMSK GMSK π/4

CHANNEL RATE (Kbps) 270.8 270.8 48.6

CONTROL

MODULATION

CHANNEL RATE (Kbps) 270.8 270.8 48.6

935-960 1805-1880 824-849

DQPSK

GMSK GMSK π/4

DQPSK

Severalapplications are combinations of frequencyand time domain multiple access schemes. For example, GSM is a TDMA signal that is frequency hopped. The individual channels contain Gaussian MSK modulated signals. The PDC again offers the 0.012Hz tuning resolution for dehopping the received signal. The combination of halfband and 256-tap programmable, 22-bit coefﬁcient FIR ﬁlters readily performs the necessary matched ﬁltering for demodulation and optimum detection of the GMSK signals.

CDMA Based Standards and Applications

For CodeDivision Multiple Access (CDMA) type signals, the PDC offers the ability to have a single wideband RF front end, from which it can select a single spread channel of interest. The synchronization circuitry provides for easy control of multiple PDC for applications where multiple received signals are required, such as base-stations.

In IS-95 CDMA, the receive signal bandwidth is approximately 1.2288MHz wide with many spread spectrum channel in the band. The PDC supplies the downconversion and ﬁltering required to receive a single RF channel in the presence of strong adjacent interference. Multiple PDC’s would be sourced from a single receive RF chain, each processing a different receive frequency channel. The despreader would usually follow the PDC. In some very speciﬁc applications,with short, ﬁxed codes,the ﬁltering and despreading may be possible with innovative use of the programmable, 22-bit coefﬁcient FIR ﬁlter. The PDC offers

0.012Hz resolution on tuning to the desired receive channel

and excellent rejection of the portions of the band not being processed, via the halfband and 255-tap programmable, 22bit coefﬁcient FIR ﬁlter.

Traditional Modulation Formats

AM, ASK, FM AND FSK

The PDC has the capability to fully demodulate AM and FM modulated waveforms.The PDCoutputs 15bits ofamplitude or 16 bits of frequency for these modulation formats. The FM discriminator hasa 63-tapprogrammable,22-bit coefficientFIR filter for additional signal conditioning of the FM signal. Digital versions of these formats, ASK and FSK are also readily processed using the PDC. Just as in the AM modulated case, ASK signals will use 15-bit magnitude output of the Cartesian to Polar Coordinate converter. Multi-tone FSK can be processed several w a ys . The frequency information out of the discriminator can be used to identify the received tone, or the filter canbe used toidentify and pow erdetect a specifictone of the received signal. AMPS is an example of an FM application.

PM AND PSK

The PDC provides the downconversion, demodulation, matched ﬁltering and coordinate conversion required for demodulation of PM andPSK modulated waveforms. These modulation formats will require external carrier and symbol timing recovery loop ﬁlters to complete the receiver design. The PDC was designed to interface with the HSP50210 Digital Costas Loop to implement the carrier phase and symbol timing recovery loop ﬁlters (for continuous PSK signals - not burst).

Digital modulation formats that combine amplitude and phase for symbol mapping, such asm-ary QAM,can also be downconverted, demodulated, and matched ﬁltered. The received symbol information is provided with 16 bits of resolution in either Cartesian or Polar coordinates to facilitate remapping into bits and to recover the carrier phase. External Symbol mapping and Carrier Recovery Loop Filtering is required for this waveform.

Resampling and Interpolation Filters

Two key features of the resampling FIR ﬁlter are that the resampler ﬁlter allows the output sample rate to be programmed with millihertz resolution and that the output sample rate can be phase locked to an independent separate clock. The re-sampler frees the front end sampling clocks from having to be synchronous orintegrally related in rate to the baseband output. The asynchronous relationship between front end and back end clocks is critical in applications where ISDN interfaces drive the baseband interfaces, but the channel sample rates are not related in any way. The interpolation halfband ﬁlters can increase the rate of the output when narrow frequency bands are being processed. The increase in output rateallows maximum use of the programmable FIR while preserving time resolution in the baseband data.

3-9

Page 58

HSP50214B

14-Bit Input and Processing Resolution

The PDC maintains a minimum of 14 bits of processing resolution through to the output, providing over 84dB of dynamic range. The 18 bits of resolution on the internal referencesprovide a spuriousﬂoor that isbetter than98dBc. Furthermore, the PDCprovides upto 42dB of gain scalingto compensate for any change in gain in the RF front end as well as up to 96dB of gain in the internal PDC AGC. This gain maximizes the output resolution for small signals and compensates for changes in the RFfront end gain, to handle changes in the incoming signal.

Summary

The greatest feature of the PDC is its ability to be reconﬁgured to process many common standards in the communications industry. Thus, a single hardware element can receive and process a wide variety of signals from PCS to traditional cellular, from wireless local loop to SATCOM. The high resolution frequency tuning and narrowband ﬁltering are instrumental in almost all of the applications.

Multiple Chip Synchronization

Multiple PDCs are synchronized using a MASTER/SLAVE conﬁguration. One part is responsible for synchronizing the front end internal circuitry using CLKIN while another part is responsible for synchronizing the backend internal circuitry using PROCCLK.

The PDC issynchronized with other PDCsusing ﬁve control lines: SYNCOUT, SYNCIN1, SYNCIN2, MSYNCO, and MSYNCI. Figure 2 shows the interconnection of these ﬁve signals for multiple chip synchronization where different sources are used for CLKIN and PROCCLK.

PDC A is the Master sync through MSO. PDC B conﬁgures the CLKIN sync through SYNCIN1. PDC A conﬁgures the PROCCLK sync through SYNCIN2.

HSP50214B

MSYNCO

MSYNCI

(MASTER

SYNCIN2)

SYNCOUT

SYNCIN2

SYNCIN1

FIGURE 2. SYNCHRONIZATION CIRCUIT

SYNCOUT for PDC B should be set to be synchronous with CLKIN (Control Word 0, Bit 3 = 0. See the Microprocessor Write Section). SYNCOUT for PDC B is tied to the SYNCIN1 of all the PDCs. The SYNCIN1 can be programmed so that

HSP50214B

MSYNCO

MSYNCI

SYNCOUT

SYNCIN2

SYNCIN1

ALL OTHER SYNCIN1 ALL OTHER SYNCIN2 ALL OTHER MSI

(MASTER SYNCIN1)

the carrierNCO and/or the5th orderCIC filter ofall PDCscan be synchronously loaded/updated using SYNCIN1. See Control Word 0, Bits 19 and 20 in the Microprocessor Write Section for details.

SYNCOUT for one of the PDC’s other than PDC B, should be set for PROCCLK (bit 3 = 1 in Control Word 0). This output signal is tied to the SYNCIN2 of all PDCs. The SYNCIN2 can be programmed so that the AGC updates its accumulator with the contents in the master registers (Control Word 8,Bit 29 in the MicroprocessorWrite Section). SYNCIN2 is also used to load or reset the timing NCO using bit 5, Control Word 11. The halfband and FIR ﬁlters can be reset on SYNCIN2 using Control Word 7, Bit 21. The MSYNCO of one of the PDCs is then used to drive the MSYNCI of all the PDCs (including its own).

For application conﬁgurations where CLKIN and PROCCLK have the same source, SYNCIN1 and SYNCIN2 can be tied together.However, ifdifferent enabling isdesired forthe front end andbackendprocessing of the PDC’s,these signalscan still be controlled independently.

In the HSP50214B, the Control Word 25 reset signal has been extended so that the front end reset is 10 CLKIN periods wide and the back end reset is 10 PROCCLK periods wide.This guaranteesthat no enableswill becaught in the pipelines. In addition, the SYNCIN1 internal reset signal, which is enabled by setting Control Word 7, Bit 21 = 1, has been extended to 10 cycles.

In summary, SYNCIN1 is used to update carrier phase offset, updatecarrier center frequency, reset CICdecimation counters and reset the carrier NCO (clear the feedback in the NCO). SYNCIN2 is used to reset the HB ﬁlter, FIR ﬁlter, re-sampler/HB state machines and the output FIFO, load a new gain into the AGC and load a new re-sampler NCO center frequency and phase offset.

Input Section

The block diagram of the input controller is provided in Figure 3. The input can support offset binary or two’s complement data and can be operated in gated or interpolated mode (see Control Word 0 from the Microprocessor Write Section). The gated mode takes one sample per clock when the input enable (ENI) is asserted. The gated modeallows the user to synchronize a low speed sampling clock to a high speed CLKIN.

The interpolated mode allows the user to input data at alow sample rate and to zero-stuff the data prior to ﬁltering. This zero stufﬁngeffectivelyinterpolates theinput signal upto the rate of the input clock (CLKIN). This interpolated mode allows the part to be used at rates where the sampling frequency is above the maximum input rate range of the halfband ﬁlter section, and where the desired output bandwidth is too wide to use a Cascaded Integrator Comb (CIC) ﬁlter without signiﬁcantly reducing the dynamic range.

3-10

Page 59

HSP50214B

See Figures 4-7 for an interpolated input example, detailing the associated spectral results.

Interpolation Example:

The speciﬁcations for the interpolated input example are: CLKIN = 40MHz

Input Sample Rate = 5 MSPS PROCCLK = 28MHz Interpolate by 8, Decimate by 10 Desired 85dB dynamic range output bandwidth = 500kHz

Input Level Detector

The Input Level Detector Section measures the average magnitude errorat the PDCinput for themicroprocessor by comparing the input level against a programmable threshold and then integrating the result. It is intended to provide a gain error for use in an AGC loop with either the RF/IF or A/D converter stages (see Figure 8). The AGC loop includes Input Level Detector,the microprocessor and an external gain control amplifier (or attenuator). The input samples are rectified and added to a threshold

INPUT LEVEL DETECTOR † STATUS (0) †

LEVEL

DETECT

IN(13:0)

FORMAT

INPUT

†

GAINADJ(2:0)

REG

INPUT FORMAT

REG

NCO††

INPUT_THRESH † INTG_MODE † INTG_INTEVAL †

REGREG

DELAY 3

programmed via the microprocessor interface, as shown in Figure 9. The bit weighting of the data path through the input threshold detector is shown in Figure 10. The threshold is a signed number, so it should be set to the inverse of the desired input level. The threshold can be set to zero if the average input level is desired instead of the error. The sum of the threshold and the absolute value of the input is accumulated in a 32-bit accumulator. The accumulator can handle up to 2

samples without overflow. The integration time is controlled by an 18-bit counter. The integration counter preload (ICPrel) is programmed via the microprocessor interface through Control Word 1. Only the upper 16 bits are programmable. The 2 LSBs are always zero. Control Word 1, Bits 29-14 are programmed to:

ICPrel N()41+⁄=

(EQ. 1)

where N is the desired integration period, deﬁned as the number of input samples to be integrated. N must be a

multiple of 4: [0, 4, 8, 12, 16 .... , 2

MUX

SHIFT

LIMIT

BYPASS †

CIC

∑

ENI

INTERP †

CONTROL WORD 0 CONTROL WORD 1

CLKIN

CONTROL

LOGIC

INPUT_MODE † INPUT_FMT † INPUT_THRESH† INTG_MODE† INTG_INTEVAL†

FIGURE 3. BLOCK DIAGRAM OF THE INPUT SECTION

5MHz

CLKIN = 5MHz

BYPASS

CIC

FILTER

MIN. R = 4

PROCCLK = 28MHz

HB/FIR FILTER

MUX

MAX. fS = 4MHz

(EXCEEDED IN

BYPASS PATH)

500kHz = 85dB

BANDWIDTH (NOT ACHIEVED WITH CIC FILTER PATH)

Without Interpolation, the CIC bypass path exceeds the HB/FIR ﬁlter input sample rate and the CIC ﬁlter path will not yield the desired 85dB dynamic range band width of 500kHz.

FIGURE 4. STATEMENT OF THE PROBLEM

3-11

DELAY 3

† Controlled via microprocessor interface.

††See NCO Section for more details.

↑8 (0 STUFF) = 40MHz

5MHz

CLKIN = 40MHz

CIC FILTER

R = ↓10

FIGURE 5. BLOCKDIAGRAMOF THEINTERPOLATION

APPROACH

4MHz

HB/FIR FILTER

500kHz = 85dB BANDWIDTH

Page 60

HSP50214B

5MHz 10MHz 15MHz 20MHz 25MHz 30MHz 35MHz 40MHz 45MHz 50MHz

5MHz 10MHz 15MHz 20MHz 25MHz 30MHz 35MHz 40MHz

THE INPUT DATA SPECTRUM SAMPLED AT RATE R = f

f’S/2f’S/4f’S/8 3f’S/8 5f’S/8 7f’S/83f’S/4

f’

10f

FIGURE 6. INTERPOLATION SPECTRUM: INTERPOLATE BY 8 THE INPUT DATA WITH ZERO STUFFING; SAMPLE AT RATE R = f’s

8MHz 12MHz 16MHz 20MHz 24MHz 28MHz 32MHz 36MHz 40MHz

4MHz

DECIMATE BY 10 AND CIC FILTER; SAMPLE AT RATE R = f’s/10

85dB DYNAMIC RANGE BANDWIDTH

4MHz2MHz1MHz 3MHz

CIC FILTER FREQUENCY RESPONSE

CIC FILTER ALIAS PROFILE

O.5MHz

FIGURE 7. ALIAS PROFILE AND THE 85dB DYNAMIC RANGE BANDWIDTH

INPUT

µPROC

DAC

GCA

A/D

INPUT LEVEL DETECTOR (24-BIT ERROR VALUE)

THRESH

PDC

FIGURE 8. PROCESSOR BASED EXTERNAL IF AGC

3-12

Page 61

HSP50214B

INPUT

IN(13:0)

GATING

|X|

LOGIC

INPUT_THRESHOLD †

R E G

INTEGRATION_INTERVAL†

START †

INTEGRATION_MODE†

COUNTER

CLKIN

CONTINUOUS SINGLE

ACCUMULATOR

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

-11

-12

-13

µPROC READ

-1

-2

-3

-4

-6dB

-12dB

-18dB

-24dB

-30dB

-36dB

-42dB

-48dB

-54dB

-60dB

-66dB

-72dB

-78dB

† Controlled via microprocessor interface.

A/D

OUTPUT

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

-11

-12

-13

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

-11

-12

-13

INPUT

MAGNITUDE

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

-11

-12

-13

THESHOLD

-2

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

-11

-12

-13

FIGURE 10. INPUT THRESHOLD DETECTOR BIT WEIGHTING

ACCUMULATOR

+ +

CLKIN

“0”

FIGURE 9.

The integration period counter can be set up to run continuously orto countdown and stop. Continuous integration counter operation lets the counter run, with sampling occurring every time the counter reaches zero . Because the processor samples the detector read port asynchronous to the CLKIN,

READ CODE A(2:0)

PORTS

data can be missed unless the status bit is monitored by the processor toensure that asample is taken forevery integration count down sequence.

Additionally, in the HSP50214B, the ability to align the start/restart of the input level detector integration period with an external event is pro vided. This allo ws the sync signals, which aresynchronized to external events,to be used to align all of the gain adjustments or measurements. If Control Word 27, Bit 17is set to alogic one, the SYNCIN1signal will cause the input level detector to start/restart its integration period. If Control Word 27, Bit 17 is set to a logic zero, control of the start/restart of the input level detector integration period does not respond to SYNCIN1.

In the count down and stop mode, the microprocessor read commands canbe synchronized to system ev ents ,such as the

000 010001

start of a burst for a TDMA application. The integration counter can be started at any time by writing to Control Word 2. At the end of the integr ationperiod (counter= 0000),the upper23 bits of the accumulator are transferred to a holding register f or reading by the microprocessor. Note that it is not the restarting of the counter (by writing to Control Word 2) that latches the current value, but the end of the integr ation count. When the accumulator results are latched, a bit is set in the Status Register to notify the processor. Reading the most significant byte of the 23 bits clears thestatus bit. Seethe Microprocessor Read Section. Figure 11 illustrates a typical AGC detection process.

ADDR(2:0)

R E G

R E

U X

TO µPROC

3-13

Page 62

HSP50214B

Typically, the average input error is read fromthe Input Level Detector port for use in AGC Applications. By setting the threshold to0, however,the averagevalue ofthe input signal can be read directly. The calculation is:

dBFS

RMS

20() 1.111()level()N()16()()⁄[]log=

(EQ. 2)

where “level” is the 24-bit value read from the 3 level Detector Registers and “N” is the number of samples to be integrated. Note that to get the RMS value of a sinusoid, multiply the average value of the rectiﬁed sinusoid by 1.111. For a full scale input sinusoid, this yields an RMS value of approximately 3dBf

NOTE: 1.111 scales the rectiﬁed sinusoid average (2/π) to 1/√2

A) INPUT SIGNAL

AMPLITUDE

C) THRESHOLD

AMPLITUDE

E) DETECTOR OUTPUT

AMPLITUDE

FIGURE 11. SIGNAL PROCESSING WITHIN LEVEL DETECTOR

B) RECTIFIED SIGNAL

AMPLITUDE

D) ACCUMULATOR INPUTS

AMPLITUDE

F) CLOSED LOOP STEADY STATE

(CONSTANT INPUT)

AMPLITUDE

In the HSP50214B, the polarity of the LSB’s of the integration period pre-load is selectable. If Control Word 27, Bit 23 is set to a logic one, the two LSB’s of the integration period preload are set to logic ones. This allows a power of two to be set for the integration period, for easy normalization in the processor. If Control Word 27, Bit 23 is set to a logic zero, then the two LSB’s of the integration period preload are set to zeros as in the HSP50214.

Carrier Synthesizer/Mixer

The Carrier Synthesizer/MixerSection of the HSP50214B is shown in Figure 12. The NCO has a 32-bit phase accumulator, a 10-bit phase offset adder, and a sine/cosine ROM. The frequency of the NCO is the sum of a center frequency Control Word, loaded via the microprocessor interface (Control Word 3, Bits 0 to 31), and an offset frequency, loaded serially via the COF and COFSYNC pins. The offset frequencycan be zeroed inControl Word 0,Bit 1. Both frequency control terms are 32 bits and the addition is

modulo 2

. The output frequency of the NCO is computed

as:

fCfS* N 232()⁄ ,=

(EQ. 3)

or in terms of the programmed value:

NINTfC232fS⁄×[]

HEX

(EQ. 3A)

where N is the 32-bit sum of the center and offset frequency terms, f

is the frequencyof the carrier NCO sinusoids,fSis

the input sampling frequency, and INT is the integer of the computation. See the Microprocessor Write Section on instructions for writing Control Word 3.

TO MIXERS

PHASE

ACCUMULATOR

ENI

18 18

REG REG

SIN/COS

ROM

REG

SINCOS

CARRIER

PHASE

†

STROBE

MUX

CARRIER

PHASE

R E G

OFFSET

†

CLEAR PHASE

ACCUM

†

COF

ENABLE†

COFSYNC

COF

SYNCIN1

MUX

COF

REG

SYNC REG

SHIFT REG

SYNC

CIRCUITRY

REG

CARRIER

FREQUENCY

STROBE

CARRIER FREQUENCY (fC)

†

CARRIER LOAD ON

UPDATE

†

† Controlled via microprocessor interface.

FIGURE 12. BLOCK DIAGRAM OF NCO SECTION

Forexample, ifN is3267 (decimal), and f

is 65MHz,then f

is 49.44Hz. If received data is modulated at a carrier frequency of 10MHz, then the synthesizer/mixer should be programmed for N = 27627627 (hex) or D89D89D8 (hex).

Because the input enable, ENI, controls the operation of the phase accumulator, the NCO output frequency is computed relative to the input sample rate, f

, not to f

CLKIN

. The frequency control, N, is interpreted as two’s complement because the output of the NCO is quadrature. Negative frequency L.O.s selectthe uppersideband; positivefrequency L.O.s select the lower sideband. The r ange of the NCO is

-f

/2 to+fS/2. Thefrequency resolutionof theNCO isfS/(232)

or approximately 0.015Hz when CLKIN is 65 MSPS and ENI is tied low .

†

3-14

Page 63

HSP50214B

The phase of the Carrier NCO can be shifted by adding a 10-bit phaseoffset to the MSB’s (modulo 360o) ofthe output of the phase accumulator. This phase offset control has a resolution of 0.35oand can be interpreted as two’s complement from -180oto 180

to 360

(0to2π). The phase offset is given by:

2π PO 210⁄()× 29()PO 291–()≤≤–();=

OFF

512 to 511–()

(-π toπ) or as binary from 0

(EQ. 4)

or, in terms of the parameter to be programmed:

PO INT 2

()2π⁄]

OFF

HEX

π– φ

OFF

π<<();[=

(EQ. 4A)

where PO is the 10-bit two’s complement v alue loaded into the Phase Offset Register (Control Word4, Bits 9-0). For example, a value of 32 (decimal) loaded into the Phase Offset Register would produce a phase offset of 11.25 would produce an offsetof 180

. Thephase offsetis loadedvia

and a value of -512

the microprocessor interface. See the Microprocessor Write Section on instructions for writing Control Word 4.

The most signiﬁcant 18 bits from the phase adder are used as the address a sin/cos lookup table. This lookup table maps phase into sinusoidal amplitude. The sine and cosine values have 18 bits of amplitude resolution. The spurious components in the sine/cosine generation are at least

-102dBc. The sine and cosine samples are routed to the mixer section where they are multiplied with the input samples to translate the signal of interest to baseband.

The mixermultiplies the 14-bitinput by the18-bit quadrature sinusoids. The mixer equations are:

OUTIIN

ωc()cos×=

ωc()sin×=

(EQ. 5)

(EQ. 5A)

The mixer output is rounded symmetrically to 15 bits. To allow the frequency and phase of multiple parts to be

updated synchronously, two sets of registers are used for latching the center frequency and phase offset words. The offset phase and center frequency Control Words are first loaded into holding registers. The contents of the holding registers are transferred to active registers in one of two w ays. The first technique involves writing to a specific Control W ord Address. A processor write to Control Word 5, transfers the center frequency value to the active register while a processor write to Control Word 6 transfers the phase offset v alue to the active register .

The second technique, designed for synchronizing updates to multiple parts, uses the SYNCIN1 pin to update the active registers.When ControlWord 1,Bit 20 isset to1, theSYNCIN1 pin causes boththe centerfrequency andPhase Offset Holding Registers to be transferred to active registers . Additionally, when Control Word 0, Bit 0 is set to 1, the feedbac k in the phase accumulator is zeroed when the transfer from the holding to active register occurs. This feature pro vides

synchronization of the phase accumulator starting phase of multiple parts. It can also be used to reset the phase of the NCO synchronous with a specific event.

The carrier offset frequency is loaded using the COF and COFSYNC pins. Figure 13 details the timing relationship between COF, COFSYNC and CLKIN. Theoffset frequency word can be zeroed if it is not needed. Similarly, the Sample Offset Frequency Register controlling the ReSampler NCO is loaded via the SOF and SOFSYNC pins. The procedure for loading data through the two pin NCO interfaces is identical except that the timing of SOF and SOFSYNC is relative to PROCCLK.

CLKIN

COFSYNC/

SOFSYNC

COF/

SOF

OTE: Data must be loaded MSB first.

IGURE 13. SERIAL INPUT TIMING FOR COF ANDSOF INPUTS

MSB

LSB

MSB

Each serialword hasa programmableword widthof either 8, 16, 24, or 32 bits (See Control Word 0, Bits 4 and 5, for the Carrier NCO programming and Control Word 11, Bits 3 and 4, for Timing NCO programming). On the rising edge of the clock, data on COF or SOF is clocked into an input shift register. The beginning of a serial word is designated by asserting either COFSYNC or SOFSYNC “high” one CLK period prior to the ﬁrst data bit.

32†

30 28 26

22 20

14 12 10

SHIFT COUNTER VALUE

†

6 4 2 0

ASSERTION OF

COFSYNC, SOFSYNC

DATA TRANSFERRED

TO HOLDING REGISTER

(8)

CLK TIMES

(24)

(16)

(32)

54504642383430262218141062

††

†Serial word width can be: 8, 16, 24, 32 bits wide. †T

is determined by theCOFSYNC, COFSYNC rate.

FIGURE 14. HOLDINGREGISTERS LOAD SEQUENCE FOR

COF AND SOF SERIAL OFFSET FREQUENCY DAT A

NOTE: Serial Data mustbe loaded MSBfirst, and COFSYNCor

SOFSYNC should not be asserted for more than one CLK cycle.

3-15

Page 64

HSP50214B

NOTE: COF loading and timing is relative to CLKIN while SOF

loading and timing is relative to PROCCLK.

NOTE: TD can be 0, and the fastest rate is with 8-bit word width.

The assertionof the COFSYNC(or SOFSYNC)starts acount down from the programmed word width. On f ollo wing CLKs, data is shifted into the register until the specified number of bits have been input. At this point the contents of the register are transf erredfrom the Shift Registerto the respective 32-bit Holding Register. The Shift Register can accept new data on the follo wingCLK. If the serial input word is defined tobe less than 32 bits, it will be transferred to the MSBs of the 32-bit Holding Registerand the LSBs ofthe Holding Registerwill be zeroed. See Figure 14 for details.

CIC Decimation Filter

The mixer outputmay be filtered with the CICfilter orit may be routed directly to the halfband filters. The CIC filter is used to reduce the sample rate of awideband signal to arate that the halfbands and programmable filters can process, giv en the maximum computation speed of PROCCLK. (See Halfband and FIR Filter Sections for techniques to calculate this value).

Prior to the CIC ﬁlter, the output of themixer goes through a barrel shifter. The shifter is used to adjust the gain in 6dB steps to compensate for the variation in CIC ﬁlter gain with decimation. (See Equation 6). Fine gain adjustments must be done in the AGC Section. The shifter is controlled by the sum of a 4-bit CIC Shift Gain word from the microprocessor and a3-bit gainword fromthe GAINADJ(2:0) pins. Thethree bit value is pipelined to matchthe delayof theinput samples. The sum of the 3 and 4-bit shift gain words saturates at a value of 15. Table 1 details the permissible values for the GAINADJ(2:0) barrel shifter control, while Figure 15 shows the permissible CIC Shift Gain values.

The CICﬁlter structure forthe HSP50214B isﬁfth order; that is it has ﬁve integrator/comb pairs. A ﬁfth order CIC has 84dB of alias attenuation for output frequencies below 1/8 the CIC output sample rate.

15 14 13 12 11 10

9 8 7 6 5 4 3 2

CIC SHIFT GAIN (FROM PROCESSOR)

1 0

812202836445260

FIGURE 15. CIC SHIFT GAIN VALUES

8-BIT INPUT 10-BIT INPUT 12-BIT INPUT 14-BIT INPUT

164403224 645648

DECIMATION (R)

ALLOWABLE CIC SHIFT GAINS ARE BELOW THE CURVES

The decimation factor of the CIC filter is programmed in Control Word 0, Bits 12 - 7. The CIC Shift Gain is programmed in Control Word 0, Bits 16-13. The CIC Bypass is set in Control Word 0, Bit 6. When bypassing the CIC filter, the

ENI signal must be de-asserted between samples, i.e.,

the CLKIN rate must be ≥2 • f

TABLE 3. GAIN ADJUST CONTROL AND CIC DECIMATION

∆GAIN VALUE

(dB) GAIN ADJ(2:0)

0 000 32

6 001 27 12 010 24 18 011 21 24 100 18 30 101 16 36 110 12 42 111 10

MAX. CIC

DECIMATION

CIC Gain Calculations

The gain through the CIC ﬁlter increases with increased decimation. The programmable barrel shifter that precedes the ﬁrst integrator in the CIC is used to offset this variation. Gain variations dueto decimation should be offsetusing the 4-bit CICShift Gainword. Thisallows theinput signal level to be adjusted in 6dB steps to control the CIC output level.

The gain at each stage of the CIC is:

kRN,=

where R is the decimation factor andN isthe numberof stages. The inputto theCIC fromthe mixeris 15bits, andthe bit widths of the accumulators for the five stages in the HSP50214B are 40, 36, 32, 32, and 32, as shown in Figure 16. This limits the maximum decimation in the CIC to 32 for a full scale input.

If R is32, thegain throughall fiveintegratorstages is32 (The gain through the last four CIC stages is 2 last 3 it is 2

, etc.). The sum of the input bits and the growth

bits cannot exceed the accumulator size. This means that for a decimation of 32 and 15 input bits, the first accumulator must be 15 + 25 = 40 bits.

Thus, the value of the CIC Shift Gain word can be calculated:

SG = FLOOR 39 -[ IIN()- log2(R)5for 4<R<32

for R = 4= 15

NOTE: The number ofinput bitsis IIN.(If the number ofbits into

the CIC ﬁlter is used, the value 40 replaces 39).

For 14 bits, Equation 7 becomes:

SG FLOOR 25 log

15= for R 4=

R()5]for 4 R 32<<–[=

(EQ. 6)

5=225

, through the

(EQ. 7)

(EQ. 8A)

3-16

Page 65

HSP50214B

For 12 bits, Equation 7 becomes:

SG FLOOR 27 log2R()5]for 5 < R < 40–[=

15= for 4 R 5≤≤

(EQ. 8B)

For 10 bits, Equation 7 becomes:

SG FLOOR 29 log2R()5]for 6 < R < 52–[=

for 4 R 6≤≤15=

(EQ. 8C)

For 8 bits, Equation 7 becomes:

SG FLOOR 31 log2R()5]for 9 < R < 64–[=

15= for 4 R 9≤≤

(EQ. 8D)

Figure 15is aplot of Equations 8A through8D.The 4-bit CIC Shift Gain word has a range from 0 to 15. The 6-bit Decimation Factor counter preload ﬁeld, (R-1), has a range from 0 to 63, limited by the input resolution as cited above.

Using the Input Gain Adjust Control Signals

The input gain offset control GAINADJ(2:0)) is provided to offset the signal gain through the part, i.e., to keep the CIC ﬁlter output level constant as the analog front end attenuation is changed. The gain adjust offset is 6dB per code, so the gain adjust range is 0 to 42dB. For example, if 12dB of attenuation is switched in at the receiver RF front end, a code of 2 would increase the gain at the input to the CIC ﬁlterup 12dB so that theCIC ﬁlter output would notdrop by 12dB. This ﬁxed gain adjust eliminates the need for the software to continually normalize.

One must exercise care when using this function as it can cause overﬂow in the CIC ﬁlter. Each gain adjust in the shifter from the gain adjust control signals is the equivalent of an extra bit of input. The maximum decimation in the CIC is reducedaccordingly.With a decimationof 32, all40 bits of the CIC are needed, so no input offset gain is allowed. As the decimation is reduced, the allowable offset gain increases. Table 3 shows the decimation range versus desired offsetgain range.Table 3 assumes thatthe CICShift Gain has been programmed per Equation 7 or 8A.

The CIC filter decimation counter can be loaded synchronous with other PDC chips, using the SYNCIN1 signal and the CIC External Sync Enable bit. The CIC external Sync Enable is set via Control Word 0, Bit 19.

activated by their respective bit location (15-20) in Control Word 7. Any combination of halfband ﬁlters may be used, or all may be bypassed.

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

-11

-12

-13

-14

-15

-16

-17

-18

-19

-20

-21

-22

-23

-24

-25

-26

-27

-28

-29

-30

-31

ACC5

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

-11

-12

-13

-14

-15

-16

-17

-18

-19

-20

-21

-22

-23

CIC

OUTPUT

ACC1

INPUT

0 2 2 2 2 2 2 2 2 2 2 2 2

OUTPUT SHIFTER BITS TAKEN WHEN CIC IS BYPASSED

2 2

INPUT

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

-11

-12

-13

-14

(SHFT=0)

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

-11

-12

-13

-14

(SHFT=15)

0 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

2 2 2 2 2 2 2 2

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

-11

-12

-13

-14

-15

-16

-17

-18

-19

-20

-21

-22

-23

-24

-25

-26

-27

-28

-29

-30

-31

-32

-33

-34

-35

-36

-37

-38

-39

ACC2

ACC3

ACC4

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

-11

-12

-13

-14

-15

-16

-17

-18

-19

-20

-21

-22

-23

-24

-25

-26

-27

-28

-29

-30

-31

-32

-33

-34

-35

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

-11

-12

-13

-14

-15

-16

-17

-18

-19

-20

-21

-22

-23

-24

-25

-26

-27

-28

-29

-30

-31

NOTE: If 14input bitsare notneeded, the gain adjust can be in-

creased by one foreach bitthat theinput isshifted down at the input. For example, if only 12 bits are needed, an offset range of 24dB is possible for a decimation of 24.

Halfband Decimating Filters

The Programmable Down Converter has ﬁve halfband ﬁlter stages, as shown in Figure 17. Each stage decimates by 2 and ﬁlters out half of the available bandwidth. The ﬁrst halfband, or HB1, has 7 taps. The remaining halfbands; HB2, HB3, HB4, and HB5; have 11, 15, 19, and 23 taps respectively. The coefﬁcients for thesehalfbands aregiven in Table 4. Figure 18 shows the frequency responseof each of the halfbandﬁlters with respect to normalizedfrequency,F Frequency normalization is with respect to the input sampling frequency of each ﬁlter section. Each stage is

3-17

FIGURE 16. CIC FILTER BIT WEIGHTING

Since each halfband ﬁlter section decimates by 2, the total decimation through the halfband ﬁlter is given by:

DECHB2N=

(EQ. 9)

where N = Number of Halfband Filters Selected (1 - 5).

Page 66

HSP50214B

HALFBAND

FILTER INPUT

FN = f

CONTROL WORD 7, BIT 15

= F

HB1

CONTROL WORD 7, BIT 16

= F

HB2

CONTROL WORD 7, BIT 17 FN = F

HB3

CONTROL WORD 7, BIT 18

= F

HB4

HALFBAND FILTER 5

HALFBAND FILTER 1

= fS OR fS/2

HB1

HALFBAND FILTER 2

= F

HB2

HB1

HALFBAND FILTER 3

1 F

= F

HB3

HB2

OR F

HB3

HALFBAND FILTER 4

1 F

= F

HB4

OR F

HB3

†

= f

HB2

†

HB1

†

-20

†

-40

-60

-80

MAGNITUDE (dB)

-100

-120

-6dB BANDWIDTH

HALFBAND FILTER 5 HALFBAND FILTER 4 HALFBAND FILTER 3 HALFBAND FILTER 2 HALFBAND FILTER 1

0.125 0.25 0.375 0.5

NORMALIZED FREQUENCY (FN)

FIGURE 18. HALFBAND FILTER FREQUENCY RESPONSE

ALIAS PROFILES

-20

-40

-6dB BANDWIDTH

CONTROL WORD 7, BIT 19

= F

OR F

HB4

HALFBAND FILTER OUTPUT

† Each halfband section decimates by 2.

FIGURE 17. BLOCKDIAGRAMOF HALFBAND FILTER

SECTION

-60 HALFBAND FILTER 5

-80

MAGNITUDE (dB)

-100

-120

HALFBAND FILTER 4 HALFBAND FILTER 3 HALFBAND FILTER 2 HALFBAND FILTER 1

0.125 0.25 0.375 0.5 NORMALIZED FREQUENCY (FN)

FIGURE 19. HALFBAND FILTER ALIAS CONSIDERATIONS

3-18

Page 67

HSP50214B

TABLE 4. HALFBAND FILTER COEFFICIENTS

COEFFICIENTS HALFBAND #1 HALFBAND #2 HALFBAND #3 HALFBAND #4 HALFBAND #5

C0 - 0.031303406 0.005929947 -0.00130558 0.000378609 -0.000347137 C1 0.000000000 0.000000000 0.000000000 0.000000000 0.000000000 C2 0.281280518 -0.049036026 0.012379646 -0.003810883 0.00251317 C3 0.499954224 0.000000000 0.000000000 0.000000000 0.000000000 C4 0.281280518 0.29309082 -0.06055069 0.019245148 -0.010158539 C5 0.000000000 0.499969482 0.000000000 0.000000000 0.000000000 C6 - 0.031303406 0.29309082 0.299453735 -0.069904327 0.03055191 C7 0.000000000 0.499954224 0.000000000 0.000000000 C8 -0.049036026 0.299453735 0.304092407 -0.081981659

C9 0.000000000 0.000000000 0.500000000 0.000000000 C10 0.005929947 -0.06055069 0.304092407 0.309417725 C11 0.000000000 0.000000000 0.500000000 C12 0.012379646 -0.069904327 0.309417725 C13 0.000000000 0.000000000 0.000000000 C14 -0.00130558 0.019245148 -0.081981659 C15 0.000000000 0.000000000 C16 -0.003810883 0.03055191 C17 0.000000000 0.000000000 C18 0.000378609 -0.010158539 C19 0.000000000 C20 0.00251317 C21 0.000000000 C22 -0.000347137

NOTE: While Halfband ﬁltersare typicallyselected startingwith thelast stage inthe ﬁlterchain togive themaximumalias free bandwidth,

a higherthroughput ratemay beobtained using other ﬁlter combinations. See ApplicationNote 9720, “Calculating Maximum Processing Rates of the PDC”.

Depending on the number of halfbands used, PROCCLK must operate at aminimum rateabovethe input sample rate, f

, tothe halfband. Thisrelationship depends onthe number

of multiplies for each of the halfband ﬁlter stages. The ﬁlter calculations take 3, 4, 5, 6, and 7 multiplies per input for HB1, HB2, HB3, HB4, and HB5 respectively. If we keep the assumption that f

is the input sampling frequency, then

Equation 10 shows the minimum ratio needed.

HB5

)]/2

(EQ. 10)

PROCCLK/fS

(6)(HB4)(2 (5)(HB3)(2 (4)(HB2)(2 (3)(HB1)(2

≥ ([(7)(HB5)(2

(HB4 + HB5) (HB3+HB4+HB5) (HB2+HB3+ HB4+HB5) (HB1+HB2+HB3+HB4+HB5)

where HB1 = 1 if this section is selected and 0 if it is bypassed;

HB2 = 1 if this section is selected and 0 if it is bypassed; HB3 = 1 if this section is selected and 0 if it is bypassed; HB4 = 1 if this section is selected and 0 if it is bypassed; HB5 = 1 if this section is selected and 0 if it is bypassed; T = number of Halfband Filters Selected. The range for T is from 0 to 5.

Examples of PROCCLK Rate Calculations

Suppose we enable HB1, HB3, and HB5. Using Figure 16, HB1= 1, HB3 = 1, and HB5 = 1. Since stage 2 and stage 4 are not used, HB2 and HB4 = 0. PROCCLK must operate faster than (7x2+5x4+3x8)/8 = 7.25 times faster than f

If allfive halfbands are used, then PROCCLK must operateat (7x2+6x4+5x8+4x16+3x32)/32 = 7.4375 times faster than f

255-Tap Programmable FIR Filter

The Programmable FIR ﬁlter can be used to implement real ﬁlters with even or odd symmetry, using upto 255 ﬁlter taps, or complex ﬁlters with up to 64 taps. The FIR ﬁlter takes advantage of symmetry in coefﬁcients by summing data samples that share a common coefﬁcient, prior to multiplication. In this manner, two ﬁlter taps are calculated per multiply accumulate cycle. Asymmetric ﬁlters cannot share common coefﬁcients, so only one tap per multiply accumulate cycle is calculated. The ﬁlter can be effectively bypassed by setting the coefﬁcient C coefﬁcients, C

= 0.

= 1 and all other

3-19

Page 68

HSP50214B

Additionally, the Programmable FIR ﬁlter provides for decimation factors, R, from 1 to 16. The processing rate of the Filter Compute Engine is PROCCLK. As a result, the frequency of PROCCLK must exceed a minimum value to ensure thata ﬁlter calculation is completebefore theresult is required for output. In conﬁgurations which do not use decimation, one input sample period is available for ﬁlter calculation before an output is required. For conﬁgurations which employ decimation, up to 16 input sample periods may be available for ﬁlter calculation.

For real filter configurations, use Equation 11 to calculate the number of taps availab le at a given input filter sample rate.

TAPS floor PROCCLK F

SYM) SYM()ODD#()[]–

SAMP

R⁄()⁄ R]–[()1 +(=

(EQ. 11A)

COEFFICIENT VALUECOEFFICIENT VALUE

EVEN SYMMETRIC EVEN TAP FILTER

EVEN SYMMETRIC

ODD TAP FILTER

CN-1

COEFFICIENT NUMBER

CN-1

COEFFICIENT NUMBER

ODD SYMMETRIC EVEN TAP FILTER

COEFFICIENT VALUE COEFFICIENT VALUE

ODD SYMMETRIC

ODD TAP FILTER

CN-1

COEFFICIENT NUMBER

for real ﬁlters, and

TAPS floor (PROCCLK F

SAMP

R⁄()⁄ R) 2]⁄–[=

(EQ. 11B)

for complex ﬁlters, where ﬂoor is deﬁned as the integer portion ofa number; PROCCLK isthe computeclock; f

SAMP

= the FIR input sample rate; R = Decimation Factor; SYM = 1 for symmetrical ﬁlter, 0 for asymmetrical ﬁlter; ODD# = 1 for an odd number of ﬁlter taps, 0 = an even number of taps.

Use Equation 12 to calculate the maximum input rate.

SAMP

PROCCLK()R()R floor Taps()[[+[⁄ += SYM()ODD#()]1SYM+()⁄]]

(EQ. 12A)

for real ﬁlters, and

SAMP

(EQ. 12B)

, R =

SAMP

PROCCLK()R()[]R floor Taps()2()][+[]⁄=

for complex ﬁlters, where ﬂoor[x], PROCCLK, f Decimation Factor, SYM, and ODD# are deﬁned as in Equation 11.

Use Equation 13 to calculate the maximum output sample rate for both real and complex ﬁlters.

FIR OUT

()R⁄=

SAMP

(EQ. 13)

The coefﬁcients are 22 bits and are loaded using writes to Control Words 128 through 255 (see Microprocessor Write Section). For real ﬁlters, the same coefﬁcients are used by I and Q paths. If the ﬁlter is conﬁgured as a symmetric ﬁlter using Control Word 17, Bit 9, then coefﬁcients are loaded starting with the center coefﬁcient in Control Word 128 and proceeding to last coefﬁcient in Control Word 128+n. The ﬁlter symmetry type can be set to even or odd symmetric, and the number of ﬁlter coefﬁcients can be even or odd, as illustrated in Figure20. Note that complex ﬁlterscan also be realized but are only allowed to be asymmetric. Only the coefﬁcients that are used need to be loaded.

COEFFICIENT VALUE

ASYMMETRIC

EVEN TAP FILTER

CN-1

COEFFICIENT NUMBER

VALUE

Q(0)

IMAGINARY

COEFFICIENT

REAL COEFFICIENT V

COMPLEX FILTERS

REAL FILTERS

I(0)

COEFFICIENT VALUE

ASYMMETRIC

ODD TAP FILTER

ALUE

CN-1

Q(N-1)

COEFFICIENT NUMBER

I(N-1)

COEFFICIENT NUMBER

Deﬁnitions: Even Symmetric: h(n) = h(N-n-1) for n = 0 to N-1

Odd Symmetric: h(n) = -h(N-n-1) for n = 0 to N-1 Asymmetric: A ﬁlter with no coefﬁcient symmetry. Even Tap ﬁlter: A ﬁlter where N is an even number. Odd Tap ﬁlter: A ﬁlter where N is an odd number. Real Filter: A ﬁlter implemented with real coefﬁcients. Complex Filters: A ﬁlter with quadrature coefﬁcients.

FIGURE 20. DEMONSTRATION OF DIFFERENTTYPES OF

DIGITAL FIR FILTERS CONFIGURED IN THE PROGRAMMABLE DOWNCONVERTER

Automatic Gain Control (AGC)

The AGC Section provides gain to small signals, after the large signalsand out-of-bandnoise have beenﬁltered out, to ensure that small signals have sufﬁcient bit resolution in the Resampling/Interpolating Halfband ﬁlters and the Output Formatter. The AGC can also be used to manually set the gain. The AGC optimizes the bit resolution for a variety of input amplitude signal levels. The AGC loop automatically adds gain to bring small signals fromthe lower bits of the 26bit programmable FIRﬁlter output intothe 16-bit range of the

3-20

Page 69

HSP50214B

output section. Without gain control, a signal at -72dBFS = 20log

-12

) at the input would have only 4 bits of

resolution at the output (12 bits less than the full scale 16 bits). The potential increase in the bit resolution due to processing gain of the ﬁlters can be lost without the use of the AGC.

Figure 23 shows the Block Diagram for the AGC Section. The FIR ﬁlter data output is routed to the Resampling and Halfband ﬁlters after passing through the AGC multipliers and Shift Registers. The outputs of the Interpolating Halfband ﬁlters are routed to the Cartesian to Polar coordinate converter. The magnitude output of the coordinate converter is routed through the AGC error detector, the AGC error scaler and into the AGC loop ﬁlter. This ﬁltered error term is used to drive the AGC multiplier and shifters, completing the AGC control loop.

The AGCMultiplier/Shifter portion of the AGC isidentiﬁed in Figure 23. The gain control from the AGC loop ﬁlter is sampled when new data enters the Multiplier/Shifter. The limit detector detects overﬂow in the shifter or the multiplier and saturates the output of I and Q data paths independently. The shifter has a gain from 0 to 90.31dB in

6.021dB steps,where 90.31dB = 20log

(2N), when N = 15.

The mantissa provides an additional 6dB of gain in

0.0338dB steps where 6.0204dB = 20log where X = 2

-1. Thus, the AGC multiplier/shifter transfer

[1+(X)2

-15

function is expressed as:

AGC Mult/Shift Gain 2

1X()2

15–

],+[=

(EQ. 14)

where N, the shifter exponent, has a range of 0<N<15 and X, the mantissa, has a range of 0<X<(2

-1).

Equation 14 can be expressed in dB,

(AGC Mult/Shift Gain)dB 20log102N1X()2

-15

]+[()=

(EQ. 14A)

The full AGC range of the Multiplier/Shifter is from 0 to

96.331dB (20log

[1+(215-1)2

-15

] + 20log10[215] = 96.331). Figure 21 illustrates the transfer function of the AGC multiplier versus mantissa control for N = 0. Figure 22 illustrates the complete AGC Multiplier/Shifter Transfer function for all values of exponent and mantissa control.

GAIN - LINEAR AND dB

0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240

AGC CONTROL MANTISSA VALUES (TIMES 256)

FIGURE 21. AGC MULTIPLIER LINEAR AND dB TRANSFER

FUNCTION

100

GAIN (dB)

0 64 128 192

AGC CONTROL WORD (MANTISSA x 256)

FIGURE 22. AGC GAIN CONTROL TRANSFER FUNCTION

G (dB)

G (LINEAR)

N = 15 N = 14

N = 13 N = 12

N = 11 N = 10

N = 9 N = 8

N = 7 N = 6

N = 5 N = 4 N = 3

N = 2 N = 1

N = 0

The Cartesianto PolarCoordinate converter accepts I and Q data and generates magnitude and phase data. The magnitude output is determined by the equation:

The resolution of the mantissa was increased to 16 bits in the AVersion,to providea theoreticalAM modulationlevelof

-96dBc (depending on loop gain, settling mode and SNR). This effectively eliminates AM spurious caused by the AGC resolution.

For ﬁxed gains, either set the upper and lower AGC limits to the same value, or set the limits to minimum and maximum gains and set the AGC loop gain to zero.

3-21

r 1.64676 I

2Q2

+ .=

(EQ. 15)

where the magnitudelimits are determined by themaximum I and Q signal levels into the Cartesian to Polar converter. Taking fractional 2’s complement representation, magnitude ranges from 0 to 2.329, where the maximum output is

r 1.64676 1.0()21.0()

+= 1.64676 1.414× 2.329==

The AGC loopfeedbackpath consistsof anerror detector, error scaling, andan AGCloop filter. Theerror detectorsubtracts the magnitude output of the coordinate converter from the programmable AGC THRESHOLD value. The bit weighting of

Page 70

HSP50214B

the AGC THRESHOLD value (Control W ord 8, Bits 16-28) is shown inT ab le5. Note that the MSB is alw a yszero. Therange of the AGCTHRESHOLD v alueis 0to +3.9995.The AGCError Detector output has the identical range.

TABLE 5. AGC THRESHOLD (CONTROL WORD 8) BIT

WEIGHTING

28 27 26 25 24 23 22 21 20 19 18 17 16

22212

-12-22-32-42-52-62-72-82-92-10

. 2

The loop gain is set in the AGC Error Scaling circuitry, using the two programmable mantissas and exponents. The mantissa, M, is a 4-bit value which weights the loop ﬁlter input from 0.0 to 0.9375. The exponent, E, deﬁnes a shift

factor that provides additional weighting from 2

to 2

-15

. Together the mantissa and exponent deﬁne the loopgain as given by,

AGC Loop Gain M

where M E

is a 4-bit binary value ranging from 0 to 15. Table 7 and

is a 4-bit binary value ranging from 0 to 15, and

8 detail the binary values and th

24–2

15 ELG–()–

e resulting scaling effects of

(EQ. 16)

the AGC scaling mantissa and exponent. The composite (shifter and multiplier) AGC scaling Gain range is from

0.0000 to 2.329(0.9375)

= 0.0000 to 2.18344. The scaled

gain error can range (depending on threshold) from 0 to

2.18344, which maps to a “gain change per sample” range of 0 to 3.275dB/sample.

The AGC Gain mantissa and exponent values are programmed into Control Word 8, Bits 0-15. The PDC provides for the storing of two values of AGC Scaling Gain (both exponent and mantissa). This allows for quick adjustment of the loop gain by simply asserting the external control line AGCGNSEL. When AGCGNSEL = 0, then AGC GAIN 0 is selected, and when AGCGNSEL = 1, AGC Loop Gain 1 is selected. Possible applications include acquisition/tracking, no burst present/burst present, strong signal/weak signal, track/hold, or fast/slow AGC values.

The AGCloop ﬁlter consists ofan accumulator with a built in limiting function. The maximum and minimum AGC gain limits are provided to keep the gain within a speciﬁed range and are programed by 12-bit Control Words using the following the equation:

AGC Gain Limit 1 m

AGC Gain Limit()dB = 6.02()eeee()20 1.0 0.mmmmmmmm+()log+

+()2

AGC

(EQ. 17)

(EQ. 17A)

9–

where mis an 8-bit mantissa value between0 and 255, and e is the 4-bit exponent ranging from 0 to 15. Control Word 9, Bits 16-27are usedfor programming the upper limit, while bits 0-11 are used to programthe lowerthreshold. Theranges and format for these limit values are sho wn in Tables 6A - C. The bit weightings for the AGC Loop Feedback elements are detailed in Table 9.

TABLE 6A. AGC LIMIT EXPONENT vs GAIN

GAIN(dB) EXPONENT MANTISSA

96.332 15 255

90.309 15 0

84.288 14 0

78.268 13 0

72.247 12 0

66.227 11 0

60.206 10 0

54.185 9 0

48.165 8 0

42.144 7 0

36.124 6 0

30.103 5 0

24.082 4 0

18.062 3 0

12.041 2 0

6.021 1 0

0.000 0 0

TABLE 6B. AGC LIMIT MANTISSA vs GAIN

GAIN(dB) EXPONENT MANTISSA

6.000 0 255

5.750 0 240

5.500 0 226

5.250 0 212

5.000 0 199

4.750 0 185

4.500 0 173

4.250 0 161

4.000 0 149

3.750 0 138

3.500 0 127

3.250 0 116

3.000 0 105

2.750 0 95

2.500 0 85

2.250 0 75

2.000 0 66

1.750 0 57

1.500 0 48

1.250 0 39

1.000 0 31

0.750 0 23

0.500 0 15

0.250 0 7

0.020 0 1

3-22

Page 71

HSP50214B

TABLE 6C. AGC LIMIT DATA FORMAT

CONTROL WORD 9 BIT: 27 26 25 24 23 22 21 20 19 18 17 16

FORMAT e e e emmmmmmmm

SERIAL

OUT

µP

(11 MANTISSA

4 EXPONENT)

MSB = 0

EXP=2

AGC LOOP FILTER

M U X

AGC

LOAD

MANTISSA =

NNNN

01.XXXXXXXXXXXXXX

µP

(RANGE = -2.18344 TO 2.18344)

LIMITER

LIMIT

DET

UPPER LIMIT

LOWER LIMIT †

LIMIT

DET

†

AGC ERROR SCALING

EXP

AGCGNSEL

EXP †

†

LOOP GAIN 0

MAN

SHIFT

MANTISSA

AGC REGISTER 0

AGC REGISTER 1

MAGNITUDE

(RANGE = 0 TO 2.3)

(RANGE = 0 TO 1)

† EXP †

LOOP GAIN 1

MAN

AGC

ERROR

DETECTOR

∆

†

(S = 0)

UNSIGNED

THRESHOLD

STT.TTTTTTTTTT

IFIR

QFIR

SHIFTER

AGC MULTIPLIER/SHIFTER

LIMITER

LIMIT

DET

† Controlled via microprocessor interface.

FIGURE 23. AGC BLOCK DIAGRAM

Using AGC loop gain, the AGC range, and expected error detector output, the gain adjustments per output sample for the Loop Filter Section of the Digital AGC can be given by

AGC Slew Rate 1.5dB THRESH MAG*1.64676())×–(=

()24–()2

 

15 ELG–()–

(EQ. 18)

IAGC

QAGC

LIMITER

RESAMPLING

FIR FILTERS

AND

INTERPOLATING

HALFBAND

FILTERS

CARTESIAN

POLAR

COORDINATE

CONVERTER (G = 1.64676)

The loop gain determines the growth rate of the sum in the loop accumulator which, inturn, determines how quickly the AGC gain traces the transfer function given in Figures 21 and 22. Since the log of the gain response is roughly linear, the loop response can be approximated by multiplying the maximum AGC gain error by the loop gain. The expected

3-23

Page 72

HSP50214B

range for the AGC rate is ~ 0.000106 to 3.275dB/output sample timefor athreshold of1/2 scale. See the notesat the bottom of Table 9 for calculation of the AGC response times. The maximum AGC Response is given by:

AGC Response

Input(Cart/Polar Gain)(Error Det Gain) AGC(=

Max

Loop Gain)(AGC Output Weighting)

(EQ. 19)

Since the AGC error is scaled to adjust the gain, the loop settles asymptotically to its ﬁnal value. The loop settles to the mean of the signal.

TABLE 7. AGC LOOP GAIN BINARY MANTISSA TO GAIN

SCALE FACTOR MAPPING

BINARY

CODE

(MMMM)

0000 0.0000 1000 0.5000 0001 0.0625 1001 0.5625 0010 0.1250 1010 0.6250 0011 0.1875 1011 0.6875 0100 0.2500 1100 0.7500 0101 0.3125 1101 0.8125 0110 0.3750 1110 0.8750 0111 0.4375 1111 0.9375

TABLE 8. AGC LOOP GAIN BINARY EXPONENT TO GAIN

BINARY

CODE

(EEEE)

0000 2 0001 2 0010 2 0011 2 0100 2 0101 2 0110 2 0111 2

For example , if M Gain = 0.3125*2

SCALE

FACTOR

SCALE FACTOR MAPPING

SCALE

FACTOR

10-

= 0101 and ELG = 1100, the AGC Loop

-7

. The loop gain mantissas and exponents

BINARY

CODE

(MMMM)

BINARY

CODE

(EEEE)

1000 2 1001 2 1010 2 1011 2 1100 2 1101 2 1110 2 1111 2

SCALE

FACTOR

SCALE

FACTOR

are set in the AGC Loop Par ameter Control Register (Control Word 8, Bits 0-15).

Two AGC loop gainsare providedin the Programmab leDown Converter, for quick adjustment of the AGC loop. The A GC Gain select is a control input to the device, selecting Gain 0 when AGCGNSEL = 0, and selecting Gain 1 when AGCGNSEL = 1.

In the HSP50214, a reset event (caused by SYNCIN2 or CW25) would clear the AGC loop ﬁlter accumulator. In the HSP50214B, if Control Word 27, Bit 15 is set to zero, the AGC loop ﬁlter accumulator will clear as in the original HSP50214. If Control Word 27, Bit 15 is set to a one, the backend reset (from CW25) will not clear the AGC loop ﬁlter accumulator.

In the HSP50214, the settling mode of the AGC forces the mean of the signal magnitude error to zero. Thegain error is scaled and used to adjust the gain up or down. This proportional scaling mode causes the AGC to settle to the ﬁnal gain value asymptotically. This AGC settling mode is preferred in many applications because the loop gain adjustments get smaller and smaller as the loop settles, reducing any AM distortion caused by the AGC.

With this AGC settling mode, the proportional gain error causes the loop to settle more slowly if the threshold is small. This is because the maximum value of the threshold minus the magnitude is smaller. Also, the settling can be asymmetric, wherethe loopmay settlefasterfor “over range” signals than for “under range” signals (or vice versa).

In someapplications, such as burst signalsor TDMA signals, a very fast settling time and/or a more predictable settling time is desired. The AGC may be turned off or slowed down after an initial AGC settling period.

To minimize the settling time, a median AGC settling mode has been addedto the HSP50214B. This mode uses a ﬁxed gain adjustment with only the direction of the adjustment controlled by the gain error. This makes the settling time independent of the signal level.

For example, if the loop is set to adjust 0.5dB per output sample, the loop gain can slew up or down by 16dB in 16 symbol times, assuming a 2 samples per symbol output sample rate. This is called a median settling mode because the loop settles to where there is an equal number of magnitude samples above and below the threshold. The disadvantage of this modeis that the loop willhave awander (dither) equal to the programmed step size. For this reason, it is advisable to set one loop gain for fast settling at the beginning of the burst and the second loop gain for small adjustments during tracking.

The median settling mode is enabled by setting Control Word 27, Bit 16 to a logic one. If Control Word 27, Bit 16 is zero, the mean loop settling mode is selected and the loop works identically to the HSP50214.

In the median mode, the loop works as follows: The sign of the true gain error selects a ﬁxed gain error of

0010000000000

or 1110000000000b.

These gain error values are scaled by the programmable AGC loop gains to adjust the data path gain.

3-24

Page 73

HSP50214B

The maximum slew rate is ~1.5dB per output sample. See Equation 18.

In order to fully evaluate the dynamic range of the PDC, Table 9Bis provided, whichdetails the bitweighting from the input to the AGC Multiplier.

Re-Sampler/Halfband Filter

The re-sampler is an NCO controlled polyphase ﬁlter that allows the output sample rate to have a non-integer relationship tothe input sample rate. The ﬁlter enginecan be viewedconceptually as a ﬁxedinterpolation ﬁlter, followed by an NCO controlled decimator.

The prototype polyphase ﬁlter has 192 taps designed at 32 times the input sample rate. Each of the 32 phases has 6 ﬁlter taps (6)(32) = 192. The stopband attenuation of the prototype ﬁlter is greater than 60dB, as shown in Figure 24. The signal to totalimage power ratio is approximately 55dB, due to the aliasing of the interpolation images. The ﬁlter is capable of decimation factors from 1 to 4. If the output is at least 2x the baud rate, the 32 interpolation phases yield an effective sample rate of 64x the baud rate or approximately

1.5%, (1/64), maximum timing error. Following the Re-sampler are two interpolation halfband

ﬁlters. The halfband ﬁlters allow the user to up-sample by 2 or 4 to recover time resolution lost by decimating. Interpolating by 2 or 4 gives 1/4 or 1/8 baud time resolution (assuming 2x baud at the re-sampler output). The halfband ﬁlters use the same coefﬁcients as HB3 and HB5 from the Halfband Filters Section. If one halfband is used, the 23-tap ﬁlter is chosen. If two are used, the 23-tap ﬁlter runs ﬁrst followed by the 15-tap ﬁlter operating at twice the ﬁrst

halfband’s rate. The 23-tap ﬁlter requires 7 multiplies, and the 15-tap ﬁlter requires 5 multiplies to complete a ﬁlter calculation.

Using theinterpolation halfbandﬁlters allows for reduction in the FIR ﬁlter sample rate. This optimizes the use of the programmable FIR ﬁlter by allowing the FIR output sample rate to be closer to the Nyquist rate of the desired bandwidth. Optimizing the FIR ﬁlter performance provides better use of the programmable FIR taps. Table 10 details the maximum clocking rates forthe possible resampling and interpolation halfband ﬁlter conﬁgurations of this section of the PDC. Control Word 16, Bits 2-0 identify the ﬁlter conﬁguration. Control Word 16, Bit 3 is used to bypass the polyphase re-sampler ﬁlter.

For proper data output from the interpolation ﬁlters, the data ready signal must account for the interpolation process. Figure 25 illustrates the insertion of additional data ready pulses toprovide sufﬁcient pulsesfor the new output sample rate. The Re-sampler OutputPulse Delayparameter is set in Control Word 16,Bits 4-11. These bits setthe delaybetween the output samples when interpolation is utilized. Program this distance between pulses using

()1]–[=

PROCCLK/fOUT

(EQ. 20)

A value of at least 5 is required to have sufficient time to update the Output Buffer Register. (Writing 5 samples requires 5clock cycles) A value ofat least 16 is requiredfor proper serial output from the part. (Conversion from 16-bit parallel to serial). The value is programmed in numbers of PROCCLK’s.

-20

-40

-60

MAGNITUDE (dB)

-80

-100

-120 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

FREQUENCY (RELATIVE TO f

FIGURE 24A. POLYPHASE RESAMPLERFILTERBROADBAND

FREQUENCY RESPONSE

There is a 65dB limitation in SNR using the Re-Sampler Filter. When only the Interpolation FIRs are used, the full SNR range is passed.

)

-10

-20

-30

-40

-50

MAGNITUDE (dB)

-60

-70

-80 0

0.0625

FIGURE 24B. POLYPHASE RESAMPLER FILTERPASS BAND

0.25

0.125

0.1875

0.3125

FREQUENCY (RELATIVE TO fS)

FREQUENCY RESPONSE

0.375

0.5

0.4375

0.625

0.5625

0.6875

0.75

0.8125

0.875

3-25

0.9375

Page 74

HSP50214B

AGC

ACCUM

BIT

POSITION

GAIN

ERROR

INPUT

GAIN

ERROR

BIT

WEIGHT

TABLE 9A. BIT WEIGHTING FOR AGC LOOP FEEDBACK PATH

AGC LOOP

FILTER

AGC LOOP

FILTER GAIN

(MANTISSA)

GAIN

MULTIPLIER

(OUTPUT)

SHIFT

= 0

SHIFT

= 4

SHIFT

= 8

SHIFT

= 15

AGC

OUTPUT

AND AGC

LIMITS BIT

WEIGHT

AGC GAIN

RESOLUTION

(dB)

31 22220 30 2222 E3 48 29 2222 E2 24 28 2222 E1 12 27 12 = 2 2 2 2 2 2 E0 6 26 11 = 1 1 2 2 2 1 M-1 3 25 10 = 0. 0. 0. 2 2 2 0. M -2 1.5 24 9 = 1 x 1 2 2 2 1 M -3 0.75 23 8 = 2 x 2 2 2 2 2 M -4 0.375 22 7 = 3 x 3 2 2 2 3 M -5 0.1875 21 6 = 4 x 4 2 2 2 4 M -6 0.09375 20 5= 5 5 2225M -7 0.04688 19 4= 6 6 2216X -8 0.02344 18 3 = 7 7 2 2 0. 7 -9 0.01172 17 2= 8 8 2218 -10 0.00586 16 1= 9 9 2229 -11 0.00293 15 0 = 10 10 2 1 3 10 -12 0.00146 14 11 2 0. 4 11 -13 0.000732 13 12 2 1 5 12 -14 0.000366 12 13 2 2 6 13 -15 0.000183 11 14 1 3 7 14 -16 0.0000916 10 0. 4 8 G -17 0.0000458

9 1 5 9 G -18 0.0000229 8 2 6 10 G -19 0.0000114 7 3 7 11 G -20 0.00000572 6 4 8 12 G -21 0.00000286 55913G 4 6 10 14 G 3711GG 2812GG 1913GG

01014GG AGC Response AGC Response

AGC Response

= Input(Cart/PolarGain)(Error Det Gain)(AGC Loop Gain

Max



2()1.64676()

Max

2()1.64676()2

Min

------

1()1.5dB()3.275dB/output sample time∼



15–

()1()1.5dB()0.000106dB/output sample time∼

)(AGC Output Weighting). G = ground = 0.

Max

Thus, the expected range for the AGC rate is ~ 0.000106 to 3.275dB/output sample time.

3-26

Page 75

HSP50214B

TABLE 9B. PDC BIT WEIGHTING

BIT

WEIGHT INPUT SIN/COS MIX OUT

CIC IN

SHIFT = 0

CIC IN

SHIFT = 15

CIC BIT

WEIGHTS

IIIIICCCCC CIC OUT HB D AT AIN

HB DATA

OUT/FIR IN

FIR

COEF

0 0 0 0 S S xxxxxxxxxx 0 0 0 0 1 1 1 1 1 S S xxxxxxxxxx 1 1 1 1 0 0 2 2 2 2 S S xxxxxxxxxx 2 2 2 2 1 1 3 3 3 3 S S xxxxxxxxxx 3 3 3 3 2 2 4 4 4 4 S S xxxxxxxxxx 4 4 4 4 3 3 5 5 5 5 S S xxxxxxxxxx 5 5 5 5 4 4 6 6 6 6 S S xxxxxxxxxx 6 6 6 6 5 5 7 7 7 7 S S xxxxxxxxxx 7 7 7 7 6 6 8 8 8 8 S S xxxxxxxxxx 8 8 8 8 7 7

9 9 9 9 S S xxxxxxxxxx 9 9 9 9 8 8 10 10 10 10 S 10(S) xxxxxxxxxx 10 10 10 10 9 9 11 11 11 11 S 11 xxxxxxxxxx 11 11 11 11 10 10 12 12 12 12 S 12 xxxxxxxxxx 12 12 12 12 11 11 13 13 13 13 S 13 xxxxxxxxxx 13 13 13 13 12 12 14 14 14 S 14 xxxxxxxxxx 14 14 14 14 13 13 15 15 SRnd S 15 xxxxxxxxxx 15 15 15 15 14 14 16 16 S 16 xxxxxxxxxx 16 16 16 16 15 15 17 17 S 17 xxxxxxxxxx 17 17 17 17 16 16 18 S 18 xxxxxxxxxx 18 18 18 18 17 17 19 S 19 xxxxxxxxxx 19 19 19 19 18 18 20 S 20 xxxxxxxxxx 20 20 20 20 19 19 21 S 21 xxxxxxxxxx 21 21 21 21 20 20 22 S 22 xxxxxxxxxx 22 22 22 21 21 23 S 23 xxxxxxxxxx 23 23 23 22 22 24 S 24 xxxxx Rnd Rnd Rnd 23 23 25 25(S) 25 xxxxx SAT SAT SAT 24 24 26 26 26 xxxxx 25 Rnd 27 27 27 xxxxx 26 SAT 28 28 28 xxxxx 27 29 29 29 xxxxx 28 30 30 30 xxxxx 29 31 31 31 xxxxx 30 32 32 32 xx 31 33 33 33 xx 32 34 34 34 xx (Rnd Out

35 35 35 xx 36 36 36 x 37 37 37 x 38 38 38 x 39 39 39 x

NOTES:

1. SRnd = Symmetric Round; Rnd = Round; SAT = Saturation.

2. The NBW out of the CIC filter is 0.5 xf should be ~ 8 (9dB or 1.5 bits) versus A/D noise, the processing gain should be 10log(BWIN/BW

. If the NBWIN=fS/4 and NBWOUT = f

SOUT

/2, then the processing gain for a decimation x 16 CIC

SOUT

OUT

FIR

MULTI/

ACC

of Mult.)

FIR

OUT

3-27

Page 76

HSP50214B

2 1 0

-1

-2

-3

-4

-5

-6

MAGNITUDE (dB)

-7

-8

-9

-10 0

0.125

0.0625 FREQUENCY (RELATIVE TO fS)

0.1875

0.25

0.3125

0.375

0.4375

FIGURE 24C. POLYPHASE RESAMPLERFILTEREXPANDED

RESOLUTION PASSBAND FREQUENCY RESPONSE

TABLE 10. POLYPHASE AND INTERPOLATING HALFBAND

FILTER MAXIMUM CLOCKING RATES

RE-SAM-

PLER

MODE

CLOCK

CY-

CLES

INPUT

RATE (MHz)

INTER-

POLATION

RATE

OUTPUT

RATE (MHz)

Bypass 0 55.00 - 55.00 Polyphase Filter 6 55/6

= 9.17

Polyphase and 1 Halfband

13 55/13

= 4.23

- 9.17 (Note 3)

2 8.46

(Note 3)

Filter Polyphase and

2 Halfband

23 55/23

= 2.39

4 9.56

(Note 3)

Filters 1 Halfband

Filter 2 Halfband

Filters

7 55/7

= 7.86

17 55/17

= 3.24

2 15.72

4 12.94

NOTE:

3. This frequency is set by the Resampler NCO.

In burst systems(such as TDMA), time resolution is needed for quickly identifying the optimum sample point. The timing is adjusted by shifting the decimation in the DSP µP to the closest sample. Use of timing error in this way may yield a faster acquisition than a phase-locked loop coherent bit synchronization. Finding the optimum sample point minimizes intersymbol interference.

Fine time resolution is needed in CDMA systems to resolve different multipath ra ys. In CDMA systems, the demands on the programmable FIR can only be relieved by the resampler/interpolation halfband filters. Assume the chip rate

0.5

for a baseband CDMA system is 1.2288MHz and PROCCLK is limited to 55MHz. Using the symmetric filter pre-sum approach, PROCCLK limits the programmable FIR to 110MIPS (millions ofinstructions per second) eff ective due to symmetry. If the CDMA filter (loaded into the prog r ammable FIR Section) requires an impulse response with a span of 12 chips, thefilter at 2xthe chip-rate w ouldneed 24 taps .The 24 taps would translate into 59MIPS = (1.2288MHz)(2)(24). To get the same filtering at 8x the chip rate would require 944MIPS = (1.2288MHz)(8)(96). Direct 8x filtering can not be accomplished with the programmable filter alone because 944MIPS are much greater that the 60MIPs effectiv e limit set byPROCCLK. Itis necessary todecimate downto 2xthe chip rate to get a realistic number of filter taps. Both interpolation halfband filters are then used to obtain the 8x CDMA output. 944MIPS is a lot of MIPS. The HSP50214B gets the equivalent processing by decimating down and interpolating backup.

POLYPHASE

RESAMPLER

FILTER

RESAMPLER

NCO

PROCCLK

PROCCLK/N

THIS BLOCK GENERATES EXTRA DATA READY PULSES FOR THE NEW OUTPUTS FROM THE INTERPOLATION PROCESS.

NV = INVALID MODE

HALFBAND

FILTER #1

PULSE DELAY

COUNTER

FIGURE 25. GENERATING DATA READY PULSES FOR OUT-

PUT DATA

PULSE DELAY

HALFBAND

FILTER #2

HB2

HB1

MUX

# EXTRA

PULSES

RSMPLR

0 BYPASS 0 1 1

3 (NV)

3 (NV) 3

Timing NCO

The Timing NCO is very similar to the carrier NCO Phase Accumulator Section. It provides the NCO driven sample pulse and associated phase information to the resampling ﬁlter processdescribed inthe Re-samplerFilter Section.The Timing NCO doesnot include the SIN/COS Section found in the Carrier NCO. The top level block diagram is shown in Figure 26.

3-28

Page 77

HSP50214B

EN EXT TIMING NCO SYNC

SYNCIN2 TIMING PHASE STROBE †

TIMING NCO

PHASE OFFSET

ENABLE SOF

SOFSYNC

NUMBER OF SOF BITS †

†

SOF

†

SYNC

REG

PHASE

ACCUMULATOR

MUX

SOF

SYNC

SHIFT REG

REG

TIMING NCO CENTER

REG

FREQUENCY

† Controlled via microprocessor interface.

FIGURE 26. TIMING NCO BLOCK DIAGRAM

REG REG

CARRY OUT = RUN FILTER STROBE

MUX

SCF

SYNC

†

FILTER PHASE SELECT

CLEAR PHASE

TIMING NCO

TIMING FREQ STROBE

ACC

PH ACC

LOAD ON UPDATE

†

TIMING

NCO

ACC.

CARRY

PHASE(31:28)

REFCLK

†

† Controlled via microprocessor interface.

NCO DIVIDE†

PROGRAMMABLE

DIVIDER

REFERENCE

DIVIDE†

PROGRAMMABLE

DIVIDER

(NCO DIVIDE)/2†

REG

∆

TE(15:0)

FIGURE 27. TIMING ERROR GENERATION

Figure 27A illustrates an application where the Timing Error Generator is used to lock the receiver samples with a transmit data rate. In this example, the receive samples are at four times the transmit data rate. An external loop ﬁlter is required, whosefrequency error outputis fed into the Timing NCO. This allows the loop to track out the long term drift between the receivesample rateand the transmit data clock.

The programmable parameters for the Timing NCO include an Enable External Timing NCO Sync (Control Word 11, Bit

5), the serial word width, Number of Offset Frequency Bits (Control Word 11, Bits 3-4), an Enable Offset Frequency control (Control Word 11, Bit 2), a Clear NCO Accumulator control (Control Word 11, Bit 1), a Timing NCO Phase Accumulator Load On Update control (Control Word 11, Bit

0), the Timing NCO Center Frequency (Control Word 12), a Timing Phase Offset (Control Word 13, Bits 0-7), a Timing Frequency Strobe (Control Word 14) and a Timing Phase Strobe (Control Word 15). Refer to the Carrier Synthesizer Mixer Sectionfor a detailed discussion of the serial interface for the Timing NCO offset frequency word.

A timing error detector is provided for measuring the phase differencebetween thetiming NCO and a external clockinput, REFCLK. Timing Error is generated by comparing the values of two programmable counters. One counter is clocked with the Timing NCO carry out and the other is clocked by the REFCLK. The 12-bit NCO Divide parameter is set in Control Word 18, Bits 16-27. The NCO Divide parameter is the preload to the counter that is clocked by the Timing NCO carry out. The 12-bit Reference Divide parameter is set in Control Word 18, Bits 0-11, and is the preload for the counter that is clocked by the Reference clock. Figure 26 details the block diagram of the timing error generation circuit. The 16 bits of timing error are available both as a PDC serial output and as aprocessor read parameter.See the Processor Read Section for more details on accessing this value.

LOOP

FILTER

µP

TIMING

NCO ACC.

CARRY

PHASE(31:28)

Tx DATA CLK

(REFCLK)

RT= TOTAL DECIMATION (CIC, HB FILTERS AND FIR)

CLKIN/R

NCO DIVIDE = 4N†

PROGRAMMABLE

DIVIDER

REFERENCE

DIVIDE = N†

PROGRAMMABLE

DIVIDER

(NCO DIVIDE)/2†

REG

TO Tx BLOCK (MODULATOR)

† Controlled via microprocessor interface.

FIGURE 27A. TIMING ERROR APPLICATION

∆

TE(15:0)

3-29

Page 78

HSP50214B

Cartesian to Polar Converter

The Cartesian to Polar converter computes the magnitude and phase of the I/Q vector. The I and Q inputs are 18 bits. The converter phase output is18 bits (truncated)with the 16 MSB’srouted to theoutput formatter andall 18 bitsrouted to the frequency discriminator. The 16-bit output phase can be interpreted either as two’s complement (-0.5 to approximately 0.5) or unsigned (0.0 to approximately 1.0), as shown in Figure 28. The phase conversion gain is 1/2π. The phase resolution is 16 bits. The 16-bit magnitude is unsigned binary format with a range from 0 to 2.32. The magnitude conversion gain is 1.64676. The magnitude resolution is 16 bits. The MSB is always zero.

Table 11 details the phase and magnitude weighting for the 16 bits output from the PDC.

TABLE 11. MAG/PHASE BIT WEIGHTING

BIT MAGNITUDE PHASE (o)

15 (MSB) 22 (Always 0) 180

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

-11

-12

-13

90 45

22.5

11.25

5.625

2.8125

1.40625

0.703125

0.3515625

0.17578125

0.087890625

0.043945312

0.021972656

0.010986328

0.005483164

14 2 13 2 12 2 11 2 10 2

92 82 72 62 52 42 32 22 12

0 (LSB) 2

The magnitude and phase computation requires 17 clocks for full precision. At the end of the 17 clocks, the magnitude and phase are latched into a register to be held for the next stage, either the output formatter or frequency discriminator. If anew inputsample arrives before the endof the17 cycles, the results of the computations up until that time, are latched. This latching means that an increase in speed causes only a decrease in resolution. Table 12 details the exact resolution that can be obtained with a ﬁxed number of clock cycles upto the required 17. The input magnitude and phase errors induced by normal SNR values will almost always be worse than the Cartesian to Polar conversion.

TABLE 12. MAG/PHASE ACCURACY vs CLOCK CYCLES

MAGNITUDE

ERROR

CLOCKS

6 0.065 3.5 2 7 0.016 1.8 1 8 0.004 0.9 0.5

9 <0.004 0.45 0.25 10 <0.004 0.22 0.12 11 <0.004 0.11 0.062 12 <0.004 0.056 0.03 13 <0.004 0.028 0.016 14 <0.004 0.014 0.008 15 <0.004 0.007 0.004 16 <0.004 0.0035 0.002 17 <0.004 0.00175 0.001

† Assumes ±180

= fS.

(% fS)

PHASE

ERROR (DEG.)†

PHASE

ERROR

(% fS)

In theHSP50214, theinput tothe coordinate converter I/Q to |r|/θ) block is 18bits. If thesignal range is large and theAGC is not used, the quantization noise can become a contributing factor inthe phase and frequency computations. For example, if the signal range is 84dB and the maximum signal is set at full scale, the minimum signal would have only 4 bits each for I and Q.

+π/2

3ff f

4000

7fff

±π

8000

bfff

-π/2

FIGURE 28. PHASEBIT MAPPING OF COORDINATE

CONVERTER OUTPUT

c000

0000

ffff

7fff

8000

4000

bfff

π/2

3π/2

3fff

c000

3-30

0000

ffff

In the HSP50214B, an additional data path option was added that allows the output of the 255 tap programmable FIR ﬁlter to be routed directly to the coordinate converter. Rather than having to select only 18 bits out of the available 26 bit output, all 26 bits of the FIR output are routed to the coordinate converter. This change eliminates quantization effects to give more accuracy in the phase and frequency discriminator outputs. The AGC settling time is not a factor because the AGC is effectively bypassed for the magnitude, phase, and frequency computations.

NOTE: The most signiﬁcant 18 bits of the computed phase are

still routed to the discriminator.

Page 79

HSP50214B

One caveat to selecting theFIR outputs to berouted directly to the coordinate converter is that because the I/Q samples for the coordinate conversion are chosen from before the resampler, the magnitude and phase samples will not align with the I/Q samples, if the resampler or interpolation halfband ﬁlters are used.

This optional signalrouting mode was intendedfor FM or for burst PSK where a ﬁxed decimation can be used. It is also applicable when resampling or timing adjustments on the demodulated samples are done in a processor following PDC.

The magnitude resolution may suffer because there is no gain adjustment before computing the magnitude. If the signal is < - 90dBFS, it will be below the LSB of the magnitude output.

The enable signal for gating data into the coordinate converter is either the AGC data ready signal or the resampler data ready signal. If the resampler is bypassed, the AGC data ready signal is used and there is a delay of 6 clock cycles between the FIR data being ready and the coordinate converter block sampling it. If the resampler is enabled, itsdata ready signalwill be delayed by 6 clocks (for the AGC) plus the compute delay of the resampler block. This may cause the I/Q to |r|/θ output sample alignment to shift withdecimation. For thisreason, it is recommended that the resampler/halfband ﬁlter block be bypassed when using this new data path.

To selectthe outputof the 255 tap programmable FIRﬁlter to be routed to the coordinate converter, set Control Word 27, Bit 13 to a logic one. For routing as in the HSP50214, set Control Word 27, Bit 13 to a logic zero.

Frequency Discriminator

The discriminator block delays phase from the Cartesian to Polar Section and subtracts it from the latest sample. This delay and subtract can be modeled as a programmable delay comb filter. The output of the filter is dθ/dt, or frequency. The transfer function of the discriminator is set by

Hz() 1Z

where D is the programmable discriminator delayexpressed in number of sample clock delays. The discriminator output frequency isthen ﬁltered with a programmableFIR ﬁlter. The Block Diagram of the Frequency Discriminator is shown in Figure 29.

The range of delay in the discriminator is from 1 to 8 samples.Modulo 2π subtraction eliminates rollover problems in the subtraction at 2π. The alias free discriminator frequency range is given by:

Range

D–

–=

FREQDISC

CW F±

SAMPOUT

(EQ. 21)

D1+()⁄ ;=

(EQ. 22)

where D is the discriminator delay deﬁned in Equation 21 (1 < D < 8), f

SAMPOUT

is the Discriminator FIR ﬁlter output sample rate and CW is the desired center frequency. When the phase multiplier is set to a value other than 2

, the discriminator range is reduced proportionally. The phase multiplier canbe 1, 2, 4or 8 (2

to 23). Thus,a multiply of 2 reduces the range by 2, a multiply of 22 reduces the range by 4, and a multiply of 2

reduces the range by 8.

The FIRﬁlter canbe conﬁguredwith upto 63 symmetric taps and up to 32 asymmetric taps. In the symmetric mode, the FIR can be conﬁgured for even or odd symmetry, as well as with an even or odd number of ﬁlter taps. Decimation is provided to allow more processing time for longer (i.e., more taps) ﬁlter structures.

PHASE INPUT

PHASE MULTIPLIER

DISCRIMINATOR DELAY †

DISCRIMINATOR EN †

FIR COEFFICIENTS †

DISC. FIR DECIMATION †

FIR SYMMETRY TYPE †

FIR SYMMETRY †

FIR TAPS †

†

DELAY

(1-8)

63-TAP

FIR

FILTER

FREQ(15:0) (2’s COMPLEMENT)

† Controlled via microprocessor interface.

FIGURE 29. FREQUENCY DISCRIMINATOR BLOCK DIAGRAM

The HSP50214B offers an expanded choiceof signals to be ﬁltered by the discriminator FIR. The choices are:

1) 18 bits of delayed, and subtracted (and optionally shifted) phase. This is the Discriminator FIR ﬁlter input found in the HSP50214.

2) 18 bits of magnitude from the coordinate converter block. This was added to provide for post-detection ﬁltering of AM signals.

3) 18 bits from the I output of the resampler/interpolation halfband ﬁlter block. This was added to provide for processing of SSB signals.

The shift, delay, and subtract functions are bypassed for items (2) and (3).

In addition to the FIR input selections, the Q input to the coordinate converter block can be zeroed so that the magnitude output is the magnitude of I only. Again this was added to provide for processing SSB signals.

3-31

Page 80

HSP50214B

The Discriminator FIR ﬁlter input selections are made in Control Word 27, Bits 18 and 19. The bit deﬁnitions are:

00 Item (1) described above. 01 Item (2) described above. 1X Item (3) described above. Control Word 27, Bit 14 is used to control the Q input to the

coordinate converter. The bit deﬁnitions is:

0 I and Q enabled to the I/Q to R/Theta block. 1 The Q input to the I/Q to R/Theta block is zeroed.

The enable signals associated with the various input selections to the Discriminator FIR ﬁlter are:

1 The data ready strobe from the coordinate con-

verter block.

2 The data ready strobe from the coordinate con-

verter block.

The enable signals associated with the various input selections to the coordinate converter are:

3a The data ready signal to the coordinate converter

block when the resampler is bypassed. This is the AGC output data ready signal.

3b The data ready to the coordinate converter block

when the resampler/halfband ﬁlters are enabled. This is the resampler halfband ﬁlter block output data ready signal.

The discriminator input is 18 bits, and the output is rounded asymmetrically to 16 bits. The phase into the discriminator can be multiplied by 2

0,21,22

,or23(modulo 2π) to remove PSK data modulation. All programmable parameters for the Frequency Discriminator are set in Control Word 17. Bits 15 and 16 are the phase multiplier which represents the shift applied tothe inputphase. ForCW,the multiplyshould equal

, (00). For BPSK, QPSK, and 8PSK, the multiply should

equal 2

, (01); 22, (10); or 23, (11); respectively. Bit 14 is used to enable or disable the discriminator. Bits 11-13 set the decimationin the programmable FIRﬁlter. Bit10 sets the ﬁlter symmetry typeas either oddor even,bit 9 sets whether the ﬁlter is asymmetric or symmetric, and bits 3-8 set the number ofFIR ﬁltertaps. Bits 0-2 set thenumber of delays in the frequency discriminator.

Output Section

The OutputSection routesthe 7 typesof processedsignals to output pins in three basic modes. These basic modes are: Parallel Direct Output, Serial Direct Output, and the Buffer RAM Output. The Serial and Parallel Direct Output modes were designed to output data strobes and “real time” continuous streams of data. The Buffer RAM Output mode outputs data upon receipt of an asynchronous request from an external DSP processor or other baseband processing engine. The use of the interrupt signal from the Programmable Down Con verter in conjunction with the

request strobes from the controller ensures that data is transferred only when both the controller and the Programmable Down Converter are ready. The Buffer RAM output can be operated in a First In First Out (FIFO) or SNAPSHOT mode with the data output either via the 8-bit processor interface or a 16-bit processor interface.

Parallel Direct Output Port Mode

The P arallelDirect Output Port Mode outputs tw o16-bit words, AOUT and BOUT, of “real time” data. Figure 30 details the parallel output circuitry . Selection of the data source f or the AOUT and BOUT parallel outputs is done viaControl Word 20, Bits 22-23, and 20-21, respectively. The AOUT port can output I, Magnitude,or F requencydata. TheBOUT port canoutput Q, Phase or Magnitude data. The upper bytes of AOUT and BOUT arealways inthe parallel directmode. The16-bit parallel direct mode is selected by setting Control Word 20, Bit 25, to zero.

The

DATARDY output is asserted during the ﬁrst clock cycle of thenew data on the AOUTbus. Therate at which the data out of the HSP50214 transitions and the rate at which DATARDY is asserted can be different.

Data Transitions:

The transition rate of the parallel output data is dependent on which of the three types of data is selected for the AOUT Output channel: I (real symbols), |r| (magnitude), or f (frequency). Q (quadrature symbols), ø (phase), or |r| (magnitude) are available on the BOUT output. When selected as an output, the I Q, |r|, and ø outputs transition at the symbol rate. The f (frequency) output transitions at the discriminator FIR filter output rate.

AOUT DIRECT PAR OUTPUT MODE DATA SOURCE

(2’s COMPLEMENT)

(UNSIGNED BINARY)

(2’s COMPLEMENT)

(UNSIGNED BINARY)

Controlled via microprocessor interface.

†

MAG

FREQ

BOUT DIRECT PAR OUTPUT MODE DATA SOURCE

PHAS

MAG

RAM (15:0)

FIGURE 30. PARALLEL OUTPUT BLOCK DIAGRAM

†

MUXMUX

A(15:8) A(7:0)

RAM(15:8)

†

DATA SOURCE FOR LSB

B(15:8) B(7:0)

RAM (7:0)

DATARDY

AOUT(15:8)

AOUT(7:0)

MUX

BOUT(15:8)

BOUT(7:0)

MUX

†

3-32

Page 81

HSP50214B

Data Ready Signal Assertion Rate:

The assertion rate of the DATARDY signal Is the data transition rate of the A time alignment of parallel data words availablefor output are as follows:

output data either [I, |r| or f]. The

OUT

Note that the BOUT data word may be at a different r ate and skewed in time with respect to

DATARDY, depending on the type of data selected for output. This is because of the timing relationships defined above, and because the DATARDY is driven by the AOUT signal. Figure 32 details such a configuration.

I and Q are aligned in time, |r| and ø are time aligned, but one sample clock delayed

from the associated I and Q samples.

When the f (frequency) word is selected for output on AOUT, the DATARDY signalis asserted atthe discriminatorFIR ﬁlter output rate, whichwill be a reduced rate when decimation is

DATARDY Is asserted time aligned with and at the same rate as the data type selected for the AOUT output.

Figure 31 details the timing of the AOUT and

DATARDY for

an AOUT = I data selection.

engaged in the ﬁlter. The f (frequency)S output is delayed from the associated I and Q samples one sample time plus, the discriminator FIR ﬁlter impulse response time. Figure 33 details the timing of this conﬁguration for a FIR ﬁlter that decimates by 4.

AOUT

PROCCLK

DATARDY

NOTE: The number of PROCCLKS per outputsymbol isnot representative, but shown to besmall for clarity ofestablishing timing withrespect to the DATARDY signal.Foreach application, therelationship of theoutput symbolrateto PROCCLK mustbe properlyillustrated to determine the exact nature of the timing.

I0 I1 I2 I3 I4 I5 I6

DR0 DR1 DR2 DR3 DR4 DR5 DR6

FIGURE 31. DATARDY WAVEFORMS WHEN I (READ DATA) IS SELECTED AS AOUT

BOUT

AOUT

PROCCLK

DATARDY

BOUT

AOUT

PROCCLK

DATARDY

NOTE: I and Q are sample aligned in time. |r| and φ are sample aligned in time, but one sample delayed from I or Q. The frequency

sample is delayed intime fromI or Qby 1sample time+ 63 tapFIR impulseresponse. Ifthe FIR isset todecimate andfrequency is selected for AOUT, the DATARDY signal will be at the discriminator FIR output (decimated) rate.

Q0 Q1 Q2 Q3 Q4 Q5 Q6

|r|0 |r|1 |r|2 |r|3 |r|4 |r|5 |r|6

DR0 DR1 DR2 DR3 DR4 DR5 DR6

FIGURE 32. DATARDY WAVEFORMS WHEN |r| (MAGNITUDE) IS SELECTED AS AOUT

1 + FIR Delay

Q0 Q1 Q2 Q3 Q4 Qn Qn+1 Qn+2

DR-1

FIGURE 33. DATARDY WAVEFORMS WHEN f (FREQUENCY) IS SELECTED AS AOUT

DR0

f0 (R = 4)

3-33

Page 82

HSP50214B

Serial Direct Output Port Mode

The Serial Direct Output Port Mode offers the ability to construct two serial output data streams, SEROUTA AND SEROUTB, from 16-bit I, Q, magnitude, phase, frequency, timing error, and A GC le vel data words. The total number of data words(1 to 8) for serialoutput, and thesequential orderof these data word components of the serial output are programmable.Each data word maybe used oncein eitherthe SEROUTAor SEROUTBdata streams .Figure 34 illustratesthe conceptual implementation of the Serial Direct Output Port Mode.

In the Serial Direct Mode, the output data is loaded into Serial Shift Registers and routed to two serial output pins, SEROUTA and SEROUTB. The serial output shift clock, SERCLK, is PROCCLK divided by 1, 2, 4, 8, or 16. The divide down ratio is programmed using Control Word 20, Bits 14-16. The data is shifted out on the rising edge of the internal SERCLK. The externalclock polarity of SERCLK is programmable via Control Word 20, Bit 18. A sync signal is provided for detection of the start or end of each word in the serial sequence. Control Word 20, Bit 17, sets the SERSYNC signal location as either preceding the MSB (typical for interfacing with microprocessors) or following the LSB (typical for interfacing to D/A converters). Control Word 20, Bit 19, sets the SERSYNC polarity as active low or high. The LSB of each data word can be configured as either the true LSB data, or set at a fixed logic “1” or “0” for use as a tag bit. Control Word 20, Bits 0-13 set the LSB of each of the 7 types of data words that can be configured in the serial output stream. Control Word 19, Bits 21-24 set the number of serial data words that will be linked to form the serial outputs.Up to 7 data words can be linked to form the serial output. SEROUTA and SEROUTB will have an identical number of words in the serial output streams.

The 16-bit I, Q, magnitude, phase, frequency, timing error, AGC level, and “zeros” data words are loaded into their respective shift registers. The Magnitude and AGC Level data word are unsigned binary format with a leading zero, while the remaining signals are 2’s complement format.

Any of the eight data sources can be selected as the first serial word for SEROUTA or SEROUTB. Control Word 19, Bits 25-30 set the data type for the first serial word for SEROUTAand SEROUTB.The threebit data type identifier is shown both in Table 13 and in Figure 34, to the right of the controls for the cross matrix switch. Serial output data word sequences are formed by linking data words by programming the data source for each shift requester’s shift input signal. This programming links the Shift Registers together in one or two serial chains. Thus, the Control Word 19 ter m “Link follows X data”, where X is one of the seven data types.Once the data source dataword is selected (by programming a three bit word representing one of the data types into Control Word 19, Bits 25-27 (SEROUTA), and 28-30 (SEROUTB)), the process for

identifying the next word is to select a three bit data type identifier which represents the data type to follow the source data type.Program these bits into the Control Word 19 field representing the “Link following X data”, where X = the source data type, defines the second word in the sequence. Likewise, the third data word is linked by selecting the Control Word 19 bits that identify the “Link following X data”, where X = the data type of the second word in the serial chain.The process continues until all the desired data words have been linked.

NOTE: I and Q are sample aligned in time. |r| and φ are sample

aligned in time, but one sample delayed from I or Q. The frequency sample is delayed in time from I orQ by1 sample time + 63 tap FIR impulse response. If the FIR is set to decimate, the FIR output will be repeated every sample time until anew valueappears at the filteroutput. (i.e., the frequency samples are clocked out at the I, Q sample rate regardless of decimation.)

TABLE 13. LINKING CONTROL WORDS FOR SERIAL OUTPUT

DATA TYPE

IDENTIFIER DATA TYPE

000 I Data 001 Q Data 010 Magnitude (MAG) Data 011 Phase (PHAS) Data 100 Frequency (FREQ) Data 101 Timing Error (TIMER) Data 110 AGC Gain 111 Zeros

Two examples will illustratethe process ofconfiguring a serial output using the Serial Output mode.

The serial data stream looks like:

SEROUTA: CONTROL WORD 19 FIELD

start I data word > SEROUTA source data = 000 Q data word > Link following I data = 001 φ data word > Link following Q data = 011 Zero data word > Link following φ data = 111 end >

SEROUTB: CONTROL WORD 19 FIELD

start |r| data word > SEROUTB source data = 010 f data word > Link following |r| data = 100 TE data word> Link following f data = 101 AGC data word > Link following TE data = 110 end >

3-34

Page 83

I (15:0)

(2’s COMP)

Q (15:0)

(2’s COMP)

(O; UNSIGNED BINARY)

|r| (15:0)

φ (15:0)

(2’s COMP)

f (15:0)

(2’s COMP)

(15:0)

(2’s COMP)

AGC

(O; UNSIGNED BINARY)

(15:0)

ZERO

PROCCLK

NUM OF SER WORD LINKS IN A CHAIN

AGC DATA SERIAL OUTPUT TAG BIT † TIMING ERROR DATA SERIAL OUTPUT TAG BIT † FREQUENCY DATA SERIAL OUTPUT TAG BIT † PHASE DATA SERIAL OUTPUT TAG BIT † MAGNITUDE DATA SERIAL OUTPUT TAG BIT † Q DATA SERIAL OUTPUT TAG BIT † I DATA SERIAL OUTPUT TAG BIT †

REGREGREGREGREGREGREGREG

SHIFT REG

SERIAL OUT CLOCK DIVIDER † SERIAL OUTPUT SYNC POSITION † SERIAL OUTPUT CLOCK POLARITY †

SERIAL OUTPUT SYNC POLARITY †

SHIFT REG

PROGRAMMABLE

†

MUX

SEROUTB

SOURCE

DIVIDER

HSP50214B

DATA SOURCE FOR SEROUTA † LINK FOLLOWING I DATA †

LINK FOLLOWING Q DATA † LINK FOLLOWING MAG DATA † LINK FOLLOWING PHASE DATA† LINK FOLLOWING FREQ DATA † LINK FOLLOWING TIMING DATA † LINK FOLLOWING AGC DATA †

FOLLOWS I

SHIFT REG

FOLLOWS Q

SHIFT REG

CROSS MATRIX SWITCH

CROSS

MATRIX

SWITCH

DATA SOURCE FOR SEROUTB †

FOLLOWS |r|

SHIFT REG

FOLLOWS φ

SHIFT REG

FOLLOWS

SHIFT REG

FOLLOWS TE

SHIFT REG

FOLLOWS AGC

SHIFT REG

SEROUTA

SOURCE

XXX SOURCE 000 I 001 Q 010 MAG 011 PHASE 100 FREQUENCY 101 TIMING ERROR 110 AGC

ZERO

111

6 5 4 3 2 1 0

SERIAL OUTPUT SHIFT REGISTER

SEROUTA

6 5 4 3 2 1 0

SERIAL OUTPUT SHIFT REGISTER

SEROUTB

‡

SERCLK

‡

SERSYNC

† Controlled via microprocessor interface ‡ Polarity is programmable

3-35

FIGURE 34. SERIAL OUTPUT FORMATTER BLOCK DIAGRAM

Page 84

HSP50214B

Serial Output Conﬁguration Example 1:

It is desired to output the I data word, followed by the Q data word, followed by the Phase data word on the SEROUTA output. Similarly, it is desired to output the Magnitude data word followed by the Frequency data word, follow ed by the Timing Error data word, followed b ythe AGC Level data word on the SEROUTB output. Table 14 illustrates how Control Word 19 should be programmed.

TABLE 14. EXAMPLE 1 SERIAL OUTPUT CONTROL SETTINGS

CONTROL

WORD 19

BIT POSITION FUNCTION

30-28 SEROUTA Data Source 000 (I) 27-25 SEROUTB Data Source 010 (|r|) 24-21 Number of Serial Word

Links in a Chain 20-18 Link following I data 001 (Q) 17-15 Link following Q data 011 (φ) 14-12 Link following |r| data 100 (f)

11-9 Link followingφ data 111 (Zeros)

8-6 Link following f data 101 (Timing) 5-3 Link following AGC data XXX (N/A) 2-0 Link following Timing

Error data

NOTE: Becauseall but the first data w ordin the serial outputis iden-

tified b y the data type that it follows, SEROUTBcan only be fully independent ofthe sequencein SEROUTAif itdoes not use any of the samedata wor dtypes. Thisimplies apartition as described in Example 1. Once a data wor dthat isused in SEROUT A is called out in SER OUTB, the remaining sequence in SEROUTB will be identical to that portion of SEROUT A sequence that follows the duplicate data type. This follows from using the “Link follows ‘data type’ data” for word linkage.

NOTE: Each type of data word should be used only once in each

data stream. If the “Link following I data” is programmed with the data type identifierfor I, thenthe part will repeat the Idata worduntil all of the datawordlocations are filled. In Example 1, if bits20-18 wereerroneouslyprogrammedto 000 (I data) then the SEROUTA wouldbe four sequentialrepeats of the I data word.

Serial Output Conﬁguration Example 2:

It is desired to output only three data words on each serial output. TheI data word,followedby the Qdata word,followed bythe Magnitudedata wordis tobe outputon SEROUTA. The Q dataword followed b ythe Magnitudedata word,followed by the one other data word to be output on SEROUTB. The choices for the remaining data word in the SEROUTB signal are: phase, frequency, AGC lev el and timing error. Table 15 illustrates how Control Word 19 should be progr ammed.

BIT

VALUE RESULT

100 (4)

110 (AGC)

TABLE 15. EXAMPLE 2 SERIAL OUTPUT CONTROL SETTINGS

CONTROL

WORD 19

BIT POSITION FUNCTION

30-28 SEROUTA Data Source 000 (I) 27-25 SEROUTB Data Source 001 (Q) 24-21 Number of Serial Word

Links in a Chain 20-18 Link following I data 001 (Q) 17-15 Link following Q data 010 (|r|) 14-12 Link following |r| data TBD TBD

11-9 Link following φ data XXX (N/A)

8-6 Link following f data XXX (N/A) 5-3 Link following AGC data XXX (N/A) 2-0 Link following Timing

Error data

BIT

VALUE RESULT

011 (3)

XXX (N/A)

The serial data stream looks like:

SEROUTA: CONTROL WORD 19 FIELD

start I data word > SEROUTA source data = 000 Q data word > Link following I data = 001 |r|data word > Link following Q data = 010 end >

SEROUTB: CONTROL WORD 19 FIELD

start Q data word > SEROUTB source data = 001 |r|data word > Link following Q data = 010 TBD data word> Link following |r| data = TBD end >

As shown by this example, once Q was linked to |r| in the SEROUTA chain, the SEROUTB chain must have |r| following Q, if Q is selected. Figure 35 illustrates the construction of the serial output streams. If the serial data stream was changed to be a lengthof four data words, then, by default, the SEROUTA would be whatever is selected for SEROUTB data word 3. SEROUTB would need to identify the fourth data word. Thus, SEROUTA and SEROUTB are

not fully independent because they share the Q data

word (and by default, the MAGNITUDE follows Q data link and whatever is selected for data word 3 to follow MAGNITUDE data in SEROUTB).

The other signals provided with the SEROUTA and SEROUTB are the SERSYNC and the SERCLK. The SERSYNC signal can be programmed in either early or late sync mode. The sync signal is pulsed active low or active high for each information word link of the chain of data created using Control Word 19. Figure 36 shows the four possible conﬁgurations of SERSYNC as programmed using Control Word 20.

As previously discussed, Control Word 20, Bits 17 and 19, set thefunctionality ofthe LSB ofeach dataword. Thesebits may be programmed to be either a logic “0”, logic “1” or as normal data. The ﬁxed states are designed to allow the microprocessor to synchronize to the serial data stream.

3-36

Page 85

TBD

HSP50214B

CONTROL WORD 19, BITS 24-21 = 011

(3 DATA WORDS IN EACH SERIAL OUTPUT)

DATA WORD 1DATA WORD 2DATA WORD 3

IQMAGNITUDE

DATA WORD 1DATA WORD 2DATA WORD 3

QMAGNITUDE

SEROUTA

SEROUTB

THE REMAINING CHOICES FOR THE THIRD LINK ON SEROUTB ARE:

PHASE, FREQUENCY, AGC LEVEL, AND TIMING ERROR

FIGURE 35. EXAMPLE 2 SERIAL OUTPUT DATA STREAM

“NORMAL”

“INVERTED”

“NORMAL”

“INVERTED”

LSB WORD0

SERSYNC FOLLOWS LSB

SERSYNC PRECEDES MSB

MSB WORD1

DATA SHIFT MSB FIRST

1 15 1412215 14 • • •

15 14

LSB WORD1

FIGURE 36. VALID SERSYNC CONFIGURATION OPTIONS

The serial direct output can be programmed to output less than 16bits. New outputdata preempts oldoutput data, so if SERSYNC is programmed to precede the MSB, then data will shift out until new data comes along. Note that if SERSYNC isprogrammed tofollow theLSB, thena sync will never occur.

Buffer RAM Output Port

The Buffer RAM parallel output mode utilizes a RAM to store output data for future retrieval by either the 8-bit microprocessor that is configuring the PDC or by a 16-bit baseband processing engine (which could also be a microprocessor). Data is output from the RAM only on request and can beobtained from either the 8-bitµP interface orfrom a 16-bit interface that uses the two LSBytes of AOUT and BOUT. The RAM holds up to eight 80-bit sample sets. Each sample set includes 16 bits of each I, Q, magnitude, phase, and frequency data.The RAMsamples aremapped asshown in Table 16. The Buffer RAM controller supports both FIFO and Snapshot modes.

MSB WORD2

• • •

SAMPLE

NOTE: I and Q are sample aligned in time. |r| and φ are sample

NOTE: Once magnitude is identiﬁed to follow Q,

it must be that way on both serial outputs.

MSB WORD3

• • • 2

LSB WORD2

LATE SERSYNC MODE

EARLY SERSYNC MODE

TABLE 16. RAM DATA STORAGE MAP

RAM

SET

0I 1I 2I 3I 4I 5I 6I 7I

DATA

(000)

(15:0) Q0(15:0) |r|0(15:0) φ0(15:0) f0(15:0)

(15:0) Q1(15:0) |r|1(15:0) φ1(15:0) f1(15:0)

(15:0) Q2(15:0) |r|2(15:0) φ2(15:0) f2(15:0)

(15:0) Q3(15:0) |r|3(15:0) φ3(15:0) f3(15:0)

(15:0) Q4(15:0) |r|4(15:0) φ4(15:0) f4(15:0)

(15:0) Q5(15:0) |r|5(15:0) φ5(15:0) f5(15:0)

(15:0) Q6(15:0) |r|6(15:0) φ6(15:0) f6(15:0)

(15:0) Q7(15:0) |r|7(15:0) φ7(15:0) f7(15:0)

DATA

(001)

|r|

DATA

(010)

DATA

(011)

aligned in time, but one sample delayed from I or Q. The frequency sample is delayed in time from I or Q by 1 sample time + 63 tap FIR impulse response. If the FIR is set to decimate, the FIR output will be repeated every sample time until anew value appears atthe filteroutput. (i.e., the frequency samples are clocked out at the I, Q sample rate regardless of decimation.)

DATA

(100)

3-37

Page 86

HSP50214B

The FIFOmode allowsthe processor toservice the interface only when enough samples are present in the RAM. This mode is provided so that the µProcessor does not have to service the PDC every output sample. An interrupt, INTRRPT, is asserted when the desired number of samples are available. The PDC can be programmed to assert the interrupt when up to 7 samples are available. Control Word 21, Bit 15 is used to set the Buffer RAM controller to the FIFO mode, while Control Word 21, Bits 12-14 set the number of RAM samples to be stored (0 to 7) before the interrupt (

INTRRPT) is asserted. Control Word 20, Bit 24 determines whether the RAM output interface is the 8-bit microprocessor interface or the16-bit processor interface. In the 16-bit interface the MSByte is sent to AOUT(7:0) while the LSByte is sent to BOUT(7:0).

The

INTRRP output signal goes low for 8 PROCCLK cycles when the number of samples in the Buffer RAM (depth) reaches the programmed depth. The depth of the RAM is calculated using Equation 23. A DSP microprocessor or the data processing engine can use the

INTRRP signal to know

that the RAM is ready to be read.

RAM

ADDR

WRITE

ADDR

–()1]

READ

–[=

MOD8

(EQ. 23)

|r|

φ ƒ

SEQUENCER

NEW

DAT A

FIGURE 37. 16-BITMICROPROCESSOR INTERFACEBUFFER

TABLE 17. BUFFER RAM OUTPUT SELECT DEFINITIONS

MUX

16 16

WRITE

SEL(2:0) OUTPUT DATA TYPE

000 I Data 001 Q Data 010 Magnitude 011 Phase

DUAL PORT

RAM

DATA INPUT

“SET OF WORDS”

ADDRESS

SEQUENCER

INCR

PROCCLK

RAM MODE BLOCK DIAGRAM

DATA OUTPUT

INCR

Q |r|

φ ƒ

STATUS

0 1 2 3

MUX

4 6

OUTPUT DAT A

OEBL SEL(2:0)

FIFO Operation via 16-Bit µProcessor Interface

Figure 37 shows the conceptual conﬁguration of the 16-bit

µProcessor interface. This interface looks like a 16-bit µProcessor read-only microprocessor interface. The

SEL(2:0) linesare theaddress bus and the OEALand OEBL lines arethe read lines. The addressis decodedas shown in Table 17.

Use of the 16-bit interface for Buffer RAM output requires Control Word 20, Bit 25, to be set to a logic “0” and Control Word 20, Bit 24, to be set to a logic “1”. Once the Control Word 20 has been set to route data to AOUT(7:0) and BOUT(7:0), then the microprocessor must place a value on the PDC input pins SEL(2:0), to choose which data type will be output on AOUT(7:0) and 6BOUT(7:0). Table 17 deﬁnes the data types in terms of SEL(2:0). With the control lines set, the selected data is read MSByte on AOUT(7:0) and LSByte on BOUT(7:0) when New data only read when bit modes. Programming SEL(2:0) = 110 outputs a 16-bit status signal on AOUT and BOUT. The FIFO status includes FULL, EMPTY, FIFO Depth, and READYB. These status signals are deﬁned in Table 18.

OEAL and OEBL (are low).

OEBL goes low, so use µP for 8-

100 Frequency 101 Unused 110 Memory Status 111 Reading this address increments tothe next

sample set

TABLE 18. STATUS BIT DEFINITIONS

AOUT BIT

LOCATION INFORMATION

(7:5) FIFO depth - When in FIFO mode, these bits

are the current depth of the FIFO.

4 EMPTY - When in FIFO mode, the FIFO is

empty, and the read pointer cannot be advanced. Active High.

3 FULL - When in FIFO mode, the FIFO is full,

and new samples will not be written. Active High.

2 READYB - Whenin FIFO mode,the outputbuff-

er has reached the programmed threshold. In the snapshot mode, the programmed number of samples have been taken. Active Low.

3-38

1-0 GND

NOTE: In the Status output, BOUT(7:0) are all GND.

Page 87

HSP50214B

Figure 38 shows the interface between a 16-bit microprocessor (or other baseband processing engine) and the Buffer RAM Output Section of the Programmable Down Converter,conﬁgured for data output via the parallel outputs AOUT and BOUT. In the 16-bit microprocessor interface conﬁguration, the Buffer RAM pointer is incremented when the µProcessor reads address SEL(2:0) = 7 and

OEBL = 0.

INTRRP

OEAL,

OEBL

SEL(0:2)

8 CLKS

> 4 CLKS

0147 01

After reset, the FIFO must be incremented to read the first sample set. This is because the RAM read and write pointers cannot point to the same address. Thus, the FIFO pointer must move to the ne xt address before reading the next set of data (I, Q, |r|, φ, andf) samples. 4 PROCCLK cycles are required after an increment before reading can resume. The FIFO writepointer isreset to z ero(the firstdata sample)when Control Word 22 is written to via the 8-bit microprocessor interface. See the Microprocessor Read Section f or more detail on how to obtain the Buffer RAM output with this technique. Figure 39 shows the timing diagram required f or parallel output operations. In this diagram, only the I, Q and Frequency data are taken from each sample before incrementing to the next sample. Figure 39 assumes that the pointer has already been incremented into a sample.

NOTE: For thevery first sample read, thepointer must be incre-

mented first and 4 PROCCLKs must pass before this sample can be read.

Figure 39shows INTRRP goinglow before the FIFO is read. The FIFO can be read before the number of samples reaches the INTRRP pointer. The number of samples in the FIFO must be monitored by the user via a status read.

INTRRP

PDC

HSP50214B

FIGURE 38. INTERFACE BETWEEN A 16-BIT MICROPROCES-

SOR AND PDC IN FIFO BUFFER RAM MODE

OEAL

AOUT(7:0)

OEBL

BOUT(7:0)

SEL(2:0)

INT

D(15:8)

16-BIT

µP

D(7:0)

A(2:0)

AOUT(7:0),

BOUT(7:0)

PROCCLK

FIGURE 39. TIMING DIAGRAM FOR PDC IN FIFO MODE WITH

IQFR IQ

1234 12345678

OUTPUTS I, Q, AND FREQUENCY SENT TO AOUT(7:0) AND BOUT(7:0)

Suppose the depth of the Buffer RAM Output Section is programmed for an

INTRRP pointer depth of 4. If the output is at 4 times the baud rate, the processing routine for the microprocessor may only need to read the buffer when the Buffer RAM had 4 samples since processing is usually on a baud by baud basis.

Figure 40 illustrates the conceptual view of the FIFO as a circular buffer, with the Write address one step ahead of the Read Address.

Figure 40A deals with clockwise read and write address incrementing. The FIFO depth is the difference between the Write and Read pointers, modulo 8. Figure 40B illustrates a FIFO status of Full, while Figure 40C illustrates a FIFO empty statuscondition. Figure 40D illustrates aprogrammed FIFO depth of 3 and the INTRRP signal indicating that the buffer has sufﬁcient data to be read.

Following some simple rules for operating the FIFO will eliminate most operational errors:

Rule #1: The Read and Write Pointers cannot point at the same address (the circuitry will not allow this).

Rule #2: The FIFO is full when the Write Address = Read Address -1 (no more data will be written until somesamples are read or the FIFO is reset).

Rule #3: The FIFO is empty when the Read Address = (Write Address -1) (the circuitry will not allow the read pointer to be incremented).

Rule #4: You cannot write over what you have not read.

3-39

Rule #5: RESET places the Write address pointer = 000 and Read address pointer = 111.

Rule #6: The best addressing scheme is to read the FIFO until it is empty. This avoids erroneous

INTRRP assertions and provides forsimple FIFOdepth monitoring.The interrupt is generated when the depth increments past the threshold.

Page 88

HSP50214B

READ

A: FIFO DEPTH IS (WRITE - READ)

B: FIFO FULL IS WHEN (WRITE - READ) = 7

FIFO

DEPTH

WRITE

READ

WRITE

FIFO Operation via 8-Bit µProcessor Interface

The Buffer RAM Output may also be accessed via the 8-bit microprocessor interface C(7:0). Figure 41 shows the conceptual conﬁguration of the 8-bit µprocessor interface. Control Word 20, Bit 24 must be set to 0 in order to obtain Buffer RAM data to this output. The Microprocessor Read Section describes how to read the data from each sample out of the C(7:0) interface.

Recall that FIFO can be read before the INTRRP signal goes low; the number ofsamples in theFIFO must be monitored bythe user. The timing relationship of the shown in Figure 42.

The read pointer of the FIFO is incremented when Control Word 23 is written to. The data cannot be read from the next sample until 4 PROCCLKs after the Buffer RAM pointer has been incremented. Control Word 22 is used to reset theRead and Write pointersof the Buffer RAM output to the first sample to 000 and 007 for write and read respectively.

INTRRP sta y s l ow fo r 8 P ROCCLK cycles. The

INTRRP to the snapshot data is

C: FIFO EMPTY IS WHEN (WRITE - READ) = 1

WRITE

D: FIFO READY IS WHEN (WRITE - READ) > DEPTH

READ

READY

FIGURE 40. FIFO REGISTER OPERATION

3-40

Page 89

NEW

DAT A

CONTROL

WORD 23

A(2:0)

|r|

φ ƒ

SEQUENCER

MUX

16 16

WRITE

ADDRESS “5”

0: I;Q (2’s COMP) 1: |r|;

φ (O; UNSIGNED BINARY; 2’s COMP)

2: ƒ (2’s COMPLEMENT) 4: INPUT AGC (O; UNSIGNED BINARY) 5: AGC; TIMING (O; UNSIGNED BINARY;

DUAL PORT

RAM

DATA INPUT

“SET OF WORDS”

ADDRESS

SEQUENCER

INCR

R2, R1, R0 A2, A1, A0

2’s COMP)

FIGURE 41. 8-BIT MICROPROCESSOR INTERFACE BUFFER RAM MODE BLOCK DIAGRAM

I Q |r|

φ ƒ

DATA OUTPUT

STATUS

0 1 2 3 4

MUX

R0R1

INT(15:0)

INT(22:16)

AGC

TIMING

HSP50214B

LSByte

MUX

MSByte

0 1 2

MUX

R0 A1

MUX

A1A2 A0

OUTPUT DAT A

R2 R1 R0 A2 A1 A0 SELECTION

000000RAM I LSB 000001RAM I MSB 000010RAM Q LSB 000011RAM Q MSB 001000RAM |r| LSB 001001RAM |r| MSB 001010RAMφ LSB 001011RAMφ MSB 010000RAMƒ LSB 010001RAMƒ MSB 0 1 1 X X X NOT USED 100000INPUT INTEG LSB 100001INPUT INTEG NMSB 100010INPUT INTEG MSB 101000AGC LSB 101001AGC MSB 101010TIMING LSB 101011TIMING MSB 11XXXXNOT USED

X X X 1 1 1 STATUS

PROCCLK

DATARDY

(I/Q SELECTED)

DATARDY

φ SELECTED)

(R/

INTRRP

WRITES TO SNAPSHOT

RAM

I/Q

R/ DELAY TO DATARDY DEPENDS ON LENGTH OF FIR IF FREQ CHOSEN

IQR

FIGURE 42. RAM LOAD SEQUENCE

Snap Shot Operation

The snapshot mode takes sets of adjacent samples at programmed intervals. It is provided for tracking algorithms that do not require processing of every sample, but do require sets of adjacent samples. For example, bit sync algorithms have narrow loop bandwidths that may not need to be updated every sample. Computing the bit phase may require 4 adjacent samples at 2 times the baud rate. The snapshot mode allows the processor to implement the tracking algorithms for high speed data without having to handle every data sample.

The interval from the start of one snapshot to the start of a second snapshot isprogrammed into bits 11-4 (where bit 11 is the MSB) of Control Word 21. The actual interval is the

value programmed plus 1. If bits 11-4 = 11111111, then the interval is set to 256. If sample sets are to be taken every 4 samples, then bits 11-4 = 00000011.

Figure 43 shows the relationship between the snapshot samples and the snapshot interval.

ADJACENT

SAMPLES

01234

# SAMPLES = 4

INTERVAL = 64

FIGURE 43. SNAP SHOT SAMPLING

6362

64 65

3-41

Page 90

HSP50214B

The PDC begins to ﬁll the buffer each time an interval number of samples have passed. The number of sample sets the PDC writes into the buffer and is programmed into bits 3-0 of Control Word 21. The number of samples stored is the programmed value and may be from 1 to 8 sample sets. A sample set consists of I, Q, |r|, φ and ƒ.

In snap shot operations, the buffer is read the same as for FIFO operations. Figures 37 and 39 describe the Design Blocksand Timingrequired to output data on AOUT(7:0)and BOUT(7:0). Table 17 summarizes the selectable output signals. The method for reading data through the Microprocessor Section in snap shot modeis identical to the method described in the FIFO mode subsection and the Microprocessor Read Section.

Avoiding Timing Pitfalls When Using the Buffer RAM Output Port

In snapshot mode, the whole buffer is written whenever the interval counter has timed-out. After time-out, old data can be written over. Thus, the data contained within the buffer must be retrieved before time-out to avoid data loss.

It may be desirable to disable the controlling microprocessor during read cycles to avoid the generating extra interrupts.Figure 44details howthe WRITE address can trigger extra interrupts. Care must be taken to either read sufﬁcient data out of memory or RESET the addressing to ensure that a complete set of data is the cause of the interrupt.

INTRRP

WRITE

ADDRESS

WR RD WR

A COMPLETE SET OF 3 DATA SAMPLES IS IN MEMORY AT INTRRP

A: NORMAL READ/WRITE SEQUENCE

INTRRP

WRITE

ADDRESS

WR RD WR

THE THIRD INTERRUPT HAS ONLY 1 NEW DATA ENTRY

B: FALSE TRIGGERED INTERRUPT READ/WRITE SEQUENCE

FIGURE 44. AVOIDING FALSE INTRRP ASSERTIONS

INTRRP

(INSTEAD OF 3) ATINTRRP

INTRRPT into the

INTRRP

WR RD

REEST

INTRRP

TIME

Microprocessor Write Section

The Microprocessor Write Section uses an indirect addressing schemewhere a 32-bit dataword is firstloaded in a four 8-bit byte master registers using f our writes via C(7:0). The desired destination register address is then written to another address using C(7:0). Writing this address triggers a circuit that generatesa pulse,synchronous toclock, that loads the Destination Register.The synccircuits anddata wordsare synchronized to different clocks , CLKIN or PROCCLK, depending on the Destination Registers.

A(2:0) determines the destination for the data on bus, C(7:0). Table19 showsthe addressmap for microprocessorinterface. Figure 45 shows the Control Register loading sequence. The data in C(7:0) and address map in A(2:0) is loaded into the PDC on the rising edge of WR and is latched into the Master Register on the rising edge of WR and A(2:0) = 100. Four clocks must pass before loading the next Control Word to guarantee that the data has been transferred.

Some registers can be loaded (i.e., transferred from the Master Registerto a Configuration Register or from aHolding Register to an active register) by initiating a sync. F or example, to load the A GC Gain, the value of the AGC gain is first loaded into the Holding Registers, then a transfer is initiated b ySYNCIN2 ifControl Word8, Bit 29= 1.This allows the AGCgain to be loaded b ydetecting a system e vent, such as a start of a new burst. Bit 20 of Control Word 0 has the same effect on the Carrier NCO center frequency for assertion of SYNCIN1, except it transfers from a dedicated holding register - not the Master Register.

TABLE 19. DEFINITION OF ADDRESS MAP

A2-0 REGISTER DESCRIPTION

0 Holding Register 0. Transfers to bits 7-0 of the 32-bit Des-

tination Register. Bit 0 is the LSB of the 32-bit register.

1 Holding Register1. Transfers to bits 15-8 of a 32-bit Desti-

nation Register.

2 Holding Register2. Transfers tobits 23-16of a32-bit Des-

tination Register.

3 Holding Register3. Transfers tobits 31-24of a32-bit Des-

tination Register. Bit 31 is the MSB of the 32-bit register.

4 This is the Destination Address Register. On the fourth

CLK following a write to this register, the contents of the Holding Registers are transferred to the Destination Register. All 8 bits written to this register are decoded into the Destination Register Address. The conﬁguration destination address map is given in thetables inthe ControlWord Section.

5 Selects data sourcefor reading.See MicroprocessorRead

Section.

Suppose a(0018D038)H needsto beloaded intoControl Word 0, then Table 20 details the steps to be taken.

3-42

Page 91

HSP50214B

TABLE 20. EXAMPLE PROCESSOR WRITE SEQUENCE

STEP A(2:0) C(7:0) COMMENT

1 000 0011 1000 Loads 38 into Master Register

(7:0) on rising edge of WR.

2 001 1101 0000 Loads D0 into Master Register

(15:8) on rising edge of WR.

3 010 0001 1000 Loads 18 into Master Register

(23:16) on rising edge of WR.

4 011 0000 0000 Loads 00 into Master Register

(31:24) on rising edge of WR.

5 100 0000 0000 Load “0018D038” into Conﬁgu-

ration Control Register 0.

6 Wait 4 CLKS.

CLK =

(PROCCLK,

CLKIN)

A2-0

C7-0

01234

LSB MSB

ADD

PROCLK

A2-0

C7-0

LOAD ADDRESS

OF TARGET

CONTROL REGISTER

READ CODE C(2:0)

THREE-STATE

INPUT BUS

READ ADDRESS

OUTPUT DATA C(7:0)

ASSERT

TO ENABLE DATA

OUTPUT ON C0-7

FIGURE 46. READINGTHE CONTROL REGISTERSUSING A

LATCH CODE EQUAL TO A 5, A READ ADDRESS AND A READ CODE

TABLE 21. PROCESSOR READ SEQUENCE (INPUT LEVEL

SELECTOR)

STEP A(2:0) C(7:0) COMMENT

1 101 100 Write Read Code, 100 to

Address 5, WR pulled high to

2 000 1111 1000

generate rising edge. Drop RD low, Read AGC LSB.

(F4)H

LOAD

CONFIGURATION

DAT A

LOAD ADDRESS OF

TARGET CONTROL

WAIT 4 CLKs

LOAD NEXT

CONFIGURATION

FIGURE 45. LOADING THECONTROL REGISTERS WITH

32-BIT CONTROL WORDS

Microprocessor Read Section

The microprocessor read uses both read and write procedures to obtain data from the PDC. A write must be done to location 5 to select the source of data to be read. The read source is determined by the value placed on the lower three bits of C(7:0). The output from a particular read code isselected using a read address placed onA(2:0). The output is sent to C(7:0) on the falling edge of

If the Read Address is equal to 111, the Read Code is ignored, and the status bits shown in Table 22 in the Output Section is sent to C(7:0). Thisstate was providedso that the user could obtain the status bits quickly.

Refer to the Timing Diagram in Figure 46. Suppose the input level detector has a hex value of (321AF5)H, then Table 21 details the steps to be taken.

RD.

3 001 0001 1010

(1A)H

4 010 0011 0010

(32)H

TABLE 22. DEFINITION OF ADDRESS MAP

READ

CODE C(2:0)

STATUS

TYPE READ ADDRESS A(2:0)

000 Buffer

RAM Iand Q

001 Buffer

RAM Output (|r| and φ)

010 Buffered

Frequency

011 Not Used 100 InputLevel

Detector

Pull RD high, then drop low, Read AGC NLSB.

Pull RD high, then drop low, Read AGC MSB.

000- I LSB. 001- I MSB. 010- Q LSB. 011- Q MSB. See Output Section.

000- MAG LSB (7-0). 001- MAG MSB (15-8). 010- PHASE LSB (7-0). 011- PHASE MSB (15-8). See Output Section.

000- FREQ LSB. 001- FREQ MSB. See Output Section.

Input AGC 000- input AGC LSB (0-7). 001- input AGC NLSB (8-15). 010- input AGC MSB (16-23).

3-43

Page 92

HSP50214B

TABLE 22. DEFINITION OF ADDRESS MAP (Continued)

READ

CODE C(2:0)

101 AGC Data

110 Not Used 111 Not Used

Don’t Care Status 111- Status (6:0) consisting of

STATUS

TYPE READ ADDRESS A(2:0)

AGC(mustwrite to location10 to samandTiming Error

ple)

000- AGC LSB(lower 8 bitsof linear

Control Word 3 used by multiplier)

mmmmmmmm LSB.

001- AGC MSB (4 shift control bits

and first three bits of linear) Control

Word oeeeemmm MSB. This yields

11 bits ofthe linear controlmantissa.

010- Timing error LSB, not stabi-

lized.

011- Timing error MSB, not stabi-

lized.

(6:4)-FIFO depth when output is in

FIFO Buffer RAM Output Mode.

(3)-EMPTY signalling the FIFO is

empty and the read pointer cannot

be advanced (Active High).

(2)-FULL signalling the FIFO is full

and new samples will notbe written

(Active High).

(1)-READYB Output buffer has

reached the programmed threshold

in FIFO mode or the programmed

numberof samples havebeen taken

in snapshot mode. (Active Low).

(0)-INTEGRATION has been com-

pleted in theinput level detectorand

is ready to be read. (Active High).

Applications

Composite Filter Response Example

For this example consider a total receive band roughly 25MHz wide containing 124 200kHz wide FDM channels as shown in Figure 47.The designgoal forthe PDCis to tune to and ﬁlter out a single 200kHz FDM channel from the FDM band, passing only baseband samples onto the baseband processor at a multiple of the 270.8 KBPS bit rate.

124 CHANNELS

•

••

FREQUENCY

200kHz

CHANNEL

FREQUENCY

FIGURE 47. RECEIVE SIGNAL FREQUENCY SPECTRUM

RF/IF Considerations

The input frequency to the PDC is dependent on the A/D converter selected, the RF/IF frequency, the bandwidth of interest and the sample rate of the converter. If the A/D converter has sufﬁcient bandwidth, then undersampling techniques can be used to downconvert IF/RF frequencies as part of the digitizing process, using the PDCto process a lower frequency alias of the input signal.

For example, a 70MHzIF can besampled at 40MHzand the resulting 10MHz signal alias can be processed by the PDC to perform thedesired downconversion/tuning andﬁltering. If the IF signal is less than 1/2 the sample frequency then standard oversampling techniques can be used to process the signal.Of thetwo techniques, only undersampling allows part of the down conversion function to be brought into the digital domain just through sampling, assuming that a sampling frequency can be found that keeps the alias signals low and that the A/D converter has the bandwidth to accept the unconverted analog signal.

3-44

Page 93

HSP50214B

PDC Conﬁguration

For this example, the PDC is conﬁgured as follows:

CLKIN: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39MHz

Mode: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Gated

Input Format: . . . . . . . . . . . . . As required by Digital Source

Carrier NCO Fc: . . . . . . . .As determined by Channel Freq.

Carrier NCO Phase Offset: . . . . . . . . . . . . . . . . . . . . . . . . .0

Carrier NCO Offset Frequency: . . . . . . . . . . . . . . . .Disabled

CIC Filter: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enabled

Decimation: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

PROCCLK:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28MHz

Half Band Filters: . . . . . . . . . . . . . . . . . . HB3 and 5 Enabled

FIR Filter: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gsmtemp ﬁle

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . f

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Decimation = 1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Passband: 90kHz

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transition Band: 25kHz

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Passband Atten: 3dB

. . . . . . . . . . . . . . . . . . . . . . . . . Stop Band Atten: 111.25713

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .FIR Order: 90

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIR Symmetry: Even

Resampling Filter: . . . . . . . . . . . . . . . . . . . . . HB1 Enabled

= 541.667kHz

References

For Intersil documents available on the web, see http://www.intersil.com/ Intersil AnswerFAX (321) 724-7800.

[1] HSP50210Data Sheet,Intersil Corporation,AnswerFAX

Doc. No. 3652.

[2] CellularRadio andPersonalCommunications: ABook of

Selected Readings, Theodore S. Rappaport, 1995 by IEEE, Inc.

[3] AN9720Application Note,Intersil Corporation,

“Calculating Maximum Processing Rates of the PDC (HSP50214B)”, AnswerFAX Doc. No. 99720.

[4] FO-007 Block Diagram of HSP50214.

The basis for this conﬁguration is:

Sampling Rate: Select a high rate PROCCLK Output Rate: 1.083MHz (4x Bit Rate; 8x Baud Rate) CIC Filtering: Primarily Rate Reduction (39/18 = 2.166MHz). HB Filtering: Flat passband with rate reduction by 4 - low

enough (541.66kHz) for sufﬁcient FIR Taps to be used. FIR Filtering: Primary shaping ﬁlter/set ﬁnal out of band

suppression. Polyphase/HalfBand Filtering: Interpolate by twoto output

8x baud rate or 4x bit rate. The CIC and halfband ﬁlter responses are shown in Figures

48A and B. The composite filter response constrained primarily by

halfband filter 5 and the FIR filter, are shown in Figure49A-C. For a more detailed discussion of design approaches and

trades when designing with the PDC, refer to AN9720[3], “Calculating the Maximum Processing Rates of the PDC”.

3-45

Page 94

HSP50214B

-10

-30

-50

-70

MAGNITUDE (dB)

-90

-110 fS = CIC INPUT RATE

-130

-10

-30

-10

-30

-50

-70

MAGNITUDE (dB)

-90

-110 fS = CIC INPUT RATE

FREQUENCY

-130

FREQUENCY

FIGURE 48A. CIC FILTER RESPONSE FIGURE 48B. HB3 FILTER RESPONSE

fS = CIC INPUT RATE

-10

-30

-50

-70

MAGNITUDE (dB)

-90

-110

-130

-50

-70

MAGNITUDE (dB)

-90

-110

fS = CIC INPUT RATE

FREQUENCY

-130

FREQUENCY

FIGURE 49A. HB5 FILTER RESPONSE FIGURE 49B. 255 FIR TAP FILTER RESPONSE

fS = CIC INPUT RATE

-10

-30

-50

-70

MAGNITUDE (dB)

-90

-110

-130 FREQUENCY

FIGURE 49C. COMPOSITE FILTER RESPONSE

FIGURE 49D. PDC FILTER FREQUENCY SPECTRUMS EXAMPLE (NORMALIZED TO SAME SCALE)

3-46

Page 95

HSP50214B

Conﬁguration Control Word Deﬁnitions

Note that in the Configuration Control Register Tab les , some of the available 32 bits in a Control Word are not used. Unused bits do not need to be written to the Master Register. If thedestination only has16 bits,then only 2bytes needto be written to the Master Register. Figure 45 details the timing for

CONTROL WORD 0: CHIP CONFIGURATION, INPUT SECTION, CIC GAIN (SYNCHRONOUS TO CLKIN)

BIT

POSITION FUNCTION DESCRIPTION

31-21 Reserved Reserved.

proper operation of the Microprocessor Write Section. Bits identified as “Reserved” should be programmed to a zero.

NOTE: CLKIN or PROCCLK must be present to properly load

control words. Note in the header which is applicable.

20 Carrier NCO External

Sync Enable

19 CIC External Sync

Enable

18 Input Format 0- Two’s Complement Input Format.

17 Input Mode 0- Input operates in Gated Mode.

16-13 CIC Shift Gain These bits control the barrel shifter at the input to the CIC ﬁlter. These bits are added to the

12-7 CIC Decimation

Counter Preload

6 CIC Bypassed Active high, this bit routes the output of the input shifter to the output of the CIC with no ﬁltering.

0- The SYNCIN1 pin has no effect on the Carrier NCO. 1- When the SYNCIN1 pin is asserted, the carrier center frequency and phase are updated from the holding registers to the active register. Also, if bit 0 of this word is active, the carrier phase accumulator feedback will be zeroed to set the Carrier NCO to a known phase, allowing the NCOs of multiple parts to be initialized and updated synchronously.

0- The SYNCIN1 pin has no effect on the CIC ﬁlter. 1- When the SYNCIN1 pin is asserted, the decimation counter is loaded, allowing the decimation counters inmultiple chips to be synchronized. When CW27 bit-22 isset to a 1, SYNCIN1will reset both front end and back end circuitry.

1- Offset Binary Input Format.

1- Input operates in Interpolated Mode.

GAINADJ(2:0)pins to determinethe total shift.The sumis saturatedat 15.See theCIC DecimationFilter Section for values to be programmed in this ﬁeld based on CIC ﬁlter Decimation. Bit 16 is the MSB. SG = Floor [39 - (number of input bits) - 5log2(R)] for 4 < R < 31 SG = 15 for R = 4. SG = 0 for R = 32.

These bitscontrol the decimation in the CIC ﬁlter. Programthis ﬁeld to R-1, whereR is the desired decimation factor in the ﬁlter. The decimation factor range is 4-32. See CIC Filter Section for effective decimation range relative to the CIC Shift Gain value. Bit 12 is the MSB. While this ﬁeld allows values from 0 - 63, the valid values are in the range from 4- 32.

When the CIC ﬁlter is bypassed, CLKINmust beat leasttwice theinput samplerate (ENI should be toggled to achieve this). When the CIC ﬁlter is bypassed, the bottom 24 bits of the barrel shifter output are routed to the halfband ﬁlters.

5-4 Number of Offset

Frequency Bits

3 Syncout CLK Select This bit selects whether the SYNCOUT signal is generated from CLKIN of from PROCCLK

2 Clear Phase Accum 0- Enable accumulator in Carrier NCO.

1 Carrier NCO Offset

Frequency Enable

0 Carrier NCO Load

Phase Accum On Update

00 - 8 bits. 01 - 16. 10 - 24. 11 - 32.

0- CLKIN. 1- PROCLK.

1- Zero feedback in accumulator. When set to 1, this bit enables the offset frequency word to be added to the center frequency Control

Word. The offset is loaded serially via the COF and COFSYNC pins. When this bit is set to 1, the µP update to the Carrier NCO frequency or an external carrier NCO load

using SYNCIN1 willzero thefeedback of thephase accumulator, as wellas updatethe phaseor frequency. This function can be used to set the NCO to a known phase synchronized to an external event.

3-47

Page 96

HSP50214B

CONTROL WORD 1: INPUT LEVEL DETECTOR (SYNCHRONOUS TO CLKIN)

BIT

POSITION FUNCTION DESCRIPTION

31 Reserved Reserved. 30 Integration Mode 0- Integration of magnitude error stops when the interval counter times out.

1- Integration runs continuously. When theinterval counter times out, theintegrator reloads,and theresults of the integration is sent to a register for the processor to read.

29-14 Integration Interval These are the top 16 bits of the 18-bit integration counter, ICPrel. ICPrel = (N)/4+1; where N is the de-

siredintegration period inCLKIN cycles,deﬁned asthe numberof inputsamples tobe integrated.N must

be a multiple of 4: [0, 4, 8, 12,16.... , 218]. Bit 29 is the MSB. If the input is interpolated, then the zeros

must be accounted for, as they will be added to the threshold! If the gatedinput modeis used,the same input sample will be accumulated multiple times.

13-0 Input Threshold Input Magnitude Threshold. Bits 12-0correspond toinput bits12-0. The magnitude of the input isadded

to this threshold, where the threshold is a signed number. Bit 13 is the MSB.

CONTROL WORD 2: INPUT LEVEL DETECTOR START STROBE (SYNCHRONIZED TO CLKIN)

BIT

POSITION FUNCTION DESCRIPTION

N/A Start Input Level

Detector AGC Integrator

Writing to this location starts/restarts the input AGC error integrator. The integrator will either restart or stop when the integration interval counter times out depending on bit 30 of Control Register 1 (see Microprocessor Write Section).

CONTROL WORD 3: CARRIER NCO CENTER FREQUENCY (SYNCHRONIZED TO CLKIN)

BIT

POSITION FUNCTION DESCRIPTION

31-0 Carrier Center

Frequency

NOTE: In the HSP50214B, if the SYNCIN1 occurs when the NCO is not updating, the load signal is held internal to the part until the next NCO update.

CONTROL WORD 4: CARRIER PHASE OFFSET (SYNCHRONIZED TO CLKIN)

BIT

POSITION FUNCTION DESCRIPTION

31-10 Reserved Reserved.

9-0 Carrier Phase Offset Thesebits, PO, are used to offsetthe phase of the carrier NCO. The bits are computed by the Equation

CONTROL WORD 5: CARRIER FREQUENCY STROBE (SYNCHRONIZED TO CLKIN)

BIT

POSITION FUNCTION DESCRIPTION

N/A Carrier Frequency

Strobe

These bits control the frequency of the Carrier NCO. The frequency range of the NCO is ± fS/2 where fSis the inputsample rate.The bitsare computedby the equationN =(F This location isa holding register.After loading,a transfer tothe activeregister is doneby writing toControl Word 5 or by generatinga SYNCIN1 with Control Word0, Bit 20 set to 1. The CarrierNCO only updates ENI is active.

PO =INT[(210φ bit offset binaryrepresentation. Bit 9is the MSB.This locationis a holdingregister.After loading, atransfer to the active register is done by writing to Control Word 6 or by generating a SYNCIN1 with Control Word 0, Bit 20 set to 1. The carrier NCO only updates when ENI is active.

Writing to this address updates the carrier frequency Control Word from the Holding Register.

off

)/ 2π]

HEX

;(-π<φ

< π) for10-bit 2’s complement representation or from 0 to 2π for 10-

off

)*232. Bit 31is theMSB.

NCO/fS

CONTROL WORD 6: CARRIER PHASE STROBE (SYNCHRONIZED TO CLKIN)

BIT

POSITION FUNCTION DESCRIPTION

N/A Carrier Phase Strobe Writing to this address updatesthe carrier phase offset ControlWord with the value writtento the phase

offset (PO) register.

3-48

Page 97

HSP50214B

CONTROL WORD 7: HB, FIR CONFIGURATION (SYNCHRONIZED TO PROCCLK)

BIT

POSITION FUNCTION DESCRIPTION

31-22 Reserved Reserved.

21 Enable External

Filter Sync

20 Halfband (HB)

Bypass

19 HB5 Enable 0- Disables HB number 5 (the last in the cascade).

18 HB4 Enable Setting this bit enables HB filter number 4. 17 HB3 Enable Setting this bit enables HB filter number 3. 16 HB2 Enable Setting this bit enables HB filter number 2. 15 HB1 Enable Setting this bit enables HB filter number 1.

14-11 FIR Decimation Load decimation from 1-16, where 0000 = 16. Bit 14 is the MSB.

10 FIR Real/Complex 0- Complex Filter.

9 FIR Sym Type 0- Odd Symmetry.

8 FIR Symmetry 0- Symmetric Filters.

7-0 FIR Taps Number of taps in the FIR filter. Range is 1 to 255, where 0000000 is invalid.

0- The SYNCIN2 pin has no effect on the halfband and FIR filters. 1- When the SYNCIN2 pin is asserted, the filter control circuitry in the halfband filters, the FIR, the resampler, andthe discriminator are reset. SYNCIN2 can be usedto synchronize the computations of the filters in multiple parts for the alignment (see Synchronization Section).

1- Bypass Halfband Filters. 0- Enable HB Filters (at least one HB must be enabled).

1- Enables HB filter number 5.

0001 - 1 1001 - 9 0010 - 2 1010 - 10 0011 - 3 1011 - 11 0100 - 4 1100 - 12 0101 - 5 1101 - 13 0110 - 6 1110 - 14 0111 - 7 1111 - 15 1000 - 8 0000 - 16

1- Dual Real Filters.

1- Even Symmetry.

1- Asymmetric Filters.

CONTROL WORD 8: AGC CONFIGURATION 1 (SYNCHRONIZED TO PROCCLK)

BIT

POSITION FUNCTION DESCRIPTION

31-30 Reserved Reserved.

29 Sync AGC Updates to

SYNCIN2

28-16 Threshold The magnitudemeasurement outof thecartesian to polar converter is subtracted from this value to get

15-12 Loop Gain 1

Mantissa

11-8 Loop Gain 1

Exponent

7-4 Loop Gain 0 Mantissa Selected whenAGCGNSEL = 0.These bits areMMMM. Seedescription for bits15-12. Same equations

3-0 Loop Gain 0

Exponent

When this bitis 1,the SYNCIN2pin loads thecontents ofthe master registersinto theAGC accumulator.

the gain error.A gainof 1.647 in the cartesianto polar conversion that mustbe takeninto account when computing this threshold. These bits are weighted -22 down to 2

Selected whenAGCGNSEL =1. Thesebits, MMMM,together with the exponent bits, EEEE (11-8), set the loop gain for the AGC loop. The gain adjustment per output sample is:

1.5dB (Threshold -[Magnitude * 1.6]) 0.MMMM * 2 and the threshold is programmed in bits 28-16. The decimal value for the mantissa is calculated as DEC(MMMM)/16. Bit 15 is the MSB.

Selected whenAGCGNSEL =1. Thesebits are EEEE. See description of bits 15-12. Bit11 isthe MSB.

are used for Loop 0. Bit 7 is the MSB. Selected whenAGCGNSEL = 0. These bits are EEEE.See description for bits 15-12. Same equations

are used for Loop 0. Bit 3 is the MSB.

-(15 - EEEE)

-10

. Bit 28 is the MSB.

where magnitude ranges from 0 to 1.414

3-49

Page 98

HSP50214B

CONTROL WORD 9: AGC CONFIGURATION 2 (SYNCHRONIZED TO PROCCLK)

BIT

POSITION FUNCTION DESCRIPTION

31-28 Reserved Reserved. 27-16 Upper Limit Maximum Gain/MinimumSignal. Theupper fourbits are used for exponent; the remaining bits form the

mantissa in the fractional offset binary: [eeeemmmmmmmm].See theAGC Sectionfor details. Bit 27 is the MSB. The gain is in dB. G = (6.02)(eeee) + 20log10(1.0 + 0.mmmmmmmm)

eeee = Floor [log mmmmmmmm = Floor [256(10

15-12 Reserved Reserved.

11-0 Lower Limit Minimum Gain/MaximumSignal. Theupper fourbits areused forexponent; theremaining bitsform the

mantissa in the fractional offset binary: [eeeemmmmmmmm].See theAGC Sectionfor details. Bit 11 is the MSB. The gain is in dB. G = (6.02)(eeee) + 20log10(1.0 + 0.mmmmmmmm)

eeee = Floor [log mmmmmmmm = Floor [256(10

CONTROL WORD 10: AGC SAMPLE GAIN CONTROL STROBE (SYNCHRONIZED TO PROCCLK)

BIT

POSITION FUNCTION DESCRIPTION

N/A Sample AGC Gain

Writing to this location samples the output of the AGC loop filter to stabilize the value for µP reading.

Level

(10

GAIN dB/20

)]

GAIN dB/20/2eeee

)]

GAIN dB/20/2eeee

- 1)]

CONTROL WORD 11: TIMING NCO CONFIGURATION (SYNCHRONIZED TO PROCCLK)

BIT

POSITION FUNCTION DESCRIPTION

31-6 Reserved Reserved.

5 Enable External

Timing NCO Sync

0- SYNCIN2 has no effect on the timing NCO. 1- When SYNCIN2 is asserted, the timingNCO centerfrequency andphase areupdated withthe value loaded intheir holding registers. If bit0 of this word isset to 1, the phaseaccumulator feedback is also zeroed.

4-3 Number of Offset Fre-

quency Bits

00 - 8 bits. 01 - 16. 10 - 24. 11 - 32.

2 Enable Offset

Frequency

1 Clear Phase

Accumulator

0 Timing NCO Phase

Accumulator Load On Update

0- Zero Offset Frequency to Adder. 1- Enable Offset Frequency.

0- Enable Accumulator. 1- Zero Feedback in Accumulator.

When this bit is set to 1, the µP update to the timing NCO frequency or an external timing NCO load using SYNCIN2 will zero the feedback of the phase accumulator as well as update the phase and frequency. This function can beused to set the NCOto a known phase synchronized to anexternal event.

CONTROL WORD 12: TIMING NCO CENTER FREQUENCY (SYNCHRONIZED TO PROCCLK)

BIT

POSITION FUNCTION DESCRIPTION

31-0 Timing NCO Center

Frequency

These bits control the frequency of the timing NCO.The frequency range of the NCO isfrom 0 to F

where F

SAMP

equation: N =(f

RESAMP OUT/FRESAMP

is the input sample rate to the resampling ﬁlter. The bits are computed by the

)*232. Bit 31 is theMSB. This location is a holding register. After loading, a transfer to the Active Register is done by writingto Control Word 14 or by generating a SYNCIN2with Control Word 11, Bit 5 set to 1.

RE-

3-50

Page 99

HSP50214B

CONTROL WORD 13: TIMING PHASE OFFSET (SYNCHRONIZED TO PROCCLK)

BIT

POSITION FUNCTION DESCRIPTION

31-8 Reserved Reserved.

7-0 Timing NCO Phase

Offset

CONTROL WORD 14: TIMING FREQUENCY STROBE (SYNCHRONIZED TO PROCCLK)

BIT

POSITION FUNCTION DESCRIPTION

N/A Timing Frequency

Strobe

CONTROL WORD 15: TIMING PHASE STROBE (SYNCHRONIZED TO PROCCLK)

BIT

POSITION FUNCTION DESCRIPTION

N/A Timing Phase Strobe Writing tothis addressupdates theactive timingNCOPhase Offset Registerin thetimingNCO (see Tim-

CONTROL WORD 16: RESAMPLING FILTER CONTROL (SYNCHRONIZED TO PROCCLK)

BIT

POSITION FUNCTION DESCRIPTION

31-12 Reserved Reserved.

11-4 Re-Sampler Output

Pulse Delay

3 Re-Sampler Bypass 0- Resampling Filter Enabled. A valid combination of bits 2-0 must also be selected.

These bits areused tooffset the phaseof theTiming NCO. Therange is 0to 1times the resampler input period interpretedeither as ±T/2(2’scomplement) or 0to T(offset binary).Bit 7 is theMSB.This location is a holding register. Afterloading, a transferto theActive Register is done bywriting toControl Word 15 or by generating a SYNCIN2 with Control Word 11, Bit 5 set to 1.

Writingto this address updatesthe activetiming NCO FrequencyRegister in thetiming NCO (seeTiming NCO Section).

ing NCO Section).

NOTE: These bits programthe delay between outputsamples when interpolating. The extra outputscan

be delayed from 2 to 255 clocks from the ﬁrst output. A delay of 2 equals 255 clocks of delay. A delay of 0 or 1 is aninvalid mode.When interpolating by 2, oneextra outputis generated; when interpolating by 4,3 extra outputsare generated.Program by theequation (PROCCLK/f Bit 11 is the MSB.

NOTE: If less than 5 is programmed, there will not be sufficient time to fully update the output

buffer. If less than16 isprogrammed, theserial outputmay be preempted.This meansthat it won’t finishand if the sync isprogrammed to followthe data,there may never bea sync.

1- Resampling Filter Section (including Interpolation halfband filters) is bypassed.

OUT

)-1.

2-0 Filter Mode Select;

2- HB2 Enabled 1- HB1 Enabled 0- Re-Sampler Enabled

3-51

000- Not Valid. 001- Re-Sampler Enabled. 010- Halfband 1 Enabled. 011- Re-Sampler and Halfband Filter 1 Enabled. 100- Not Valid. 101- Not Valid. 110- Both Halfband Filters Enabled. 111- Re-Sampler and Both Halfband Filters Enabled.

Page 100

HSP50214B

CONTROL WORD 17: DISCRIMINATOR FILTER CONTROL, DISCRIMINATOR DELAY (SYNCHRONIZED TO PROCCLK)

BIT

POSITION FUNCTION DESCRIPTION

31-17 Reserved Reserved. 16-15 Phase Multiplier These bitsprogram allow the phase output of the cartesian to polar converter to be multiplied by 1, 2, 4, or

8 (modulo 2π) to remove phase modulation before the frequency is measured. 00- No Shift on Phase Input to frequency discriminator. 01- Shift PhaseInput tofrequency discriminator up 1 (onebit), discarding the MSB andzero ﬁlling theLSB. 10- Shift PhaseInput tofrequency discriminatorup 2 (two)bits, discardingthe MSBand zeroﬁlling theLSB. 11- Shift PhaseInput to frequencydiscriminator up 3(three) bits ,discarding theMSB and zerofilling the LSB.

14 Discriminator Enable 0- Disable Discriminator.

1- Enable Discriminator.

13-11 Discriminator FIR

Decimation

10 FIR Symmetry Type 0- Odd Symmetry.

9 FIR Symmetry 0- Symmetric.

8-3 Number of FIR Taps Number of FIR taps from 1 to 63, where00000 isnot valid (00001= 1tap, 00010 = 2 taps,etc. upto 11111

2-0 Discriminator Delay Sets the number of delays from 1 to 8in the discriminator. Setdelay dddto delayminus 1, where 000 repre-

The decimation can be programmed from 1 to 8, where 000 = decimate by 8; 001= decimate by 1; 010 = decimate by2; 011 = decimate by 3; 100 = decimate by 4; 101 = decimateby 5; 110 = decimateby 6; and 111 - decimate by 7.

1- Even Symmetry.

1- Asymmetric.

= 63 taps). Bit 8 is the MSB.

sents 1 delay; 001 represents 2 dela ys, 010 represents3 delays,011 represents 4 delays, 100 represents 5 delays, 101 represents 6 delays, 110 represents 7 delays, and 111 represents 8 dela ys. If ddd the decimal representation bits 2-0, then the discriminator a transfer function H(Z) = 1-Z

-(ddd + 1)

CONTROL WORD 18: TIMING ERROR PRELOADS (SYNCHRONIZED TO PROCCLK)

BIT

POSITION FUNCTION DESCRIPTION

31-28 Reserved Reserved. 27-16 NCO Divide The Re-Sampler NCO output is divided down by the value loaded into this register plus 1. Load with a

value that is one less than the desired period. Bit 27 is the MSB.

11-0 Reference Divide The reference clock is divided down bythe valueloaded into this register plus 1. Load with avalue that

is one less than the desired period. Bit 27 is the MSB. A minimum preload of “I” is required.

CONTROL WORD 19: SERIAL OUTPUT ORDER (SYNCHRONIZED TO PROCCLK)

BIT

POSITION FUNCTION DESCRIPTION

31 Reserved Reserved.

30-28 Data Source for

SEROUTA

27-25 Data Source for

SEROUTB

24-21 NumberofSerialWord

Links in a Chain

20-18 Link Following I Data The serial data word, or link, following the I data word is selected using Table 12

Serial Output A Source. The serial data source is selected using Table 12 (see Output Section).

Serial Output B Source. The serial data source is selected using Table 12 (see Output Section).

This parameterdetermines thenumber ofSERSYNC pulsesgenerated. Itcan be set from 1 to 7. If this parametermatches the numberof serialwords thatare linkedtogether toform aserial outputchain, then there will be a syncpulse forevery wordin the serial output. In applications wherea processoris receivingthe serial data,it may bedesirable tohave a singleSERSYNC pulsefor the wholeserial outputchain, instead of a SERSYNC foreach wordin the data chain. Theprocessor thenparses out the various data words. As an example, if the I and Q are chained together and a single SERSYNC pulse is generated for this serialoutput chain,no ambiguity existsin theprocessor about whichtwo data samples(one from I and one from Q) are related.

(see Output Section).

3-52

Pentek 6210 Operating Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Date Rev Applicable Serial #’s Comments

08/14/98 Preliminary 9841001 − Forward 11/16/98 Preliminary 9841001 − Forward

2/18/99 Preliminary 9841001 − Forward

3/24/99 Preliminary 9841001 − Forward

6/24/99 Preliminary 9841001 − Forward

3/6/00 A 9841001 − Forward

3/9/00 A.1 9841001 − Forward

3/17/00 B 98041001 − Forward

3/21/00 B.1 98041001 − Forward

10/24/00 B.2 98041001 − Forward

4/5/01 C 98041001 − Forward

Initial release.

WARRANTY

COPYRIGHT INFORMATION

Chapter 1: Overview

Chapter 2: Installation and Connections

Chapter 3: Memory Map and Register Descriptions

Appendix E: Configuration EEPROM Format

Appendix F: Application Note

Chapter 1: Overview

1.1 General Description

1.2 Input Section

1.3 A/D Converters

1.4 Digital Drop Receivers

1.5 Connection to VIM Motherboard

1.6 Simplified Block Diagram

1.7 Specifications

1.7 Specifications (continued)

1.7 Specifications (continued)

Chapter 2: Installation and Connections

2.1 Inspection

2.2 Jumper Blocks

2.3 Model 6210 Front Panel Features

2.3.1.1 Duty Cycle Sensitivity

2.3 Model 6210 Front Panel Features (continued)

2.3.1 External Clock Input (continued)

2.3.1.1 Duty Cycle Sensitivity (continued)

2.3 Model 6210 Front Panel Features (continued)

2.3.1 External Clock Input (continued)

2.3.1.1 Duty Cycle Sensitivity (continued)

2.3.3 Indicator LEDs

2.3 Model 6210 Front Panel Features (continued)

2.3.3 Indicator LEDs (continued)

2.4.1 Signals for Synchronizing Multiple Boards

2.4.1.1 MCLK, MCLK

2.4.1.2 PRCLK, PRCLK

2.4.1.2 PRCLK, PRCLK (continued)

2.4.1.3 MSYNC, MSYNC

2.4.1.4 SYNC1, SYNC1

2.4.1.5 SYNC2, SYNC2

2.4.2 Serial Port Signals

2.4.2 Serial Port Signals (continued)

1) #1 Phillips screwdriver

2.5.1 Preparing the VIM Module for Installation

Chapter 3: Memory Map and Register Descriptions

3.1 Overview

3.2 Model 6210 Memory Map

3.4 Control Register (continued)

3.4.1 PROCCLK Frequency Divider (continued)

3.4 Control Register (continued)

3.7 Programmable Amplifier Gain (continued)

3.8.2 Pack Mode (continued)

3.8.2 Pack Mode (continued)

3.10.2 The Other Processor’s DDR (D1 = 1, D0 = 0)

3.10.3 The Processor’s Own DDR (D1 = 0, D0 = 1)

3.10 Serial Port Connection Register (continued)

3.10.4 Not Connected (D1 = 0, D0 = 0)

3.12 Processor Interface the HSP50214 DDR