Pentek 53661 Getting Started Manual

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Page 1

GETTING STARTED GUIDE

MODEL 53661

4−Channel 200 MHz A/D

with four Digital Down−Converters

Cobalt

Family VPX Board

Manual Part Number: 820.53661 Rev: 2.2 - June 12, 2014

Setting the Standard for

Digital Signal Processing

Pentek, Inc.

One Park Way

Upper Saddle River, NJ 07458

(201) 818-5900

www.pentek.com

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Page 2 Model 53661 Getting Started Guide

Manual Revision History

Date Revision Comments

2/3/11 Preliminary Initial Release 3/21/11 Preliminary GateFlow FPGA Design Kit, added information about the flashload utility. 7/25/11 Preliminary Added battery information to What’s in the Box? Added 800.71601 to Documentation

Required for Installation and Documentation for This Product.

3/20/12 1.0 Timing and Synchronization, 2 − Added a note about input limit. Revised for 5306 carrier.

11/26/12 1.1

9/19/13 1.2

12/11/13 1.3

1/28/14 2.0

4/30/14 2.1

6/12/14 2.2

Added hex key to What’s in the Box? Added JTAG PCB information to Installing the Hardware and GateFlow FPGA Design Kit.

Note added to What’s in the Box? and Installing the Hardware.

Revised What’s in the Box?

Added information about Options 104 and 105 to FPGA Digital Interfaces.

Removed the battery and battery installation instructions from What’s in the Box? because the battery now ships installed in Model 53661.

Added JTAG board to What’s in the Box?

Trademarks

Pentek, Cobalt, GateFlow, and ReadyFlow are registered trademarks of Pentek, Inc.

PCI Express and PCIe are registered trademarks of PCI−SIG. Linux is a registered trademark of Linus B. Torvaids. Microsoft and Windows are trademarks or registered trademarks of Microsoft Corporation. Xilinx, Virtex−6, Foundation ISE ,iMPACT, and Platform Cable USB are registered trademarks of Xilinx Inc.

Printed in the United States of America.

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Model 53661 Getting Started Guide Page 3

What’s in the Box?

Your shipment of the Pentek Model 53661 should include the items on the following list. If anything is missing or damaged, contact Pentek immediately at (201) 818−5900. Please save the shipping container and packing material in case reshipment is required.

Quantity

Part Number Description

002.53661

Model 53661 Board (consisting of a Model 71661 mounted on a Model 5306 Carrier)

1 002.71504 Terminator Board

1 004.71605 JTAG Board

2 385.30150 Screws for JTAG Board

1 807.71605 Instruction Sheet for JTAG Board

3 353.02607 26−Pin Socket for Ribbon Cable (Sync)

2 feet 378.62602 26−Conductor Ribbon Cable, 30GA 025 (Sync)

2 356.00015 Shorting Plugs

1 900.10153 Hex Key, 3/32” (Options 703 and 763 only)

1 808.53661 Instruction Manual Kit (all included manuals)

The list above includes all the standard parts that are shipped with the Pentek Model

53661. The options for this product are described in this Getting Started Guide and in the Pentek Model 53661 Installation Manual (included in the box).

NOTE:

If your Model 53661 has Option 741, you must use a 5HP width (1") VPX slot. Refer to the Model 53661 Installation Manual for details.

Rev. 2.2

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Introduction

This document describes the Pentek Model 53661 Cobalt® Family VPX board, its asso− ciated software, what to consider before installation, and installation steps.

Before You Begin: Description of Hardware

Pentek’s Cobalt Family Model 53661 is a multichannel, high−speed data converter. Using the 3U VPX card format, the Model 53661 includes four 200−MHz, 16−bit A/D converters and four Digital Down−Converters (DDCs).

The Pentek Model 53661 consists of one Pentek Model 71661 XMC module mounted on a Pentek Model 5306 VPX carrier, assembled and tested as a single board. It is ready to plug into a chassis with a single 3U VPX slot. The Model 5306 carrier features built−in support for PCI Express

(PCIe®).

The Pentek Model 53661 Installation Manual (800.53661) provides installation instructions for the Model 53661, and the Pentek Model 71660 Operating Manual (800.71660) and Pen− tek Model 71661 Addendum Manual (800.71661) describe the operation and programming of the Pentek 71661 XMC module.

Before You Begin: Consider the VPX Backplane

The Pentek Model 5306 carrier is designed to operate in VPX systems. Before installing the Model 53661, you will need to know or consider the following:

 Is your VPX backplane connection x4 or x8 PCIe? The Model 53661 offers two

backplane choices: Gen 1 x8 PCIe and Gen 2 x4 PCIe.

 The slot characteristics can vary between slots in the same chassis, so you need to

know the characteristics for the slot you select and choose a configuration accordingly using SW4:1−4 and SW5:4 as described in the Model 53661 Installation Manual. If you need a different configuration other than what is described in Section

2.8.3 of the Model 53661 Installation Manual, contact Pentek.

 The Model 71661 XMC module is shipped to boot with the Gen 1 x8 PCIe default

FPGA code. If you want a different default, see Section 2.4.2 of the Model 53661 Installation Manual.

Rev. 2.2

 Ensure that the VPX chassis has enough cooling and power capabilities for the

number of installed modules. Refer to the specifications in Section 1.6 of the Model

53661 Installation Manual.

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Model 53661 Getting Started Guide Page 5

Before You Begin: Jumper and Switch Settings

As shipped from the factory, all jumpers and switches are set in default positions on the Pentek Model 53661. The default operating parameters they select may or may not meet your requirements. Therefore, consider the following before installation:

Pentek Model

 FPGA MGT Clock Operation: Primary and secondary PCIe clock frequency,

auxiliary MGT clock frequency, secondary PCIe clock disable, auxiliary MGT clock disable, and primary and secondary PCIe clock source

 FPGA Configuration: FLASH write protect, FPGA configuration enable, FPGA

configuration select (must agree with setting for Crosspoint Switch Routing, below: x4 or x8), configuration select enable, XMC JTAG enable, JTAG chain mode

For example, Switch SW1−1 allows you to change the setting for the primary PCIe clock frequency from 250 MHz (the factory default) to 100 MHz.

To preview the 71661 XMC module switch settings you’ll need to consider for the Model 53661, refer to Section 2.4 of the Model 53661 Installation Manual.

NOTE:

Pentek Model 5306 Carrier PCB Jumpers

There are no user−settable jumpers on the 5306 carrier.

71661 XMC Module Switches

The Model 53661 module is shipped to boot with the Gen 1 x8 PCIe default FPGA code. If you want a different default, see Section 2.4.2 of the Model 53661 Installation Manual.

Pentek Model 5306 Carrier PCB Switches

 Crosspoint Switch Routing: Selects a user configuration stored in onboard Flash

memory. The selected configuration will load from memory on power−up for the crossbar switch routing. Five default configurations are available for the Model 53661, as described in Section 2.8 of the Model 53661 Installation Manual. This setting must agree with the Model 71661 FPGA configuration setting (see above).

To preview the jumper and switch settings you’ll need to consider for the 5306 carrier PCB, refer to Sections 2.7 and 2.8 of the Model 53661 Installation Manual.

Rev. 2.2

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Before You Begin: Description of Software

Board Support Software for the Pentek Model 71661 XMC

Pentek’s ReadyFlow® Board Support Packages (BSP) contain software support for the

Model 71661 XMC. This includes a device driver for the 71661, plus the ReadyFlow Board Support Library data structures and routines. The following available BSPs allow high−level programming for various workstation platforms. Refer to the User’s Guide indicated for each platform:

• Model 4994A Option 166 ReadyFlow BSP for Linux

• Model 4995A Option 166 ReadyFlow BSP for Windows

Pentek’s ReadyFlow

for the Model 71661 XMC. Refer to the Programmer’s Reference for Models 71660, 71661, and 71662 (801.71660).

Board Support Libraries contain a set of C−language routines

(816.71660)

(815.71660)

Software for the FPGAs

The FPGA is supported with a Pentek GateFlow® FPGA Design Kit. The GateFlow Design Kit (Model 4953 Option 661) facilitates user−installed FPGA functions using the Xilinx ISE Foundation tool suite. The FPGA Design Kit allows the user to modify, add to, or replace the default logic functions within the FPGA with functions of his or her own definition.

Note that GateFlow is a very specialized software package intended for users with experience in FPGA logic programming. This package may not be required if your application needs are met with the Pentek−default FPGA code.

Refer to the following GateFlow software documentation: Pentek Model 4953−661 User Manual: Pentek Cobalt Model 71661 GateFlow User Manual (807.71661).

Rev. 2.2

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Model 53661 Getting Started Guide Page 7

Before You Begin: Consider the Product’s Options

Timing and Synchronization

The following timing and synchronization options are available for the Model 71661 XMC module’s A/D converters (all input/output signals are the same as defined for the standard Model 71660):

• Onboard VCXO and clock synthesizer: An onboard voltage controlled crystal oscillator (VCXO) and internal FPGA registers provide onboard sources for all sync, gate, and clock signals.

• External clock: The front panel has one SSMC coaxial connector, labeled CLK, for input of an external sample clock. The external clock signal must be a sine wave or square wave of +0 dBm to +10 dBm, with a frequency range from 10 to 500 MHz. The external clock input can be used as the sample clock for the A/D converters. This input is enabled using Sync Bus Control Register 1 (see the Model 71660 Operating Manual). The clock source selected by these bits is input to a CDC7005 Clock Synthesizer that generates separate output clocks, each programmable as sub− multiples of the input frequency. One of the CDC7005 output clocks (Y0) provides ADC timing.

NOTE:

• Trigger input: The front panel has one SSMC coaxial connector, labeled TRIG, for

input of an external trigger. The external trigger signal must be an LVTTL signal. The trigger input can be used as a gate or trigger for A/D signal processing. This input is enabled using Sync Bus Control Register 2 TTL SRC bits (see the Model 71660 Operating Manual).

NOTE:

• 26−pin sync bus front panel connector: This connector (labeled SYNC/GATE) provides clock, sync, and gate input/output pins for the Low−Voltage Positive Emit− ter−Coupled Logic (LVPECL) Sync Bus. It allows multiple modules to be synchronized. When the Model 71661 is a bus Master, these pins output LVPECL Sync Bus signals to other slave units. When the 71661 is a bus Slave, these pins input LVPECL signals from a bus Master. This connector also accepts two Low−Voltage TTL (LVTTL) Gate/ Sync inputs. For a description of the SYNC/GATE connector pin configuration, refer to the Model 53661 Installation Manual.

NOTE:

Ensure that the ADC clock never exceeds the ADS5485 rated clock speed during any change of frequency with the input clock signal.

The front panel TTL Gate and Sync signals are 5V tolerant but they must not have any negative voltage applied. They are terminated with a 392− ohm resistor to 3.3V and a 392−ohm resistor to ground.

When connecting LVPECL Sync Bus pins to additional Model 71661 modules, the LVPECL pins on the LAST unit must be terminated. Pentek includes a terminating board, part # 002.71504, with your shipment for this purpose.

Rev. 2.2

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FPGA Digital Interfaces

The 71661 features a Xilinx Virtex−6 FPGA for signal interfaces and processing. The FPGA is pre−configured with a four−channel digital down−converter IP core. This FPGA also provides board interfaces including PCIe and Aurora.

The FPGA is factory programmed by Pentek to implement the standard signal process− ing and control functions specified in the Model 71660 Operating Manual. The Pentek GateFlow shipped functions. Following are the options for custom I/O:

Option 104 − PMC Connector

The 5306 VPX carrier provides one 64−pin PMC connector, designated J14 on the car− rier PCB. These pins are directly wired from PMC J14 to the VPX P2 connector for user I/O.

Option 104 for the 71661 provides 40 pins (20 differential pairs) defined as 'User I/O' from the FPGA to PMC connector P14. These connections are programmed for low− voltage differential signals (LVDS) in the default FPGA configuration. Refer to the sup− plied Model 71660 Operating Manual for description of these signals.

FPGA Design Kit facilitates integration of user−created IP with the factory

Option 105 − XMC Connector

The 5306 VPX carrier provides two XMC connectors, designated J15 and J16 on the carrier PCB. J15 provides one x4 PCI Express link between the XMC and the carrier. J16 provides one x8 or two x4 serial links between the XMC and the carrier for 71661 Option 105 gigabit serial I/O.

The 5306 VPX carrier routes these data links from the XMC J15 and J16 connectors to the VPX P1 connector.

NOTE:

The P14 signals can be configured in the FPGA as either LVDS or LVTTL but in either case are limited to 2.5V and cannot be driven with a negative voltage.

NOTE:

Refer to Section 2.10.4 of the Model 53661 Installation Manual for the pin mapping of the VPX P1 connection and Section 2.10.5 for the pin mapping of the VPX P2 connections.

Four 200−MHz, 16−bit A/D converters provide data to the FPGA, where the data can be formatted, processed, or routed to board resources. The Model 71661 includes a Pentek−supplied FPGA IP Core with four multiband Digital Downconverters (DDCs) and a beamformer. Multiple 71661 modules may be linked together over an Aurora gigabit serial link to perform beamforming of up to 256 input channels.

Rev. 2.2

NOTE:

The Aurora serial interface for beamforming across multiple 71661 modules is not available with the Model 5306 carrier. The Model 53661 provides beamforming using the four onboard DDC channels.

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Model 53661 Getting Started Guide Page 9

FPGA Configurations

Following are the Xilinx Virtex−6 FPGA options for the Model 71661 XMC module:

 Option 061 FPGA is a Xilinx XC6VLX130T

 Option 062 is XC6VLX240T

 Option 063 is XC6VLX365T

 Option 064 is XC6VSX315T

 Option 065 is XC6VSX475T

The 71661 is shipped with a default set of logic functions for the FPGA, on FLASH memory. The 71661 loads the FPGA configuration from FLASH memory at power−up. Up to four FPGA configurations can be stored in FLASH, identified as Version 0, Ver− sion 1, Version 2, and Version 3. Versions 0 and 1 are the Pentek−supplied default boot configuration (0 is the Gen 1 x4 PCIe code, 1 is the Gen 2 x4 PCIe code) and Versions 2 and 3 are reserved for user−defined configurations.

Documentation Required for Installation

NOTE: Some manuals are used for more than one Pentek product. The manuals listed

below are all used for Model 53661.

• Pentek Model 53661 Installation Manual (800.53661): Describes the installation and connections for the Model 53661.

• Pentek Model 71660 Operating Manual (800.71660): Describes the operation and programming of the Model 71661 XMC module (a component of the Model 53661).

• Pentek Model 71661 Addendum Manual (800.71661): Describes any additions to the resources described in the Model 71660 Operating Manual for programming the DDC and Interpolator Core resources (the Model 71661 is part of the Model 53661).

• Installation and Getting Started Guide for the Pentek ReadyFlow software for the workstation platform you’re using (815.71660 for Windows, 816.71660 for Linux).

• Pentek Cobalt Model 71661 GateFlow User Manual (807.71661)

Rev. 2.2

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Step 1: Unpacking and Inspecting the Unit

After unpacking, inspect the unit carefully for possible damage to connectors or com− ponents. Refer to page 3 for a list of what should be in the box. If anything is damaged or missing, contact Pentek immediately at (201) 818−5900. Please save the shipping container and packing material in case reshipment is required.

Step 2: Checking the Jumper and Switch Settings

At the factory, all DIP switches and jumpers on the Model 53661 are installed in default positions. The default parameters selected may or may not meet your requirements.

As described above in Before You Begin: Jumper and Switch Settings, the switches and jumpers set FPGA MGT clock operation, FPGA configuration, XMC MVMRO, EEPROM write protect, PMC PCI/PCI−X modes, and crosspoint switch routing. Before installing your Model 53661, review Chapter 2 in the Model 53661 Installation Manual to determine whether you need to change any settings.

NOTE:

You should only change the jumpers or switches that are described in the Model 53661 Installation Manual − all others are reserved for factory use.

If you need to access certain jumpers on the VPX carrier, you must first remove the XMC module from the VPX carrier, as described in Section 2.3 of the Model 53661 Installation Manual.

Step 3: Installing the Hardware

The Model 53661 consists of one Pentek Model 71661 XMC module mounted on a Pen− tek Model 5306 3U VPX carrier. This carrier conforms to the 3U height VPX card format as per VITA 46.0 (VPX Baseline Standard specification).

To install the Model 53661, follow the procedure in Section 2.11 (Installing the Model 53661 in a VPX Card Cage) in the Model 53661 Installation Manual.

NOTE:

NOTE: The JTAG PCB on the Model 53661 board (on the Model 71661 XMC module)

If your Model 53661 has Option 741, you must use a 5HP width (1") VPX slot. Refer to the Model 53661 Installation Manual for details.

is used for downloading new FPGA configuration code. If you do not plan to use the JTAG PCB, you can remove it before installing Model 53661. If you do plan to use the JTAG PCB, you should remove it before you deploy the Model 53661 board.

Rev. 2.2

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Model 53661 Getting Started Guide Page 11

Step 4: Installing the Cabling

Connect a cable for each analog signal your application requires to the Pentek Model 71661 XMC front panel SSMC socket receptacles on the Pentek Model 53661. These are labeled IN 1, 2, 3, and 4: one for each ADC input channel.

The other cabling you install on the Model 53661’s front panel depends on how you want to handle timing and synchronization (see Timing and Synchronization). Several boards can be synchronized on the sync bus.

NOTE:

With Model 53661 Option 703, the front panel of the 71661 module is not available, as shown in the Model 53661 Installation Manual. Special connection hardware is available for the coaxial connectors on the 71661 front panel. Call Pentek for further information.

Step 5: Installing the Software

ReadyFlow Software

Pentek's ReadyFlow Libraries are software packages designed to provide software development tools for specific Pentek products on specific operating systems or plat− forms. The installation procedure is different for each platform:

− The installation steps can be summarized as follows:

Linux

• Installing ReadyFlow in a Linux system

• Installing WinDriver (required to run example programs)

• Building the ReadyFlow example programs

• Building the ReadyFlow board support libraries

For complete details, refer to Chapter 2 of the Model 4994A Option 166 User’s Guide (816.71660).

Windows the Model 53661 under Windows. The installation steps can be summarized as follows:

• Installing ReadyFlow in a Windows system

• Initializing the hardware (Model 53661) in Windows (responding to the New Hardware Wizard)

• Building the ReadyFlow example programs

• Building the ReadyFlow board support libraries

For complete details, refer to Chapter 2 of the Model 4995A Option 166 User’s Guide (815.71660).

− You must install the Pentek ReadyFlow package BEFORE you attempt to boot

Rev. 2.2

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Page 12 Model 53661 Getting Started Guide

GateFlow FPGA Design Kit

The following software and hardware is required to use the GateFlow FPGA Design Kit:

• Xilinx’s Foundation ISE (Version 12.1 or later − the design kit was produced using ISE Project Navigator Release 12.1, Application Version M.53d).

• Flashload Utility: This utility is supplied with the ReadyFlow software, but used with the GateFlow FPGA Design Kit as part of the process for implementing a project. The flashload utility reads a memory on the Model 71661 XMC module.

• Pentek Model 71605 JTAG PCB: This JTAG adaptor, which comes already installed on the Model 71661 XMC module, is used for downloading new configuration code. After completing the development of your changes to the standard Pentek factory− supplied configuration, you should remove the JTAG PCB.

• Xilinx’s Platform Cable: To connect to your development computer system you will need one of the following two cables, purchased from Xilinx:

.mcs file, creating a binary image that is loaded into FLASH

• Platform Cable USB (DLC−9, Xilinx part # HWUSB−G)

• Platform Cable USB II (DLC10, Xilinx part # HWUSB−II−G)

The Platform USB cable connects to a USB port on your development computer system, and thus carries its own 5V supply connection. The other end of both cables terminates in a pod, which contains a shrouded connector for a 14−pin, 2 mm pitch ribbon cable. The ribbon cable is included with the shipment of both Xilinx pro− gramming cables.

To install the FPGA Design Kit for the Model 71661’s Processing FPGA, copy the

Flow

folder on the DVD−ROM to the root directory of the C: drive of the system you’ll be

\Gate-

working on. Unzip the archived project files.

The directory structure of the GateFlow DVD−ROMs mimics that of the development system upon which the original projects were created. We recommend that you copy

\GateFlow folder on each DVD−ROM to the root directory of the C: drive of the sys−

the tem you’ll be working on, such that the original, absolute pathnames of all files in the included project are maintained.

Full details for installing the FPGA Design Kit are provided in Chapter 1 of the Gate− Flow user manuals listed in Documentation Required for Installation.

Rev. 2.2

Details about using flashload to download the

.mcs file into the FLASH memory are

provided in Chapter 2, Section 2.4.2 of the GateFlow user manual.

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Model 53661 Getting Started Guide Page 13

Step 6: Using the Software

ReadyFlow Software

The User’s Guide for each ReadyFlow BSP provides instructions for using the Ready− Flow software. Chapter 3 provides the following:

• Introduction to ReadyFlow − Provides an overview of how the software is used.

• Using ReadyFlow − Provides details about using ReadyFlow, along with a modified

code snippet from an example program.

• Using Linked Lists − Describes how to set up ADC Trigger Controller Linked Lists

along with a code snippet from an example program.

Chapter 4 describes the ReadyFlow data structures and routines that access the Linux or Windows device driver functions.

Chapter 5 describes Command Line use and operation.

Chapter 6 describes Signal Analyzer use and operation.

GateFlow FPGA Design Kit

Chapter 2 of the GateFlow User Manual covers procedures for implementing a project:

• Using Your GateFlow FPGA Design Kit with Xilinx’s Foundation ISE Software

• Preparing for a New FPGA Configuration

• Transferring Configuration Data to the Model 71661

The GateFlow FPGA Design Kit includes test bench files and simulation projects that functionally simulate many operations of the Model 71661, when the FPGAs are con− figured with their factory default configurations. Details are provided in Chapter 3 of the GateFlow User Manual (see Documentation Required for Installation).

We recommend that before attempting any operational modifications of the default FPGA design, you should become very familiar with the board’s performance when operated with the default design. Once you are comfortably familiar with the default operation, we recommend that your first project with the FPGA design kit should be to re−compile the default code with one very simple change (the contents of the read− only FPGA Revision registers), and re−configure the FPGA with the re−compiled con− figuration file. (Refer to Chapter 2 of the GateFlow User Manual for details.)

If you discover that you can use the entire default design for the FPGA, and simply need to add another function or two, Table 1−2 in Chapter 1 of the GateFlow User Man− ual will help you to determine how much of the FPGA’s resources remain available for your use.

Rev. 2.2

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Documentation for This Product

Any of the documentation listed below that is not supplied with the Model 53661 can be found at www.pentek.com.

Product Documentation

Some manuals are used for more than one Pentek product. The manuals listed below are all used for Model 53661.

Part No Type / Description

800.53661 Installation Manual - Model 53661 4-Channel 200 MHz A/D with 4 DDCs Cobalt Family VPX Board

800.71660 Operating Manual - Model 71660 4-Channel 200 MHz A/D Cobalt Family XMC Module

800.71661 Addendum Manual - Model 71661 4-Channel 200 MHz A/D with 4 DDCs Cobalt Family XMC

Module

800.71603 Addendum: Model 716xx Reprogram FPGA from FLASH

801.71660 Programmer's Reference - ReadyFlow Board Support Libraries for Models 71660, 71661, and

71662

807.71661 User’s Manual - Model 4953 Option 661 Design Kit for FPGA on the Model 71661

809.7x660 Supplemental Manual - Vendor Data Sheets for Model 7x660 Series Operating Manuals

815.71660 User's Guide - Model 4995A Option 166/661/662/176 Windows ReadyFlow BSP for Models

71660, 71661, 71662, and 71760

816.71660 User's Guide - Model 4994A Option 166/661/662/176 Linux ReadyFlow BSP for Models 71660, 71661, 71662, and 71760

Rev. 2.2