Pentek 52791 Getting Started Manual

GETTING STARTED GUIDE

MODEL 52791

L−Band Tuner with 2−Channel 500 MHz A/D

and Digital Downconverters

®

Onyx

Family VPX Board

Manual Part Number: 820.52791
Rev: 1.0 - July 25, 2016

Setting the Standard for

Digital Signal Processing

Pentek, Inc.

One Park Way

Upper Saddle River, NJ 07458

[phone]

www.pentek.com

Page 2 Model 52791 Getting Started Guide

Manual Revision History

Date Revision Comments

7/25/16 1.0 Initial Release

Copyright

Copyright © 2016, Pentek, Inc. All Rights Reserved. Contents of this publication may not be reproduced in any form
without written permission.

The Linux kernel is Copyright © by Linus B. Torvalds, under the terms of the General Public License (GPL).

Trademarks

Pentek, Cobalt, GateFlow, GateXpress, Onyx, and ReadyFlow are trademarks or registered trademarks of Pentek, Inc.

Linux is a registered trademark of Linus B. Torvalds. Microsoft and Windows are trademarks or registered trademarks of
Microsoft Corporation. OpenVPX is a trademark of VITA. PCI Express and PCIe are registered trademarks of PCI−SIG.
Xilinx, Virtex−7, ISE Design Suite, iMPACT, and Platform Cable USB are registered trademarks of Xilinx Inc.

Printed in the United States of America.

Model 52791 Getting Started Guide Page 3

What’s in the Box?

Your shipment of the Pentek Model 52791 should include the items on the following
list. If anything is missing or damaged, contact Pentek immediately at (201) 818−5900.
Please save the shipping container and packing material in case reshipment is required.

Quantity

1

Part Number Description

002.52791

Model 52791 board set (consisting of the Model
71791 mounted on the Model 5201 3U VPX carrier)

1 300.70001 Front Panel Gasket

2 356.00015 Shorting Plugs

3 353.02607

26−Pin Socket for Ribbon Cable (Sync)

a

1 378.62602 26−Conductor Ribbon Cable, 30GA 025 (Sync)

4 385.30200 Mounting Screws (2.5x6mm Phillips)

1 174.50010 1.55V Silver Oxide Battery (see Note below)

1 900.10153 Hex key, 3/32” (option 763 only)

1 808.52791 Instruction Manual Kit (all included manuals)

a. To purchase separately, use Pentek Model 2140-998.

The list above includes all the standard parts that are shipped with the Pentek Model

52791. The options for this product are described in this Getting Started Guide and in the
Pentek Model 52791 Installation Manual (included in the box).

NOTE:

NOTE:

Model 52791 requires two VPX slots: one in which to install the Model 52791
assembly and a vacant slot to the right of it, required to accommodate the
JTAG board.

If your Model 52791 has Option 741, you must use a 5HP width (1") VPX slot.

Rev. 1.0

Page 4 Model 52791 Getting Started Guide

Introduction

This document describes the Pentek Model 52791 Onyx® Family VPX board, its
associated software, what to consider before installation, and installation steps.

Before You Begin: Description of Hardware

Pentek's Onyx Family Model 52791 is a multichannel, high−speed analog data
converter. Using the 3U VPX card format, the 52791 includes one L−band tuner, two
500−MHz, 12−bit A/D converters, and two digital downconverters.

Model 52791 consists of one Pentek Model 71791 XMC module mounted on a Pentek
Model 5201 3U VPX carrier, assembled and tested as a single board. It is ready to plug
into a chassis with a single 3U VPX slot. The Model 5201 is a 3U VPX carrier that
features built−in support for PCI Express

®

.

The Pentek Model 52791 Installation Manual (800.52791) provides installation instructions
for the Model 52791 and the Pentek Model 71791 Operating Manual (800.71791) describes
the operation and programming of the Pentek 71791 XMC module.

Before You Begin: Consider the VPX Backplane

The Pentek Model 5201 carrier is configured in accordance with the VITA 65
OpenVPX™ standard, which defines VPX Slot Profiles for various signal connections.
Before installing Model 52791, you will need to know or consider the following:

 Is your VPX backplane connection x4 or x8 PCIe?

 VPX P0 is pinned out in accordance with the VITA 46.0 VPX Baseline Standard.

 VPX P1 Slot Profile SLT3−PAY−1F2F has one Fat Pipe Data Plane (x4 PCIe interface),

and two Fat Pipe Expansion Planes (two x4 Aurora links).

 VPX P1 Slot Profiles are as follows:

•SLT3−PAY−1F (without Option 105) has one Fat Pipe Data Plane (x4 PCIe
interface). (Note that without Option 105 the Expansion Plane is no connects.)

Rev. 1.0

•SLT3−PAY−1F2F (with Option 105) has one Fat Pipe Data Plane (x4 PCIe
interface), and two Fat Pipe Expansion Planes (x8 user−defined).

 VPX P2 has 24 user−defined differential pairs (with Option 104 only).

 Ensure that the VPX chassis has enough cooling and power capabilities for the

number of installed modules. Refer to the specifications in Section 1.6 of the Model
52791 Installation Manual.

Model 52791 Getting Started Guide Page 5

Before You Begin: Jumper and Switch Settings

As shipped from the factory, all jumpers and switches are set in default positions on the
Pentek Model 52791. The default operating parameters they select may or may not meet
your requirements. Therefore, consider the following before installation:

Pentek Model

When you install Model 52791, you may need to set DIP switch SW1 on the 71791 XMC
module (which controls FPGA configuration) based on the characteristics of your host
bus. Therefore, you will need to consider the following before you begin installation:

•FLASH memory write protect/write enable

• PLX PCIe switch maximum speed select

• Select boot configuration at power on

• PCIe clock select

• P16 clock select

• JTAG source select

• GateXpress
loading and reloading the FPGA)

For example, Switch SW1−2 allows you to change the maximum speed of the PLX PCIe
switch from Gen 3 (the factory default) to Gen 2.

NOTE:

71791 XMC Module Switch SW1 − FPGA Configuration

®

disable (GateXpress is the FPGA−PCIe configuration manager for

The Model 71791 XMC module is shipped to boot with the Gen 3 x8 PCIe
default FPGA code. The Model 5201 VPX carrier limits the default of the
Model 52791 to Gen 3 x4.

To preview the DIP switch settings you’ll need to make, refer to Section 2.4 of the Model
52791 Installation Manual.

Pentek Model 5201 VPX Carrier Jumpers

 XMC JTAG: Jumper block JB1 includes or bypasses the 71791 XMC as part of the

JTAG chain from the Pentek JTAG connector (J5).

 XMC Reset Source: Jumper block JB3 selects the source of the reset signal sent to the

XMC interface (VPX SYSRESET or Board Power On).

 XMC MVMRO: Jumper block JB4 enables/disables MVMRO (XMC Write Prohibit)

for the XMC interface.

To preview the jumper settings you’ll need to consider for the 5201 carrier PCB, refer to
Section 2.6 of the Model 52791 Installation Manual.

NOTE:

To access all jumpers, you must remove the XMC module from the VPX
carrier, as described in Section 2.3 of the Model 52791 Installation Manual.

Rev. 1.0

Page 6 Model 52791 Getting Started Guide

Before You Begin: Jumper and Switch Settings (continued)

Pentek Model 5201 VPX Carrier Switches

 Clock Driver Operation: DIP switch SW1 selects modes for the XMC interface clock

drivers. SW1 sets the following functions: clock power down, SRC stop, PLL bypass,
and PLL bandwidth.

 XMC Geographic Address: DIP switch SW2 selects the Geographic Address bits

(GA0, GA1, GA2) for the XMC site interface.

To preview the DIP switch settings you’ll need to consider for the 5201 carrier PCB,
refer to Section 2.7 of the Model 52791 Installation Manual.

Before You Begin: Description of Software

Board Support Software for the Pentek Model 71791 XMC

Pentek’s ReadyFlow® Board Support Packages (BSP) contain software support for the

Model 71791 XMC module. This includes a device driver, plus the ReadyFlow Board
Support Library data structures and routines. The following available BSPs allow
high−level programming for various workstation platforms. Refer to the user’s guide
indicated for each platform:

®

• Model 4994A ReadyFlow BSP for Linux

• Model 4995A ReadyFlow BSP for Windows

®

Pentek’s ReadyFlow

structures and routines for accessing the Model 71791 programmable resources. Refer
to the ReadyFlow Programmer’s Reference for details.

Board Support Libraries contain a set of C−language data

Installation and Getting Started Guide

®

Installation and Getting Started Guide

Software for the FPGAs

The FPGA is supported with a Pentek GateFlow® FPGA Design Kit. The GateFlow
Design Kit (Model 4953) facilitates user−installed FPGA functions using the Xilinx ISE
Design Suite. The FPGA Design Kit allows the user to modify, add to, or replace the
default logic functions within the FPGA with functions of his or her own definition.

NOTE:

GateFlow is a very specialized software package intended for users with
experience in FPGA logic programming. This package may not be required if
the default functions included in the FPGA code, as written by Pentek, satisfy
the requirements of your application.

Rev. 1.0

Refer to the GateFlow User Manual for more information.

Model 52791 Getting Started Guide Page 7

Before You Begin: Consider the Product’s Options

Timing and Synchronization

The following timing and synchronization options are available for the Model 52791
VPX board’s A/D converters. For more information, refer to the Model 71791 Operating

Manual.

• External sample clock: Received from the front panel SSMC connector labeled EXT
CLK. The external clock signal must be a sine wave or square wave of +0 dBm to +12

dBm, with a frequency range from 10 to 200 MHz. This input is enabled using the
Sync Bus Control Register 1 CLK SEL bits. The clock source selected by these bits is
input to a CDCM7005 Clock Synthesizer that generates separate output clocks, each
programmable as sub−multiples of the input frequency. One of the CDCM7005
output clocks (Y0) provides ADC timing.

NOTE:

• Onboard crystal oscillator: Alternately, the sample clock can be sourced from an
onboard programmable voltage−controlled crystal oscillator (VCXO).

• 26−pin sync bus front panel connector: This connector (labeled SYNC/GATE)
provides clock, sync, and gate input/output pins for the Low−Voltage Positive
Emitter−Coupled Logic (LVPECL) Sync Bus. When the Model 71791 is a bus Master,
these pins output LVPECL Sync Bus signals to other slave units. When the 71791 is a
bus Slave, these pins input LVPECL signals from a bus Master. This connector also
accepts two Low−Voltage TTL (LVTTL) Gate/Sync inputs. The mating 26−pin
connector is Pentek part # 353.02607 (Pentek Model 2140−998). For a description of
the SYNC/GATE connector pin configuration, see the Model 71791 Operating Manual.

NOTE:

NOTE:

Ensure that the ADC clock never exceeds the ADS5463 (or ADS5474) rated
clock speed during any change of frequency with the input clock signal.

The LVTTL GATE/TRIG and SYNC/PPS signals are 5V tolerant but they
must NOT have any negative voltage applied. They are terminated with a
392−Ohm resistor to 3.3V and a 392−Ohm resistor to ground.

When connecting LVPECL Sync Bus pins to additional Model 71791
modules, the LVPECL pins on the LAST unit must be terminated. Pentek
includes a terminating board, Model 2140−999, with your shipment for
this purpose.

• External trigger input: The front panel has one SSMC coaxial connector, labeled
TRIG, for input of an external trigger or gate signal. The external trigger signal must
be an LVTTL signal. The trigger input can be used as a gate or trigger for A/D signal
processing using the GATE A/B RCV SRC bits of Sync Bus Control Register 2 GATE
A/B TTL SRC bits.

NOTE:

The front panel TRIG input is 5V tolerant but it must NOT have any
negative voltage applied. It is terminated with a 392−Ohm resistor to 3.3V
and a 392−Ohm resistor to ground.

Rev. 1.0

Page 8 Model 52791 Getting Started Guide

Timing and Synchronization (continued)

• Reference clock: The front panel has one SSMC coaxial connector for a tuner

reference clock input, labeled REF CLK. The external reference clock signal must be a
sine wave of 0.5 − 2.0 V

, with a frequency range from 12 to 30 MHz. This input is

P−P

enabled using the Clock Control/Status Register REF CLK SEL bit. The front panel
has one SSMC coaxial connector for a tuner reference clock output, labeled REF OUT.
The external reference clock output is a sine wave of 1 − 2.0 V

, with a frequency

P−P

range from 4 to 30 MHz.

FPGA Digital Interfaces

Model 78791 includes a Xilinx Virtex−7 FPGA. The FPGA serves as a control and status
engine with data and programming interfaces to each of the onboard resources includ−
ing the A/D converters and RAM memory. The FPGA is factory programmed by Pen−
tek to implement the standard signal processing and control functions specified in the
Model 71791 Operating Manual. The Pentek GateFlow
gration of user−created IP with the factory−shipped functions.

®

FPGA Design Kit facilitates inte−

Option 104 − PMC Connector

The 5201 VPX carrier provides one 64−pin PMC connector, designated J14, on the car−
rier PCB. These pins are directly wired from PMC J14 to the VPX P2 connector for user

I/O.

NOTE:

The P14 signals can be configured in the FPGA as either LVDS or LVTTL but

in either case are limited to 2.5V for the VX330T, or 1.8V for the VX690T, and
also cannot be driven with a negative voltage.

NOTE:

Refer to Section 2.9.6 of the Model 52791 Installation Manual for the pin

mapping of the VPX P2 connection.

Option 104 for the 71791 provides 48 pins (24 differential pairs) defined as 'User I/O'

from the FPGA to PMC connector P14. These connections are programmed for low−

voltage differential signals (LVDS) in the default FPGA configuration. Refer to the sup−
plied Model 71791 Operating Manual for a description of these signals.

Option 105 − XMC Connector

The 5201 VPX carrier provides two XMC connectors, designated J15 and J16 on the
carrier PCB. J15 provides one x4 PCI Express link between the XMC and the carrier.
J16 provides one x8 or two x4 serial links between the XMC and the carrier for 71791

Option 105 gigabit serial I/O.

Rev. 1.0

The 5201 VPX carrier routes these data links from the XMC J15 and J16 connectors to
the VPX P1 connector.

NOTE:

Refer to Section 2.9.5 of the Model 52791 Installation Manual for the pin

mapping of the VPX P1 connection.

Model 52791 Getting Started Guide Page 9

FPGA Configurations

Following are the Xilinx Virtex−7 FPGA options for the Model 71791 XMC module:

 Option 073 is a Xilinx XC7VX330T−2 FPGA

 Option 076 is a Xilinx XC7VX690T−2 FPGA

Model 71791 is shipped with a default FPGA configuration on FLASH memory. Model
71791 loads the FPGA configuration from FLASH memory at power−up. Up to four
FPGA configurations can be stored in FLASH, identified as Version 0, Version 1, Ver−
sion 2, and Version 3. The default FPGA configuration is located in the Version 0 space.
The other three positions are empty.

The 71791 is shipped with the FPGA configuration SW (SW1-2) set to ON, which sets

the board’s maximum speed to Gen 3 x8. However, the Model 5201 carrier limits the

number of lanes to x4. For more information, refer to Section 2.4 in the Model 52791
Installation Manual.

Documentation Required for Installation

• Pentek Model 52791 Installation Manual (800.52791): Provides installation
instructions for the Model 52791.

• Pentek Model 71791 Operating Manual (800.71791): Describes the operation and
programming of the Model 71791 XMC module (which is part of the Model 52791).

• Installation and Getting Started Guide for the Pentek ReadyFlow software for the
workstation platform you’re using (Windows or Linux)

• GateFlow User Manual

Rev. 1.0

Page 10 Model 52791 Getting Started Guide

Step 1: Unpacking and Inspecting the Unit

After unpacking, inspect the unit carefully for possible damage to connectors or com−
ponents. Refer to page 3 for a list of what should be in the box. If anything is damaged
or missing, contact Pentek immediately at (201) 818−5900. Please save the shipping
container and packing material in case reshipment is required.

Step 2: Checking the Switch Settings

At the factory, all DIP switches on the Model 52791 are installed in default positions.
The default parameters selected may or may not meet your requirements.

As described above in Before You Begin: Jumper and Switch Settings, the switches con−
trol various configuration settings. Before installing Model 52791, review Sections 2.4,

2.6, and 2.7 in the Model 52791 Installation Manual to determine whether you need to
change any settings.

NOTE:

You should only change the switches that are described in the Model 71791
Operating Manual and Model 52791 Installation Manual − all others are

reserved for factory test and setup purposes only.

Step 3: Installing the Hardware

Model 52791 includes one Pentek 71791 XMC module mounted on a Pentek Model 5201
VPX carrier. The Model 5201 carrier is designed to operate in VPX systems. This carrier
conforms to the 3U height VPX card format as per VITA 46.0 (VPX Baseline Standard
specification). To install Model 52791, follow the procedure in Section 2.10 (Installing
the Model 52791 in a VPX Card Cage) of the Pentek Model 52791 Installation Manual.

NOTE:

NOTE:

NOTE:

Model 52791 requires two VPX slots: one in which to install the Model 52791
assembly and a vacant slot to the right of it, required to accommodate the
JTAG board.

If your Model 52791 has Option 741, you must use a 5HP width (1") VPX slot.

The JTAG PCB on the Model 52791 board (on the Model 71791 XMC module)
is used for downloading new FPGA configuration code. If you do not plan to
use the JTAG PCB, you can remove it before installing Model 52791. If you do
plan to use the JTAG PCB, you should remove it before you deploy the Model
52791 board.

Rev. 1.0

Model 52791 Getting Started Guide Page 11

Step 4: Installing the Cabling

Connect a cable for the RF analog signal input your application requires to the Model
52791’s front panel SSMC coaxial connector labeled RF IN. The analog input signal
must be a full−scale level of +10 dBm, into 50  input impedance, with a frequency
range from 925 MHz to 2175 MHz. The other cabling you install on the Model 52791’s
front panel depends on how you want to handle timing and synchronization (see Tim−
ing and Synchronization). Multiple boards can be synchronized via the 26−pin sync bus
connectors (SYNC) using a ribbon cable.

Step 5: Installing the Software

ReadyFlow Software

Pentek's ReadyFlow Libraries are software packages designed to provide software
development tools for specific Pentek products on specific operating systems or
platforms. The installation procedure is different for each platform:

− The installation steps can be summarized as follows:

Linux

• Installing ReadyFlow in a Linux system

• Installing WinDriver (required to run example programs)

• Building the ReadyFlow example programs

• Building the ReadyFlow board support libraries

For complete details, refer to Chapter 2 of the Model 4994A ReadyFlow BSP for Linux
Installation and Getting Started Guide.

Windows
Model 52791 under Windows. The installation steps can be summarized as follows:

• Installing ReadyFlow in a Windows system

• Initializing the hardware in Windows (responding to the New Hardware Wizard)

• Building the ReadyFlow example programs

• Building the ReadyFlow board support libraries

For complete details, refer to Chapter 2 of the Model 4995A ReadyFlow BSP for Windows
Installation and Getting Started Guide.

− You must install the Pentek ReadyFlow package BEFORE you attempt to boot

Rev. 1.0

Page 12 Model 52791 Getting Started Guide

GateFlow FPGA Design Kit

The following software and hardware is required to use the GateFlow FPGA Design
Kit:

• Xilinx's ISE Design Suite (Version 14 or later).

• v7_flash.exe: The FLASH memory on Model 52791 provides nonvolatile storage for

the configuration data which is loaded into the FPGA upon power−up. New config−
uration data may be downloaded directly to the FLASH Memory the via PCIe, using
a command−line utility program provided with the ReadyFlow device drivers for
Model 52791, called
Chapter 2, Section 2.4.2 of the GateFlow user manual.

• Pentek Model 71605 JTAG PCB: This JTAG adaptor, which comes already installed
on Model 52791, is used for downloading new configuration code. After completing
the development of your changes to the standard Pentek factory− supplied configu−
ration, you should remove the JTAG PCB.

v7_flash.exe. Details about using v7_flash.exe are provided in

• Xilinx’s Platform Cable: To connect to your development computer system you will
need one of the following two cables, purchased from Xilinx:

• Platform Cable USB (DLC−9, Xilinx part # HWUSB−G)

• Platform Cable USB II (DLC10, Xilinx part # HWUSB−II−G)

The Platform USB cable connects to a USB port on your development computer
system, and thus carries its own 5V supply connection. The other end of both cables
terminates in a pod, which contains a shrouded connector for a 14−pin, 2 mm pitch
ribbon cable. The ribbon cable is included with the shipment of both Xilinx pro−
gramming cables.

To install the FPGA Design Kit for the Model 52791’s Processing FPGA, copy the

Flow

folder on the DVD−ROM to the root directory of the C: drive of the system you’ll be

\Gate-

working on. Unzip the archived project files.

The directory structure of the GateFlow DVD−ROMs mimics that of the development
system upon which the original projects were created. We recommend that you copy

\GateFlow folder on each DVD−ROM to the root directory of the C: drive of the sys−

the
tem you’ll be working on, such that the original, absolute pathnames of all files in the
included project are maintained.

Full details for installing the FPGA Design Kit are provided in Chapter 1 of the Gate−
Flow user manuals listed in Documentation Required for Installation.

Rev. 1.0

Model 52791 Getting Started Guide Page 13

Step 6: Using the Software

ReadyFlow Software

The User’s Guide for each ReadyFlow BSP provides instructions for using the Ready−
Flow software. Chapter 3 provides the following:

• Introduction to ReadyFlow − Provides an overview of how the software is used.

• Using ReadyFlow − Provides details about using ReadyFlow, along with a modified

code snippet from the example program.

• Using Linked Lists − Describes how to set up ADC Trigger Controller Linked Lists

along with a code snippet from an example program.

Chapter 4 describes the ReadyFlow data structures and routines that access the Linux
or Windows device driver functions.

Chapter 5 describes Command Line use and operation.

Chapter 6 describes Signal Analyzer use and operation.

GateFlow FPGA Design Kit

Chapter 2 of the GateFlow User Manual covers procedures for implementing a project:

• Using Your GateFlow FPGA Design Kit with Xilinx’s ISE Design Suite Software

• Preparing for a New FPGA Configuration

• Transferring Configuration Data to the Model 71791

The GateFlow FPGA Design Kit includes test bench files and simulation projects that
functionally simulate many operations of the Model 71791 XMC module, when the
FPGAs are configured with their factory default configurations. Details are provided in
Chapter 3 of the GateFlow User Manual (see Documentation Required for Installation).

We recommend that before attempting any operational modifications of the default
FPGA design, you should become very familiar with the board’s performance when
operated with the default design. Once you are comfortably familiar with the default
operation, we recommend that your first project with the FPGA design kit should be to
re−compile the default code with one very simple change (the contents of the read−
only FPGA Revision registers), and re−configure the FPGA with the re−compiled con−
figuration file. (Refer to Chapter 2 of the GateFlow User Manual for details.)

If you discover that you can use the entire default design for the FPGA, and simply
need to add another function or two, Table 1−2 in Chapter 1 of the GateFlow User Man−
ual will help you to determine how much of the FPGA’s resources remain available for
your use.

Rev. 1.0

Page 14 Model 52791 Getting Started Guide

Documentation for This Product

Any of the documentation listed below that is not supplied with the Model 52791 can
be found at www.pentek.com

Product Documentation

Some manuals are used for more than one Pentek product. The manuals listed below are
all used for Model 52791.

Part No Type / Description

800.52791 Installation Manual - Model 52791 L-Band Tuner with 2-Channel 500 MHz A/D and 2 DDCs on
3U VPX Carrier

800.71791 Operating Manual - Model 71791 1-Ch L-Band Tuner with 2-Channel 500 MHz A/D and 2 DDCs
XMC Module

809.7x791 Supplemental Manual - Vendor Data Sheets for Model 7x730 Series Operating Manuals

- GateFlow User Manual

- Programmer's Reference - ReadyFlow Board Support Librariesa

- Model 4994A ReadyFlow BSP for Linux − Installation and Getting Started Guidea

- Model 4995A ReadyFlow BSP for Windows − Installation and Getting Started Guide

a

.

a

a. Contact Pentek for part number.

Other Technical Documentation

Catalogs:

• Pentek Product Catalog

• Product Selection Guide: http://www.pentek.com/selectguide/SelectGuide.cfm

Handbooks:

• Critical Techniques for High−Speed A/Ds In Real−Time Systems

• High−speed Switched Serial Fabrics Improve System Design

• Putting FPGAs to Work For Software Radio

• Software Radio Handbook

Receive the Latest Information with YourPentek

To receive automatic notification about updates to this product’s documentation, set up
a YourPentek profile at http://www.pentek.com/go/ypmanual
notify you of any lifecycle changes for this product.

. YourPentek will also

Rev. 1.0