Pentek 4284 Operating Manual

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Pentek Model 4284 Operating Manual Page 1

OPERATING MANUAL

MODEL 4284

TMS320C40 Digital Signal Processor MIX Baseboard for VMEbus Systems

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Manual Part No: 800.42840 Rev: F.2 − July 26, 2000

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Page 3

Page 2 Pentek Model 4284 Operating Manual

Pentek Model 4284 Operating Manual − Revision History

Date Rev Applicable Serial #’s Comments

01/03/94 Pre. 9401003 − 9441043 06/03/94 A 9401003 − 9441043

06/10/94 A.1 9401003 − 9441043 07/08/94 B 9401003 − 9441043

10/11/94 B.1 9401003 − 9441043

11/11/94 B.2 9401003 − 9441042 12/29/94 C 9441043 − Forward

01/27/95 C.1 9441043 − Forward

01/05/96 C.2 9441043 − Forward

09/10/96 D 9441043 − Forward

07/02/97 D.1 9441043 − Forward

09/22/97 D.2 9441043 − Forward

05/04/98 E 9441043 − Forward

05/21/98 E.1 9441043 − Forward

7/23/98 E.2 9441043 − Forward 10/12/98 E.3 9441043 − Forward 10/22/98 F 9441043 − Forward

12/06/99 F.1 9441043 − Forward

7/26/00 F.2 9441043 − Forward

References made in this manual to the Texas Instruments TMS320C4x User's Guide are made specifically to Revision C of that publication, dated August 1993.

Pentek warrants that all products manufactured by Pentek conform to published Pentek specifications and are free from defects in mate− rials and workmanship for a period of one year from the date of delivery when used under normal operating conditions and within the service conditions for which they were furnished.

The obligation of Pentek arising from a warranty claim shall be limited to repairing or at its option, replacing without charge, any product which in Pentek’s sole opinion proves to be defective within the scope of the warranty.

Pentek must be notified in writing of the defect or nonconformity within the warranty period and the affected product returned to Pentek within thirty days after discovery of such defect or nonconformity.

Buyer shall prepay shipping charges, taxes, duties and insurance for products returned to Pentek for warranty service. Pentek shall pay for the return of products to buyer except for products returned from another country.

Pentek shall have no responsibility for any defect or damage caused by improper installation, unauthorized modification, misuse, neglect, inade− quate maintenance, accident or for any product which has been repaired or altered by anyone other than Pentek or its authorized representatives.

The warra nty described above is buyer’s sole and exclusive remedy and no other warranty, whether written or oral, is expressed or implied. Pentek specifically disclaims fitness for a particular purpose. Under no circumstances shall Pentek be liable for any direct, indirect, special, incidental or consequential damages, expenses, losses or delays (including loss of profits) based on contract, tort, or any other legal theory.

Initial Product Release − Manual generated by Engineering Dept.

Complete rewrite, reformat and update. Changed pinout of TCK connector. Added Software examples and Appendices.

Added header file listings to sample 4284 setup code in Appendix A, Section A.1.

Listed Pentek part # for ordering Comm Port cables. Minor change to detail block diagram. Add section 4.8 on memory usage & table of transfer times. Changes to Tables 4−8 to properly represent transfer timing for 50 MHz 'C40. Delete Table 4−9 & refer to 'C40 Manual for DMA timing info. Changes to Sections 2.11.4 and 3.2.1, regarding which signals are inputs and which are outputs. Correct pin numbering error in Table 2−12. System Clock jumper installed between pins 1−2, not 11−12.

New features: Flash EEPROM and Turbo−MIX. Properly identify jumper blocks SW1 and SW2 in Figure 2−2. Expanded discussion of Reset Operation. Add more transfer timing tables for 40 and 50 MHz parts, using block repeat, DMA and Turbo−MIX. Descriptions of these tables updated. Turbo−MIX example added to Appendix A. Flash EEPROM programming code added to Appen− dix A. Update Boot Code in Appendix B. Add info re:Option 010, in which A32 addr ess is independent of A24 address, a nd Memory Window jumpers affect A24 window only. Correct Table 2−2 (A16 address 8700 is reserved). A24 inhibit bit also prevents A32 access. This change affects Section 2.4.3, Section 3.11.2.4, and Table 3−12. Mention FTL in Section 1.9 (Software Support). Add info on mating connector for front panel Serial and GPIO connectors (Sec. 2.11). Add Section 2.14, describing blinking of Front Panel LED on power−up . Corre ction to note in Section 4.2.1, re ference to EPROM rev. should be Revision E, not B. Indicate that use of the Linker Command File shown in Sections 4.3.1 and A.6 requires a change to .main. Changes to Hex File Loader & Starter in Section A.7. Sec. 3.8.5: 'C40 Int. to VME Status bit in Transfer Mode Reg. is accessible to the 'C40 (not VME) for read only. Add Tables & Figures to Table of Contents. Update MIX Appendix to Rev. F.1. IACK Vector Register must be re−written to clear VME interrupts generated by 4284. This infor− mation added as a Note in Section 3.11.1, and to text in Section 4.6.1. Section 4.2.1 − The code that triggers a boot from Flash EEPROM is A55A 5AA5, not A55A A55A − this changes the last paragraph on pg. 52, the first paragraph on pg. 53, Table 4−4, and the first paragraph on page 57. Add Parallel C to Software Development Support section (1.9). Replaced board diagram with VSB ver− sion of board. Added section 3.12 on VSB. Modified Table 3−7 to include VSB addresses. Revisions to VSB section (3−12) − renamed Table 3−14 (VSB Control Register) and renamed some bits in the table. Add Tables 3−15 − 3−17 illustrating bit field usages in VSB Control Register. Add VSB interface to Detailed Block Diagram (Fig. 4−1). In SW Development Support section (1.9) Parallel C is now calle d Diamond. Correct & cross reference to Table 3−16 in Table 3−14.

Correct address range for VME Master Access in Table 3−7 (0xB000 0000 − 0xBFFF FFFF)

Regardless of DRAM Window size, DRA M must be mapped on an address bounmd ary that is a multiple of the actual DRAM size. This changes text in Secs. 2.4.2 and 2.4.3, and Tables 2−5 − 2−7, and deletes Tables 2−8 & 2−9 (these tables all concerned base address vs. window size). Add note to S ec. 2.4.3 indi− cating that for DRAM access, each ‘C40 address is equivalent to four VME addresses. Reinforce same concept in Sec. 4.10. Give VME addr ess of DRAM in S ec. 3.10 & add a note to the ‘C40 memory Map stat− ing that DRAM is shared w/ VME. Sec. 4.2.3 − Host Control Reset does NOT reset MIX or VSB. Change timer address in Sec. A.4 (1st executable line under main()) to 0x100020. Remove MIX Appendix & refer− ences to it (this info now included in 800.00001).

Sec. 1.9 − Removed SPOX, FTL & Diamond from Software Support list. Corrections to Tables 2−5 thru 2−7, which were correct up until last Rev. Sec. 2.1.2.1 − Comm Port Cable is Model 2104, not 2014. Table 4−3: Removed extra ‘0’ in last row of address column. Added NOTEs to Sec’s 4.2.4 & 4.3.5 about initial− izing the Local Control Register if you do not boot from t he factory EP ROM. Remove Sec. 4.4.2 (Down− loading SPOX programs), and the sentence referencing SPOX in Sec. 4.4

Sec. 1−12: delete reference to Opt. 060. Additional corrections to Tables 2−5 thru 2−7. Update Boot Code listing in Appendix B.

WARRANTY

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Pentek Model 4284 Operating Manual Page 9

Chapter 1: Overview

1.1 General Description

The Model 4284 MIX Baseboard for VMEbus systems is based on the Texas Instruments TMS320C40 Floating Point Digital Signal Processor. The 4284’s ‘C40 acts as both a VMEbus Master and a MIX bus Master. It serves as a powerful 40 or 50 MFlop Digital Signal Processor, as well as a complete DMA controller.

This manual will describe the installation and operation of the Model 4284 in several typical VMEbus environments.

1.2 MIX Bus Support

The Model 4284’s MIX interface supports high−speed, multi−master control and data transfer to any of Pentek’s MIX modules. Mapped directly into the ‘C40’s local bus, this 32−bit data channel includes support for full interrupt handling and generation, to ensure optimum real−time performance.

1.3 TMS320C40 Comm Port Interface

The six high−speed Communications Ports of the ‘C40 are buffered, and brought out to convenient front panel connectors. Any MIX module stacked on the 4284 thus becomes Comm Port compatible. In this manner, the 4284 acts as a Comm Port based I/O controller for other ‘C40 systems.

1.4 Flexible VMEbus Control

The Model 4284 has master, slave and system controller capabilities on the VMEbus. As a bus master, it can read from and write to the entire 32−bit address space of the VMEbus, thus accessing any external slave device. As a system controller, it can act as a bus arbiter for multiple−master systems.

1.5 Local and Global Static RAM

Two separate banks of SRAM are provided for the ‘C40, one on its local bus and the other on the global bus. Each bank may be either 1 or 2 MBytes deep, depending upon the options ordered. These resources maximize the use of the ‘C40’s dual−bus archi− tecture and its ability to conduct data and program cycles in parallel on the two busses. Both the local and global SRAMs operate with zero wait state performance.

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Page 10 Pentek Model 4284 Operating Manual

1.6 Dual Access DRAM

A 4, 8 or 16 MByte dual−access DRAM provides an extremely powerful structure for passing data and programs between the ‘C40 and the VMEbus. From the VMEbus, this resource appears as relocatable slave memory in A24 or A32 address space. From the ‘C40, it is mapped directly onto the global bus.

1.7 Local EPROM

In order to support nonvolatile storage of programs or data, the Model 4284 is equipped with a user−programmable 32 kByte EPROM, located on the ‘C40’s local bus. Ideal for embedded systems, that self−boot from power−up, this memory is also used for system firmware.

1.8 Flash EEPROM Option

The Model 4284 may optionally be equipped with a 128 kByte (Option 002) or 512 kByte (Option 003) in−circuit programmable Flash EEPROM. The Flash EEPROM is mapped as a 'C40 Local Bus resource, and code programmed into it may be executed at boot time.

1.9 Software Development Support

No DSP hardware product offering is complete without a full complement of develop− ment software. The Model 4284 software products are described briefly below.

SwiftTools Development Environment

SwiftNet Communications Protocols

Pentek’s SwiftTools is a complete software development environment for PC−AT and SUN workstations. It is tailored to work directly with Pentek’s family of digital signal processing products which incorporate TMS320C40 and TMS320C30 digital signal processors. SwiftTools integrates all of the operations involved in a typical software develop− ment project and supports full C language source code generation and debugging with a comprehensive suite of powerful tools for a wide range of applications. SwiftTools includes an in−line assembler and disassembler for on−screen changes to object code in RAM. Registers can be examined and loaded, and memory regions can be examined, filled, and moved. Full file uploading and downloading routines are provided and provisions for EPROM byte manipulation are included.

Pentek’s SwiftNet is a software product that supports a network of distributed VMEbus systems connected via Ethernet to a host computer, such as a SUN workstation or PC−AT. All software development tools are run on the host with remote target access provided transparently to the user. SwiftNet utilizes the industry standard TCP/IP interface for Ethernet, making it quite portable across many Operating System environments.

Rev.: F.2

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Pentek Model 4284 Operating Manual Page 11

1.9 Software Development Support (continued)

Macro Assembler/ Linker

The assembler translates assembly language source code into machine language object files in common object file format (COFF). The linker section combines the COFF object files into an executable object module. The archiver supports a macro library accessible by the assembler.

C Compiler The compiler is a full implementation of Kernighan and Ritchie C

language, generating assembly language compatible with the Macro Assembler/Linker. Time critical assembly language routines are callable within the C program.

Code Composer Go−DSP’s Code Composer is a fully integrated development

environment with advanced features specifically tuned for DSP code Designers. It allows code designers to edit, build, manage projects, debug and profile from a single application.

XDS−510 Emulator

The Texas Instruments XDS510 Emulator allows the user to access the ‘C40 through a ‘back door’ port provided by a special 14−pin connector on the board. The emulator board is installed in a PC/AT computer where all software development can take place.

Bus Adapters Pentek offers bus adapters to provide a connecting link between the

computer your ‘C40 programs will be developed on and the VMEbus card cage where those programs will be run. Supported platforms include PC/AT compatibles, SUN SPARCStations and HP Workstations.

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Page 12 Pentek Model 4284 Operating Manual

1.10 VSB Interface (Option 012)

The VME Subsystem Bus (VSB) is a secondary bus utilizing the outer rows of pins (rows A and C) on the VME P2 connector, which are unused in the standard VMEbus implementation. The Model 4284 operates as a VSB master and interrupt handler using the VSB1400A/B chip set from PLX Technologies.

1.11 Block Diagram

A simplified block diagram of the Model 4284 TMS320C40 DSP/MIX Baseboard for VMEbus systems is presented as Figure 1−1, below. More detail can be found in the diagram presented as Figure 4−1, on page 58 of this manual. The elements of these diagrams will be discussed in detail in Chapter 4 of this manual.

Rev.: F.2

Figure 1−1: Model 4284 − Simplified Block Diagram

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Pentek Model 4284 Operating Manual Page 13

1.12 Specifications

Processor

Type: Texas Instruments TMS320C40 Clock Speed

Standard: 40 MHz Option 015: 50 MHz

Address Bus: 32 Bits Data Bus: 32 Bits

Dual−Access DRAM

Size

Standard: 4 MBytes (1M x 32) Option 007: 8 MBytes (2M x 32) Option 008: 12 MBytes (3M x 32)

Option 009: 16 MBytes (4M x 32) Arbitration: Hardware, fully transparent ‘C40 Access: Memory mapped on Global bus, 3 wait states VMEbus Access: 4, 8, 12 or 16 MBytes of VMEbus slave memory

Relocatable on 1 MByte boundaries, 170 ns DTACK

delay

Local Static RAM

Size

Standard: 256k x 32 (1 MByte)

Option 005: 512k x 32 (2 Mbyte) ‘C40 Access: Memory mapped on local bus, 0 wait states

Global Static RAM

Size

Standard: 256k x 32 (1 MByte)

Option 006: 512k x 32 (2 Mbyte) ‘C40 Access: Memory mapped on global bus, 0 wait states

EPROM

Size

Standard: 32 kBytes

Option 016: 64 kBytes ‘C40 Access: Memory mapped on Local Bus, 1 wait state

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Page 15

Page 14 Pentek Model 4284 Operating Manual

1.12 Specifications (continued)

Flash EEPROM (optional)

Size

Option 002: 128 kBytes Option 003: 512 kBytes

‘C40 Access: Memory mapped on Local Bus, 1 wait state

VMEbus Compliance

Bus Master: D32 A32 I(1−7) IH(1−7) Slave: D32 A32 Slot 1 Controller: Level 3 Arbiter, can drive SYSCLK and SYSRST

MIX Bus Compliance

Type: Conforms to Intel MIX Specifications, Master/Slave,

Interrupt generator and handler

Width: 32−bits for data and address Speed: 16 MBytes/sec typical

J−Tag XDS Support:

Serial I/O Support:

14−pin Connector for Texas Instruments XDS−510 J−Tag Emulator

Front Panel 10−pin connector for RS−232 level signals.

Misc. I/O Support: Front Panel 10−pin connector for timers, flags, etc.

VME Subsystem Bus (VSB) Interface: (Option 012 ONLY!)

Master, Interrupt Handler Address Bus Width: 32 bits Data Bus Width: 32 bits

Physical

Dimensions: 6U Eurocard − (160 mm x 233.35 mm)

Multilayer construction.

Power: + 5 V

@ 3A max.

– 5 VDC @ 0A (for MIX modules only) +12 V –12 V

@ 0A (for MIX modules only)

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Pentek Model 4284 Operating Manual Page 15

Chapter 2: Installation and Connections

2.1 Inspection

After unpacking the unit, inspect it carefully for possible damage to connec− tors or components. If any damage is discovered, contact Pentek immediately at (201) 818−5900. Please save the original shipping container and packing material in case re−shipment is required.

2.2 Introduction

This section contains information and instructions for the configuration and various modes of operation of the Model 4284. These are achieved by setting jumper blocks on the board, before it is installed in the VMEbus card cage.

The Model 4284 supports up to three expansion modules, which may be attached to its MIX stacking connector. These modules and the MIX interface system are described in the manual entitled “MIX Tutorial for VMEbus Systems”, included with your ship− ment. Prior to attaching any expansion modules you should successfully install the Model 4284 by itself. This makes access to the jumper blocks and diagnosis of installa− tion problems easier.

2.3 Jumper Block Locations

A drawing of the Model 4284’s the circuit board, showing the location of jumper blocks referred to in the sections below, is shown in Figure 2−2, on the following page.

Figure 2−1, below, shows the pin numbering for double−row jumper blocks used in the

Model 4284. Pin 1 of the jumper blocks is indicated by the line extending from the box that surrounds the header. All of the jumper blocks on the 4284 are right−angle head− ers, located near the edges of the board. This makes them accessible without removing the DRAM mezzanine card or any attached MIX modules.

For most of the jumper blocks on the Model 4284, each jumper position represents a bit. Installing a jumper in a given bit’s position sets that bit to a ‘0’. Leaving the jumper off sets the bit to a ‘1’.

Figure 2−1: Jumper

Block Pin Numbering

Rev.: F.2

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Page 16 Pentek Model 4284 Operating Manual

Figure 2−2: Model 4284 Circuit Board Showing Jumper Block Locations, Option −012 (VSB) shown.

Rev.: F.2

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2.4 VMEbus Slave Base Address Jumper Settings

The VMEbus Slave resources available on the Model 4284 are the dual−access DRAM (shared with the ‘C40), accessible in A24 or A32 address space, and the Host Control Register and IACK Vector Register, both accessed in A16 space. The base addresses for these resources are determined by the placement of shorting jumpers on the jumper blocks described in the sections below.

2.4.1 A16 Base Address − Jumper Block JB6

The Host Control Register allows a VMEbus Bus Master to control the reset and interrupt lines into the ‘C40. The IACK Vector Register is an 8−bit reg− ister loaded from the VMEbus which stores a vector that the Model 4284 sends in response to an interrupt acknowledge (IACK) cycle.

Both of these registers are mapped into the VMEbus 16−bit address space, for Address Modifier Codes 29 and 2D. The addresses at which they reside are selected by the placement of shorting jumpers on jumper block JB6. If there is more than one Model 4284 in a card cage, these jumpers can be set to uniquely configure the addresses for each board. The address set by this jumper block is referred to as the A16_base address.

Jumpers should ALWAYS be installed in positions 9−10 and 11−12 on jumper block JB6. For the remaining positions, pins 1−2 set the value of address bit A8, pins 3−4 set A9, pins 5−6 set A10, and pins 7−8 set the value of A15. Any A16 address on the VMEbus is compared with the settings of these jumpers to determine if this is the board to be accessed.

For any given board, the IACK Vector Register is mapped at the A16_base address and the Host Control Register is mapped at A16_base + 0x0004.

Table 2−1, below, describes the address bits that are set by this jumper

block, and their hexadecimal weights. Table 2−2, on the next page, lists the 16 available A16 Base Addresses, and the jumper settings used to obtain each of them. Note that one of the 16 possible combinations (all four jump− ers removed) is not a valid selection.

Table 2−1: Model 4284 − A16 Base Address − Jumper Block JB6

Address Bits and Hexadecimal Weights of Jumper Positions

Pins 11 − 12 Pins 9 − 10 Pins 7 − 8 Pins 5 − 6 Pins 3 − 4 Pins 1 − 2

Jumpers must always be

installed on these pins

A15

(0x8000)

A10

(0x0400)A9(0x0200)A8(0x0100)

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Page 18 Pentek Model 4284 Operating Manual

2.4 VMEbus Slave Base Address Jumper Settings (continued)

2.4.1 A16 Base Address (continued)

Table 2−2: Model 4284 − A16 Base Address − Jumper Block JB6

Jumper Settings for Available Base Addresses

Hex Address Pins 7 − 8 Pins 5 − 6 Pins 3 − 4 Pins 1 − 2

*0x0000 ON ON ON ON

0x0100 ON ON ON OFF 0x0200 ON ON OFF ON 0x0300 ON ON OFF OFF 0x0400 ON OFF ON ON 0x0500 ON OFF ON OFF 0x0600 ON OFF OFF ON 0x0700 ON OFF OFF OFF 0x8000 OFFONONON 0x8100 OFF ON ON OFF 0x8200 OFF ON OFF ON 0x8300 OFF ON OFF OFF 0x8400 OFF OFF ON ON 0x8500 OFF OFF ON OFF 0x8600 OFF OFF OFF ON 0x8700 Reserved

* − Factory deault setting

Rev.: F.2

2.4.2 VME DRAM Window Size Jumpers − Jumper Block JB7

Jumper block JB7 is used to set the size of the area occupied by the Model

4284’s DRAM in VME A24 or A32 Address space. These jumpers are set at

the factory for the memory installed in your unit. However, the installed

memory size is an important parameter to consider when setting the Base

Address. This is because the memory must be mapped on address bound−

aries that are multiples of the window size. For example, for the standard

(4 MByte) DRAM size, only four A24 base addresses (0x00 0000, 0x40 0000,

0x80 0000 and 0xC0 0000) are valid.

If you have 16 Mbytes of DRAM in your Model 4284 (Option 009), and are

restricted to the use of A24 address space (i. e., your card cage or cage con−

troller has no VME P2 connectors), then the 4284’s DRAM occupies ALL of

your available memory. In this case, you may wish to reduce the VMEbus’

window on the DRAM by rearranging the jumpers on JB7 for less apparent

memory. This makes the upper portion of the DRAM inaccessible by

VME, but it is still available to the ‘C40.

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Pentek Model 4284 Operating Manual Page 19

2.4 VMEbus Slave Base Address Jumper Settings (continued)

2.4.2 VME DRAM Window Size Jumpers (continued)

For the 12 Mbyte DRAM size (Option 008), if all of DRAM is to be available to the VMEbus, set these jumpers for a 16 MByte window.

Table 2−3, below, tells which of JB7's jumper positions corresponds to

which address bit, and summarizes the settings of the DRAM window size jumper block.

Table 2−3: Model 4284 − VMEbus DRAM Window Size − Jumper Block JB7

DRAM

Window

1 Megabyte ON ON ON ON

2 Megabytes ON ON ON OFF

4 Megabytes ON ON OFF OFF

8 Megabytes ON OFF OFF OFF

16 Megabytes OFF OFF OFF OFF

Pins 7 − 8

(A23)

Pins 5 − 6

(A22)

Pins 3 − 4

(A21)

Pins 1 − 2

(A20)

NOTES: 1) Option 010 for the Model 4284 handles the Memory Window

size issue differently. On units equipped with this option, jumper block JB7 sets the Window Size for A24 space ONLY. All of the DRAM is available in A32 space in these units, regardless of the settings of JB7.

2) Reducing the DRAM Window size does not change the requirement that the DRAM must be mapped on a VME address boundary that is a multiple of the full DRAM size. In A24 space, the standard (4 MByte) DRAM can only be mapped at addresses 0x00 0000, 0x40 0000, 0x80 0000 or 0xC0 0000. The Option 007 (8 MByte) DRAM must have a base address of 0x00 0000 or 0x80 0000, and the Option 008 (12 MByte) and 009 (16 MByte) DRAMs must be mapped at VME address 0x00 0000 in A24 space. See Section 2.4.3, which begins at the top of the next page, for information about setting the DRAM base address.

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Page 20 Pentek Model 4284 Operating Manual

2.4 VMEbus Slave Base Address Jumper Settings (continued)

2.4.3 VME DRAM Base Address − Jumper Blocks SW1 and SW2

The Base Address used by VMEbus Masters when accessing the DRAM on the Model 4284 is determined by the settings of jumper blocks SW1 and SW2. SW2 sets the upper four bits (A20 − A23) of the A24 Base address. The upper eight bits of the A32 base address (A24 − A31) are set by SW1. Like the jumper blocks discussed above, an installed jumper in a given bit’s posi− tion sets that bit to ‘0’, and an absent jumper sets the bit to a ‘1’.

Table 2−4: Model 4284 − A24 DRAM Base Address Jumper Block SW2 −

Address Bits and Hex Weights of Jumper Positions

Pins 7 − 8 Pins 5 − 6 Pins 3 − 4 Pins 2 − 1

A23

(0x80 0000)

A22

(0x40 0000)

A21

(0x20 0000)

A20

(0x10 0000)

Table 2−4, above, lists the address bits set by jumper block SW2 and their

hex weights. Table 2−5, below, summarizes all valid A24 DRAM base addresses that may be set with SW2. Note that the DRAM MUST be mapped on an address boundary that is a multiple of the full size of the DRAM, regardless of the settings of the DRAM Window jumpers.

Table 2−5: Model 4284 − A24 Base Address − Jumper Block SW2

Jumper Settings for Valid Base Addresses − 4 MByte DRAM

Hex Address Pins 7 − 8 (A23) Pins 5 − 6 (A22) Pins 3 − 4 (A21) Pins 1 − 2 (A20)

*0x00 0000 ON ON OFF OFF

0x40 0000 ON OFF OFF OFF

0x80 0000 OFF ON OFF OFF

0xC0 0000 OFF OFF OFF OFF

* − factory default setting

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Pentek Model 4284 Operating Manual Page 21

2.4 VMEbus Slave Base Address Jumper Settings (continued)

2.4.3 VME DRAM Base Address (continued)

Some of the addresses listed in Table 2−5 are not valid for larger DRAM sizes. Table 2−6 and Table 2−7, below, list the jumper settings for valid VME DRAM base addresses when the DRAM size is greater than 4 MBytes.

Table 2−6: Model 4284 − A24 Base Address − Jumper Block SW2

Jumper Settings for Valid Base Addresses − 8 MByte DRAM

Hex Address Pins 7 − 8 (A23) Pins 5 − 6 (A22) Pins 3 − 4 (A21) Pins 1 − 2 (A20)

*0x00 0000 ON OFF OFF OFF

0x80 0000 OFF OFF OFF OFF

* − Factory Default Setting

Table 2−7: Model 4284 − A24 Base Address − Jumper Block SW2

Jumper Settings for Valid Base Address − 12 or 16 MByte DRAM

Hex Address Pins 7 − 8 (A23) Pins 5 − 6 (A22) Pins 3 − 4 (A21) Pins 1 − 2 (A20)

*0x00 0000 OFF OFF OFF OFF

* − Factory Default Setting

Table 2−8, below, lists the bits and weights set by jumper block SW1,

which set the A32 base address for the 4284’s DRAM. All jumpers are installed on this block at the factory, configuring it for an A32 base address of 0x0000 0000.

Table 2−8: Model 4284 − A32 DRAM Base Address − Jumper Block SW1

Address Bits and Hexadecial Weights of Jumper Positions

Pins 15 − 16 Pins 13 − 14 Pins 11 − 12 Pins 9 − 10 Pins 7 − 8 Pins 5 − 6 Pins 3 − 4 Pins 1 − 2

A31

(0x8000 0000)

A30

(0x4000 0000)

A29

(0x2000 0000)

A28

(0x1000 0000)

A27

(0x0800 0000)

A26

(0x0400 0000)

A25

(0x0200 0000)

A24

(0x0100 0000)

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Page 22 Pentek Model 4284 Operating Manual

2.4 VMEbus Slave Base Address Jumper Settings (continued)

2.4.3 VME DRAM Base Address (continued)

If any jumpers are removed from jumper block SW2, which sets the A24 base address, then the complete A32 base address is the sum of the two settings. For example, if the jumper between pins 7 and 8 of SW2 is removed, which sets the A24 base address to 0x80 0000 (this address is invalid if your DRAM window is set for 16 MBytes, see Note (2) on page 19, and Table 2−7), and the jumper between pins 15 and 16 of SW1 is also removed, then the A32 base address for the DRAM is 0x8080 0000. Another important point to keep in mind is that, in A32 space as well as in A24 space, the Model 4284’s DRAM MUST be mapped on an address boundary that is a multiple of the memory size (see the first paragraph of Section 2.4.2, page 18.)

NOTE:

While the ‘C40 addresses the 4284’s Dual−Port DRAM in Longword mode, VMEbus masters address all resources in byte mode. Consequently, each ‘C40 address is equivalent to four VMEbus addresses. For example, if a VMEbus master wishes to read data that the 4284’s ‘C40 wrote to the DRAM at ‘C40 address 0x8000 0020, the VME master would find that data at VME address VME_base+0x0000 0080.

In some applications, it may be necessary or convenient to disable VMEbus access to the Model 4284’s DRAM. This can be accomplished by setting the DRAM_Inhibit bit in the Host Control Register (D4 at address A16_base+0x04) to the logic '1' state. See Section 3.11.2.4 for further details.

NOTE:

For 4284s equipped with Option 010, the A32_base address is set by SW1 ONLY. The setting of the A24_base address jumper block (SW2) has no effect on the A32_base address in Option 010.

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Pentek Model 4284 Operating Manual Page 23

2.5 VSB System Arbiter Jumpers − JB14, JB15, and JB16 Mezzanine Board

The VSB interface on the Model 4284 Option 012 can be configured to include the sys− tem bus arbitration function. This is accomplished by placing shorting jumpers between pins 2 & 3 of JB14, JB15, and JB16 on the Model 4284’s VSB Mezzanine board.

If you would rather have another device in your card cage handle VSBus arbitration, then the Model 4284’s VSB arbiter functions should be diabled. To do this, place the shorting jumpers between pins 1 & 2 of JB14, JB15, and JB16 on the Model 4284’s VSB Mezzanine board. This is the factory default setting.

The shorting jumpers should always be in the same positions of all three of these Jumper Blocks. Table 2−9, below, summarizes the settings.

Table 2−9: Model 4284, Option 012 −

VSB System Controller Jumper Blocks −

JB14, JB15, and JB16, Mezzanine Board

Jumper Position VSB System Arbitration

*1 − 2 Disabled

2 − 3 Enabled

* − Factory default position

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Page 24 Pentek Model 4284 Operating Manual

2.6 Bus Request and Bus Grant Jumpers

In the Model 4284, jumper blocks JB8, JB9 and JB10 are used for the selection of the device’s VME Bus Request level, and to receive and pass on Bus Grant signals. The sections below describe the functions of these blocks.

2.6.1 Bus Request Jumpers − Jumper Block JB8

The Bus Request signal generated by the Model 4284 is connected to pins 4, 6, 8, and 10 of jumper block JB8. Installing a jumper between pins 3 & 4 of JB8 connects the internal bus request signal to the VMEbus BREQ0 line, making the 4284 a level 0 bus requester. Similarly, the 4284 may request mastership of the VMEbus on level 1 (BREQ1) if a jumper is installed on JB8 between pins 5 & 6. Placing a jumper between pins 7 & 8 of JB8 allows the Model 4284 to drive the BREQ2 line as a level 2 requester, and the 4284 can be configured as a level 3 requester (BREQ3) by jumpering pins 9 & 10 of JB8 together (this is the factory default setting). Table 2−10, below, summarizes jumper settings for JB8.

Table 2−10: Model 4284 VMEbus Master Request and Grant Jumpers

− Jumper Blocks JB8, JB9, and JB10

Bus Request Level Request Pins JB8 BGIn Pins JB9 BGOut Pins JB10

BREQ0 3 − 4 1 − 2 1 − 2

BREQ1 5 − 6 3 − 4 3 − 4

BREQ2 7 − 8 5 − 6 5 −6

*BREQ3 9 − 10 7 − 8 7 − 8

* − Factory Default Setting

One, and only one, of the four jumpers described in the table above should be installed on JB8 at any given time. If two or more of these jumpers are installed, the VMEbus’ priority arbitration scheme is defeated by the shorting together of bus request lines. If no jumpers are installed, the 4284’s VMEbus Master interface is unable to request the bus, effectively disabling the 4284 as a bus master.

2.6.2 Bus Grant Jumpers − Jumper Blocks JB9 and JB10

The four VME Bus Grant In signals (BGIn0 connected to pins 1, 3, 5, and 7 of jumper block JB9, respectively. After a bus requester level has been selected by JB8, the same level’s Bus Grant In signal must be connected to the 4284’s VME Master Interface by jumpering the appropriate odd−numbered pin of JB9 to the adjacent even−numbered pin. These connections are summarized in Table 2−10, above.

, BGIn1, BGIn2, and BGIn3) are

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Pentek Model 4284 Operating Manual Page 25

2.6 Bus Request and Buys Grant Jumpers (continued)

2.6.2 Bus Grant Jumpers (continued)

If the 4284 receives a Bus Grant In signal on the appropriate level, but it did not request the bus, VMEbus Master Interface will generate a Bus Grant Out signal, which is delivered to the even numbered pins (2, 4, 6 and 8) on jumper block JB10. This signal must be jumpered across the block and back out to the VMEbus to complete the Bus Grant daisy chain. Table 2−10, on the previous page, summarizes these settings. Once a requester level has been selected, ALL the pins listed in that row of the table, and ONLY the pins listed in that row of the table, should be installed on the jumper blocks indicated.

2.6.3 Unused Bus Grant Levels

The Bus Grant signals on the VMEbus are daisy chained, meaning that they are not simply connected across the bus to each module, but must be passed along from one module to the next. The jumpering scheme detailed above allows the 4284 to pass along only the Bus Grant signal for the level on which it requests the bus. However, if there will be other potential VMEbus Master modules positioned to the right of the 4284 in your card cage, the Bus Grant In and Out signals on the other levels must be connected to one another, to bypass the 4284.

There are two ways to accomplish this. The first, and likely the easiest if available, is to jumper these signals together on your VME backplane. Con− sult the documentation provided with your card cage to determine if and how this can be done for your particular card cage.

If backplane jumpering is unavailable or inconvenient, the unused Grant signals can be connected on the 4284 card by wiring the signals from JB9 to JB10. The jumper block pins may be connected using wire−wrap tech− niques. To bypass level 0, BG0In pin 1 to JB10 pin 1. In the same manner, level 1 can be bypassed by wiring JB9 pin 3 to JB10 pin 3, Level 2 can be bypassed by connecting pin 5 of JB9 to pin 5 of JB10, and wiring pin 7 on the two blocks together bypasses level 3.

can be connected to BG0Out by wiring JB9

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Page 26 Pentek Model 4284 Operating Manual

2.7 Slot 1 System Controller Jumpers

The 4284 can be configured as a VME slot 1 System Controller by placing jumpers in certain locations. A VMEbus System Controller drives the System Clock and System Reset lines, and performs arbitration when the bus is requested by more than one mas− ter at a time. The jumpers discussed below should be installed ONLY if the 4284 will reside in Slot 1 of your VME card cage, which is dedicated to the system controller.

Table 2−11, below, summarizes the jumper settings. The subsections following the table

describe functions enabled by the jumpers.

Table 2−11: Model 4284 − VMEbus System Control Jumpers

Control Function Jumper Block Pins

SYSRST Enable JB8 1 − 2

Level 3 Arbiter JB9 9 − 10

System Clock JB12 1 − 2

2.7.1 System Reset Enable − Jumper Block JB8

Connecting pins 1 and 2 of jumper block JB8 allows the 4284 to drive the VME System Reset line (SYSRST

). The Reset signal is generated by setting bit 0 of the ‘C40’s VMEbus Modifier Register, at ‘C40 address 0x9000 0000, to the logic ‘1’ state. Adding this jumper connects the reset signal to the bus. See Figure 3−1, on page 43 of this manual, for a block diagram of the 4284’s reset circuitry.

The other pins in this jumper block are used to select the 4284’s VMEbus requester level. See Section 2.6.1 on page 24 for further details.

2.7.2 Bus Arbiter Enable Jumper − Jumper Block JB9

Placing a jumper between pins 9 and 10 of JB9 enables the Model 4284 as a single level VMEbus arbiter on level 3. This allows the 4284 to receive Bus Requests on BREQ3 from other VME Master devices and to supply the ini− tial signal on the BG3In/Out

The remaining pins in this block are used to select the Bus Grant In level for the 4284’s own VME Master Interface. See Section 2.6.2 on

page 24 for further details.

daisy chain.

Rev.: F.2

2.7.3 System Clock Jumper − Jumper Block JB12

The Model 4284 can be enabled to drive the VMEbus System Clock line by placing a jumper between pins 1 and 2 of JB12.

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Pentek Model 4284 Operating Manual Page 27

2.8 System Reset Jumper − Jumper Block JB11

Installing a jumper between pins 1 and 2 of jumper block JB11 causes the VME System Reset signal to reset the 4284’s ‘C40. This jumper is installed at the factory, and should always be present if the Model 4284 is not the slot 1 VME System Controller.

If the Model 4284 is the slot 1 VME System Controller, and you do not want the 4284’s internally generated System Reset signal to reset the ‘C40, remove the jumper between pins 1 and 2 of jumper block JB11.

2.9 VMEbus IRQ Jumpers − Jumper Block JB13

There are seven possible VMEbus interrupts that may be used as interrupt inputs to the ‘C40. However, only three of these may be enabled at any given time. Jumpers are installed on jumper block JB13 to assign which three of the seven VME IRQs can be ser− viced by the ‘C40. After the proper setting of these jumpers, the three IRQs are referred to as ‘C40 interrupt sources VME_IRQ_A, VME_IRQ_B and VME_IRQ_C. Table 2−12, below, describes the possible configurations.

NOTE:

Table 2−12: Model 4284 − VMEbus Interrupt Handler IRQ

Configuration Jumpers − Jumper Block JB13

VMEbus IRQ

Level

IRQ1 1 − 2 N/A N/A

IRQ2 3 − 5 11 − 13 13 − 14

IRQ3 2 − 4 11 − 12 12 − 14

IRQ4 5 − 6* 6 − 8 14 − 16

IRQ5 5 − 7 7 − 8 15 − 17

IRQ6 19 − 20 9 − 11* 17 − 19

IRQ7 18 − 20 8 − 10 17 − 18*

VME_IRQ_A VME_IRQ_B VME_IRQ_C

N/A − Not Available * − Factory Default Settings

‘C40 Interrupt Requests

Only three of these jumpers should be installed at any given time. Installing more than three jumpers on JB13 shorts IRQ signals together on the VME backplane.

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Page 28 Pentek Model 4284 Operating Manual

2.10 ‘C40 Boot Code Address − Jumper Block JB4

The address of the code you want to use to boot the ‘C40 processor on your 4284 is par− tially determined by the setting of this jumper block. When the ‘C40 is reset, it can jump to one of four addresses, called Reset Vectors. The Reset Vector for the processor is selected by a pair of bits in the Host Control Register (see Section 3.11.2.3 and Section 4.2 of this manual). The power−up default setting of these bits selects the ‘C40’s internal ROM. The ROM program instructs the ‘C40 to jump to another address and run the boot code found there. That is the address determined by this jumper block. For fur− ther details on the reset operation of the ‘C40, see Sections 6.7 (Reset Operation) and

12.1 (Processor Initialization) of the Texas Instruments TMS320C4x User’s Guide.

Table 2−13, below, describes the jumper settings and the available boot code addresses.

While the table lists all eight possible settings of this jumper block, only two of these settings (Comm Port and EPROM) are valid boot locations. The factory default set− tings point to the external EPROM, where the boot program is located that initializes the memory map and makes the front panel LED blink at power−up.

Table 2−13: Model 4284 − ‘C40 Boot Code Address

Jumper Settings − Jumper Block JB4

Address Location Pins 1 & 2 Pins 3 & 4 Pins 4 & 6

COMM PORT Comm Port OFF OFF OFF

0x0030 0000* Ext. EPROM ON OFF OFF

0x4000 0000

0x6000 0000 Not Available ON ON OFF

0x8000 0000

0xA000 0000 Not Available ON OFF ON

0xC000 0000

undefined Do Not Use ON ON ON

* Factory Default Setting − Also used for boot from Flash EEPROM or Global DRAM − See Note 4, Next page

Do Not Use

†

OFF ON OFF

OFF OFF ON

OFF ON ON

†

− See Note 3, next page

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Pentek Model 4284 Operating Manual Page 29

2.10 ‘C40 Boot Code Address (continued)

Notes to Experienced ‘C40 Users:

(1) The previous discussion assumes that the ROM enable pin (ROMEN) on the

‘C40 is held in the high state. There is a 2−pin jumper block associated with this pin on the ‘C40. Installing a jumper on this block (JB3) pulls the input low, and leaving the jumper off pulls the input high (the default state). If you wanted to boot the ‘C40 from a vector address other than those that can be pointed to by the RESETLOC(0,1) pins (driven by bits in the Host Control Register − see Section 3.8.2.3), you could install this jumper and dis− able the internal ROM. However, you would then need to plant your own reset vector in a region of memory that is not installed on the 4284. (The essential point of all the above is . . . don't install the jumper on JB3 − instead, fetch the reset vector from the 'C40's ROM.)

(2) During the ‘C40 reset cycle, jumper block JB4 drives the IIOF(1−3)

via a multiplexer. Following initialization, the multiplexer switches states, causing the IIOF

pins to be driven by the interrupt sources for the ‘C40. See Section 3.3,

Section 3.4 and Section 4.4 of this manual for further information about interrupt

handling on the Model 4284. See the Texas Instruments TMS320C4x User’s Guide, Section 3.1.10 (IIOF

Flag Register) for further details.

(3) Addresses 0x4000 0000, 0x8000 0000, and 0xC000 0000 point to the Local SRAM,

Global DRAM, and SRAM, respectively. While these are valid memory addresses, there is no practical way to load boot code to any of these and retain it while re−booting.

(4) During the boot from standard EPROM, the first address of the Global DRAM is

read. Based on the value found there, the remainder of the boot sequence may be executed from DRAM, from the flash EEPROM, or from the standard EPROM.

2.11 ‘C40 TCLK Connectivity Jumpers − Jumper Block JB5

The TCLK(0,1) I/O signals from the ‘C40 on the Model 4284 can be connected to either the front panel’s general purpose I/O connector (labeled TCK), or to the Transmit Data input and Receive Data output of the RS−232 level translator, where they can be used to synthesize asynchronous serial communication signals. Jumper block JB5 determines where these signals are connected. Table 2−14, below, describes the settings available on this jumper block.

pins on the ‘C40,

Table 2−14: Model 4284 − TCLK I/O Connectivity − Jumper Block JB5

TCLK Signal TCLK Connector RS−232 Translator

TCLK0 JB5, 1− 2 (Pin 1) JB5, 5 − 6* (Receive)

TCLK1 JB5, 3 − 4 (Pin 2) JB5, 7 − 8* (Transmit)

* − Factory Default Settings

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Page 30 Pentek Model 4284 Operating Manual

2.12 The Model 4284 Front Panel

Available to the user on the front panel of the Model 4284 are the six buffered Comm Ports from the ‘C40, a JTAG connector for the Texas Instruments XDS−510 emulator, an RS−232−level serial communications port, a general−purpose I/O connector (labeled TCK), a software−controllable LED and a Reset button. Each of these resources will be discussed in the sections below, which will give pinouts for the connectors and describe the signals they carry.

2.12.1 Comm Port Connectors

The Model 4284 provides front panel access to the six buffered communications ports, referred to as ‘Comm’ Ports, from the TMS320C40. There are six Comm Port connectors on the front panel with mark− ings on the panel showing the Comm Port number. For example the designation “COM5” refers to Comm Port 5.

Figure 2−3, at the right, shows the front

panel Comm Port layout and the pin assignments. The connectors are keyed to prevent improper insertion.

Comm Port cables can be easily assembled by using a 3M hand press with locator plate #3443−110 and standard 16−conduc− tor, 0.050 pitch flat ribbon cable such as 3M #3365/16. Every Model 4284 ships with six mating connectors (3M #50116−B000) and the optional strain relief (3M #3448−50116). By using these standard components, you can easily configure the Comm Port cables to minimize excess cable length for any given interconnect pattern.

As an aid to consistent assembly tech− niques, make sure that pin 1 of each socket at the end of the cable is connected to pin 1 of the ribbon cable. Pin 1 of the cable is identified by the colored stripe. A typical Comm Port cable is shown in Figure 2−4, on the next page.

Figure 2−3: Model

4284 Front Panel

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Pentek Model 4284 Operating Manual Page 31

2.12 The Model 4284 Front Panel (continued)

2.12.1 Comm Port Connectors (continued)

Figure 2−4: Comm Port Cable

All twelve signal lines on the Comm Ports are equipped with a series 24τ resistor to properly match the characteristic impedance of the flat ribbon wiring used in the Comm Port cables.

Comm Port cables are available preassembled from Pentek as Model 2104. Cable lengths of up to 18 in. can be accommodated.

At Power−up, Comm Ports 0, 1 and 2 are configured as outputs (i. e., to write), and Ports 3, 4 and 5 are configured as inputs (i. e., to read). Changing a Comm Port’s I/O configuration is a simple matter of addressing it for the opposite function. In other words, if you wish to use Port 3 as an output, all you need to do is address it to write. If that port were connected to Port 0, then when the data written by Port 3 arrives at Port 0, that port reconfigures itself as an input. See Chapter 8 (Communication Ports) of the Texas Instru− ments TMS320C4x User’s Guide for further details.

2.12.2 XDS Emulator Connector

The Model 4284 has provisions for use with the Texas Instruments XDS510 Emulator. The emulator connector is available on the 4284’s front panel. This connector is keyed for proper alignment with the socket connector at the end of the emulator cable. Refer to Texas Instruments TMS320C40 Emulator User’s Guide or the documentation sup− plied with the XDS system for operating details. Figure 2−5, at the right, gives the pinout of the emulator connector.

Figure 2−5: XDS

Connector Pinout

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Page 32 Pentek Model 4284 Operating Manual

2.12 The Model 4284 Front Panel (continued)

2.12.3 Serial Port Connector

Although there is no UART on the Model 4284, the ‘C40 can synthesize asynchronous serial communications in software using its TCLK0 and TCLK1 I/O pins. These pins may be brought to the front panel directly or through the RS232 driver/receiver by setting the proper jumpers on Jumper block JB5, described in Section 2.10 and Table 2−13 (see page 28). Example ‘C’ source code for serial communication using the ‘C40 TCLKs is included in Appendix A of this manual, and on Pentek's Example Software Diskette.

If a jumper is installed between pins 7 and 8 of jumper block JB5, then pin 3 on the front panel con− nector labeled SER provides an output signal driven by TCLK1 and shifted to RS−232 levels. If a jumper is installed between pins 5 and 6 of JB5, then pin 2 on this con− nector can accept an RS−232 level input signal, shift it back to TTL levels and deliver it to the ‘C40’s TCLK0 pin. Pin 5 of this connector is grounded and the other seven pins are unconnected. Figure 2−6, at the right, shows the pinout of the 4284’s Serial Port connector.

Figure 2−6: Serial Port

Connector Pinout

Rev.: F.2

2.12.4 General Purpose I/O (TCK) Connector

Some signals that may be of general use are brought to the front panel connector labeled TCK. These can include the TCLK(0,1) I/O signals if the proper jumpers are placed on jumper block JB5 (see Section 2.10 and Table 2−13, page 28). Figure 2−7, at the right, shows the pinout of the TCK connector.

Please note that while pins 3 − 8 are connected to MIX bus signals, it is possible in some circumstances to use pins 3, 6, 7, and 8 as general purpose TTL outputs. Pins 4 and 5 are connected to MIX bus inputs, and can sometimes be used in as general purpose TTL inputs.

Figure 2−7:

General Purpose I/O

Connector Pinout

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Pentek Model 4284 Operating Manual Page 33

2.12 The Model 4284 Front Panel (continued)

2.12.4 General Purpose I/O (TCK) Connector (continued)

NOTE:

The recommended mating socket (i. e., female) connector for both the Serial Port and G. P. I/O connectors is manufactured by Berg. Similar connectors from other manufacturersmay be too wide to fit in the panel cutout if the adjecent Comm Port connector is also installed. Berg's part number for this item is 71600−410, and Pentek's part number for it is 353.01006.

2.12.4.1 Erasing Flash EEPROM from the TCK Connector

In order to write new information into the Model 4284’s Flash EEPROM, the EEPROM sector you want to write must first be erased. To erase the entire contents of the Flash EEPROM, con− nect a shorting jumper between pins 3 and 5 of the front panel TCK connector, then push the Reset button. When the 4284 is reset in this manner, the LED indicator remains lit until the Flash EEPROM is completely erased, and then blinks normally (see

Section 2.12.5, below.)

If you want to erase only the specific sector(s) of the Flash EEPROM that you intend to overwrite, please refer to

Section 4.3.3.2.

2.12.5 LED Indicator

The LED on the front panel of the Model 4284 is driven by bit 6 of the ‘C40 VMEbus Modifier Register at ‘C40 address 0x9000 0000 (See Section 3.8 for more details about this register). Writing a ‘1’ to this bit turns the LED on, and writing a ‘0’ turns it off.

2.12.6 Reset Button

Pressing the push−button on the Model 4284’s front panel commences a reset cycle that, upon completion, returns the 4284 to its power−up state. See Section 4.2 for more details about the reset operation of the Model 4284.

2.13 Installing MIX Expansion Modules on the Model 4284

For MIX module stack assembly procedures and other important information about Pentek’s family of MIX expansion modules, please refer to the manual entitled “MIX Tutorial for VMEbus Systems”, Pentek part #800.00001, included with this shipment.

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Page 35

Page 34 Pentek Model 4284 Operating Manual

2.14 Installing the Model 4284 in the VME Card Cage

Once the assembly of the Model 4284 and expansion module(s) has been completed, the assembly can be installed in the card cage.

CAUTION!!

TURN OFF ALL POWER TO THE CARD CAGE

BEFORE INSERTING OR REMOVING ANY BOARD

Since the MIX baseboard is the only portion of the assembly that actually engages in the back plane, when inserting and removing the assembly, only use the front panel ejector/handles of the Model 4284 − not those of the expansion modules. After insert− ing the assembly, push in on the top and bottom ejector/handles of the Model 4284 only to fully seat the connectors in the back plane.

Once the assembly is seated, the captive panel screws at the top and bottom of each front panel should be screwed into the top and bottom rails of the card cage.

When removing the assembly, first loosen all captive screws on the top and bottom of each front panel. Then push the ejector/handles of the Model 4284 only away from the center of the panel to eject the assembly from the cage. Once disengaged, pull outward on the Model 4284 ejector/handles to remove the assembly.

2.15 Power−Up Self−Test

When power is applied to the Model 4284, some basic diagnostic routines are run from the EPROM. If no problems are encountered during this procedure, the LED on the 4284's front panel blinks about five times a second (the 'C40's Timer 0 is used as a counter). If the factory boot code was executed and the LED only blinks approximately once per sec− ond, then the 'C40 had trouble accessing the shared DRAM. If the factory boot code was executed and the LED does not blink at all, then a more serious problem exists.

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Pentek Model 4284 Operating Manual Page 35

Chapter 3: Memory Maps and Register Descriptions

3.1 TMS320C40 Local Bus Memory Map

The Model 4284’s TMS320C40 has two 32−bit data buses, called the Local and Global busses. The map for the resources assigned to Local Memory, as seen by the ‘C40 pro− cessor, is presented below. The following sections give more detailed information about the Local Memory resources and their usage.

Table 3−1: Model 4284 − TMS320C40 Local Memory Map

0x0000 0000− 0x0000 0FFF

0x0000 1000− 0x000F FFFF

0x0010 0000− 0x0010 00FF

0x0010 0100− 0x002F F7FF 0x002F F800− 0x002F FBFF 0x002F FC00− 0x002F FFFF 0x0030 0000− 0x0030 7FFF 0x0030 8000− 0x00AF FFFF 0x00B0 0000− 0x00B7 FFFF 0x00B8 0000− 0x0FFF FFFF

Internal ROM (Boot Loader)

Reserved

Internal Peripherals

(see Table 3−2, next page)

Reserved

1k Internal RAM (Block 0)

1k Internal RAM (Block 1)

External 32k or 64k x 8 Boot EPROM

(Boot, Look & Set Functions)

Reserved

External 128k or 512k x 8 Flash

EEPROM (optional)

Reserved

0x1000 0000 ‘C40 MIX Bus Control Register 0x1000 0001 Reserved

0x1000 0002

0x1000 0003 ‘C40 Interrupt Routing Register 0x1000 0004 ‘C40 Interrupt to VME Register 0x1000 0005− 0x1FFF FFFF 0x2000 0000− 0x23FF FFFF 0x2400 0000− 0x27FF FFFF 0x2800 0000− 0x2BFF FFFF 0x2C00 0000− 0x3FFF FFFF 0x4000 0000− 0x4003 FFFF 0x4004 0000− 0x4007 FFFF

‘C40 Interrupt Status/Control

Reserved

MIX Bus − Module 0

MIX Bus − Module 1

MIX Bus − Module 2

Reserved

External Local SRAM

(256k x 32)

External Local SRAM

− Opt. 005 (256k x32)

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Page 36 Pentek Model 4284 Operating Manual

3.1 TMS320C40 Local Bus Memory Map (continued)

Table 3−2: TMS320C40 Internal Peripherals

0x0010 0000− 0x0010 000F 0x0010 0010− 0x0010 001F 0x0010 0020− 0x0010 002F 0x0010 0030− 0x0010 003F 0x0010 0040− 0x0010 004F 0x0010 0050− 0x0010 005F 0x0010 0060− 0x0010 006F 0x0010 0070− 0x0010 007F

Local and Global Control Port

Analysis Module Block Registers

Timer 0 Registers

Timers 1 Registers

Comm Port 0

Comm Port 1

Comm Port 2

Comm Port 3

0x0010 0080− 0x0010 008F 0x0010 0090− 0x0010 009F 0x0010 00A0− 0x0010 00AF 0x0010 00B0− 0x0010 00BF 0x0010 00C0− 0x0010 00CF 0x0010 00D0− 0x0010 00DF 0x0010 00E0− 0x0010 00EF 0x0010 00F0− 0x0010 00FF

Comm Port 4

Comm Port 5

DMA Channel 0

DMA Channel 1

DMA Channel 2

DMA Channel 3

DMA Channel 4

DMA Channel 5

3.2 ‘C40 MIX Bus Control Register

− Read/Write at 0x1000 0000

This 16−bit register is the means by which the ‘C40 on the Model 4284 monitors and controls the activities of the expansion modules on the MIX bus. Table 3−3, below, defines the register’s bit structure. Brief descriptions of the functions of the bits follow the table. For more detail, refer to the MIX bus specification. All bits in this register are cleared to the ‘0’ state at power−up reset, and they may generally be left in that state.

Table 3−3: Model 4284 − ‘C40 MIX Bus Control Register − R/W @ 0x1000 0000

Bit # D15 D14 D13 D12 D11 D10 D9 D8

Bit Name MXRST Turbo−MIX MXDC MXMIO MXBE3 MXBE2 MXBE1 MXBE

Bit # D7 D6 D5 D4 D3 D2 D1 D0

Bit Name N/U N/U MXID2 MXID1 MXID0 SDOUT SCLK SDIN

3.2.1 Serial EEPROM Data Transfer − Bits D0 − D2

The three least significant bits in this register are concerned with the transfer of serial data to the EEPROM that may be contained on a MIX module. At the time of this writing, none of Pentek’s MIX modules for VMEbus systems contain such an EEPROM.

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Pentek Model 4284 Operating Manual Page 37

3.2 ‘C40 MIX Bus Control Register (continued)

3.2.1 Serial EEPROM Data Transfer (continued)

However, the D0 bit of this register would be used as a serial data stream to be written to the module’s EEPROM. D2 contains a serial stream read from the module’s EEPROM, and D1 has the clock signal which controls the transfer.

These bits are also brought to the front panel’s General Purpose I/O con− nector (TCK), where the SDOUT and SCLK lines may be used as TTL inputs, and the SDIN line may be used as a TTL output.

3.2.2 MIX Module ID − Bits D3 − D5

During a MIX bus reset (when the MXRST line, D15 of this register, is high), a MIX baseboard (e. g., the Model 4284) determines how many expansion modules are present in its MIX stack by reading the states of these three bits. Any installed module will drive the bit associated with its stack position to the low state when the Reset bit is high. If no mod− ule is installed in a given stack position, then the bit associated with that position will be high during Reset.

These bits also serve as chip select lines for the modules’ Serial EEPROMs (if they exist), when the reset signal is inactive. Additionally, they are brought to the front panel’s General Purpose I/O connector (TCK), where they may be used as TTL outputs.

3.2.3 MIX Byte Enables − Bits D8 − D11

These four bits allow a byte sent over the MIX bus to be justified in one of four positions on the 32 bit data bus, or a word to be justified in either of two positions. Only one of these four bits should be in the low state for byte transfers, two should be low for word transfers, and all four are low for Longword transactions.

When the 4284 is booted from the factory−installed EPROM, these bits are all set low, which enables Longword exchanges. For use with Pentek MIX modules, this default configuration is the setting you will want for almost all MIX bus transactions. Table 3−4, on the next page, describes the relation− ship between which byte enable bits are activated (i. e., low) and which bits of the MIX data bus will be used in a given data exchange.

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Page 38 Pentek Model 4284 Operating Manual

3.2 ‘C40 MIX Bus Control Register (continued)

3.2.3 Mix Byte Enables (continued)

Table 3−4: Model 4284 − MIX Bus Byte Enables and Data Bus Usage

Transfer

Type

32−bit − LLLLmnk l 00Single Cycle

32−bit 1 HHLLXXk l 001 word +

2 cycle 2 LLHHXXmn101 word

24−bit − H L L L X m n l 0 0 Single Cycle

24−bit − L L L H m n l X 0 1 Single Cycle

24−bit 1 HLLLXXn l 001 word +

2 cycle 2 HLHHXXXm101 byte

24−bit 1 LLLHXX l X011 byte +

2 cycle 2 LLHHXXmn101 word

16−bit − H H L L X X m l 0 0 Single Cycle

16−bit − L L H H X X m l 1 0 Single Cycle

16−bit 1 H L L H X X l X 0 1 2 bytes =

2 cycle 2 HLHHXXXm101 word

8−bit − H H H L X X X l 0 0 Single Cycle

8−bit − H H L H X X l X 0 1 Single Cycle

8−bit − H L H H X X X l 1 0 Single Cycle

8−bit − L H H H X X l X 1 1 Single Cycle

Cycle # (Note1)

Notes: (1) Cycle # indicates the order in which multiple MIX cycles MUST be run.

Byte Enable Signals Data Bus Utilization Physical Address

Comment

MXBE3 MXBE2 MXBE1 MXBE0 D31−D24 D23−D16 D15−D8 D7−D0 A1 A0

(2) X = no byte, m = most significant byte, n = next more significant byte,

k = next less significant byte, l = least significant byte

(3) For Pentek MIX modules, use the 32−bit single cycle setting, which is the default.

Rev.: F.2

3.2.4 MIX Bus Status Bits

− Bits D12 and D13

The MXMIO (Memory/IO select) and MXDC (decode) bits are used by MIX bus slave modules to determine the type of access requested. For use with Pentek MIX modules for VMEbus systems, these two bits should ALWAYS be held in the low state.

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Pentek Model 4284 Operating Manual Page 39

3.2 ‘C40 MIX Bus Control Register (continued)

3.2.5 Turbo−MIX − D14

This feature is supported ONLY TMS320C40's! This bit is unused on 4284's with 40 MHz 'C40's.

Turbo−MIX mode allows faster transfers to occur over the MIX bus. These accel− erated transfers are effectively a violation of the MIX bus timing specification, as all external wait states are ignored (i. e., the RDY signal is generated internally).

Another important operating characteristic of Turbo−MIX mode is that the MIX bus transceivers are always enabled, which means that the 'C40 is unable to properly access it’s Local SRAM, EPROM or the registers at 0x1000 0000 − 0x1000 0004. Several of Pentek’s MIX modules have been tested and found to operate properly in Turbo−MIX mode, and changes may be made to some other modules to support this feature. Contact Pentek at (201) 818−5900 for the latest list of MIX modules supporting Turbo−MIX.

Turbo−MIX mode is enabled on 50 MHz 4284 boards by setting bit D14 to the ‘1’ state. When this bit is cleared to the ‘0’ state, Turbo−MIX mode is disabled, and normal MIX bus timing specifications are met.

3.2.6 MIX Bus Reset − D15

All expansion modules on the MIX bus are held in their power−up reset state while this bit is held high. For normal operation of the modules, this bit should be low.

on 4284's equipped with 50 MHz

3.3 ‘C40 Interrupt Status and Control Register − Read/Write at 0x1000 0002

The architecture of the Model 4284 allows several interrupt sources to share a single interrupt input on the ‘C40. Therefore, when the ‘C40 receives an interrupt, this regis− ter should be read to determine where the interrupt came from.

The eight LSBs of this register are accessible by the ‘C40 for read operations only. These bits are initially cleared to the ‘0’ state by the power−up reset (a C40RST clears this register). They are set to the ‘1’ state by the individual interrupt sources when they issue their interrupts. The VME interrupt status bits are cleared back to ‘0’ at the end of the VMEbus IACK cycle, when the 'C40 reads the IACK Vector from the interrupter. The MIX interrupt status bits are cleared when the ‘C40 accesses the inter− rupting module. The VMEbus interrupt status bit is cleared by a 'C40 IACK instruc− tion. The Timeout interrupt status bit is cleared by any write operation to this register.

also

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Page 40 Pentek Model 4284 Operating Manual

3.3 ‘C40 Interrupt Status and Control Register (continued)

The three remaining bits in this register (D8 − D10) are accessible for ‘C40 read and write operations. These bits contain the binary−coded level of the IRQ signal that is asserted when the ‘C40 interrupts the VMEbus. The level on which you wish to inter− rupt the VMEbus is written to these three bits. When serviced by a VME Interrupt Handler, this is the IACK level to which the 4284 responds with the vector previously written to the IACK Vector Register (see Section 3.11.1).

Table 3−5, below, summarizes the bit structure of the ‘C40 Interrupt Status and Control

Register. The actual sources of the VMEbus IRQ’s are set by jumpers placed on JB13. Refer to Section 2.9 of this manual for further details. The MIX bus interrupts are gen− erated by the device in the stack position with the corresponding number (i. e., the module in MIX slot 1 generates MXINT1, etc.).

Table 3−5: Model 4284 − ‘C40 Interrupt Status and Control Register − R/W @ 0x1000 0002

Bit # D15 D14 D13 D12 D11 D10 D9 D8

Bit Name N/U N/U N/U N/U N/U IRQlev2 IRQlev1 IRQlev0

Bit # D7 D6 D5 D4 D3 D2 D1 D0

Bit Name TimeOutInt HosInt MXINT2 MXINT1 MXINT0 VME_IRQ_C VME_IRQ_B VME_IRQ_A

3.4 ‘C40 Interrupt Routing Register − Read/Write at 0x1000 0003

The TMS320C40 on the Model 4284 has four interrupt inputs, labeled herein as INT_0 through INT_3. The various sources of interrupts such as VME, MIX modules, host register access and bus timeout circuitry can be flexibly routed by setting certain bits in this register. These interrupts are logically OR'ed together, so it is possible to have multiple events driving a single interrupt input. It is also possible (though not very useful) to have a single event driving multiple interrupt inputs.

Table 3−6, on the next page, describes the bit structure of this register. As shown in the

table, the least significant byte of the register (D0 − D7) connects interrupt sources to the ‘C40’s INT_0 input, the next byte (D8 − D15) connects the sources to INT_1, the third byte (D23 − D16) routes interrupts to INT_2, and the most significant byte (D31 − D24) connects with INT_3. All bits are high true, i. e., a ‘1’ in a given bit connects the indicated source to that byte’s interrupt input.

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Pentek Model 4284 Operating Manual Page 41

3.4 ‘C40 Interrupt Status and Control Register (continued)

Table 3−6: Model 4284 − ‘C40 Interrupt Routing Register − R/W @ 0x1000 0003

Bit # D31 D30 D29 D28 D27 D26 D25 D24

Bit Name TimeOutInt HostInt MXINT2 MXINT1 MXINT0 VME_IRQ_C VME_IRQ_B VME_IRQ_A

Bit

Function

Bit # D23 D22 D21 D20 D19 D18 D17 D16

Bit Name TimeOutInt HostInt MXINT2 MXINT1 MXINT0 VME_IRQ_C VME_IRQ_B VME_IRQ_A

Bit

Function

Bit # D15 D14 D13 D12 D11 D10 D9 D8

Bit Name TimeOutInt HostInt MXINT2 MXINT1 MXINT0 VME_IRQ_C VME_IRQ_B VME_IRQ_A

Bit

Function

Bit # D7 D6 D5 D4 D3 D2 D1 D0

Bit Name TimeOutInt HostInt MXINT2 MXINT1 MXINT0 VME_IRQ_C VME_IRQ_B VME_IRQ_A

Bit

Function

1 = I n t e r r u p t c o n n e c t e d t o ‘ C 4 0 I N T _ 3

0 = I n t e r r u p t n o t c o n n e c t e d t o ‘ C 4 0 I N T _ 3

1 = I n t e r r u p t c o n n e c t e d t o ‘ C 4 0 I N T _ 2

0 = I n t e r r u p t n o t c o n n e c t e d t o ‘ C 4 0 I N T _ 2

1 = I n t e r r u p t c o n n e c t e d t o ‘ C 4 0 I N T _ 1

0 = I n t e r r u p t n o t c o n n e c t e d t o ‘ C 4 0 I N T _ 1

1 = I n t e r r u p t c o n n e c t e d t o ‘ C 4 0 I N T _ 0

0 = I n t e r r u p t n o t c o n n e c t e d t o ‘ C 4 0 I N T _ 0

3.5 ‘C40 Interrupt to VMEbus Register

Writing any data to this register causes the VMEbus IRQ assigned in the ‘C40 Interrupt Status and Control Register (see Section 3.3) to be asserted. The inter− rupt is cleared by a ‘C40 reset, or when a VMEbus master writes to the VMEBus IACK register. This interrupt’s status can be read in the ‘C40 VMEbus Modifier Register at 0x9000 0000, bit D7.

3.6 Other Local Memory Resources

Other resources that may be found in the ‘C40’s Local Bus memory map are the ‘C40’s internal Boot Loader ROM and two internal 1 kByte RAM blocks. Also accessed on the Local Bus are the External Boot EPROM (32k x 8, beginning at address 0x0030 0000), the optional Flash EEPROM (128k x 8 for Option 002 or 512k x 8 for Option 003, beginning at address 0x00B0 0000) and the Local 256k x 32 SRAM (512k x 32 in units with the extended Local SRAM, Option 005), beginning at address 0x4000 0000.

The Flash EEPROM supports non−volatile storage of programs or other data. For more information about how data is written into this memory region, and other details about its use, please refer to Section 4.3 of this manual.

− Write Only at 0x1000 0004

The MIX bus is effectively seen as extension of the ‘C40’s Local Bus. Each MIX module can be accessed in its own 64 M−Longword region on the Local Bus. Module 0’s region begins at 0x2000 0000, Module 1’s at 0x2400 0000, and Module 2’s at 0x2800 0000.

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Page 42 Pentek Model 4284 Operating Manual

3.7 TMS320C40 Global Memory Map

The ‘C40’s Global bus provides the processor with access to the Global SRAM, in addi− tion to those resources that are either shared with, or involved with, the VMEbus. The memory map for these resources is presented in Table 3−7, below.

Table 3−7: Model 4284 − ‘C40 Global Bus Memory Map

0x8000 0000− 0x800F FFFF

0x8010 0000− 0x801F FFFF

0x8020 0000− 0x802F FFFF

0x8030 0000− 0x803F FFFF 0x8040 0000− 0x87FF FFFF 0x8800 0000− 0x8FFF FFFF

0x9000 0000 ‘C40 VMEbus Modifier Register

0x9000 0001

0x9000 0002− 0xA000 0000

* − The DRAM is also accessible to VME, beginning at the VME_base address

1M x 32 Dual Port DRAM*

1M x 32 Dual Port DRAM

(Options 007, 008, and 009)*

1M x 32 Dual Port DRAM

(Options 008 and 009)*

1M x 32 Dual Port DRAM

(Option 009 only)*

Reserved

VSBus Master Access Region

(Option 012 only)

VSB Control Register

(Option 012 only)

Reserved

0xA000 0001 VME IACK Level 1 Code (001) 0xA000 0002 VME IACK Level 2 Code (010) 0xA000 0003 VME IACK Level 3 Code (011) 0xA000 0004 VME IACK Level 4 Code (100) 0xA000 0005 VME IACK Level 5 Code (101) 0xA000 0006 VME IACK Level 6 Code (110) 0xA000 0007 VME IACK Level 7 Code (111)

0xA000 0008−

0xAFFF FFFF

0xB000 0000−

0xBFFF FFFF

0xC000 0000−

0xC003 FFFF

0xC004 0000−

0xC007 FFFF

VMEbus Master Access

Ext. Global SRAM − Opt. 006

Reserved

External Global SRAM

(256k x 32)

3.8 The ‘C40 VMEbus Modifier Register − Read/Write at 0x9000 0000

The TMS320C40 on the Model 4284 may become a VMEbus Master by accessing the 256 M−Longword portion of its memory map beginning at ‘C40 address 0xB000 0000. The VMEbus address space that it will access and the desired data width is designated when the ‘C40 writes to a register mapped into its Global Bus.

This VMEbus Modifier Register contains Data Transfer Select (TRSEL) bits, Address Modifier bits and two Page Address bits. Note that this register need only be written once unless a change in address space or data width is needed for subsequent transfers.

Besides the Address Modifier and Transfer Select bits, the ‘C40 VMEbus Modifier Register contains bits to fire the VMEbus System Reset (if the 4284 is configured as a slot 1 System Controller), to lock the VMEbus and to control the front panel LED Indicator. There are also two VMEbus Page Address bits, and a status bit indicating that the ‘C40 has issued an inter− rupt to the VMEbus. Table 3−8, at the top of the next page, gives this register’s bit definition. The sections beginning below the table give detailed descriptions of the functions of each bit or group of bits.

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Pentek Model 4284 Operating Manual Page 43

3.8 The ‘C40 VMEbus Modifier Register − (continued)

Table 3−8: Model 4284 − ‘C40 VMEbus Modifier Register − R/W @ 0x9000 0000

Bit # D15 D14 D13 D12 D11 D10 D9 D8

Bit Name VME_PA31 VME_PA30 VM E_AM 5 VME_AM4 VM E_A M3 VME _AM2 V ME_AM1 V ME_A M0

Bit # D7 D6 D5 D4 D3 D2 D1 D0

Bit Name HstIntStat LED VME_Lock TRSEL3 TRSEL2 TRSEL1 TRSEL0 Sys_Rst

3.8.1 VMEbus System Reset − Bit D0

This bit is used to fire a VME System Reset pulse, if the 4284 is configured as the slot 1 System Controller. While reading the description of this reset, on the following page, it may help to refer to Figure 3−1, below.

Figure 3−1: Model 4284 Reset Circuit Diagram

Writing a ‘1’ to this bit triggers a 1−shot type pulse generator. If a jumper is installed between pins 1 and 2 of JB8, this pulse is delivered to the VMEbus System Reset line. If another jumper is installed between pins 1 and 2 of JB11, then this pulse also resets the ‘C40 processor on the 4284, by means of the internal C40RST

signal. An auxiliary function of the C40RST signal is to

clear this register, thus resetting this bit to the ‘0’ state.

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Rev.: F.2

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Page 44 Pentek Model 4284 Operating Manual

3.8 The ‘C40 VMEbus Modifier Register (continued)

3.8.2 VMEbus Transfer Mode Select − Bits D1 − D4

VMEbus address bits A1 through A31 are implemented as 31 separate bus lines. These lines are used to explicitly address 2

VME address bit A0 does not actually correspond to an address line on the bus, but is used in the control of two data strobe lines: DS0 and DS1. DS0 becomes active for the lower byte of the 16−bit word, and DS1 for the upper byte. For single byte transfers, only one DS strobe is active. For 16−bit transfers, both data strobes become active at the same time. For 32−bit transfers, besides activating both strobes, the LWORD (longword) bus line is also asserted.

The TRSEL(3−0) bits determine the memory cycle operation of the Bus Mas− ter Interface of the Model 4284. This interface allows the unit to access the VMEbus for read, write, and interrupt acknowledge (IACK) cycles. Data transfers for reads and writes may be 8, 16, or 32−bits wide, thus supporting many different types of VMEbus devices. The TRSEL(3−0) bits should be set up prior to conducting bus cycles and may be changed at any time by writing a new pattern. The bit definitions for this register are shown in

Table 3−9, at the top of the following page. Details for each type of data

cycle can be found in the sections beginning below.

16−bit words.

3.8.2.1 32−bit Longword Memory Cycle

Data is transferred in a single 32−bit cycle with DS0, DS1, and LWORD word of the TMS320C40 is aligned on a 32−bit word boundary in VMEbus address space. This implies that VME address A01 = L. All 32 bits of the TMS320C40 and VMEbus data busses are used.

(longword) lines asserted on the VMEbus. The 32−bit

Rev.: F.2

3.8.2.2 16−bit Word Memory Cycle − Double Cycle

Data is transferred in two consecutive 16−bit word cycles with both DS0 address A01 = L, and the second with A01 = H. Both transfers use data lines D0 through D15 of the VMEbus.

The TMS320C40 uses its own data lines D0 through D15 for the first transfer and lines D16 through D31 for the second.

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and DS1 asserted. The first word is sent with VME

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Pentek Model 4284 Operating Manual Page 45

3.8 The ‘C40 VMEbus Modifier Register (continued)

3.8.2 VMEbus Transfer Mode Select (continued)

Table 3−9: Model 4284 − VMEbus Transfer Select (TRSEL) Bit Functions

TRSEL BITS

321 0

(D4) (D3) (D2) (D1)

xx00

x001

0101

1101

0010

0110

1010

1110

Description

32−bit Long Word

16−bit Word Double

Cycle (Long Word

Transfer as two

16−bit words)

16−bit Word Single

Word Transfer

16−bit Word Single

Word Transfer

8−bit Byte Single

Byte Transfer

8−bit Byte Single

Byte Transfer

8−bit Byte Single

Byte Transfer

8−bit Byte Single

Byte Transfer

VMEbus ‘C40

Strobes Addr Data Data

DS0,

DS1

DS0

DS1

DS0

DS1

DS0,

DS1

DS0,

DS1

DS0

DS1

DS0

DS1

A01 = L

= L

A01 = L

= H

A01 = H

= H

A01 = L

= H

A01 = H

= H

A01 = L

= H

A01 = L

= H

A01 = H

= H

A01 = H

= H

D0 − 31 D0 − 31

D0 − 15 D0 − 15

D0 − 15 D16 − 31

D0 − 15 D0 − 15

D0 − 15 D16 − 31

D0 − 7 D0 − 7

D8 − 15 D8 − 15

D0 − 7 D16 − 23

D8 − 15 D24 − 31

Comments

Single 32−bit

Transfer Cycle

First of Two

16−bit Cycles

Second of Two

16−bit Cycles

Low Order 16−bit

Word Cycle

High Order 16−bit

Word Cycle

Lowest Order

Byte Cycle

Next to Lowest

Order Byte Cycle

Next to Highest

Order Byte Cycle

Highest Order

Byte Cycle

XX11

3.8.2.3 16−bit Word Memory Cycle − Single Cycle

3.8.2.4 8−bit Byte Memory Cycle − Single Cycle

IACK Cycle

LW = VMEbus line LWORD, x = don’t care

DS0 A1 − A3 D0 − D7 D0 − D7 IACK Vector Read

In this case, only a single 16−bit word is transferred. Selection of the word is accomplished by setting TRSEL3 = VME address A01. Both DS0 and DS1 are asserted and VMEbus data lines D0 through D15 are used. If TRSEL3 = L, TMS320C40 data lines D0 through D15 are used, and if TRSEL3 = H, 'C40 data lines D16 through D31 are used.

In this case, a single byte is transferred. Selection of the byte is accomplished by setting TRSEL3 = VME address A01 and TRSEL2= VME address A00. Each of the four possible cycles is described in

Table 3−9, above. Note that only one data strobe line is asserted,

depending on TRSEL2 (A00). Also note the data line correspondence between the data busses for the TMS320C40 and the VMEbus.

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3.8 The ‘C40 VMEbus Modifer Register (continued)

3.8.2 VMEbus Transfer Mode Select (continued)

3.8.2.5 IACK Cycle

The IACK cycle setting is used by the TMS320C40 when acknow− ledging that it has initiated an interrupt on the VMEbus. See

Section 4.5.1.1 for a complete description of the IACK cycle.

3.8.3 VMEbus Lock − Bit D5

When the 'C40 tries to obtain mastership of the VMEbus, it may set this bit to the '1' state to retain exclusive control of the bus. This bit should be set before requesting the bus from the arbiter. It is used to enable DMA trans− actions over VME, and for other kinds of inseparable multi−cycle bus oper− ations (e. g., Read−Modify−Write). The system controller may not grant the bus to another device until this bit is cleared to '0'.

3.8.4 LED Indicator Driver − Bit D6

The LED Indicator on the Model 4284’s front panel is turned on when this bit is in the ‘1’ state. To turn the LED off, clear this bit to the ‘0’ state.

3.8.5 ‘C40 Interrupt to VMEbus Status − Bit D7

This bit is accessible to the 'C40 for read operations only. It is a status bit indi− cating that the Model 4284’s ‘C40 has sent a pending interrupt to the VMEbus System. The bit is set to a ‘1’ by the ‘C40 immediately after it sends the inter− rupt to VME, and is cleared to ‘0’ by the VMEbus Interrupt Handler during the IACK cycle.

3.8.6 VMEbus Address Modifier − Bits D8 − D13

There are three addressing modes defined for VMEbus transfers: 32−bit, 24−bit, and 16−bit modes. These modes are provided to support a variety of bus devices ranging from simple I/O functions with only a few memory locations to large RAM arrays with hundreds of megabytes of storage.

The addressing mode is determined by a special 6−bit code that is placed on six dedicated VMEbus lines by the current VMEbus Master and is known as the Address Modifier Code, or AM Code.

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3.8 The ‘C40 VMEbus Modifier Register (continued)

3.8.6 VMEbus Address Modifier (continued)

The VMEbus specification defines the usage of certain AM codes as shown in , above. As a VMEbus Master, the Model 4284 can output all the AM codes assigned by VME specification. Note that while the 4284 can generate block transfer AM codes (3F, 3B, 0F and 0B), its VMEbus Master interface does not provide support for block transfers. As a VME Slave, it responds to the codes indicated in the table. User−defined codes may be included by modifying the AM Code PAL.

Table 3−10: Model 4284 − Address Modifier Codes

AM Code Function

*0x3F

0x3E 0x3D

*0x3B

0x3A 0x39

0x2D 0x29

*0x0F

*0x0E

0x0D *0x0B *0x0A

0x09

0x10 − 0x1f User Defined

All Others Reserved

* − The Model 4284 can generate this AM code as a VMEbus Master, but does not respond to it as a Slave.

†

− The Model 4284 cannot master VMEbus block transfers.

A24 − Standard Supervisory Block Transfer

A24 − Standard Supervisory Program Access

A24 − Standard Supervisory Data Access

A24 − Standard Nonprivileged Block Transfer

A24 − Standard Nonprivileged Program Access

A24 − Standard Nonprivileged Data Access

A16 − Short Supervisory Access

A16 − Short Nonprivileged Access

A32 − Extended Supervisory Block Transfer†

A32 − Extended Supervisory Program Access

A32 − Extended Supervisory Data Access

A32 − Extended Nonprivileged Block Transfer†

A32 − Extended Nonprivileged Program Access

A32 − Extended Nonprivileged Data Access

†

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3.8 The ‘C40 VMEbus Modifier Register (continued)

3.8.7 VMEbus Page Address − Bits D14 and D15

The Global Memory map for the Model 4284 (see Section 3.7), allocates a region containing 256 M−addresses to VMEbus Master Access from the ‘C40. Because all ‘C40 data transactions are longwords, this 256 M−long− word address region is equivalent to 1 GByte of VME address space. The A32 VME−bus access region, however, is 4 GBytes deep. The two most sig− nificant bits in the ‘C40 VMEbus Modifier Register allow the 4 GByte VME A32 region to be divided into four 1 GByte pages for access by the ‘C40. D15 in this register is therefore equivalent to the A31 VME address bit, and D14 is equivalent to A30.

3.9 VMEbus IACK Level Codes − Read Only at 0xA000 0001 − 0xA000 0007

When an Interrupt Handler in a VMEbus system receives an interrupt on a level within its range, it first seeks control of the data transfer bus. After it has been granted bus control, it drives the IACK address bus (A01 − A03), corresponding to the level on which it was interrupted. In the Model 4284, these seven locations contain the IACK codes. These codes are actually the lower 3 bits of their addresses, i. e., the code at location 0xA000 0005 is 101

line low and places a 3−bit code on the LSBs of the VME

For example, if the 4284 is interrupted on level 5, it (after gaining bus control) asserts IACK and places 1012 on the 3 lowest VME address bus lines. The interrupting devices monitor these 3 LSBs, so the interrupter on level 5 can recognize that this cycle acknowledges its interrupt.

When reading the odd−numbered registers in this group (i. e., codes 1, 3, 5 and 7), the code resides in the upper 16 bits of the 32−bit longword. In these cases, the result of the read operation needs to be "word−swapped" (or shifted right 16 bits) before placing the code on the address bus.

3.10 Other Global Memory Resources

Also mapped into the ‘C40’s Global Memory space are the 256k x 32 Global SRAM (512k x 32 in units with the extended Global SRAM, Option 006), beginning at address 0xC000 0000, and the Dual Ported DRAM, shared with the VMEbus.

The DRAM may be 1, 2 or 4 M−longwords deep, depending upon the options pur− chased. Regardless of its depth, the DRAM is mapped at the beginning of the ‘C40’s Global Bus memory region, i. e., it begins at address 0x8000 0000. For VMEbus mas− terw, the DRAM region begins at the VME_base address.

Rev.: F.2

Remember that the ‘C40 always accesses this memory on longword address bound− aries, while external VMEbus Masters address it on byte boundaries. When writing this memory from the VME side, be certain that the data is properly aligned, so the ‘C40 can interpret it properly.

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Pentek Model 4284 Operating Manual Page 49

3.11 VMEbus Slave Memory Resources

The Model 4284 responds as a VMEbus slave device for accesses to its Dual−Ported DRAM and to the IACK Vector and Host Control Registers.

The IACK Vector that the 4284 responds with when participating in an IACK cycle may be programmed by the host computer. The vector is contained in the IACK Vector Register (at the A16_base address), which is mapped into A16 space. Another A16 reg− ister (the Host Control Register, at address A16_base+0x04) is provided so that the Host computer may reset or interrupt the TMS320C40. Other desired ‘C40 interrupt sources are selected at jumper block JB13 (see Section 2.8).

The A16_base address is selected by setting jumpers (see Section 2.4.1). These two reg− isters are enabled for D16 accesses only.

3.11.1 VMEbus IACK Vector Register − Read/Write at A16_base + 0x00

This 8−bit register is used to store the IACK Vector Address (VA in the table below), which are placed on the VME Data bus when a resource on the Model 4284 issues an interrupt to VME. Table 3−11, below, shows the correspon− dence between the bits in this register and the VME Data Bus lines that are their destinations.

NOTE: This register must be re−written to clear a VMEbus interrupt

generated by the 4284. The interrupt is not automatically cleared by the hardware operations of the IACK cycle.

Table 3−11: Model 4284 − VMEbus IACK Vector Register − R/W @ A16_base

Bit # D7 D6 D5 D4 D3 D2 D1 D0

Bit Name VA7 VA6 VA5 VA4 VA3 VA2 VA1 VA0

3.11.2 VMEbus Host Control Register − Read/Write at A16_base + 0x04

This register provides a means for the Host computer to issue interrupts and resets to the ‘C40. Two of the bits in this register drive the RESETLOC pins on the ‘C40, which determine where the ‘C40 finds its boot code after a reset. Another bit can be used to prohibit VME access to the 4284’s DRAM. Table 3−12, below, describes the Host Control Register’s bit struc− ture. The subsections beginning at the top of the next page describe the functions of this register’s bits.

Table 3−12: Model 4284 − VMEbus Host Control Register − R/W @ A16_base+0x04

Bit # D7 D6 D5 D4 D3 D2 D1 D0

Bit Name N/U N/U N/U DRAM_INH VME_RST1 VME_RST0 HOST_INT HOST_RS T

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Page 50 Pentek Model 4284 Operating Manual

3.11 VMEbus Slave Memory Resources (continued)

3.11.2 VMEbus Host Control Register (continued)

3.11.2.1 Host Reset − Bit D0

This bit can be used to implement a VMEbus software reset func− tion. It is active when set to logic ‘1’, and reset to ‘0’ by the power on reset (PONRS shown in Figure 3−1, in Section 3.8.1. See Section 4.1 for more details about the reset operation the 4284.

3.11.2.2 Host Interrupt − Bit D1

This bit can be used as a VMEbus software interrupt to the ‘C40. This interrupt can be routed to any of the ‘C40’s four interrupt inputs (referred to herein as INT0 ‘C40 Interrupt Routing Register at ‘C40 address 0x1000 0003. See

Section 3.4 for more details.

). It is ‘or−ed’ with other ‘C40 reset sources, as

− INT3), by setting bits in the

The bit is active when set to logic ‘1’. It is reset to ‘0’ by the general purpose reset signal C40RST (see Figure 3−1 on page 43), or by the ‘C40’s IACK signal. See Section 4.1 for more details about reset oper− ation. See Section 4.4 for more details about interrupt handling.

3.11.2.3 VMEbus Reset Vector Select − Bits D2 and D3

Bits D3 and D2 of the Model 4284’s VMEbus Host Control Regis− ter drive the RESETLOC(1,0) pins on the ‘C40 Processor. These pins tell the processor where to look to find the address of the initialization code to be run when the RESET input is driven low. See Section 2.10 of this manual for more details. For a complete description of ‘C40 reset operation, See the Texas Instruments’ TMS320C4x User’s Guide, Sections 6.7 (Reset Operation) and

12.1 (Processor Initialization.)

Table 3−13, below, shows which location the ‘C40 boots from, as

a function of the settings of the VME_RST(0,1) bits in the VMEbus Host Control Register.

Table 3−13: Model 4284 − Reset Vector Select Bits

VME_RST1 VME_RST0 Memory Block Boot Address

0 0 Local 0x0000 0000

0 1 Local 0x7FFF FFFF

1 0 Global 0x8000 0000

1 1 Global 0xFFFF FFFF

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Pentek Model 4284 Operating Manual Page 51

3.11 VMEbus Slave Memory Resources (continued)

3.11.2 VMEbus Host Control Register (continued)

3.11.2.4 DRAM Inhibit − Bit D4

When bit 4 in the Model 4284’s VMEbus Host Control Register is set to a ‘1’, access to the 4284’s DRAM as a VMEbus slave resource is prevented. The Model 4284 effectively disappears from the VMEbus A24 and A32 Slave memory map when this bit is set. This bit must be cleared to the ‘0’ state if VME access to the 4284’s DRAM is necessary. This feature is only implemented on 4284’s with PC board revisions D and higher. On earlier boards, VME slave access to the 4284’s DRAM is always enabled.

3.12 Model 4284 VSB Interface (Option 012)

The VME Subsystem Bus (defined in IEEE Specification 1096−1988), or VSB, allows processor boards to access additional memory and/or I/O over a local bus, to remove some data traffic from the VME bus and improve total system throughput. The local bus utilizes the outer rows of pins (rows A and C) on the VME P2 connector, which are unused in the standard VMEbus implementation. The subsystem bus is physically implemented by connecting two or more adjacent VMEbus P2 connectors by means of an overlay board, placed over the pins that protrude from the rear of the card cage’s backplane. Overlay boards are available from many sources, in lengths to cover from two to six P2 connectors. For example, Overlay boards may be ordered from ELMA Electronic, (44350 Grimmer Blvd., Fremont, CA 94538, Tel: (510) 656−3400 Fax: (510) 656−3783), as Model #69−B0xVSB, where x is the number of slots that the VSB back− plane will cover.

The Model 4284 operates as a VSB master and interrupt handler using the VSB1400A/B chip set from PLX Technologies. The 4284 cannot be accessed as a VSB slave, nor can it issue VSB interrupts. Mastership of the VSBus by an external VME device accessing the 4284 as a slave is not supported.

There are two resources on the Model 4284 that are used during VSB transactions. The ‘C40 memory region between 0x8800 0000 and 0x8FFF FFFF is used to conduct VSBus master accesses, and a VSB Control Register is provided at ‘C40 address 0x9000 0001 (see Table 3−7, on page 42). This register is described in detail in Section 3.12.1, below.

3.12.1 The VSB Control Register (Option 012 only) − R/W @ ‘C40 Global

Address 0x9000 0001

Table 3−14 at the top of the next page, shows the bit arrangement of the VSB

Control Register on the Model 4284, Option 012. Finctional descriptions of the bits and fields are given in the subsections that follow the table. All bits in this register are cleared to the logic ‘0’ state at power−up.

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3.12 Model 4284 VSB Interface (Option 012) (continued)

3.12.1 The VSB Control Register (continued)

Table 3−14: Model 4284, Option 012 − VSB Control Register −

R/W @ ‘C40 Global Address 0x9000 0001

Bit # D31 D30 D29 D28 D27 D26 D25 D24

Bit Name R e s e r v e d

Bit

Function

Bit # D23 D22 D21 D20 D19 D18 D17 D16

Bit Name R e s e r v e d VSA_1 VSA_0

Bit

Function

Bit # D15 D14* D13* D12 D11 D10 D9 D8

Bit

Name

Bit

Function

Bit # D7 D6 D5 D4 D3 D2 D1 D0

Bit Name VSA_31 VSA_30 VSA_29 R e s e r v e d

Bit

Function

1 = Enable

0 = Disable

1 = 2G (2

* − These bits are Read Only. All bits are cleared to tle logic ‘0’ state at power−up.

W r i t e a s ‘ 0 ‘ − M a s k w h e n R e a d i n g

BLT_

Enable

)

1 = 1G (230)

0 = 0

3.12.1.1 Low−Order VSB Address Bits

W r i t e a s ‘ 0 ‘ − M a s k w h e n R e a d i n g

VSB_

BERR

1 = F a l s e

0 = T r u e

0 = 0

VSB_

IRQ

1 = 512M (229)

0 = 0

VSB_LOCK

Enable

1 = Disable

0 = Enable

W r i t e a s ‘ 0 ‘ − M a s k w h e n R e a d i n g

Space_1 Space_0 Size_1 Size_0

See Table 3−15,

page 54

− D17 (VSA_1) and D16 (VSA_0)

)

1 = 2 (2

0 = 0

See Table 3−16,

1 = 1 (20)

page 55

0 = 0

Rev.: F.2

The VSA_0 (D16) and VSA_1 (D17) bits drive the two least sig− nificant VSB Address lines (AD00 and AD01) during the address broadcast phase, respectively on the VSBus during the address phase of VSB transactions. These are the low−order address bits; AD00 and AD01, respectively. They are used to allow byte and word transactions to be conducted on the 32−bit VSBus. Table 3−17, on page 55, shows how these bits, the high−order address bits in this register (D7 (VSA_31), D6 (VSA_30) and D5 (VSA_29)) and the ‘C40’s Global Address Bus are mapped into VSB addresses.

3.12.1.2 Block Transfer Enable Bit − D15 (BLT_Enable)

Set this bit to the logic ‘1’ state to allow block transfers over the VSBus. For single byte, word or longword transfers, clear this bot to the logic ‘0’ state.

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Pentek Model 4284 Operating Manual Page 53

3.12 Model 4284 VSB Interface (Option 012) (continued)

3.12.1 The VSB Control Register (continued)

3.12.1.3 VSB Bus Error Bit − D14 (VSB_BERR), Read Only

If this bit reads back in the logic ‘0’ state, a VSBus error occurred during the previous data cycle. This bit will read back in the logic ‘1’ state if the previous data cycle completed without error.

3.12.1.4 VSB Interrupt Request Bit − D13 (VSB_IRQ), Read Only

The VSB_IRQ master. When this bit reads back inthe logic ‘0’ state, an interrupt is being requested. A logic ‘1’ in this bit indicates that no inter− rupt is requested. The master responds to an interrupt request in one of two ways:

1) It might initiate a VSB IACK (Interrupt Acknowledge) cycle. Slaves that have an interrupt request pending participate in the IACK cycle to determine the one slave whose interrupt requests will be serviced. The active master then reads status and ID information from this slave.

2) It might initiate a VSB read cycle, polling the various slave devices for status and ID information until a device that has an interrupt request pending is found.

line is used by slaves to request an interrupt from a

3.12.1.5 VSB_LOCK_Enable Bit − D12

The VSBus supports Indivisible−Access data cycles (e. g., Read− Modify−Write). The processor conducting such cycles needs the ability to retain mastership of the bus until all phases of the access are complete. This bit supports such activity by locking out other processors that may be requesting the bus during this time. Clear this bit to the logic ‘0’ state to enable the bus lock. When the Indivisible−Access cycle is complete, this bit should be set to logic ‘1’ state to allow other processors access to the VSBus. If the Model 4284 is the only VSBus master in your system, this bit may be left in the default logic ‘0’ state.

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Page 54 Pentek Model 4284 Operating Manual

3.12 Model 4284 VSB Interface (Option 012) (continued)

3.12.1 The VSB Control Register (continued)

3.12.1.6 VSB Address Space Select Bits − D11 (Space_1) & D10 (Space 0)

These two bits drive the Space1 and Space 0 Address Lines on the VSB Backplane, through inverting buffers. These lines are analo− gous to the VME Address Modifier lines, AM0 − AM5, in that they select an address space. The VSB specification defines three address spaces, System, I/O and Alternate. Table 3−15, below, gives the settings of this bit field to select each available address space. Both of these bits default to the logic ‘0’ state at power− up, which selects System address space.

Table 3−15: Model 4284, Option 012 −

Address Space Selection

Address Space Space_1 (D11) Space_0 (D10)

System Address Space 00

I/O Address Space 01

Alternate Address Space 10

Reserved − Do Not Use 11

NOTE:

These bits are inverted before delivery to the VSB

Space1 and Space0 address lines.

3.12.1.7 VSB Data Size Bits − D9 (Size_1) & D8 (Size 0)

These bits drive the SIZE0 During the address broadcast phase, the active master drives SIZE0

− SIZE1 with a size code. The size code indicates the num− ber of byte location(s) that the master wishes to access during the data transfer phase. The VSB specification defines four sizes for data transfer: Single−Byte, Double−Byte, Triple−Byte, and Quad−Byte. During these byte transfers, the master requests access to byte locations. During Single−Byte transfers, access to one byte is requested, and during Quad−Byte transfers, four con− secutive bytes are requested. During Double− and Triple−byte transfers, the master requests two and three consecutive bytes respectively. Table 3−16, at the top of the next page, shows the bit settings for the four data sizes.

& SIZE1 address lines on the VSBus.

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Pentek Model 4284 Operating Manual Page 55

3.12 Model 4284 VSB Interface (Option 012) (continued)

3.12.1 The VSB Control Register (continued)

3.12.1.7 VSB Data Size Bits (continued)

Table 3−16: Model 4284, Option 012 −

Data Size Selection

Data Size Size_1 (D9) Size_0 (D8)

Longword (Quad−byte) 00

Single−byte 01

Word (Double−byte) 10

Triple−byte 11

3.12.1.8 High−Order VSB Address (Page) Bits − VSA_31 (D7),

VSA_30 (D6) & VSA_29 (D5)

The VSA_31 (D7), VSA_30 (D6) and VSA_29 (D5) bits drive the three most significant VSB address lines (AD31, AD30 and AD29, respectively) during the address broadcast phase. They essen− tially behave as page bits, allowing access to the entire 4 GByte VSB address region using only a 128 M−Longword (1 Gbyte) region of ‘C40 memory. Table 3−17, below, shows how these three bits, the two low−order address bits (D17 (VSA_1) and D16 (VSA_0)) in this register, and the ‘C40 Global Address bus map into VSB Address bits.

Table 3−17: Model 4284, Option 012 − VSB Address Bit Mapping

V S B A d d r e s s / D a t a B i t s

AD31AD30AD29AD28AD27AD26AD25AD24AD23AD22AD21AD20AD19AD18AD17AD16AD15AD14AD13AD12AD11A310AD9AD8AD7AD6AD5AD4AD3AD2AD1AD

D7D6D

VSBCR ’C 4 0 G l o b a l A d d r e s s B i t s VSBCR

GA26GA25GA24GA23GA22GA21GA20GA19GA18GA17GA16GA15GA14GA13GA12GA11GA10GA9GA8GA7GA6GA5GA4GA3GA2GA1GA

NOTE: VSBCR = VSB Control Register

D17D

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This page is intentionally blank

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Pentek Model 4284 Operating Manual Page 57

Chapter 4: Working with the Model 4284

4.1 Introduction

The discussions in the sections that follow will make reference to items contained in

Figure 4−1, on the following page. This is a more detailed block diagram of the

Model 4284 than the one presented in Figure 1−1, which only showed which resources were accessible from which bus. By contrast, Figure 4−1 shows what other resources may be affected when a given resource is accessed.

4.2 Resetting and Booting the Model 4284

There are three distinct paths by which the 'C40 processor on the Model 4284 may be reset. These are the Power−up/Push−button Reset, the VME System Reset, and the Host Control Reset. There are subtle differences in the results of each of these resets, which will be described in the sections below.

4.2.1 The Power−Up or Push−Button Reset

When power is initially applied to the Model 4284, the RESET input on the TMS320C40 is held low for a brief period of time by an RC network. This activation of the RESET input places the ‘C40 processor in the state described in Table 6−4 (Pin States After System Reset), in Section 6.7 (Reset Operation) of the Texas Instruments TMS320C4x User's Guide. Assuming that no jumper is installed on JB3 (this enables the Internal Boot ROM, and is the factory default condition), when the Reset is released control of the ‘C40 passes to the code found at the Reset Vector location. This location is determined by the contents of the VME_RST(1,0) bits in the Host Control Register (see Table 3−13, in Section 3.11.2.3 of this manual). The power−up reset also clears these two bits, thus pointing to the ‘C40’s Internal ROM at location 0x0000 0000. The instructions found there direct the ‘C40 to read its IIOF(1−3) pins and, based on the result of that read and an internally stored table (see Table 4−1, below), jump to an address where it will find the code to boot load.

Table 4−1: Model 4284 − ‘C40 Boot Code Address Jumper Settings − Jumper Block JB4

Address Location Pins 1 & 2 Pins 3 & 4 Pins 5 & 6 COMM PORT Comm port OFF OFF OFF 0x0030 0000* Ext. EPROM ON OFF OFF

0x4000 0000 Do Not Use OFF ON OFF 0x6000 0000 Not Available ON ON OFF

0x8000 0000 Do Not Use OFF OFF ON 0xA000 0000 Not Available ON OFF ON 0xC000 0000 Do Not Use OFF ON ON

Undefined Do Not Use ON ON ON

* − Factory Default Setting − Also used for boot from Flash EEPROM or Global DRAM

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Page 58 Pentek Model 4284 Operating Manual

Rev.: F.2

Figure 4−1: Model 4284 − Detailed Block Diagram

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Pentek Model 4284 Operating Manual Page 59

4.2 Resetting and Booting the Model 4284 (continued)

4.2.1 The Power−Up or Push−Button Reset (continued)

The 'C40's IIOF(1−3) pins are driven by the output of a multiplexer. Dur− ing resets, the multiplexer transfers the logic states found at Jumper Block JB4 (installed jumper = 0, absent jumper = 1) to the IIOF pins. The factory setting of JB4 sets the jump location to 0x0030 0000, which is the beginning of the 4284's EPROM. The code provided in the EPROM, after it is boot loaded, initializes some of the 'C40's internal registers, among them the Local and Global Bus Interface Control Registers. Pointers to the Look, Set and other useful functions contained in the EPROM (including the Flash EEPROM support functions) are planted in DRAM. These are described in

Table 4−2, below. The EPROM code also initializes the registers on the

4284 that are external to the 'C40, as described in Table 4−3, at the top of the next page.

Table 4−2: Model 4284 − DRAM Locations of Pointers to EPROM Functions

VME Slave Offset (DRAM_Base+…) ‘C40 Address Contents

0x0000 0800 0x8000 0200 Function (command) address from Host

0x0000 0804 0x8000 0201

0x0000 0080 0x8000 0202

0x0000 080C 0x8000 0203

0x0000 0810 0x8000 0204 Ready to Host (0=not ready / 1=ready)

0x0000 0814 0x8000 0205 Pointer to LOOK function

0x0000 0818 0x8000 0206 Pointer to SET function

0x0000 081C 0x8000 0207 Pointer to BLOCK MOVE function

0x0000 0820 0x8000 0208 Aux ready flag for factory use

0x0000 0824 0x8000 0209 Test pattern 0xA5A5 A5A5

0x0000 0828 0x8000 020A Test pattern 0x5A5A 5A5A

0x0000 082C 0x8000 020B Test pattern 0x1234 5678

0x0000 0830 0x8000 020C Test pattern 0x8765 4321

0x0000 0834 0x8000 020D Test pattern 0xFFFF FFFF

0x0000 0838 0x8000 020E Firmware Version 0x10C=1.0c

0x0000 083C 0x8000 020F Test pattern 0x8000 0200

0x0000 0840 0x8000 0210 Pointer to FLASH BOOT function

0x0000 0844 0x8000 0211 Pointer to FLASH LOOK function

0x0000 0848 0x8000 0212 Pointer to FLASH SET function

0x0000 084C 0x8000 0213 Pointer to FLASH ERASE function

0x0000 0850 0x8000 0214 Pointer to FLASH ERASE SECTOR function

0x0000 0854 0x8000 0215 Pointer to FLASH BYTE LOAD function

0x0000 0858 0x8000 0216 Pointer to FLASH BYTE LOAD function

0x0000 085C 0x8000 0217 Pointer to FLASH BYTE UNLOAD

0x0000 0860 0x8000 0218 Pointer to FLASH WORD LOAD function

0x0000 0864 0x8000 0219 Pointer to FLASH WORD UNLOAD function

First Command Argument − Address for Look/Set Function or

Source Adress for block move of Flash Boot Address.

Data from Host for set function or destination

address for block move

Second Command Argument − Data to Host for

Look or Word cound −1 for block move

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Page 60 Pentek Model 4284 Operating Manual

4.2 Resetting and Booting the Model 4284 (continued)

4.2.1 The Power−Up or Push−Button Reset (continued)

Table 4−3: Model 4284 − Register States After Boot from Factory EPROM

IACK Vector Register A16_base+0x00 Indeterminate Must be initialized by user code before interrupting VME

HOST Control

‘C40 VME Modifier

‘C40 MIX Bus Control

‘C40 Interrupt Status

and Control Register

‘C40 Interrupt

Routing Register

‘C40 Interrupt to VME

* − The state of the LED bit (and the LED) should toggle at ≅ 5 Hz following standard EPROM initalization

After register initialization, the EPROM code directs the ‘C40 to read the first location in the Global DRAM (‘C40 address 0x8000 0000). Based on the contents of that memory location, the ‘C40 will perform one of the following actions:

1) If the data at 0x8000 0000 is 0xA55A 5AA5, then the ‘C40 uses the location pointed to by the next Global DRAM address (0x8000 0001) as the boot load address.

A16_base+0x04 All bits cleared (0)

0x9000 0000 0x3D40*

0x1000 0000 All bits cleared (0)

0x1000 0002

0x1000 0003 0x0000 4000

0x1000 0004 Cleared (0)

D0−D7=0, D8−D10

are indeterminate

Host Reset & Interrupt Inactive, Reset Vector is start of internal

ROM, A24 access enabled

Page=0, AM=3D, Host Int cleared, LED on*, bus lock off, 32−bit

VME transfers

MIX bus will be ready for use after MXRST (D15) is toggled,

byte enables set for 32−bit, single−cycle transfers

No pending interrupts, Interrupter Level must be written to D8−

D10 before interrupting VME

Host Interrupt ONLY enabled, connected to INT_1

Initialize IACK Vector Reg and IRQ_lev (0−2) bits(D8−D10) in

‘C40 Interrupt S&C Reg before issuing this interrupt

Rev.: F.2

2) If the data at 0x8000 0000 is 0xC33C 3CC3, then the ‘C40 will return to EPROM and continue to execute the factory default boot code found there. This is used to block the boot loading of valid code stored in the Flash EEPROM (see below), if desired. The processor is left running a program that toggles the front panel LED and awaiting an interrupt to direct it elsewhere.

3) If neither of the codes listed above are found at 0x8000 0000, the ‘C40 then reads the first address of the Flash EEPROM (0x00B0 0000.) Based on the contents of this address, one of the following will occur:

a) If the data at 0x00B0 0000 is 0xA55A 5AA5, the ‘C40 will boot load

and execute the code contained in the Flash EEPROM.

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Pentek Model 4284 Operating Manual Page 61

4.2 Resetting and Booting the Model 4284 (continued)

4.2.1 The Power−Up or Push−Button Reset (continued)

3) DRAM Boot

(continued)

b) If the data at 0x00B0 0000 is anything different from 0xA55A 5AA5,

the ‘C40 will resume executing the code from the standard EPROM. The processor is left running a program that toggles the front panel LED and awaiting an interrupt to direct it elsewhere.

NOTE:

The boot sequence described above is followed only if your Model 4284 contains Boot EPROM Revision E or higher. If your 4284 is unable to boot from DRAM in the manner described above, contact Pentek at (201) 818−5900, and we will arrange for an EPROM upgrade.

Table 4−4, below, summarizes the addresses read during the boot proce−

dure, the significant data codes that may found at those addresses, and the actions taken if those codes are detected.

Table 4−4: Model 4284 − Addresses Read During EPROM Boot

Address Resource Data Code Action

A55A 5AA5

Boot Load from address pointed to by data at

0x8000 0001

0x8000 0000 Global DRAM

0x00B0 0000

Flash

EEPROM

If no problems are encountered in the boot procedure, and the processor followed one of the two possible paths that lead to continuing with the stan− dard EPROM boot, the LED on the 4284’s front panel will blink about five times a second (the blink rate is dependent upon the speed of the processor

− the ‘C40’s Timer 0 is used as a counter). If the factory boot code was exe− cuted and the LED only blinks around once per second, then the ‘C40 has had trouble accessing the shared DRAM. If the factory boot code was exe− cuted and the LED does not blink at all, then a more serious problem exists.

Pressing the Reset button on the Model 4284’s front panel will initiate a reset cycle identical to the power−up reset described above.

C33C 3CC3

Any other data Action based on contents of 0x00B0 0000

A55A 5AA5 Boot Load from Flash EEPROM (see Section 4.3.5)

Any other data Resume Boot of EPROM code

Resume Boot of EPROM Code (Blocks Flash

EEPROM Boot)

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Page 62 Pentek Model 4284 Operating Manual

4.2 Resetting and Booting the Model 4284 (continued)

4.2.2 The VME System Reset

In order for the VME System Reset signal to reach the ‘C40 processor on the Model 4284, a jumper must be installed between pins 1 and 2 of jumper block JB11 (see Section 2.8). The reset cycle that results from a VME System Reset is nearly identical to the Power−Up Reset described above, except that the Host Control Register is not cleared, so its contents will be unchanged by this reset.

If the 4284 is to be your Slot 1 VME System Controller, it must be configured to drive the VME System Reset line by installing a jumper between pins 1 and 2 of Jumper Block JB8. In this case, you may or may not want the Sys− tem Reset signal to reset the ‘C40 (i. e., the presence or absence of the jumper at JB11 1−2 is dictated by the requirements of your application).

The System Reset pulse delivered by the 4284 comes from a one−shot gener− ator (74HCT4538), and is triggered by writing a ‘1’ to bit D0 of the VMEbus Modifier Register at ‘C40 address 0x9000 0000.

4.2.3 The Host Control Reset

This reset is triggered when a VMEbus Master writes a ‘1’ to bit D0 of the VME Host Control Register at address A16_base+0x04. The ‘C40 processor will be held in the reset state until either (a) a VMEbus Master writes a ‘0’ to D0 of the Host Control Register, or (b) a Power−Up or Push−Button Reset occurs.

The effect of this Reset on the 4284 is nearly identical to that of a Power−Up Reset. The differences lies in the fact that, like the VME System Reset, this does not clear the Host Control Register (i. e., this bit does not reset itself). Additionally, the Host Control Reset DOES NOT RESET the MIX or VSB interfaces, which are reset by the Power−up, Push−button and VME Syatem Resets.

4.2.4 Booting From User Code

By rearranging the jumpers placed on JB4, the ‘C40 on the Model 4284 can be made to look at the Comm Ports, rather than the Pentek−supplied EPROM, for its boot code. Table 4−1, in Section 4.2.1 of this manual (see page 57), describes the jumper setting needed to boot from the Comm Port Interface. Jumper settings are also physically available that point to the Local and Global SRAMs, but these are not very useful because the SRAMs can only be written by the ‘C40.

Rev.: F.2

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Pentek Model 4284 Operating Manual Page 63

4.2 Resetting and Booting the Model 4284 (continued)

4.2.4 Booting from User Code (continued)

The boot may also be run from a program residing in the 4284’s Global DRAM or in the Flash EEPROM. To boot from either of the above, the jumpers on JB4 should remain at the factory settings (i. e., to boot from EPROM), shown in Table 4−1. The EPROM boot code directs the ‘C40 to read the first location in the DRAM (0x8000 0000). Based on the contents of that address, the ‘C40 may boot from DRAM, Flash EEPROM or resume the standard EPROM boot. See Section 4.2.1, above, for further details

To boot the 4284 from a Comm Port, set the jumpers on JB4 as shown in the top line of Table 4−1, install the 4284 in the VME card cage, and apply power. The loader waits for the first input data from any of the six Comm Ports, then loads the code from that channel.

NOTE:

A more detailed description of the boot load procedure and the structure of the boot source program’s data stream can be found in Section 13.7.2 (Boot Loading Sequence) of the Texas Instruments TMS320C4x User's Guide. An example of 'C40 Assembly Language source code for a boot loader program is provided in Section 13.7.4 (Example of Communication Port Boot Loading) of that manual.

When the Model 4284 is booted from the code provided in the factory−supplied Boot EPROM, the value stored in the ‘C40’s internal Local Memory Interface Control Register (address 0x0010 0004) is manipulated. If the EPROM boot is allowed to complete, this register will contain the value 0x3DEF 0000, which allows the ‘C40 to properly access the MIX bus. If, however, the boot is re−directed to another source (e. g., Flash EEPROM or Comm Port), the instruction that sets this value will never be reached. In such cases, the “new” boot code must also write the value 0x3DEF 0000 to ‘C40 address 0x0010 0004, to enable access to the MIX bus.

4.3 Flash EEPROM Operations

The Flash EEPROM Options (Options 002 (128k x 8) and 003 (512k x 8)) support non− volatile storage of programs for boot loading. Other data, such as short tables, may also be stored here. This resource is mapped into the ‘C40’s Local Bus memory map, beginning at address 0x00B0 0000.

Any data to be stored in this memory region must be in Intel HEX format. A program for converting COFF program files into this format, hex30, is provided by Texas Instrtuments as a part of their Optimizing ‘C’ Compiler package.

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Page 64 Pentek Model 4284 Operating Manual

4.3 Flash EEPROM Operations (continued)

In most cases, when this option is included on the Model 4284, the user's goal is to have the processor boot load the code in the Flash EEPROM immediately upon power−up or warm reset. The procedures involved in accomplishing that goal will involve all of the operations one might want to perform using the Flash memory. We will therefore describe the procedures for loading bootable HEX code into the Flash EEPROM, and boot loading into that code, in the sections below.

4.3.1 Converting COFF Files into Intel HEX Format

Program files to be written into the 4284’s Flash EEPROM must be in Intel HEX format. COFF (Common Object File Format) files, of the type nor− mally written into the 4284’s DRAM or SRAM regions, can be converted into Intel HEX format by creating an appropriately−named linker com− mand file for the program, and passing the linker command file's name to the hex30 program, supplied by Texas Instruments. The COFF file to be converted should have the extension .out or .x40. The linker command file's name should have the extension .cmd. An example of such a linker command file, boot84.cmd, is presented in Figure 4−2, below, and is also included in Section A.6 of this manual. The command line syntax to create the Intel HEX file demo84.hex from the COFF file led84.out, using the linker command file shown in Figure 4−2 would be:

hex30 boot84.cmd<enter>

/************* FILE - boot84.cmd **************/ /**********************************************/ /* Boot build for C40 EEPROM */ /**********************************************/ led84.out /* Input file */

-o demo84.hex /* HEX output file */

-i /* intel format */

-memwidth 8 /* 8-bit memory */

-boot /* Convert all .sect */

-bootorg 0h /* Boot source addr */

-cg 3D9EC000h /* Global mem conf. */

-cl 3DEF4110h /* Local mem conf. */

-e c0000c53h /* PC after load addr */

-iack 4003fc00h /* IACK dummy read */

-ivtp 4003fc00h /* IV pointer */

-tvtp 4003fc00h /* TV pointer */ /**********************************************/

Rev.: F.2

Figure 4−2: Model 4284 − Linker Command File for COFF

− HEX File Conversion

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Pentek Model 4284 Operating Manual Page 65

4.3 Flash EEPROM Operations (continued)

4.3.1 Converting COFF Files into Intel HEX Format (continued)

To modify the linker command file shown at the bottom of the previous page to work with COFF files of your own, substitute the name of your COFF file on the /*Input file*/ line, and the name you wish the new HEX file to be given after the -o on the /*HEX output file*/ line. Examine the map file created when your COFF file was compiled to find the entry point, and substitute that address after the -e on the /*PC after load addr*/ line.

Before compiling the file that will be passed to the conversion routine shown above, it may be necessary to add the line shown below to the .main section of your source code. This line is needed if the code involves access to the MIX bus. It establishes a pointer to the ‘C40’s Local Control Port from Flash EEPROM space.

*(unsigned int*)0x100004=0x3DEF4000

4.3.2 Loading the HEX File into the Shared Global DRAM

The procedure above created a HEX file, residing in your workstation, that is suitable for writing into the 4284’s Flash EEPROM. The Flash EEPROM on the Model 4284 resides on the ‘C40's Local bus, and can be accessesed

ONLY

shared memory area (i. e., the Global DRAM) before it can be written into the Flash EEPROM.

The HEX file should be written into the 4284’s Global DRAM in the format shown in Table 13−4 (Byte−Wide Configured Memory) , in Section 13.7.3 (External Memory Boot Loading) of the Texas Instruments TMS320C4x User's Guide. The contents of the HEX file must be offset from the begin− ning of the block that will be transferred into the Flash EEPROM by 8 bytes (2 longwords). This is necessary so that the Flash Boot Flag (0xA55A 5AA5) and Flash Boot Code Start Address (0x00B0 0008) may be inserted at the first two locations in the block.

For example, if one wished to load a HEX file at the Global DRAM block beginning at VMEbus address DRAM_base+0x0000 1000, the first byte of the HEX file should be placed at VMEbus address DRAM_base+0x0000 1008.

by the ‘C40. Therefore, the HEX file must be written into the 4284’s

4.3.3 Erasing the Flash EEPROM

Before new data can be loaded into the Flash EEPROM, the existing data must first be erased. Two methods are available for erasing the Flash mem− ory. The first method is the simpler of the two, but it can only be used erase the entire content of the EEPROM. The second method can be used to selec− tively erase 64 kByte sectors of the EEPROM.

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Page 66 Pentek Model 4284 Operating Manual

4.3 Flash EEPROM Operations (continued)

4.3.3 Erasing the Flash EEPROM (continued)

4.3.3.1 Erasing All of Flash EEPROM from the TCK Connector

To erase the entire contents of the Flash EEPROM, connect a shorting jumper between pins 3 and 5 of the front panel TCK connector (see Figure 4−3, below), and then push the Reset button. When the 4284 is reset in this manner, the LED indicator will remain lit until the Flash EEPROM is completely erased, and then blink normally.

Figure 4−3: TCLK I/O Connector

4.3.3.2 Erasing Selected Flash EEPROM Sectors

The Flash EEPROM used on the Model 4284 is partitioned into 64 kByte sectors. Option 002 (128 kBytes) has two sectors, and Option 003 (512 kBytes) has eight sectors. Table 4−5, below, lists the starting addresses of each Flash EEPROM sector.

Table 4−5: Model 4284 − Flash

EEPROM Sector Start Addresses

Sector Start Address

0 0x00B0 0000 1 0x00B1 0000 2 0x00B2 0000 3 0x00B3 0000 4 0x00B4 0000 5 0x00B5 0000 6 0x00B6 0000 7 0x00B7 0000

Option 002 contains only sectors 0 and 1,

NOTE:

Option 003 contains all 8 sectors

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Pentek Model 4284 Operating Manual Page 67

4.3 Flash EEPROM Operations (continued)

4.3.3 Erasing the Flash EEPROM (continued)

4.3.3.2 Erasing Selected Flash EEPROM Sectors (continued)

Individual sectors of the Flash memory can be erased by calling some of the functions described in Table 4−2, on page 59 of this manual. The procedure is described below:

1) Read the pointer to the Flash Erase Sector function from DRAM_base+0x0854. Write the result of that read into the Host Function Command Pointer location, DRAM_base+0x0000 0800.

2) Write the address of the sector to be erased (from

Table 4−5, previous page) to the Flash Boot Address location,

DRAM_base+0x0000 0804.

3) Write a '0' to the Host Ready Flag Location, DRAM_base+0x0000 0810.

4) Set the Host Interrupt Bit in the 4284's Host Control Register to the '1' state, by writing a '2' to A16_base+0x0004.

5) The firmware will now begin to erase the Flash EEPROM sector at the address given in step (2), on the previous page.

6) Poll the Host Ready Flag (DRAM_base+0x0000 0810). This will be set to the '1' state by the firmware upon completion of the sector erase operation.

If necessary, the procedure described above can be repeated to erase additional sectors. Note that the entire Flash EEPROM can also be erased using the procedure above, if you begin by copying the Flash Erase function pointer (at DRAM_base+0x0000 0850) to the Host Command location, instead of the Flash Erase Sector pointer.

4.3.4 Moving the Code from Global DRAM to Flash EEPROM

After the Flash EEPROM sectors you wish to move your code into have been erased, you are ready to copy your code from the DRAM to the Flash EEPROM. This will also involve the use of some of the firmware functions described in Table 4−2 (see page 59). A description of the procedure begins at the top of the next page.

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Page 68 Pentek Model 4284 Operating Manual

4.3 Flash EEPROM Operations (continued)

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1) Read the pointer to the Flash Word Load function from DRAM_base+0x0000 0860. Write the result of that read into the Host Function Command Pointer location, DRAM_base+0x0000 0800.

2) Write the address of the source data in DRAM to the Flash Boot Address location, DRAM_base+0x0000 0804. If, for example, the HEX file was written to a Global DRAM block beginning at VMEbus address DRAM_base+0x0000 1000 (as described in Section 4.3.2), the equivalent 'C40 address (0x8000 0400) would be written to DRAM_base+0x0000 0804).

3) Write the starting address of the Flash EEPROM sector that you wish to move the code into (from Table 4−5, page 66) to the Block Move Destination location (DRAM_base+0x0000 0808). If you wish to be able

to boot this code by any of the conventional methods (i. e., power−up, reset button, VME System Reset or Host Control Reset), move the code to EEPROM sector 0.

4) Subtract 1 from the number of longwords to be moved into the Flash EEPROM (i. e., (number of bytes / 4) − 1). Write the result into the Block Length location, DRAM_base+0x0000 080C.

5) Write a ‘0’ to the Host Ready Flag Location, DRAM_base+0x0810.

6) Set the Host Interrupt Bit in the 4284’s Host Control Register to the ‘1’ state, by writing a ‘2’ to A16_base+0x0004.

7) The firmware will now begin to move 32−bit longwords from the DRAM address given in step (2) of this procedure to the Flash EEPROM sector at the address given in step (3) (see previous page).

8) Poll the Host Ready Flag (DRAM_base+0x0000 0810). This will be set to the ‘1’ state by the firmware upon completion of the block move operation.

4.3.5 Booting the Flash EEPROM Program

After following the procedure above, you have a choice of methods that you may use to execute the code that you have stored in the Flash EEPROM. If you loaded the code into sector 0 of the Flash EEPROM, then it can be exe− cuted at power−up (see Section 4.2.1), by pushing the reset button, or by any of the other reset methods described in Section 4.2.

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Pentek Model 4284 Operating Manual Page 69

4.3 Flash EEPROM Operations (continued)

4.3.5 Booting the Flash EEPROM Program (continued)

If the code was not loaded into sector 0, then the code cannot be booted by conventional methods. It can be booted, however, by the firmware func− tions in EPROM. The procedure for this is described below.

1) Read the pointer to the Flash Boot function from DRAM_base+0x0860.

Write the result of that read into the Host Function Command Pointer location, DRAM_base+0x0800.

2) Write the Flash EEPROM address of the code you wish to boot to the Flash

Boot Address location, DRAM_base+0x0804.

3) Set the Host Interrupt Bit in the 4284's Host Control Register to the '1'

state, by writing a '2' to A16_base+0x04.

4) Firmware will now boot the code that it finds at the Flash EEPROM at the

sector address given in step (2).

NOTE:

When the Model 4284 is booted from the code provided in the factory−supplied Boot EPROM, the value stored in the ‘C40’s internal Local Memory Interface Control Register (address 0x0010 0004) is manipulated. If the EPROM boot is allowed to complete, this register will contain the value 0x3DEF 0000, which allows the ‘C40 to properly access the MIX bus. If, however, the boot is re−directed to another source (e. g., Flash EEPROM), the instruction that sets this value will never be reached. In such cases, the “new” boot code must also write the value 0x3DEF 0000 to ‘C40 address 0x0010 0004, to enable access to the MIX bus.

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Page 70 Pentek Model 4284 Operating Manual

4.4 Downloading Programs to the Model 4284

‘C40 programs in Common Object File Format (COFF) can be transferred into the 4284’s shared DRAM over the VMEbus. One recommended method for achieving this file transfer is via Pentek’s SwiftNet Communications Protocols. Another is via the Texas Instruments XDS−510 Emulator.

4.4.1 Downloading Programs with SwiftNet

Pentek’s SwiftNet Communications Protocols are used to provide data transfer links over a distributed DSP network. Included with SwiftNet is a utility program, PNCFG, used to identify and provide essential information about the processors in the network. Another Program, PNLOAD, is used to transfer COFF files from the host system on which they were developed to target DSPs defined in PNCFG. COFF files may be developed in Pentek’s SwiftTools Environment, which can call PNLOAD to accomplish the file transfer, or with any ‘C40 compatible compiler/assembler/linker package. See the SwiftNet and SwiftTools Operating Manuals for further details.

4.4.2 Downloading Programs with the XDS−510 Emulator

Users of the Texas Instruments XDS−510 Emulator can transfer 'C40 COFF programs into the 4284 via the front panel JTAG connector. For that code to be properly executed, however, the 4284’s register set must be put into its boot state. This must be done by the user, because operating environment of the emulator prevents the 4284 from executing its boot code at power−up.

There are also two registers internal to the ‘C40 which must be initialized before you try to access the external registers. The Global Memory Interface Control Register, at address 0x0010 0000, must be set to 0x3D9E C000, and the Local Memory Interface Control Register, at address 0x0010 0004, must be set to 0x3DEF 4710. You may either load these values from the emula− tor’s command interface, or place commands to initialize the registers at the beginning of any program you may load. For more information about the use of these registers, see Sections 7.3 (Memory Interface Control Registers) and 7.4 (Programmable Wait States) of the the Texas Instruments TMS320C4x User's Guide.

One method of initializing the external register set is to issue the RUN com− mand from the emulator, and then push the reset button, before loading your code. Another method is to initialize the registers explicitly at the beginning of your code, after setting up the internal registers (see the last paragraph on the previous page). See Table 4−3, in Section 4.2.1 of this manual (see page 60), for the external register addresses and states to which they should be initialized.

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Pentek Model 4284 Operating Manual Page 71

4.5 Handling Interrupts on the Model 4284

Interrupts targeted for the four interrupt inputs of the ‘C40 processor on the Model 4284 can come from any three of the seven VMEbus IRQs , from the three MIX module inter− rupt lines, from the Host Control Register, or may be caused by a VMEbus time−out. The sections below describe and contrast the handling of interrupts from all these sources.

4.5.1 Handling VMEbus Interrupts

Up to three of the seven VMEbus IRQs may be connected to the ‘C40 proces− sor on the Model 4284. These are selected by placing jumpers on jumper block JB13. Table 4−6, below, describes the settings available on this jumper block.

Table 4−6: Model 4284 − VMEbus IRQ Configuration Jumpers

Jumper Block JB13

VMEbus

IRQLevel

IRQ1 1 − 2 N/A N/A

IRQ2 3 − 5 11 − 13 13 − 14

IRQ3 2 − 4 11 − 12 12 − 14

IRQ4 5 − 6* 6 − 8 14 − 16

IRQ5 5 − 7 7 − 8 15 − 17

IRQ6 19 − 20 9 − 11* 17 − 19

IRQ7 18 − 20 8 − 10 17 − 18*

N/A = Not Available * − Factory Default Settings

VME_IRQ_A VME_IRQ_B VME_IRQ_C

‘C40 Interrupt Requests

Selecting the VMEbus IRQs that can interrupt the processor does not quite finish the job of interrupt enabling, however. The ‘C40 Interrupt Routing Register, at ‘C40 address 0x1000 0003, must be programmed to a value that will select the interrupts you need to respond to (from among the eight possible interrupt sources on the 4284), and connects one or more of them to one or more of the four interrupt inputs on the ‘C40.

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4.5 Handling Interrupts on the Model 4284 (continued)

4.5.1 Handling VMEbus Interrupts (continued)

Table 4−7, below, describes the connections that can be made by this register.

A ‘1’ in any bit connects the source to the indicated interrupt. As shown in the table, the low order byte of this 32−bit register (D0 − D7) connects interrupt sources to INT_0, the next higher order byte (D8 − D15) connects them to INT_1, the second highest order byte (D16 − D23) connects with INT_2, and the most significant byte delivers interrupts to INT_3. As far as the VME IRQs are concerned, the least significant bit in each byte (D0, D8, D16 and D24) connects VME_IRQ_A to that byte’s ‘C40 interrupt input, the next higher order bit in each byte (D1, D9, D17 and D25) connects VME_IRQ_B, and VME_IRQ_C is routed to the ‘C40 by means of the third bit in each byte of the register (D2, D10, D18, and D26). By default, the only interrupt that this reg− ister enables (when the 4284 is booted with the code Pentek supplies in the EPROM), is the Host Control Interrupt, which gets connected to INT_1.

Table 4−7: Model 4284 − ‘C40 Interrupt Routing Register − R/W @ 0x1000 0003