Pegatron VA70HW, Aspire V3-772 Schematic

5

4

3

2

1

VA70HW BLOCK DIAGRAM

HDMI

PAGE 38

eDP Panel

D D

C C

B B

PAGE 37

CRT

Head Phone
(Combo Jack)

MIC

TPM

K/B

Click T/P

FAN

PAGE 39

PAGE 58

PAGE 43

PAGE 48

PAGE 48

PAGE 49

DDIC

eDP x 2

NVIDIA N14E

Azalia Codec
RTK/ALC3225

EC
IT8528E

SPI ROM
4MB (BIOS/EC)

SPI ROM
2MB (ME)

dGPU

PAGE 41 42

PAGE 30

PAGE 28

PAGE 70~79

PAGE 30

SATA HDD

SATA HDD

SATA ODD

PCIE X 16

VGA

Azalia

LPC

HSPI

SPI

PAGE 60

PAGE 60

PAGE 60

CPU

Haswell

FDI x 2

PCH

Lynx Point

SATA

PAGE 3-10

DMI x 4

PAGE 13-19

PCIE *1

PCIE *1

PCIE *1

SATA 3.0

DDR3L 1333/1600 MHz
channel A

DDR3L 1333/1600 MHz
channel B

USB2.0

USB2.0

USB2.0

USB2.0

USB3.0

USB2.0

USB3.0

PCIE *1

USB2.0

DDR-III
SO-DIMM*2

DDR-III
SO-DIMM*2

Camera

USB PORT9

USB PORT2

USB20 PORT1
USB30 PORT2

USB20 PORT0
USB30 PORT1

MiniCard
WLAN/WMAX

BT combo

Giga LAN
BCM57780

Card Reader
RTS5209

mSATA/SSD

PAGE 16

PAGE 17

PAGE 58

PAGE 61

PAGE 55

PAGE 33

PAGE 40

PAGE 40

PAGE 53

RJ45

PAGE 34

SD Socket

五五五五五五五五五五五五

PAGE 40

POWER

CPU VCORE

SYSTEM, +3V, +5V

+VCCP & +VCCP_VT

DDR & VTT

2.5V & 1.5VS &1.1VS

SMART CHARGER

POWER DETECT

LOAD SWITCH

POWER PROTECT

Power Rails

Sleep State

S0 ON

S3 OFFON ONON

PCIe Port

PCIE_P1

PCIE_P2

PCIE_P3

PCIE_P4

PCIE_P5

PCIE_P6

USB20 PORT

USB P00

USB P01

USB P02

USB P03

USB P04

USB P05

USB P08

USB P09

USB P10

USB P11

USB P12

USB P13

PAGE 80

PAGE 81

PAGE 82

PAGE 83

PAGE 84

PAGE 88

PAGE 90

PAGE 91

PAGE 92

RTC VA VSUS

ON ON

CARDREADER

mSATA

Mini CARD (WLAN)

LAN

External MB

External MB

External DB

WiFi

Camera

External DB

BT

PCIE/mSATA

VGA POWER

GPU VCORE

+1.05VS_VGA

+3VS_VGA

+12VS_VGA

LOAD SWITCH

POWER PROTECT

ON

PAGE 80

PAGE 91

PAGE 92

VS

OFFS4 ON ONON

OFFON ONONS5/ AC

OFFS5/ DC ON OFFON

SATA PORT

SATA P0 HDD 1

SATA P1

ODD

IO BOARD PWR BOARD

USB PORT3

A A

USB PORT9

5

4

HP_OUT

MIC IN

POWER Button

POWER LED

LID SW

3

2

SATA P2

SATA P3

SATA P4

mSATA

SATA P5

HDD 2

BLOCK DIAGRAM

BLOCK DIAGRAM

BLOCK DIAGRAM

Title :

Title :

Title :

Wing_Cheng

Wing_Cheng

Wing_Cheng

Engineer:

Engineer:

BU1-RD Div.1-HW RD Dept.1

BU1-RD Div.1-HW RD Dept.1

BU1-RD Div.1-HW RD Dept.1

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Engineer:

VA70_HW

VA70_HW

VA70_HW

1

Rev

Rev

Rev

1.0

1.0

1 96Monday, February 04, 2013

1 96Monday, February 04, 2013

1 96Monday, February 04, 2013

1.0

5

4

3

2

1

+VCCIOA_OUT

U0301A

D D

C C

B B

DMI_TXN022
DMI_TXN122
DMI_TXN222
DMI_TXN322

DMI_TXP022
DMI_TXP122
DMI_TXP222
DMI_TXP322

DMI_RXN022
DMI_RXN122
DMI_RXN222
DMI_RXN322

DMI_RXP022
DMI_RXP122
DMI_RXP222
DMI_RXP322

FDI_CSYNC22
FDI_INT22

D21
C21
B21
A21

D20
C20
B20
A20

D18
C17
B17
A17

D17
C18
B18
A18

H29

J29

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

FDI_CSYNC
DISP_INT

Haswell rPGA EDS

DMI FDI

PEG_RCOMP

PEG_RXN_10
PEG_RXN_11
PEG_RXN_12
PEG_RXN_13
PEG_RXN_14
PEG_RXN_15

PEG

PEG_RXP_10
PEG_RXP_11
PEG_RXP_12
PEG_RXP_13
PEG_RXP_14
PEG_RXP_15

PEG_TXN_10
PEG_TXN_11
PEG_TXN_12
PEG_TXN_13
PEG_TXN_14
PEG_TXN_15

PEG_TXP_10
PEG_TXP_11
PEG_TXP_12
PEG_TXP_13
PEG_TXP_14
PEG_TXP_15

PEG_RXN_0
PEG_RXN_1
PEG_RXN_2
PEG_RXN_3
PEG_RXN_4
PEG_RXN_5
PEG_RXN_6
PEG_RXN_7
PEG_RXN_8
PEG_RXN_9

PEG_RXP_0
PEG_RXP_1
PEG_RXP_2
PEG_RXP_3
PEG_RXP_4
PEG_RXP_5
PEG_RXP_6
PEG_RXP_7
PEG_RXP_8
PEG_RXP_9

PEG_TXN_0
PEG_TXN_1
PEG_TXN_2
PEG_TXN_3
PEG_TXN_4
PEG_TXN_5
PEG_TXN_6
PEG_TXN_7
PEG_TXN_8
PEG_TXN_9

PEG_TXP_0
PEG_TXP_1
PEG_TXP_2
PEG_TXP_3
PEG_TXP_4
PEG_TXP_5
PEG_TXP_6
PEG_TXP_7
PEG_TXP_8
PEG_TXP_9

E23
M29
K28
M31
L30
M33
L32
M35
L34
E29
D28
E31
D30
E35
D34
E33
E32
L29
L28
L31
K30
L33
K32
L35
K34
F29
E28
F31
E30
F35
E34
F33
D32
H35
H34
J33
H32
J31
G30
C33
B32
B31
A30
B29
A28
B27
A26
B25
A24
J35
G34
H33
G32
H31
H30
B33
A32
C31
B30
C29
B28
C27
B26
C25
B24

PEG_COMP

PEG_RXN15
PEG_RXN14
PEG_RXN13
PEG_RXN12
PEG_RXN11
PEG_RXN10
PEG_RXN9
PEG_RXN8
PEG_RXN7
PEG_RXN6
PEG_RXN5
PEG_RXN4
PEG_RXN3
PEG_RXN2
PEG_RXN1
PEG_RXN0
PEG_RXP15
PEG_RXP14
PEG_RXP13
PEG_RXP12
PEG_RXP11
PEG_RXP10
PEG_RXP9
PEG_RXP8
PEG_RXP7
PEG_RXP6
PEG_RXP5
PEG_RXP4
PEG_RXP3
PEG_RXP2
PEG_RXP1
PEG_RXP0
PEG_TXN0_C
PEG_TXN1_C
PEG_TXN2_C
PEG_TXN3_C
PEG_TXN4_C
PEG_TXN5_C
PEG_TXN6_C
PEG_TXN7_C
PEG_TXN8_C
PEG_TXN9_C
PEG_TXN10_C
PEG_TXN11_C
PEG_TXN12_C
PEG_TXN13_C
PEG_TXN14_C
PEG_TXN15_C
PEG_TXP0_C
PEG_TXP1_C
PEG_TXP2_C
PEG_TXP3_C
PEG_TXP4_C
PEG_TXP5_C
PEG_TXP6_C
PEG_TXP7_C
PEG_TXP8_C
PEG_TXP9_C
PEG_TXP10_C
PEG_TXP11_C
PEG_TXP12_C
PEG_TXP13_C
PEG_TXP14_C
PEG_TXP15_C

CX0301 0.22UF/10V /EGL
CX0302 0.22UF/10V /EGL
CX0303 0.22UF/10V /EGL
CX0304 0.22UF/10V /EGL
CX0305 0.22UF/10V /EGL
CX0306 0.22UF/10V /EGL
CX0307 0.22UF/10V /EGL
CX0308 0.22UF/10V /EGL
CX0309 0.22UF/10V /DGPU
CX0310 0.22UF/10V /DGPU
CX0311 0.22UF/10V /DGPU
CX0312 0.22UF/10V /DGPU
CX0313 0.22UF/10V /DGPU
CX0314 0.22UF/10V /DGPU
CX0315 0.22UF/10V /DGPU
CX0316 0.22UF/10V /DGPU
CX0317 0.22UF/10V /EGL
CX0318 0.22UF/10V /EGL
CX0319 0.22UF/10V /EGL
CX0320 0.22UF/10V /EGL
CX0321 0.22UF/10V /EGL
CX0322 0.22UF/10V /EGL
CX0323 0.22UF/10V /EGL
CX0324 0.22UF/10V /EGL
CX0325 0.22UF/10V /DGPU
CX0326 0.22UF/10V /DGPU
CX0327 0.22UF/10V /DGPU
CX0328 0.22UF/10V /DGPU
CX0329 0.22UF/10V /DGPU
CX0330 0.22UF/10V /DGPU
CX0331 0.22UF/10V /DGPU
CX0332 0.22UF/10V /DGPU

1 2

R0301 24.9Ohm1%

R1.2 2012/12/19
CX0301~CX0308, CX0317~CX0324 options are changed to /EGL

12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12

PEG_RXN[15:0] 70

PEG_RXP[15:0] 70

+VCCIOA_OUT

+VCCIOA_OUT 4,6

PEG Compensation

Enable PCIE Lane Reversal
Need to PD CFG[2]

PEG_TXN15 70
PEG_TXN14 70
PEG_TXN13 70
PEG_TXN12 70
PEG_TXN11 70
PEG_TXN10 70
PEG_TXN9 70
PEG_TXN8 70
PEG_TXN7 70
PEG_TXN6 70
PEG_TXN5 70
PEG_TXN4 70
PEG_TXN3 70
PEG_TXN2 70
PEG_TXN1 70
PEG_TXN0 70
PEG_TXP15 70
PEG_TXP14 70
PEG_TXP13 70
PEG_TXP12 70
PEG_TXP11 70
PEG_TXP10 70
PEG_TXP9 70
PEG_TXP8 70
PEG_TXP7 70
PEG_TXP6 70
PEG_TXP5 70
PEG_TXP4 70
PEG_TXP3 70
PEG_TXP2 70
PEG_TXP1 70
PEG_TXP0 70

SOCKET_947P

12V012BSM001

A A

5

4

If Support PCIE Gen3, change AC Cap to 0.22uF

3

Title :

Title :

Title :

Engineer:

Engineer:

PEGATRON COMPUTER INC

PEGATRON COMPUTER INC

PEGATRON COMPUTER INC

Size Project Name

Size Project Name

Size Project Name

B

B

B

Date: Sheet of

Date: Sheet of

Date: Sheet of

2

VA70_HW

VA70_HW

VA70_HW

Engineer:

CPU(1)_DMI,PEG,FDI,CLK,MISC

CPU(1)_DMI,PEG,FDI,CLK,MISC

CPU(1)_DMI,PEG,FDI,CLK,MISC

Wing_Cheng

Wing_Cheng

Wing_Cheng

3 96Friday, January 18, 2013

3 96Friday, January 18, 2013

3 96Friday, January 18, 2013

1

Rev

Rev

Rev

1.0

1.0

1.0

5

+VCCIO_OUT

+1.05VS

H_PECI25

D D

R1.2 2012/11/26
reserved for 2014 processor

CLK_DP_N21
CLK_DP_P21

C C

C0404

0.1UF/10V

+VCCIO_OUT

SP0406 R0603
SP0407 R0603

R1.2 2012/11/08
cost dwon 0ohm

+VCCIO_OUT

12

Stuff R0408

@

Intel MOW WW14: stuff
H_CPUPWRGD PD 10Kohm

1 2
1 2

1KOhm

CLK_DP_SSC _P_R

CLK_DP_SSC _N_R

12

R0440
100KOhm

@

H_PECI

R1.1

12

@

R04171KOh m

CLK_DP_N_R
CLK_DP_P_R

R0418

12

@

@

1 2

R0419 10KOhm

1 2

R0420 10KOhm

@

12

R040462Ohm

H_THRMTR IP#25,47

H_CPUPW RGD25
PM_DRAM_PW RGD22
PCH_PLTRS T_CPU#25

CLK_DP_SSC _N21

CLK_DP_SSC _P21

+VCCIO_OUT

H_PM_SYNC22

R1.0 PU/PD for JTAG signals

+1.05VS

VCCST
XDP_TMS
XDP_TDI_R
XDP_PREQ#

XDP_TCK
XDP_TRST#

B B

1 2

R0401 51Ohm@

1 2

R0402 51Ohm@

1 2

R0406 51Ohm

@

1 2

R0407 51Ohm

1 2

R0405 51Ohm

4

1

T0419

1

T0420

H_PROCHOT#

CLK_EXP_N21
CLK_EXP_P21

SSC CLOCK TERMINATION
Stuff R0445 & R0446 only when SSC clock not used

1 2

R0430 0Ohm@

R0403 56Ohm

12

R040810KOhm

SP0408 R0 402
SP0409 R0 402

SP0405 R0402
SP0404 R0402

HDMI_TXN2_PCH39
HDMI_TXP2_PCH39
HDMI_TXN1_PCH39
HDMI_TXP1_PCH39
HDMI_TXN0_PCH39
HDMI_TXP0_PCH39
HDMI_CLKN_PC H39
HDMI_CLKP_PCH39

DDI Port B: N/A
DDI Port C: HDMI
DDI Port D: DP to VGA

DDI signals Mapping, check 497750

12
12

SP0401R0402

12

SP0402R0402

12

SP0403R0402

1 2
1 2

1 2

SP0410 R0 603

1 2

SP0411 R0 603

1 2
1 2

TP_SKTOCC# _R

TP_CATERR# _R

H_PROCHOT# _D
H_THRMTR IP#_R

H_PM_SYNC_R

H_CPUPW RGD_R
VDDPWRGOOD_ R

R1.2 2012/11/08
cost dwon 0ohm

CLK_DP_SSC _N_R
CLK_DP_SSC _P_R

CLK_EXP_N_R
CLK_EXP_P_R

U0301B

AP32

SKTOCC#

AN32

CATERR#

AR27

PECI

AK31

FC1

AM30

PROCHOT#

AM35

THERMTRIP#

AT28

PM_SYNC

AL34

PWRGOOD

AC10

SM_DRAMPWROK

AT26

PLTRSTIN#

G28

DPLL_REF_CLKN

H28

DPLL_REF_CLKP

F27

SSC_DPLL_REF_CLKN

E27

SSC_DPLL_REF_CLKP

D26

BCLKN

E26

BCLKP

SOCKET_947P

12V012BSM001

T28
U28
T30
U30
U29
V29
U31
V31

T34
U34
U35
V35
U32
T32
U33
V33

P29
R29
N28
P28
P31
R31
N30
P30

SOCKET_947P

12V012BSM001

U0301H

DDIB_TXBN_0
DDIB_TXBP_0
DDIB_TXBN_1
DDIB_TXBP_1
DDIB_TXBN_2
DDIB_TXBP_2
DDIB_TXBN_3
DDIB_TXBP_3

DDIC_TXCN_0
DDIC_TXCP_0
DDIC_TXCN_1
DDIC_TXCP_1
DDIC_TXCN_2
DDIC_TXCP_2
DDIC_TXCN_3
DDIC_TXCP_3

DDID_TXDN_0
DDID_TXDP_0
DDID_TXDN_1
DDID_TXDP_1
DDID_TXDN_2
DDID_TXDP_2
DDID_TXDN_3
DDID_TXDP_3

Haswell rPGA EDS

MISC

PWR

CLOCKTHERMAL

Haswell rPGA EDS

DDI

3

eDP

SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2

DDR3

SM_DRAMRST#

JTAG

BPM_N_0
BPM_N_1
BPM_N_2
BPM_N_3
BPM_N_4
BPM_N_5
BPM_N_6
BPM_N_7

EDP_AUXN
EDP_AUXP

EDP_HPD

EDP_RCOMP

EDP_DISP_UTIL

EDP_TXN_0
EDP_TXP_0
EDP_TXN_1
EDP_TXP_1

FDI_TXN_0
FDI_TXP_0
FDI_TXN_1
FDI_TXP_1

PRDY#
PREQ#

TMS

TRST#

TDO

DBR#

2

+VCCIO_OUT

+1.35V_VCCDDQ

AP3

SM_RCOMP_0

AR3

SM_RCOMP_1

AP2

SM_RCOMP_2

AN3

AR29
AT29
AM34

TCK

AN33
AM33
AM31

XDP_TDI_R

TDI

AL33

XDP_TDO_R

AP33

H_DBR#_R

AR30
AN31
AN29
AP31
AP30
AN28
AP29
AP28

M27
N27
P27
E24
R27

P35
R35
N34
P34
P33
R33
N32
P32

R0411 100Ohm1%
R0412 75Ohm1%
R0413 100Ohm1%

XDP_PRDY#
XDP_PREQ#
XDP_TCK
XDP_TMS
XDP_TRST#

DP_COMP

R0410 2 4.9Ohm1%

R1.2 2012/10/29
option changed from /non_FDI

R1.2 2012/12/06
remove R0436~R0439 for GDDR5

R0432 0Ohm
R0433 0Ohm
R0434 0Ohm
R0435 0Ohm

12
12
12

XDP_BPM0
XDP_BPM1
XDP_BPM2
XDP_BPM3
XDP_BPM4
XDP_BPM5
XDP_BPM6
XDP_BPM7

EDP_AUXN 37

EDP_AUXP 37

EDP_HPD# 37

1 2

EDP_DISP_UTIL 37

EDP_TXN0 37
EDP_TXP0 37
EDP_TXN1 37
EDP_TXP1 37

12
12
12
12

R1.2 2012/10/29
option changed from /FDI

+VCCIOA_OUT

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

CPUDRAMRST# 5

T0403
T0404
T0405
T0406
T0407
T0408
T0409
T0410

T0411
T0412
T0413
T0414
T0415
T0416
T0417
T0418

FDI_TXN0 22
FDI_TXP0 22
FDI_TXN1 22
FDI_TXP1 22

+3VSUS

+3V

+1.05VS

+VCCIOA_OUT

1

+VCCIO_OUT 6,37,47,63

+1.35V_VCCDDQ 6

+3VSUS 22,23,27,28 ,30,33,43,61,81,92

+3V 37,43,63,65,91

+1.05VS 25,26,27,47 ,63,80,82

+VCCIOA_OUT 3,6

R1.2 2012/11/27
design gude and check list use 5%
Intel CRB 1%

PM_DRAM_PW RGD

Intel MOW WW14:

A A

change R0449, R0450 va lue

5

+1.35V_VCCDDQ

12

R04230Ohm

R1.1

Power good for +1.35V_VCCDDQ (delay > 15ns)
Processor may be damaged if VIH exceeds the maximum voltage for extended periods.
SM_DRAMPWROK VIH MAX = 1.0V ; VIH MIN=0.45*VDDQ

12

12

R0421

1.8KOhm

1%

0.87 Volt

R0424

9.09KOHM

R0422

3.3KOHM

1%

+3VSUS

@

U0401

A

5

VCC

Y

Vcc=1.65~5.5

@

C0403

0.22UF/10V

B

GND

12

12

@

+3VSUS

12

R0425

1

2

34

10KOhm

@

Q0402

3

PMBS3904

C

B

1

E
2

C0402

@

0.22UF/10V

@

4

+1.35V_VCCDDQ

R0426

1 2

12

17.4KOhm

12

@

R0427
47KOhm

1%

@

VR_HOT#80

Intel Comments

3

1 2

R0431 0Ohm@

H_PROCHOT#

C0401

47PF/50V

@

3

Q0401

2N7002

D

1

THRO_CPU

G

S

2

THRO_CPU 30

2

Title :

Title :

Title :

CPU(1)_DMI,PEG,FDI,CLK,MISC

CPU(1)_DMI,PEG,FDI,CLK,MISC

CPU(1)_DMI,PEG,FDI,CLK,MISC

Engineer:

Engineer:

VA70_HW

VA70_HW

VA70_HW

Engineer:

PEGATRON COMPUT ER INC

PEGATRON COMPUT ER INC

PEGATRON COMPUT ER INC

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Wing_Cheng

Wing_Cheng

Wing_Cheng

4 96Friday, January 18, 2013

4 96Friday, January 18, 2013

4 96Friday, January 18, 2013

1

Rev

Rev

Rev

1.0

1.0

1.0

1 2

5

4

3

2

1

+1.35V

D D

C C

DIMM_VREF_CA18

DRAMRST_CNTRL_PCH

DIMM0_VREF_DQ16,18

R1.2 2012/11/28
cost dwon 0ohm

DRAMRST_CNTRL_PCH DDR_CA_VREF

B B

DRAMRST_CNTRL_PCH

DIMM1_VREF_DQ17,18

CPU driven VREF path is stuffed by default
CRB 0.7

M_A_DQ[63:0]16

R1.2 2012/11/08

2N7002

cost dwon 0ohm

Q0506

12

3

D

SP0501
R0603

1

G

S

2

@

12

SP0502

34

Q0502B

R0603

D

@

5

S

G

UM6K1NG1DTN

UM6K1NG1DTN

G

12

S

2

@

Q0502A

D

6 1

SP0503
R0603

R1.2 2012/11/28
cost dwon 0ohm

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

DDR_WR_VREF01
DDR_WR_VREF02

R05151KOhm

12

1%

1%

@

AR15
AT14
AM14
AN14
AT15
AR14
AN15
AM15

AM9
AN9
AM8
AN8
AR9
AT9
AR8
AT8

AJ9

AK9

AJ6

AK6

AJ10

AK10

AJ7
AK7
AF4
AF5
AF1
AF2
AG4
AG5
AG1
AG2

J1
J2
J5
H5
H2
H1
J4
H4
F2
F1
D2
D3
D1
F3
C3
B3
B5
E6
A5
D6
D5
E5
B6
A6

E12
D12

B11

A11

E11
D11

B12

A12
AM3

F16

F13

R05101KOhm

R05091KOhm

12

12

1%

@

@

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
SM_VREF
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

Haswell rPGA EDS

U0301C

AC7

RSVD_AC7

U4

SA_CK_N_0

V4

SA_CK_P_0

AD9

SA_CKE_0

U3

SA_CK_N_1

V3

SA_CK_P_1

AC9

SA_CKE_1

U2

SA_CK_N_2

V2

SA_CK_P_2

AD8

SA_CKE_2

U1

SA_CK_N_3

V1

SA_CK_P_3

AC8

SA_CKE_3

M7

SA_CS_N_0

L9

SA_CS_N_1

M9

SA_CS_N_2

M10

SA_CS_N_3

M8

SA_ODT_0

L7

SA_ODT_1

L8

SA_ODT_2

L10

SA_ODT_3

V5

SA_BS_0

U5

SA_BS_1

AD1

SA_BS_2

V10

VSS1

U6

SA_RAS#

U7

SA_WE#

U8

SA_CAS#

V8
AC6
V9
U9
AC5
AC4
AD6
AC3
AD5
AC2
V6
AC1
AD4
V7
AD3
AD2

AP15
AP8
AJ8
AF3
J3
E2
C5
C11
AP14
AP9
AK8
AG3
H3
E3
C6
C12

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
SA_MA_15

SA_DQS_N_0
SA_DQS_N_1
SA_DQS_N_2
SA_DQS_N_3
SA_DQS_N_4
SA_DQS_N_5
SA_DQS_N_6
SA_DQS_N_7
SA_DQS_P_0
SA_DQS_P_1
SA_DQS_P_2
SA_DQS_P_3
SA_DQS_P_4
SA_DQS_P_5
SA_DQS_P_6
SA_DQS_P_7

SOCKET_947P

12V012BSM001

R1.0 S3 circuit:- DRAM_RST# to memory should be high during S3

R1.0 0209
Change R0508 to 1K ohm
R0508 close to DIMM

DDR3_DRAMRST#16,17 CPUDRAMRST# 4

DRAMRST_CNTRL_PCH21

+1.35V 6,16,18,63,83

M_B_DQ[63:0]17

M_A_DIM0_CLK_DDR#0 16
M_A_DIM0_CLK_DDR0 16
M_A_DIM0_CKE0 16
M_A_DIM0_CLK_DDR#1 16
M_A_DIM0_CLK_DDR1 16
M_A_DIM0_CKE1 16
M_A_DIM0_CLK_DDR#2 16
M_A_DIM0_CLK_DDR2 16
M_A_DIM0_CKE2 16
M_A_DIM0_CLK_DDR#3 16
M_A_DIM0_CLK_DDR3 16
M_A_DIM0_CKE3 16

M_A_DIM0_CS#0 16
M_A_DIM0_CS#1 16
M_A_DIM0_CS#2 16
M_A_DIM0_CS#3 16
M_A_DIM0_ODT0 16
M_A_DIM0_ODT1 16
M_A_DIM0_ODT2 16
M_A_DIM0_ODT3 16

M_A_BS0 16
M_A_BS1 16
M_A_BS2 16

M_A_RAS# 16

M_A_WE# 16

M_A_CAS# 16

M_A_A[15:0] 16

M_A_DQS#[7:0] 16

M_A_DQS[7:0] 16

+1.35V

1 2

R0508 1KOhm

R0520,R0521 must be grounded.
CRB 0.7

12

S

2

G

1

12

Haswell rPGA EDS

1 2

R0506 4.99KOhm

@

AR18

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

R0507
1KOhm

@

1 2

0614-change Q0501 from UM6K1N to 2N7002

CPUDRAMRST#_R

SB_DQ_0

AT18

SB_DQ_1

AM17

SB_DQ_2

AM18

SB_DQ_3

AR17

SB_DQ_4

AT17

SB_DQ_5

AN17

SB_DQ_6

AN18

SB_DQ_7

AT12

SB_DQ_8

AR12

SB_DQ_9

AN12

SB_DQ_10

AM11

SB_DQ_11

AT11

SB_DQ_12

AR11

SB_DQ_13

AM12

SB_DQ_14

AN11

SB_DQ_15

AR5

SB_DQ_16

AR6

SB_DQ_17

AM5

SB_DQ_18

AM6

SB_DQ_19

AT5

SB_DQ_20

AT6

SB_DQ_21

AN5

SB_DQ_22

AN6

SB_DQ_23

AJ4

SB_DQ_24

AK4

SB_DQ_25

AJ1

SB_DQ_26

AJ2

SB_DQ_27

AM1

SB_DQ_28

AN1

SB_DQ_29

AK2

SB_DQ_30

AK1

SB_DQ_31

L2

SB_DQ_32

M2

SB_DQ_33

L4

SB_DQ_34

M4

SB_DQ_35

L1

SB_DQ_36

M1

SB_DQ_37

L5

SB_DQ_38

M5

SB_DQ_39

G7

SB_DQ_40

J8

SB_DQ_41

G8

SB_DQ_42

G9

SB_DQ_43

J7

SB_DQ_44

J9

SB_DQ_45

G10

SB_DQ_46

J10

SB_DQ_47

A8

SB_DQ_48

B8

SB_DQ_49

A9

SB_DQ_50

B9

SB_DQ_51

D8

SB_DQ_52

E8

SB_DQ_53

D9

SB_DQ_54

E9

SB_DQ_55

E15

SB_DQ_56

D15

SB_DQ_57

A15

SB_DQ_58

B15

SB_DQ_59

E14

SB_DQ_60

D14

SB_DQ_61

A14

SB_DQ_62

B14

SB_DQ_63

R0501 0Ohm

Q0501

@

2N7002

D

3

C0501

@

0.047UF/16V

U0301D

AG8

RSVD1

Y4

SB_CKN0

AA4

SB_CK0

AF10

SB_CKE_0

Y3

SB_CKN1

AA3

SB_CK1

AG10

SB_CKE_1

Y2

SB_CKN2

AA2

SB_CK2

AG9

SB_CKE_2

Y1

SB_CKN3

AA1

SB_CK3

AF9

SB_CKE_3

P4

SB_CS_N_0

R2

SB_CS_N_1

P3

SB_CS_N_2

P1

SB_CS_N_3

R4

SB_ODT_0

R3

SB_ODT_1

R1

SB_ODT_2

P2

SB_ODT_3

R7

SB_BS_0

P8

SB_BS_1

AA9

SB_BS_2

R10

VSS2

R6

SB_RAS#

P6

SB_WE#

P7

SB_CAS#

R8
Y5
Y10
AA5
Y7
AA6
Y6
AA7
Y8
AA10
R9
Y9
AF7
P9
AA8
AG7

AP18
AP11
AP5
AJ3
L3
H9
C8
C14
AP17
AP12
AP6
AK3
M3
H8
C9
C15

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
SB_MA_15

SB_DQS_N_0
SB_DQS_N_1
SB_DQS_N_2
SB_DQS_N_3
SB_DQS_N_4
SB_DQS_N_5
SB_DQS_N_6
SB_DQS_N_7
SB_DQS_P_0
SB_DQS_P_1
SB_DQS_P_2
SB_DQS_P_3
SB_DQS_P_4
SB_DQS_P_5
SB_DQS_P_6
SB_DQS_P_7

SOCKET_947P

12V012BSM001

1%

M_B_DIM0_CLK_DDR#0 17
M_B_DIM0_CLK_DDR0 17
M_B_DIM0_CKE0 17
M_B_DIM0_CLK_DDR#1 17
M_B_DIM0_CLK_DDR1 17
M_B_DIM0_CKE1 17
M_B_DIM0_CLK_DDR#2 17
M_B_DIM0_CLK_DDR2 17
M_B_DIM0_CKE2 17
M_B_DIM0_CLK_DDR#3 17
M_B_DIM0_CLK_DDR3 17
M_B_DIM0_CKE3 17

M_B_DIM0_CS#0 17
M_B_DIM0_CS#1 17
M_B_DIM0_CS#2 17
M_B_DIM0_CS#3 17

M_B_DIM0_ODT0 17
M_B_DIM0_ODT1 17
M_B_DIM0_ODT2 17
M_B_DIM0_ODT3 17

M_B_BS0 17
M_B_BS1 17
M_B_BS2 17

M_B_RAS# 17

M_B_WE# 17

M_B_CAS# 17

M_B_A[15:0] 17

M_B_DQS#[7:0] 17

M_B_DQS[7:0] 17

Reserve S3 power reduction schematic

If don't support S3 power reduction

A A

5

1. Unmount R0450, R0452, U0404, R0453, Q0403, C0404, R0455, R0454, C0405

2. Change R0449 to 200ohm from 1kohm, change R0409 to 130ohm from 0ohm - Design Guide 1.0 page 106

3. Unmount Q0501, C0501, R0506, R0504, R0507

4. Mount R0501, change r0508 to 0ohm from 1kohm

5 Unmount Q0701, R0703, R0705, Q0702

6. Mount R0702 and short JP0701

7. Unmount R2232, R2231, Q2203

4

3

Title :

Title :

Title :

CPU(2)_DDR3

CPU(2)_DDR3

CPU(2)_DDR3

Wing_Cheng

Wing_Cheng

Engineer:

Engineer:

VA70_HW

VA70_HW

VA70_HW

Engineer:

1

PEGATRON COMPUTER INC

PEGATRON COMPUTER INC

PEGATRON COMPUTER INC

Size Project Name

Size Project Name

Size Project Name

C

C

C

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Wing_Cheng

5 96Friday, January 18, 2013

5 96Friday, January 18, 2013

5 96Friday, January 18, 2013

Rev

Rev

Rev

1.0

1.0

1.0

5

Decoupling guide from Intel (SPEC)

VDDQ 22uF * 11 pcs (stuff)
10uF * 10 pcs (stuff)
330uF * 2 pcs (stuff)

Decoupling guide from Intel ( SPEC)

+VCORE 10uF * 11pcs (stuff)
22uF * 19pcs (stuff)

D D

470uF * 4pcs (stuff)

PS_S3CNTRL_1.5V22

Default: no sup port
S3 power reduct ion

C C

+VCORE

12

12

C0654

C0647

22UF/6.3V

22UF/6.3V

vx_c0805_h57_small

12

C0630
22UF/6.3V

vx_c0805_h57_small

12

C0638
22UF/6.3V

vx_c0805_h57_small

vx_c0805_h57_small

12

C0641
22UF/6.3V

vx_c0805_h57_small

12

C0628
22UF/6.3V

vx_c0805_h57_small

B B

vx_c0805_h57_small

vx_c0805_h57_small

vx_c0805_h57_small

Decoupling guide from Intel (EE)

VDDQ 22uF * 2pcs (stuff)
10uF * 2pcs (stuff)
330uF * 1pcs (stuff)

Decoupling guide from Intel ( EE)

+VCORE 10uF * 11 pcs (stuff)
22uF * 19 pcs (stuff)
470uF * 5 pcs (stuff)

1 2

@

R0608 0Ohm

@

+1.35V

VR_SVID_DATA80

12

12

C0652
22UF/6.3V

vx_c0805_h57_small

12

C0640
22UF/6.3V

vx_c0805_h57_small

12

C0632
22UF/6.3V

vx_c0805_h57_small

C0650
22UF/6.3V

vx_c0805_h57_small

12

C0636
22UF/6.3V

vx_c0805_h57_small

12

C0629
22UF/6.3V

vx_c0805_h57_small

12

C0648
22UF/6.3V

vx_c0805_h57_small

12

C0634
22UF/6.3V

vx_c0805_h57_small

12

C0631
22UF/6.3V

vx_c0805_h57_small

12

C0623470PF/50V

12

C0653
22UF/6.3V

12

C0639
22UF/6.3V

12

C0635
22UF/6.3V

PS_S3CNTRL_1.5V_R

PS_S3CNTRL_1.5V_R

@

SIR472DP-T1-GE3

5 4

5
6
7
8

Q0601

4.2A

3MM_OPEN_5MIL

1MM_OPEN_M1M2

12

vx_c0805_h57_small

12

vx_c0805_h57_small

12

vx_c0805_h57_small

4

G

D

3

S

2
1

JP0601

2

112

JP0602

2

112

Placement note:

1. R0602 close to CPU

2. R0603 close to CPU

3. R0605 close to VR

4. R0608 close to CPU

5. R0607 close to VR

6. R0611 close to CPU

+VCCIO_OUT +VCCIO_OUT

R0610
130Ohm

1%

R1.2 2012/11/08

1 2

cost dwon 0ohm

SP0602 R0 402

12

C0649

C0651

22UF/6.3V

22UF/6.3V

vx_c0805_h57_small

vx_c0805_h57_small

12

C0637

C0607

22UF/6.3V

22UF/6.3V

vx_c0805_h57_small

vx_c0805_h57_small

12

C0609

C0633

22UF/6.3V

22UF/6.3V

vx_c0805_h57_small

vx_c0805_h57_small

12

+

1 2

12

C0645
22UF/6.3V

vx_c0805_h57_small

12

C0627
22UF/6.3V

vx_c0805_h57_small

12

C0610
22UF/6.3V

CE0602
560UF/2.5V

@

12

C0644
22UF/6.3V

12

C0608
22UF/6.3V

3

12

12

+

C0604

CE0601

22UF/6.3V

560UF/2.5V

vx_c0805_h57_small

vx_c0805_h57_small

12

@

C0603
10UF/10V

vx_c0805_h57_small

vx_c0805_h57_small

R0609
130Ohm

1%

1 2

VR_SVID_CLK80

Power team sugg estion

12

C0616
22UF/6.3V

vx_c0805_h57_small

12

12

C0605
22UF/6.3V

vx_c0805_h57_small

12

@

C0622
10UF/10V

vx_c0805_h57_small

If XDP not implemented, then Route Processor PWR_DEBUG as a test point.
This Test point must be clearly labeled(shark bay schematic check list 497750)

12

@

C0614
22UF/6.3V

vx_c0805_h57_small

vx_c0805_h57_small

12

12

@

C0642
10UF/10V

vx_c0805_h57_small

Unstuff R0622

Intel MOW WW09: renamed
VCCIO2PCH to RSVD

+VCCIO_OUT

R0613

54.9Ohm

R1.2 2012/11/08

1%

cost dwon 0ohm

1 2

VR_SVID_ALERT#80

1 2

SP0603 R0 402

12

12

@

@

C0625

C0626

22UF/6.3V

22UF/6.3V

vx_c0805_h57_small

12

@

@

C0643

C0646

10UF/10V

10UF/10V

vx_c0805_h57_small

vx_c0805_h57_small

R1.2 2012/11/16
follow Intel CRB
Place as close to CPU as possible
R1.2 2012/11/26
follow design guide

+VCCIO_OUT

12

@

@

C0606

C0618

22UF/6.3V

22UF/6.3V

vx_c0805_h57_small

vx_c0805_h57_small

12

12

@

@

C0615

C0613

10UF/10V

10UF/10V

vx_c0805_h57_small

vx_c0805_h57_small

+VCCIO_OUT(1---1.05V) output from CPU

+VCCIOA_OUT

+VCCIO2PCH

R0611
75Ohm

+VCCIO_OUT

R0603 0Ohm
R0604 0Ohm@
R0605 0Ohm

12

C0657

22UF/6.3V

@

1%

R1.1

12

12

12

@

C0619
22UF/6.3V

vx_c0805_h57_small

vx_c0805_h57_small

12

12

@

C0601
10UF/10V

vx_c0805_h57_small

VCCSENSE80

1 2
1 2
1 2

C0655

12

4.7UF/6.3V
C0611

0.01UF/50V

@

12

@

@

C0620

C0621

22UF/6.3V

22UF/6.3V

vx_c0805_h57_small

12

@

@

C0602

C0617

10UF/10V

10UF/10V

vx_c0805_h57_small

R0601

100Ohm

1%

SP0601 R0 402

+VCCIO_OUT_R
+VCCIO2PCH_R
+VCCIOA_OUT_R

12

12

R0612 43Ohm

T0606

T0602
T0603
T0605
T0604

12

@

C0624
22UF/6.3V

+VCORE

+VCORE

R1.2 2012/11/08
cost dwon 0ohm

1 2

1 2

C0612

0.01UF/50V

1

1
1
1
1

+1.35V_VCCDDQ

VCC_SENSE_R

T0601

H_CPU_SVIDALRT#

H_CPU_SVIDCLK
H_CPU_SVIDDAT

PWR_DEBUG

+VCORE

+1.35V_VCCDDQ

+1.35V

+VCORE

+VCCIO_OUT

+VCCIO2PCH

+VCCIOA_OUT

U0301E

K27

RSVD23

L27

RSVD22

T27

RSVD21

V27

RSVD20

AB11

VDDQ13

AB2

VDDQ12

AB5

VDDQ11

AB8

VDDQ10

AE11

VDDQ9

AE2

VDDQ8

AE5

VDDQ7

AE8

VDDQ6

AH11

VDDQ14

K11

VDDQ15

N11

VDDQ5

N8

VDDQ16

T11

VDDQ4

T2

VDDQ17

T5

VDDQ3

T8

VDDQ18

W11

VDDQ2

W2

VDDQ19

W5

VDDQ1

W8

VDDQ20

N26

RSVD19

K26

VCC103

AL27

RSVD18

AK27

RSVD24

AL35

VCC_SENSE

E17

RSVD27

AN35

VCCIO_OUT

A23

RSVD25

F22

VCOMP_OUT

W32

RSVD30

AL16

RSVD29

J27

1

RSVD26

AL13

RSVD28

AM28

VIDALERT#

AM29

VIDSCLK

AL28

VIDSOUT

AP35

VSS3

H27

PWR_DEBUG

AP34

VSS4

AT35

RSVD_TP4

AR35

RSVD_TP3

AR32

RSVD_TP2

AL26

RSVD_TP1

AT34

VSS5

AL22

VSS6

AT33

VSS7

AM21

VSS8

AM25

VSS9

AM22

VSS10

AM20

VSS11

AM24

VSS12

AL19

VSS13

AM23

VSS14

AT32

VSS15

Y25

VCC11

Y26

VCC10

Y27

VCC9

Y28

VCC8

Y29

VCC7

Y30

VCC6

Y31

VCC5

Y32

VCC4

Y33

VCC3

Y34

VCC2

Y35

VCC1

SOCKET_947P

12V012BSM001

2

+1.35V_VCCDDQ 4

+1.35V 5,16,18,63,83

+VCORE 9,63,80

+VCCIO_OUT 4,37,47,63

+VCCIO2PCH 27

+VCCIOA_OUT 3,4

Haswell rPGA EDS

VCC100

VCC99
VCC98
VCC97
VCC96
VCC95
VCC94
VCC93
VCC92
VCC91
VCC90
VCC89
VCC88
VCC87
VCC86
VCC85
VCC84
VCC83
VCC82
VCC81
VCC80
VCC79
VCC78
VCC77
VCC76
VCC75
VCC74
VCC73
VCC72
VCC71
VCC70
VCC69
VCC68
VCC67
VCC66
VCC65
VCC64
VCC63
VCC62
VCC61
VCC60
VCC59
VCC58
VCC57
VCC56
VCC55
VCC54
VCC53
VCC52
VCC51
VCC50
VCC49

VCC48
VCC102
VCC101

VCC47

VCC46

VCC45

VCC44

VCC43

VCC42

VCC41

VCC40

VCC39

VCC38

VCC37

VCC36

VCC35

VCC34

VCC33

VCC32

VCC31

VCC30

VCC29

VCC28

VCC27

VCC26

VCC25

VCC24

VCC23

VCC22

VCC21

VCC20

VCC19

VCC18

VCC17

VCC16

VCC15

VCC14

VCC13

VCC12

AA26
AA28
AA34
AA30
AA32
AB26
AB29
AB25
AB27
AB28
AB30
AB31
AB33
AB34
AB32
AC26
AB35
AC28
AD25
AC30
AD28
AC32
AD31
AC34
AD34
AD26
AD27
AD29
AD30
AD32
AD33
AD35
AE26
AE32
AE28
AE30
AG28
AG34
AE34
AF25
AF26
AF27
AF28
AF29
AF30
AF31
AF32
AF33
AF34
AF35
AG26
AH26
AH29
AG30
AG32
AH32
AH35
AH25
AH27
AH28
AH30
AH31
AH33
AH34
AJ25
AJ26
AJ27
AJ28
AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35
G25
H25
J25
K25
L25
M25
N25
P25
R25
T25

U25
U26
V25
V26

W26
W27

+VCORE

1

Cap of 470UF or more place at power schematic

A A

Title :

Title :

Title :

CPU(4)_PWR

CPU(4)_PWR

CPU(4)_PWR

Wing_Cheng

Wing_Cheng

Wing_Cheng

Engineer:

Engineer:

VA70_HW

VA70_HW

VA70_HW

Engineer:

Rev

Rev

Rev

1.0

1.0

1.0

6 96Friday, January 18, 2013

6 96Friday, January 18, 2013

6 96Friday, January 18, 2013

1

PEGATRON COMPUTER INC

PEGATRON COMPUTER INC

PEGATRON COMPUTER INC

Size Project Nam e

Size Project Nam e

Size Project Nam e

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

5

4

3

2

5

D D

C C

4

3

2

1

B B

A A

Title :

Title :

Title :

CPU(4)_PWR

CPU(4)_PWR

CPU(4)_PWR

Wing_Cheng

Wing_Cheng

Engineer:

Engineer:

VA70_HW

VA70_HW

VA70_HW

Engineer:

1

PEGATRON COMPUTER INC

PEGATRON COMPUTER INC

PEGATRON COMPUTER INC

Size Project Name

Size Project Name

Size Project Name

C

C

C

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Wing_Cheng

7 96Friday, January 18, 2013

7 96Friday, January 18, 2013

7 96Friday, January 18, 2013

Rev

Rev

Rev

1.0

1.0

1.0

5

Haswell rPGA EDS

U0301F

A10

VSS16

A13

VSS127

A16

VSS238

A19

VSS268

A22

VSS279

A25

VSS290

A27

VSS301

A29

D D

C C

B B

A A

A31
A33

AA11
AA25
AA27
AA31
AA29

AB1
AB10
AA33
AA35

AB3
AC25
AC27

AB4

AB6

AB7

AB9
AC11
AD11
AC29
AC31
AC33
AC35

AD7

AE1
AE10
AE25
AE29

AE3
AE27
AE35

AE4

AE6

AE7

AE9
AF11

AF6

AF8
AG11
AG25
AE31
AG31
AE33

AG6
AH1

AH10

AH2
AG27
AG29

AH3
AG33
AG35

AH4

AH5

AH6

AH7

AH8

AH9

AJ11

AJ5
AK11
AK25
AK26
AK28
AK29
AK30
AK32

E19

A3

A4
A7

VSS312
VSS323
VSS17
VSS28
VSS39
VSS50
VSS61
VSS72
VSS83
VSS94
VSS105
VSS116
VSS128
VSS139
VSS150
VSS161
VSS172
VSS183
VSS194
VSS205
VSS216
VSS227
VSS239
VSS250
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS291
VSS292
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS313

SOCKET_947P

12V012BSM001

5

VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333

VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82

AK34
AK5
AL1
AL10
AL11
AL12
AL14
AL15
AL17
AL18
AL2
AL20
AL21
AL23
E22
AL3
AL4
AL5
AL6
AL7
AL8
AL9
AM10
AM13
AM16
AM19
E25
AM32
AM4
AM7
AN10
AN13
AN16
AN19
AN2
AN21
AN24
AN27
AN30
AN34
AN4
AN7
AP1
AP10
AP13
AP16
AP19
AP4
AP7
W25
AR10
AR13
AR16
AR19
AR2
AR22
AR25
AR28
AR31
AR34
AR4
AR7
AT10
AT13
AT16
AT19
AT21
AT24
AT27
AT3
AT30
AT4
AT7
B10
B13
B16
B19
B2
B22

4

B34

B4
B7

C1
C10
C13
C16
C19

C2
C22
C24
C26
C28
C30
C32
C34

C4

C7
D10
D13
D16
D19
D22
D25
D27
D29
D31
D33
D35

D4

D7

E1

E10
E13
E16

E4

E7

F10
F11
F12
F14
F15
F17
F18
F20
F21
F23
F24
F26
F28
F30
F32
F34

F4
F6
F7
F8
F9

G1
G11

G2
G27
G29

G3
G31
G33
G35

G4

G5
H10
H26

H6

H7

J11
J26
J28

J30
J32
J34

J6
K1

SOCKET_947P

12V012BSM001

4

U0301G

VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS173

3

Haswell rPGA EDS

3

VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257

VSS_SENSE

RSVD31

K10
K2
K29
K3
K31
K33
K35
K4
K5
K7
K8
K9
L11
L26
L6
M11
M26
M28
M30
M32
M34
M6
N1
N10
N2
N29
N3
N31
N33
N35
N4
N5
N6
N7
N9
P11
P26
P5
R11
R26
R28
R30
R32
R34
R5
T1
T10
T29
T3
T31
T33
T35
T4
T6
T7
T9
U11
U27
V11
V28
V30
V32
V34
W1
W10
W3
W35
W4
W6
W7
W9
Y11
H11
AL24
F19
T26
AK35
AK33

2

Placement note:

1. SP0801 close to CPU

SP0801 R0 402

VSS_SENSE_R

T0801

1

2

R1.2 2012/11/08
cost dwon 0ohm

1 2

1 2

PEGATRON COMPUTER INC

PEGATRON COMPUTER INC

PEGATRON COMPUTER INC

Size Projec t Name

Size Projec t Name

Size Projec t Name

B

B

B

Date: Sheet of

Date: Sheet of

Date: Sheet of

R0802
100Ohm

1%

VSSSENSE 80

VA70_HW

VA70_HW

VA70_HW

Engineer:

Engineer:

Engineer:

Title :

Title :

Title :

1

CPU(3)_CFG,RSVD,GND

CPU(3)_CFG,RSVD,GND

CPU(3)_CFG,RSVD,GND

Wing_Cheng

Wing_Cheng

Wing_Cheng

8 96Friday, January 18, 2013

8 96Friday, January 18, 2013

8 96Friday, January 18, 2013

1

Rev

Rev

Rev

1.0

1.0

1.0

5

4

3

2

1

CFG strapping information:

CFG[1:0]: Reserved configuration lane.

D D

C C

B B

CFG[2]: PCIE Static Numbering Lane Reversal- CFG[2] is for the 16x

- 1: (Default) Normal Operation, Lane # definition matches sockect pin map definition

- 0: Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

CFG[4]: eDP enable

-1 = Disabled

-0 = Enabled

CFG[6:5]: PCI Express Port Bifurcation Straps

-00 = 1 x8, 2 x4 PCI Express*

-01 = reserved

-10 = 2 x8 PCI Express*

-11 = 1 x16 PCI Express*

CFG[19:7]: Reserved configuration lane.

CFG2

R0903 1KOhm

CFG4

R0905 1KOhm

CFG5

R0904 1KOhm@

CFG6

R0906 1KOhm@

CFG7

R0907 1KOhm@

CFG9

R0909 1KOhm

The CFG signals have a default value of '1'

1 2

1%

1 2

1%

1 2

1%

1 2

1%

1 2

1%

1 2

1%

@

R0901 49.9Ohm1%

R0902 49.9Ohm1%

+VCORE

U0301I

AT1

RSVD_TP17

AT2

RSVD_TP16

AD10

RSVD2

A34

RSVD_TP15

A35

RSVD_TP14

W29

RSVD_TP18

W28

RSVD_TP19

12

H_CPU_RSVDG26

12

H_CPU_RSVDW34

T0905
T0906
T0907
T0908
T0910
T0911
T0912
T0914
T0913
T0915
T0917
T0916
T0918
T0919
T0920
T0921

G26

TESTLO1

W33

RSVD3

AL30

RSVD4

AL29

RSVD5

F25

VCC104

C35

RSVD_TP13

B35

RSVD_TP12

AL25

RSVD_TP20

W30

RSVD_TP21

W31

RSVD_TP22

W34

AT20
AR20
AP20
AP22
AT22
AN22
AT25
AN23
AR24
AT23
AN20
AP24
AP26
AN25
AN26
AP25

TESTLO2

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15

SOCKET_947P

12V012BSM001

1

CFG0

1

CFG1

1

CFG2

1

CFG3

1

CFG4

1

CFG5

1

CFG6

1

CFG7

1

CFG8

1

CFG9

1

CFG10

1

CFG11

1

CFG12

1

CFG13

1

CFG14

1

CFG15

+VCORE

Haswell rPGA EDS

RSVD_TP11
RSVD_TP10

RSVD_TP9
RSVD_TP8

CFG_RCOMP

CFG_16
CFG_18
CFG_17
CFG_19

RSVD6

RSVD7
RSVD8

RSVD9
RSVD10
RSVD11

RSVD12

RSVD13
RSVD14

RSVD15

RSVD_TP7

RSVD_TP6
RSVD_TP5

RSVD16
RSVD17

VSS258
VSS259

+VCORE 6,63,80

C23
B23
D24
D23

AT31
AR21
AR23
AP21
AP23

AR33
G6

FC2

AM27
AM26
F5
AM2
K6

E18

U10
P10

B1

NC

A2
AR1

E21
E20

AP27
AR26

AL31
AL32

R1.2 2012/11/26
reserved for 2014 processor

PM_PWROK 22,30,92

12

R0910

4.7KOhm

@
1%

R1.2 2012/11/28
channged from 2.2k/5%

12

R0911

2.2KOhm

1%
@

T0922
T0923
T0925
T0924

1 2

R090849.9Ohm 1%

CFG_RCOMP

1

CFG16

1

CFG17

1

CFG18

1

CFG19

FC_G6

FC signals are signals that are available for compatibility with other processors. A test point
may be placed on the board for these lands. Refer to the appropriate platform design guide
for implementation details.(haswell EDS 487246)

A A

Title :

Title :

Title :

CPU(3)_CFG,RSVD,GND

CPU(3)_CFG,RSVD,GND

CPU(3)_CFG,RSVD,GND

Wing_Cheng

Wing_Cheng

1

Wing_Cheng

9 96Friday, January 18, 2013

9 96Friday, January 18, 2013

9 96Friday, January 18, 2013

Rev

Rev

Rev

1.0

1.0

1.0

Engineer:

Engineer:

VA70_HW

VA70_HW

VA70_HW

Engineer:

PEGATRON COMPUTER INC

PEGATRON COMPUTER INC

PEGATRON COMPUTER INC

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

5

D D

C C

4

3

2

1

B B

A A

Title :

Title :

Title :

NB(3)_****

NB(3)_****

NB(3)_****

Wing_Cheng

Wing_Cheng

Engineer:

Engineer:

VA70_HW

VA70_HW

VA70_HW

Engineer:

1

PEGATRON COMPUTER INC

PEGATRON COMPUTER INC

PEGATRON COMPUTER INC

Size Project Name

Size Project Name

Size Project Name

C

C

C

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Wing_Cheng

10 96Friday , January 18, 2013

10 96Friday , January 18, 2013

10 96Friday , January 18, 2013

Rev

Rev

Rev

1.0

1.0

1.0

5

R1.2 2012/11/20

1 2
3 4

M_A_WE #
M_A_RAS #
M_A_CAS #

M_A_BS2
M_A_BS1
M_A_BS0

1 2
3 4

10KOhm
10KOhm

10KOhm
10KOhm

/DGPU
/DGPU

Part ref. changed

98

M_A_A0

97

M_A_A1

96

M_A_A2

95

M_A_A3

92

M_A_A4

91

M_A_A5

90

M_A_A6

86

M_A_A7

89

M_A_A8

85

M_A_A9

107

M_A_A10

84

M_A_A11

83

M_A_A12

119

M_A_A13

80

M_A_A14

78

M_A_A15

102
104
101
103

121
114

120
116

113
110
115

79
108
109

74

73

201

RN1601A

197

RN1601B

188

M_A_DQS 7

186

M_A_DQS #7

171

M_A_DQS 6M_A_DQS 2

169

M_A_DQS #6

154

M_A_DQS 5

152

M_A_DQS #5

137

M_A_DQS 4

135

M_A_DQS #4

64

M_A_DQS 3

62

M_A_DQS #3

47

M_A_DQS 2

45

M_A_DQS #2

29

M_A_DQS 1

27

M_A_DQS #1

12

M_A_DQS 0

10

M_A_DQS #0

187
170
153
136

63

46

28

11

202
200

R1.2 2012/11/20
Part ref. changed

98

M_A_A0

97

M_A_A1

96

M_A_A2

95

M_A_A3

92

M_A_A4

91

M_A_A5

90

M_A_A6

86

M_A_A7

89

M_A_A8

85

M_A_A9

107

M_A_A10

84

M_A_A11

83

M_A_A12

119

M_A_A13

80

M_A_A14

78

M_A_A15

102
104
101
103

121
114

120
116

113
110
115

79
108
109

74

73

201

RN1602A

197

RN1602B

188

M_A_DQS 7

186

M_A_DQS #7

171

M_A_DQS 6

169

M_A_DQS #6

154

M_A_DQS 5

152

M_A_DQS #5

137

M_A_DQS 4

135

M_A_DQS #4

64

M_A_DQS 3

62

M_A_DQS #3

47

M_A_DQS 2

45

M_A_DQS #2

29

M_A_DQS 1

27

M_A_DQS #1

12

M_A_DQS 0

10

M_A_DQS #0

187
170
153
136

63

46

28

11

202
200

H:4mm

CON1601 A

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15

CK1
CK1#
CK0
CK0#

S1#
S0#

ODT1
ODT0

WE#
RAS#
CAS#

BA2
BA1
BA0

CKE1
CKE0

SA1
SA0

DQS7
DQS#7
DQS6
DQS#6
DQS5
DQS#5
DQS4
DQS#4
DQS3
DQS#3
DQS2
DQS#2
DQS1
DQS#1
DQS0
DQS#0

DM7
DM6
DM5
DM4
DM3
DM2
DM1
DM0

SCL
SDA

DDR3_D IMM_204P

12V02G IRM001

H:8mm

CON1602 A

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15

CK1
CK1#
CK0
CK0#

S1#
S0#

ODT1
ODT0

WE#
RAS#
CAS#

BA2
BA1
BA0

CKE1
CKE0

SA1
SA0

DQS7
DQS#7
DQS6
DQS#6
DQS5
DQS#5

DDR3_D IMM_204P

DQS4

12V02G BRM001

DQS#4
DQS3
DQS#3
DQS2
DQS#2
DQS1
DQS#1
DQS0
DQS#0

DM7
DM6
DM5
DM4
DM3
DM2
DM1
DM0

SCL
SDA

/DGPU

5

M_A_DQ0

DQ0

7

M_A_DQ4

DQ1

15

M_A_DQ3

DQ2

17

M_A_DQ2

DQ3

4

M_A_DQ7

0

DQ4

6

M_A_DQ6

DQ5

16

M_A_DQ1

DQ6

18

M_A_DQ5

DQ7

21

M_A_DQ1 1

DQ8

23

M_A_DQ9

DQ9

33

M_A_DQ1 5

DQ10

35

M_A_DQ1 4

DQ11

22

M_A_DQ1 0

DQ12

24

M_A_DQ8

1

DQ13

34

M_A_DQ1 2

DQ14

36

M_A_DQ1 3

DQ15

39

M_A_DQ2 0

DQ16

41

M_A_DQ1 7

DQ17

51

M_A_DQ1 8

DQ18

53

M_A_DQ2 3

DQ19

40

M_A_DQ1 6

2

DQ20

42

M_A_DQ2 1

DQ21

50

M_A_DQ1 9

DQ22

52

M_A_DQ2 2

DQ23

57

M_A_DQ2 4

DQ24

59

M_A_DQ2 8

DQ25

67

M_A_DQ2 7

DQ26

69

M_A_DQ3 1

DQ27

56

M_A_DQ2 5

3

DQ28

58

M_A_DQ2 9

DQ29

68

M_A_DQ3 0

DQ30

70

M_A_DQ2 6

DQ31

129

M_A_DQ3 7

DQ32

131

M_A_DQ3 2

DQ33

141

M_A_DQ3 5

DQ34

143

M_A_DQ3 4

DQ35

130

M_A_DQ3 8

DQ36

132

M_A_DQ3 3

DQ37

140

M_A_DQ3 6

4

DQ38

142

M_A_DQ3 9

DQ39

147

M_A_DQ4 4

DQ40

149

M_A_DQ4 2

DQ41

157

M_A_DQ4 7

DQ42

159

M_A_DQ4 5

DQ43

146

M_A_DQ4 0

DQ44

148

M_A_DQ4 1

DQ45

158

M_A_DQ4 3

5

DQ46

160

M_A_DQ4 6

DQ47

163

M_A_DQ5 2

DQ48

165

M_A_DQ5 3

DQ49

175

M_A_DQ5 5

DQ50

177

M_A_DQ5 4

DQ51

164

M_A_DQ5 1

DQ52

166

M_A_DQ4 9

DQ53

174

M_A_DQ4 8

6

DQ54

176

M_A_DQ5 0

DQ55

181

M_A_DQ5 8

DQ56

183

M_A_DQ6 1

DQ57

191

M_A_DQ6 3

DQ58

193

M_A_DQ5 7

DQ59

180

M_A_DQ6 0

DQ60

182

M_A_DQ5 6

DQ61

192

M_A_DQ6 2

7

DQ62

194

M_A_DQ5 9

DQ63

30

RESET#

5

M_A_DQ0

DQ0

7

M_A_DQ4

DQ1

15

M_A_DQ3

DQ2

17

M_A_DQ2

DQ3

4

M_A_DQ7

DQ4

6

M_A_DQ6

DQ5

16

M_A_DQ1

DQ6

18

M_A_DQ5

0

DQ7

21

M_A_DQ1 1

DQ8

23

M_A_DQ9

DQ9

33

M_A_DQ1 5

DQ10

35

M_A_DQ1 4

DQ11

22

M_A_DQ1 0

DQ12

24

M_A_DQ8

DQ13

34

M_A_DQ1 2

DQ14

36

M_A_DQ1 3

1

DQ15

39

M_A_DQ2 0

DQ16

41

M_A_DQ1 7

DQ17

51

M_A_DQ1 8

DQ18

53

M_A_DQ2 3

DQ19

40

M_A_DQ1 6

DQ20

42

M_A_DQ2 1

DQ21

50

M_A_DQ1 9

DQ22

52

M_A_DQ2 2

2

DQ23

57

M_A_DQ2 4

DQ24

59

M_A_DQ2 8

DQ25

67

M_A_DQ2 7

DQ26

69

M_A_DQ3 1

DQ27

56

M_A_DQ2 5

DQ28

58

M_A_DQ2 9

DQ29

68

M_A_DQ3 0

DQ30

70

M_A_DQ2 6

3

DQ31

129

M_A_DQ3 7

DQ32

131

M_A_DQ3 2

DQ33

141

M_A_DQ3 5

DQ34

143

M_A_DQ3 4

DQ35

130

M_A_DQ3 8

DQ36

132

M_A_DQ3 3

DQ37

140

M_A_DQ3 6

DQ38

142

M_A_DQ3 9

4

DQ39

147

M_A_DQ4 4

DQ40

149

M_A_DQ4 2

DQ41

157

M_A_DQ4 7

DQ42

159

M_A_DQ4 5

DQ43

146

M_A_DQ4 0

DQ44

148

M_A_DQ4 1

DQ45

158

M_A_DQ4 3

DQ46

160

M_A_DQ4 6

5

DQ47

163

M_A_DQ5 2

DQ48

165

M_A_DQ5 3

DQ49

175

M_A_DQ5 5

DQ50

177

M_A_DQ5 4

DQ51

164

M_A_DQ5 1

DQ52

166

M_A_DQ4 9

DQ53

174

M_A_DQ4 8

DQ54

176

M_A_DQ5 0

6

DQ55

181

M_A_DQ5 8

DQ56

183

M_A_DQ6 1

DQ57

191

M_A_DQ6 3

DQ58

193

M_A_DQ5 7

DQ59

180

M_A_DQ6 0

DQ60

182

M_A_DQ5 6

DQ61

192

M_A_DQ6 2

DQ62

194

M_A_DQ5 9

7

DQ63

30

DDR3_D RAMRST#SMB_CLK _S

RESET#

R1601

150Ohm

150Ohm

D D

C C

B B

A A

C1621

10PF/50 V

@

M_A_DIM0 _CLK_D DR#0

@

M_A_DIM0 _CLK_D DR1

12

12

R1602

C1622

10PF/50 V

@

M_A_DIM0 _CLK_D DR#1

@

150Ohm

150Ohm

M_A_DQS [7:0]5

M_A_DQS #[7:0]5

12

R1604

@

12

R1603

@

M_A_DIM0 _CLK_D DR2

12

C1624

10PF/50 V

M_A_DIM0 _CLK_D DR#2

@

M_A_DIM0 _CLK_D DR3

12

C1623

10PF/50 V

M_A_DIM0 _CLK_D DR#3

@

SMBus Slave Address: A2H

M_A_DQS 0
M_A_DQS 1

M_A_DQS 3
M_A_DQS 4
M_A_DQS 5
M_A_DQS 6
M_A_DQS 7
M_A_DQS #0
M_A_DQS #1
M_A_DQS #2
M_A_DQS #3
M_A_DQS #4
M_A_DQS #5
M_A_DQS #6
M_A_DQS #7

M_A_DIM0 _CLK_D DR15

M_A_DIM0 _CLK_D DR#15

M_A_DIM0 _CLK_D DR05

M_A_DIM0 _CLK_D DR#05

M_A_DIM0 _CS#15
M_A_DIM0 _CS#05

M_A_DIM0 _ODT15
M_A_DIM0 _ODT05

M_A_DIM0 _CKE15
M_A_DIM0 _CKE05

SMBus Slave Address: A0H

DM should connect to GND directly
Design Guide 0.9 p86 (436735)

SMB_CLK _S1 7,28,48,5 3,55
SMB_DAT _S17 ,28,48,53 ,55

M_A_DIM0 _CLK_D DR35

M_A_DIM0 _CLK_D DR#35

M_A_DIM0 _CLK_D DR25

M_A_DIM0 _CLK_D DR#25

M_A_DIM0 _CS#35
M_A_DIM0 _CS#25

M_A_DIM0 _ODT35
M_A_DIM0 _ODT25

M_A_DIM0 _CKE35
M_A_DIM0 _CKE25

DM should connect to GND directly
Design Guide 0.9 p86 (436735)

M_A_A[15 :0]5

M_A_WE #5
M_A_RAS #5
M_A_CAS #5

M_A_BS25
M_A_BS15
M_A_BS05

SMB_DAT _S

+3VS

M_A_DIM0 _CLK_D DR0

12

12

ok

ok

ok

ok

ok

ok

ok

ok

4

M_A_DQ[6 3:0] 5

DDR3_D RAMRST# 5,17

JP1601

112

3MM_OPEN_5 MIL

JP1602

2

112

2MM_OPEN_5 MIL

+1.35V_D DR3

12

C1601

0.1UF/10V

Layout Note: Place th ese caps near SO DIM M 0

1

PM_EXTT S#0_DI M_A

T1601

Reserve

+V_VREF _CA_D IMM0

12

C1609

2.2UF/6.3V

@

+V_VREF _DQ_D IMM0

12

C1607

2.2UF/6.3V

@

+1.35V_D DR3

12

12

C1616

C1612

0.1UF/10V

0.1UF/10V

/DGPU

T1602

Reserve

+V_VREF _CA_D IMM0

+V_VREF _DQ_D IMM0

1

PM_EXTT S#0_DI M_A

12

C1619

2.2UF/6.3V

@

12

C1611

2.2UF/6.3V

@

/DGPU

12

C1618

0.1UF/10V

/DGPU

12

C1613

0.1UF/10V

/DGPU

Layout Note: Place th ese caps near SO DIM M 0

+1.35V_D DR3+1.35V

2

12

C1602

0.1UF/10V

12

C1608

0.1UF/10V

12

C1610

0.1UF/10V

R1.2 2012/11/20
Part ref. changed

75

99
105
111
117
123

13

19

25

31

37

43

48

54

60

65

71
127
133
138
144
150
155
161
167
172
178
184
189
195

198
125

77
122

126

+1.35V

+0.675VS

+3VS

+1.35V_D DR3

R1.2 2012/11/20
Part ref. changed

CON1601 B

75

VDD1
VDD381VDD4
VDD587VDD6
VDD793VDD8

99

VDD9

105

VDD11

111

VDD13

117

VDD15

123

VDD17

2

VSS1

8

VSS3

13

VSS5

19

VSS7

25

VSS9

31

VSS11

37

VSS13

43

VSS15

48

VSS17

54

VSS19

60

VSS21

65

VSS23

71

VSS25

127

VSS27

133

VSS29

138

VSS31

144

VSS33

150

VSS35

155

VSS37

161

VSS39

167

VSS41

172

VSS43

178

VSS45

184

VSS47

189

VSS49

195

VSS51

198

EVENT#

125

TEST

77

NC1

122

NC2

126

VREFCA

1

VREFDQ

CON1602 B

DDR3_D IMM_204P

12V02G IRM001

VDD1

VDD2
VDD381VDD4
VDD587VDD6
VDD793VDD8

VDD10

VDD9
VDD11

VDD12

VDD13

VDD14

VDD15

VDD16

VDD17

VDD18

2

VSS2

VSS1

8

VSS4

VSS3

VSS6

VSS5

VSS8

VSS7
VSS9

VSS10
VSS12

VSS11

VSS14

VSS13

VSS16

VSS15

VSS18

VSS17

VSS20

VSS19

VSS22

VSS21

VSS24

VSS23

VSS26

VSS25

VSS28

VSS27

VSS30

VSS29

VSS32

VSS31

VSS34

VSS33

VSS36

VSS35

VSS38

VSS37

VSS40

VSS39

VSS42

VSS41

VSS44

VSS43

VSS46

VSS45

VSS48

VSS47

VSS50

VSS49

VSS52

VSS51

GND1

EVENT#

GND2

TEST

NP_NC1

NC1

NP_NC2

NC2

VTT1
VTT2

VREFCA

1

VDDSPD

VREFDQ

DDR3_D IMM_204P

12V02G BRM001
/DGPU

3

+1.35V 5,6,18 ,63,83

+0.675VS 17 ,63,83

+3VS 17,20,21 ,22,23,25 ,26,27,2 8,30,33,3 7,38,39,4 0,41,43 ,47,48,49 ,53,55,6 0,63,65,6 6,91,92

+1.35V_D DR3 1 7

C1606

0.1UF/10V

12

/DGPU

+0.675VS

C1617

0.1UF/10V

12

+3VS

C1603

0.1UF/10V

/DGPU

12

C1615

2.2UF/6.3V

@

+3VS

12

+1.35V_D DR3

12

C1614

0.1UF/10V

12

C1605

2.2UF/6.3V

@

+1.35V_D DR3

C1604

0.1UF/10V

Reference schematic have 2.2 uf cap.

VDD10
VDD12
VDD14
VDD16
VDD18

VSS10
VSS12
VSS14
VSS16
VSS18
VSS20
VSS22
VSS24
VSS26
VSS28
VSS30
VSS32
VSS34
VSS36
VSS38
VSS40
VSS42
VSS44
VSS46
VSS48
VSS50
VSS52

NP_NC1
NP_NC2

VDDSPD

76

VDD2

82
88
94
100
106
112
118
124

3

VSS2

9

VSS4

14

VSS6

20

VSS8

26
32
38
44
49
55
61
66
72
128
134
139
145
151
156
162
168
173
179
185
190
196

207

GND1

208

GND2

205
206

203

VTT1

204

VTT2

199

12

76
82
88
94
100
106
112
118
124

3
9
14
20
26
32
38
44
49
55
61
66
72
128
134
139
145
151
156
162
168
173
179
185
190
196

207
208

205
206

203

+0.675VS

204

199

12

C1620

0.1UF/10V

/DGPU

+1.35V_D DR3

12

+

1BV090 000003

@

CE1603
220UF/6.3 V

2

+1.35V_D DR3

Layout Note: Place th ese caps near SO DIM M 0

12

12

C1626
10UF/10V

C1625
10UF/10V

12

C1628
10UF/10V

Layout Note: Place th ese caps near SO DIM M 0

12

12

C1636
10UF/10V

/DGPU

12

C1635

C1638

10UF/10V

10UF/10V

/DGPU

/DGPU

1

+0.675VS

12

C1633
10UF/10V

@

12

C1643
10UF/10V

@

C1627

C1631

10UF/10V

10UF/10V

@

@

12

12

C1637

C1641

10UF/10V

10UF/10V

@

@

12

12

12

12

C1632
1UF/6.3V

+0.675VS+1.35V_D DR3

12

12

C1639

C1642

1UF/6.3V

1UF/6.3V

/DGPU

/DGPU

C1629
1UF/6.3V

12

12

C1634

C1630

1UF/6.3V

1UF/6.3V

@

@

12

12

C1640

C1644

1UF/6.3V

1UF/6.3V

@

@

Title :

Title :

Title :

DDR3(1)_SO-DIMM0

DDR3(1)_SO-DIMM0

DDR3(1)_SO-DIMM0

Engineer:

Wing_Cheng

Engineer:

Wing_Cheng

Engineer:

BG1-CSC -HW R&D D ept.5

BG1-CSC -HW R&D D ept.5

BG1-CSC -HW R&D D ept.5

Size P roject Name

Size P roject Name

Size P roject Name

D

D

D

VA70_HW

VA70_HW

VA70_HW

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

1

Wing_Cheng

16 96Friday, January 18, 20 13

16 96Friday, January 18, 20 13

16 96Friday, January 18, 20 13

Rev

Rev

Rev

1.0

1.0

1.0

5

H:4MM

CON1701 A

98

M_B_A0

97

M_B_WE #5
M_B_RAS #5
M_B_CAS #5

M_B_BS25
M_B_BS15
M_B_BS05

M_B_WE #
M_B_RAS #
M_B_CAS #

M_B_BS2
M_B_BS1
M_B_BS0

1 2

10KOhm

3 4

10KOhm

1 2

10KOhm

3 4

10KOhm

/DGPU

M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

M_B_DQS 7
M_B_DQS #7
M_B_DQS 6
M_B_DQS #6
M_B_DQS 5
M_B_DQS #5
M_B_DQS 4
M_B_DQS #4
M_B_DQS 3
M_B_DQS #3
M_B_DQS 2
M_B_DQS #2
M_B_DQS 1
M_B_DQS #1
M_B_DQS 0
M_B_DQS #0

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

M_B_DQS 7
M_B_DQS #7
M_B_DQS 6
M_B_DQS #6
M_B_DQS 5
M_B_DQS #5
M_B_DQS 4
M_B_DQS #4
M_B_DQS 3
M_B_DQS #3
M_B_DQS 2
M_B_DQS #2
M_B_DQS 1
M_B_DQS #1
M_B_DQS 0
M_B_DQS #0

RN1701A
RN1701B

RN1702A
RN1702B

96
95
92
91
90
86
89
85

107

84
83

119

80
78

102
104
101
103

121
114

120
116

113
110
115

79
108
109

74

73

201
197

188
186
171
169
154
152
137
135

64

62

47

45

29

27

12

10

187
170
153
136

63

46

28

11

202
200

DDR3_D IMM_204P

12V02G ISM001

H:8MM

CON1702 A

98
97
96
95
92
91
90
86
89
85

107

84
83

119

80
78

102
104
101
103

121
114

120
116

113
110
115

79

108
109

74
73

201
197

188
186
171
169
154
152
137
135

64
62
47
45
29
27
12
10

187
170
153
136

63
46
28
11

202
200

DDR3_D IMM_204P

12V02G ISM000

/DGPU

1202-000R000

(12V02GIRM001)

M_B_DIM0 _CLK_D DR0

12

12

R1701

@

R1702

@

M_B_DQS [7:0]5

M_B_DQS #[7:0]5

R1703

150Ohm

R1704

150Ohm

C1737

@

12

12

C1738

@

12

12

@

@

12

12

@

@

SMBus Slave Address: A6H

10PF/50 V

M_B_DIM0 _CLK_D DR#0

M_B_DIM0 _CLK_D DR1

10PF/50 V

M_B_DIM0 _CLK_D DR#1

SMBus Slave Address: A4H

M_B_DQS 0
M_B_DQS 1
M_B_DQS 2
M_B_DQS 3
M_B_DQS 4
M_B_DQS 5
M_B_DQS 6
M_B_DQS 7
M_B_DQS #0
M_B_DQS #1
M_B_DQS #2
M_B_DQS #3
M_B_DQS #4
M_B_DQS #5
M_B_DQS #6
M_B_DQS #7

SMB_CLK _S1 6,28,48,5 3,55
SMB_DAT _S16 ,28,48,53 ,55

M_B_DIM0 _CLK_D DR2

C1739

10PF/50 V

M_B_DIM0 _CLK_D DR#2

M_B_DIM0 _CLK_D DR3

C1740

10PF/50 V

M_B_DIM0 _CLK_D DR#3

M_B_DIM0 _CLK_D DR15
M_B_DIM0 _CLK_D DR#15
M_B_DIM0 _CLK_D DR05
M_B_DIM0 _CLK_D DR#05

M_B_DIM0 _CS#15
M_B_DIM0 _CS#05

M_B_DIM0 _ODT15
M_B_DIM0 _ODT05

M_B_DIM0 _CKE15
M_B_DIM0 _CKE05

+3VS

DM should connect to GND directly
Design Guide 0.9 p86 (436735)

M_B_DIM0 _CLK_D DR35

M_B_DIM0 _CLK_D DR#35

M_B_DIM0 _CLK_D DR25

M_B_DIM0 _CLK_D DR#25

M_B_DIM0 _CS#35
M_B_DIM0 _CS#25

M_B_DIM0 _ODT35
M_B_DIM0 _ODT25

M_B_DIM0 _CKE35
M_B_DIM0 _CKE25

+3VS

DM should connect to GND directly
Design Guide 0.9 p86 (436735)

SMB_CLK _S
SMB_DAT _S

5

150Ohm

D D

150Ohm

C C

B B

A A

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15

CK1
CK1#
CK0
CK0#

S1#
S0#

ODT1
ODT0

WE#
RAS#
CAS#

BA2
BA1
BA0

CKE1
CKE0

SA1
SA0

DQS7
DQS#7
DQS6
DQS#6
DQS5
DQS#5
DQS4
DQS#4
DQS3
DQS#3
DQS2
DQS#2
DQS1
DQS#1
DQS0
DQS#0

DM7
DM6
DM5
DM4
DM3
DM2
DM1
DM0

SCL
SDA

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15

CK1
CK1#
CK0
CK0#

S1#
S0#

ODT1
ODT0

WE#
RAS#
CAS#

BA2
BA1
BA0

CKE1
CKE0

SA1
SA0

DQS7
DQS#7
DQS6
DQS#6
DQS5
DQS#5
DQS4
DQS#4
DQS3
DQS#3
DQS2
DQS#2
DQS1
DQS#1
DQS0
DQS#0

DM7
DM6
DM5
DM4
DM3
DM2
DM1
DM0

SCL
SDA

5

M_B_DQ1

DQ0

7

M_B_DQ5

DQ1

15

M_B_DQ4

DQ2

17

M_B_DQ7

DQ3

4

M_B_DQ3

DQ4

6

M_B_DQ0

DQ5

16

M_B_DQ2

0

DQ6

18

M_B_DQ6

DQ7

21

M_B_DQ1 4

DQ8

23

M_B_DQ1 0

DQ9

33

M_B_DQ1 5

DQ10

35

M_B_DQ1 2

DQ11

22

M_B_DQ9

DQ12

24

M_B_DQ8

DQ13

34

M_B_DQ1 1

1

DQ14

36

M_B_DQ1 3

DQ15

39

M_B_DQ1 6

DQ16

41

M_B_DQ1 7

DQ17

51

M_B_DQ2 2

DQ18

53

M_B_DQ1 9

DQ19

40

M_B_DQ2 1

DQ20

42

M_B_DQ2 0

DQ21

50

M_B_DQ1 8

2

DQ22

52

M_B_DQ2 3

DQ23

57

M_B_DQ2 7

DQ24

59

M_B_DQ2 5

DQ25

67

M_B_DQ3 1

DQ26

69

M_B_DQ2 8

DQ27

56

M_B_DQ2 6

DQ28

58

M_B_DQ2 4

DQ29

68

M_B_DQ2 9

3

DQ30

70

M_B_DQ3 0

DQ31

129

M_B_DQ3 3

DQ32

131

M_B_DQ3 2

DQ33

141

M_B_DQ3 8

DQ34

143

M_B_DQ3 4

DQ35

130

M_B_DQ3 6

DQ36

132

M_B_DQ3 7

DQ37

140

M_B_DQ3 5

4

DQ38

142

M_B_DQ3 9

DQ39

147

M_B_DQ4 1

DQ40

149

M_B_DQ4 0

DQ41

157

M_B_DQ4 7

DQ42

159

M_B_DQ4 6

DQ43

146

M_B_DQ4 5

DQ44

148

M_B_DQ4 4

5

DQ45

158

M_B_DQ4 2

DQ46

160

M_B_DQ4 3

DQ47

163

M_B_DQ5 3

DQ48

165

M_B_DQ5 2

DQ49

175

M_B_DQ5 0

DQ50

177

M_B_DQ4 9

DQ51

164

M_B_DQ4 8

DQ52

166

M_B_DQ5 4

DQ53

174

M_B_DQ5 1

6

DQ54

176

M_B_DQ5 5

DQ55

181

M_B_DQ5 9

DQ56

183

M_B_DQ6 3

DQ57

191

M_B_DQ6 1

DQ58

193

M_B_DQ6 0

DQ59

180

M_B_DQ5 8

DQ60

182

M_B_DQ5 7

DQ61

192

M_B_DQ6 2

7

DQ62

194

M_B_DQ5 6

DQ63

30

5
7
15
17
4
6
16
18
21

M_B_DQ1 4

23

M_B_DQ1 0

33

M_B_DQ1 5

35

M_B_DQ1 2

22

M_B_DQ9

24

M_B_DQ8

34

M_B_DQ1 1

36

M_B_DQ1 3

39
41
51
53
40
42
50
52
57

M_B_DQ2 7

59

M_B_DQ2 5

67

M_B_DQ3 1

69

M_B_DQ2 8

56

M_B_DQ2 6

58

M_B_DQ2 4

68

M_B_DQ2 9

70

M_B_DQ3 0

129
131
141
143
130
132
140
142
147

M_B_DQ4 1

149

M_B_DQ4 0

157

M_B_DQ4 7

159

M_B_DQ4 6

146

M_B_DQ4 5

148

M_B_DQ4 4

158

M_B_DQ4 2

160

M_B_DQ4 3

163
165
175
177
164
166
174
176
181

M_B_DQ5 9

183

M_B_DQ6 3

191

M_B_DQ6 1

193

M_B_DQ6 0

180

M_B_DQ5 8

182

M_B_DQ5 7

192

M_B_DQ6 2

194

M_B_DQ5 6

30

DDR3_D RAMRST#

M_B_DQ1
M_B_DQ5
M_B_DQ4
M_B_DQ7
M_B_DQ3
M_B_DQ0
M_B_DQ2
M_B_DQ6

M_B_DQ1 6
M_B_DQ1 7
M_B_DQ2 2
M_B_DQ1 9
M_B_DQ2 1
M_B_DQ2 0
M_B_DQ1 8
M_B_DQ2 3

M_B_DQ3 3
M_B_DQ3 2
M_B_DQ3 8
M_B_DQ3 4
M_B_DQ3 6
M_B_DQ3 7
M_B_DQ3 5
M_B_DQ3 9

M_B_DQ5 3
M_B_DQ5 2
M_B_DQ5 0
M_B_DQ4 9
M_B_DQ4 8
M_B_DQ5 4
M_B_DQ5 1
M_B_DQ5 5

DDR3_D RAMRST# 5,16

RESET#

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5

0

DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13

1

DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21

2

DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29

3

DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37

4

DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44

5

DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53

6

DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61

7

DQ62
DQ63

RESET#

4

M_B_DQ[6 3:0] 5M_B_A[15 :0]5

ok

ok

ok

ok

ok

ok

ok

ok

4

+1.35V_D DR3

12

12

C1702

C1701

0.1UF/10V

0.1UF/10V

Layout Note: Place th ese caps near SO DIM M 1

1

PM_EXTT S#0_DI M_B

T1701

Reserve

+V_VREF _CA_D IMM1

12

12

C1724

2.2UF/6.3V

@

+V_VREF _DQ_D IMM1

12

12

C1722

2.2UF/6.3V

@

+1.35V_D DR3

12

12

C1730

C1735

0.1UF/10V

0.1UF/10V

/DGPU

Layout Note: Place th ese caps near SO DIM M 1

/DGPU

T1702

Reserve

+V_VREF _CA_D IMM1

+V_VREF _DQ_D IMM1

1

PM_EXTT S#0_DI M_B

12

C1732

2.2UF/6.3V

@

12

C1733

2.2UF/6.3V

@

12

/DGPU

12

/DGPU

C1723

0.1UF/10V

C1725

0.1UF/10V

C1729

0.1UF/10V

C1727

0.1UF/10V

CON1701 B

75

VDD1
VDD381VDD4
VDD587VDD6
VDD793VDD8

99

VDD9

105

VDD11

111

VDD13

117

VDD15

123

VDD17

2

VSS1

8

VSS3

13

VSS5

19

VSS7

25

VSS9

31

VSS11

37

VSS13

43

VSS15

48

VSS17

54

VSS19

60

VSS21

65

VSS23

71

VSS25

127

VSS27

133

VSS29

138

VSS31

144

VSS33

150

VSS35

155

VSS37

161

VSS39

167

VSS41

172

VSS43

178

VSS45

184

VSS47

189

VSS49

195

VSS51

198

EVENT#

125

TEST

77

NC1

122

NC2

126

VREFCA

1

VREFDQ

DDR3_D IMM_204P

12V02G ISM001

CON1702 B

75

VDD1
VDD381VDD4
VDD587VDD6
VDD793VDD8

99

VDD9

105

VDD11

111

VDD13

117

VDD15

123

VDD17

2

VSS1

8

VSS3

13

VSS5

19

VSS7

25

VSS9

31

VSS11

37

VSS13

43

VSS15

48

VSS17

54

VSS19

60

VSS21

65

VSS23

71

VSS25

127

VSS27

133

VSS29

138

VSS31

144

VSS33

150

VSS35

155

VSS37

161

VSS39

167

VSS41

172

VSS43

178

VSS45

184

VSS47

189

VSS49

195

VSS51

198

EVENT#

125

TEST

77

NC1

122

NC2

126

VREFCA

1

VREFDQ

DDR3_D IMM_204P

12V02G ISM000

/DGPU

NP_NC1
NP_NC2

VDDSPD

NP_NC1
NP_NC2

VDDSPD

3

+1.35V

+1.35V 5,6,16 ,18,63,83

+0.675VS

+0.675VS 16 ,63,83

+3VS

+3VS 16,20,21 ,22,23,25 ,26,27,2 8,30,33,3 7,38,39,4 0,41,43 ,47,48,49 ,53,55,6 0,63,65,6 6,91,92

+1.35V_D DR3

+1.35V_D DR3 1 6

@

Layout Note: Place th ese caps near SO DIM M 1

12

12

C1741

C1742

10UF/10V

10UF/10V

Layout Note: Place th ese caps near SO DIM M 1

12

12

C1705
10UF/10V

/DGPU

/DGPU

C1710
10UF/10V

12

/DGPU

12

+0.675VS

12

+0.675VS

/DGPU

3

C1703

0.1UF/10V

12

C1715

0.1UF/10V

C1728

0.1UF/10V

12

C1736

0.1UF/10V

+1.35V_D DR3

12

+1.35V_D DR3

12

/DGPU

C1704

0.1UF/10V

+3VS

12

C1720

0.1UF/10V

+3VS

12

C1714

2.2UF/6.3V

@

C1734

2.2UF/6.3V

@

12

+

CE1703
220UF/6.3 V

1BV090 000003

76

VDD2

82
88
94
100

VDD10

106

VDD12

112

VDD14

118

VDD16

124

VDD18

3

VSS2

9

VSS4

14

VSS6

20

VSS8

26

VSS10

32

VSS12

38

VSS14

44

VSS16

49

VSS18

55

VSS20

61

VSS22

66

VSS24

72

VSS26

128

VSS28

134

VSS30

139

VSS32

145

VSS34

151

VSS36

156

VSS38

162

VSS40

168

VSS42

173

VSS44

179

VSS46

185

VSS48

190

VSS50

196

VSS52

207

GND1

208

GND2

205
206

203

VTT1

204

VTT2

199

76

VDD2

82
88
94
100

VDD10

106

VDD12

112

VDD14

118

VDD16

124

VDD18

3

VSS2

9

VSS4

14

VSS6

20

VSS8

26

VSS10

32

VSS12

38

VSS14

44

VSS16

49

VSS18

55

VSS20

61

VSS22

66

VSS24

72

VSS26

128

VSS28

134

VSS30

139

VSS32

145

VSS34

151

VSS36

156

VSS38

162

VSS40

168

VSS42

173

VSS44

179

VSS46

185

VSS48

190

VSS50

196

VSS52

207

GND1

208

GND2

205
206

203

VTT1

204

VTT2

199

C1744
10UF/10V

2

+0.675VS+1.35V_DDR 3+1.35V _DDR3

12

C1745
10UF/10V

@

12

C1711
10UF/10V

/DGPU

C1749

C1750

10UF/10V

10UF/10V

@

@

12

12

C1712

C1713

10UF/10V

10UF/10V

@

@

2

12

12

12

12

C1746
1UF/6.3V

+0.675VS+1.35V_DDR3

12

C1726
10UF/10V

@

12

C1716
1UF/6.3V

/DGPU

C1743
1UF/6.3V

12

12

C1747

C1748

1UF/6.3V

1UF/6.3V

@

@

12

/DGPU

C1717
1UF/6.3V

12

12

C1719

C1718

1UF/6.3V

1UF/6.3V

@

@

1

Title :

Title :

Title :

DDR3(2)_SO-DIMM1

DDR3(2)_SO-DIMM1

DDR3(2)_SO-DIMM1

Engineer:

Wing_Cheng

Engineer:

Wing_Cheng

Engineer:

BG1-CSC -HW R&D D ept.5

BG1-CSC -HW R&D D ept.5

BG1-CSC -HW R&D D ept.5

Size P roject Name

Size P roject Name

Size P roject Name

D

D

D

VA70_HW

VA70_HW

VA70_HW

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

Wing_Cheng

17 96Friday, January 18, 20 13

17 96Friday, January 18, 20 13

17 96Friday, January 18, 20 13

Rev

Rev

Rev

1.0

1.0

1.0

5

DDR3L Vref

D D

M3: CPU driven VREF path is stuffed be default.
M1: VREF_DQ driven by a Voltage Divider Network during Processor power-off

4

3

+V_VREF_DQ_DIMM0

2

+1.35V_DDR3

+V_VREF_CA_DIMM0

+V_VREF_DQ_DIMM0

+V_VREF_CA_DIMM1

+V_VREF_DQ_DIMM1

1

+1.35V_DDR3 16,17

+V_VREF_CA_DIMM0 16

+V_VREF_DQ_DIMM0 5,16

+V_VREF_CA_DIMM1 17

+V_VREF_DQ_DIMM1 5,17

M3

DIMM0_VREF_DQ5,16

DIMM1_VREF_DQ5,17

+1.35V

R1.2 2012/11/08

C C

12

C1803

0.1UF/16V

cost dwon 0ohm
R1.2 2012/12/04

R1804

change short pin size

1KOhm

1 2

1 2

SP1805 R0402

nb_r0402_short_25mil

12

R1805
1KOhm

@

12

12

C1802

0.1UF/16V

R1803
0Ohm

+1.35V

1 2

12

R1816
1KOhm

R1815
1KOhm

SP1804 R0402

nb_r0402_short_25mil

+V_VREF_DQ_DIMM1

R1.2 2012/11/08
cost dwon 0ohm

R1.2 2012/12/04
change short pin size

1 2

12

12

C1804

0.022UF/16V

R1807

24.9Ohm

1%

12

12

C1805

0.022UF/16V

R1808

24.9Ohm

1%

CHKLST, 497750

M1

Intel 0203
M3+M1: Default Recommendation

B B

M3

DIMM_VREF_CA5

+1.35V

R1810
1KOhm

1 2

12

12

A A

C1801

0.1UF/16V

R1811
1KOhm

R1.2 2012/11/08
cost dwon 0ohm

R1.2 2012/12/04
change short pin size

1 2

SP1803 R0402

nb_r0402_short_25mil

CHKLST, 497750

12

12

C1806

0.022UF/16V

R1809

24.9Ohm

1%

1 2

SP1802 R0402

nb_r0402_short_25mil

1 2

SP1801 R0402

nb_r0402_short_25mil

M1

5

4

+V_VREF_CA_DIMM0

+V_VREF_CA_DIMM1

Title :

Title :

Title :

DDR3(3)_CA/DQ Voltage

DDR3(3)_CA/DQ Voltage

Engineer:

Engineer:

PEGATRON COMPUTER INC

PEGATRON COMPUTER INC

PEGATRON COMPUTER INC

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

3

2

Date: Sheet of

VA70_HW

VA70_HW

VA70_HW

Engineer:

DDR3(3)_CA/DQ Voltage

Wing_Cheng

Wing_Cheng

Wing_Cheng

18 96Friday, January 18, 2013

18 96Friday, January 18, 2013

18 96Friday, January 18, 2013

1

Rev

Rev

Rev

1.0

1.0

1.0

5

D D

C C

4

3

2

1

B B

A A

R1.4--2

Title :

Title :

Title :

VID Controller

VID Controller

VID Controller

Wing_Cheng

Wing_Cheng

Engineer:

Engineer:

VA70_HW

VA70_HW

VA70_HW

Engineer:

1

PEGATRON COMPUTER INC

PEGATRON COMPUTER INC

PEGATRON COMPUTER INC

Size Project Name

Size Project Name

Size Project Name

C

C

C

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Wing_Cheng

19 96Friday , January 18, 2013

19 96Friday , January 18, 2013

19 96Friday , January 18, 2013

Rev

Rev

Rev

1.0

1.0

1.0

5

4

3

2

1

GND

C2005

1UF/6.3V

C2004

1UF/6.3V

+RTCBAT

12

J2001
BATT_HOLDER_2P

12V20GBSM000

1

1

2

2

GNDGND

JRST2002

Open
(Default)

R1.2 2012/11/06

工工工工工工

R2001 1KOhm

1

JRST2001

1

2

SGL_JUMP

@

2

JRST2002

SGL_JUMP

@

T2011

1

T2010

1

12

+RTC_BAT

R1.0 0110

增增增增增增增增增增增增增增增增增增增增

Shunt

12

R2028330KOhm 1%

@

+VCC_RTC+3VA

D2001

1

2

1V/0.2A

T2012

1

3

12

GND

Connector Type 1217-001L000

TPM Settings

Clear ME RTC
Registers

Keep ME RTC
Registers

GND

JRST2001

Shunt

Open
(Default)

C2003
1UF/6.3V

T2005

1

T2007

1

T2006

1

ACZ_SDIN0_AUD41

R1.2 2012/12/03
Add R2031

PCH_FLASH_DESCRIPTOR30

ACZ_SDOUT_AUD41

C2001

12

RTC_X1_C

15PF/50V

12

C2002 15PF/50V

R2020 330KOhm1%

SB_SPKR41

2

3

07V080000003

1 2

R2011

R2012

R2015

1 2

R2031 10KOhm

1 2

R2013

+VCC_RTC

ACZ_BCLK_AUD41

ACZ_SYNC_AUD41

ACZ_RST#_AUD41,42

EXT_SCI#30

GND

GND

GND

R1.1

1

T2001

1

T2002

1

T2003

1

T2004

R1.2 2012/11/28
follow Intel design guide

T2008

GND

1

SP2002

1 2

R0402

14

X2001

32.768KHZ
10MOhm

33Ohm

1 2

33Ohm

1 2

33Ohm

1 2

33Ohm

1 2

R2017 10KOhm

R2027 0Ohm

12

R2002

PCH_INTVRMEN

@

1 2

RTC_X1

RTC_X2

SRTC_RST#

SM_INTRUDER#

RTC_RST#

ACZ_BCLK

ACZ_SYNC

ACZ_RST#

Remove TP

ACZ_SDOUT

HDA_DOCK_EN#

+3VSUS_ORG

PCH_JTAG_TCK_BUF

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

PM_TEST_RST_N

+VCC_RTC

+3VSUS_ORG

+VTT_PCH_VCCIO

U2001A

B5

RTCX1

B4

RTCX2

B9

SRTCRST#

A8

INTRUDER#

G10

INTVRMEN

D9

RTCRST#

B25

HDA_BCLK

A22

HDA_SYNC

AL10

SPKR

C24

HDA_RST#

L22

HDA_SDI0

K22

HDA_SDI1

G22

HDA_SDI2

F22

HDA_SDI3

A24

HDA_SDO

B17

DOCKEN#/GPIO33

C22

HDA_DOCK_RST#/GPIO13

AB3

JTAG_TCK

AD1

JTAG_TMS

AE2

JTAG_TDI

AD3

JTAG_TDO

F8

TP25

C26

TP22

AB6

TP20

DH82LPMS

02V000000012

+12VS

+1.5VS

+VCC_RTC 22,27

+3VA

+3VA 27,30,63,65,81,88,93

+3VS

+3VS 16,17,21,22,23,25,26,27,28,30,33,37,38,39,40,41,43,47,48,49,53,55,60,63,65,66, 91,92

+3VSUS_ORG 21,22, 24,25,26,27

+12VS 28,39,41,63,91

+1.5VS 21,22,24,26,27,41,53,55,63,84

+VTT_PCH_VCCIO 26, 27

LPT_PCH_M_EDS

SATA_RXN_0
SATA_RXP_0

SATA_TXN_0

SATA_TXP_0

SATA_RXN_1
SATA_RXP_1

SATA_TXN_1

SATA_TXP_1

SATA

JTAGRTC AZALIA

SATA_RXN_2
SATA_RXP_2

SATA_TXN_2

SATA_TXP_2

SATA_RXN_3
SATA_RXP_3

SATA_TXN_3

SATA_TXP_3

SATA_RXN4/PERN1
SATA_RXP4/PERP1

SATA_TXN4/PETN1

SATA_TXP4/PETP1

SATA_RXN5/PERN2
SATA_RXP5/PERP2

SATA_TXN5/PETN2

SATA_TXP5/PETP2

SATA_RCOMP

SATALED#

SATA0GP/GPIO21

SATA1GP/GPIO19

SATA_IREF

TP9

TP8

BC8
BE8

AW8
AY8

BC10
BE10

AV10
AW10

BB9
BD9

AY13
AW13

BC12
BE12

AR13
AT13

BD13
BB13

AV15
AW15

BC14
BE14

AP15
AR15

AY5

AP3

AT1

AU2

BD4

BA2

BB2

Int. PU

SATA_COMP

SATA_DET0_R_N

BBS_BIT0_R

R1.3 2013/1/11
mSATA move to port 4

1 2

R2026 7.5KOhm

1 2

R2024 10KOhm

SP2001 R0402

R2016 0Ohm

12

12

+1.5VS
+3VS

1

+1.5VS

SATA_RXN0 60
SATA_RXP0 60

SATA_TXN0 60
SATA_TXP0 60

SATA_RXN2 60
SATA_RXP2 60

SATA_TXN2 60
SATA_TXP2 60

SATA_RXN4 53
SATA_RXP4 53

SATA_TXN4 53
SATA_TXP4 53

SATA_RXN5 60
SATA_RXP5 60

SATA_TXN5 60
SATA_TXP5 60

SATA_LED# 66

T2009

BBS_BIT0 23

HDD1

ODD

mSATA

HDD2

RTC battery

3
4

D D

+VCC_RTC

RTCRST# RC delay
should be 18ms~25ms

12

5%

R2018 20KOhm

12

GND GND

R20231MOhm

12

12

5%

R2021 20KOhm

C C

B B

12

Request by CSC
for CMOS clear
function

CMOS Settings

Clear CMOS

Keep CMOS

INTVRMEN: Integrated SUS 1.05V VRM Enables
Low: Enable External VRs
High:Enable Internal VRs

PCH_INTVRMEN

HDA_DKEN : Flash Descriptor Security Overide
H = Disabled (Default)
L = Enabled

Note : Rising edge of PWROK

HDA_DOCK_EN#

A A

5

JRST2003

1MM_OPEN_M1M2

112

2

12

R2030 1KOhm

@

Strap information:

HDA_SPKR: No reboot strap
Low: Disable (Default)
High:Enable

HDA_SDO:

1.Flash descriptor security:
Sampled Low: in effect.
Sampled High: override

2.HDA_SDO which sample high on the rising edge of PWROK
Will also disable Intel ME.

HDA_DOCK_EN#:
Reserved

[0216] : ACZ_SYNC strap is no longer supported on LPT, by Intel FAE Stu.

4

3

SB_SPKR

ACZ_SDOUT

R2019 1KOhm@

R2022 1KOhm@

1 2

1 2

SATA0GP的pull up

+3VS

+3VSUS_ORG

2

電電，參參參參

(43K ohm)和check list(10K ohm))

+3VS

SATA_DET0_R_N

1 2

R2025 10KOhm

@

PEGATRON COMPUTER INC

PEGATRON COMPUTER INC

PEGATRON COMPUTER INC

Size Project Name

Size Project Name

Size Project Name

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

VA70_HW

VA70_HW

VA70_HW

寫的寫寫??先先參參參參

Title :

Title :

Title :

PCH(1)_SATA,IHDA,RTC,LPC

PCH(1)_SATA,IHDA,RTC,LPC

PCH(1)_SATA,IHDA,RTC,LPC

Wing_Cheng

Wing_Cheng

Engineer:

Engineer:

Engineer:

1

Wing_Cheng

20 96Friday , January 18, 2013

20 96Friday , January 18, 2013

20 96Friday , January 18, 2013

Rev

Rev

Rev

1.0

1.0

1.0

5

CLK_REQ1#

A20

C20

A18

C18

B21

D21

G20

AL11

AJ11

AJ7

AL7

AJ10

AH1

AH3

AJ4

AJ2

Y43

Y45

AB1

AA44
AA42

AF1

AB43

AB45

AF3

AD43
AD45

T3

AF43

AF45

V3

AE44
AE42

AA2

AB40
AB39

AE4

AJ44

AJ42

Y3

AH43

AH45

D44

E44

B42

F41

A40

U2001D

LAD_0

LAD_1

LAD_2

LAD_3

LFRAME#

LDRQ0#

LDRQ1#/GPIO23

SERIRQ

SPI_CLK

SPI_CS0#

SPI_CS1#

SPI_CS2#

SPI_MOSI

SPI_MISO

SPI_IO2

SPI_IO3

1

1

1

1
1
1

1

1

1

1

1

T2130

SP2117
SP2118

SP2119

1

CLK_PCH_SRC6_N

1

CLK_PCH_SRC6_P

1

/TPM

CLK_PCH_SRC0_N

CLK_PCH_SRC0_P

CLK_REQ0#

CLK_PCH_SRC2_N

CLK_PCH_SRC2_P

CLK_REQ2#

CLK_PCH_SRC3_N
CLK_PCH_SRC3_P
CLK_REQ3#

CLK_PCH_SRC4_N
CLK_PCH_SRC4_P
CLK_REQ4#

CLK_PCH_SRC5_N
CLK_PCH_SRC5_P
CLK_REQ5#

CLK_REQ6#

CLK_PCH_SRC7_N

CLK_PCH_SRC7_P

CLK_REQ7#

CLK_XDP_N

CLK_XDP_P

12

R213222Ohm

12

R212922Ohm

1

T2121

12

CLK_PCH_SRC1_N

12

CLK_PCH_SRC1_P

12

CLKOUT_PCI0_R

12

CLK_PCI_FB_R

R212822Ohm

CLK_KBCPCI_PCH_R

12

CLK_DEBUG_R

R213022Ohm

CLK_DBG_R

1

SNN_LPC_DRQ#1

Serial Interrupt Request

T2102

T2104

T2101

D D

CLK_PCIE_mSATA#_PCH53

CLK_PCIE_mSATA_PCH53

CLK_REQ2_PCIE_mSATA#53

CLK_PCIE_WLAN#_PCH55

CLK_PCIE_WLAN_PCH55

CLK_REQ3_WLAN#55

CLK_PCIE_LAN#33

CLK_PCIE_LAN33

CLK_REQ4_LAN#33

C C

B B

CLK_PCIE_CR#_PCH40
CLK_PCIE_CR_PCH40

CLK_REQ1_CR#40

SP2104 R0402

SP2105 R0402

SP2106 R0402

SP2107 R0402
SP2108 R0402
SP2109 R0402

100MHz

LPCCLK43

CLK_KBCPCI_PCH30

CLK_DEBUG65

DGPU_PWR_EN is active high

LPC_FRAME#30,43,65

INT_SERIRQ30,43,65

PCH_SPICLK28,30

PCH_SPICS0#28

PCH_SPICS1#28,30

PCH_SPISI28,30

PCH_SPISO28,30

SPI_WP_IO228,30

SPI_HOLD#_IO328,30

1 2

1 2

1 2

1 2

SP2101 R0402

1 2

SP2102 R0402

1 2

SP2103 R0402

1 2
1 2
1 2

T2116
T2117
T2118

T2134
T2133
T2135

T2114

T2115

T2111

T2132

T2131

CLK_PCI_FB

C2103
10PF/50V

1 2

@

GND

LPC_AD030,43,65

LPC_AD130,43,65

LPC_AD230,43,65

LPC_AD330,43,65

PCH_SPICS1#

4

U2001C

CLKOUT_PCIE_N_0

CLKOUT_PCIE_P_0

PCIECLKRQ0#/GPIO73

CLKOUT_PCIE_N_1
CLKOUT_PCIE_P_1

PCIECLKRQ1#/GPIO18

CLKOUT_PCIE_N_2

CLKOUT_PCIE_P_2

PCIECLKRQ2#/GPIO20/SMI#

CLKOUT_PCIE_N_3
CLKOUT_PCIE_P_3
PCIECLKRQ3#/GPIO25

CLKOUT_PCIE_N_4
CLKOUT_PCIE_P_4
PCIECLKRQ4#/GPIO26

CLKOUT_PCIE_N5
CLKOUT_PCIE_P_5
PCIECLKRQ5#/GPIO44

CLKOUT_PCIE_N_6
CLKOUT_PCIE_P_6
PCIECLKRQ6#/GPIO45

CLKOUT_PCIE_N_7

CLKOUT_PCIE_P_7

PCIECLKRQ7#/GPIO46

CLKOUT_ITPXDP

CLKOUT_ITPXDP_P

CLKOUT_33MHZ0

CLKOUT_33MHZ1

CLKOUT_33MHZ2

CLKOUT_33MHZ3

CLKOUT_33MHZ4

CLOCK SIGNAL

DH82LPMS

02V000000012

SPILPC

LPT_PCH_M_EDS

LPT_PCH_M_EDS

SMBus

C-Link

Thermal

CLKOUT_PEG_A

CLKOUT_PEG_A_P

PEGA_CLKRQ#/GPIO47

CLKOUT_PEG_B

CLKOUT_PEG_B_P

PEGB_CLKRQ#/GPIO56

CLKOUT_DMI

CLKOUT_DMI_P

CLKOUT_DP

CLKOUT_DP_P

CLKOUT_DPNS

CLKOUT_DPNS_P

CLKIN_DMI

CLKIN_DMI_P

CLKIN_GND

CLKIN_GND_P

CLKIN_DOT96N

CLKIN_DOT96P

CLKIN_SATA

CLKIN_SATA_P

REFCLK14IN

CLKIN_33MHZLOOPBACK

XTAL25_OUT

XTAL25_IN

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

ICLK_IREF

TP19
TP18

DIFFCLK_BIASREF

SMBALERT#/GPIO11

SMBCLK

SMBDATA

SML0ALERT#/GPIO60

SML0CLK

SML1ALERT#/PCHHOT#/GPIO74

SML0DATA

SML1CLK/GPIO58

SML1DATA/GPIO75

CL_CLK

CL_DATA

CL_RST#

TD_IREF

AB35

CLK_PCIE_PEG#_PCH_L

AB36

CLK_PCIE_PEG_PCH_L

AF6

CLK_REQ_PEG_A#

Y39

Y38

U4

AF39

AF40

AJ40
AJ39

AF35

CLK_DP_N

AF36

CLK_DP_P

AY24

CLK_BUF_EXP_N

AW24

CLK_BUF_EXP_P

AR24

CLK_BUF_CPYCLK_N

AT24

CLK_BUF_CPYCLK_P

H33

CLK_BUF_DOT96_N

G33

CLK_BUF_DOT96_P

BE6

CLK_BUF_CKSSCD_N

BC6

CLK_BUF_CKSSCD_P

F45

CLK_BUF_REF14

D17

CLK_PCI_FB

AL44
AM43

C40

DGPU_EDID_SELECT#

F38

CLK_OUT1

F36

CLK_OUT2

F39

DGPU_PRSNT#

AM45

ICLK_IREF

AD39
AD38

AN44

N7

R10

U11

N8

U8

R7

H6

K6

N11

AF11

AF10

AF7

BA45

TP1

BC45

TP2

BE43

TP4

BE44

TP3

AY43

CLK_PCH_PEG_B_N

CLK_PCH_PEG_B_P

CLK_REQ_PEG_B#

XTAL25_OUT
XTAL25_IN

SP2120

DIFFCLK_BIASREF

SCL_3A

SDA_3A

DRAMRST_CNTRL_PCH

SML0_CLK

SML0_DAT

SML1ALERT#

SML1_CLK

SML1_DAT

12

R2103

8.06KOhm

+3VS

+1.5VS

+3VSUS_ORG

+VCCAXCK_VRM

1 2

SP2113 R0402

1 2

SP2114 R0402

1 2

SP2112 R0402

1

1

1

1

NB_R0402_20MIL_SMALL

1 2

R1.2 2012/11/28
cost dwon 0ohm

1%

1 2

R2116 7.5KOhm

1

It must be 8.2k ohm 1% ???

3

+3VS 16,1 7,20,22,23,25,26,27,28,30,33,37,38,39,40,41,43,47,48,49,5 3,55,60,63,65,66,91,92

+1.5VS 20,22,24,26,27,41,53,55,63,84

+3VSUS_ORG 20,22,2 4,25,26,27

+VCCAXCK_VRM 27

CLK_PCIE_PEG#_PCH 70

CLK_PCIE_PEG_PCH 70

T2109

T2110

T2105

CLKREQ_PEG# 70

CLK_EXP_N 4

CLK_EXP_P 4

CLK_DP_SSC_N 4
CLK_DP_SSC_P 4

CLK_DP_N 4
CLK_DP_P 4

100MHz

135MHz

135MHz

SP2111
R0402

1 2

XTAL25_OUT_C

1

1

1

12

T2113

T2128

T2126

T2127

+1.5VS

R1.2 2012/12/04
change short pin size

+VCCAXCK_VRM

R2111 1MOhm

Debug

SCL_3A

SDA_3A

SCL_3A

SDA_3A

DRAMRST_CNTRL_PCH

SML0_CLK

SML0_DAT

SML1_CLK

SML1_DAT

SML1ALERT#

ELAN_ALERT#

T2112

ELAN_ALERT# 48

SCL_3A 28

SDA_3A 28

DRAMRST_CNTRL_PCH 5

1

T2120

1

T2122

SML1_CLK 28

SML1_DAT 28

1

T2123

1

T2124

1

T2125

R1.1

C2102 12PF/50V

1 2

GND

X2101

13

25MHZ

2

GND

4

C2101 12PF/50V

1 2

07V080000010

GND

1

T2136

1

T2137

RN2103B 2.2KOhm

RN2103A 2.2KOhm

34

12

1 2

R2104 1KOhm

3 4

2.2KOhm

1 2

2.2KOhm

1 2

2.2KOhm

3 4

2.2KOhm

1 2

R2105 10KOhm

1 2

R2131 10KOhm

2

RN2104B

RN2104A

RN2105A

RN2105B

+3VSUS_ORG

CLK_BUF_CPYCLK_N
CLK_BUF_CPYCLK_P

CLK_BUF_EXP_N
CLK_BUF_EXP_P
CLK_BUF_DOT96_N
CLK_BUF_DOT96_P
CLK_BUF_CKSSCD_N
CLK_BUF_CKSSCD_P

CLK_BUF_REF14

INT_SERIRQ

DGPU_EDID_SELECT#

DGPU_PRSNT#

DGPU_PRSNT#

PCH CLKREQ Setting:
Not connected to device.

CLK_REQ4_LAN#

CLK_REQ0#

CLK_REQ3_WLAN#

CLK_REQ6#

CLK_REQ5#

CLK_REQ7#

CLK_REQ_PEG_B#

CLK_REQ_PEG_A#

Connected to device.

R1.2 2012/12/13
WLAN clk pull-high換換+3VS

CLK_REQ3_WLAN#

CLK_REQ1#

CLK_REQ2#

CLK_REQ6#

CLK_REQ4_LAN#

CLK_REQ3_WLAN#

CLK_REQ2#

CLK_REQ1#

1 2
3 4

1 2
3 4
1 2
3 4
3 4
1 2

1 2

R2101 10KOhm

CLOCK TERMINATION for FCIM
Default power-on mode is ICC.

1 2

R2107 10KOhm

1 2

R2113 10KOhm@

1 2

R2106 10KOhm/UMA

1 2

R2109 10KOhm/DGPU

1 2

R2117 10KOhm

1 2

R2118 10KOhm

@

1 2

R2133 10KOhm

1 2

R2121 10KOhm

1 2

R2122 10KOhm

1 2

R2123 10KOhm

1 2

R2124 10KOhm

1 2

R2125 10KOhm

1 2

R2108 10KOhm

1 2

R2119 10KOhm

1 2

R2120 10KOhm

1 2

R2114 10KOhm@

1 2

R2112 10KOhm@

1 2

R2110 10KOhm@

1 2

R2126 10KOhm@

@

1 2

R2127 10KOhm

10KOhm
10KOhm

10KOhm
10KOhm
10KOhm
10KOhm
10KOhm
10KOhm

RN2108A
RN2108B

RN2109A
RN2109B
RN2110A
RN2110B
RN2111B
RN2111A

GND

+3VS

GND

+3VSUS_ORG

R1.2 2012/12/17
Add R2133

+3VS

GND

1

GND

A A

DH82LPMS

02V000000012

BG1\CORE

BG1\CORE

BG1\CORE

Size Project Nam e

Size Project Nam e

Size Project Nam e

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

VA70_HW

VA70_HW

VA70_HW

Title :

Title :

Title :

PCH(2)_PCIE,CLK,SMB,PEG

PCH(2)_PCIE,CLK,SMB,PEG

PCH(2)_PCIE,CLK,SMB,PEG

Wing_Cheng

Wing_Cheng

Wing_Cheng

Engineer:

Engineer:

Engineer:

1

Rev

Rev

Rev

1.1

1.1

1.1

21 96Friday, January 18, 2013

21 96Friday, January 18, 2013

21 96Friday, January 18, 2013

5

DMI_RXN03
DMI_RXN13

D D

If SUSWARN #/SUS_ACK # handshake
is not used, these signals are tied on the board

R1.2 2012/11/06

工工工工工工

PM_PWROK9,30,92

C C

PM_RSMRST# has pull down 10k ohm in EC

DMI_RXN23
DMI_RXN33

DMI_RXP03
DMI_RXP13

DMI_RXP23
DMI_RXP33

DMI_TXN03
DMI_TXN13

DMI_TXN23
DMI_TXN33

DMI_TXP03
DMI_TXP13

DMI_TXP23
DMI_TXP33

R2225 0Ohm

+1.5VS

+1.5VS

T2211

SUS_PWR_ACK_R

1

SUSACK#_PCH

+3VS

T2212

1

ME_SUSPWRDNACK30

SYS_PWROK SYS_PWROK_R

PM_DRAM_PWRGD4

PM_RSMRST#30

PM_PWRBTN#30

ME_AC_PRESENT30

T2201

1

T2202

1

T2203

1

12

R2231 7.5KOhm

1 2

SP2208 R040 2

1 2

R2203 0Ohm@

R2205 10KOhm

SP2209 R040 2

1 2

SP2205 R040 2

1 2

SP2212 R040 2

1 2

SP2206 R040 2

1 2

SP2210 R040 2

1 2

SP2207 R040 2

1 2

SP2211 R040 2

1 2

12

12

4

DMI_IREF

DMI_RCOMP

SUSACK#_RSUSACK#_RSUSACK#_RSUSACK#_R

PM_SYSRST#_R

PM_PCH_PWROK_R

PM_APWROK_R

PM_RSMRST_R

SUS_PWR_ACK_R

AC_PRESENT_R

BATLOW#

RI#

SLP_WLAN#

U2001B

AW22

DMI_RXN_0

AR20

DMI_RXN_1

AP17

DMI_RXN_2

AV20

DMI_RXN_3

AY22

DMI_RXP_0

AP20

DMI_RXP_1

AR17

DMI_RXP_2

AW20

DMI_RXP_3

BD21

DMI_TXN_0

BE20

DMI_TXN_1

BD17

DMI_TXN_2

BE18

DMI_TXN_3

BB21

DMI_TXP_0

BC20

DMI_TXP_1

BB17

DMI_TXP_2

BC18

DMI_TXP_3

BE16

DMI_IREF

AW17

TP12

AV17

TP7

AY17

DMI_RCOMP

R6

SUSACK#

AM1

SYS_RESET#

AD7

SYS_PWROK

F10

PWROK

AB7

APWROK

H3

DRAMPWROK

J2

RSMRST#

J4

SUSWARN#/SUSPWRNACK/GPIO30

K1

PWRBTN#

E6

ACPRESENT/GPIO31

K7

BATLOW#/GPIO72

N4

RI#

DH82LPMS

AB10

TP21

D2

SLP_WLAN#/GPIO29

02V000000012

LPT_PCH_M_EDS

DMI

System Power

Management

FDI

FDI_RXN_0

FDI_RXN_1

FDI_RXP_0

FDI_RXP_1

FDI_CSYNC

FDI_INT

FDI_IREF

FDI_RCOMP

DSWVRMEN

DPWROK

WAKE#

CLKRUN#

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN#

3

AJ35

AL35

AJ36

AL36

AV43

TP16

AY45

TP5

AV45

TP15

AW44

TP10

AL39

AL40

AT45

AU42

TP17

AU44

TP13

AR44

C8

L13

K3

AN7

U7

Y6

Y7

C6

H1

F3

F1

AY3

G5

FDI_CSYNC_R

FDI_INT_R

FDI_IREF

FDI_RCOMP

DSWODVREN

PCH_DPROK

PM_CLKRUN#

SUS_STAT

SUSCLK_C

SLP_S5#

SLP_S4#_R

SLP_S3#_R

ME_PM_SLP_A#_R

SLP_DSW#_R

ME_PM_SLP_LAN#_R

SP2213 R040 2

1 2

SP2201 R040 2

1 2

R2230 7.5KOhm

R2208 330KOhm@

1 2

R2207 330KOhm

1 2

SP2214 R040 2

1 2

T2206

1

T2205

1

T2204

1

SP2202 R040 2

1 2

SP2203 R040 2

1 2

R2210 0Ohm@

12

1 2

1 2

T2209

1

R22260Ohm

GND

PM_RSMRST_R

1

+VCC_RTC

2

FDI_TXN0 4

FDI_TXN1 4

FDI_TXP0 4

FDI_TXP1 4

FDI_CSYNC 3

FDI_INT 3

+1.5VS

R1.2 2012/10/29
option changed from /FDI
R1.2 2012/12/19
option changed from /non_RETINA

+1.5VS

DSWODVREN - On Die DSW VR Enable
HIGH - Enabled(DEFAULT) ; LOW-Disabled

PCIE_WAKE# 3 3,53

PM_CLKRUN# 43

PM_SUSC# 30

PM_SUSB# 30

SLP_SUS# 30

H_PM_SYNC 4

T2210

i-AMT

i-AMT

+3VSUS_ORG

+1.5VS

+VCC_RTC

+3VSUS

+5VSUS

+12VSUS

+VCCDSW

+3VSUS_ORG 20,21,24,25 ,26,27

+3VS

+3VS 16,17,20,21,23,25,26,27,28,30,33 ,37,38,39,40,41,43,47,48,49,53,55,60,6 3,65,66,91,92

+1.5VS 20,21,24,26,27,41,53 ,55,63,84

+VCC_RTC 20,27

+3VSUS 4,23,27,28,30 ,33,43,61,81,92

+5VSUS 30,60,61,63 ,65,66,83,91

+12VSUS 28,33,55,6 0,81,91

+VCCDSW 27

+3VA

+3VA 20,27,30,63,65,81,88,93

1

R1.2 2012/12/17
U2201 @
R2204 mount

SYS_PWROK for PCH

R2204 0Ohm

12

+3VSUS

U2201

A

1

2

3 4

12

R2223
10KOhm

@

61

B

GND

Vcc=2~5.5

@

5

VCC

Q2201B

UM6K1N

SYS_PWROK

+3VS

/TPM

R2212 8.2KOhm

+12VSUS+3VSUS +5VSUS

5%

R2222
100KOhm

@

1 2

PS_S3CNTRL_1.5V 6

34

@

5

4

PM_CLKRUN#

PM_PWROK

PCH_DPROK

SUSCLK_C

1 2

R2213 10KOhm

1 2

R2235 100KOhm@

1 2

R2229 1KOhm@

1 2

3

GND

PLL ON DIE VR ENABLE
HIGH - ENABLED

GND

LOW - DISABLED (DEFAULT

PCIE_WAKE#

ME_AC_PRESENT
BATLOW#

ME_PM_SLP_A#_R

ME_SUSPWRDNACK

RI#

ME_PM_SLP_LAN#_R

R2232 10KOhm

R2234 10KOhm
R2233 10KOhm

R2217 10KOhm@

R2218 10KOhm

R2214 10KOhm

R2220 10KOhm@

2

Y

PM_SUSB#

PM_PWROK

SP2204 R040 2

1 2

R2224 0Ohm@12

5

10KOhm

R2221

R2206 0Ohm@12

12

@

Q2201A

UM6K1N

@

2

GND GND

DELAY_VR_AND_ALL_SYS92

B B

SUSB_EC#23,30 ,63,91,92

A A

1 2

1 2
1 2

1 2

1 2

1 2

1 2

+3VSUS_ORG

Title :

Title :

Title :

PCH(3)_FDI,DMI,SYS PWR

PCH(3)_FDI,DMI,SYS PWR

PCH(3)_FDI,DMI,SYS PWR

Engineer:

Wing_Cheng

Engineer:

Wing_Cheng

Engineer:

PEGATRON COMPUTER INC

PEGATRON COMPUTER INC

PEGATRON COMPUTER INC

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

VA70_HW

VA70_HW

VA70_HW

Date: Sheet of

Date: Sheet of

Date: Sheet of

Wing_Cheng

22 96Friday, January 18, 2013

22 96Friday, January 18, 2013

22 96Friday, January 18, 2013

1

Rev

Rev

Rev

1.0

1.0

1.0

5

R1.2 2012/10/29
option changed from /non_FDI_@

R1.2 2012/12/06

CRT_B_PCH

DAC_B_PCH38

D D

DAC_G_PCH38

DAC_R_PCH38

+3VS

1 2

R2309 1KOhm@

1 2

R2307 1KOhm@

1 2

R2308 1KOhm@

1 2

R2313 10KOhm

R2327 2.2KOhm

R2328 2.2KOhm

C C

CRT Disable: (For discrete graphic)

1. NC:

CRT_R,CRT_G,CRT_B

CRT_HSYCN,CRT_VSYNC

2. 1KΩ+-5% pull-down to GND:

50 ohm

CRT_G_PCH

50 ohm

CRT_R_PCH

50 ohm

R1.2 2012/10/29
option changed from /FDI
R1.2 2012/12/19
option changed from /non_RETINA

R1.3 2013/1/8
R2332~R2334 are removed

12

12

@

12

12

12

R231810KOhm @

R231910KOhm /DGPU

R232010KOhm /DGPU

Close to CPU

LCD_BL_PWM_PCH

LCD_BACKEN_PCH

LCD_VDD_EN_PCH

DGPU_PWM_SELECT#

DGPU_SELECT#

DGPU_HOLD_RST#_R

DGPU_PWR_EN

DDC2BC_PCH

DDC2BD_PCH

3. Connected to GND:

4. Connect to +V3.3:

CRT_ITRN
DAC_IREF

VCCADAC

JP2301 SHORT_PIN

JP2302 SHORT_PIN

JP2303 SHORT_PIN

BBS_BIT0,BBS_BIT1 : Boot BIOS Strap

Boot BIOS Strap

BBS_BIT0BBS_BIT1

Boot BIOS Location

LPC0

0

remove R2335~R2337, R2339~R2341, JP2304~JP2306 for GDDR5

0

Reserved (NAND)

Reserved

SPI

0 1

1

1 (PCH) DEFAULT1

12

12

12

R1.2 2012/10/29
option changed from /FDI

R1.2 2012/12/19
option changed from /non_RETINA

STP_A16OVR:
A16 swap override Strap/

Top-Block swap override jumper

Low=Enabled A16 swap override/
Top-Block swap override

High=Default

Sampled on rising edge of PWROK.

B B

BBS_BIT020

BBS_BIT0

BBS_BIT1

R1.1

1 2

R2310 1KOhm@

1 2

R2311 1KOhm@

1 2

R2316 10KOhm@

1 2

R2317 10KOhm@

STP_A16OVR

+3VS

GND

R2304

150Ohm

VGA_PWRON91

4

12

R2305

150Ohm

DGPU_HOLD_RST#70

1 2

R2312 1KOhm@

12

R2306

150Ohm

GND

+3VS

DGPU_PWR_EN63

R2325 0Ohm@

37.5 ohm

37.5 ohm

37.5 ohm

12

LCD_BL_PWM_PCH37

LCD_BACKEN_PCH37

LCD_VDD_EN_PCH37

GND

1 2

T2305

T2302

DDC2BC_PCH38

DDC2BD_PCH38

DAC_HSYNC_PCH38

DAC_VSYNC_PCH38

+3VSUS

GND

R1.2 2012/11/27
follow intel design guide
co-lay with R2326

SP2306 R0402

SP2307 R0402

SP2308 R0402

10KOhm

10KOhm

10KOhm

10KOhm

1 2

SP2301 R0402

1

DGPU_PWR_EN

1

U2301

5

VCC

4

GND3Y

SN74LVC1G08DCKR

@

1 2

R2324 0Ohm

B_PCH

G_PCH

R_PCH

1 2

SP2304 R0402

1 2

SP2305 R0402

1 2

R2326 649OHM1%

R1.2 2012/12/06
remove R2348 for GDDR5

1 2

1 2

1 2

56

78

34

12

1

A

2

B

RN2301C

RN2301D

RN2301B

RN2301A

R1.2 2012/12/19
option changed from /non_RETINA

INT_PIRQA#

INT_PIRQB#

INT_PIRQC#

INT_PIRQD#

DGPU_HOLD_RST#_R

DGPU_SELECT#

BBS_BIT1

DGPU_PWM_SELECT#

STP_A16OVR

PLT_RST#

+3VS

12

R2321
10KOhm

@

R2323 0Ohm@

GND

3

T45

U44

V45

M43

M45

N42

N44

U40

U39

N36

K36

G36

H20

L20

K17

M20

A12

B13

C12

C10

Int. PU

A10

AL6

Int. PU

DH82LPMS

02V000000012

U2302

1

A

2

B
GND3Y

SN74LVC1G08DCKR

@

GND

1 2

R2314 0Ohm

1 2

SUSB_EC# 22,30,63,91,92

U2001E

VGA_BLUE

VGA_GREEN

VGA_RED

VGA_DDC_CLK

VGA_DDC_DATA

VGA_HSYNC

VGA_VSYNC

DAC_IREF

VGA_IRTN

EDP_BKLTCTL

EDP_BKLTEN

EDP_VDDEN

PIRQA#

PIRQB#

PIRQC#

PIRQD#

GPIO50

GPIO52

GPIO54

GPIO51

GPIO53

GPIO55

5

VCC

4

DGPU_PWR_EN

+3VS

12

R2347
0Ohm

@

+3VS

+3V

LPT_PCH_M_EV

DDPB_CTRLCLK

DDPB_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPD_CTRLCLK

DDPD_CTRLDATA

DISPLAY

LVDSCRT

PCI

+3VSUS

12

Strap information:

R2346

There signals have a weak internal pull down

0Ohm

@

DDPB_CTRLDATA: "0" = Port is not detected; "1"= Port is detected
DDPC_CTRLDATA: "0" = Port is not detected; "1"= Port is detected
DDPD_CTRLDATA: "0" = Port is not detected; "1"= Port is detected

BUF_PLT_RST# 30,33,40,43,47,53,55,70

12

R2315

100KOhm

GND

DDPB_AUXN

DDPC_AUXN

DDPD_AUXN

DDPB_AUXP

DDPC_AUXP

DDPD_AUXP

DDPB_HPD

DDPC_HPD

DDPD_HPD

PIRQE#/GPIO2

PIRQF#/GPIO3

PIRQG#/GPIO4

PIRQH#/GPIO5

PME#

PLTRST#

R40

R39

R35

R36

N40

N38

H45

K43

J42

H43

K45

J44

K40

K38

H39

G17

F17

L15

M15

AD10

Y11

2

+3VS 16,17,20,21,22,25,26,27,28,30,33,37,38,39,40,41,43,47,48,49,53,55,60,63,65,66, 91,92

+3V 37,43,63,65, 91

HDMI_DDC_CLK_PCH 39

T2306

HDMI_DDC_DATA_PCH 39

1

R1.1

R1.2 2012/10/29

DPC_AUXN

DPC_AUXP

MPC_PWR_CTRL#

SATA_ODD_DA#

EXTTS_SNI_DRV0_PCH

EXTTS_SNI_DRV1_PCH

PCI_PME#

PLT_RST#

1

T2303

option changed from /non_FDI

R1.2 2012/12/06
remove R2338, R2329~R2331, R2349 for GDDR5

1

T2304

R1.2 2012/11/27

HDMI_HPD_PCH 39

SATA_ODD_DA# 60

1

T2301

+3VS

12

R23221KOhm @

follow intel design guide

GND

1 2
1 2
1 2
1 2

是否會浪費電?

R234210KOhm
R234310KOhm @
R234410KOhm @
R234510KOhm @

1

SATA_ODD_DA#
EXTTS_SNI_DRV1_PCH

EXTTS_SNI_DRV0_PCH

MPC_PWR_CTRL#

A A

Title :

Title :

Title :

PCH(4)_DP,LVDS,CRT

PCH(4)_DP,LVDS,CRT

PCH(4)_DP,LVDS,CRT

Wing_Cheng

Wing_Cheng

Engineer:

Engineer:

VA70_HW

VA70_HW

VA70_HW

Engineer:

PEGATRON COMPUTER INC

PEGATRON COMPUTER INC

PEGATRON COMPUTER INC

Size Project Name

Size Project Name

Size Project Name

C

C

C

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Wing_Cheng

1

Rev

Rev

Rev

1.0

1.0

1.0

23 96Friday , January 18, 2013

23 96Friday , January 18, 2013

23 96Friday , January 18, 2013

5

U2001I

PCIE_IREF

AW31
AY31

BE32
BC32

AT31

AR31

BD33
BB33

AW33
AY33

BE34
BC34

AT33

AR33

BE36
BC36

AW36
AV36

BD37
BB37

AY38
AW38

BC38
BE38

AT40
AT39

BE40
BC40

AN38
AN39

BD42
BD41

BE30

BC30

BB29

BD29

PERN1/USB3RN3
PERP1/USB3RP3

PETN1/USB3TN3
PETP1/USB3TP3

PERN2/USB3RN4
PERP2/USB3RP4

PETN2/USB3TN4
PETP2/USB3TP4

PERN_3
PERP_3

PETN_3
PETP_3

PERN_4
PERP_4

PETN_4
PETP_4

PERN_5
PERP_5

PETN_5
PETP_5

PERN_6
PERP_6

PETN_6
PETP_6

PERN_7
PERP_7

PETN_7
PETP_7

PERN_8
PERP_8

PETN_8
PETP_8

PCIE_IREF

TP11

TP6

DH82LPMS

02V000000012

PCIE_RCOMP

PCIE_RXN1_CR4 0
PCIE_RXP1_CR40

PCIE_TXN1_CR40
PCIE_TXP1_CR40

D D

PCIE_RXN6_mSATA53
PCIE_RXP6_mSATA53

PCIE_TXN6_mSATA5 3
PCIE_TXP6_mSATA53

PCIE_RXN2_WLAN55
PCIE_RXP2_WLAN55

PCIE_TXN2_WLAN55
PCIE_TXP2_WLAN55

PCIE_RXN3_LAN33
PCIE_RXP3_LAN33

PCIE_TXN3_LAN33
PCIE_TXP3_LAN33

C C

B B

A A

+1.5VS

+1.5VS

1 2

C2409 0.1UF/10V

1 2

C2410 0.1UF/10V

@

1 2

C2404 0.1UF/10V

1 2

C2403 0.1UF/10V

@

1 2

C2401 0.1UF/10V

1 2

C2402 0.1UF/10V

1 2

C2406 0.1UF/10V

1 2

C2407 0.1UF/10V

SP2403 NB_R0402_20MIL_SMALL

1 2

R1.2 2012/11/28
cost dwon 0ohm

R1.2 2012/12/04
change short pin size

1 2

R2401 7.5KOhm

5

PCIE_TXN1_CR_C
PCIE_TXP1_CR_C

PCIE_TXN6_mSATA_C
PCIE_TXP6_mSATA_C

PCIE_TXN2_WLAN_C
PCIE_TXP2_WLAN_C

PCIE_TXN3_GLAN_C
PCIE_TXP3_GLAN_C

PCIE_RCOMP

LPT_PCH_M_EDS

PCIe

4

B37

USB_PN0

USB2N0

D37

USB_PP0

USB2P0

A38

USB_PN1

USB2N1

C38

USB_PP1

USB2P1

A36

USB_PN2

USB2N2

C36

USB_PP2

USB2P2

A34

USB2N3

C34

USB2P3

B33

1

USB_PN4

USB2N4

D33

USB_PP4

USB2P4

F31

USB_PN5

USB2N5

G31

USB_PP5

USB2P5

K31

USB2N6

L31

USB2P6

G29

USB_PN7

USB2N7

H29

USB_PP7

USB2P7

A32

USB_PN8

USB2N8

C32

USB_PP8

USB2P8

A30

USB_PN9

USB2N9

C30

USB_PP9

USB2P9

B29

USB_PN10

USB2N10

D29

USB_PP10

USB2P10

A28

USB_PN11

USB2N11

C28

USB_PP11

USB2P11

G26

USB_PN12

USB2N12

F26

USB_PP12

USB2P12

F24

USB2N13

USB

4

USB2P13

USB3RN1
USB3RP1
USB3TN1
USB3TP1
USB3RN2
USB3RP2
USB3TN2
USB3TP2
USB3RN5
USB3RP5
USB3TN5
USB3TP5
USB3RN6

USB3RP6
USB3TN6
USB3TP6

USBRBIAS#

USBRBIAS

OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43

OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14

G24

AR26
AP26
BE24
BD23
AW26
AV26
BD25
BC24
AW29
AV29
BE26
BC26
AR29
AP29
BD27
BE28

K24
K26

M33

TP24

L33

TP23

P3
V1
U2
P1
M3
T1
N2
M1

USB_BIAS

OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14

1

1
1

1
1

1
1

T2403
T2405

T2404
T2406

T2407
T2408

T2401
T2402

1 2

R2403 22.6Ohm1%

SP2402 R0402

1 2

SP2401 R0402

@

1 2

R2404 0Ohm

7 8
1 2
3 4
1 2
7 8
5 6
3 4
5 6

1 2

USB_PN5 55
USB_PP5 55

USB_PN8 37
USB_PP8 37
USB_PN9 61
USB_PP9 61

USB_PN11 53
USB_PP11 53

10KOhm
10KOhm
10KOhm
10KOhm
10KOhm
10KOhm
10KOhm
10KOhm

USB_PN0 61
USB_PP0 61
USB_PN1 61
USB_PP1 61
USB_PN2 61
USB_PP2 61

GND

3

USB3_RX1_N 61
USB3_RX1_P 61
USB3_TX1_N 61

USB3_TX1_P 61
USB3_RX2_N 61
USB3_RX2_P 61
USB3_TX2_N 61

USB3_TX2_P 61

RN2401D
RN2401A
RN2401B
RN2402A
RN2402D
RN2401C
RN2402B
RN2402C

Place within 500 mils of PCH

3

+3VSUS_ORG

USB_OC0# 61

USB_OC1# 61

USB PORT

USB P00

USB P01

USB P02

USB P03

USB P04

USB P05

USB P07

USB P08

USB P09

USB P10

USB P11

USB P12

USB P13

External 2.0/3. 0

External 2.0/3. 0

External 2.0

WiFi

Camera

External 2.0

BT

PCIE/mSATA

+3VSUS

+3VSUS_ORG

+12VS

+1.5VS

2

+3VSUS 4,22,23,27,28,30,33,43,61,81,92

+3VS

+3VS 16,1 7,20,21,22,23,25,26,27,28,30,33,37,38,39,40,41,43,47,48,4 9,53,55,60,63,65,66,91,92

+3V

+3V 37,43,6 3,65,91

+3VSUS_ORG 20,21,22,25,26, 27

+12VS 28, 39,41,63,91

+1.5VS 20,21,22,26,27,41,53,55,63,84

2

1

Title :

Title :

Title :

PCH(5)_PCI,NVRAM,USB

PCH(5)_PCI,NVRAM,USB

PCH(5)_PCI,NVRAM,USB

Wing_Cheng

Wing_Cheng

Wing_Cheng

Engineer:

Engineer:

VA70_HW

VA70_HW

VA70_HW

Engineer:

1

24 96Friday, January 18, 2013

24 96Friday, January 18, 2013

24 96Friday, January 18, 2013

PEGATRON COMPUTER INC

PEGATRON COMPUTER INC

PEGATRON COMPUTER INC

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Rev

Rev

Rev

1.0

1.0

1.0

5

R2561

10KOhm

@

R2558

10KOhm

EXT_SMI#

PCH_GPIO8

PM_LANPHY_EN

PCH_GPIO24

DGPU_HPD_INTR#

PCH_ALERT#

DGPU_PWROK

GPIO69

GPIO1

STP_PCI#

SATA_DET#4

PCH_GPIO0_R

GPIO27

+3VS

12

R2559

10KOhm

12

R2560

10KOhm

@

GND

+3VS

12

R2553

10KOhm

@

PCB_ID0
PCB_ID1
PCB_ID2

12

R2554

10KOhm

@

GND

1 2

R2512 1KOhm

12

R2513 10KOhm

@

12

R2518 10KOhm

@

12

R2520 10KOhm

@

@

12

R2514 10KOhm

12

@

R2515 10KOhm

12

R2519 10KOhm

12

R2502 10KOhm@

12

R2521 10KOhm@

12

R2517 10KOhm

12

R2522 10KOhm

12

R2556 10KOhm

@

12

R2557 10KOhm

@

PCB ID2 PCB_ID1 PCB_ID0
R1.0 TBD 0 0
R1.1 TBD 0 1
R1.2 TBD 1 0
R1.3 TBD 1 1

+3VSUS_ORG

+3VS

+3VSUS_ORG

WLAN_ON53,55

+3VS

D D

C C

B B

R1.2 2012/11/30
PCB_ID R1.2

12

12

GND

RCIN# has pull high at EC side

R1.2 2012/11/29
R2523, eDP_ON# pull-up is removed

4

Reserved
This signal has a weak internal pull-up but requires an
external pull down.

PCH_GPIO8

+3VS +3VS

12

12

R2524

R2525

10KOhm

10KOhm

@

@

34

Q2501B

5

UM6K1N

DGPU_PWROK

PCH_GPIO8_R

@

Q2501A
UM6K1N

@

GND GND

R2532 10KOhm@

R2526 10KOhm@

61

2

12

12

R1.1

1 2

R2534 1KOhm1%

+3VS GND

@

Functional Strap Definitions
Usage: TLS Confidentiality(Intel Crypto Transport Layer Security)
"0" = Disable
"1" = Enable

1 2

R2533 200KOhm1%

+3VS

Functional Strap Definitions

@

Usage: Reserved
This signal has a weak internal pull-down.
NOTES:

1. The internal pull-down is disabled after PLTRST# deasserts.

2. This signal should not be pulled high when strap is sampled

WLAN_ON_R

GND

FDI_OVRVLTG

SATA_ODD_PRSNT#_R

1 2

SP2506 R0402

1 2

R2531 100KOhm

@

SATA_ODD_PWRGT60

3

+3VS

+3VS 16,17,20,21,22,23,26,27,28,30,33,37,38,39,40,41,43,47,48,49,53,55,60,63,65,66,91,92

+3VSUS

+3VSUS 4,22,23,27,28,30,33,43,61,81,92

+VCCDSW

SP2502 R0402

SP2501 R0402

DGPU_PWROK87,92

WLAN_LED66

AOAC_ON55

R1.2 2012/11/08
cost dwon 0ohm

SP2507 R0402

BT_ON_PCH55

1

PCH_ALERT#

PCB_ID2

+VCCDSW 27

+3VSUS_ORG 20,21,22,24,26,27

1 2

1 2

DGPU_PWROK

1 2

SP2505 R0402

1 2

IO Flexible:

GPIO70

GPIO71

GPIO70

GPIO71

+3VSUS_ORG

R1.2 2012/11/28
eDP_ON# is not used
R1.2 2012/11/29
T2505, R2563 are removed, too

PCH_GPIO8_R

WLAN_RST#_PCH53,55

EXT_SMI#30,65

OP_SD#42

SATA_ODD_PRSNT#60

T2504

GPIO change:
CIO_PLUG_EVENT/PCIE_WAKE#/OP_SD#/DDR_VOLT_SEL
PCB_ID2

R1.1

PCH_GPIO0_R

GPIO1

1

DGPU_HPD_INTR#

T2503

PM_LANPHY_EN

HOST_ALERT#1_R

SATA_DET#4

1 2

SP2504 R0402

1 2

SP2503 R0402

1 2

R25520Ohm @

R2527 10KOhm@

R2528 10KOhm@

R2529 10KOhm@

R2530 10KOhm@

GPIO27

WLAN_ON_R

STP_PCI#

SATA_PWR_EN#1_R

SATA_ODD_PRSNT#_R

FDI_OVRVLTG

PCB_ID0

PCB_ID1

CRIT_TEMP_REP#_R

GPIO69

GPIO70

GPIO71

GND

12

12

12

12

PCH_GPIO24

LPT_PCH_M_EDS

U2001F

AT8

BMBUSY#/GPIO0

F13

TACH1/GPIO1

A14

TACH2/GPIO6

G15

TACH3/GPIO7

Y1

GPIO8

K13

LAN_PHY_PWR_CTRL/GP IO12

AB11

GPIO15

AN2

SATA4GP/GPIO16

C14

TACH0/GPIO17

BB4

SCLOCK/GPIO22

Y10

GPIO24

R11

GPIO27

AD11

GPIO28

AN6

GPIO34

AP1

GPIO35/NMI#

AT3

SATA2GP/GPIO36

AK1

SATA3GP/GPIO37

AT7

SLOAD/GPIO38

AM3

SDATAOUT0/GPIO39

AN4

SDATAOUT1/GPIO48

AK3

SATA5GP/GPIO49

U12

GPIO57

C16

TACH4/GPIO68

D13

TACH5/GPIO69

G13

TACH6/GPIO70

H15

TACH7/GPIO71

BE41

VSS25

BE5

VSS24

C45

VSS23

A5

VSS22

DH82LPMS

02V000000012

+3VS

USB3 Port 3 PCIE Port2 Mode (USB3P3_PCIEP2_MODE)
USB3p3_tach6_gp70 pin is a ‘0’, then Root Port 2 is
assigned to USB3 Port 3, else it is assigned to PCI Express.

USB3 Port 2 PCIE Port1 Mode (USB3P2_PCIEP1_MODE)
USB3p2_tach7_gp71 pin is a ‘0’, then Root Port 1is
assigned to USB3 Port 2, else it is assigned to PCI Express.

GND

CPU/Misc

GPIO

PROCPWRGD

THRMTRIP#

PLTRST_PROC#

NCTF

2

TP14 is Intel R eserved Pin: Mu st have a pull up resistor to VCC3_3. Standar d
resistor value in the range of 4.7K to 15K ok (shark bay LPT EDS 486708)

AN10

TP14

AY1

H_PECI_R

PECI

AT6

RCIN#

AV3

AV1

PM_THRMTRIP#

AU4

N10

VSS3

A2

VSS4

A41

VSS13

A43

VSS14

A44

VSS12

B1

VSS11

B2

VSS10

B44

VSS21

B45

VSS9

BA1

VSS1

BC1

VSS2

BD1

VSS8

BD2

VSS6

BD44

VSS7

BD45

VSS5

BE2

VSS20

BE3

VSS19

D1

VSS18

E1

VSS17

E45

VSS16

A4

VSS15

1 2

1 2

GND

GND

need close to EC

R25030Ohm @

1 2

R250443Ohm

R2505390Ohm 1%

R2506 1KOhm1%

12

@

A20GATE 30

H_PECI 4
H_PECI_EC 30

RCIN# 30

H_CPUPWRGD 4

H_THRMTRIP# 4,47

+1.05VS

PCH_PLTRST_CPU# 4

1

A A

GPIO27

5

12

R2535 10KOhm

@

Title :

Title :

Title :

PCH(6)_CPU,GPIO,MISC

PCH(6)_CPU,GPIO,MISC

GND

4

3

2

PEGATRON COMPUTER INC

PEGATRON COMPUTER INC

PEGATRON COMPUTER INC

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

VA70_HW

VA70_HW

VA70_HW

Date: Sheet

Date: Sheet of

Date: Sheet of

1

Engineer:

Engineer:

Engineer:

PCH(6)_CPU,GPIO,MISC

Wing_Cheng

Wing_Cheng

Wing_Cheng

Rev

Rev

Rev

1.0

1.0

1.0

of

25 96Friday, January 18, 2013

25 96Friday, January 18, 2013

25 96Friday, January 18, 2013

5

LPT_PCH_M_EDS

U2001J

AL34

VSS116

AL38

VSS115

AL8

VSS114

AM14

VSS113

D D

C C

AM24
AM26
AM28
AM30
AM32
AM16
AN36
AN40
AN42

AP13
AP24
AP31
AP43

AK16
AT10
AT15
AT17
AT20
AT26
AT29
AT36
AT38

AV13
AV22
AV24
AV31
AV33
BB25
AV40

AY10
AY15
AY20
AY26
AY29

VSS112
VSS111
VSS91
VSS90
VSS110
VSS118
VSS89
VSS88
VSS117

AN8

VSS109
VSS108
VSS87
VSS107
VSS86

AR2

VSS85
VSS84
VSS83
VSS82
VSS37
VSS36
VSS35
VSS38
VSS34
VSS80

D42

VSS33
VSS32
VSS119
VSS39
VSS28
VSS31
VSS29
VSS30

AV6

VSS106

AW2

VSS105

F43

VSS81
VSS104
VSS103
VSS102
VSS101
VSS100

AY7

VSS99

B11

VSS98

B15

VSS97

VSS96
VSS95
VSS94
VSS93
VSS92
VSS40
VSS42
VSS41
VSS43
VSS45
VSS44
VSS48
VSS47
VSS46
VSS49
VSS50
VSS53
VSS52
VSS51
VSS55
VSS54
VSS56
VSS58
VSS57
VSS60
VSS59
VSS61
VSS62
VSS63
VSS65
VSS64
VSS66
VSS67
VSS68
VSS71
VSS70
VSS69
VSS73
VSS72
VSS74
VSS76
VSS75
VSS78
VSS77
VSS79

K39
L2
L44
M17
M22
N12
N35
N39
N6
P22
P24
P26
P28
P30
P32
R12
R14
R16
R2
R34
R38
R44
R8
T43
U10
U16
U28
U34
U38
U42
U6
V14
V16
V26
V43
W2
W44
Y14
Y16
Y24
Y28
Y34
Y36
Y40
Y8

+V1.05VS_PCH_VCC

10UF/10V

1 2

C2612 1UF/6.3V

GND

+V1.05VM_VCCASW

DCPSUS1，DCPSUS2(27頁)，DCPSUS3:
If INTVRMEN is strapped high then power to this well is supplied internally
and this pin should be left as no connect.
If INTVRMEN is strapped low then power to this well must be supplied by an
external 1.05 V suspend rail.
Note: External VR mode applies to Mobile Only.
(shark bay GaryReff schematic 481356)

C2616

12

12

C2603
22UF/6.3V

4

R2601 5.1Ohm

12

12

C2614

C2615

1UF/6.3V

1UF/6.3V

GNDGND GND GND

1 2

12

12

C2604

C2605

1UF/6.3V

1UF/6.3V

GNDGNDGND

1.31A

12

C2601
1UF/6.3V

+PCH_VCCDSW

0.67A

AA24
AA26
AD20
AD22
AD24
AD26
AD28
AE18
AE20
AE22
AE24
AE26
AG18
AG20
AG22
AG24

AA18

Y26

U14

U18
U20
U22
U24
V18
V20
V22
V24
Y18
Y20
Y22

U2001G

VCC7
VCC8
VCC9
VCC11
VCC10
VCC12
VCC13
VCC1
VCC17
VCC2
VCC16
VCC15
VCC14
VCC6
VCC5
VCC4
VCC3

DCPSUSBYP
VCCASW12
VCCASW11
VCCASW1
VCCASW2
VCCASW3
VCCASW9
VCCASW10
VCCASW4
VCCASW5
VCCASW6
VCCASW7
VCCASW8

3

LPT_PCH_M_EDS

2

+VCCA_DAC_1_2

12

12

C2620

0.1UF/16V

C2606

1UF/6.3V

GND

@

12

C2623 10UF/10V@

C2617

0.1UF/16V

GND

12

C2621
10UF/10V

GNDGND

+V3.3S_ADACBG

1 2

12

C2608

1UF/6.3V

0Ohm

1 2

R2602

NB_R0402_20MIL_SMALL

1 2

SP2617

NB_R0402_20MIL_SMALL

1 2

SP2616

12

1UF/6.3V

C2607

C2619

0.01UF/50V

P45

P43

M31

BB44

AN34

AN35

R30
R32

Y12

AJ30
AJ32

AJ26
AJ28
AK20
AK26
AK28

BE22

AK18

AN11

AK22

AM18
AM20
AM22
AP22
AR22
AT22

70mA

13mA

+3VS_VCC_GIO

1

1

+V1.5S_VCCAPLL_FDI

+V1.05S_VCC_EXP

T2601

T2602

+V1.05S_VCC_EXP
+VCCAPLL_USB3

+VCCAPLL_EXP

C2610 10UF/10V

+VCCAPLL_SATA3

VCCADAC1_5

CRT DAC

FDI

HVCMOS

Core

USB3

PCIe/DMI

SATA

VCCMPHY

VSS26

VCCADACBG3_3

VCCVRM2

VCCIO1

VCCIO2

VCC3_3_R30
VCC3_3_R32

DCPSUS1

VCCSUS3_3_1
VCCSUS3_3_2

DCPSUS3_1
DCPSUS3_2

VCCIO3
VCCVRM3
VCCVRM4

VCCVRM5

VCCIO4

VCCVRM1

VCCIO9

VCCIO11
VCCIO10

VCCIO5

VCCIO6

VCCIO7

VCCIO8

GND

1UF/6.3V

1 2

C2609

GND

12

GND

@

12

C2611
10UF/10V

GND

B2601

21

1kOhm/100Mhz

R2603 0Ohm

1 2

NB_R0402_20MIL_SMALL

GND

1 2

SP2613

12

12

C2622

C2613

10UF/10V

1UF/6.3V

+3VSUS_ORG

+3VSUS_VCCPSUS

+1.5VS

1UF/6.3V

+1.5VS

R1.2 2012/12/03
cost dwon 0ohm
R1.2 2012/12/04
change short pin size

+1.5VS

+3VS

R1.2 2012/12/03
cost dwon 0ohm

+1.5VS

12

SP2614

12

C2618

0.1UF/16V

GND

12

C2602

GND

1

R1.2 2012/11/27
follow intel design guide
R1.2 2012/11/28
R2611 is removed
R1.2 2012/12/06
remove R2612, R2610 for GDDR5

R1.2 2012/12/19
option changed to N/A

+VTT_PCH_VCCIO

R1.2 2012/12/04
change short pin size

R1.2 2012/12/17
R2606 is removed

NB_R0402_20MIL_SMALL

1 2

SP2615

@

+3VS

R1.2 2012/12/03
cost dwon 0ohm

R1.2 2012/12/04
change short pin size

+1.5VS

NB_R0402_20MIL_SMALL

1 2

R1.2 2012/12/03
cost dwon 0ohm

R1.2 2012/12/04
change short pin size

GND

DH82LPMS

02V000000012

B B

A A

5

GND

DH82LPMS

02V000000012

+1.05VS +V1.05VS_PCH_VCC

JP2601

112

2MM_OPEN_5MIL

JP2602

2

2MM_OPEN_5MIL

JP2603

112

2MM_OPEN_5MIL

4

1.29A

2

+V1.05VM_VCCASW

0.67A

112

+VTT_PCH_VCCIO

3.629A

2

3

+V1.05VM_VCCASW

+VTT_PCH_VCCIO

+1.05VS

+1.5VS

+3VSUS_VCCPSUS

+V1.05VM_VCCASW 27

+VTT_PCH_VCCIO 27

+1.05VS 4,25,27,47,63,80, 82

+1.5VS 20,21,22,24,27,41,53,55,63,84

+3VS

+3VS 16,17,20,21,22,23,25,27,28,30,33,37,38,39,40,41,43,47,48,49,53,55,60,63,65,66, 91,92

+3VSUS_VCCPSUS 27

2

Title :

Title :

Title :

PCH(7)_POWER,GND

PCH(7)_POWER,GND

PCH(7)_POWER,GND

Wing_Cheng

Wing_Cheng

Engineer:

Engineer:

VA70_HW

VA70_HW

VA70_HW

Engineer:

BG1\CORE

BG1\CORE

BG1\CORE

Size Project Name

Size Project Name

Size Project Name

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Wing_Cheng

26 96Friday , January 18, 2013

26 96Friday , January 18, 2013

26 96Friday , January 18, 2013

1

Rev

Rev

Rev

1.1

1.1

1.1

5

LPT_PCH_M_EDS

U2001K

AA16

VSS136

AA20

VSS197

AA22

VSS196

AA28

VSS195

AA4

VSS194

AB12

VSS193

AB34

VSS192

AB38

VSS146

AB8

VSS128

AC2

D D

C C

B B

VSS145

AC44

VSS191

AD14

VSS190

AD16

VSS189

AD18

VSS204

AD30

VSS203

AD32

VSS202

AD40

VSS209

AD6

VSS208

AD8

VSS188

AE16

VSS187

AE28

VSS186

AF38

VSS185

AF8

VSS184

AG16

VSS183

AG2

VSS201

AG26

VSS200

AG28

VSS199

AG44

VSS198

AJ16

VSS182

AJ18

VSS148

AJ20

VSS147

AJ22

VSS150

AJ24

VSS149

AJ34

VSS181

AJ38

VSS180

AJ6

VSS179

AJ8

VSS178

AK14

VSS177

AK24

VSS176

AK43

VSS175

AK45

VSS174

AL12

VSS173

AL2

VSS172

BC22

VSS206

BB42

VSS205

DH82LPMS

02V000000012

GND

B19

VSS171

B23

VSS170

B27

VSS169

B31

VSS168

B35

VSS167

B39

VSS166

B7

VSS165

BA40

VSS164

BD11

VSS163

BD15

VSS162

BD19

VSS161

AY36

VSS160

AT43

VSS159

BD31

VSS129

BD35

VSS130

BD39

VSS131

BD7

VSS132

D25

VSS144

AV7

VSS133

F15

VSS143

F20

VSS134

F29

VSS142

F33

VSS135

BC16

VSS121

D4

VSS120

G2

VSS122

G38

VSS123

G44

VSS124

G8

VSS125

H10

VSS126

H13

VSS127

H17

VSS139

H22

VSS140

H24

VSS141

H26

VSS138

H31

VSS158

H36

VSS137

H40

VSS157

H7

VSS156

K10

VSS155

K15

VSS154

K20

VSS153

K29

VSS152

K33

VSS151

BC28

VSS207

R1.2 2012/12/03
cost dwon 0ohm
R1.2 2012/12/04
change short pin size

+1.05VS

NB_R0402_20MIL_SMALL

1 2

SP2713

+3VS

NB_R0402_20MIL_SMALL

1 2

SP2716

+1.05VS

NB_R0402_20MIL_SMALL

1 2

SP2719

+1.5VS

GND

R2726 0Ohm

+1.05VS

R1.2 2012/12/03
cost dwon 0ohm

R1.2 2012/12/04
change short pin size

NB_R0402_20MIL_SMALL

1 2

SP2711

10UF/10V

+1.05VS_VCC_SSCFF

12

C2718
1UF/6.3V

GND

+3VS_VCC_FLEX23

12

C2721
1UF/6.3V

GND

+1.05VS_VCCCLKF100

12

C2724
1UF/6.3V

1 2

C2703

0.1UF/16V

C2715

+1.05VS

+3VSUS_ORG

12

GND

+3VS

SP2714

+3VS

SP2717

SP2720

+VTT_PCH_VCCIO
GND

+VCCAXCK_VRM

+1.05VS

R1.2 2012/12/03
cost dwon 0ohm

R1.2 2012/12/04
change short pin size

4

SP2708

R1.2 2012/12/03
cost dwon 0ohm

R1.2 2012/12/04
change short pin size

12

SP2709

+3VS

SP2710

NB_R0402_20MIL_SMALL

1 2

SP2712

NB_R0402_20MIL_SMALL

1 2

+3VS_VCC_FLEX0

GND

NB_R0402_20MIL_SMALL

1 2

+3VS_VCC_ASEPCI

GND

NB_R0402_20MIL_SMALL

1 2

+1.05VS_VCCSSCF100

NB_R0402_20MIL_SMALL

1 2

12

12

12

+3VSUS_VCCPUSB

R1.2 2012/12/03
cost dwon 0ohm
R1.2 2012/12/04
change short pin size

NB_R0402_20MIL_SMALL

1 2

C2714 0.1UF/16V

NB_R0402_20MIL_SMALL

1 2

12

12

C2716

@

10UF/10V

GND

+3VS

C2719
1UF/6.3V

+1.05VS

C2722
1UF/6.3V

C2725
1UF/6.3V

C2702

0.1UF/16V

1 2

+1.05VS_VCCUSBCORE

1 2

C2730 0.1UF/16V

+1.05VS_VCC_AXCK_DCB

C2717
1UF/6.3V

NB_R0402_20MIL_SMALL

1 2

SP2715

NB_R0402_20MIL_SMALL

1 2

SP2718

12

GND

GND

+1.05VS_VCCAUSB

+3VS_VCCAUBG

GND

GND

T2701

+1.05VS_VCC_SSCFF

+3VS_VCC_FLEX0

+3VS_VCC_FLEX1

+3VS_VCC_FLEX23

+3VS_VCC_ASEPCI

+VCCCLKF135

+1.05VS_VCC_SSCFF

+1.05VS_VCCCLKF100

+1.05VS_VCCSSCF100

+1.05VS_VCCCLKF100

+1.05VS_VCCSSCF100

+3VS_VCC_FLEX1

12

C2720
1UF/6.3V

GND

+VCCCLKF135

12

C2723
1UF/6.3V

GND

3

U2001H

R24

VCCSUS3_3_9

R26

VCCSUS3_3_3

R28

VCCSUS3_3_4

U26

VCCSUS3_3_5

M24

VSS27

U35

VCCUSBPLL

L24

VCC3_3_1

U30

VCCIO12

V28

VCCIO14

V30

VCCIO13

Y30

VCCIO16

1

Y35

DCPSUS2

AF34

VCCVRM7

AP45

VCC20

Y32

VCCCLK1

M29

VCCCLK3_3_1

L29

VCCCLK3_3_2

L26

VCCCLK3_3_3

M26

VCCCLK3_3_4

U32

VCCCLK3_3_5

V32

VCCCLK3_3_6

AD34

VCCCLK2

AA30

VCCCLK3

AA32

VCCCLK4

AD35

VCCCLK5

AG30

VCCCLK6

AG32

VCCCLK7

AD36

VCCCLK8

AE30

VCCCLK9

AE32

VCCCLK10

DH82LPMS

02V000000012

LPT_PCH_M_EDS

USB

20mA

VCCSUS3_3_6

Azalia

CPU

SPI

GND

12

C2728
1UF/6.3V

VCCSUS3_3_7

VCCDSW3_3

VCCSUSHDA

VCCSUS3_3_8

V_PROC_IO_1
V_PROC_IO_2

+3VM_VCCPSPI

GPIO/LPC

RTC

ICC

Fuse

Thermal

+3VSUS_VCCPSUS

R20
R22

A16

AA14

DCPSST

AE14

VCC3_3_2

AF12

VCC3_3_3

AG14

VCC3_3_4

U36

VCCIO15

A26

K8

A6

VCCRTC

P14

DCPRTC1

P16

DCPRTC2

AJ12
AJ14

AD12

VCCSPI

P18

VCC18

P20

VCC19

L17

VCCASW13

R18

VCCASW14

AW40

VCCVRM6

AK30

VCC3_3_5

AK32

VCC3_3_6

R2701 0Ohm@

R2702 0Ohm

+3VS_VCCPCORE

+V1.05S_VCCAUX

+3VSUS_VCCPAZSUS

+VCCPRTCSUS

+VCCRTCEXT

+1.05VS_VCCPCPU

+3VM_VCCPSPI

+3VS_VCCPFUSE

PCH_VCC_1_1_20

PCH_VCC_1_1_21

+V1.5S_VCCATS

12

12

+VCCDSW

+VCCSST

+3VS_VCCPTS

+3VS

+3VM_SPI

NB_R0402_20MIL_SMALL

1 2

SP2703

SP2704

12

GND

12

C2709

0.1UF/16V

12

C2711

0.1UF/16V

GND

2

1 2

C27050.1UF/16V

+VTT_PCH_VCCIO

+3VSUS_ORG

NB_R0402_20MIL_SMALL

1 2

R1.2 2012/12/03
cost dwon 0ohm

C2706

0.1UF/16V
C2712

0.1UF/16V

12

C2710

0.1UF/16V

NB_R0402_20MIL_SMALL

1 2

SP2705

NB_R0402_20MIL_SMALL

1 2

SP2706

NB_R0402_20MIL_SMALL

1 2

SP2707

NB_R0402_20MIL_SMALL

1 2

SP2721

R1.2 2012/12/03
cost dwon 0ohm

R1.2 2012/12/04
change short pin size

+VCCPRTCSUS

GND

NB_R0402_20MIL_SMALL

1 2

SP2702

12

C2701

0.01UF/50V

GND

R1.2 2012/12/04
change short pin size

12

12

12

C2731

C2713

1UF/6.3V

0.1UF/16V

GND

12

C2727
1UF/6.3V

GND

+V1.05VM_VCCASW

+V1.05VM_VCCASW

+1.5VS

R1.2 2012/12/03
cost dwon 0ohm

R1.2 2012/12/04
change short pin size

+3VS

12

C2726
1UF/6.3V

GND

+VCCDSW

NB_R0402_20MIL_SMALL

1 2

SP2701

R1.2 2012/12/03
cost dwon 0ohm

R1.2 2012/12/04
change short pin size

1 2

0Ohm

1 2

@

Unstuff R2731, stuff R2732

Intel MOW WW09: renamed
VCCIO2PCH to RSVD

R2719 0Ohm

R2718 0Ohm

+3VS

R2732

R27330Ohm

1 2

@

1 2

R1.2 2012/12/04
change short pin size

C2704

0.1UF/16V

+VCC_RTC

+1.05VS

+VCCIO2PCH

+3VSUS_ORG

12

GND

R1.1

+3VSUS_ORG

1

12

C2708

0.1UF/16V

GND

GND

+3VA

12

C2729
1UF/6.3V

R2720
0Ohm

+1.05VS

1 2

R2734
0Ohm

+3VS

1 2

@

GND

A A

5

GND

+3VSUS

JP2702

2

1MM_OPEN_M1M2

4

3

+3VSUS_ORG

261mA

112

+V1.05VM_VCCASW

+3VSUS

+3VSUS_ORG

+1.05VS

+VTT_PCH_VCCIO

+VCCAXCK_VRM

+3VSUS_VCCPSUS

+3VA

+VCC_RTC

+VCCIO2PCH

2

+V1.05VM_VCCASW 26

+3VSUS 4,22,23,28,30, 33,43,61,81,92

+3VSUS_ORG 20, 21,22,24,25,26

+1.5VS

+1.5VS 20,21,22,24,26, 41,53,55,63,84

+3VS

+3VS 16,17,20,21,22,23,25,26,28,30,33,37, 38,39,40,41,43,47,48,49,53,55,60,63,65,66,91,92

+1.05VS 4,25,26,47,63, 80,82

+VTT_PCH_VCCIO 26

+VCCAXCK_VRM 21

+3VSUS_VCCPSUS 26

+3VA 20,30,63,65,81,88,93

+VCC_RTC 20,22

+VCCIO2PCH 6

Title :

Title :

Title :

PCH(8)_POWER,GND

PCH(8)_POWER,GND

PCH(8)_POWER,GND

Wing_Cheng

Wing_Cheng

Wing_Cheng

Engineer:

Engineer:

VA70_HW

VA70_HW

VA70_HW

1

Engineer:

27 96Friday, January 18, 2013

27 96Friday, January 18, 2013

27 96Friday, January 18, 2013

PEGATRON COMPUTER INC

PEGATRON COMPUTER INC

PEGATRON COMPUTER INC

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Rev

Rev

Rev

1.0

1.0

1.0

5

PCH SPI ROM

@

+3VA_EC

D D

C C

+3VSUS

R2802 0Ohm

R2803 0Ohm

PCH_SPICS0#21
PCH_SPISO21,30

PCH_SPICS1#21,30

12

12

R2801 0Ohm

+3VM_SPI

PCH_SPICS0#

SPI_WP_IO221,30

PCH_SPISO

PCH_SPICS1#

+3VM_SPI

D2801

1

3

2

@

1V/0.2A

12

R1.2 2012/11/29
reserved for intel design guide

R2822
1KOhm

@

1 2

1 2

R28040Ohm

1 2

R280533Ohm

1 2

R280633Ohm

1 2

R28170Ohm

1 2

R281633Ohm

1 2

R281833Ohm

@
@
@

@

+3VM_SPI

R2807
1KOhm

1 2

SPI1_CS#0
SPI1_SO
+3VM_SPI1_WP#

+3VM_SPI

R2821
1KOhm

1 2

@

SPI2_CS#1
SPI2_SO

+3VM_SPI2_WP# SPI2_CLK

4

R1.2 2012/11/28
follow intel design guide

U2801

1

CS#

2

SO/SIO1

3

WP#/SIO2

4

GND

MX25L1675EM2I-10G

05V000000023

R1.2 2012/11/28
follow intel design guide

U2802

1

CS#

2

DO(IO1)

3

WP#(IO2)

4

GND

W25Q32FVSSIQ

05V000000022
@

VCC

NC/SIO3

SCLK

SI/SIO0

(16Mb)

HOLD#/RESET#(IO3)

(32Mb)

C2802

0.1UF/16V

8
7
6
5

VCC

CLK

DI(IO0)

12

SPI1_HOLD#
SPI1_CLK
SPI1_SI

0.1UF/16V

8
7
6
5

+3VM_SPI

C2801

R1.2 2012/11/28
follow intel design guide

R2808
1KOhm

1 2

+3VM_SPI

12

@

SPI2_HOLD#

SPI2_SI

R2811 33Ohm
R2809 33Ohm
R2810 33Ohm

R1.2 2012/11/28
follow intel design guide

R2815
1KOhm

1 2

@

R2814 33Ohm
R2812 33Ohm
R2813 33Ohm

3

1 2
1 2
1 2

1 2
1 2
1 2

@
@
@

+3VM_SPI

R1.2 2012/11/29
reserved for intel design guide

R2823
1KOhm

@

1 2

SPI_HOLD#_IO3 21,30

PCH_SPICLK 21,30

PCH_SPISI 21,30

R1.0 0106

2

+3VS

+3VS 16,17,20,21,22,23,25,26,27,30,33,37,38,39,40,41,43,47,48,49,53,55,60,63,65,66, 91,92

+12VS 39,41,63,91

+12VSUS 22,33, 55,60,81,91

+3VM_SPI 27

+3VSUS 4,22,23,27,30,33, 43,61,81,92

+12VSUS

+3VM_SPI

+3VSUS

+12VS

PCH EC

ROM setting:
Configuration 1. ITE HSPI -> short J2803 pin2 & 3
and no stuff U2801,U2802
Configuration 2. One ROM solution -> short J2803 pin1&2
and no stuff U2802 ; stuff U2801(BIOS+ME)
Configuration 3. Two ROM solution -> short J2803 pin1&2 , J2802 pin2&3
Stuff U2801(ME), Stuff U2802(BIOS)

Follow Intel setting:
U2801: ME
U2802: BIOS

1

<6.5 inch <6.5 inch

SPI ROM
(32Mb)

SPI ROM
(128 Kb)

+12VS

5

R2820 0Ohm

R2819 0Ohm

34

1 2

@

1 2

+3VS

SMBUS Link device

eDP
WLAN

34

12

RN2801A

4.7KOHM

RN2801B

4.7KOHM

CPU XDP
PCH XDP

+3VS

SMB_CLK_S 16,17,48,53,55

SMB_DAT_S 16,17,48,53,55

+12VSUS

+12VS

SML1_CLK 21

PCH

SML1_DAT 21

SCL_VGA 30,49,74

SDA_VGA 30,49,74

2

+3VS

ANX6211

Title :

Title :

Title :

PCH(9)_SPI,SMB

PCH(9)_SPI,SMB

PCH(9)_SPI,SMB

Wing_Cheng

Wing_Cheng

Engineer:

Engineer:

VA70_HW

VA70_HW

VA70_HW

Engineer:

1

PEGATRON COMPUTER INC

PEGATRON COMPUTER INC

PEGATRON COMPUTER INC

Size Project Name

Size Project Name

Size Project Name

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Wing_Cheng

28 96Friday , January 18, 2013

28 96Friday , January 18, 2013

28 96Friday , January 18, 2013

Rev

Rev

Rev

1.0

1.0

1.0

SPI Debug Connector

B B

A A

5

4

PCH SMBus

EC, VGA Thermal

+3VSUS

SCL_3A21

PCH

SDA_3A21

+3VS +3VSUS

SMB1_CLK30,49,74

SMB1_DAT30,49,74

3

2

6 1

Q2801A

UM6K1N

3 4

Q2801B

UM6K1N

2

Q2802A

UM6K1N

61

5

Q2802B

UM6K1N

R1.2 2012/10/29
option changed from /non_FDI_@

R1.2 2012/11/28
R2822, R2823 are removed

5

D D

C C

4

3

2

1

B B

A A

Title :

Title :

Title :

CLK_ICS9LRS3197

CLK_ICS9LRS3197

CLK_ICS9LRS3197

Wing_Cheng

Wing_Cheng

Engineer:

Engineer:

VA70_HW

VA70_HW

VA70_HW

Engineer:

PEGATRON COMPUTER INC

PEGATRON COMPUTER INC

PEGATRON COMPUTER INC

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

5

4

3

Date: Sheet of

2

Wing_Cheng

1

Rev

Rev

Rev

1.0

1.0

29 96Friday, January 18, 2013

29 96Friday, January 18, 2013

29 96Friday, January 18, 2013

1.0

5

D D

+3VA_EC

C C

R1.2 2012/11/06

工工工工工工

B B

RF_ON55

Q3001B
UM6K1N

+3VS_WLAN

+3VS_WLAN

12

12

R3040
10KOhm

34

5

61

Q3001A
UM6K1N

GND GND

12

R3035 0Ohm

@

R1.2 2012/11/06

工工工工工工

H_PECI_EC25

T3012

USBCHG_EN81

R3041
10KOhm

PCH_FLASH_DESCRIPTOR20

2

RF_ON_R

Thermal sensor

H_PECI_EC

1

SPI_HOLD#_IO321,28

R1.2 2012/11/08
cost dwon 0ohm
R1.2 2012/11/28
change back to 0ohm
R1.2 2012/12/06
R3042, R3044 are replaced by SP3008, SP3012
R1.2 2012/12/17
SP3008, SP3012 replaced by 0ohm

CLK_KBCPCI_PCH21

ME_SUSPWRDNACK22

WLAN_RST#_EC55

PM_PWRBTN#22

Battery

12

C3011

10PF/50V

@

SPI_WP_IO221,28

PCH_FLASH_DESCRIPTOR

LPC_AD021,43,65
LPC_AD121,43,65
LPC_AD221,43,65
LPC_AD321,43,65

LPC_FRAME#21,43,65

BUF_PLT_RST#23,33,40,43,47,53,55,70

INT_SERIRQ21,43,65

EXT_SMI#25,65
EXT_SCI#20

A20GATE25

RCIN#25

EC_RST#47

1

T3013

KSI048
KSI148
KSI248
KSI348
KSI448
KSI548
KSI648

KSI748
KSO048
KSO148

KSO248
KSO348
KSO448
KSO548
KSO648
KSO748
KSO848
KSO948
KSO1048
KSO1148
KSO1248
KSO1348
KSO1448
KSO1548

THRO_CPU4

BAT_LEARN88

TP_CLK48

TP_DAT48

SMB0_CLK63,88
SMB0_DAT63,88
SMB1_CLK28,49,74
SMB1_DAT28,49,74

LCD_BACKOFF#37

CTL_FAN49
FB_CLAMP71,74,84

IOAC_EN55,81

1 2

R3044 0Ohm

1 2

R3042 0Ohm

SCLCDP_EC61

R1.2 2012/11/08
cost dwon 0ohm
R1.2 2012/12/04
remove R3016

Share ROM

A A

R1.2 2012/11/08
cost dwon 0ohm
R1.2 2012/11/28
change back to 0ohm

FDIO2

5

12

R3069 0Ohm

R3029 15Ohm

1 2

R3072

0Ohm

+3VA_EC_SPI

R3071
1KOhm

1 2

ROM_WP#_S

SCE#_SSCE#

SO_SSO

R1.2 2012/11/28
follow Intel design guide

CS#
DO(IO1)
WP#(IO2)
GND

HOLD#/RESET#(IO3)

DI(IO0)

(32Mb)

0.1UF/16V

VCC

CLK

U3003

1
2
3
4

W25Q32FVSSIQ

05V000000022

need to check ROM P/N

C9201

8
7
6
5

+3VACC

+3VS

7 8

47OHM

5 6

47OHM

3 4

47OHM

1 2

47OHM

1 2

SP3004 R0402

1 2

SP3005 R0402

1 2

SP3006 R0402

1 2

SP3007 R0402

T3009

SPI_HOLD#_IO3_R

1 2

R3079 0Ohm@

SCE#
SCK
SI
SO

+3VA_EC_SPI

R1.2 2012/11/28
follow Intel design guide

12

R3070
1KOhm

1 2

ROM_HD#_S

SCLK_S

SI_S

4

LAD0

RN3004D

LAD1

RN3004C

LAD2

RN3004B

LAD3

RN3004A

1

eDP_ON#_EC

SPI_WP_IO2_R

SCLCDP_EC_R

R1.2 2012/11/08
cost dwon 0ohm
R1.2 2012/11/28
change back to 0ohm

1 2

R3073 0Ohm

R3030 15Ohm

R3067 15Ohm

4

U3001

3

VBAT

127

VSTBY(PLL)

121

VSTBY5

114

VSTBY4

92

VSTBY3

50

VSTBY2

26

VSTBY1

74

AVCC

11

VCC

10

LAD0/GPM0

9

LAD1/GPM1

8

LAD2/GPM2

7

LAD3/GPM3

13

LPCCLK/GPM4

6

LFRAME#/GPM5

22

LPCRST#/GPD2

5

SERIRQ/GPM6

15

ECSMI#/GPD4

23

ECSCI#/GPD3

126

GA20/GPB5

4

KBRST#/GPB6

14

WRST#

58

KSI0/STB#

59

KSI1/AFD#

60

KSI2/INIT#

61

KSI3/SLIN#

62

KSI4

63

KSI5

64

KSI6

65

KSI7

36

KSO0/PD0

37

KSO1/PD1

38

KSO2/PD2

39

KSO3/PD3

40

KSO4/PD4

41

KSO5/PD5

42

KSO6/PD6

43

KSO7/PD7

44

KSO8/ACK#

45

KSO9/BUSY

46

KSO10/PE

51

KSO11/ERR#

52

KSO12/SLCT

53

KSO13

54

KSO14

55

KSO15

119

CRX0/GPC0

123

CTX0/TMA0/GPB2

85

PS2CLK0/TMB0/CE C/GPF0

86

PS2DAT0/TMB1/GPF1

87

PS2CLK1/DTR0#/ GPF2

88

PS2DAT1/RTS0#/GPF3

89

PS2CLK2/GPF4

90

PS2DAT2/GPF5

110

SMCLK0/GPB3

111

SMDAT0/GPB4

115

SMCLK1/GPC1

116

SMDAT1/GPC2

117

SMCLK2/PECI/GPF 6

118

SMDAT2/PECIRQT#/GPF7

81

DAC5/RIG0#/GPJ5

80

DAC4/DCD0#/GPJ4

79

DAC3/TACH1B/GPJ3

78

DAC2/TACH0B/GPJ2

77

HDIO3/GPJ1

76

TACH2/HDIO2/GPJ0

128

CK32K/GPJ6

2

CK32KE/GPJ7

101

FSCE#

105

FSCK

102

FMOSI

103

FMISO

IT8528E/AX

06V380000016

RING#/PWRFAIL#/

PWUREQ#/BBO/SMCL K2ALT/GPC7

FDIO2/DTR1#/SBUSY/G PG1/ID7

CTX1/SOUT1/GPH2/SMDAT3/ID2

FDIO3
SCK
SI

CRX1/SIN1/SMCLK3 /GPH1/ID1

3

+3VA_EC

+3VA_EC 28,47

+3VS

+3VS 16,17,20,21,22,23,25,26,27,28,33,37,38,39,40,41,43,47,48,49,53,55,60,63,65,66,91,92

+3VSUS

+3VSUS 4,22,23,27,28,33,43,61,81,92

+3VA

+3VA 20,27,63,65,81,88,93

R1.2 2012/11/08

R3075 0Ohm

SP3003

1 2

1

T3008

RF_ON_R
FDIO2

1

T3006

FDIO3

1

T3003

1 2

R3056 0Ohm

1 2

R3057 0Ohm

1 2

R3058 0Ohm

1 2

R3059 0Ohm

GND
GND

EC_AGND

cost dwon 0ohm

1 2

SP3013 R0402

1 2

SP3021 R0402

1 2

SP3017 R0402

1 2

SP3018 R0402

1 2

@

R0402

ADC0/GPI0
ADC1/GPI1
ADC2/GPI2
ADC3/GPI3

ADC4/GPI4
ADC5/DCD1#/GPI5
ADC6/DSR1#/GPI6
ADC7/CTS1#/GPI7

PWM0/GPA0
PWM1/GPA1
PWM2/GPA2
PWM3/GPA3
PWM4/GPA4

PWM5/GPA5
PWM6/SSCK/GP A6
PWM7/RIG1#/ GPA7

RXD/SIN0/GPB0

TXD/SOUT0/GPB1

CK32KOUT/LPCRST#/GPB7

KSO16/SMOSI/GPC3

TMRI0/GPC4

KSO17/SMISO/GPC5

TMRI1/GPC6

RI1#/GPD0
RI2#/GPD1

GINT/CTS0#/GPD5

TACH0A/GPD6

TACH1A/TMA1/GPD7

L80HLAT/BAO/GPE0

EGAD/GPE1

EGCS#/GPE2
EGCLK/GPE3

PWRSW/GP E4

RTS1#/GPE5
LPCPD#/GPE6
L80LLAT/GPE7

SSCE1#/FSCE1 #/GPG0

SSCE0#/GPG2

FDIO3/DSR0#/GP G6

CLKRUN#/GPH0/ID0

HSCE#/GPH3/ID3

HSCK/GPH4/ID4
HMISO/GPH5/ID5
HMOSI/GPH6/ID6

VCORE

VSS1

VSS2
VSS3
VSS4
VSS5
VSS6

AVSS

66
67

SUS_PWRGD_R

68

ALL_SYSTEM_PWRGD_R

69

VRM_PWRGD_R

70
71

SLP_SUS#_R

72
73

24
25
28
29
30
31
32
34

108
109
112

56

KSO16

120
57

KSO17

124
16

18
21
33
47

FAN0_TACH

48

19

VSUS_ON_EC

82
83
84
125
35
17
20

LAN_WAKE#

106
107
100
104

93

EN_POC_PWR

94
95
96

HSPI_CS

97

HSPI_CLK

98

HSPI_SO

99

HSPI_SI

R1.2 2012/11/08
cost dwon 0ohm
R1.2 2012/11/28
change to 33ohm for Intel check list
R1.2 2012/12/07
R3056~R3059 are replaced by SP3014, SP3015, SP3019, SP3020
R1.2 2012/12/17
SP3014, SP3015, SP3019, SP3020 are replaced by 0ohm

1

C3008 0.1UF/16V

1 2

12
27
49
91
113
122

75

Cload=12.5PF
place close to EC

non-Share ROM

+3VA_EC_SPI

R3013

3.3KOhm

1 2

U3002

@

SCE# SCE#_nonS
SO SO_nonS ROM_HD#_nonS

12

R3068 0Ohm@
R3031 15Ohm

@

1
2
3

ROM_WP#_nonS SCK_nonS

4

PM25LD010C-SCE

GND

3

SLP_SUS# 22
WLAN_WAKE# 55

CHGCB0 61

USBP2_EN 61

PCH_SPICS1# 21,28
PCH_SPICLK 21,28
PCH_SPISO 21,28
PCH_SPISI 21,28

+3VA_EC +3VA_EC_SPI

1

2

1 2

R3039 0Ohm

8

CE#

VCC

7

SO

HOLD#

6

WP#

SCK

5

SIO

GND

(128KB)

@

AD_IINP 88
SUS_PWRGD 81,92
ALL_SYSTEM_PWRGD 92
VRM_PWRGD 80,92

THERM_ALERT#_EC 74

VR_IMON 80

PWR_BLUE_LED# 65,66
CHG_LED_BLUE# 66
BAT_ORG_LED# 66

PWR_AMBER_LED# 65,66

FB_CLAMP_TGL_REQ# 74

USBP0_EN 61
EC_SPKR 41

LCD_EC_PWM 37

LAN_PWR_ON# 33

BT_ON_EC 55

PM_RSMRST# 22

KSO16 48

AC_IN_OC 74,88,90

KSO17 48

BAT1_IN_OC# 90

ME_AC_PRESENT 22

PM_SUSB# 22

PM_SUSC# 22

PM_PWROK 9,22,92

FAN0_TACH 49
USBP1_EN 61

VSUS_ON 63,81,91,93

SUSC_EC# 63,91
SUSB_EC# 22,23,63,91,92

CPU_VRON 80

PWR_SW#_M 65
RF_DET# 55

LID_SW# 37,65

D3001

@

3

0.8V/0.2mA

07V030000001

+3VA_EC_SPI

R3001

3.3KOhm

1 2

@

T3010

T3011

mSATA_PWR_ON#
LAN_PWR_ON#
AUD_PWR_ON#
CAMERA_PWR_ON#
ODD_PWR_ON#

12

C3010

0.1UF/16V

@

@
@

2

1

1

R301615Ohm
R302315Ohm

AC_IN_OC# 90

M_VREF 83

R3074 0Ohm

+3VA_EC

12

12

C3002

C3001

10UF/10V

0.1UF/16V

GND

SP3001

1 2

R0603

EC_AGND

GND

For PU / PD

+3VA_EC

10KOhm

1 2

R3062

1 2

R3004 47KOhm

1 2

R3025 10KOhm

1 2

RN3001A

3 4

RN3001B

+3VS

7 8

RN3001D

5 6

RN3001C

1 2

R3055 10KOhm

PM_SUSB#
PM_SUSC#

CPU_VRON

PCH_FLASH_DESCRIPTOR

PM_RSMRST#

AC_IN_OC is pulled high at power

VSUS_ON

R3008 100KOHM

+3VSUS

R3053 100KOHM@

+3VA_EC

R3054 10KOhm

SCK

SISI_nonS

2

AC_IN_OC

@

BAT1_IN_OC#

PWR_SW#_M
SMB0_CLK

4.7KOHM

SMB0_DAT

4.7KOHM

4.7KOHM

4.7KOHM

THERM_ALERT#_EC

1 2

R3006 100KOHM

1 2

R3007 100KOHM

1 2

R3009 100KOHM

1 2

R3076 100KOHM

1 2

R3011 10KOhm

1 2

12

1 2

@

VSUS_ON Default Pull High to +3VSUS

BU2/RD3

BU2/RD3

BU2/RD3

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

12

C3003

0.1UF/16V

SMB1_DAT
SMB1_CLK

VSUS_ON

VSUS_ON

VA70_HW

VA70_HW

VA70_HW

+3VA_EC

12

C3004

10UF/10V

+3VS

12

C3006

0.1UF/16V

R1.2 2012/11/08
follow MA50

+3VS

1 2

RN3002A

3 4

RN3002B

3 4

RN3003B

1 2

RN3003A

GND

+3VS

1 2

R3017 10KOhm

1 2

R3018 10KOhm

1 2

R3060 10KOhm

1 2

R3066 10KOhm

+3VA_EC

1 2

R3038 10KOhm

R3061 10KOhm

R3064 10KOhm

R3063 10KOhm

+3VSUS

R3020 10KOhm

R3065 10KOhm @

+5VSUS

R3014 47KOhm

R3027 47KOhm

+5VA

R3015 47KOhm

R3022 47KOhm

Title :

Title :

Title :

ITE8528E

ITE8528E

ITE8528E

Engineer:

Wing_Cheng

Engineer:

Wing_Cheng

Engineer:

Wing_Cheng

30 96Friday, January 18, 2013

30 96Friday, January 18, 2013

30 96Friday, January 18, 2013

L3001

1kOhm/100Mhz

1 2

1 2

4.7KOHM

4.7KOHM

4.7KOHM

4.7KOHM

1 2

1 2

@

1 2

1 2

1 2

@

@

@

@

@

SP3002

R0603

12

12

12

12

1

+3VA_EC+3VA

21

12

C3005

0.1UF/16V

+3VACC

12

C3007

0.1UF/16V

EC_AGND

TP_CLK
TP_DAT
SUSB_EC#
SUSC_EC#

A20GATE

RCIN#

FAN0_TACH

FB_CLAMP_TGL_REQ#

WLAN_WAKE#

IOAC_EN

RF_DET#

RF_DET#

PM_PWRBTN#

LAN_PWR_ON#

PWR_BLUE_LED#

PWR_AMBER_LED#

BAT_ORG_LED#

CHG_LED_BLUE#

Rev

Rev

Rev

1.0

1.0

1.0

1

R1.2 2012/11/06

工工工工工工

T3014

1

T3015

1

T3016

1

R1.2 2012/12/05
R3065 changed to @

R1.2 2012/11/30
cost down

5

4

3

2

1

Close to LAN chip withi n 250mils

PCIE_RXP3_L OM

PCIE_RXN3_LOM

D D

BUF_PLT_RST#

PCIE_WAKE# _LAN

XTALO

C C

12

C3315 0.1UF/10V

C3314 0.1UF/10V

PCIE_TXP3
PCIE_TXN3

CLK_PCIE_LA N
CLK_PCIE_LA N#

+VDD1.2_LAN

12

C3301

0.1UF/10V

Frank
0503 LAN_LPWR is not defined GPIO in PCH .

1 2

R3312 4.7KOhm@

1 2

R3311 4.7KOhm

R3301

1 2

200Ohm

R1.1
change value for -R test repor t

12

VDDC LX

12

C3308

10UF/6.3V

+VDD33_LOM

X3301 25MHZ

1 3

2

4

C3309
15PF/50V

1AV20000000 5

PCIE_RXP3_L AN 24

PCIE_RXN3_LAN 24

PCIE_TXP3_L AN 24
PCIE_TXN3_LAN 24

CLK_PCIE_LA N 21
CLK_PCIE_LA N# 21

L3304

4.7UH

09V03000008 4

Irat=1.2A

XTALIXTALO_R

C3325
15PF/50V

1AV20000000 5

BUF_PLT_RST#23,30,40,43,47,53,55,70

R1.1 IOAC 10/31

4.7UF/6.3V

1

T3301

CLK_REQ4_LAN#21

+VDD33_LOM

SP3301

12

C3302

+VDD1.2_LAN

12

12

C3310

4.7UF/6.3V

R1.2 2012/10/29
pin 46~48 has been connected
together.

LED_BLINKINGn34

LED_LINKn34

R1.2 2012/11/08
cost dwon 0ohm

0Ohm@

12

LAN_LPWR_R

R3308

1 2

SP3302 R0402

PCIE_WAKE# _LAN

VDDC

1 2

12

C3316

0.1UF/10V

+VDD1.2_LAN

SR_VDD

LX
XTALI

NB_R0603_32MIL_ SMALL

C3307

0.1UF/10V

U3301

1

LOW_PWR

2

PERST#

3

CLKREQ#

4

WAKE#

5

MODE

6

VDDC1

7

VREGPNP_CTL

8

SR_VFB

9

SR_VDD

10

SR_VDDP

11

SR_LX

12

XTALI

BCM57780A0KMLG

02V0H0000001

XTALO
XTALVDD

12

12

C3304

0.1UF/10V

+VDD33_LOM

EECLK

49

48

47

46

45

44

GND

EECLK

LINKLED#

SPD100LED#

TRAFFICLED#

SPD1000LED#

XTALO13XTALVDDH14VDDC215PCIE_TXD_N16PCIE_TXD_P17PCIE_PLLVDDL118PCIE_REFCLK_N19PCIE_REFCLK_P20PCIE_PLLVDDL221PCIE_RXD_P22PCIE_RXD_N23GPHY_PLLVDDL

VDDC

+VDD_LANPLL

PCIE_RXN3_LOM

PCIE_RXP3_LOM

0.1UF/10V

EEDAT

43

CLK_PCIE_LAN#

C3305

+3VS

VDDC

VDDO

42

41

VDDO

EEDATA

+VDD_LANPLL

CLK_PCIE_LAN

12

R3303
1KOhm

AVDDL

40

39

38

37

VDDC3

TRD3_P

TRD3_N

AVDDL3

AVDDH2
TRD2_N

TRD2_P

VMAIN_PRSNT

AVDDL2

TRD1_P
TRD1_N
AVDDH1
TRD0_N

TRD0_P
AVDDL1

RDAC

BIASVDDH

24

+VDD_GPHYPLL

PCIE_TXN3

PCIE_TXP3

L_TRDP3 34
L_TRDN3 34

R1.0 chnge VP P/N.

36

AVDDH

35
34
33

AVDDL

32
31
30

AVDDH

29
28
27

AVDDL

26

RDAC

25

BIASVDD

+VDD33_LOM

R3305
1KOhm

1 2

EECLK

@

EEDAT

R3307
1KOhm

1 2

+VDD1.2_LAN

L3301

+VDD_GPHYPLL

12

C3321

C3320

4.7UF/6.3V

0.1UF/10V

+VDD_LANPLL

12

C3322

C3323

0.1UF/10V

4.7UF/6.3V

AVDDL

12

C3317

C3318

4.7UF/6.3V

0.1UF/10V

L_TRDN2 34
L_TRDP2 34

L_TRDP1 34
L_TRDN1 34

L_TRDN0 34
L_TRDP0 34

1 2

R3302

1.24KOhm

10V22000019 8

+VDD33_LOM

12

R3304
1KOhm

1 2

8
7
6
5

AT24C02C-XHM-T

R3306

05V02000000 3

1KOhm

@

1 2

C3303

0.1UF/10V

@

U3302

1

A0

VCC

2

A1

WP

3

A2

SCL

4

GND

SDA

@

AVDDH

C3313

0.1UF/10V

XTALVDD

C3324

0.1UF/10V

BIASVDD

C3319

0.1UF/10V

12

12

12

C3312

0.1UF/10V

21

12

1KOhm/100Mhz

09V01000003 8

+VDD1.2_LAN

L3307

21

1KOhm/100Mhz

12

09V01000003 8

R1.2-26 EMI

12

12

+VDD1.2_LAN

L3306

21

1.5KOhm/100Mhz

09V01000003 9

+VDD33_LOM

L3302

21

1KOhm/100Mhz

09V01000003 8

+VDD33_LOM

L3303

21

1KOhm/100Mhz

09V01000003 8

+VDD33_LOM

L3305

21

1KOhm/100Mhz

09V01000003 8

BG1-HW RD Div.2-NB RD Dept.5

BG1-HW RD Div.2-NB RD Dept.5

BG1-HW RD Div.2-NB RD Dept.5

Size Project Name

Size Project Name

Size Project Name

D

D

D

Date: Sheet of

Date: Sheet of

Date: Sheet of

R1.1 10/31 EMI CHANGE

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

VA70_HW

VA70_HW

VA70_HW

LAN_RTL8411

LAN_RTL8411

LAN_RTL8411

Wing_Cheng

Wing_Cheng

Wing_Cheng

33 9 6Friday, January 18, 2013

33 9 6Friday, January 18, 2013

33 9 6Friday, January 18, 2013

Rev

Rev

Rev

1.0

1.0

1.0

B B

R1.2 2012/10/29

+3VSUS

+12VSUS

3

1

G

2

/TP1_LAN

3

option changed from /ABCT

R3315

1 2

0Ohm

10V44000000 1
@

S

D

3

2

SI2304BDS-T1-G E3

G

1

Q3301

/TP1_LAN

R3314
100KOhm

/TP1_LAN

1 2

D

Q3302

12

2N7002

S

C3355
1UF/25V

1AV30000003 1

/TP1_LAN

R3313
10KOhm

1

G

0Ohm

PCIE_WAKE# _LAN

2

S

R1.1 IOAC 10/31

12

+VDD33_LOM

12

C3306

12

0.1UF/10V

C3311

4.7UF/6.3V

1

R1.1 10/31 EMI CHANGE

L3308

21

1.5KOhm/100Mhz

09V01000003 9

PCIE_WAKE#22,53

3

D

2N7002
Q3303

@

R3309

2

For LAN power control on S5 state

LAN_PWR_ON#30

A A

5

4