Page 1
5
IPX41-D3
D D
Intel Pentium processor
Conroe-L/Conroe/Wolfdate
VGA
C C
B B
A A
PCI Express
X16 SLOT
HDMI
PCI Express
X1 SLOT
Audio
ALC662
USB2.0
8 ports
LAN
Realtek
RTL8111DL
PCI-E X4
PCI-E X16
PCI-E X1
Azalia Link
480Mb/s
e
e
PCI-E X1
P
P
www.schematic-x.blogspot.com
4
Revision:1.02
LGA775
HOST BUS
INTEL
GMCH
EagleLake
DMI Link
INTEL
ICH7
t
t
a
a
g
g
SPI
r
r
SPI
Channel A
Channel B
SATA
o
o
n
n
LPC
3
53.+5V_DUAL53
545554.+3P3V_PCIE&+3P3V_LAN
56
DDR3 DIMM A1
DDR3 DIMM B1
f
f
n
n
o
o
SATA1
SATA2
C
C
SUPER I/O
Fintek F71808EU
PS2 KB/MS
FAN Control
H/W Monitor
i
i
d
d
2
e
e
01
01.Block Diagram
02
02.ECN CONTROL TABLE
03.Power Sequence
03
04.Power Flow
04
05
05.Clock Distribution
06.CLOCK06
07
07.PROCESSOR LGA775 1 - 3
08
08.PROCESSOR LGA775 2 - 3
09
09.PROCESSOR LGA775 3 - 3
10
10.INTEL EAGLELAKE 1 - 7
11
11.INTEL EAGLELAKE 2 - 7
12
12.INTEL EAGLELAKE 3 - 7
13
13.INTEL EAGLELAKE 4 - 7
14
14.INTEL EAGLELAKE 5 - 7
15
15.INTEL EAGLELAKE 6 - 7
16.INTEL EAGLELAKE 7 - 7
16
17.DDR3 CHANNEL A
17
i
i
18
18.DDR3 CHANNEL B
t
t
19
19.DDR3 TERMINATION A&B
20
n
n
20.INTEL ICH7 1 - 4
21
21.INTEL ICH7 2 - 4
22
22.INTEL ICH7 3 - 4
23
23.INTEL ICH7 4 - 4
24
24.PCI EXPRESS X1 SLOT
25
25.PCI EXPRESS X16 SLOT
26
26.INTEGRATED VGA PORT
27.DVI/HDMI CONTROL
27
28.DVI&HDMI / PCIE MUX
28
29.DVI&HDMI LEVEL SHIFTER
29
303230.DVI&HDMI CONNECTOR
31
31.USB CON.
32.USB HEADER CONNECTOR
33
33.SATA CONNECTOR FOR CPC
34
34.Realtek RTL8111DL
35.RJ-45+USB CONNECTOR
35
36.REALTEK ALC662 AZALIA CODEC
36
37.REAR AUDIO CONNECTOR
37
38
38.EMI CAP
39.SUPER I/O - F71808EU
39
40.PS2 KB &MS CONNECTOR FOR CPC
40
41.FAN CIRCUIT
41
42.FRONT PANEL CIRCUIT FOR CPC
42
43.SPI SERIAL FLASH LPC DEGUG
43
44.RTC / CMOS / SPKR/SCREW HOLE
44
45.ATX POWER_24P CONNECTOR
45
46
46.VCORE CONTROLLER
47
47.VCORE DRIVER1
48
48.VCORE DRIVER2
49
49.+1P1V_CORE
50
50.+1P1V_FSB_VTT
51
51.VTT_DDR&3P3VSB SWITCHING&1P5
52
52.+1P5V_DUAL
l
l
a
a
<Variant Name>
<Variant Name>
<Variant Name>
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
IPX41-D3
IPX41-D3
IPX41-D3
1
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
Block Diagram
Block Diagram
Block Diagram
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
1 54Thursday, December 10, 2009
1 54Thursday, December 10, 2009
1 54Thursday, December 10, 2009
1.02
Rev
Rev
Rev
Page 2
5
ECN Control Table
ECN Control Table
ECN Control TableECN Control Table
4
3
2
1
D D
C C
B B
ECN No.
ECN No.
ECN No.ECN No.
DATE
DATE Schematics Revision
DATEDATE
Subject
Subject
SubjectSubject
n
n
C
C
Schematics Revision BOM Part Number
Schematics RevisionSchematics Revision
d
d
i
i
f
f
n
n
o
o
e
e
BOM Part Number PCB
BOM Part NumberBOM Part Number
l
l
a
a
i
i
t
t
n
n
PCBA
PCBA
PCBAPCBA
Revision
Revision
RevisionRevision
PCB
PCBPCB
Revision
Revision
RevisionRevision
o
o
r
r
t
t
a
a
g
g
e
e
P
P
A A
<Variant Name>
<Variant Name>
<Variant Name>
Title :
Title :
Title :
ECN
ECN
ECN
Ttepic Zhu
Ttepic Zhu
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
IPX41-D3
IPX41-D3
IPX41-D3
Engineer:
Ttepic Zhu
2 54Thursday, December 10, 2009
2 54Thursday, December 10, 2009
1
2 54Thursday, December 10, 2009
1.02
1.02
1.02
Rev
Rev
Rev
Page 3
5
A
4
3
PCIRST#
2
1
3.3V
o
o
3.3V
8
PLTRST#
PSON#
7
PWROK
Power
Supply
6
8
n
n
8
f
f
PWROK_PS
PCIRST#_PCIEX16
PCIRST#_PCIEX1
d
d
i
i
/X
e
e
PCI Express X16
9
t
t
n
n
PCI Express X1
9
PCIRST#
3.3V
i
i
3.3V
a
a
l
l
8
GMCH
D D
C C
User press
Reset
button
10
B B
CPURST#
User press
Ctrl+Alt+Del
User press
Power
button
RSTCON#
Default
CPU
User
Clear
CMOS
PWRBTN#
Default
RTCRST#
CPUPWRGD
HINIT#
RTCRST#
1
Vcore
a
a
8
3
Super IO
3.3V
3.3V
RST_KB
RSMRST#
2
3.3V
3.3V
3.3V
3.3V
3.3V
o
o
r
r
t
t
Vcore
5
SLP_S3#
3.3V
ICH7
n
n
RTL8111DL
PWROK
7
5
SLP_S4#
3.3V
PLTRST#
Buffer Out
4
IO_PWRBTN#
3.3V
PLTRST#
C
C
3.3V
PCIRST#
g
g
e
e
P
P
1.02
1.02
1.02
A
Rev
Rev
Rev
<Variant Name>
<Variant Name>
<Variant Name>
Title :
Title :
Title :
Power Sequence
Power Sequence
Power Sequence
Ttepic Zhu
Ttepic Zhu
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
IPX41-D3
IPX41-D3
IPX41-D3
Engineer:
Ttepic Zhu
3 54Thursday, December 10, 2009
3 54Thursday, December 10, 2009
3 54Thursday, December 10, 2009
Page 4
5
A
ATX12V
NCP5392MNR2G
3Phases
D D
ATXPWR
S0
VCORE_EN
I max.=75A.
TDC: 60A.
TDP:65W.(6)
4
VCORE
I max.=75A.
TDC: 60A.
TDP:65W.(6)
3
2
1
+5VSB
C C
+5V
+3VSBSW (S3)
+12V
B B
+3.3V
APM9932CKC
S0/S3/S5
APM9932CKC
S0/S3/S5
AOD452*2
S3/S5:+5VS B
S0/S3
APW7120+AOD452*2
e
e
g
g
+5V_DUAL_USB_R
+5V_DUAL_USB_F
LIN REG,1085
S0/S3/S5
+5V_DUAL
r
r
t
t
a
a
+1P1V_CORE
o
o
Io: 9A
Io: 3A
Io: 3A
+3P3VSB
Switch
APW7120KE_TRL
S0/S1/S3
n
n
Io: 1.5A
o
o
C
C
+1P5V_DUAL
Io
f
f
S0/S1: 12A
n
n
i
i
d
d
VTT_SELEC T
+12V
a
a
i
i
t
t
n
n
e
e
Io: 6.0A
+1P5V_DUAL
LM358 +
FDU8780_F071
S0
AOD472
S0
RT9045GSP +0P75V_VTT_DDR
S0
Io: 1.5A
+1P1V_FSB_VTT
Io: 1.5A
+1P5_ICH
Io
S0:1A
l
l
P
P
NOTE:
Linear REG
Switch REG
<Variant Name>
<Variant Name>
<Variant Name>
Title :
Title :
Title :
Power Flow
Power Flow
Power Flow
Ttepic Zhu
Ttepic Zhu
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
IPX41-D3
IPX41-D3
IPX41-D3
Engineer:
Ttepic Zhu
4 54Thursday, December 10, 2009
4 54Thursday, December 10, 2009
4 54Thursday, December 10, 2009
1.02
1.02
1.02
A
Rev
Rev
Rev
Page 5
5
A
4
3
2
1
200/266/333 MHz
ICS
SLG8XP548T
D D
14.318 MHz
XTAL
C C
200/266/333 MHz
100 MHz
96 MHz
100 MHz
100 MHz
33 MHz
14.318 MHz
CK_FSB_CPU/#
CK_FSB_NB/#
CK_96M_DREF/#
CK_100M_PCIEX16/#100 MHz
CK_100M_ICH/#
CK_100M_SATA/#
CK_48M_USB48 MHz
CK_33M_ICH
CK_14M_ICH
CK_33M_SIO33 MHz
C
C
CPU
MCH
EagleLake
PCIEX16
ICH7
o
o
Super I/O
n
n
f
f
i
i
d
d
e
e
n
n
t
t
i
i
a
a
l
l
n
o
o
n
CK_PCIE_SLOT1/#100 MHz
CK_100M_LAN/#
PCIEX1_1
LAN
<Variant Name>
<Variant Name>
<Variant Name>
Clock Distribution
Clock Distribution
Clock Distribution
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
IPX41-D3
IPX41-D3
IPX41-D3
Engineer:
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
B B
r
r
t
t
a
a
g
g
e
e
P
P
100 MHz
A
Rev
Rev
Rev
1.02
1.02
5 54Thursday, December 10, 2009
5 54Thursday, December 10, 2009
5 54Thursday, December 10, 2009
1.02
Page 6
5
+3P3V
CKL1 600O hm/100Mhz/0.5A
mx_l0603CKL1 600O hm/100Mhz/0.5A
mx_l0603
NI
NI
+3P3VSB
CKL2 600O hm/100Mhz/0.5A
I
D D
C C
B B
A A
I
PCB40
PCB40
PCB
PCB
PCB_BOA RD
PCB_BOA RD
I
I
21
mx_l0603CKL2 600O hm/100Mhz/0.5A
mx_l0603
21
2009.08.04 shawn
Clock gen power change to +3P3VSB for WOL function.
+CLKVCC3
VRMPW RGD_ICH[22]
SMB_CLK _S[17,18,22,2 4,25]
SMB_DAT A_S[17,18,22,2 4,25]
5
+CLKVCC3
12
I
I
CKCB2
CKCB2
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
NOTE:
CKR2 CKR10
2009.08.04 shawn
CKCB19 removed.
12
12
NI
NI
I
I
CKCB11
CKCB11
CKCB12
CKCB12
10UF/6.3V
10UF/6.3V
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
X5R 10%
X5R 10%
mx_c0805
mx_c0805
mx_c0805
mx_c0805
GND GND
GND
GND
2009.08.04 shawn
LR24 0ohm VP removed.
e
e
P
P
12
12
GND
NI
NI
CKC10
CKC10
33PF/50V
33PF/50V
NPO 5%
NPO 5%
GND
NI
NI
CKC11
CKC11
33PF/50V
33PF/50V
NPO 5%
NPO 5%
4
12
12
GND
PIN17 PIN18
25MHz
12
I
I
CKCB13
CKCB13
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
12
NI
NI
CKCB17
CKCB17
4.7UF/6.3 V
4.7UF/6.3 V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
2009.08.04 shawn
LR19 0ohm VP removed.
g
g
12
I
I
CKC8
CKC8
33PF/50V
33PF/50V
NPO 5%
NPO 5%
GND GND GND
I
I
CKCB3
CKCB3
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
GND
1 2
1 2
4
I
I
CKCB4
CKCB4
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
25MHzNI I
12
I
I
CKCB9
CKCB9
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
12
I
I
CKCB14
CKCB14
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
12
I
I
CKCB18
CKCB18
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
a
a
I
I
Y1
Y1
14.318Mh z
14.318Mh z
GND
GND
3
3
12
I
I
CKCB5
CKCB5
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
+CLKVCC3
GND
12
I
I
CKCB15
CKCB15
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GNDGND
VDD48_BW
r
r
t
t
CLK_PW RGD
OSC_CK14 M_XTALIN
OSC_CK14 M_XTALOUT
12
I
I
CKC9
CKC9
33PF/50V
33PF/50V
NPO 5%
NPO 5%
VDDPCI
VDD_PL L3
VDD_SRC
VDDCPU
VDDREF
12
I
I
CKR2
CKR2
10K
10K
VOUT_VDDI O
VDD_IO_9 6
+VDD_IO
12
I
I
CKCB16
CKCB16
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
o
o
GND
12
GNDGND
I
I
CKCB6
CKCB6
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
GND
IIII
IIII
CKU2
CKU2
CKU2
CKU2
CKU2CKU2
CKU2CKU2
2
VDD_PCI
16
VDD_PLL3
31
VDD_SRC
47
VDD_CPU
53
VDD_REF
8
VSS_PCI
23
VSS_SRC1
34
VSS_SRC2
44
VSS_CPU
50
VSS_REF
40
SEL_24.576MHz
12
VDD_I/O_3.3
20
VDD_PLL3_I/O
26
VDD_SRC_I/O1
37
VDD_SRC_I/O2
41
VDD_CPU_I/O
19
VSS_PLL3
15
VSS_I/O
n
n
9
VDD_48
11
VSS_48
48
CKPWRGD/PD#
52
XTAL_IN
51
XTAL_OUT
56
SCL
55
SDA
CLOCK Gen. IN06
CLOCK Gen. IN06
C
C
3
CPU_0
CPU_0#
CPU_1_AMT
CPU_1_AMT#
SRC_8/CPU_ITP
SRC_8#/CPU_ITP#
SRC_7
SRC_7#
SRC_6
SRC_6#
PCI_STOP#/SRC_5
CPU_STOP#SRC_5#
SRC_4
SRC_4#
SRC_3
SRC_3#
SRC_2
SRC_2#
25MHz_0_F
25MHz_1/24.576MHz
SRC_0/DOT_96
SRC_0#/DOT_96#
ITP_EN/PCI_5
PCI_4/SRC_5_EN
PCI_3
PCI_2
PCI_1
PCI_0
o
o
FS_A/48MHz_0
FS_B/TEST_MODE
REF/FS_C/TEST_SEL
3
RCPUHC LK
46
RCPUHC LK#
45
RMCHHCL K
43
RMCHHC LK#
42
39
38
RCK_100M_ ICH
36
RCK_100M _ICH#
35
RCK_10 0M_PE16
33
RCK_100 M_PE16#
32
RCK_100 M_PE1
30
RCK_10 0M_PE1#
29
RCK_100M _MCH
27
RCK_100 M_MCH#
28
RCK_100 M_LAN
24
RCK_10 0M_LAN#
25
RCK_100 M_SATA
21
RCK_100 M_SATA#
22
R_LAN_2 5M
17
18
RCK_96M_ DREF
13
RCK_96M _DREF#
14
PCIF5/ITP_EN(Pin7):
1: CPU_ITP
PCI4/SRC5_EN(Pin6):
1: SRC5 Output
PCI_5
7
CK_33M_P CI4
6
RCK_33M_ SIO
5
RCK_33M _DBG
4
RCK_33M_ ICH
f
n
n
RCK_48M _USB
FSLB
RCK_14M_ ICH
f
Del CK_48_SIO to FS
CK_48M_U SB
3
1
PCI3/CFG0(Pin5):
Strap for SATA PLL
1: PLL2, SS OFF
PCI2/TME(Pin4):
1: SR enable
10
49
54
0
0
0
0
NOBOM
NOBOM
NOBOM
NOBOM
I
I
0
0
0
0
NOBOM
NOBOM
NOBOM
NOBOM
0
0
0
0
NOBOM
NOBOM
NOBOM
NOBOM
0
0
0
0
NOBOM
NOBOM
NOBOM
NOBOM
0
0
0
0
NOBOM
NOBOM
NOBOM
NOBOM
0
0
0
0
NOBOM
NOBOM
NOBOM
NOBOM
0
0
0
0
NOBOM
NOBOM
NOBOM
NOBOM
CKR1 33
CKR1 33
1 2
I
I
0
0
0
0
NOBOM
NOBOM
NOBOM
NOBOM
12
NI
NI
CKR68
CKR68
4.7K
4.7K
i
i
12
NI
NI
CKR64
CKR64
4.7K
4.7K
GND GND GND
+CLKVCC3
12
I
I
CKR67
CKR67
4.7K
4.7K
d
d
12
NI
NI
CKR61
CKR61
4.7K
4.7K
12
NI
NI
CKC12
CKC12
10PF/50V
10PF/50V
NPO 5%
NPO 5%
GND
2
CKR23
CKR23
12
CKR22
CKR22
12
CKR210ICKR210
12
CKR240ICKR240
12
CKR5
CKR5
12
CKR6
CKR6
12
CKR7
CKR7
12
CKR8
CKR8
12
CKR10
CKR10
12
CKR11
CKR11
12
CKR9
CKR9
12
CKR14
CKR14
12
CKR12
CKR12
12
CKR13
CKR13
12
CKR20
CKR20
12
CKR19
CKR19
12
t
CKR25
CKR25
12
CKR26
CKR26
12
12
e
e
I
I
CKR66
CKR66
4.7K
4.7K
12
NI
NI
CKR60
CKR60
4.7K
4.7K
2009.08.04 shawn
Add CKR41 for SIO CK_48M_SIO clock.
CKR40, CKR41 change to 22ohm.
I
I
I
I
CKR39 33
CKR39 33
I
I
NOTE:
Single End damping resistor
Single Load => 33 OHM
Double Load => 22 OHM
2
t
n
n
12
NI
NI
CKC5
CKC5
10PF/50V
10PF/50V
NPO 5%
NPO 5%
GND
CKR41 22 OHM 5%
CKR41 22 OHM 5%
1 2
CKR40 22 OHM 5%
CKR40 22 OHM 5%
1 2
1 2
1
CPUHCLK [7]
CPUHCLK # [7]
MCHHCL K [10]
MCHHCL K# [10]
CK_100M_ ICH [20]
CK_100M_ ICH# [20]
CK_100M _PE16 [25]
CK_100M _PE16# [25]
CK_100M _PE1 [24]
CK_100M _PE1# [24]
CK_100M _MCH [10]
CK_100M_ MCH# [10]
CK_100M _SATA [21]
CK_100M _SATA# [21]
i
i
CK_96M_ DREF [ 13]
CK_96M_ DREF# [13]
l
l
CK_100M _LAN [34]
CK_100M _LAN# [34]
a
a
CK_25M _LAN [34]
1 2
I
1 2
I
1 2
I
1 2
NI
2009.08.13 shawn
CKC6 removed.
AR72 1KIAR72 1K
I
1 2
AR27 1KIAR27 1K
I
1 2
AR28 1KIAR28 1K
I
1 2
PEGATRON DT-MB RESTRICTED SECRET
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
2009.08.04 shawn
CKR1 form NI change to I for LAN 25M clock.
NOTE:
PCIF_5 is dedicated for ICH
PCI4 is for the shortest route
PCI3 is for the longest route
SR5833ISR5833
SR5933ISR5933
SR5733ISR5733
SR6033NISR6033
12
NI
NI
CKC3
CKC3
10PF/50V
10PF/50V
NPO 5%
NPO 5%
GND GND
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
IPX41-D3
IPX41-D3
IPX41-D3
GND
12
NI
NI
CKC4
CKC4
10PF/50V
10PF/50V
NPO 5%
NPO 5%
12
NI
NI
CKC13
CKC13
10PF/50V
10PF/50V
NPO 5%
NPO 5%
1
CK_33M_SI O [39]
CK_33M_T PM [43 ]
CK_33M_IC H [20]
CK_33M_D EBUG [43]
CLOCK CK505
CLOCK CK505
CLOCK CK505
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
FSBSEL0 [ 8,13]
CK_48M_SI O [39]
CK_48M_U SB [20]
FSBSEL1 [ 8,13]
CK_14M_IC H [22]
FSBSEL2 [ 8,13]
6 54Thursday, December 10, 2009
6 54Thursday, December 10, 2009
6 54Thursday, December 10, 2009
Rev
Rev
Rev
1.02
1.02
1.02
Page 7
5
I
I
XU1A
XU1A
SOCKET77 5/ATX
HA#[3..35][10]
HA#3
HA#4
HA#5
HA#6
D D
HREQ#[0..4][10]
HADSTB0#[10]
HT2
HT2
HT7
HT7
NOBOM
NOBOM
NOBOM
NOBOM
C C
B B
A A
NOBOM
NOBOM
NOBOM
NOBOM
HRS#[0..2][10]
CPURES ET#[10]
HA#[3..35][10]
TPC26b
TPC26b
TPC26b
TPC26b
HADSTB1#[10]
TPC26b
TPC26b
TPC26b
TPC26b
CPUHCLK[6]
CPUHCLK #[6]
HT12
HT12
HT13
HT13
1
1
1
1
5
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15 CPU_TP _AD3
HA#16
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
CPU_TP_ N4
CPU_TP_ P5
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HA#32
HA#33
HA#34
HA#35
CPU_TP _AC4
CPU_TP _AE4
HRS#2
HRS#1
HRS#0
+VTT_O UT_R
12
I
I
HR13
HR13
62
62
12
NI
NI
HC1
HC1
22PF/50V
22PF/50V
NPO 5%
NPO 5%
GND
SOCKET77 5/ATX
L5
A03#
P6
A04#
M5
A05#
L4
A06#
M4
A07#
R4
A08#
T5
A09#
U6
A10#
T4
A11#
U5
A12#
U4
A13#
V5
A14#
V4
A15#
W5
A16#
K4
REQ0#
J5
REQ1#
M6
REQ2#
K6
REQ3#
J6
REQ4#
R6
ADSTB0#
N4
RSVD1
P5
RSVD2
AB6
A17#
W6
A18#
Y6
A19#
Y4
A20#
AA4
A21#
AD6
A22#
AA5
A23#
AB5
A24#
AC5
A25#
AB4
A26#
AF5
A27#
AF4
A28#
AG6
A29#
AG4
A30#
AG5
A31#
AH4
A32#
AH5
A33#
AJ5
A34#
AJ6
A35#
AD5
ADSTB1#
AC4
RSVD3
AE4
RSVD4
A3
RS2#
F5
RS1#
B3
RS0#
F28
BCLK0
G28
BCLK1
G23
RESET#
P
P
REV=1.3
REV=1.3
e
e
ADS#
BNR#
HIT#
RSP#
BPRI#
DBSY#
DRDY#
HITM#
IERR#
INIT#
LOCK#
TRDY#
BINIT#
DEFER#
MCERR#
AP0#
AP1#
DP0#
DP1#
DP2#
DP3#
BR0#
GTLREF1
GTLREF0
GTLREF2
GTLREF3
g
g
FC10
FC15
4
+1P1V_FS B_VTT
12
I
I
HR1
HR1
62
62
D2
C2
D4
CPU_TP_ H4
H4
G8
B2
C1
E4
HIERR#
AB2
P3
C3
E3
AD3
G7
CPU_TP _AB3
AB3
CPU_TP_ U2
U2
CPU_TP_ U3
U3
CPU_TP_J 16
J16
CPU_TP _H15
H15
CPU_TP _H16
H16
CPU_TP_J 17
J17
F3
H2
CPU_GTL REF0
H1
1 2
F2
G10
a
a
CPU_MC H_GTLREF
E24
CPU_GTL REF_SEL
H29
12
NI
NI
HCB5
HCB5
220PF/5 0V
220PF/5 0V
X7R 10%
X7R 10%
GND
4
RMA1
RMA1
NOBOM
NOBOM
SMD4X25_ NP
SMD4X25_ NP
RMA1 is soldermask on trace for RMA
1
purpose. Place on suitable location where
1
can be easily reached by Probe
HADS# [10]
HBNR# [10]
HIT# [10]
HBPRI# [10]
HDBSY# [10]
HDRDY# [10]
HITM# [10]
HINIT# [21]
HLOCK# [10]
HTRDY# [10]
HDEFER# [10]
HT9
HT9
HT10
HT10
1
NOBOM
NOBOM
1
NOBOM
NOBOM
TPC26b
TPC26b
HT11
HT11
TPC26b
TPC26b
HT5
HT5
1
NOBOM
NOBOM
HT6
HT6
1
NOBOM
NOBOM
TPC26b
TPC26b
HT1
HT1
1
NOBOM
NOBOM
TPC26b
TPC26b
1
NOBOM
NOBOM
TPC26b
TPC26b
TPC26b
TPC26b
I
I
HR5
HR5
10
12
NI
NI
HCB2
HCB2
220PF/5 0V
220PF/5 0V
X7R 10%
X7R 10%
o
o
HT39
HT39
1
HT14
HT14
TPC26b
TPC26b
1
TPC26b
TPC26b
10
I
I
HR6
HR6
10
10
n
n
NOBOM
NOBOM
NOBOM
NOBOM
12
12
CPU_GTL REF1
12
NI
NI
HCB1
HCB1
220PF/5 0V
220PF/5 0V
X7R 10%
X7R 10%
GND GND GNDGND
NOTE:
Place near CPU
NJP11
NJP11
NJP10
NJP10
SHORTPIN _RECT
SHORTPIN _RECT
SHORTPIN _RECT
SHORTPIN _RECT
NOBOM
NOBOM
NOBOM
NOBOM
1 2
r
r
t
t
+VTT_O UT_L
12
I
I
HR2
HR2
62
62
CPU_GTL REF1_R
CPU_GTL REF0_R
12
I
I
HCB3
HCB3
1UF/10V
1UF/10V
mx_c0603
mx_c0603
3
HT8
HT8
1
NOBOM
NOBOM
TPC26b
TPC26b
HT3
HT3
1
NOBOM
NOBOM
TPC26b
TPC26b
HT4
HT4
1
NOBOM
NOBOM
TPC26b
TPC26b
HBREQ0# [10]
+VTT_O UT_L
12
12
12
I
I
HCB4
HCB4
1UF/10V
1UF/10V
mx_c0603
mx_c0603
C
C
3
+VTT_O UT_L
12
I
I
HR4
HR4
57.6
57.6
1%
1%
12
I
I
HR8
HR8
100
100
1%
1%
o
o
GNDGND
HD#[0..63][10]
I
I
2009.08.04 shawn
HR3
HR3
HR3 from 49.9ohm change to 57.6ohm
57.6
57.6
1%
1%
n
n
I
I
HR7
HR7
100
100
1%
1%
i
i
HD#[0..63][10] HD#[0..63] [10]
f
f
HDBI0#[10]
HDSTBN0 #[10]
HDSTBP0#[10]
d
d
HDBI1#[10]
HDSTBN1 #[10]
HDSTBP1#[10]
2
I
I
XU1B
XU1B
SOCKET77 5/ATX
SOCKET77 5/ATX
HD#0
B4
A10
A11
B10
C11
B12
C12
D11
E10
D10
F11
F12
D13
E13
G13
F14
G14
F15
G15
G11
G12
E12
C5
A4
C6
A5
B6
B7
A7
D8
A8
C8
B9
G9
F8
F9
E9
D7
D00#
D01#
D02#
D03#
D04#
D05#
D06#
D07#
D08#
D09#
D10#
D11#
D12#
D13#
D14#
D15#
DBI0#
a
a
i
i
t
t
DSTBN0#
DSTBP0#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
DBI1#
DSTBN1#
DSTBP1#
REV=1.3
REV=1.3
NOTE:
ICH_GPIOA
PEGATRON DT-MB RESTRICTED SECRET
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Pr oject Name
Size Pr oject Name
Size Pr oject Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7 HD#39
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
n
n
e
e
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
2
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
l
l
DBI2#
DSTBN2#
DSTBP2#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DBI3#
DSTBN3#
DSTBP3#
Default is 0.63*VTT
ICH_GPIOB
G16
E15
E16
G18
G17
F17
F18
E18
E19
F20
E21
F21
G21
E22
D22
G22
D19
G20
G19
D20
D17
A14
C15
C14
B15
C18
B16
A17
B18
C21
B21
B19
A19
A22
B22
C20
A16
C17
0
10
01
11
1
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
GTLREF
0.615*VTT0
0.63*VTT
0.65*VTT
0.67*VTT
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
IPX41-D3
IPX41-D3
IPX41-D3
1
HD#[0..63] [10]
HDBI2# [10]
HDSTBN2 # [10]
HDSTBP2# [10]
HDBI3# [10]
HDSTBN3 # [10]
HDSTBP3# [10]
COMMENTS
HQ1 off, HQ2 on
HQ3 off, HQ4 on
HQ1 off, HQ2 on
HQ3 on, HQ4 off
HQ1 on, HQ2 off
HQ3 off, HQ4 on
HQ1 on, HQ2 off
HQ3 on, HQ4 off
INTEL LGA-775 1 - 3
INTEL LGA-775 1 - 3
INTEL LGA-775 1 - 3
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
7 54Thursday, December 10, 2009
7 54Thursday, December 10, 2009
7 54Thursday, December 10, 2009
Rev
Rev
Rev
1.02
1.02
1.02
Page 8
5
PLACE NEAR SB
+1P1V_FS B_VTT
PLACE COMPONENTS AS CLOSE AS
POSSIBLE TO CPU SOCKET. THE
TRACE WIDTH TO CAPS MUST BE
NO SMALLER THAN 12 MIL.
D D
C C
+VTT_O UT_R
RCVID[0..7][46]
B B
VID_SELEC T[46]
VCC_MB _SENSE[46]
VSS_MB_S ENSE[46]
+VCORE
A A
SMI#[21]
A20M#[21]
HFERR#[21]
INTR[21]
NMI[21]
IGNNE#[21]
STPCLK#[21]
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOTE:
The VCCIO PLL Filter Circuit is no longer
needed since Conroe CPU
HRN2C
680
680
680
680
680
680
680
680
680
680
680
680
680
680
680
680
NOBOM
NOBOM
NOBOM
NOBOM
HRN2C
HRN1A
HRN1A
HRN1D
HRN1D
HRN2D
HRN2D
HRN2A
HRN2A
HRN2B
HRN2B
HRN1B
HRN1B
HRN1C
HRN1C
HT32
HT32
TPC26b
TPC26b
5
GND
5 6
I
I
1 2
I
I
7 8
I
I
7 8
I
I
1 2
I
I
3 4
I
I
3 4
I
I
5 6
I
I
TRD_CPU _P[39]
TRD_CPU _N[39]
HT31
HT31
TPC26b
TPC26b
1
1
12
I
I
HR17
HR17
62
62
HT42
HT42
TPC26b
TPC26b
HT43
HT43
1
TPC26b
TPC26b
HT44
HT44
1
TPC26b
TPC26b
VCC_SEN _AN3
VSS_SEN _AN4
HT42
1
HT43
HT44
RCVID0
RCVID1
RCVID2
RCVID3
RCVID4
RCVID5
RCVID6
RCVID7
GND
GND
P
P
I
I
XU1C
XU1C
SOCKET77 5/ATX
SOCKET77 5/ATX
P2
SMI#
K3
A20M#
R3
FERR#/PBE#
K1
LINT0
L1
LINT1
N2
IGNNE#
M3
STPCLK#
A23
VCCA
B23
VSSA
C23
VCCIOPLL
AM2
VID0
AL5
VID1
AM3
VID2
AL6
VID3
AK4
VID4
AL4
VID5
AM5
VID6
AM7
VID7
AN7
VID_SECECT
AE8
SKTOCC#
AL1
THERMDA
AK1
THERMDC
AJ7
VSS_AJ7
AH7
VSS_AH7
AN5
VCC_MB_REGULATION
AN6
e
e
VSS_MB_REGULATION
AN3
VCC_SENSE
AN4
VSS_SENSE
AL8
VCC_D_SENSE
AL7
VSS_D_SENSE
4
( CPU_SLP )
BOOTSELECT
g
g
REV=1.3
REV=1.3
4
If NOT support C3/ C4, these 4 signals
Note:
can be NC with a PU resistor
Install HR24 for pin: L2
PM_SLP#
DPSLP#
Install HR22 for pin: P1
CPU_PSI
Install HR36 for pin: Y3
DPRSTP#
Install HR37 for pin: T2
TESTHI0
F26
TESTHI00
TESTHI01
TESTHI10
TESTHI11
TESTHI13
TESTHI02
TESTHI03
TESTHI04
TESTHI05
TESTHI06
TESTHI07
TESTHI08
TESTHI09
COMP0
COMP1
COMP2
COMP3
COMP4
COMP5
COMP6
COMP7
COMP8
TESTHI12
RSVD33
RSVD34
RSVD35
RSVD36
RSVD12
RSVD21
RSVD9
MSID0
MSID1
LL_ID1
LL_ID0
PECI
IMPSEL
a
a
FORCEPR#
PWRGOOD
PROCHOT#
THERMTRIP#
TESTHI1
W3
TESTHI10
H5
TESTHI11
P1
TESTHI13
L2
TESTHI2_7
F25
G25
G27
G26
G24
F24
TESTHI8
G3
TESTHI9
G4
HCOMP0
A13
HCOMP1
T1
HCOMP2
G2
HCOMP3
R1
HCOMP4
J2
HCOMP5
T2
Y3
HCOMP7
AE3
HCOMP8
B13
TESTHI12
W2
HR48
HR48
NI
NI
CPU_RSV D33
G1
CPU_TP_R C2
CPU_TP_R C2
U1
CPU_TP_R C3
A24
CPU_TP_R C4
E29
CPU_TP _AH2
AH2
CPU_TP_ G6
G6
CPU_TP _F29
F29
MSID0
W1
MSID1
V1
CPU_LL_ID 1
AA2
CPU_LL_ID 0
V2
CPU_BOO T
Y1
VRDSEL
AL3
o
NC
t
t
o
G5
r
r
IMPSEL_F 6
F6
AK6
N1
AL2
M2
THERMALTRIP# NEED A PULL UP RESISTOR NEAR SB
HR41 51
HR41 51
I
I
HR19 51
HR19 51
I
I
HR20 51
HR20 51
I
I
HR22 51
HR22 51
I
I
HR24 51
HR24 51
I
I
HR23 51
HR23 51
I
I
HR25 51
HR25 51
I
I
HR44 51
HR44 51
I
I
HR49 49.9 1%
HR49 49.9 1%
I
I
HR46 49.9 1%
HR46 49.9 1%
I
I
HR28 49.9 1%
HR28 49.9 1%
I
I
HR33 49.9 1%
HR33 49.9 1%
I
I
HR32 49.9 1%
HR32 49.9 1%
NI
NI
HR37 49.9 1%
HR37 49.9 1%
I
I
HR36 49.9 1%
HR36 49.9 1%
I
I
HR47 49.9 1%
HR47 49.9 1%
NI
NI
HR39 24.9 1%
HR39 24.9 1%
I
I
HR21 51
HR21 51
I
I
0
0
12
HR54 51
HR54 51
I
I
1
1
TPC26b
TPC26b
1
TPC26b
TPC26b
1
TPC26b
TPC26b
1
TPC26b
TPC26b
1
TPC26b
TPC26b
TPC26b
TPC26b
+VTT_O UT_L
12
NI
NI
HR53
HR53
62
62
n
n
12
I
I
HR56
HR56
51
51
GND
3
+1P1V_FS B_VTT
12
12
12
12
12
12
1 2
1 2
CPU_PSI [46]
1 2
1 2
1 2
1 2
12
12
12
12
1 2
12
12
HT21
HT21
HT15
HT15
NOBOM
NOBOM
HT22
HT22
NOBOM
NOBOM
HT16
HT16
NOBOM
NOBOM
HT24
HT24
NOBOM
NOBOM
HT25
HT25
NOBOM
NOBOM
NOBOM
NOBOM
HR641K
HR641K
1 2
12
NI
NI
HR50
HR50
51
51
GND
HT29
HT29
1
NOBOM
NOBOM
TPC26b
TPC26b
HT30
HT30
1
NOBOM
NOBOM
TPC26b
TPC26b
PECI [39]
+VTT_O UT_R +VTT_OUT _L +V TT_OUT_R
12
I
I
HR61
HR61
130
130
1%
1%
+VTT_O UT_L
GND
NI
NI
GND
12
NI
NI
HR51
HR51
o
o
51
51
C
C
GND
12
GND
12
12
NI
NI
HR62
HR62
100
100
12
NI
NI
HCB16
HCB16
0.1UF/16V
0.1UF/16V
GND
3
+VTT_O UT_L
I
I
HR55
HR55
51
51
I
I
HR63
HR63
130
130
1%
1%
+VTT_O UT_R
I
I
I
I
I
I
+VTT_O UT_R
I
I
I
I
I
SYS_RESE T#[22,39,42]
f
f
1 2
VRM_PW RGD[22,46]
FSBSEL0[6, 13]
FSBSEL1[6, 13]
FSBSEL2[6, 13]
HFORCE PH# [48]
CPUPW RGD [22]
PROCHO T# [48]
H_THMTR IP# [21]
I
I
I
I
I
I
I
+1P1V_FS B_VTT
+VTT_O UT_R
+VTT_O UT_L
HR60 5 1
HR60 5 1
I
I
n
n
BOOTSELECT:
Install PD resistor to
prevent PSC SMF CDM PSL
CPU from booting
HR18 49.9 1%
HR18 49.9 1%
1 2
HR43 49.9 1%
HR43 49.9 1%
1 2
HR42 49.9 1%
HR42 49.9 1%
1 2
12
I
I
HR26
HR26
49.9
49.9
1%
1%
GND
HR30 51
HR30 51
1 2
HR29 51
HR29 51
1 2
HR31 51
HR31 51
1 2
HR34 51
HR34 51
1 2
HR35 51
HR35 51
1 2
HR38 51
HR38 51
1 2
e
e
d
NOBOM
NOBOM
i
i
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
d
HT23
HT23
HT17
HT17
TPC26b
TPC26b
TPC26b
TPC26b
HT18
HT18
HT19
HT19
TPC26b
TPC26b
HT26
HT26
HT20
HT20
TPC26b
TPC26b
HT27
HT27
TPC26b
TPC26b
HT28
HT28
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
HR57 470 1%
HR57 470 1%
1 2
I
I
HR59 470 1%
HR59 470 1%
1 2
I
I
HR58 470 1%
HR58 470 1%
1 2
I
I
2009.08.14 shawn
HR57, HR58, HR59 from 470 5% change to 470 1%.
2
I
I
XU1D
XU1D
SOCKET77 5/ATX
SOCKET77 5/ATX
TCK
AE1
TCK
TDI
AD1
TDI
TDO
AF1
TDO
TMS
AC1
TMS
TRST#
AG1
t
t
AJ2
AJ1
AD2
AG2
AF2
AG3
AC2
AK3
AJ3
N5
C9
E7
AE6
D16
A20
E23
AM6
G29
H30
G30
TRST#
i
i
BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#
DBR#
ITPCLK<0>
ITPCLK<1>
RSVD17
RSVD18
RSVD19
RSVD20
RSVD22
RSVD23
RSVD31
VTTPWRGD
BSEL0
BSEL1
BSEL2
a
a
REV=1.3
REV=1.3
12
I
I
HR27
HR27
49.9
49.9
1%
1%
GND
BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#
n
n
CPU_ITPH CLK
1
CPU_ITPHC LK#
1
CPU_TP_ N5
1
H_BPM1 _2
CPU_TP_ E7
1
CPU_TP _AE6
1
CPU_TP _D16
1
CPU_TP _A20
1
CPU_TP _E23
1
+VTT_O UT_R +1P5V_ICH
12
I
I
HR52
HR52
680
680
12
NI
NI
HC2
HC2
100PF/5 0V
100PF/5 0V
NPO 5%
NPO 5%
GND
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
l
l
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT_OUT1
VTT_OUT2
VCC_PLL
2009.10.22 shawn
+CPU_VCCPLL floating, change power net name to +1P5V_ICH.
VTT_SEL
1
NOTE:
FSB_VTT Net Name changed
+1P1V_FS B_VTT
A29
B25
B29
B30
C29
A26
B27
C28
A25
A28
A27
C30
A30
C25
C26
C27
B26
D27
D28
D25
D26
B28
D29
D30
+VTT_O UT_R
AA1
J1
D23
F27
+VTT_O UT_L
12
NI
NI
HCB13
HCB13
0.1UF/16V
0.1UF/16V
GND GND
12
I
I
HCB14
HCB14
0.01UF/25 V
0.01UF/25 V
X7R 10%
X7R 10%
GNDGND
VTT_SE LECT [50]
12
12
PEGATRON DT-MB RESTRICTED SECRET
INTEL LGA-775 2 - 3
INTEL LGA-775 2 - 3
INTEL LGA-775 2 - 3
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Pr oject Name
Size Pr oject Name
Size Pr oject Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Engineer:
IPX41-D3
IPX41-D3
IPX41-D3
1
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
8 54Thursday, December 10, 2009
8 54Thursday, December 10, 2009
8 54Thursday, December 10, 2009
NI
NI
HCB12
HCB12
0.1UF/16V
0.1UF/16V
NI
NI
HCB15
HCB15
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
Rev
Rev
Rev
1.02
1.02
1.02
Page 9
5
4
3
2
1
+VCORE
D D
I
I
I
XU1E
XU1E
SOCKET77 5/ATX
SOCKET77 5/ATX
AA8
VCC1
AB8
VCC2
AC23
VCC3
AC24
VCC4
AC25
VCC5
AC26
VCC6
AC27
VCC7
AC28
VCC8
AC29
VCC9
AC30
VCC10
AC8
VCC11
AD23
VCC12
AD24
VCC13
AD25
VCC14
AD26
VCC15
AD27
VCC16
AD28
VCC17
AD29
VCC18
AD30
VCC19
AD8
C C
B B
A A
AE11
AE12
AE14
AE15
AE18
AE19
AE21
AE22
AE23
AE9
AF11
AF12
AF14
AF15
AF18
AF19
AF21
AF22
AF8
AF9
AG11
AG12
AG14
AG15
AG18
AG19
AG21
AG22
AG25
AG26
AG27
AG28
AG29
AG30
AG8
AG9
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
REV=1.3
REV=1.3
VCC112
VCC111
VCC110
VCC109
VCC108
VCC107
VCC106
VCC105
VCC104
VCC103
VCC102
VCC101
VCC100
VCC99
VCC98
VCC97
VCC96
VCC95
VCC94
VCC93
VCC92
VCC91
VCC90
VCC89
VCC88
VCC87
VCC86
VCC85
VCC84
VCC83
VCC82
VCC81
VCC80
VCC79
VCC78
VCC77
VCC76
VCC75
VCC74
VCC73
VCC72
VCC71
VCC70
VCC69
VCC68
VCC67
VCC66
VCC65
VCC64
VCC63
VCC62
VCC61
VCC60
VCC59
VCC58
VCC57
AM14
AM12
AM11
AL9
AL30
AL29
AL26
AL25
AL22
AL21
AL19
AL18
AL15
AL14
AL12
AL11
AK9
AK8
AK26
AK25
AK22
AK21
AK19
AK18
AK15
AK14
AK12
AK11
AJ9
AJ8
AJ26
AJ25
AJ22
AJ21
AJ19
AJ18
AJ15
AJ14
AJ12
AJ11
AH9
AH8
AH30
AH29
AH28
AH27
AH26
AH25
AH22
AH21
AH19
AH18
AH15
AH14
AH12
AH11
I
XU1F
XU1F
SOCKET77 5/ATX
SOCKET77 5/ATX
AM15
VCC113
AM18
VCC114
AM19
VCC115
AM21
VCC116
AM22
VCC117
AM25
VCC118
AM26
VCC119
AM29
VCC120
AM30
VCC121
AM8
VCC122
AM9
VCC123
AN11
VCC124
AN12
VCC125
AN14
VCC126
AN15
VCC127
AN18
VCC128
AN19
VCC129
AN21
VCC130
AN22
VCC131
AN25
VCC132
AN26
VCC133
AN29
VCC134
AN30
VCC135
AN8
VCC136
AN9
VCC137
J10
VCC138
J11
VCC139
J12
VCC140
J13
VCC141
J14
VCC142
J15
VCC143
J18
VCC144
J19
VCC145
J20
VCC146
J21
VCC147
J22
VCC148
J23
VCC149
J24
VCC150
J25
VCC151
J26
VCC152
J27
VCC153
J28
VCC154
J29
VCC155
J30
VCC156
J8
VCC157
J9
VCC158
K30
VCC159
K29
VCC160
K28
VCC161
K27
VCC162
K26
VCC163
K25
VCC164
K24
VCC165
K23
VCC166
K8
VCC167
Y8
VCC168
P
P
REV=1.3
REV=1.3
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
e
e
NOBOM
NOBOM
NOBOM
NOBOM
VCC225
VCC224
VCC223
VCC222
VCC221
VCC220
VCC219
VCC218
VCC217
VCC216
VCC215
VCC214
VCC213
VCC212
VCC211
VCC210
VCC209
VCC208
VCC207
VCC206
VCC205
VCC204
VCC203
VCC202
VCC201
VCC200
VCC199
VCC198
VCC197
VCC196
VCC195
VCC194
VCC193
VCC192
VCC191
VCC190
VCC189
VCC188
VCC187
VCC186
VCC185
VCC184
VCC183
VCC182
VCC181
VCC180
VCC179
VCC178
VCC177
VCC176
VCC175
VCC174
VCC173
VCC172
VCC171
VCC170
VCC169
g
g
L8
M23
M24
M25
M26
M27
M28
M29
M30
M8
N23
N24
N25
N26
N27
N28
N29
N30
N8
P8
R8
T23
T24
T25
T26
T27
T28
T29
T30
T8
U23
U24
U25
U26
U27
U28
U29
U30
U8
V8
W23
W24
W25
W26
W27
W28
W29
W30
W8
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y30
a
a
HT33
HT33
HT34
HT34
1
HT35
HT35
1
TPC26b
TPC26b
HT36
HT36
1
TPC26b
TPC26b
HT37
HT37
1
TPC26b
TPC26b
HT38
HT38
1
TPC26b
TPC26b
1
TPC26b
TPC26b
TPC26b
TPC26b
r
r
t
t
CPU_TP_ D1
CPU_TP _D14
CPU_TP_ E5
CPU_TP_ E6
CPU_TP _F23
CPU_TP_ J3
o
o
GND
I
I
XU1G
XU1G
SOCKET77 5/ATX
SOCKET77 5/ATX
AF28
VSS1
AF27
VSS2
AF26
VSS3
AF25
VSS4
AF24
VSS5
AF23
VSS6
AF20
VSS7
AF17
VSS8
AF16
VSS9
AF13
VSS10
AF10
VSS11
AE7
VSS12
AE5
VSS13
AE30
VSS14
AE29
VSS15
AE28
VSS16
AE27
VSS17
AE26
VSS18
AE25
VSS19
AE24
VSS20
AE20
VSS21
AE2
VSS22
AE17
VSS23
AE16
VSS24
AE13
VSS25
AE10
VSS26
AD7
VSS27
AD4
VSS28
AC7
VSS29
AC3
VSS30
AC6
VSS31
AB7
VSS32
AB30
VSS33
AB29
VSS34
AB28
VSS35
AB27
VSS36
AB26
VSS37
AB25
VSS38
AB24
VSS39
AB23
VSS40
AB1
VSS41
AA7
VSS42
AA6
VSS43
AA30
VSS44
AA3
VSS45
AA29
VSS46
AA28
VSS47
AA27
VSS48
AA26
VSS49
AA25
VSS50
A12
VSS51
A15
VSS52
A18
VSS53
A2
VSS54
A21
VSS55
A6
VSS56
A9
VSS57
n
n
AA23
VSS58
AA24
VSS59
AF29
VSS60
D1
RSVD27
D14
RSVD28
E5
RSVD29
E6
RSVD30
F23
RSVD37
J3
RSVD32
C
C
REV=1.3
REV=1.3
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
AF3
AF30
AF6
AF7
AG10
AG13
AG16
AG17
AG20
AG23
AG24
AG7
AH1
AH10
AH13
AH16
AH17
AH20
AH23
AH24
AH3
AH6
AJ10
AJ13
AJ16
AJ17
AJ20
AJ23
AJ24
AJ27
AJ28
AJ29
AJ30
AJ4
AK10
AK13
AK16
AK17
AK2
AK20
AK23
AK24
AK27
AK28
AK29
AK30
o
o
AK5
AK7
AL10
AL13
AL16
AL17
AL20
AL23
AL24
AL27
AL28
AM1
AM10
AM13
AM16
AM17
AM20
AM23
AM24
AM27
AM28
AM4
AN1
AN10
AN13
AN16
AN17
AN2
AN20
AN23
AN24
AN27
AN28
B1
n
n
GND
f
f
GND
B11
B14
B17
B20
B24
B5
B8
C10
C13
C16
C19
C22
C24
C4
C7
D12
D15
D18
D21
D24
D3
D5
D6
D9
E11
E14
E17
E2
E20
E25
E26
E27
E28
E8
F10
i
i
F13
F16
F19
F22
F4
F7
H10
H11
H12
H13
H14
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H3
H6
I
I
XU1H
XU1H
SOCKET77 5/ATX
SOCKET77 5/ATX
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
d
d
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
REV=1.3
REV=1.3
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
e
e
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
Y7
Y5
Y2
W7
W4
V7
V6
V30
V3
V29
V28
V27
V26
V25
V24
V23
U7
T7
T6
T3
R7
R5
R30
R29
R28
n
n
R27
R26
R25
R24
R23
R2
P7
P4
P30
P29
P28
P27
P26
P25
P24
P23
N7
N6
N3
M7
M1
L7
L6
L30
L3
L29
L28
L27
L26
L25
L24
L23
K7
K5
K2
J7
J4
H9
H8
H7
t
t
i
i
GND
a
a
l
l
I
I
XU1I
XU1I
SOCKET77 5/ATX
SOCKET77 5/ATX
1
RM_POST_NC1
2
RM_POST_NC2
3
RM_POST_NC3
4
RM_POST_NC4
REV=1.3
REV=1.3
PEGATRON DT-MB RESTRICTED SECRET
INTEL LGA-775 3 - 3
INTEL LGA-775 3 - 3
INTEL LGA-775 3 - 3
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Pr oject Name
Size Pr oject Name
Size Pr oject Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Engineer:
IPX41-D3
IPX41-D3
IPX41-D3
1
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
9 54Thursday, December 10, 2009
9 54Thursday, December 10, 2009
9 54Thursday, December 10, 2009
Rev
Rev
Rev
1.02
1.02
1.02
Page 10
5
I
I
NU1A
AA35
AA37
AA36
H39
N39
N35
N37
N40
M45
R35
R36
R34
R37
R39
U38
U34
U40
Y36
U35
U37
Y37
Y34
Y38
G38
K35
C43
G39
C39
B39
B40
K31
K25
C32
D32
D30
G44
K44
H45
H40
H37
H42
G43
G42
D27
P30
P29
N25
L36
L37
J38
F40
L38
L43
J41
T36
T37
T34
J39
J40
T39
J31
F33
J25
F26
J42
L40
J43
L42
J44
L44
NU1A
FSB_AB_3
FSB_AB_4
FSB_AB_5
FSB_AB_6
FSB_AB_7
FSB_AB_8
FSB_AB_9
FSB_AB_10
FSB_AB_11
FSB_AB_12
FSB_AB_13
FSB_AB_14
FSB_AB_15
FSB_AB_16
FSB_AB_17
FSB_AB_18
FSB_AB_19
FSB_AB_20
FSB_AB_21
FSB_AB_22
FSB_AB_23
FSB_AB_24
FSB_AB_25
FSB_AB_26
FSB_AB_27
FSB_AB_28
FSB_AB_29
FSB_AB_30
FSB_AB_31
FSB_AB_32
FSB_AB_33
FSB_AB_34
FSB_AB_35
FSB_REQB_0
FSB_REQB_1
FSB_REQB_2
FSB_REQB_3
FSB_REQB_4
FSB_ADSTBB_0
FSB_ADSTBB_1
FSB_DSTBPB_0
FSB_DSTBNB_0
FSB_DINVB_0
FSB_DSTBPB_1
FSB_DSTBNB_1
FSB_DINVB_1
FSB_DSTBPB_2
FSB_DSTBNB_2
FSB_DINVB_2
FSB_DSTBPB_3
FSB_DSTBNB_3
FSB_DINVB_3
FSB_ADSB
FSB_TRDYB
FSB_DRDYB
FSB_DEFERB
FSB_HITMB
FSB_HITB
FSB_LOCKB
FSB_BREQ0B
FSB_BNRB
FSB_BPRIB
FSB_DBSYB
FSB_RSB_0
FSB_RSB_1
FSB_RSB_2
FSB_CPURSTB
P
P
HPL_CLKINN
HPL_CLKINP
RSVD21
EAGLELA KE
EAGLELA KE
FSB
FSB
REV=1.4
REV=1.4
FSB_DB_0
FSB_DB_1
FSB_DB_2
FSB_DB_3
FSB_DB_4
FSB_DB_5
FSB_DB_6
FSB_DB_7
FSB_DB_8
FSB_DB_9
FSB_DB_10
FSB_DB_11
FSB_DB_12
FSB_DB_13
FSB_DB_14
FSB_DB_15
FSB_DB_16
FSB_DB_17
FSB_DB_18
FSB_DB_19
FSB_DB_20
FSB_DB_21
FSB_DB_22
FSB_DB_23
FSB_DB_24
FSB_DB_25
FSB_DB_26
FSB_DB_27
FSB_DB_28
FSB_DB_29
FSB_DB_30
FSB_DB_31
FSB_DB_32
FSB_DB_33
FSB_DB_34
FSB_DB_35
FSB_DB_36
FSB_DB_37
FSB_DB_38
FSB_DB_39
FSB_DB_40
FSB_DB_41
FSB_DB_42
FSB_DB_43
FSB_DB_44
FSB_DB_45
FSB_DB_46
FSB_DB_47
FSB_DB_48
FSB_DB_49
FSB_DB_50
FSB_DB_51
FSB_DB_52
FSB_DB_53
FSB_DB_54
FSB_DB_55
FSB_DB_56
FSB_DB_57
FSB_DB_58
FSB_DB_59
FSB_DB_60
FSB_DB_61
FSB_DB_62
FSB_DB_63
FSB_SWING
FSB_RCOMP
e
e
FSB_DVREF
FSB_ACCVREF
HA#[3..35][ 7] HD#[0..63] [7]
D D
C C
HREQ#[0..4][7]
HADSTB0#[7]
HADSTB1#[7]
HDSTBP0#[7]
HDSTBN0 #[7]
HDBI0#[7]
HDSTBP1#[7]
HDSTBN1 #[7]
HDBI1#[7]
HDSTBP2#[7]
HDSTBN2 #[7]
HDBI2#[7]
HDSTBP3#[7]
HDSTBN3 #[7]
HDBI3#[7]
B B
A A
HRS#[0..2][7]
CPURES ET#[7]
MCHHCL K#[6]
MCHHCL K[6]
NOBOM
NOBOM
HADS#[7]
HTRDY#[7]
HDRDY#[7]
HDEFER#[7]
HITM#[7]
HIT#[7]
HLOCK#[7]
HBREQ0#[7]
HBNR#[7]
HBPRI#[7]
HDBSY#[7]
NT3
NT3
1
TPC26b
TPC26b
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HA#32
HA#33
HA#34
HA#35
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HRS#0
HRS#1
HRS#2
TP_MCH_ N25
5
4
F44
C44
D44
C41
E43
B43
D40
B42
B38
F38
A38
B37
D38
C37
D37
B36
E37
J35
H35
F37
G37
J33
L33
G33
L31
M31
M30
J30
G31
K30
M29
G30
J29
F29
H29
L25
K26
L29
J26
M26
H26
F25
F24
G25
H24
L24
J24
N24
C28
B31
F35
C35
B35
D35
D31
A34
B32
F31
D28
A29
C30
B30
E27
B28
B24
A23
g
g
C22
B23
4
3
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
HXSW ING
HXRCOM P
a
a
MCH_GT LREF0
r
r
t
t
12
I
I
NR5
NR5
16.5
16.5
1%
1%
GND
12
NI
NI
NCB2
NCB2
220PF/5 0V
220PF/5 0V
X7R 10%
X7R 10%
GND GND GND
MCH_GTL REF0 W/S =10/7
MCH_GTL REF0 W/S =10/7
MCH_GTL REF0 W/S =10/7MCH_GTL REF0 W/S =10/7
1
SDVO_CTRL_DATA
1
SDVO CARD PRESENT, PEG DISABLE
0
SDVO DISABLE(DEFAULT)
0
n
n
12
GND
12
HXSW ING_R
I
I
NCB1
NCB1
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
R_MCH_G TLREF0
I
I
NCB3
NCB3
1UF/16V
1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
HXSWING W/S=10/ 10
HXSWING W/S=10/ 10
HXSWING W/S=10/ 10HXSWING W/S=10/ 10
HXRCOMP W/S=10/ 7
HXRCOMP W/S=10/ 7
HXRCOMP W/S=10/ 7HXRCOMP W/S=10/ 7
I
I
NR4
NR4
51
51
o
o
12
I
I
NR8
NR8
51
51
12
C
C
+1P1V_FS B_VTT
3
NT43 T PC26b
NT43 T PC26b
NT42 TPC 26b
NT42 TPC 26b
NOBOM
NOBOM
NOBOM
NOBOM
o
o
12
I
I
NR3
NR3
301
301
1%
1%
12
I
I
NR6
NR6
100
100
1%
1%
GND
CK_100M _MCH[6]
CK_100M_ MCH#[ 6]
NOBOM
NOBOM
NOBOM
NOBOM
n
n
+1P1V_FS B_VTT
12
I
I
NR7
NR7
57.6
57.6
1%
1%
12
I
I
NR9
NR9
100
100
1%
1%
TPC26b
TPC26b
TPC26b
TPC26b
EXP_RXP0[25]
EXP_RXN0[25]
EXP_RXP1[25]
EXP_RXN1[25]
EXP_RXP2[25]
EXP_RXN2[25]
EXP_RXP3[25]
EXP_RXN3[25]
EXP_RXP4[25]
EXP_RXN4[25]
EXP_RXP5[25]
EXP_RXN5[25]
EXP_RXP6[25]
EXP_RXN6[25]
EXP_RXP7[28]
EXP_RXN7[28]
EXP_RXP8[25]
EXP_RXN8[25]
EXP_RXP9[25]
EXP_RXN9[25]
EXP_RXP 10[25]
EXP_RXN 10[25]
EXP_RXP 11[25]
EXP_RXN 11[25]
EXP_RXP 12[25]
EXP_RXN 12[25]
EXP_RXP 13[25]
EXP_RXN 13[25]
EXP_RXP 14[25]
EXP_RXN 14[25]
EXP_RXP 15[25]
EXP_RXN 15[25]
DMI_RXP0[20]
DMI_RXN0[20]
DMI_RXP1[20]
DMI_RXN1[20]
DMI_RXP2[20]
DMI_RXN2[20]
DMI_RXP3[20]
DMI_RXN3[20]
NT1
NT1
NT2
NT2
1
1
f
f
TP_SDVO_ DATA
1
TP_SDVO _CLK
1
TP_MCH_ AD13
i
i
D9
E9
J13
G13
AB13
AD13
F6
G7
H6
G4
J6
J7
L6
L7
N9
N10
N7
N6
R7
R6
R9
R10
U10
U9
U6
d
d
U7
AA9
AA10
R4
P4
AA7
AA6
AB10
AB9
AB3
AA2
AD10
AD11
AD7
AD8
AE9
AE10
AE6
AE7
AF9
AF8
2
I
I
NU1B
NU1B
EXP_CLKP
EXP_CLKN
SDVO_CTRLDATA
SDVO_CTRLCLK
RSVD2
RSVD4
PEG_RXP_0
PEG_RXN_0
PEG_RXP_1
PEG_RXN_1
PEG_RXP_2
PEG_RXN_2
PEG_RXP_3
PEG_RXN_3
PEG_RXP_4
PEG_RXN_4
PEG_RXP_5
n
n
PEG_RXN_5
PEG_RXP_6
PEG_RXN_6
PEG_RXP_7
e
e
PEG_RXN_7
PEG_RXP_8
PEG_RXN_8
PEG_RXP_9
PEG_RXN_9
PEG_RXP_10
PEG_RXN_10
PEG_RXP_11
PEG_RXN_11
PEG_RXP_12
PEG_RXN_12
PEG_RXP_13
PEG_RXN_13
PEG_RXP_14
PEG_RXN_14
PEG_RXP_15
PEG_RXN_15
DMI_RXP_0
DMI_RXN_0
DMI_RXP_1
DMI_RXN_1
DMI_RXP_2
DMI_RXN_2
DMI_RXP_3
DMI_RXN_3
EAGLELA KE
EAGLELA KE
2
SDVO
SDVO
PCIE
PCIE
DMI
DMI
REV=1.4
REV=1.4
EXP_RCOMPO
EXP_COMPI
EXP_ICOMPO
EXP_RBIAS
PEG_TXP_0
PEG_TXN_0
PEG_TXP_1
PEG_TXN_1
PEG_TXP_2
i
i
PEG_TXN_2
PEG_TXP_3
t
t
PEG_TXN_3
PEG_TXP_4
PEG_TXN_4
PEG_TXP_5
PEG_TXN_5
PEG_TXP_6
PEG_TXN_6
PEG_TXP_7
PEG_TXN_7
PEG_TXP_8
PEG_TXN_8
PEG_TXP_9
PEG_TXN_9
PEG_TXP_10
PEG_TXN_10
PEG_TXP_11
PEG_TXN_11
PEG_TXP_12
PEG_TXN_12
PEG_TXP_13
PEG_TXN_13
PEG_TXP_14
PEG_TXN_14
PEG_TXP_15
PEG_TXN_15
DMI_TXP_0
DMI_TXN_0
DMI_TXP_1
DMI_TXN_1
DMI_TXP_2
DMI_TXN_2
DMI_TXP_3
DMI_TXN_3
1
+1P1V_C ORE
12
I
I
NR1
NR1
49.9
49.9
1%
1%
l
l
12
NOTE:
Breakout W/S:10/6
W/S:10/10
I
I
NR2
NR2
750
750
1%
1%
EXP_TX P0 [ 25]
EXP_TX N0 [25]
EXP_TX P1 [ 25]
EXP_TX N1 [25]
EXP_TX P2 [ 25]
EXP_TX N2 [25]
EXP_TX P3 [ 25]
EXP_TX N3 [25]
EXP_TX P4 [ 28]
EXP_TX N4 [28]
EXP_TX P5 [ 28]
EXP_TX N5 [28]
EXP_TX P6 [ 28]
EXP_TX N6 [28]
EXP_TX P7 [ 28]
EXP_TX N7 [28]
EXP_TX P8 [ 25]
EXP_TX N8 [25]
EXP_TX P9 [ 25]
EXP_TX N9 [25]
EXP_TXP 10 [25]
EXP_TXN 10 [25]
EXP_TXP 11 [25]
EXP_TXN 11 [25]
EXP_TXP 12 [25]
EXP_TXN 12 [25]
EXP_TXP 13 [25]
EXP_TXN 13 [25]
EXP_TXP 14 [25]
EXP_TXN 14 [25]
EXP_TXP 15 [25]
EXP_TXN 15 [25]
DMI_TXP0 [20]
DMI_TXN0 [20]
DMI_TXP1 [20]
DMI_TXN1 [20]
DMI_TXP2 [20]
DMI_TXN2 [20]
DMI_TXP3 [20]
DMI_TXN3 [20]
EXP_RCO MP
Y7
Y8
Y6
EXP_RBIA STP_MCH_ AB13
AG1
GND
C11
B11
A10
a
a
B9
C9
D8
B8
C7
B7
B6
B3
B4
D2
C2
H2
G2
J2
K2
K1
L2
P2
M2
T2
R1
U2
V2
W4
V3
AA4
Y4
AC1
AB2
NOTE:
Check Eaglelake PDG for detai if wanna
support Integrated HDMI/DVI/DP
AC2
AD2
AD4
AE4
AE2
AF2
AF4
AG4
PEGATRON DT-MB RESTRICTED SECRET
Title :
Title :
Title :
EAGLELAKE 1- 7
EAGLELAKE 1- 7
EAGLELAKE 1- 7
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Pr oject Name
Size Pr oject Name
Size Pr oject Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Engineer:
IPX41-D3
IPX41-D3
IPX41-D3
1
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
10 54Thursday, December 10, 2009
10 54Thursday, December 10, 2009
10 54Thursday, December 10, 2009
Rev
Rev
Rev
1.02
1.02
1.02
Page 11
5
M_CHA_MAA [1..14][17]
D D
M_CHA_C AS#[17]
M_CHA_R AS#[17]
M_CHA_B A0[17]
M_CHA_B A1[17]
M_CHA_B A2[17]
M_CHA_C S#0[1 7]
NOBOM
NOBOM
M_CHA_C KE0[17]
M_CHA_C KE1[17]
M_CHA_O DT0[17]
M_CHA_O DT1[17]
NOBOM
C C
B B
P
P
A A
5
NOBOM
M_CHA_C LK0[1 7]
M_CHA_C LK0#[17]
M_CHA_C LK2[1 7]
M_CHA_C LK2#[17]
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
e
e
4
HT49
HT49
1
HT48
HT48
1
HT45
HT45
1
HT47
HT47
1
HT46
HT46
1
HT40
HT40
1
HT41
HT41
1
g
g
4
M_CHA_M AA1
M_CHA_M AA2
M_CHA_M AA3
M_CHA_M AA4
M_CHA_M AA5
M_CHA_M AA6
M_CHA_M AA7
M_CHA_M AA8
M_CHA_M AA9
M_CHA_M AA10
M_CHA_M AA11
M_CHA_M AA12
M_CHA_M AA13
M_CHA_M AA14
N27146 510
N27146 424
N27146 426
N27146 514
N27146 515
N27146 428
N27146 516
a
a
t
t
r
r
I
I
NU1C
NU1C
BC41
DDR_A_MA_0
BC35
DDR_A_MA_1
BB32
DDR_A_MA_2
BC32
DDR_A_MA_3
BD32
DDR_A_MA_4
BB31
DDR_A_MA_5
AY31
DDR_A_MA_6
BA31
DDR_A_MA_7
BD31
DDR_A_MA_8
BD30
DDR_A_MA_9
AW43
DDR_A_MA_10
BC30
DDR_A_MA_11
BB30
DDR_A_MA_12
AM42
DDR_A_MA_13
BD28
DDR_A_MA_14
AW42
DDR_A_WEB
AU42
DDR_A_CASB
AV42
DDR_A_RASB
AV45
DDR_A_BS_0
AY44
DDR_A_BS_1
BC28
DDR_A_BS_2
AU43
DDR_A_CSB_0
AR40
DDR_A_CSB_1
AU44
DDR_A_CSB_2
AM43
DDR_A_CSB_3
BB27
DDR_A_CKE_0
BD27
DDR_A_CKE_1
BA27
DDR_A_CKE_2
AY26
DDR_A_CKE_3
AR42
DDR_A_ODT_0
AM44
DDR_A_ODT_1
AR44
DDR_A_ODT_2
AL40
DDR_A_ODT_3
AY37
DDR_A_CK_0
BA37
DDR_A_CKB_0
AW29
DDR_A_CK_1
AY29
DDR_A_CKB_1
AU37
DDR_A_CK_2
AV37
DDR_A_CKB_2
AU33
DDR_A_CK_3
AT33
DDR_A_CKB_3
AT30
DDR_A_CK_4
AR30
DDR_A_CKB_4
AW38
DDR_A_CK_5
AY38
DDR_A_CKB_5
o
o
EAGLELA KE
EAGLELA KE
DDR_A
DDR_A
n
n
REV=1.4
REV=1.4
DDR_A_DQS_0
DDR_A_DQSB_0
DDR_A_DM_0
DDR_A_DQ_0
DDR_A_DQ_1
DDR_A_DQ_2
DDR_A_DQ_3
DDR_A_DQ_4
DDR_A_DQ_5
DDR_A_DQ_6
DDR_A_DQ_7
DDR_A_DQS_1
DDR_A_DQSB_1
DDR_A_DM_1
DDR_A_DQ_8
DDR_A_DQ_9
DDR_A_DQ_10
DDR_A_DQ_11
DDR_A_DQ_12
DDR_A_DQ_13
DDR_A_DQ_14
DDR_A_DQ_15
DDR_A_DQS_2
DDR_A_DQSB_2
DDR_A_DM_2
DDR_A_DQ_16
DDR_A_DQ_17
DDR_A_DQ_18
DDR_A_DQ_19
DDR_A_DQ_20
DDR_A_DQ_21
DDR_A_DQ_22
DDR_A_DQ_23
DDR_A_DQS_3
DDR_A_DQSB_3
DDR_A_DM_3
DDR_A_DQ_24
DDR_A_DQ_25
DDR_A_DQ_26
DDR_A_DQ_27
DDR_A_DQ_28
DDR_A_DQ_29
DDR_A_DQ_30
DDR_A_DQ_31
DDR_A_DQS_4
DDR_A_DQSB_4
DDR_A_DM_4
DDR_A_DQ_32
DDR_A_DQ_33
DDR_A_DQ_34
DDR_A_DQ_35
C
C
DDR_A_DQ_36
DDR_A_DQ_37
DDR_A_DQ_38
DDR_A_DQ_39
DDR_A_DQS_5
DDR_A_DQSB_5
DDR_A_DM_5
DDR_A_DQ_40
DDR_A_DQ_41
DDR_A_DQ_42
DDR_A_DQ_43
DDR_A_DQ_44
DDR_A_DQ_45
DDR_A_DQ_46
DDR_A_DQ_47
DDR_A_DQS_6
DDR_A_DQSB_6
DDR_A_DM_6
DDR_A_DQ_48
DDR_A_DQ_49
DDR_A_DQ_50
DDR_A_DQ_51
DDR_A_DQ_52
DDR_A_DQ_53
DDR_A_DQ_54
DDR_A_DQ_55
DDR_A_DQS_7
DDR_A_DQSB_7
DDR_A_DM_7
DDR_A_DQ_56
DDR_A_DQ_57
DDR_A_DQ_58
DDR_A_DQ_59
DDR_A_DQ_60
DDR_A_DQ_61
DDR_A_DQ_62
DDR_A_DQ_63
3
BC5
BD4
BC3
BC2
BD3
BD7
BB7
BB2
BA3
BE6
BD6
BB9
BC9
BD9
BB8
AY8
BD11
BB11
BC7
BE8
BD10
AY11
BD15
BB15
BD14
BB14
BC14
BC16
BB16
BC11
BE12
BA15
BD16
AR22
AT22
AV22
AW21
AY22
AV24
AY24
AU21
AT21
AR24
AU24
AH43
AH42
AK42
AL41
AK43
AG42
AG44
AL42
AK44
AH44
AG41
AD43
AE42
AE45
AF43
AF42
AC44
AC42
AF40
AF44
AD44
AC41
Y43
Y42
AA45
AB43
AA42
W42
W41
AB42
AB44
Y44
Y40
T44
T43
T42
V42
U45
R40
P44
V44
V43
R41
R44
3
M_CHA_D Q0
M_CHA_D Q1
M_CHA_D Q2
M_CHA_D Q3
M_CHA_D Q4
M_CHA_D Q5
M_CHA_D Q6
M_CHA_D Q7
M_CHA_D Q8
M_CHA_D Q9
M_CHA_D Q10
M_CHA_D Q11
M_CHA_D Q12
M_CHA_D Q13
M_CHA_D Q14
M_CHA_D Q15
M_CHA_D Q16
M_CHA_D Q17
M_CHA_D Q18
M_CHA_D Q19
M_CHA_D Q20
M_CHA_D Q21
M_CHA_D Q22
M_CHA_D Q23
M_CHA_D Q24
M_CHA_D Q25
M_CHA_D Q26
M_CHA_D Q27
M_CHA_D Q28
M_CHA_D Q29
M_CHA_D Q30
M_CHA_D Q31
o
o
M_CHA_D Q32
M_CHA_D Q33
M_CHA_D Q34
M_CHA_D Q35
M_CHA_D Q36
M_CHA_D Q37
M_CHA_D Q38
M_CHA_D Q39
M_CHA_D Q40
M_CHA_D Q41
M_CHA_D Q42
M_CHA_D Q43
M_CHA_D Q44
M_CHA_D Q45
M_CHA_D Q46
M_CHA_D Q47
M_CHA_D Q48
M_CHA_D Q49
M_CHA_D Q50
M_CHA_D Q51
M_CHA_D Q52
M_CHA_D Q53
M_CHA_D Q54
M_CHA_D Q55
M_CHA_D Q56
M_CHA_D Q57
M_CHA_D Q58
M_CHA_D Q59
M_CHA_D Q60
M_CHA_D Q61
M_CHA_D Q62
M_CHA_D Q63
n
n
f
f
M_CHA_D QS0 [17]
M_CHA_D QS0# [17]
M_CHA_D M0 [17]
M_CHA_D QS1 [17]
M_CHA_D QS1# [17]
M_CHA_D M1 [17]
M_CHA_D QS2 [17]
M_CHA_D QS2# [17]
M_CHA_D M2 [17]
M_CHA_D QS3 [17]
M_CHA_D QS3# [17]
d
d
M_CHA_D M3 [17]
i
i
M_CHA_D QS4 [17]
M_CHA_D QS4# [17]
M_CHA_D M4 [17]
M_CHA_D QS5 [17]
M_CHA_D QS5# [17]
M_CHA_D M5 [17]
M_CHA_D QS6 [17]
M_CHA_D QS6# [17]
M_CHA_D M6 [17]
M_CHA_D QS7 [17]
M_CHA_D QS7# [17]
M_CHA_D M7 [17]
2
e
e
2
n
n
M_CHA_DQ[ 0..63] [17]
l
l
a
a
i
i
t
t
PEGATRON DT-MB RESTRICTED SECRET
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Pr oject Name
Size Pr oject Name
Size Pr oject Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
IPX41-D3
IPX41-D3
IPX41-D3
1
EAGELLAKE 2 - 7
EAGELLAKE 2 - 7
EAGELLAKE 2 - 7
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
11 54Thursday, December 10, 2009
11 54Thursday, December 10, 2009
11 54Thursday, December 10, 2009
Rev
Rev
Rev
1.02
1.02
1.02
Page 12
5
M_CHB_MAA [0..14][18]
D D
C C
DDR_REF NEED RO UTING
Width/Spacing: 12/12 mils
+1P5V_D UAL
DDR3_DR AM_PWRO K[19]
e
e
I
I
NCB4
NCB4
0.1UF/16V
0.1UF/16V
12
I
I
NR11
NR11
1K
1K
1%
1%
12
I
I
NR12
NR12
1K
1K
1%
1%
GND GND
5
12
I
I
NCB5
NCB5
0.1UF/16V
0.1UF/16V
090420 add by TSL
12
I
I
NCB115
NCB115
1UF/10V
1UF/10V
mx_c0603
mx_c0603
GND
P
P
12
B B
GND
MCH_DDR_RPU, MC H_DDR_RPD, MCH_DDR_SPU, MCH_DDR_SPD
NEED ROUTING LE SS THEN 1000MIL LEN GTH.
WIDTH/SPACING = 10/10 MIL
A A
4
M_CHB_W E#[18]
M_CHB_C AS#[18]
M_CHB_R AS#[18]
M_CHB_B A0[18]
M_CHB_B A1[18]
M_CHB_B A2[18]
M_CHB_C S#0[1 8]
M_CHB_C S#1[1 8]
M_CHB_C KE0[18]
M_CHB_C KE1[18]
M_CHB_O DT0[18]
M_CHB_O DT1[18]
M_CHB_C LK0[1 8]
M_CHB_C LK0#[18]
M_CHB_C LK2[1 8]
M_CHB_C LK2#[18]
M_CHA_C S#1[1 7]
M_CHA_M AA0[17]
M_CHA_W E#[17]
DDR3_DR AMRST#[17,18]
+1P5V_D UAL
12
g
g
GND
+1P5V_D UAL
12
GND GND
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
I
I
NCB6
NCB6
0.1UF/16V
0.1UF/16V
I
I
NCB7
NCB7
0.1UF/16V
0.1UF/16V
4
1
1
1
1
1
1
1
1
1
1
1
1
1
I
I
NR13
NR13
1 2
a
a
80.6
80.6
1%
1%
I
I
NR15
NR15
1 2
80.6
80.6
1%
1%
3
I
I
NU1D
NU1D
M_CHB_M AA0
M_CHB_M AA1
M_CHB_M AA2
M_CHB_M AA3
M_CHB_M AA4
M_CHB_M AA5
M_CHB_M AA6
M_CHB_M AA7
M_CHB_M AA8
M_CHB_M AA9
M_CHB_M AA10
M_CHB_M AA11
M_CHB_M AA12
M_CHB_M AA13
M_CHB_M AA14
N27146 430
HT53
HT53
N27146 431
HT55
HT55
N27146 432
HT58
HT58
N27146 434
HT61
HT61
N27146 435
HT50
HT50
N27146 436
HT54
HT54
N27146 437
HT57
HT57
N27146 438
HT60
HT60
N27146 439
HT62
HT62
N27146 440
HT51
HT51
N27146 442
HT59
HT59
N27146 445
HT52
HT52
N27146 446
HT56
HT56
DDR_VRE F M_CHB_D Q40
o
o
r
r
t
t
MCH_DD R_RPU
MCH_DD R_RPD
12
I
I
NR17
NR17
80.6
80.6
1%
1%
GND
MCH_DD R_SPU
MCH_DD R_SPD
12
I
I
NR16
NR16
249
249
1%
1%
BD24
DDR_B_MA_0
BB23
DDR_B_MA_1
BB24
DDR_B_MA_2
BD23
DDR_B_MA_3
BB22
DDR_B_MA_4
BD22
DDR_B_MA_5
BC22
DDR_B_MA_6
BC20
DDR_B_MA_7
BB20
DDR_B_MA_8
BD20
DDR_B_MA_9
BC26
DDR_B_MA_10
BD19
DDR_B_MA_11
BB19
DDR_B_MA_12
BE38
DDR_B_MA_13
BA19
DDR_B_MA_14
BD36
DDR_B_WEB
BC37
DDR_B_CASB
BD35
DDR_B_RASB
BD26
DDR_B_BS_0
BB26
DDR_B_BS_1
BD18
DDR_B_BS_2
BB35
DDR_B_CSB_0
BD39
DDR_B_CSB_1
BB37
DDR_B_CSB_2
BD40
DDR_B_CSB_3
BC18
DDR_B_CKE_0
AY20
DDR_B_CKE_1
BE17
DDR_B_CKE_2
BB18
DDR_B_CKE_3
BD37
DDR_B_ODT_0
BC39
DDR_B_ODT_1
BB38
DDR_B_ODT_2
BD42
DDR_B_ODT_3
AY33
DDR_B_CK_0
AW33
DDR_B_CKB_0
AV31
DDR_B_CK_1
AW31
DDR_B_CKB_1
AW35
DDR_B_CK_2
AY35
DDR_B_CKB_2
AT31
DDR_B_CK_3
AU31
DDR_B_CKB_3
AP31
DDR_B_CK_4
AP30
DDR_B_CKB_4
AW37
DDR_B_CK_5
AV35
DDR_B_CKB_5
AR43
DDR3_A_CSB1
BB40
DDR3_A_MA0
AT44
DDR3_A_WEB
AV40
DDR3_B_ODT3
AR6
DDR3_DRAM_PWROK
BC24
DDR3_DRAMRSTB
AN29
RSVD7
n
n
AN30
RSVD8
AJ33
RSVD5
AK33
RSVD6
BB44
DDR_VREF
BA43
DDR_RPU
AY42
DDR_RPD
BC44
DDR_SPU
BC43
DDR_SPD
DDR_B
DDR_B
EAGLELA KE
EAGLELA KE
C
C
REV=1.4
REV=1.4
DDR_B_DQSB_0
DDR_B_DQSB_1
DDR_B_DQSB_2
DDR_B_DQSB_3
DDR_B_DQSB_4
DDR_B_DQSB_5
DDR_B_DQSB_6
DDR_B_DQSB_7
3
DDR_B_DQS_0
DDR_B_DM_0
DDR_B_DQ_0
DDR_B_DQ_1
DDR_B_DQ_2
DDR_B_DQ_3
DDR_B_DQ_4
DDR_B_DQ_5
DDR_B_DQ_6
DDR_B_DQ_7
DDR_B_DQS_1
DDR_B_DM_1
DDR_B_DQ_8
DDR_B_DQ_9
DDR_B_DQ_10
DDR_B_DQ_11
DDR_B_DQ_12
DDR_B_DQ_13
DDR_B_DQ_14
DDR_B_DQ_15
DDR_B_DQS_2
DDR_B_DM_2
DDR_B_DQ_16
DDR_B_DQ_17
DDR_B_DQ_18
DDR_B_DQ_19
DDR_B_DQ_20
DDR_B_DQ_21
DDR_B_DQ_22
DDR_B_DQ_23
DDR_B_DQS_3
DDR_B_DM_3
DDR_B_DQ_24
DDR_B_DQ_25
DDR_B_DQ_26
DDR_B_DQ_27
DDR_B_DQ_28
DDR_B_DQ_29
DDR_B_DQ_30
DDR_B_DQ_31
DDR_B_DQS_4
o
o
DDR_B_DM_4
DDR_B_DQ_32
DDR_B_DQ_33
DDR_B_DQ_34
DDR_B_DQ_35
DDR_B_DQ_36
DDR_B_DQ_37
DDR_B_DQ_38
DDR_B_DQ_39
DDR_B_DQS_5
DDR_B_DM_5
DDR_B_DQ_40
DDR_B_DQ_41
DDR_B_DQ_42
DDR_B_DQ_43
DDR_B_DQ_44
DDR_B_DQ_45
DDR_B_DQ_46
DDR_B_DQ_47
DDR_B_DQS_6
DDR_B_DM_6
DDR_B_DQ_48
DDR_B_DQ_49
DDR_B_DQ_50
DDR_B_DQ_51
DDR_B_DQ_52
DDR_B_DQ_53
DDR_B_DQ_54
DDR_B_DQ_55
DDR_B_DQS_7
DDR_B_DM_7
DDR_B_DQ_56
DDR_B_DQ_57
DDR_B_DQ_58
DDR_B_DQ_59
DDR_B_DQ_60
DDR_B_DQ_61
DDR_B_DQ_62
DDR_B_DQ_63
AW8
AW9
AY6
M_CHB_D Q0
AV7
M_CHB_D Q1
AW4
M_CHB_D Q2
BA9
M_CHB_D Q3
AU11
M_CHB_D Q4
AU7
M_CHB_D Q5
AU8
M_CHB_D Q6
AW7
M_CHB_D Q7
AY9
AT15
AU15
AR15
M_CHB_D Q8
AY13
M_CHB_D Q9
AP15
M_CHB_D Q10
AW15
M_CHB_D Q11
AT16
M_CHB_D Q12
AU13
M_CHB_D Q13
AW13
M_CHB_D Q14
AP16
M_CHB_D Q15
AU16
AR20
AR17
AU17
M_CHB_D Q16
AY17
M_CHB_D Q17
AV17
M_CHB_D Q18
AR21
M_CHB_D Q19
AV20
M_CHB_D Q20
AP17
M_CHB_D Q21
AW16
M_CHB_D Q22
AT20
M_CHB_D Q23
AN20
AU26
AT26
AV25
M_CHB_D Q24
AT25
M_CHB_D Q25
AV26
M_CHB_D Q26
AU29
M_CHB_D Q27
AV29
M_CHB_D Q28
AW25
M_CHB_D Q29
AR25
M_CHB_D Q30
n
n
AP26
M_CHB_D Q31
AR29
AR38
AR37
AU39
M_CHB_D Q32
AR36
M_CHB_D Q33
AU38
M_CHB_D Q34
AN35
M_CHB_D Q35
AN37
M_CHB_D Q36
AV39
M_CHB_D Q37
AW39
M_CHB_D Q38
AU40
M_CHB_D Q39
AU41
AK34
AL34
AL37
AL35
M_CHB_D Q41
AL36
M_CHB_D Q42
AK36
M_CHB_D Q43
AJ34
M_CHB_D Q44
AN39
M_CHB_D Q45
AN40
M_CHB_D Q46
AK37
M_CHB_D Q47
AL39
AF37
AF36
AJ35
M_CHB_D Q48
AJ38
M_CHB_D Q49
AJ37
M_CHB_D Q50
AF38
M_CHB_D Q51
AE37
M_CHB_D Q52
AK40
M_CHB_D Q53
AJ40
M_CHB_D Q54
AF34
M_CHB_D Q55
AE35
AB35
AD35
AD37
M_CHB_D Q56
AD40
M_CHB_D Q57
AD38
M_CHB_D Q58
AB40
M_CHB_D Q59
AA39
M_CHB_D Q60
AE36
M_CHB_D Q61
AE39
M_CHB_D Q62
AB37
M_CHB_D Q63
AB38
Add DIMM B to
FS
d
d
i
i
f
f
2
M_CHB_D QS1 [18]
M_CHB_D QS1# [18]
M_CHB_D M1 [18]
M_CHB_D QS2 [18]
M_CHB_D QS2# [18]
M_CHB_D M2 [18]
e
e
M_CHB_D QS3 [18]
M_CHB_D QS3# [18]
M_CHB_D M3 [18]
M_CHB_D QS4 [18]
M_CHB_D QS4# [18]
M_CHB_D M4 [18]
M_CHB_D QS5 [18]
M_CHB_D QS5# [18]
M_CHB_D M5 [18]
M_CHB_D QS6 [18]
M_CHB_D QS6# [18]
M_CHB_D M6 [18]
M_CHB_D QS7 [18]
M_CHB_D QS7# [18]
M_CHB_D M7 [18]
2
M_CHB_D QS0 [18]
M_CHB_D QS0# [18]
M_CHB_D M0 [18]
t
t
n
n
1
M_CHB_DQ[ 0..63] [18]
l
l
a
a
i
i
PEGATRON DT-MB RESTRICTED SECRET
Title :
Title :
Title :
EAGLELAKE 3 - 7
EAGLELAKE 3 - 7
EAGLELAKE 3 - 7
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Pr oject Name
Size Pr oject Name
Size Pr oject Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Engineer:
IPX41-D3
IPX41-D3
IPX41-D3
1
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
Rev
Rev
Rev
1.02
1.02
12 54Thursday, December 10, 2009
12 54Thursday, December 10, 2009
12 54Thursday, December 10, 2009
1.02
Page 13
5
NRN25A 8.2K
FSBSEL0[6,8]
FSBSEL1[6,8]
D D
Add PCIE_B4 for DVI and HDMI to FS
PCIE_B4[25,27,28,29]
EXP_EN_H DR[25]
NOTE:
C C
DUALX8 1x16 PCIe 2x8 PCIe DUALX8 ENABLE
MTYPE NOT
EXP_SLR
ITPM_EN#
+1P1V_C L
12
B B
12
GND GND
A A
1 2
NOBOM
NOBOM
HIGH DESCRIPTIONLOWPIN
CONCURRENT
PRESENCE
NORMAL
ATX
ENABLE
I
I
NR35
NR35
1K
1K
CLINK VREF TARGET=0.349V
1%
1%
12
I
I
I
I
NR38
NR38
NCB8
NCB8
470
470
0.1UF/16V
0.1UF/16V
1%
1%
5
FSBSEL2[6,8]
NR661K
NR661K
12
NI
NI
NR760
NR760
12
NI
NI
NR30
NR30
1K
1K
GND
CONCURRENT
PRESENCE PCIe CARD IN
BTX
DISABLETCEN TLS CONFIDENTAL ITY
NRN25A 8.2K
NRN25B 8.2K
NRN25B 8.2K
NRN25C 8.2K
NRN25C 8.2K
NOBOM
NOBOM
NOBOM
NOBOM
12
NI
NI
NR75
NR75
1K
1K
PCI-E/SDVOEXP_SM NOT
PRIMARY SLOT
PCI-E LANE RESE RVALRESERVE
iTPM EnableENABLEDI SABLE
PLTRST#[22,39,43]
PWR GD_SIO_OUT[22,39]
P
P
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NRN25D 8.2K
NRN25D 8.2K
12
NI
NI
NR32
NR32
1K
1K
12
34
56
78
NT13
NT13
NT14
NT14
1
1
TPC26b
TPC26b
TPC26b
TPC26b
12
NI
NI
NR22
NR22
1K
1K
NR80 3KI1%NR80 3KI1%
1 2
2009.08.14 shawn
NR80 from 3K 5% change to 3K 1%.
e
e
NT38
NT38
NT39
NT39
1
NT40
NT40
1
TPC26b
TPC26b
NT41
NT41
1
TPC26b
TPC26b
1
TPC26b
TPC26b
TPC26b
TPC26b
I
I
I
I
I
I
I
I
12
NI
NI
NR23
NR23
1K
1K
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
g
g
GND
12
12
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
TPC26b
4
NI
NI
NR24
NR24
1K
1K
NT15
NT15
NT16
NT16
1
NT17
NT17
1
NT25
NT25
1
NT18
NT18
1
NT19
NT19
1
NT20
NT20
1
NT21
NT21
1
NT22
NT22
1
NT23
NT23
1
NT24
NT24
1
NT27
NT27
1
NT28
NT28
1
NT29
NT29
1
NT30
NT30
1
NT31
NT31
1
NT32
NT32
1
NT33
NT33
1
NT34
NT34
1
NT35
NT35
1
NT36
NT36
1
1
CL_VREF
CL_RST#
I
I
a
a
NR81
NR81
1.5K
1.5K
TP_MCH _A45
TP_MCH_ B2
TP_MCH_ BE1
TP_MCH_ BE45
4
MCH_BS EL0
MCH_BS EL1
MCH_BS EL2
EXP_EN
DUALX8_ EN
TP_MCH_ M20
TP_MCH_ N17
MTYPE
EXP_SM
EXP_SLR
ITPM_EN#
TCEN
12
NI
NI
NR28
NR28
1K
1K
GNDG NDGND GND GNDGND
TP_MCH_ M17
TP_MCH_ G20
TP_MCH_ J16
TP_MCH_ M16
TP_MCH_ J15
TP_MCH_ J20
TP_MCH_ AR7
TP_MCH_ AN10
TP_MCH_ AN11
TP_MCH_ AN9
TP_MCH_ R31
TP_MCH_ R32
TP_MCH_ U30
TP_MCH_ U31
TP_MCH_ R15
TP_MCH_ R14
TP_MCH _T15
TP_MCH _T14
TP_MCH_ AB15
TP_MCH _L13
TP_MCH _L11
t
t
F17
G16
P15
G15
F20
M20
N17
K16
H17
F15
L17
J17
AN17
A44
BD1
BD45
BE2
BE44
B14
B45
AK15
AD42
AN16
W30
AW44
R42
U32
M17
G20
J16
M16
J15
J20
AR7
AN10
AN11
AN9
R31
R32
U30
U31
R15
R14
T15
T14
AB15
L13
L11
AN13
AY4
AY2
AW2
r
r
AN8
A45
B2
BE1
BE45
I
I
NU1E
NU1E
BSEL0
BSEL1
BSEL2
RSVD12
DUALX8_Enable
ALLZTEST
XORTEST
RSVD16
EXP_SM
EXP_SLR
ITPM_ENB
CEN
NC9
NC1
NC13
NC14
NC15
NC16
NC11
NC12
NC7
NC4
NC8
NC19
NC10
NC17
NC18
RSVD20
BSCANTEST
RSVD14
RSVD19
RSVD13
RSVD15
JTAG_TDI
JTAG_TDO
JTAG_TCK
JTAG_TMS
RSVD24
RSVD25
RSVD28
RSVD29
RSVD23
RSVD22
RSVD27
RSVD26
RSVD3
RSVD18
RSVD17
CL_VREF
o
o
CL_DATA
CL_CLK
CL_RSTB
CL_PWROK
RSVD1
RSVD9
RSVD10
RSVD11
EAGLELA KE
EAGLELA KE
DPL_REFSSCLKINP
DPL_REFSSCLKINN
n
n
MISC
MISC
REV=1.4
REV=1.4
CRT_HSYNC
CRT_VSYNC
CRT_RED
CRT_GREEN
CRT_BLUE
CRT_IRTN
VGA
VGA
CRT_DDC_DATA
CRT_DDC_CLK
DAC_IREF
DPL_REFCLKINP
DPL_REFCLKINN
C
C
RSTINB
PWROK
ICH_SYNCB
HDA_BCLK
HDA_RSTB
HDA_SDI
HDA_SDO
HDA_SYNC
DDPC_CTRLCLK
DDPC_CTRLDATA
DPRSTPB
SLPB
3
VGA_HSYN C_3P3V
D14
VGA_VSYN C_3P3V
C14
B18
D18
C18
F13
L15
M15
DACREFS ET
B15
PLACED RESISTOR
CLOSE TO THE GM CH
WITHIN 500 MIL
LENGTH
E15
o
o
D15
DPL_REF SSCLKP
G8
G9
AN6
PWR OK_R
AR4
K15
AU4
AV4
R_SDATA_ IN1
AU2
AV1
AU3
NOTE:
For port C
HDMI PORTC DDC Control CLK
HDMI PORTC DDC Control DATA
J11
F11
NB_DPRS TP#
P43
NB_SLP#
P42
3
I
I
I
I
2009.09.28 shawn
NC1, NC2, NC3 from NI change to 10pF for EMI issue.
PLACED CAPACITO R CLOSE TO
GMCH FOR EMI
n
n
NR37 0
NR37 0
VP
VP
DDPC_CT RL_CLK [25, 29]
DDPC_CT RL_DATA [25, 29]
NT44
NT44
1
TPC26b
TPC26b
NR18 33
NR18 33
1 2
NR21 33
NR21 33
1 2
12
f
f
NOBOM
NOBOM
12
I
I
NC1
NC1
10PF/50V
10PF/50V
NPO 5%
NPO 5%
I
I
I
I
NC2
NC2
10PF/50V
10PF/50V
NPO 5%
NPO 5%
12
d
d
NR33
NR33
1K
1K
i
i
1%
1%
GND
12
NR44 33
NR44 33
1 2
12
GNDGND GNDGND
e
e
I
I
CK_96M_ DREF [ 6]
CK_96M_ DREF# [6]
PWR GD_SIO_OUT [22, 39]
ICH_SYNC# [22]
+VTT_O UT_L
12
I
I
SR29
SR29
49.9
49.9
1%
1%
2
VGA_HSYNC [26]
VGA_VSYNC [26]
1 2
VGA_RED _NB
VGA_GRE EN_NB
VGA_BLU E_NB
12
12
I
I
I
I
NR25
NR25
NR26
I
I
NC3
NC3
10PF/50V
10PF/50V
NPO 5%
NPO 5%
GND GND
i
i
PLACED RESISTOR CLOSE TO
t
t
GMCH WITHIN 250 MIL LENGTH
n
n
DDCA_DA TA [26]
DDCA_CL K [26 ]
NOTE:
Change NR33 and NR25~NR27 to 0 OHM for non-Graphics SKU,
KEEP PU resistor VR14~15 for DDCDATA/CLK
+1P1V_C ORE
12
I
I
NR39
NR39
10K
10K
GND
12
NI
NI
SCB49
SCB49
10PF/50V
10PF/50V
NPO 5%
NPO 5%
GND
BITCLK_MC H [22]
AZRST#_M CH [22]
SDATA_IN 1 [22]
SDATA_OU T_MCH [22]
AZ_SYNC_MC H [22]
If not support C3/C4,
NC DPRSTP# and pull high
Refer to Eaglelake PDG 2.0
2
NR26
150
150
150
150
1%
1%
1%
1%
l
l
a
a
NOTE:
PIN G8 G9 are required to be connected
to 100MHz SRC of CK505 if Display Port
supported.
Add for HDMI to FS
PEGATRON DT-MB RESTRICTED SECRET
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Pr oject Name
Size Pr oject Name
Size Pr oject Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
1 2
1 2
12
I
I
NR27
NR27
150
150
1%
1%
GND
PLTRST# [22 ,39,43]
IPX41-D3
IPX41-D3
IPX41-D3
1
NOBOM
NOBOM
PJP14
PJP14
SHORTPIN
SHORTPIN
NOBOM
NOBOM
PJP15
PJP15
SHORTPIN
SHORTPIN
NOBOM
NOBOM
PJP16
PJP16
SHORTPIN
SHORTPIN
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
1
VGA_RED [26]
VGA_GRE EN [26]
VGA_BLUE [26]
EAGLELAKE 4 - 7
EAGLELAKE 4 - 7
EAGLELAKE 4 - 7
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
13 54Thursday, December 10, 2009
13 54Thursday, December 10, 2009
13 54Thursday, December 10, 2009
Rev
Rev
Rev
1.02
1.02
1.02
Page 14
5
+1P1V_C ORE
D D
+1P1V_C ORE
+1P1V_C ORE
C C
+1P1V_C ORE
+1P1V_C ORE
+1P1V_C ORE
B B
A A
I
I
NL7
NL7
2.2UH/25 0mA
2.2UH/25 0mA
mx_l0805
mx_l0805
21
NL5
NL5
0.27UH/1 70mAImx_l0603
0.27UH/1 70mAImx_l0603
21
12
I
I
NCB31
NCB31
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
12
NI
NI
NCB34
NCB34
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
5
12
NI
NI
NCB32
NCB32
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
12
I
I
NCB35
NCB35
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
12
GNDGND GND
12
GNDGND GND
I
I
NCB33
NCB33
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
NI
NI
NCB36
NCB36
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
+1P1V_C ORE
12
NI
NI
NCB37
NCB37
P
P
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
e
e
4
g
g
+1P5V_ICH
4
12
NI
NI
NCB9
NCB9
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
GND
12
NI
NI
NCB13
NCB13
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
GND
12
I
I
NCB18
NCB18
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
GND
12
I
I
NCE1
NCE1
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
GND GND
12
I
I
NCE2
NCE2
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
GND
t
t
a
a
12
GND
12
GND
12
GND
12
12
GND
r
r
+1P1V_G PLLD
NI
NI
NCB10
NCB10
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
NI
NI
NCB14
NCB14
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
I
I
NCB23
NCB23
2.2UF/6.3 V
2.2UF/6.3 V
X5R 10%
X5R 10%
mx_c0603
mx_c0603
I
I
NCB27
NCB27
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
I
I
NCB30
NCB30
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
+1P1V_G PLL
+1P1V_M PLL
+1P1V_H PLL
+1P1V_D PLLB
+1P1V_D PLLA
o
o
+3P3V
12
NI
NI
NCB38
NCB38
4.7UF/6.3 V
4.7UF/6.3 V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
GND GND
n
n
+1P1V_C L
12
I
I
NCB39
NCB39
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
C
C
3
3
+1P1V_C ORE
o
o
+1P1V_H PLL_D
AA19
AA21
AA23
AA25
AA27
AA29
AA30
AB20
AB22
AB24
AB26
AB29
AB30
AC16
AC17
AC19
AC21
AC23
AC25
AC27
AC29
AD16
AD17
AD20
AD22
AD24
AD26
AD29
AE16
AE17
AE19
AE21
AE23
AE25
AE27
AE29
AF16
AF17
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
AF27
AF29
n
n
AG16
AG17
AG20
AG22
AG24
AG26
AG29
AJ16
AJ17
AJ19
AJ21
AJ23
AJ25
I
I
NU1F
NU1F
f
f
R25
B12
B16
A21
B22
U33
C20
D20
E19
AR2
EAGLELA KE
EAGLELA KE
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
d
d
VCC41
VCC42
i
i
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC68
VCCDPLL_EXP
VCCAPLL_EXP
VCCA_MPLL
VCCA_HPLL
VCCD_HPLL
VCCA_DPLLB
VCCA_DPLLA
VCC3_3
VCC_HDA
REV=1.4
REV=1.4
VCC69
VCC70
VCC71
VCC72
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC73
VCC74
VCC22
VCC50
VCC64
VCC65
VCC66
VCC67
e
e
VCC88
POWER
POWER
VCC_EXP1
VCC_EXP2
VCC_EXP3
VCC_EXP4
VCC_EXP5
VCC_EXP6
VCC_EXP7
VCC_EXP8
VCC_EXP9
VCC_EXP10
VCC_EXP11
VCC_EXP13
VCC_EXP14
VCC_EXP15
VCC_EXP16
VCC_EXP17
VCC_EXP19
VCC_EXP20
VCC_EXP21
VCC_EXP22
VCC_EXP23
VCC_EXP24
VCC_EXP25
VCC_EXP26
VCC_EXP30
VCC_EXP31
VCC_EXP32
VCC_EXP33
VCC_EXP34
VCC_EXP35
VCC_EXP36
VCC_EXP37
VCC_EXP38
VCC_EXP12
VCC_EXP18
VCC_EXP27
VCC_EXP28
VCC_EXP29
VCCAVRM_EXP
2
R26
R27
R29
T21
T24
T25
T26
T27
T29
U21
U22
U23
U24
U25
U26
U27
U29
W19
W21
W23
W25
W27
W29
Y20
Y22
Y24
Y26
T22
T23
AC4
AF3
F9
n
n
H4
L3
P3
V4
AA14
AA15
AB14
AC15
AD14
AD15
AE14
AE15
AF14
AF15
AG15
AJ10
AJ11
AJ12
AJ13
AJ14
AJ6
AJ7
AJ8
AJ9
AK10
AK11
AK12
AK13
AK6
AK7
AK8
AK9
U14
U15
W15
Y14
Y15
AJ1
AJ2
AK2
AK3
AK4
AG2
2
2009.08.14 shawn
NCB11, NCB12, NCB24 from 22uF 20% (11X23A226160)
change to 22uF 10% (11X23A226150)
+1P1V_C ORE
12
12
GND
i
i
12
t
t
GND
12
I
I
NCB65
NCB65
4.7UF/6.3 V
4.7UF/6.3 V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
2009.08.19 shawn
NCB65, NCB28, NCB29 from 2.2uF change to 4.7uF.
VCCAVR M_EXP_RVCC_AZA
12
NI
NI
NCB76
NCB76
4.7UF/6.3 V
4.7UF/6.3 V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
GND
I
I
I
I
NCB11
NCB11
NCB24
NCB24
10UF/6.3V
10UF/6.3V
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
X5R 10%
X5R 10%
mx_c1206
mx_c1206
mx_c1206
mx_c1206
GND
l
l
a
a
12
I
I
I
I
NCB19
NCB19
NCB20
NCB20
1UF/16V
1UF/16V
1UF/16V
1UF/16V
X7R 10%
X7R 10%
X7R 10%
X7R 10%
mx_c0603
mx_c0603
mx_c0603
mx_c0603
GND
+1P1V_PC IEXPRESS
12
I
I
NCB28
NCB28
4.7UF/6.3 V
4.7UF/6.3 V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
VP
VP
+1P1V_C ORE
NR79
NR79
0
0
mx_r0603
mx_r0603
1 2
NI
NI
+1P5V_ICH
NR78
NR78
0
0
mx_r0603
mx_r0603
1 2
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Pr oject Name
Size Pr oject Name
Size Pr oject Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
GND
GND
12
I
I
NCB12
NCB12
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c1206
mx_c1206
12
I
I
NCB16
NCB16
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
12
GNDGNDGND
I
I
NCB29
NCB29
4.7UF/6.3 V
4.7UF/6.3 V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
Engineer:
Engineer:
Engineer:
IPX41-D3
IPX41-D3
IPX41-D3
1
NOBOM
NOBOM
NJP1
NJP1
SHORTPIN _RECT
SHORTPIN _RECT
NOBOM
NOBOM
NJP2
NJP2
SHORTPIN _RECT
SHORTPIN _RECT
NOBOM
NOBOM
NJP5
NJP5
SHORTPIN _RECT
SHORTPIN _RECT
NOBOM
NOBOM
NJP6
NJP6
SHORTPIN _RECT
SHORTPIN _RECT
Title :
Title :
Title :
1
+1P1V_C ORE
12
12
12
12
EAGLELAKE 5 - 7
EAGLELAKE 5 - 7
EAGLELAKE 5 - 7
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
14 54Thursday, December 10, 2009
14 54Thursday, December 10, 2009
14 54Thursday, December 10, 2009
Rev
Rev
Rev
1.02
1.02
1.02
Page 15
5
4
3
2
1
12
I
I
NCB46
NCB46
2.2UF/6.3 V
2.2UF/6.3 V
X5R 10%
X5R 10%
mx_c0603
mx_c0603
12
I
I
NCB42
NCB42
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
12
I
I
NCB57
NCB57
2.2UF/6.3 V
2.2UF/6.3 V
X5R 10%
X5R 10%
mx_c0603
mx_c0603
a
a
12
NI
NI
NCB75
NCB75
1UF/16V
1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
4
+1P1V_FS B_VTT
12
NI
NI
NCB67
NCB67
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
t
t
VCCCML_ DDR
r
r
o
o
GND
Place near GMCH
I
I
NCB40
NCB40
2.2UF/6.3 V
2.2UF/6.3 V
X5R 10%
X5R 10%
mx_c0603
mx_c0603
NI
NI
NCB49
NCB49
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
I
I
NCB55
NCB55
2.2UF/6.3 V
2.2UF/6.3 V
X5R 10%
X5R 10%
mx_c0603
mx_c0603
I
I
NR60
NR60
40.2
40.2
1%
1%
mx_r0603
mx_r0603
I
I
NR62
NR62
39.2
39.2
1%
1%
mx_r0603
mx_r0603
I
I
NL12
NL12
0.1UH/30 0mA
0.1UH/30 0mA
mx_l0603
mx_l0603
12
I
I
NCB45
NCB45
2.2UF/6.3 V
2.2UF/6.3 V
X5R 10%
X5R 10%
mx_c0603
mx_c0603
12
NI
NI
NCB41
NCB41
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
12
I
I
NCB56
NCB56
2.2UF/6.3 V
2.2UF/6.3 V
X5R 10%
X5R 10%
mx_c0603
mx_c0603
GND GNDGND
12
I
I
NCB62
NCB62
1UF/16V
1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
GNDGND
e
e
21
GNDGNDGND
GNDGNDGND
g
g
GND
D D
C C
+1P5V_D UAL
12
I
I
NCB43
NCB43
2.2UF/6.3 V
2.2UF/6.3 V
X5R 10%
X5R 10%
mx_c0603
mx_c0603
+3P3V
NL10
NL10
0.27UH/1 70mAImx_l0603
0.27UH/1 70mAImx_l0603
B B
A A
Place a via in between cap and GMCH on
GND trace.It means that the GND fo r cap
has to be independent
12
I
I
NCB53
NCB53
2.2UF/6.3 V
2.2UF/6.3 V
X5R 10%
X5R 10%
mx_c0603
mx_c0603
21
+1P5V_ICH
+1P1V_C L
+3P3V_D AC_FB
5
12
12
+
+
12
I
I
NCB54
NCB54
2.2UF/6.3 V
2.2UF/6.3 V
X5R 10%
X5R 10%
mx_c0603
mx_c0603
GNDGNDGND GND
I
I
12
NCE3
NCE3
330UF/6.3 V
330UF/6.3 V
GND GND
12
12
12
I
I
NCB44
NCB44
2.2UF/6.3 V
2.2UF/6.3 V
X5R 10%
X5R 10%
mx_c0603
mx_c0603
2009.09.29 shawn
NL10 from short-pin change to 0.27uF
NCE3 from NI change to I
Add NCB66 and NCB67
Remove NR58 short pin
I
I
NCB66
NCB66
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
12
mx_c0805
mx_c0805
12
GND
P
P
I
I
NU1G
NU1G
A25
VTT_FSB1
B25
VTT_FSB2
B26
VTT_FSB3
C24
VTT_FSB4
C26
VTT_FSB5
D22
VTT_FSB6
D23
VTT_FSB7
D24
VTT_FSB8
E23
VTT_FSB9
F21
VTT_FSB10
F22
VTT_FSB11
G21
VTT_FSB12
G22
VTT_FSB13
H21
VTT_FSB14
H22
VTT_FSB15
J21
VTT_FSB16
J22
VTT_FSB17
K21
VTT_FSB18
K22
VTT_FSB19
L21
VTT_FSB20
L22
VTT_FSB21
M21
VTT_FSB22
M22
VTT_FSB23
N20
VTT_FSB24
N21
VTT_FSB25
N22
VTT_FSB26
P20
VTT_FSB27
P21
VTT_FSB28
P22
VTT_FSB29
P24
VTT_FSB30
R20
VTT_FSB31
R21
VTT_FSB32
R22
VTT_FSB33
R23
VTT_FSB34
R24
VTT_FSB35
AP44
VCC_SM1
AT45
VCC_SM2
AV44
VCC_SM3
AY40
VCC_SM4
BA41
VCC_SM5
BB39
VCC_SM6
BD21
VCC_SM7
BD25
VCC_SM8
BD29
VCC_SM9
BD34
VCC_SM10
BD38
VCC_SM11
BE23
VCC_SM12
BE27
VCC_SM13
BE31
VCC_SM14
BE36
VCC_SM15
B19
VCCA_DAC1
D19
VCCA_DAC2
n
n
A17
VCCA_EXP
B20
VCCDQ_CRT
B17
VSS179
AM30
VCCCML_DDR
EAGLELA KE
EAGLELA KE
C
C
REV=1.4
REV=1.4
3
VCC_SMCLK1
VCC_SMCLK2
VCC_SMCLK3
VCC_SMCLK4
VCC_CL2
VCC_CL3
VCC_CL5
VCC_CL6
VCC_CL9
VCC_CL10
VCC_CL12
VCC_CL13
VCC_CL15
VCC_CL23
VCC_CL38
VCC_CL58
VCC_CL65
VCC_CL66
VCC_CL67
VCC_CL69
VCC_CL70
VCC_CL71
VCC_CL72
VCC_CL73
VCC_CL74
VCC_CL75
VCC_CL84
VCC_CL85
VCC_CL78
VCC_CL79
VCC_CL83
VCC_CL1
VCC_CL4
VCC_CL7
VCC_CL8
VCC_CL11
VCC_CL14
VCC_CL16
VCC_CL17
VCC_CL21
VCC_CL22
VCC_CL25
o
o
VCC_CL26
VCC_CL27
VCC_CL28
VCC_CL29
VCC_CL30
VCC_CL31
VCC_CL32
VCC_CL33
VCC_CL34
VCC_CL35
VCC_CL36
VCC_CL37
VCC_CL39
VCC_CL40
VCC_CL41
VCC_CL55
VCC_CL42
VCC_CL44
VCC_CL46
VCC_CL47
VCC_CL48
VCC_CL49
VCC_CL50
VCC_CL51
VCC_CL52
VCC_CL45
VCC_CL53
VCC_CL54
VCC_CL56
VCC_CL57
VCC_CL59
VCC_CL60
VCC_CL61
VCC_CL62
VCC_CL63
VCC_CL64
VCC_CL68
VCC_CL76
VCC_CL77
VCC_CL43
VCC_CL18
VCC_CL24
VCC_CL19
VCC_CL20
VCC_CL80
VCC_CL82
VCC_CL81
AK32
AL31
AL32
AM31
AA32
AA33
AB32
AB33
AD32
AD33
AE32
AE33
AF32
AJ32
AK31
AL30
AM15
AM16
AM17
AM20
AM21
AM22
AM24
AM25
AM26
AM29
Y32
Y33
AP1
AP2
Y31
AA31
AB31
AC31
AD31
AE31
AF31
AG30
n
n
AG31
AJ30
AJ31
AK16
AK17
AK19
AK20
AK21
AK22
AK23
AK24
AK25
AK26
AK27
AK29
AK30
AL1
AL10
AL11
AL26
AL12
AL15
AL17
AL19
AL2
AL20
AL21
AL22
AL23
AL16
AL24
AL25
AL27
AL29
AL4
AL5
AL6
AL7
AL8
AL9
AM2
AM3
AM4
AL14
AJ15
AK14
AJ27
AJ29
W31
Y30
Y29
f
f
VCCCK_D DR
d
d
i
i
12
I
I
NCB47
NCB47
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
BOTTOM
BOTTOM
GND
n
n
e
e
12
NI
NI
NCB50
NCB50
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
BACKSIDE CAPS F OR SPECIFIC +1P1V_C ORE GMCH
2
NI
NI
NR57 1
NR57 1
1 2
BOTTOM
NI
NI
+1P1V_C L +1P1V_C ORE
i
i
t
t
12
I
I
NCB51
NCB51
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
GND GND
12
NI
NI
NCB63
NCB63
1UF/16V
1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
BOTTOM
BOTTOM
GND
12
NI
NI
NCB71
NCB71
1UF/16V
1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
BOTTOM
BOTTOM
GND GND GND
BOTTOM
NR56 1
NR56 1
1 2
BOTTOM
BOTTOM
l
l
a
a
NOBOM
NOBOM
NJP9
NJP9
12
SHORTPIN _RECT
SHORTPIN _RECT
NOBOM
NOBOM
NJP8
NJP8
12
SHORTPIN _RECT
SHORTPIN _RECT
NOBOM
NOBOM
NJP7
NJP7
12
SHORTPIN _RECT
SHORTPIN _RECT
12
I
I
NCB52
NCB52
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
12
GND
12
12
NI
NI
NI
NCB64
NCB64
1UF/16V
1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
BOTTOM
BOTTOM
NI
NI
NCB72
NCB72
1UF/16V
1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
BOTTOM
BOTTOM
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Date: Sheet of
Date: Sheet of
Date: Sheet of
NI
NCB69
NCB69
1UF/16V
1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
BOTTOM
BOTTOM
GND
PEGATRON DT-MB RESTRICTED SECRET
Size Pr oject Name
Size Pr oject Name
Size Pr oject Name
A3
A3
A3
V_CKDDR _R
12
NI
NI
NCB70
NCB70
1UF/16V
1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
BOTTOM
BOTTOM
GND
12
NI
NI
NCB74
NCB74
1UF/16V
1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
BOTTOM
BOTTOM
IPX41-D3
IPX41-D3
IPX41-D3
+1P5V_D UAL
12
GND
+1P1V_C ORE
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
1
NI
NI
NCB48
NCB48
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
BOTTOM
BOTTOM
EAGLELAKE 6 - 7
EAGLELAKE 6 - 7
EAGLELAKE 6 - 7
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
15 54Thursday, December 10, 2009
15 54Thursday, December 10, 2009
15 54Thursday, December 10, 2009
Rev
Rev
Rev
1.02
1.02
1.02
Page 16
5
NU1H
I
NU1H
I
A12
VSS1
A15
VSS2
A19
VSS3
A27
VSS4
A31
VSS6
A36
VSS7
A40
VSS8
D D
C C
B B
A A
AA1
AA11
AA12
AA13
AA20
AA22
AA24
AA26
AA34
AA38
AA40
AA44
AA8
AB11
AB12
AB19
AB21
AB23
AB25
AB27
AB34
AB36
AB39
AB4
AB6
AB7
AB8
AC20
AC22
AC24
AC26
AC45
AC5
AD12
AD19
AD21
AD23
AD25
AD27
AD3
AD34
AD36
AD39
AD6
AD9
AE1
AE11
AE20
AE22
AE24
AE26
AE34
AE38
AE40
AE44
AE8
AF10
AF11
AF12
AF13
AF33
AF35
AF39
AG19
AG21
AG23
AG25
AG27
AG45
AG5
AH2
AH3
AH4
AJ20
AJ22
AJ24
AU20
AA16
AA17
AB16
AB17
AF6
AF7
N16
P16
P17
R16
R17
R19
R30
VSS12
VSS13
VSS14
VSS15
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS143
VSS16
VSS17
VSS29
VSS30
VSS286
VSS294
VSS295
VSS301
VSS302
VSS303
VSS305
EAGLELA KE
EAGLELA KE
5
GND
GND
REV=1.4
REV=1.4
VSS116
VSS118
VSS119
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS172
VSS142
VSS144
VSS145
VSS146
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS159
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS173
VSS174
VSS175
VSS176
VSS177
VSS180
VSS181
VSS182
VSS183
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS193
VSS194
VSS196
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS206
VSS207
VSS158
VSS211
VSS213
VSS251
VSS100
VSS99
VSS98
VSS97
VSS96
VSS359
VSS358
VSS345
VSS344
VSS338
VSS337
VSS336
VSS335
VSS319
VSS317
VSS316
VSS315
VSS314
AP20
AP22
AP24
AP29
AP45
AR10
AR11
AR13
AR16
AR26
AR3
AR31
AR33
AR35
AR39
AR8
AR9
AT1
AT11
AT13
AT17
AT2
AT24
AT29
AY15
AT35
AU22
AU25
AU30
AU9
AV11
AV13
AV15
AV16
AV2
AV21
AV30
AV38
AV8
AV9
AW11
AW17
AW20
AW22
AW24
AW26
AW3
AW30
AY1
AY16
AY21
AY25
AY30
AY45
B21
B27
B29
B34
BA23
BA5
BB21
BB25
BB28
BB6
BD12
BD17
BD43
BD8
BE10
BE15
BE19
BE21
BE25
BE29
BE34
BE40
AV33
C3
C5
H38
AJ45
AJ44
AJ39
AJ36
AJ26
Y17
Y16
W17
W16
P
P
U20
U19
U17
U16
T30
T20
T19
T17
T16
e
e
GNDGND
4
g
g
4
a
a
AK35
AK38
AK39
AL38
AL44
AL45
AN33
AN36
AN38
t
t
AN7
A8
D11
D16
D21
D25
D26
D39
D6
D7
B10
E3
E31
E41
E5
F16
F2
F30
F4
F42
F45
F8
G11
G17
G24
G26
G29
G3
G35
H1
H11
H13
H15
H16
H20
H25
H30
H31
H33
H44
H7
H8
H9
J3
J37
J4
J5
J8
J9
K11
K13
K17
K20
K24
K29
K33
K45
L10
r
r
L16
L20
L26
L30
L35
L39
L4
L8
L9
M1
M24
M25
M44
N11
N13
N26
N29
N30
N33
N36
F1
C45
C1
I
I
NU1I
NU1I
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS112
VSS113
VSS114
VSS115
VSS11
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS178
VSS222
VSS223
VSS224
VSS225
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
o
o
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS287
VSS288
VSS289
VSS290
VSS291
VSS226
VSS212
VSS209
EAGLELA KE
EAGLELA KE
GND
GND
REV=1.4
REV=1.4
VSS160
VSS149
VSS148
VSS120
VSS117
VSS111
VSS210
VSS292
VSS293
VSS296
VSS297
VSS298
VSS299
VSS300
VSS304
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS318
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS339
VSS340
VSS341
VSS342
VSS343
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS360
VSS361
VSS362
VSS363
n
n
VSS364
VSS365
VSS366
VSS367
VSS368
VSS369
VSS108
VSS64
VSS109
VSS147
VSS110
VSS63
VSS107
VSS5
VSS9
VSS10
VSS184
VSS191
VSS192
VSS195
VSS197
VSS205
VSS208
NC3
NC2
NC6
NC5
AV6
AU6
AU5
AP25
AP21
AN26
C16
N38
N8
P25
P26
P31
R11
R12
R2
R38
R45
R5
R8
T10
T11
T12
T13
T3
T31
T32
T33
T35
T38
T4
T40
T6
T7
T8
T9
U1
U11
U12
U13
U36
U39
U44
U8
W1
W2
W20
W22
W24
W26
W44
W45
W5
Y10
Y11
C
C
Y12
Y13
Y19
Y2
Y21
Y23
Y25
Y27
Y3
Y35
Y39
Y9
AN22
AE13
AN24
AU35
AN25
AE12
AN21
A3
A43
A6
B44
BC1
BC45
BD2
BD44
BE3
BE43
AD30
AC30
AF30
AE30
3
3
GNDGND
o
o
n
n
f
f
2
EAGLELAKE-P/Q/G
13G070110360 HEATSINK 42.2*42 .2*30mm SILVER
13G070183000 HEATSINK 42.3 *42.3*30mm G LUE
13G070308012 HEATSINK 42.3*42 .3*30mm SILVER
HEATSINK 1
HEATSINK 1
1
2
3
4
i
i
t
t
I
I
i
i
GND
I
I
CLIP1
CLIP1
d
d
ANCHOR_ CLIP
ANCHOR_ CLIP
e
e
2
HEATSINK_ 2ANCHOR
HEATSINK_ 2ANCHOR
I
I
n
n
CLIP2
CLIP2
ANCHOR_ CLIP
ANCHOR_ CLIP
1
l
l
a
a
PEGATRON DT-MB RESTRICTED SECRET
Title :
Title :
Title :
EAGLELAKE 7 - 7
EAGLELAKE 7 - 7
EAGLELAKE 7 - 7
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Pr oject Name
Size Pr oject Name
Size Pr oject Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Engineer:
IPX41-D3
IPX41-D3
IPX41-D3
1
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
16 54Thursday, December 10, 2009
16 54Thursday, December 10, 2009
16 54Thursday, December 10, 2009
1.02
1.02
1.02
Rev
Rev
Rev
Page 17
5
NOTE:
Below 4 signals are different connection in Eaglelake platform
Channel A : CS1/WE/MA0
Channel B : ODT3 (G41 No ODT3)
D D
M_CHA_M AA0
M_CHA_M AA1
M_CHA_M AA2
M_CHA_M AA3
M_CHA_M AA4
M_CHA_M AA5
M_CHA_M AA6
M_CHA_M AA7
M_CHA_M AA8
M_CHA_M AA9
M_CHA_M AA10 M_CHA_D Q53
M_CHA_M AA11
M_CHA_M AA12
M_CHA_M AA13
NOTE:
Check clock source if Eaglelake
implemented
M_CHA_C LK0[11]
M_CHA_C LK0#[11]
M_CHA_C LK2[11]
M_CHA_C LK2#[11]
06/03 Important! follow Intel MRC code,
C C
B B
A A
only DIMMA need.
M_CHA_C S#1[12]
M_CHA_C S#0[11]
M_CHA_C KE1[11]
M_CHA_C KE0[11]
M_CHA_B A2[11]
M_CHA_B A1[11]
M_CHA_B A0[11]
SMB_DAT A_S[6,18,22,24,25]
SMB_CLK _S[6,18,22,24,25]
M_CHA_W E#[12]
M_CHA_R AS#[11]
M_CHA_C AS#[11]
M_CHA_O DT1[11]
M_CHA_O DT0[11]
DDR3_DR AMRST#[12,18]
M_CHA_D M7[11]
M_CHA_D M5[11] M_CHA_D QS4 [11]
M_CHA_D M4[11]
M_CHA_D M3[11]
M_CHA_D M2[11]
M_CHA_D M1[11]
M_CHA_D M0[11]
5
M_CHA_M AA14
GND
GND
DIMMA0A
DIMMA0A
188
A0
181
A1
61
A2
180
A3
59
A4
58
A5
178
A6
56
A7
177
A8
175
A9
70
A10/AP
55
A11
174
A12
196
A13
172
A14
171
A15
63
CK1P/NU
64
CK1N/NU
184
CK0P
185
CK0N
76
CS1#
193
CS0#
169
CKE1
50
CKE0
52
BA2
190
BA1
71
BA0
238
SDA
118
SCL
165
CB7
164
CB6
159
CB5
158
CB4
46
CB3
45
CB2
40
CB1
39
CB0
237
SA1
117
SA0
73
WE#
192
RAS#
74
CAS#
77
ODT1
195
ODT0
168
RESET#
161
DM8/DQS17P
162
NC/DQS17N
230
DM7/DQS16P
231
NC/DQS16N
221
DM6/DQS15P
222
NC/DQS15N
212
DM5/DQS14P
213
NC/DQS14N
203
DM4/DQS13P
204
NC/DQS13N
152
DM3/DQS12P
153
NC/DQS12N
143
DM2/DQS11P
P
P
144
NC/DQS11N
134
DM1/DQS10P
135
NC/DQS10N
125
DM0/DQS9P
126
NC/DQS9N
43
NC/DQS8P
42
NC/DQS8N
198
FREE1
187
FREE2
49
FREE3
48
FREE4
DDR3_DIMM _240P
DDR3_DIMM _240P
I
I
e
e
4
XMM1 COLOR: BLU E
234
DQ63
233
DQ62
228
DQ61
227
DQ60
115
DQ59
114
DQ58
109
DQ57
108
DQ56
225
DQ55
224
DQ54
219
DQ53
218
DQ52
106
DQ51
105
DQ50
100
DQ49
99
DQ48
216
DQ47
215
DQ46
210
DQ45
209
DQ44
97
DQ43
96
DQ42
91
DQ41
90
DQ40
207
DQ39
206
DQ38
201
DQ37
200
DQ36
88
DQ35
87
DQ34
82
DQ33
81
DQ32
156
DQ31
155
DQ30
150
DQ29
149
DQ28
37
DQ27
36
DQ26
31
DQ25
30
DQ24
147
DQ23
146
DQ22
141
DQ21
140
DQ20
28
DQ19
27
DQ18
22
DQ17
21
DQ16
138
DQ15
137
DQ14
132
DQ13
131
DQ12
19
DQ11
18
DQ10
13
DQ9
12
DQ8
129
DQ7
128
DQ6
123
DQ5
122
DQ4
10
DQ3
9
DQ2
4
DQ1
3
DQ0
112
DQS7P
a
a
111
DQS7N
103
DQS6P
102
DQS6N
94
DQS5P
g
g
93
DQS5N
85
DQS4P
84
DQS4N
34
DQS3P
33
DQS3N
25
DQS2P
24
DQS2N
16
DQS1P
15
DQS1N
7
DQS0P
6
DQS0N
79
RESERVED
68
NC/PAR_IN
NC/TEST4
53
167
4
NC/ERR_OUT
M_CHA_D Q63
M_CHA_D Q62
M_CHA_D Q61
M_CHA_D Q60
M_CHA_D Q59
M_CHA_D Q58
M_CHA_D Q57
M_CHA_D Q56
M_CHA_D Q55
M_CHA_D Q54
M_CHA_D Q52
M_CHA_D Q51
M_CHA_D Q50
M_CHA_D Q49
M_CHA_D Q48
M_CHA_D Q47
M_CHA_D Q46
M_CHA_D Q45
M_CHA_D Q44
M_CHA_D Q43
M_CHA_D Q42
M_CHA_D Q41
M_CHA_D Q40
M_CHA_D Q39
M_CHA_D Q38
M_CHA_D Q37
M_CHA_D Q36
M_CHA_D Q35
M_CHA_D Q34
M_CHA_D Q33
M_CHA_D Q32
M_CHA_D Q31
M_CHA_D Q30
M_CHA_D Q29
M_CHA_D Q28
M_CHA_D Q27
M_CHA_D Q26
M_CHA_D Q24
M_CHA_D Q25
M_CHA_D Q23
M_CHA_D Q22
M_CHA_D Q21
M_CHA_D Q20
M_CHA_D Q19
M_CHA_D Q18
M_CHA_D Q17
M_CHA_D Q16
M_CHA_D Q15
M_CHA_D Q14
M_CHA_D Q13
M_CHA_D Q12
M_CHA_D Q11
M_CHA_D Q10
M_CHA_D Q9
M_CHA_D Q8
M_CHA_D Q7
M_CHA_D Q6
M_CHA_D Q5
M_CHA_D Q4
M_CHA_D Q3
M_CHA_D Q2
M_CHA_D Q1
M_CHA_D Q0
t
t
M_CHA_D QS7 [11]
M_CHA_D QS7# [11]
M_CHA_D QS6 [11]
M_CHA_D QS6# [11]
M_CHA_D QS5 [11]M_CHA_D M6[11]
M_CHA_D QS5# [11]
M_CHA_D QS4# [11]
M_CHA_D QS3 [11]
M_CHA_D QS3# [11]
M_CHA_D QS2 [11]
M_CHA_D QS2# [11]
M_CHA_D QS1 [11]
M_CHA_D QS1# [11]
M_CHA_D QS0 [11]
M_CHA_D QS0# [11]
r
r
o
o
SWAP DATA signal
n
n
C
C
3
3
o
o
n
n
+1P5V_D UAL + 1P5V_DUAL
+0P75V_V TT_DDR
12
GND GND
i
i
f
f
12
I
I
D3R17
D3R17
1K
1K
1%
1%
12
I
I
D3R18
D3R18
1K
1K
1%
1%
GND
GND GND GND
I
I
D3CB17
D3CB17
4.7UF/6.3 V
4.7UF/6.3 V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
d
d
12
I
I
D3R15
D3R15
1K
1K
1%
1%
12
I
I
D3R16
D3R16
1K
1K
1%
1%
2
M_CHA_DQ[ 0..63] [11]
M_CHA_MAA [1..14] [11]
M_CHA_M AA0 [12]
DIMMA0B
+1P5V_D UAL +1P5V_D UAL
n
n
12
I
I
e
e
D3CB18
D3CB18
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
DIMM_CA_ VREF_A
DIMM_VRE F_A
12
12
I
I
D3CB6
D3CB6
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
2
I
I
D3CB5
D3CB5
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
DIMMA0B
78
VDD10
75
VDD9
72
VDD8
69
VDD7
66
VDD6
65
VDD5
62
VDD4
60
VDD3
57
t
t
VDD2
54
VDD1
51
VDD0
240
VTT2
120
VTT1
113
GND27
110
GND26
107
GND25
104
GND24
101
GND23
98
GND22
95
GND21
92
GND20
89
GND19
86
GND18
83
GND17
80
GND16
47
GND15
44
GND14
41
GND13
38
GND12
35
GND11
32
GND10
29
GND9
26
GND8
23
GND7
20
GND6
17
GND5
14
GND4
11
GND3
8
GND2
5
GND1
2
GND0
67
VREFCA
1
VREFDQ
DDR3_DIMM _240P
DDR3_DIMM _240P
I
I
i
i
l
l
197
VDD21
194
VDD20
191
VDD19
189
VDD18
a
a
186
VDD17
183
VDD16
182
VDD15
179
VDD14
176
VDD13
173
VDD12
170
VDD11
239
GND59
235
GND58
232
GND57
229
GND56
226
GND55
223
GND54
220
GND53
217
GND52
214
GND51
211
GND50
208
GND49
205
GND48
202
GND47
199
GND46
166
GND45
163
GND44
160
GND43
157
GND42
154
GND41
151
GND40
148
GND39
145
GND38
142
GND37
139
GND36
136
GND35
133
GND34
130
GND33
127
GND32
124
GND31
121
GND30
119
GND29
116
GND28
241
NP_NC1
242
NP_NC2
243
NP_NC3
236
VDDSPD
PEGATRON DT-MB RESTRICTED SECRET
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Pr oject Name
Size Pr oject Name
Size Pr oject Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
GND
1
+3P3V
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
IPX41-D3
IPX41-D3
IPX41-D3
1
DDR3 DIMMA
DDR3 DIMMA
DDR3 DIMMA
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
17 54Thursday, December 10, 2009
17 54Thursday, December 10, 2009
17 54Thursday, December 10, 2009
Rev
Rev
Rev
1.02
1.02
1.02
Page 18
5
XMM3 COLOR: BLU E
DIMMB0A
D D
NOTE:
Check clock source if Eaglelake
implemented
M_CHB_C LK2[12]
M_CHB_C LK2#[12]
M_CHB_C LK0[12]
M_CHB_C LK0#[12]
C C
B B
A A
M_CHB_C S#1[12]
M_CHB_C S#0[12]
M_CHB_C KE1[12]
M_CHB_C KE0[12]
M_CHB_B A2[12]
M_CHB_B A1[12]
M_CHB_B A0[12]
SMB_DAT A_S[6,17,22,24,25]
SMB_CLK _S[6,17,22,24,25]
M_CHB_W E#[12]
M_CHB_R AS#[12]
M_CHB_C AS#[12]
M_CHB_O DT1[12]
M_CHB_O DT0[12]
DDR3_DR AMRST#[12,17]
M_CHB_D M7[12]
M_CHB_D M6[12]
M_CHB_D M5[12]
M_CHB_D M4[12]
M_CHB_D M3[12]
M_CHB_D M2[12]
M_CHB_D M1[12]
M_CHB_D M0[12]
5
M_CHB_M AA0
M_CHB_M AA1
M_CHB_M AA2
M_CHB_M AA3
M_CHB_M AA4
M_CHB_M AA5
M_CHB_M AA6
M_CHB_M AA7
M_CHB_M AA8
M_CHB_M AA9
M_CHB_M AA10
M_CHB_M AA11
M_CHB_M AA12
M_CHB_M AA13
M_CHB_M AA14
+3P3V
GND
12
I
I
D3C02
D3C02
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
GND
DIMMB0A
188
A0
181
A1
61
A2
180
A3
59
A4
58
A5
178
A6
56
A7
177
A8
175
A9
70
A10/AP
55
A11
174
A12
196
A13
172
A14
171
A15
63
CK1P/NU
64
CK1N/NU
184
CK0P
185
CK0N
76
CS1#
193
CS0#
169
CKE1
50
CKE0
52
BA2
190
BA1
71
BA0
238
SDA
118
SCL
165
CB7
164
CB6
159
CB5
158
CB4
46
CB3
45
CB2
40
CB1
39
CB0
237
SA1
117
SA0
73
WE#
192
RAS#
74
CAS#
77
ODT1
195
ODT0
168
RESET#
161
DM8/DQS17P
162
NC/DQS17N
230
DM7/DQS16P
231
NC/DQS16N
221
DM6/DQS15P
222
NC/DQS15N
212
DM5/DQS14P
213
NC/DQS14N
203
DM4/DQS13P
204
NC/DQS13N
152
DM3/DQS12P
153
NC/DQS12N
143
DM2/DQS11P
144
NC/DQS11N
134
DM1/DQS10P
P
P
135
NC/DQS10N
125
DM0/DQS9P
126
NC/DQS9N
43
NC/DQS8P
42
NC/DQS8N
198
FREE1
187
FREE2
49
FREE3
48
FREE4
DDR3_DIMM _240P
DDR3_DIMM _240P
I
I
e
e
DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
DQS7P
DQS7N
DQS6P
DQS6N
DQS5P
DQS5N
DQS4P
g
g
DQS4N
DQS3P
DQS3N
DQS2P
DQS2N
DQS1P
DQS1N
DQS0P
DQS0N
RESERVED
NC/PAR_IN
NC/ERR_OUT
NC/TEST4
4
234
233
228
227
115
114
109
108
225
224
219
218
106
105
100
99
216
215
210
209
97
96
91
90
207
206
201
200
88
87
82
81
156
155
150
149
37
36
31
30
147
146
141
140
28
27
22
21
138
137
132
131
19
18
13
12
129
128
123
122
10
9
4
3
112
111
103
a
a
102
94
93
85
84
34
33
25
24
16
15
7
6
79
68
53
167
4
M_CHB_D Q63
M_CHB_D Q62
M_CHB_D Q61
M_CHB_D Q60
M_CHB_D Q59
M_CHB_D Q58
M_CHB_D Q57
M_CHB_D Q56
M_CHB_D Q55
M_CHB_D Q54
M_CHB_D Q53
M_CHB_D Q52
M_CHB_D Q51
M_CHB_D Q50
M_CHB_D Q49
M_CHB_D Q48
M_CHB_D Q47
M_CHB_D Q46
M_CHB_D Q45
M_CHB_D Q44
M_CHB_D Q43
M_CHB_D Q42
M_CHB_D Q41
M_CHB_D Q40
M_CHB_D Q34
M_CHB_D Q38
M_CHB_D Q33
M_CHB_D Q37
M_CHB_D Q35
M_CHB_D Q39
M_CHB_D Q36
M_CHB_D Q32
M_CHB_D Q26
M_CHB_D Q25
M_CHB_D Q29
M_CHB_D Q28
M_CHB_D Q30
M_CHB_D Q31
M_CHB_D Q24
M_CHB_D Q27
M_CHB_D Q23
M_CHB_D Q22
M_CHB_D Q21
M_CHB_D Q20
M_CHB_D Q19
M_CHB_D Q18
M_CHB_D Q17
M_CHB_D Q16
M_CHB_D Q15
M_CHB_D Q14
M_CHB_D Q13
M_CHB_D Q12
M_CHB_D Q11
M_CHB_D Q10
M_CHB_D Q9
M_CHB_D Q8
M_CHB_D Q3
M_CHB_D Q6
M_CHB_D Q5
M_CHB_D Q4
M_CHB_D Q2
M_CHB_D Q7
M_CHB_D Q1
M_CHB_D Q0
t
t
M_CHB_D QS7 [12]
M_CHB_D QS7# [12]
M_CHB_D QS6 [12]
M_CHB_D QS6# [12]
M_CHB_D QS5 [12]
M_CHB_D QS5# [12]
M_CHB_D QS4 [12]
M_CHB_D QS4# [12]
M_CHB_D QS3 [12]
M_CHB_D QS3# [12]
M_CHB_D QS2 [12]
M_CHB_D QS2# [12]
M_CHB_D QS1 [12]
M_CHB_D QS1# [12]
M_CHB_D QS0 [12]
M_CHB_D QS0# [12]
r
r
o
o
SWAP DATA signal
SWAP DATA signal
SWAP DATA signal
SWAP DATA signal
SWAP DATA signal
SWAP DATA signal
n
n
SWAP DATA signal
C
C
3
3
+1P5V_D UAL
o
o
+0P75V_V TT_DDR
12
GND GND
i
i
f
f
+1P5V_D UAL
n
n
12
12
I
I
I
I
D3R28
D3R28
D3R25
D3R25
1K
1K
1K
1K
1%
1%
1%
1%
12
12
I
I
D3R26
D3R26
I
I
1K
1K
D3R27
D3R27
1%
1%
1K
1K
1%
1%
GND GND GND
I
I
D3CB25
D3CB25
4.7UF/6.3 V
4.7UF/6.3 V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
12
I
I
D3CB12
D3CB12
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
12
I
I
D3CB26
D3CB26
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
d
d
GND
DIMM_CA_ VREF_B
DIMM_VRE F_B
12
I
I
D3CB11
D3CB11
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
2
e
e
2
78
75
72
69
66
65
62
60
57
54
51
240
120
113
110
107
n
n
104
101
98
95
92
89
86
83
80
47
44
41
38
35
32
29
26
23
20
17
14
11
8
5
2
67
1
M_CHB_DQ[ 0..63] [12]
M_CHB_MAA [0..14] [12]
DIMMB0B
DIMMB0B
VDD10
VDD9
VDD8
VDD7
VDD6
VDD5
VDD4
VDD3
VDD2
VDD1
VDD0
i
i
VTT2
t
t
VTT1
GND27
GND26
GND25
GND24
GND23
GND22
GND21
GND20
GND19
GND18
GND17
GND16
GND15
GND14
GND13
GND12
GND11
GND10
GND9
GND8
GND7
GND6
GND5
GND4
GND3
GND2
GND1
GND0
VREFCA
VREFDQ
DDR3_DIMM _240P
DDR3_DIMM _240P
I
I
197
VDD21
194
VDD20
191
VDD19
189
VDD18
186
VDD17
183
VDD16
182
VDD15
179
VDD14
176
VDD13
a
a
173
VDD12
170
VDD11
239
GND59
235
GND58
232
GND57
229
GND56
226
GND55
223
GND54
220
GND53
217
GND52
214
GND51
211
GND50
208
GND49
205
GND48
202
GND47
199
GND46
166
GND45
163
GND44
160
GND43
157
GND42
154
GND41
151
GND40
148
GND39
145
GND38
142
GND37
139
GND36
136
GND35
133
GND34
130
GND33
127
GND32
124
GND31
121
GND30
119
GND29
116
GND28
241
NP_NC1
242
NP_NC2
243
NP_NC3
236
VDDSPD
PEGATRON DT-MB RESTRICTED SECRET
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Pr oject Name
Size Pr oject Name
Size Pr oject Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
l
l
+1P5V_D UAL+1P5V_D UAL
+3P3V
GND
1
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
IPX41-D3
IPX41-D3
IPX41-D3
1
DDR3 DIMMB
DDR3 DIMMB
DDR3 DIMMB
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
18 54Thursday, December 10, 2009
18 54Thursday, December 10, 2009
18 54Thursday, December 10, 2009
Rev
Rev
Rev
1.02
1.02
1.02
Page 19
5
4
3
2
1
D D
SLP_S4#[22,38,39] DDR3_DR AM_PWRO K [12]
C C
i
i
f
n
n
f
+1P5V_D UAL
o
I
I
D3CB33
D3CB33
1UF/10V
1UF/10V
mx_c0603
mx_c0603
I
I
D3CB41
D3CB41
4.7UF/6.3 V
4.7UF/6.3 V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
12
12
12
GND GND GND GND
B B
12
GND GND
I
I
D3CB34
D3CB34
1UF/10V
1UF/10V
mx_c0603
mx_c0603
I
I
D3CB42
D3CB42
4.7UF/6.3 V
4.7UF/6.3 V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
12
I
I
D3CB35
D3CB35
1UF/10V
1UF/10V
mx_c0603
mx_c0603
12
I
I
D3CB36
D3CB36
1UF/10V
1UF/10V
mx_c0603
mx_c0603
a
a
t
t
r
r
o
o
n
n
C
C
o
d
d
e
e
+0P75V_V TT_DDR
+1P5V_D UAL +1 P5V_DUAL
D3R02
D3R01
D3R01
10K
10K
I
I
1 2
B
B
C
C
E12
3
E12
3
I
I
PMBS39 04
PMBS39 04
D3Q1
D3Q1
t
t
n
n
12
I
I
DCB5
DCB5
0.1UF/16V
0.1UF/16V
GND GND GND GND GND GND
D3R02
10K
10K
I
I
1 2
D3R03
D3R03
100KOHM
100KOHM
5%
5%
1 2
NI
NI
a
a
i
i
GND GND
09511 modify by TSL
12
I
I
DCB6
DCB6
0.1UF/16V
0.1UF/16V
12
I
I
DCB20
DCB20
1UF/10V
1UF/10V
mx_c0603
mx_c0603
l
l
12
I
I
D3C01
D3C01
0.1UF/16V
0.1UF/16V
12
I
I
DCB21
DCB21
1UF/10V
1UF/10V
mx_c0603
mx_c0603
12
I
I
DCB25
DCB25
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
12
I
I
DCB26
DCB26
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
g
g
e
e
P
P
A A
5
09511 modify by TSL
PEGATRON DT-MB RESTRICTED SECRET
DDR3 Termination A&B
DDR3 Termination A&B
DDR3 Termination A&B
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
4
3
2
Date: Sheet of
Engineer:
IPX41-D3
IPX41-D3
IPX41-D3
1
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
19 54Thursday, December 10, 2009
19 54Thursday, December 10, 2009
19 54Thursday, December 10, 2009
1.02
1.02
1.02
Rev
Rev
Rev
Page 20
5
+3P3V
4
3
2
1
DEVSEL#
IRDY#
SERR#
STOP#
PLOCK#
TRDY#
PERR#
FRAME#
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
REQ5#
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
12
SB_PAR
PME# internal pull
D D
CK_33M_IC H[6]
C C
B B
A A
up to +3VSB (20k)
ST21 TPC2 6bNOBOM ST2 1 TPC 26bNOBOM
ST8 TPC 26bNOBOM ST8 TPC26bN OBOM
Internal PU (20 K)
ST1 TP C26bNOBOM ST1 TPC26bNOBOM
1
ST2 TPC26bNOBOM ST2 TPC 26bNOBOM
1
ST3 TPC26bNOBOM ST3 TPC 26bNOBO M
1
ST4 TPC26bNOBOM ST4 TPC 26bNOBO M
1
INTE#
KRN8A
KRN8A
I
I
PLOCK#
KRN8B
KRN8B
I
I
TRDY#
KRN8C
KRN8C
I
I
STOP#
KRN8D
KRN8D
I
I
FRAME#
KRN3C
KRN3C
I
I
REQ3#
KRN3D
KRN3D
I
I
REQ2#
KRN3A
KRN3A
I
I
KRN3B
KRN3B
I
I
5
1
1
TP_GNT 0#
TP_GNT 1#
TP_GNT 2#
TP_GNT 4#
1 2
3 4
5 6
7 8
5 6
7 8
1 2
3 4
SR47
SR47
NI
NI
SR1
SR1
1K
1K
4.7K
4.7K
NI
NI
1 2
IIII
IIII
SU1A
SU1A
SU1A
SU1A
SU1AS U1A
SU1AS U1A
E10
PAR
A12
DEVSEL#
A9
PCIRST#
SB_PME#
INTA#
INTB#
INTC#
INTD#
INTE#
INTF#
INTG#
INTH#
12
GND
+3P3V +3P3V +3P3V
PCICLK
B18
PCIRST#
A7
IRDY#
B19
PME#
B10
SERR#
F15
STOP#
E11
PLOCK#
F14
TRDY#
C9
PERR#
F16
FRAME#
E7
GNT0#
D16
GNT1#
D17
GNT2#
F13
GNT3#
A14
GNT4#/GPIO48
D8
GNT5#/GPIO17
ICH_GNT#
D7
REQ0#
C16
REQ1#
C17
REQ2#
E13
REQ3#
A13
REQ4#/GPIO22
C8
GPIO1/REQ5#
A3
PIRQA#
B4
PIRQB#
C5
PIRQC#
B5
PIRQD#
G8
GPIO2/PIRQE#
F7
GPIO3/PIRQF#
F8
GPIO4/PIRQG#
G7
GPIO5/PIRQH#
ICH7
ICH7
SR9
SR9
1KOhm
1KOhm
I
I
GNT5 ,REQ5 NEED BIOS
PROGRAM
SR9
e
e
NI
1Kohm
P
P
IRDY#
REQ0#
PERR#
SERR#
DEVSEL#
REQ4#
PCI
PCI
g
g
Option A ction
FWH ROM
SPI ROM
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
C/BE0#
C/BE1#
C/BE2#
C/BE3#
KRN2A
KRN2A
KRN2B
KRN2B
KRN2C
KRN2C
KRN2D
KRN2D
KRN4A
KRN4A
KRN4B
KRN4B
KRN4C
KRN4C
KRN4D
KRN4D
4
E18
AD0
C18
AD1
A16
AD2
F18
AD3
E16
AD4
A18
AD5
E17
AD6
A17
AD7
A15
AD8
C14
AD9
E14
AD10
D14
AD11
B12
AD12
C13
AD13
G15
AD14
G13
AD15
E12
AD16
C11
AD17
D11
AD18
A11
AD19
A10
AD20
F11
AD21
F10
AD22
E9
AD23
D9
AD24
B9
AD25
A8
AD26
A6
AD27
C7
AD28
B6
AD29
E6
AD30
D6
AD31
B15
C12
D12
C15
a
a
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
C/BE0#
C/BE1#
C/BE2#
C/BE3#
t
t
Default
Select
r
r
ST26
ST26
1
ST24
ST24
1
ST25
ST25
1
ST27
ST27
1
o
o
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
n
n
Place capacity n ear ICH7 by
CDI / IBL Doc # 367652 Eaglelake PDG 1.5
SC10 0.1UF /16V X7R 10%
SC10 0.1UF /16V X7R 10%
1 2
I
PE1_RX N1[24]
PE1_RX P1[ 24]
PE1_TX N1[24]
PE1_TX P1[ 24]
LAN_RXN[34]
LAN_RXP[34]
LAN_TXN[34]
LAN_TXP[34]
C
C
KRN1A
KRN1A
I
I
KRN1B
KRN1B
I
I
KRN1C
KRN1C
I
I
KRN1D
KRN1D
I
I
KRN7A
KRN7A
I
I
KRN7B
KRN7B
I
I
KRN7C
KRN7C
I
I
KRN7D
KRN7D
I
I
I
SC9 0.1U F/16V X7R 10%
SC9 0.1U F/16V X7R 10%
1 2
I
I
SC2 0.1U F/16V X7R 10%
SC2 0.1U F/16V X7R 10%
1 2
I
I
SC1 0.1U F/16V X7R 10%
SC1 0.1U F/16V X7R 10%
1 2
I
I
SC15 0.1UF /16V X7R 10%
SC15 0.1UF /16V X7R 10%
1 2
I
I
SC3 0.1U F/16V X7R 10%
SC3 0.1U F/16V X7R 10%
1 2
I
I
SC11 0.1UF /16V X7R 10%
SC11 0.1UF /16V X7R 10%
1 2
I
I
SC16 0.1UF /16V X7R 10%
SC16 0.1UF /16V X7R 10%
1 2
I
I
SC13 0.1UF /16V X7R 10%
SC13 0.1UF /16V X7R 10%
1 2
I
I
SC12 0.1UF /16V X7R 10%
SC12 0.1UF /16V X7R 10%
1 2
I
I
SC4 0.1U F/16V X7R 10%
SC4 0.1U F/16V X7R 10%
1 2
I
I
SC14 0.1UF /16V X7R 10%
SC14 0.1UF /16V X7R 10%
1 2
I
I
SC6 0.1U F/16V X7R 10%
SC6 0.1U F/16V X7R 10%
1 2
I
I
SC5 0.1U F/16V X7R 10%
SC5 0.1U F/16V X7R 10%
1 2
I
I
SC8 0.1U F/16V X7R 10%
SC8 0.1U F/16V X7R 10%
1 2
I
I
SC7 0.1U F/16V X7R 10%
SC7 0.1U F/16V X7R 10%
1 2
I
I
SC19 0.1UF/1 6V X7R 10%
SC19 0.1UF/1 6V X7R 10%
1 2
I
I
SC20 0.1UF/1 6V X7R 10%
SC20 0.1UF/1 6V X7R 10%
1 2
I
I
o
o
+PCIE_PW R
CK_100M_ ICH#[6]
CK_100M_ ICH[6]
1 2
8.2K
8.2K
3 4
8.2K
8.2K
5 6
8.2K
8.2K
7 8
8.2K
8.2K
1 2
8.2K
8.2K
3 4
8.2K
8.2K
5 6
8.2K
8.2K
7 8
8.2K
8.2K
3
INTG#
INTH#
INTF#
REQ5#
INTA#
INTB#
INTC#
INTD#REQ1#
DMI_TXN0[10]
DMI_TXP0[10]
DMI_RXN0[10]
DMI_RXP0[10]
DMI_TXN1[10]
DMI_TXP1[10]
DMI_RXN1[10]
DMI_RXP1[10]
DMI_TXN2[10]
DMI_TXP2[10]
DMI_RXN2[10]
DMI_RXP2[10]
DMI_TXN3[10]
DMI_TXP3[10]
DMI_RXN3[10]
DMI_RXP3[10]
n
n
I
I
SR6
24.9
24.9
1 2
DMI_ICH_MT_ IR_TXN0
DMI_ICH_MT_ IR_TXP0
DMI_ICH_IT_M R_RXN0
DMI_ICH_IT_M R_RXP0
DMI_ICH_MT_ IR_TXN1
DMI_ICH_MT_ IR_TXP1
DMI_ICH_IT_M R_RXN1
DMI_ICH_IT_M R_RXP1
DMI_ICH_MT_ IR_TXN2
DMI_ICH_MT_ IR_TXP2
DMI_ICH_IT_M R_RXN2
DMI_ICH_IT_M R_RXP2
DMI_ICH_MT_ IR_TXN3
DMI_ICH_MT_ IR_TXP3
DMI_ICH_IT_M R_RXN3
DMI_ICH_IT_M R_RXP3
i
i
f
f
1%SR6
1%
d
d
LAN_TXN _C
LAN_TXP _C
DMI_COMP
SU1B
SU1B
SU1B
SU1B
SU1BS U1B
SU1BS U1B
V26
DMI0RXN
V25
DMI0RXP
U28
DMI0TXN
U27
DMI0TXP
Y26
DMI1RXN
Y25
DMI1RXP
W28
DMI1TXN
W27
DMI1TXP
AB26
DMI2RXN
AB25
DMI2RXP
AA28
DMI2TXN
AA27
DMI2TXP
AD25
DMI3RXN
AD24
DMI3RXP
AC28
DMI3TXN
AC27
DMI3TXP
F26
PERN_0
e
e
F25
PERP_0
E28
PETN_0
E27
PETP_0
H26
PERN_1
H25
PERP_1
G28
PETN_1
G27
PETP_1
K26
PERN_2
K25
PERP_2
J28
PETN_2
J27
PETP_2
M26
PERN_3
M25
PERP_3
L28
PETN_3
L27
PETP_3
P26
PERN_4
P25
PERP_4
N28
PETN_4
N27
PETP_4
T25
PERN_5
T24
PERP_5
R28
PETN_5
R27
PETP_5
C25
DMI_ZCOMP
D25
DMI_IRCOMP
AE28
DMI_CLKN
AE27
DMI_CLKP
ICH7
ICH7
IIII
IIII
n
n
2
DMI
DMI
PCI-E
PCI-E
t
t
F1
USBP0N
F2
USBP0P
G4
USBP1N
G3
USBP1P
H1
USBP2N
H2
USBP2P
J4
USBP3N
J3
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
i
i
USBP7N
USBP7P
USB
USB
OC0#
OC1#
OC2#
OC3#
OC4#
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
USBRBIAS
USBRBIAS#
CLK48
l
l
K1
K2
L4
L5
a
a
M1
M2
N4
N3
I
I
SR17 8.2K
SR17 8.2K
D3
C4
D5
D4
E5
C3
A2
B3
D1
D2
B2
PEGATRON DT-MB RESTRICTED SECRET
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Pr oject Name
Size Pr oject Name
Size Pr oject Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
1 2
USBRBIAS
IPX41-D3
IPX41-D3
IPX41-D3
12
GND
Engineer:
Engineer:
Engineer:
USBN0 [31]
USBP0 [31]
USBN1 [31]
USBP1 [31]
USBN2 [35]
USBP2 [35]
USBN3 [35]
USBP3 [35]
USBN4 [32]
USBP4 [32]
USBN5 [32]
USBP5 [32]
USBN6 [32]
USBP6 [32]
USBN7 [32]
USBP7 [32]
+3P3VSB
I
I
SR5
SR5
22.6
22.6
1%
1%
CK_48M_U SB [6]
Title :
Title :
Title :
1
ICH7 CONTROL - 1
ICH7 CONTROL - 1
ICH7 CONTROL - 1
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
20 54Thursday, D ecember 10, 2009
20 54Thursday, D ecember 10, 2009
20 54Thursday, D ecember 10, 2009
Rev
Rev
Rev
1.02
1.02
1.02
Page 21
5
D D
C C
B B
4
IIII
IIII
SU1C
SU1C
SU1C
SU1C
SU1CS U1C
SU1CS U1C
AB15
DD0
AE14
DD1
AG13
DD2
AF13
DD3
AD14
DD4
AC13
DD5
AD12
DD6
AC12
DD7
AE12
DD8
AF12
DD9
AB13
DD10
AC14
DD11
AF14
DD12
AH13
DD13
AH14
DD14
AC15
DD15
+3P3V
12
I
I
SR10
SR10
4.7K
4.7K
+3P3V +3P3V
12
I
I
SR13
SR13
4.7K
4.7K
t
t
a
a
IORDY
IDEIRQ
r
r
AF16
DDACK#
AE15
DDREQ
AF15
DIOR#
AH15
DIOW#
AG16
IORDY
AH17
DA0
AE17
DA1
AF17
DA2
AE16
DCS1#
AD16
DCS3#
AH16
IDEIRQ
o
o
ICH7
ICH7
IDE
IDE
HOST
HOST
n
n
SATA
SATA
GPIO21/SATA0GP
GPIO19/SATA1GP
GPIO36/SATA2GP
GPIO37/SATA3GP
3
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA_CLKN
SATA_CLKP
SATARBIAS#
SATARBIAS
SATALED#
A20GATE
A20M#
CPUSLP#
IGNNE#
INIT3_3V#
INIT#
C
C
INTR
FERR#
NMI
RCIN#
SERIRQ
SMI#
STPCLK#
THERMTRIP#
AF3
AE3
AG2
AH2
AE5
AD5
AG4
AH4
AF7
AE7
AG6
AH6
AD9
AE9
AG8
AH8
AF1
AE1
AH10
AG10
AF18
AF19
AH18
AH19
AE19
AE22
o
o
AH28
AG27
AG22
AG21
AF22
AF25
AG26
AH24
AG23
AH21
AF23
AH22
AF26
SATA_RX N0 [33]
SATA_RX P0 [33]
SATA_TX N0 [33]
SATA_TX P0 [33]
SATA_RX N1 [33]
SATA_RX P1 [33]
SATA_TX N1 [33]
SATA_TX P1 [33]
CK_100M _SATA# [6]
CK_100M _SATA [6]
2009/11/02
SR11 from 24.9ohm change to 22ohm for SATA EA.
SATARBIAS
ICH_AH19 _PU
ICH_AE19 _PU
ICH_AF19_ PU
ICH_AH18 _PU
CPUSLP#
TP_AG21
12
I
I
SR11
SR11
22 OHM
22 OHM
1%
1%
GND
n
n
+3P3V
12
I
I
SR12
SR12
8.2K
8.2K
f
f
A20GATE [39]
A20M# [8]
IGNNE# [8]
HINIT# [7]
INTR [8]
HFERR# [8]
NMI [8]
RST_KB [ 39]
d
d
i
i
ICH_SATA LED# [3 3]
3 4
I
I
8.2K
8.2K
7 8
I
I
8.2K
8.2K
1 2
I
I
8.2K
8.2K
5 6
I
I
8.2K
8.2K
12
I
I
SR55
SR55
8.2K
8.2K
SMI# [8]
STPCLK# [8]
2
n
n
e
e
SRN19B
SRN19B
SRN19D
SRN19D
SRN19A
SRN19A
SRN19C
SRN19C
SERIRQ [39, 43]
+3P3V
+1P1V_FS B_VTT
12
I
I
SR14
SR14
62
62
12
NI
NI
SCB1
SCB1
150PF/5 0V
150PF/5 0V
NPO 5%
NPO 5%
GND
t
t
ST5TPC26b
ST5TPC26b
1
ST6TPC26b
ST6TPC26b
1
H_THMTR IP# [8]
i
i
NOBOM
NOBOM
NOBOM
NOBOM
a
a
l
l
1
g
g
e
e
P
P
A A
PEGATRON DT-MB RESTRICTED SECRET
ICH7 CONTROL - 2
ICH7 CONTROL - 2
ICH7 CONTROL - 2
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Pr oject Name
Size Pr oject Name
Size Pr oject Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Engineer:
IPX41-D3
IPX41-D3
IPX41-D3
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
21 54Thursday, D ecember 10, 2009
21 54Thursday, D ecember 10, 2009
21 54Thursday, D ecember 10, 2009
1
Rev
Rev
Rev
1.02
1.02
1.02
Page 22
5
08 12/1 Add
12
12
I
I
I
D D
Add HDA for HDMI
to FS
*
*
*
SDATA_IN 1[13]
AZ_SDATA _IN2[ 36]
AZ_SDATA _OUT[36]
*
SDATA_OU T_MCH[ 13]
AZ_SYNC_MC H[13]
*
C C
NOBOM
NOBOM
B B
SR37
SR37
0
0
1 2
12
I
I
SC22
SC22
15PF/50V
15PF/50V
NPO 5%
NPO 5%
A A
10PF/50V
10PF/50V
BITCLK_MC H[13]
AZ_BITCLK[36]
AZ_RST#[36]
AZRST#_M CH[13]
AZ_SYNC[36]
CK_14M_IC H[6]
I
I
SR30
SR30
10MOhm
10MOhm
mx_r0402
mx_r0402
1 2
5%
5%
Y5_32.768
XY5
XY5
Crystal Holder
Crystal Holder
I
I
TPC26b
TPC26b
NOBOM
NOBOM
I
SCB28
SCB28
NPO 5%
NPO 5%
SCB2
SCB2
10PF/50V
10PF/50V
NPO 5%
NPO 5%
1
1
1
ST13
ST13
1
GNDGN D
12
I
I
GND
I
I
Y5
Y5
32.768Kh z
32.768Kh z
GND GND
GND GND
324
324
3
5
SCB53
SCB53
10PF/50V
10PF/50V
NPO 5%
NPO 5%
12
GND
4
I
I
SCB25
SCB25
10PF/50V
10PF/50V
NPO 5%
NPO 5%
RSMRST #[39]
2
GNDGND GND
SPI_MOSI[43]
SPI_MISO[43]
SPI_CS#[43]
SPI_CLK[43]
12
I
I
SC23
SC23
15PF/50V
15PF/50V
NPO 5%
NPO 5%
+3P3VSB
LAD0[39,43]
LAD1[39,43]
LAD2[39,43]
LAD3[39,43]
LFRAME#[39 ,43]
SR2433ISR2433
1 2
I
I
I
I
1 2
I
1 2
I
1 2
I
1 2
I
NOTE:
Install SR51 : PCIe Port CFG1.1 = 1
Install SR60 : PCIe Port CFG1.0 = 1
PU to +3P3V if not
support HDMI
+1P5V_ICH
NI
NI
SR33 0
SR33 0
1 2
+3P3VSB
SR2133ISR2133
1 2
SR2233ISR2233
1 2
12
SR2533ISR2533
1 2
SR2333ISR2333
SR3233ISR3233
SR2733ISR2733
SR5433ISR5433
SR61 4.7K
SR61 4.7K
NI
NI
SR56 4.7K
SR56 4.7K
NI
NI
12
I
I
SR26
SR26
8.2KOHM
8.2KOHM
GND
RTC_IN
RTC_OUT
4.7K
4.7K
SR203
SR203
I
I
SMBALER T#
SMB_CLK _S[6,17,18,24,25]
SMB_DAT A_S[6,17,18,24,25]
1 2
I
I
4.7K
4.7K
3 4
I
I
4.7K
4.7K
5 6
I
I
4.7K
4.7K
7 8
I
I
4.7K
4.7K
I
e
e
I
I
Add R175 for Intel request
P
P
1 2
5 6
3 4
7 8
I
1 2
1 2
+3P3V
12
1 2
NOBOM
NOBOM
+3P3V
1 2
SRN21A
SRN21A
SRN21B
SRN21B
SRN21C
SRN21C
SRN21D
SRN21D
g
g
12
12
12
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
4
NI
NI
SR16
SR16
4.7K
4.7K
ICH_LDRQ0 #
SR2033ISR2033
ST10TPC26b
ST10TPC26b
1
ICH_LAN_ RST#
+3P3V
I
I
SR202
SR202
4.7K
4.7K
SMLINKALE RT#
SMLINK0
SMLINK1
SR4147ISR4147
SR4247ISR4247
SR4347ISR4347
SRN22A
SRN22A
SRN22C
SRN22C
SRN22B
SRN22B
SRN22D
SRN22D
4
+3P3V
12
NI
NI
SR15
SR15
4.7K
4.7K
LDRQ1#
R_LFRAM E#
R_BITCLK
R_AZRS T#
TP_ICH_T 2
R_SDATA _OUT
R_SDATA _OUT
R_AZ_SYNC
R_AZ_SYNC
12
I
I
SR201
SR201
4.7K
4.7K
RTCRST#[44]
a
a
ICH_SPI_MOSI
ICH_SPI_CS #
ICH_SPI_CL K
SPI_ARB
+3P3VSB
I
I
I
I
I
I
I
I
t
t
IIII
IIII
SU1D
SU1D
SU1D
SU1D
SU1DS U1D
SU1DS U1D
AA5
LDRQ1#/GPIO23
AA6
LAD0
AB5
LAD1
AC4
LAD2
Y6
LAD3
AC3
LDRQ0#
AB3
LFRAME#
U1
ACZ_BIT_CLK
R5
ACZ_RST#
T2
ACZ_SDIN0
T3
ACZ_SDIN1
T1
ACZ_SDIN2
T4
ACZ_SDOUT
R6
ACZ_SYNC
AC1
CLK14
W1
EE_CS
W3
EE_DIN
Y2
EE_DOUT
Y1
EE_SHCLK
V3
LAN_CLK
U3
LAN_RSTSYNC
C19
LAN_RST#
U5
LAN_RXD0
V4
LAN_RXD1
T5
LAN_RXD2
U7
LAN_TXD0
V6
LAN_TXD1
V7
LAN_TXD2
AB1
RTCX1
AB2
RTCX2
AA3
RTCRST#
r
r
B23
SMBALERT#/GPIO11
C22
SMBCLK
B22
SMBDATA
A26
LINKALERT#
B25
SMLINK0
A25
SMLINK1
P5
SPI_MOSI
P2
SPI_MISO
P6
SPI_CS#
R2
SPI_CLK
P1
SPI_ARB
ICH7
ICH7
o
o
GPIO38
GPIO39
GPIO0
GPIO0/BM_BUSY#
LPC
LPC
GPIO16/DPRSLPVR
GPIO18/STPPCI#
GPIO20/STPCPU#
AUDIO
AUDIO
EL_RSVD/GPIO26
EL_STATE0/GPIO27
EL_STATE1/GPIO28
GPIO32/CLKRUN#
GPIO33/AZ_DOCK_EN#
GPIO34/AZ_DOCK_RST#
GPIO35/SATACLKREQ#
GPIO49/CPUPWRGD
VRMPWRGD
MISC
MISC
EPROM
EPROM
MCH_SYNC#
SUS_STAT#
LAN
LAN
RTC SMB SPI
RTC SMB SPI
n
n
INTRUDER#
TP0/BATLOW#
TP1/DPRSTP#
TP2/DPSLP#
3
1 2
8.2K
8.2K
3 4
8.2K
8.2K
5 6
8.2K
8.2K
7 8
8.2K
8.2K
GPIO0
AB18
AC21
GPIO6
AC18
GPIO7
E21
GPIO8
GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25
GPIO38
GPIO39
THRM#
PWRBTN#
SUSCLK
SYS_RST#
PLTRST#
C
C
WAKE#
PWROK
RSMRST#
INTVRMEN
SPKR
SLP_S3#
SLP_S4#
SLP_S5#
GPIO9
E20
GPIO10
A20
F19
E19
GPIO14
R4
GPIO15
E22
AC22
AC20
AF21
R3
GPIO25
D20
A21
B21
E23
AG18
AC19
U2
GPIO35
AD21
GPIO38
AD20
GPIO39
AE20
AG24
AF20
AD22
NOTE:
GPIO25 PD to
enable
the DMI AC
coupled mode
2009.08.14 shawn
SR28 from 5.1K 5% change to 5.1K 1%.
AH20
C23
A28
RI#
A27
TP_SUSC LK
C20
A22
o
o
C26
F20
ICH_INTRUDE R#
Y5
AA4
Y4
2009.08.14 shawn
SC26 from 22PF change to 33PF
2009.09.28 shawn
SR38 from I change to NI
INTVRMEN
W4
A19
B24
D23
TP_ICH_F 22
F22
ICH_BATLOW #
C21
AF24
AH25
ICH_TP3
F21
TP3
3
SRN26A
SRN26A
SRN26B
SRN26B
SRN26C
SRN26C
SRN26D
SRN26D
R_PLTRS T#
12
NI
NI
SR40
SR40
4.7K
4.7K
GND
ST14
ST14
ICH_TP1
ICH_TP2
I
I
I
I
I
I
I
I
PLED_P [42]
PLED_N [ 42]
CLKRUN# [43]
+3P3VSB
12
I
I
SR28
SR28
5.1K
5.1K
12
1%
1%
GND GND
i
i
f
f
SB_RING
ST12
ST12
n
n
1
TPC26b
TPC26b
NOBOM
NOBOM
SR34 10
SR34 10
+3P3VSB
12
I
I
SR36
SR36
4.7K
4.7K
12
NI
NI
SR38
SR38
10K
10K
GND
SPKR [44]
SLP_S3# [39]
SLP_S4# [19,38,39]
1
TPC26b
TPC26b
NOBOM
NOBOM
ST22 T PC26b NOBO MST22 T PC26b NOBO M
1
ST23 TPC26b NOBOMST2 3 TPC26b NOBOM
1
I
I
SR206
SR206
4.7K
4.7K
1 2
I
I
R25
R25
8.2K
8.2K
d
d
ICH_SYNC# [13]
SB_PW RBTN# [39]
LPCPD# [ 43]
1 2
12
12
I
I
SR44
SR44
4.7K
4.7K
+3P3VSB+3P3VSB
+3P3V
3 4
I
I
I
I
SC26
SC26
33PF/50V
33PF/50V
NPO 5%
NPO 5%
GND
12
4.7K
4.7K
SR205
SR205
I
I
SRN23B
SRN23B
8.2K
8.2K
I
I
12
I
I
e
e
SR31
SR31
100K
100K
GND
2
12
NI
NI
SCB3
SCB3
10PF/50V
10PF/50V
NPO 5%
NPO 5%
12
2
+3P3VSB
12
I
I
SR200
SR200
4.7K
4.7K
n
n
12
NI
NI
SC21
SC21
1UF/16V
1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
GND
SYS_RESE T# [8,39,42]
PLTRST# [ 13,39,43]
WAK E# [ 24,25,34]
PWR GD_SIO_OUT [13, 39]
RSMRST # [39 ]
2009.09.28 shawn
SR69 from I change to NI
NI
NI
SR69
SR69
10K
10K
GND
+3P3V+3P3VSB
12
NI
NI
SR45
SR45
4.7K
4.7K
SRN25A
SRN25A
8.2K
8.2K
SRN25B
SRN25B
8.2K
8.2K
SRN25C
SRN25C
8.2K
8.2K
SRN25D
SRN25D
8.2K
8.2K
MFG_NE T [43]
F_AUDIO_D ET# [37]
FWH _WP# [43]
LPC_PME# [39]
SR52 4.7KImx_r0402SR52 4.7KImx_r0402
SR53 4.7KImx_r0402SR53 4.7KImx_r0402
2009.10.07 shawn
SRN24 4R8P change to SR52, SR53
l
l
+3P3VSB
ST11
ST11
1
TPC26b
TPC26b
NOBOM
NOBOM
CPUPW RGD [8]
LPC_SMI# [39]
VRMPW RGD_ICH [6]
SRN23C
SRN23C
8.2K
8.2K
I
I
5 6
3
3
C
C
B
1
B
1
VRM1
E
E
I
I
2
2
SQ2
SQ2
PMBS39 04
PMBS39 04
GND
+BATT
12
SR39
SR39
390KOHM
390KOHM
5%
5%
IIII
IIII
Enable in tergated
VccSus1_05 VRM
Disable intergated
VccSus1_05 VRM
i
i
t
t
3
3
D
D
1
1
G
G
S
S
2
2
2N7002
2N7002
GND
Pin:
INTVRMEN
FWH _WP#
GPIO15
GPIO10
LPC_SMI#
MFG_NE T
a
a
VRMPG_ SQ1
I
I
SQ1
SQ1
H
L
1 2
3 4
5 6
7 8
PEGATRON DT-MB RESTRICTED SECRET
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Pr oject Name
Size Pr oject Name
Size Pr oject Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
IPX41-D3
IPX41-D3
IPX41-D3
1
+3P3VSB+3P3V
I
I
I
I
I
I
I
I
12
12
SRN23A
SRN23A
8.2K
8.2K
I
I
7 8
I
I
I
I
INTRUDER 1
INTRUDER 1
HEADER _1X2P
HEADER _1X2P
12X602012B00
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
1
+3P3V
12
VRM_PW RGD [8,46]
SRN23D
SRN23D
8.2K
8.2K
+BATT
I
I
SR35
SR35
1M
1M
1 2
ICH_INTRUDE R#
1
2
GND
ICH7 CONTROL - 3
ICH7 CONTROL - 3
ICH7 CONTROL - 3
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
22 54Thursday, D ecember 10, 2009
22 54Thursday, D ecember 10, 2009
22 54Thursday, D ecember 10, 2009
Rev
Rev
Rev
1.02
1.02
1.02
Page 23
5
+1P5V_ICH
IIII
IIII
SU1F
SU1F
SU1F
SU1F
SU1FSU1F
SU1FSU1F
E4
VSS1
AG11
VSS2
C27
VSS3
R14
VSS4
R15
VSS5
R16
VSS6
R17
VSS7
R18
VSS8
D D
C C
B B
A A
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH23
AH27
GND
AH12
TP_ICH_A H12
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
ICH7
ICH7
ST15
ST15
1
TPC26b
TPC26b
NOBOM
NOBOM
5
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
A4
A23
B1
B8
B11
B14
B17
B20
B26
B28
C2
C6
D10
D13
D18
D21
D24
E1
E2
E8
E15
F3
F4
F5
F12
F27
F28
G1
G2
G5
G6
G9
G14
G18
G21
G24
G25
G26
H3
H4
H5
H24
H27
H28
J1
J2
J5
J24
J25
J26
K24
K27
K28
L13
L15
L24
L25
L26
M3
M4
M5
M12
M13
M14
M15
M16
M17
M24
M27
M28
N1
N2
N5
N6
N11
N12
N13
N14
N15
N16
N17
N18
N24
N25
N26
P3
P4
P12
P13
P14
P15
P16
P17
P24
P27
P28
R1
R11
R12
R13
GND
12
I
I
SCB9
SCB9
1UF/16V
1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
+1P5V_ICH
12
I
I
SCB26
SCB26
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
P
P
12
I
I
SCB4
SCB4
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
12
NI
NI
SCB10
SCB10
2.2UF/6.3 V
2.2UF/6.3 V
X5R 10%
X5R 10%
mx_c0603
mx_c0603
BOTTOM
BOTTOM
GND GN DGNDGND
SL1 1UH/1A
SL1 1UH/1A
10%Imx_l1206
10%Imx_l1206
e
e
4
12
NI
NI
SCB16
SCB16
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
12
NI
NI
SCB11
SCB11
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
BOTTOM
BOTTOM
21
12
I
I
+
+
SCE1
SCE1
330UF/6.3 V
330UF/6.3 V
GNDGND
12
I
I
SCB37
SCB37
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND GND
g
g
4
12
I
I
SCB5
SCB5
0.01UF/25 V
0.01UF/25 V
X7R 10%
X7R 10%
GNDGNDGND
12
I
I
SCB12
SCB12
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
+PCIE_PW R
12
I
I
SCB27
SCB27
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
12
I
I
SCB38
SCB38
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
a
a
t
t
r
r
A1
AB10
AB17
AB7
AB8
AB9
AC10
AC17
AC6
AC7
AC8
AD10
AD6
AE10
AE6
AF10
AF5
AF6
AF9
AG5
AG9
AH5
AH9
F17
G17
H6
H7
J6
J7
T7
D26
D27
D28
E24
E25
E26
F23
F24
G22
G23
H22
H23
J22
J23
K22
K23
L22
L23
M22
M23
N22
N23
P22
P23
R22
R23
R24
R25
R26
T22
T23
T26
T27
T28
o
o
U22
U23
V22
V23
W22
W23
Y22
Y23
AA22
AA23
AB22
AB23
AC23
AC24
AC25
AC26
AD26
AD27
AD28
IIII
IIII
SU1E
SU1E
SU1E
SU1E
SU1ESU1E
SU1ESU1E
VCC1_5_A_1
VCC1_5_A_2
VCC1_5_A_3
VCC1_5_A_4
VCC1_5_A_5
VCC1_5_A_6
VCC1_5_A_7
VCC1_5_A_8
VCC1_5_A_9
VCC1_5_A_10
VCC1_5_A_11
VCC1_5_A_12
VCC1_5_A_13
VCC1_5_A_14
VCC1_5_A_15
VCC1_5_A_16
VCC1_5_A_17
VCC1_5_A_18
VCC1_5_A_19
VCC1_5_A_20
VCC1_5_A_21
VCC1_5_A_22
VCC1_5_A_23
VCC1_5_A_24
VCC1_5_A_25
VCC1_5_A_26
VCC1_5_A_27
VCC1_5_A_28
VCC1_5_A_29
VCC1_5_A_30
VCC1_5_B_1
VCC1_5_B_2
VCC1_5_B_3
VCC1_5_B_4
VCC1_5_B_5
VCC1_5_B_6
VCC1_5_B_7
VCC1_5_B_8
VCC1_5_B_9
VCC1_5_B_10
VCC1_5_B_11
VCC1_5_B_12
VCC1_5_B_13
VCC1_5_B_14
VCC1_5_B_15
VCC1_5_B_16
VCC1_5_B_17
VCC1_5_B_18
VCC1_5_B_19
VCC1_5_B_20
VCC1_5_B_21
VCC1_5_B_22
VCC1_5_B_23
VCC1_5_B_24
VCC1_5_B_25
VCC1_5_B_26
VCC1_5_B_27
VCC1_5_B_28
VCC1_5_B_29
n
n
VCC1_5_B_30
VCC1_5_B_31
VCC1_5_B_32
VCC1_5_B_33
VCC1_5_B_34
VCC1_5_B_35
VCC1_5_B_36
VCC1_5_B_37
VCC1_5_B_38
VCC1_5_B_39
VCC1_5_B_40
VCC1_5_B_41
VCC1_5_B_42
VCC1_5_B_43
VCC1_5_B_44
VCC1_5_B_45
VCC1_5_B_46
VCC1_5_B_47
VCC1_5_B_48
VCC1_5_B_49
VCC1_5_B_50
VCC1_5_B_51
VCC1_5_B_52
VCC1_5_B_53
ICH7
ICH7
3
V5REF_1
V5REF_2
V5REF_SUS
VCCRTC
VCCUSBPLL
VCCSATAPLL
VCCDMIPLL
VCC1_05_1
VCC1_05_2
VCC1_05_3
VCC1_05_4
VCC1_05_5
VCC1_05_6
VCC1_05_7
VCC1_05_8
VCC1_05_9
VCC1_05_10
VCC1_05_11
VCC1_05_12
VCC1_05_13
VCC1_05_14
VCC1_05_15
VCC1_05_16
VCC1_05_17
VCC1_05_18
VCC1_05_19
VCC1_05_20
POWER
POWER
V_CPU_IO_1
V_CPU_IO_2
V_CPU_IO_3
VCC3_3_1
VCC3_3_2
VCC3_3_3
VCC3_3_4
VCC3_3_5
VCC3_3_6
VCC3_3_7
VCC3_3_8
VCC3_3_9
VCC3_3_10
VCC3_3_11
VCC3_3_12
VCC3_3_13
VCC3_3_14
VCC3_3_15
VCC3_3_16
VCC3_3_17
VCC3_3_18
C
C
VCC3_3_19
VccSus1_05/VccLAN1_05_1
VccSus1_05/VccLAN1_05_0
VCC3_3_20
VCC3_3_21
Vcc3_3/VccHDA
VCCSUS3_3_1
VCCSUS3_3_2
VCCSUS3_3_3
VCCSUS3_3_4
VCCSUS3_3_5
VCCSUS3_3_6
VCCSUS3_3_7
VCCSUS3_3_8
VCCSUS3_3_9
VCCSUS3_3_10
VCCSUS3_3_11
VCCSUS3_3_12
VCCSUS3_3_13
VCCSUS3_3_14
VCCSUS3_3_15
VCCSUS3_3_16
VCCSUS3_3_17
VCCSUS3_3_18
VCCSUS3_3_19
VccSus3_3/VccSusHDA
VccSus3_3/VccLAN3_3_0
VccSus3_3/VccLAN3_3_1
VccSus3_3/VccLAN3_3_2
VccSus3_3/VccLAN3_3_3
VCCSUS1_05_2
VCCSUS1_05_3
VCCSUS1_05_4
3
AD17
G10
F6
W5
C1
AD2
AG28
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
AE23
AE26
AH26
A5
AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19
AH11
B13
B16
o
o
B27
B7
C10
D15
F9
G11
G12
G16
U6
A24
C24
D19
D22
E3
G19
K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7
P7
R7
V1
V5
W2
W7
AA2
C28
G20
K7
Y7
V5REF
VCCUSB PLL
VCCSATA PLL
+1.5V_DM IPLL
GND
n
n
VCCSUS _105A
VCCSUS _105B
12
NI
NI
SCB50
SCB50
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
BOTTOM
BOTTOM
GND GND
12
NI
NI
SCB13
SCB13
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
BOTTOM
BOTTOM
GND GND
12
I
I
SCB29
SCB29
i
i
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
f
f
GND GND
12
I
I
SCB32
SCB32
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
12
I
I
SCB39
SCB39
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
12
I
I
SCB20
SCB20
0.01UF/25 V
0.01UF/25 V
X7R 10%
X7R 10%
12
NI
NI
SCB51
SCB51
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
BOTTOM
BOTTOM
2
+1P1V_C ORE
12
NI
NI
SCB19
SCB19
1UF/16V
1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
BOTTOM
BOTTOM
+1P1V_FS B_VTT
e
e
d
d
12
12
I
I
I
I
SCB30
SCB30
SCB31
SCB31
0.1UF/16V
0.1UF/16V
4.7UF/6.3 V
4.7UF/6.3 V
X7R 10%
X7R 10%
X5R 10%
X5R 10%
mx_c0805
mx_c0805
12
GND GND
12
GND
12
GNDGND GND GN D
SB_VCC_S US_HDA
I
I
SCB33
SCB33
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
I
I
SCB40
SCB40
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
I
I
SCB45
SCB45
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
12
I
I
SCB34
SCB34
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
12
I
I
SCB42
SCB42
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
12
I
I
SCB46
SCB46
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
2
GND
12
NI
NI
SCB14
SCB14
100PF/5 0V
100PF/5 0V
NPO 5%
NPO 5%
GND GND
n
n
12
I
I
SCB21
SCB21
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND GND
+3P3V
12
GNDGND
12
+BATT
12
12
I
I
I
I
SCB18
SCB18
SCB6
SCB6
0.1UF/16V
0.1UF/16V
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
X7R 10%
X7R 10%
GND GND
12
I
I
SCB15
SCB15
a
a
0.01UF/25 V
0.01UF/25 V
X7R 10%
X7R 10%
i
i
t
t
12
12
I
I
SCB41
SCB41
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
I
I
SCB47
SCB47
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
I
I
NI
NI
SCB22
SCB22
SCB23
SCB23
1UF/16V
1UF/16V
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
X7R 10%
X7R 10%
mx_c0603
mx_c0603
12
12
I
I
SCB43
SCB43
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
+3P3VSB
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
12
I
I
SCB17
SCB17
1UF/16V
1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
I
I
SR49
SR49
1
1
1 2
l
l
GNDGND
I
I
SCB35
SCB35
0.01UF/25 V
0.01UF/25 V
X7R 10%
X7R 10%
12
I
I
SCB54
SCB54
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
+5VSB
12
NI
NI
SCB24
SCB24
2.2UF/6.3 V
2.2UF/6.3 V
X5R 10%
X5R 10%
mx_c0603
mx_c0603
12
GNDGND
+1P5V_ICH
12
I
I
SCB7
SCB7
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
+1P5V_ICH
NI
NI
12
SCB52
SCB52
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
GND
I
I
SR51
SR51
1
1
mx_r0603
mx_r0603
I
I
SCB36
SCB36
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
IPX41-D3
IPX41-D3
IPX41-D3
1
I
I
SR48
SR48
1K
1K
12
SD1 BAT5 4CW
SD1 BAT5 4CW
I
I
2
3
1
mx_sot323
mx_sot323
12
I
I
SCB8
SCB8
2.2UF/6.3 V
2.2UF/6.3 V
X5R 10%
X5R 10%
mx_c0603
mx_c0603
GND
2009.08.19 shawn
SCB8 from 4.7uF change to 2.2uF.
NI
NI
SR50
SR50
0
0
mx_r0603
mx_r0603
1 2
+1.5V_S L3
12
12
I
I
SCB55
SCB55
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
SL2
SL2
I
I
10UH/125 mA
10UH/125 mA
1
21
mx_l0805
mx_l0805
SL3
SL3
I
I
1UH/300m A
1UH/300m A
20%
20%
+3P3VSB
12
I
I
SR116
SR116
237
237
1%
1%
12
I
I
SR117
SR117
200
200
1%
1%
GND
ICH7 POWER - 4
ICH7 POWER - 4
ICH7 POWER - 4
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
23 54Thursday, D ecember 10, 2009
23 54Thursday, D ecember 10, 2009
23 54Thursday, D ecember 10, 2009
+1P5V_ICH
12
GND
+5V
+3P3V
NI
NI
SCB44
SCB44
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
+1P5V_ICH
21
Rev
Rev
Rev
1.02
1.02
1.02
Page 24
5
D D
4
3
PCI Express x1 SLOT
PCI Express x1 SLOT
PCI Express x1 SLOTPCI Express x1 SLOT
2
+3P3V +3P3V
1
t
t
12
NI
NI
X1R2
X1R2
0
0
mx_r0402
mx_r0402
i
i
+12V
a
a
12
I
I
X1CB4
X1CB4
0.1UF/16V
0.1UF/16V
l
l
+3P3V
12
NI
NI
X1CB5
X1CB5
0.1UF/16V
0.1UF/16V
PCIEX1_R ST# [ 34,39]
CK_100M _PE1 [ 6]
CK_100M _PE1# [6]
PE1_RX P1 [ 20]
PE1_RX N1 [20]
I
I
PCIEX1
PCIEX1
SLOT 36P,PCI-E X1
SLOT 36P,PCI-E X1
B1
+12V_1
B2
+12V_2
B3
+12V_5
B4
GND1
B5
SMCLK
B6
SMDAT
B7
GND2
B8
+3.3V_1
B9
JTAG1
B10
3.3Vaux
B11
WAKE#
B12
RSVD2
B13
GND3
B14
HSOP0
B15
HSON0
B16
GND4
B17
PRSNT2_1#
B18
GND5
o
o
PRSNT1#
+12V_3
+12V_4
+3.3V_2
+3.3V_3
PWRGD
REFCLK+
REFCLK-
n
n
NP_NC1
NP_NC2
GND6
JTAG2
JTAG3
JTAG4
JTAG5
GND7
f
f
GND8
HSIP0
HSIN0
GND9
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
i
i
A12
A13
A14
A15
A16
A17
A18
1
2
PE1_TCK
PE1_A6
PE1_A8
d
d
GND
12
I
I
X1CB3
X1CB3
0.1UF/16V
0.1UF/16V
+12V
GND
C
C
GND
+3P3VSB
+3P3V
SMB_CLK _S[6,17,18,22,25]
SMB_DAT A_S[6,17,18,22,25]
PE1_TRS T#
WAK E#[22,25,34]
C C
PE1_TX P1[20]
PE1_TX N1[20]
B B
12
+
+
I
I
X1CE1
X1CE1
820UF/6.3 V
820UF/6.3 V
GND
X1C1 0.1UF /16V X7R 10%
X1C1 0.1UF /16V X7R 10%
I
I
X1C2 0.1UF /16V X7R 10%
X1C2 0.1UF /16V X7R 10%
I
I
1.Place Near to slot
2.Please check if another side alr eady
have installe d serial capacitor
1 2
1 2
12
GND
I
I
X1CB1
X1CB1
0.1UF/16V
0.1UF/16V
12
GND
I
I
X1CB2
X1CB2
0.1UF/16V
0.1UF/16V
t
t
GND
r
r
12
NI
NI
X1R4
X1R4
0
0
mx_r0402
mx_r0402
o
o
GND
PE1_TX P1_C
PE1_TX N1_C
n
n
12
NI
NI
X1R1
X1R1
0
0
mx_r0402
mx_r0402
n
n
12
NI
NI
e
e
X1R3
X1R3
0
0
mx_r0402
mx_r0402
GND GNDGND
a
a
g
g
e
e
P
P
A A
PEGATRON DT-MB RESTRICTED SECRET
PCI EXPRESS X1
PCI EXPRESS X1
PCI EXPRESS X1
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Pr oject Name
Size Pr oject Name
Size Pr oject Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Engineer:
IPX41-D3
IPX41-D3
IPX41-D3
1
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
24 54Thursday, D ecember 10, 2009
24 54Thursday, D ecember 10, 2009
24 54Thursday, D ecember 10, 2009
Rev
Rev
Rev
1.02
1.02
1.02
Page 25
5
4
3
2
1
PCI EXPRESS X16 Graphics Card Slot
I
PCIEX16_B 7
12
r
r
I
J41
J41
SLOT 164P,PC I-E X16
SLOT 164P,PC I-E X16
B1
+12V_1
B2
+12V_2
B3
RSVD1
B4
GND1
B5
SMCLK
B6
SMDAT
B7
GND2
B8
+3.3V_1
B9
JTAG1
B10
3.3Vaux
B11
WAKE#
B12
RSVD2
B13
GND3
B14
HSOP0
B15
HSON0
B16
GND4
B17
PRSNT2_1#
B18
GND5
B19
HSOP1
B20
HSON1
B21
GND6
B22
GND7
B23
HSOP2
B24
HSON2
B25
GND8
B26
GND9
B27
HSOP3
B28
HSON3
B29
GND10
B30
RSVD3
B31
PRSNT2_2#
B32
GND11
B33
HSOP4
B34
HSON4
B35
GND12
B36
GND13
B37
HSOP5
B38
HSON5
B39
GND14
B40
GND15
B41
HSOP6
B42
HSON6
B43
GND16
B44
GND17
B45
HSOP7
B46
HSON7
B47
GND18
B48
PRSNT2_3#
B49
GND19
B50
HSOP8
B51
HSON8
B52
GND20
n
n
B53
GND21
B54
HSOP9
B55
HSON9
B56
GND22
B57
o
o
GND23
B58
HSOP10
B59
HSON10
B60
GND24
B61
GND25
B62
HSOP11
B63
HSON11
B64
GND26
B65
GND27
B66
HSOP12
B67
HSON12
B68
GND28
B69
GND29
B70
HSOP13
B71
HSON13
B72
GND30
B73
GND31
B74
HSOP14
B75
HSON14
B76
GND32
B77
GND33
B78
HSOP15
B79
HSON15
B80
GND34
B81
PRSNT2_4#
B82
RSVD4
2
PRSNT1#
+12V_3
NP_NC11NP_NC2
+12V_4
+3.3V_2
+3.3V_3
PWRGD
REFCLK+
REFCLK-
C
C
HSIP10
HSIN10
HSIP11
HSIN11
HSIP12
HSIN12
HSIP13
HSIN13
HSIP14
HSIN14
HSIP15
HSIN15
GND35
JTAG2
JTAG3
JTAG4
JTAG5
GND36
GND37
HSIP0
HSIN0
GND38
RSVD6
GND39
HSIP1
HSIN1
GND40
GND41
HSIP2
HSIN2
GND42
GND43
HSIP3
HSIN3
GND44
RSVD7
RSVD8
GND45
HSIP4
HSIN4
GND46
GND47
HSIP5
HSIN5
GND48
GND49
HSIP6
HSIN6
GND50
GND51
HSIP7
HSIN7
GND52
RSVD9
GND53
HSIP8
HSIN8
GND54
GND55
HSIP9
HSIN9
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND63
GND64
GND65
GND66
GND67
GND68
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
3
o
o
GND
PE16_TC K
PE16_A8
f
f
n
n
Add for DVI&HDMI to FS
+3P3V
VP
a
a
+12V
XR50VPXR50
t
t
GND
+3P3VSB
D D
EXP_TX P0[10]
EXP_TX N0[10]
DDPC_CT RL_CLK[13, 29]
EXP_TX P1[10]
EXP_TX N1[10]
EXP_TX P2[10]
EXP_TX N2[10]
C C
B B
A A
EXP_TX P3[10]
EXP_TX N3[10]
DDPC_CT RL_DATA[13, 29]
Add for DVI&HDMI to FS
EXP_TXP4 _MUX[28]
EXP_TXN4 _MUX[28]
EXP_TXP5 _MUX[28]
EXP_TXN5 _MUX[28]
EXP_TXP6 _MUX[28]
EXP_TXN6 _MUX[28]
EXP_TXP7 _MUX[28]
EXP_TXN7 _MUX[28]
EXP_EN_H DR[13]
EXP_TX P8[10]
EXP_TX N8[10]
EXP_TX P9[10]
EXP_TX N9[10]
EXP_TXP 10[10]
EXP_TXN 10[10]
EXP_TXP 11[10]
EXP_TXN 11[10]
EXP_TXP 12[10]
EXP_TXN 12[10]
EXP_TXP 13[10]
EXP_TXN 13[10]
EXP_TXP 14[10]
EXP_TXN 14[10]
EXP_TXP 15[10]
EXP_TXN 15[10]
GND
12
+
+
I
I
XCE1
XCE1
470uF/16 V
470uF/16 V
5
GND
12
I
I
XCB1
XCB1
0.1UF/16V
0.1UF/16V
PCIE_B4[13,27,28,29]
12
I
I
XCB2
XCB2
0.1UF/16V
0.1UF/16V
GND
XC2 0.1UF/16V X7R 10%
XC2 0.1UF/16V X7R 10%
I
I
XC3 0.1UF/16V X7R 10%
XC3 0.1UF/16V X7R 10%
I
I
XC4 0.1UF/16V X7R 10%
XC4 0.1UF/16V X7R 10%
I
I
XC5 0.1UF/16V X7R 10%
XC5 0.1UF/16V X7R 10%
I
I
XC6 0.1UF/16V X7R 10%
XC6 0.1UF/16V X7R 10%
I
I
XC7 0.1UF/16V X7R 10%
XC7 0.1UF/16V X7R 10%
I
I
XC8 0.1UF/16V X7R 10%
XC8 0.1UF/16V X7R 10%
I
I
XC9 0.1UF/16V X7R 10%
XC9 0.1UF/16V X7R 10%
I
I
XC10 0.1UF/1 6V X7R 10%
XC10 0.1UF/1 6V X7R 10%
I
I
XC11 0.1UF/1 6V X7R 10%
XC11 0.1UF/1 6V X7R 10%
I
I
XC12 0.1UF/1 6V X7R 10%
XC12 0.1UF/1 6V X7R 10%
I
I
XC13 0.1UF/1 6V X7R 10%
XC13 0.1UF/1 6V X7R 10%
I
I
XC14 0.1UF/1 6V X7R 10%
XC14 0.1UF/1 6V X7R 10%
I
I
XC15 0.1UF/1 6V X7R 10%
XC15 0.1UF/1 6V X7R 10%
I
I
XC16 0.1UF/1 6V X7R 10%
XC16 0.1UF/1 6V X7R 10%
I
I
XC17 0.1UF/1 6V X7R 10%
XC17 0.1UF/1 6V X7R 10%
I
I
XC18 0.1UF/1 6V X7R 10%
XC18 0.1UF/1 6V X7R 10%
I
I
XC19 0.1UF/1 6V X7R 10%
XC19 0.1UF/1 6V X7R 10%
I
I
XC20 0.1UF/1 6V X7R 10%
XC20 0.1UF/1 6V X7R 10%
I
I
XC21 0.1UF/1 6V X7R 10%
XC21 0.1UF/1 6V X7R 10%
I
I
XC22 0.1UF/1 6V X7R 10%
XC22 0.1UF/1 6V X7R 10%
I
I
XC23 0.1UF/1 6V X7R 10%
XC23 0.1UF/1 6V X7R 10%
I
I
XC24 0.1UF/1 6V X7R 10%
XC24 0.1UF/1 6V X7R 10%
I
I
XC25 0.1UF/1 6V X7R 10%
XC25 0.1UF/1 6V X7R 10%
I
I
XC26 0.1UF/1 6V X7R 10%
XC26 0.1UF/1 6V X7R 10%
I
I
XC27 0.1UF/1 6V X7R 10%
XC27 0.1UF/1 6V X7R 10%
I
I
XC28 0.1UF/1 6V X7R 10%
XC28 0.1UF/1 6V X7R 10%
I
I
XC29 0.1UF/1 6V X7R 10%
XC29 0.1UF/1 6V X7R 10%
I
I
XC30 0.1UF/1 6V X7R 10%
XC30 0.1UF/1 6V X7R 10%
I
I
XC31 0.1UF/1 6V X7R 10%
XC31 0.1UF/1 6V X7R 10%
I
I
XC32 0.1UF/1 6V X7R 10%
XC32 0.1UF/1 6V X7R 10%
I
I
XC33 0.1UF/1 6V X7R 10%
XC33 0.1UF/1 6V X7R 10%
I
I
SMB_CLK _S[6,17,18,22,24]
SMB_DAT A_S[6,17,18,22,24]
NI
NI
1 2
GND
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
P
P
1 2
1 2
XR3
XR3
0
0
WAK E#[22,24,34]
e
e
PE16_TR ST#
g
g
EXP_TX P0_C
EXP_TX N0_C
EXP_TX P1_C
EXP_TX N1_C
EXP_TX P2_C
EXP_TX N2_C
EXP_TX P3_C
EXP_TX N3_C
EXP_TX P4_C
EXP_TX N4_C
EXP_TX P5_C
EXP_TX N5_C
EXP_TX P6_C
EXP_TX N6_C
EXP_TX P7_C
EXP_TX N7_C
EXP_TX P8_C
EXP_TX N8_C
EXP_TX P9_C
EXP_TX N9_C
EXP_TX P10_C
EXP_TXN 10_C
EXP_TX P11_C
EXP_TXN 11_C
EXP_TX P12_C
EXP_TXN 12_C
EXP_TX P13_C
EXP_TXN 13_C
EXP_TX P14_C
EXP_TXN 14_C
EXP_TX P15_C
EXP_TXN 15_C
4
+12V
PE16_A6
CK_100M _PE16 [ 6]
CK_100M _PE16# [6]
EXP_RXP0 [10]
EXP_RXN0 [10]
EXP_RXP1 [10]
EXP_RXN1 [10]
EXP_RXP2 [10]
EXP_RXN2 [10]
EXP_RXP3 [10]
d
d
EXP_RXN3 [10]
i
i
EXP_RXP4 [10]
EXP_RXN4 [10]
EXP_RXP5 [10]
EXP_RXN5 [10]
EXP_RXP6 [10]
EXP_RXN6 [10]
EXP_RXP7 _MUX [28]
EXP_RXN7 _MUX [28]
EXP_RXP8 [10]
EXP_RXN8 [10]
EXP_RXP9 [10]
EXP_RXN9 [10]
EXP_RXP 10 [10]
EXP_RXN 10 [10]
EXP_RXP 11 [10]
EXP_RXN 11 [10]
EXP_RXP 12 [10]
EXP_RXN 12 [10]
EXP_RXP 13 [10]
EXP_RXN 13 [10]
EXP_RXP 14 [10]
EXP_RXN 14 [10]
EXP_RXP 15 [10]
EXP_RXN 15 [10]
12
NI
NI
XC34
XC34
0.1UF/16V
0.1UF/16V
GND
e
e
+3P3V +3P3V
XR1
XR1
0
0
NI
NI
1 2
mx_r0603
mx_r0603
12
NI
NI
XR4
XR4
0
0
GND
n
n
2
XR2
XR2
0
0
NI
NI
1 2
mx_r0603
mx_r0603
+3P3V
PCIE16_R ST# [39]
12
I
I
XCB3
XCB3
0.1UF/16V
0.1UF/16V
a
a
i
i
GND
t
t
PEGATRON DT-MB RESTRICTED SECRET
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
l
l
GND
12
NI
NI
XC1
XC1
0.1UF/16V
0.1UF/16V
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
IPX41-D3
IPX41-D3
IPX41-D3
PCI EXPRESS X16
PCI EXPRESS X16
PCI EXPRESS X16
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
25 54Thursday, December 10, 2009
25 54Thursday, December 10, 2009
25 54Thursday, December 10, 2009
1
Rev
Rev
Rev
1.02
1.02
1.02
Page 26
5
D D
VGA_RED[13]
VGA_GRE EN[13]
1 2
NOBOM
NOBOM
PJP13
PJP13
SHORTPIN
SHORTPIN
1 2
NOBOM
NOBOM
PJP12
PJP12
SHORTPIN
SHORTPIN
RA_R
GA_R
4
I
I
VL2
VL2
0.039UH/ 300mA
0.039UH/ 300mA
12
12
I
I
I
I
VR1
VR1
VC1
VC1
150
150
3.3PF/50V
3.3PF/50V
1%
1%
NPO 0. 25PF
NPO 0. 25PF
12
12
I
I
I
I
VR2
VR2
VC4
VC4
150
150
3.3PF/50V
3.3PF/50V
1%
1%
NPO 0. 25PF
NPO 0. 25PF
21
mx_l0603
mx_l0603
I
I
VL4
VL4
0.039UH/ 300mA
0.039UH/ 300mA
21
mx_l0603
mx_l0603
RA
GNDGNDGND
GA
12
I
I
VC2
VC2
5.6PF/50V
5.6PF/50V
NPO 0. 25PF
NPO 0. 25PF
12
I
I
VC5
VC5
5.6PF/50V
5.6PF/50V
NPO 0. 25PF
NPO 0. 25PF
I
I
VL3
VL3
0.039UH/ 300mA
0.039UH/ 300mA
21
mx_l0603
mx_l0603
I
I
VL5
VL5
0.039UH/ 300mA
0.039UH/ 300mA
21
mx_l0603
mx_l0603
12
GND
12
I
I
VC3
VC3
3.3PF/50V
3.3PF/50V
NPO 0. 25PF
NPO 0. 25PF
I
I
VC6
VC6
3.3PF/50V
3.3PF/50V
NPO 0. 25PF
NPO 0. 25PF
3
IIII
IIII
VU3
VU3
CM1213 _04SO
CM1213 _04SO
BLUE
CH1
CH1
1
VN
VN
2
CH2 CH3
CH2 CH3
3 4
CH4
CH4
GREEN
6
VP
VP
5
RED
12
I
I
VCB1
VCB1
0.1UF/16V
0.1UF/16V
RED
GREEN
BLUE
VGADATA
VGACLK
2
CH1
CH1
1
VN
VN
2
CH2 CH3
CH2 CH3
3 4
n
n
IIII
IIII
VU4
VU4
CM1213 _04SO
CM1213 _04SO
t
t
CH4
CH4
6
VP
VP
5
i
i
VVSYNC
+5V+5V
VHSYNC
12
GNDGNDGND GND
a
a
I
I
VCB4
VCB4
0.1UF/16V
0.1UF/16V
l
l
1
C C
1
1
G
G
2
2
S
S
BA_R
VP
VP
VP
VP
GND
GND
P
P
DDCA_CL K_G
DDCA_DA TA_G
1
1
G
G
2
2
S
S
I
I
VQ2
VQ2
2N7002
2N7002
3
3
D
D
VR6 0
VR6 0
1 2
VR7 0
VR7 0
1 2
1
2
3
1
2
3
e
e
I
I
VQ1
VQ1
2N7002
2N7002
3
3
D
D
VGA_BLUE[13]
NOTE:
Place there VGA filter components
within 500 mils of the VGA connector
VGA_HSYNC[13]
B B
VGA_VSYNC[13 ]
A A
DDCA_DA TA[13]
DDCA_CL K[13]
1 2
NOBOM
NOBOM
PJP11
PJP11
SHORTPIN
SHORTPIN
5
GNDGND
I
I
VL6
VL6
0.039UH/ 300mA
0.039UH/ 300mA
12
I
I
VR4
VR4
150
150
1%
1%
NI
NI
VU1
VU1
74AHCT 1G125
74AHCT 1G125
OE#
Vcc
A
GND
NI
NI
VU2
VU2
74AHCT 1G125
74AHCT 1G125
OE#
Vcc
A
GND
g
g
I
I
I
I
I
I
I
I
mx_l0603
mx_l0603
12
I
I
VC7
VC7
3.3PF/50V
3.3PF/50V
NPO 0. 25PF
NPO 0. 25PF
GND GND
+5V
5
4
Y
5
4
Y
a
a
GND
1 2
4.7K
4.7K
7 8
4.7K
4.7K
3 4
4.7K
4.7K
VRN1C
5 6
VRN1C
4.7K
4.7K
4
12
NI
NI
VCB2
VCB2
0.1UF/16V
0.1UF/16V
VRN1A
VRN1A
VRN1D
VRN1D
VRN1B
VRN1B
21
VHSYNC_OBVH SYNC_OB
VVSYNC_OB
t
t
GND GND
GNDGND
r
r
RDDCA_D ATA
RDDCA_C LK
I
I
VL7
VL7
0.039UH/ 300mA
0.039UH/ 300mA
BA
12
I
I
VC8
VC8
5.6PF/50V
5.6PF/50V
NPO 0. 25PF
NPO 0. 25PF
o
o
+3P3V
21
mx_l0603
mx_l0603
NI
NI
VR8
VR8
30
30
1 2
n
n
NI
NI
VR9
VR9
30
30
1 2
+5V +5V_VGA
I
I
VD6
VD6
SS14
SS14
1 2
12
I
I
VC9
VC9
3.3PF/50V
3.3PF/50V
NPO 0. 25PF
NPO 0. 25PF
C
C
12
I
I
VR18
VR18
2.2K
2.2K
12
3
I
I
VR19
VR19
2.2K
2.2K
VR3 100 1%
VR3 100 1%
I
I
1 2
VR5 100 1%
VR5 100 1%
I
I
1 2
o
o
n
n
f
f
12
I
I
VR20
VR20
200K
200K
1 2
i
i
I
I
VF1
VF1
1.1A/6V
1.1A/6V
d
d
12
I
I
VC10
VC10
470PF/5 0V
470PF/5 0V
X7R 10%
X7R 10%
+5V_VG A_L
e
e
VGADATA
VHSYNC
VVSYNC
VGACLK
12
NI
NI
VC11
VC11
3.3PF/50V
3.3PF/50V
NPO 0. 25PF
NPO 0. 25PF
GNDGND GND
2
12
NI
NI
VC12
VC12
3.3PF/50V
3.3PF/50V
NPO 0. 25PF
NPO 0. 25PF
I
I
VL8
VL8
80Ohm/100 Mhz/2A
80Ohm/100 Mhz/2A
mx_l0805
mx_l0805
21
12
GND
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Date: Sheet of
Date: Sheet of
Date: Sheet of
12
I
12
GND
GNDGND
I
I
VCB3
VCB3
0.1UF/16V
0.1UF/16V
I
VR21
VR21
200K
200K
I
I
J69
J69
DDC_CO NN_15P3R
DDC_CO NN_15P3R
RED
GREEN
VGADATA
BLUE
VHSYNC
VVSYNC
VGACLK
+5V_VGA_H DMI
6
1
11
7
2
12
8
3
13
9
4
14
10
5
15
GND GND
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
IPX41-D3
IPX41-D3
IPX41-D3
1
GND2
GND2
RED
RED
NC2
NC2
GND3
GND3
GREEN
GREEN
DATA
DATA
GND4
GND4
BLUE
BLUE
HSYNC
HSYNC
VCC
VCC
NC1
NC1
VSYNC
VSYNC
GND5
GND5
GND1
GND1
DCLK
DCLK
16
SIDE_G16
SIDE_G16
17
SIDE_G17
SIDE_G17
VGA PORT
VGA PORT
VGA PORT
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
26 54Thursday, December 10, 2009
26 54Thursday, December 10, 2009
26 54Thursday, December 10, 2009
NI
NI
VC13
VC13
470PF/5 0V
470PF/5 0V
X7R 10%
X7R 10%
PEGATRON DT-MB RESTRICTED SECRET
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Rev
Rev
Rev
1.02
1.02
1.02
Page 27
5
D D
Add HDMI CONTROL to FS
4
3
2
1
Digital Port Switch Control Logic
i
t
t
i
+3P3V
12
I
I
M1R28
M1R28
1K
I
I
3
3
M1Q5
M1Q5
C
C
B
1
B
1
E
E
2
2
OE_EN#
(Level Shifter)
LOW
1K
OE_EN# [29]
d
d
i
+12V
12
I
I
3
3
M1Q4
M1Q4
C
M1R32
M1R32
I
I
OE_EN#_B
1 2
10K
10K
Function
HI
PCIE x16
HDMI
a
a
t
t
1
1
PMBS39 04
PMBS39 04
r
r
B
B
GND
C
E
E
2
2
o
o
I
I
M1R29
M1R29
1K
1K
R1.02G
DP_EN_M 1Q2 [29]
n
n
C
C
o
o
n
n
f
f
i
e
e
n
n
+3P3V
12
I
C C
PCIE_B4[13,25,28,29]
NOTE:
B B
PCIE X16
Plugged
Unplugged
PCIE_B4
LOW
HI
I
M1R26
M1R26
1K
1K
M1R33
M1R33
I
I
PCIE_B4_R
1 2
12
NI
NI
M1CB24
M1CB24
15PF/50V
15PF/50V
NPO 5%
NPO 5%
GND GND
SEL
(MUX)
LOW
HI
10K
10K
DDC_EN#
(Level Shifter)
LOW
HI
PMBS39 04
PMBS39 04
a
a
l
l
g
g
e
e
P
P
A A
PEGATRON DT-MB RESTRICTED SECRET
PEGATRON DT-MB RESTRICTED SECRET
PEGATRON DT-MB RESTRICTED SECRET
HDMI CONTROL
HDMI CONTROL
HDMI CONTROL
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Pr oject Name
Size Pr oject Name
Size Pr oject Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Engineer:
IPX41-D3
IPX41-D3
IPX41-D3
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
27 54Thursday, D ecember 10, 2009
27 54Thursday, D ecember 10, 2009
27 54Thursday, D ecember 10, 2009
1
Rev
Rev
Rev
1.02
1.02
1.02
Page 28
5
A
+3P3V
D D
2009.08.11 shawn
MCB1 removed.
4
12
GND GND GND GND
NI
NI
MCB2
MCB2
0.1UF/16V
0.1UF/16V
12
I
I
MCB3
MCB3
0.1UF/16V
0.1UF/16V
12
I
I
MCB4
MCB4
0.1UF/16V
0.1UF/16V
12
I
I
MCB5
MCB5
0.1UF/16V
0.1UF/16V
3
Add HDMI / PCIE MUX to FS
IIII
IIII
MU1
MU1
MU1
MU1
MU1MU1
MU1MU1
6
VDD1
17
VDD2
22
VDD3
27
VDD4
34
VDD5
50
VDD6
55
VDD7
D0+
D0-
D1+
D1-
43
42
41
40
DVI_D0P_ C
DVI_D0N_ C
DVI_D1P_ C
DVI_D1N_ C
2
Place near Level Shifter
NOTE:
MC2 0.1UF/16V X7R 10%
MC2 0.1UF/16V X7R 10%
I
I
MC4 0.1UF/16V X7R 10%
MC4 0.1UF/16V X7R 10%
I
I
MC1 0.1UF/16V X7R 10%
MC1 0.1UF/16V X7R 10%
I
I
MC5 0.1UF/16V X7R 10%
MC5 0.1UF/16V X7R 10%
I
I
1
12
12
12
12
DVIB_TMD SB_CLK# [29]
DVIB_TMDS B_CLK [29]
DVIB_TMD SB_DATA0# [29]
DVIB_TMDS B_DATA0 [29]
EXP_TX N7[10]
EXP_TX P7[ 10]
EXP_TX N6[10]
EXP_TX P6[ 10]
EXP_TX N5[10]
EXP_TX P5[ 10]
EXP_TX N4[10]
C C
NOTE:
PCIE X16
Plugged
Unplugged
PCIE_B4
LOW
HI
SEL
(MUX) (Level Shifter)
LOW
HI
B B
EXP_TX P6[ 10]
EXP_TX N6[10]
EXP_TX P7[ 10]
EXP_TX N7[10]
EXP_TX P4[ 10]
EXP_TX N4[10]
EXP_TX P5[ 10]
EXP_TX N5[10]
EXP_TX P4[ 10]
EXP_RXP7[10]
EXP_RXN7[10]
DDC_EN#
LOW
HI
PCIE_B4[13,25,27,29]
P
P
OE_EN#
(Level Shifter)
HI
LOW
2009.08.14 shawn
No support HDMI option
1 2
0 OHM
0 OHM
3 4
0 OHM
0 OHM
5 6
0 OHM
0 OHM
7 8
0 OHM
0 OHM
g
g
e
e
1 2
0 OHM
0 OHM
3 4
0 OHM
0 OHM
5 6
0 OHM
0 OHM
7 8
0 OHM
0 OHM
a
a
RN3A
RN3A
RN3B
RN3B
RN3C
RN3C
RN3D
RN3D
RN4A
RN4A
RN4B
RN4B
RN4C
RN4C
RN4D
RN4D
Function
PCIE x16
HDMI
t
t
5%
5%
NI
NI
5%
5%
NI
NI
5%
5%
NI
NI
5%
5%
NI
NI
5%
5%
NI
NI
5%
5%
NI
NI
5%
5%
NI
NI
5%
5%
NI
NI
NOBOM
NOBOM
NOBOM
NOBOM
r
r
TPC26b
TPC26b
TPC26b
TPC26b
n
n
o
o
EXP_TXP6 _MUX [25]
EXP_TXN6 _MUX [ 25]
EXP_TXP7 _MUX [25]
EXP_TXN7 _MUX [ 25]
EXP_TXP4 _MUX [25]
EXP_TXN4 _MUX [ 25]
EXP_TXP5 _MUX [25]
EXP_TXN5 _MUX [ 25]
LT1
LT1
LT15
LT15
TP_DVII_OUT P
1
TP_DVI_O UTN
1
MU1_LE#
MR10
MR10
0 Ohm
0 Ohm
5%
5%
1 2
I
I
GND
2
IN_0+
3
IN_0-
4
IN_1+
5
IN_1-
7
IN_2+
8
IN_2-
9
IN_3+
10
IN_3-
12
OUT+
13
OUT-
14
X+
15
X-
o
o
19
LE#
C
C
18
SEL
PI3PCIE2612- AZFE
PI3PCIE2612- AZFE
n
n
GND10
GND11
GND12
D2+
D3+
Tx0+
Tx0-
Tx1+
Tx1-
Tx2+
Tx2-
Tx3+
Tx3-
AUX+
AUX-
HPD
Rx0+
Rx0-
Rx1+
Rx1-
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
D2-
D3-
NC
39
38
37
36
54
53
52
51
47
46
f
f
45
44
26
25
24
23
33
32
31
30
1
11
16
20
21
28
29
35
48
49
56
57
DVI_D2P_ C
DVI_D2N_ C
DVI_D3P_ C
DVI_D3N_ C
i
i
TP_DVI_A UXP
TP_DVI_A UXN
DVI_MUX_H PD_R
TP_DVI_R X0P
TP_DVI_R X0N
GND
MC8 0.1UF/16V X7R 10%
MC8 0.1UF/16V X7R 10%
I
I
MC7 0.1UF/16V X7R 10%
MC7 0.1UF/16V X7R 10%
I
I
MC9 0.1UF/16V X7R 10%
MC9 0.1UF/16V X7R 10%
I
I
MC11 0.1UF/16V X7R 10%
MC11 0.1UF/16V X7R 10%
I
I
e
e
d
d
LT16
LT16
1
LT17
LT17
TPC26b
TPC26b
1
TPC26b
TPC26b
LT25
LT25
1
LT26
LT26
TPC26b
TPC26b
1
TPC26b
TPC26b
HPD status
NOTE:
HI
LOW
n
n
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
DVI plugged
DVI unplugged
12
12
12
12
t
t
i
i
DVIB_TMD SB_DATA1# [29]
l
l
DVIB_TMDS B_DATA1 [29]
DVIB_TMD SB_DATA2# [29]
a
a
DVIB_TMDS B_DATA2 [29]
EXP_TXN7 _MUX [ 25]
EXP_TXP7 _MUX [25]
EXP_TXN6 _MUX [ 25]
EXP_TXP6 _MUX [25]
EXP_TXN5 _MUX [ 25]
EXP_TXP5 _MUX [25]
EXP_TXN4 _MUX [ 25]
EXP_TXP4 _MUX [25]
EXP_RXP7 _MUX [25]
EXP_RXN7 _MUX [25]
+1P1V_C ORE
M1R11
M1R11
1KOhm
1KOhm
5%
5%
1 2
NI
NI
NI
NI
M1Q10
M1Q10
3
3
D
D
2N7002
S
S
GND
2N7002
1
1
G
G
2
2
DVIB_HPD [29]
12
I
I
M1R7
M1R7
0
0
RN5A
5%
RN5A
1 2
0 Ohm
EXP_RXN7[10]
EXP_RXP7[10]
0 Ohm
3 4
0 Ohm
0 Ohm
RN5B
RN5B
5%
NI
NI
5%
5%
NI
NI
EXP_RXN7 _MUX [25]
EXP_RXP7 _MUX [25]
PEGATRON DT-MB RESTRICTED SECRET
PEGATRON DT-MB RESTRICTED SECRET
PEGATRON DT-MB RESTRICTED SECRET
HDMI / PCIE MUX
HDMI / PCIE MUX
HDMI / PCIE MUX
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Engineer:
IPX41-D3
IPX41-D3
IPX41-D3
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
28 54Thursday, December 10, 2009
28 54Thursday, December 10, 2009
28 54Thursday, December 10, 2009
Rev
Rev
1.02
1.02
1.02
A
Rev
Page 29
5
A
+3P3V
D D
DVIB_HPD[28]
PCIE_B4[13,25,27,28]
2009.09.28 shawn
HDMI SDA, SCL connect to NB port C.
DP_EN_M 1Q2[27]
DDPC_CT RL_DATA[13, 25]
DDPC_CT RL_CLK[13, 25]
DVIB_TMDS B_CLK[28]
DVIB_TMD SB_CLK#[28]
DVIB_TMDS B_DATA0[2 8]
C C
NOTE:
Pin 3, 4, 6, 10,34, and 35 are internal 100K ohm pull-up
OC_3
(Pin10)
B B
DVIB_TMD SB_DATA0#[28 ]
DVIB_TMDS B_DATA1[2 8]
DVIB_TMD SB_DATA1#[28 ]
DVIB_TMDS B_DATA2[2 8]
DVIB_TMD SB_DATA2#[28 ]
OE_EN#[27]
Pericom PI3VDP411LS
OC_2 OC_1 OC_0 Vswing
(Pin6) (Pin4)
0
0
0
0
0 0 1 0
0
0
0 1 0 0
1
0
0 1 1 0
1
0
1 0 0 0
0
1
1 0 1 0
0
1
1 1 0 0
1
1
1 1 1 0
1
1
(Pin3)
0
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
(mV)
500
600
750
1000
500
500
500
500
400
400
400
400
1000
1000
1000
1000
1
1
12
I
I
MR24
MR24
2.2K
2.2K
M1Q9
M1Q9
3
3
2N7002
2N7002
D
D
I
I
G
G
S
S
2
2
R1.02G
Pre/Deemphasis
P
P
1
1
G
G
0
0
0
0
0
1.5dB
3.5dB
6dB
0
3.5dB
6dB
9dB
0
-3.5dB
-6dB
-9dB
12
3
3
D
D
S
S
2
2
+3P3V
I
I
MR23
MR23
2.2K
2.2K
M1Q6
M1Q6
2N7002
2N7002
I
I
e
e
12
12
GND
4
2009.08.11 shawn
MCB9, MCB10 from NI change to remove.
I
I
ML1 120Ohm/ 100Mhz/0.6A
ML1 120Ohm/ 100Mhz/0.6A
21
mx_l0603
mx_l0603
12
NI
NI
MCB7
MCB7
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
MCB6
MCB6
15PF/50V
15PF/50V
NPO 5%
NPO 5%
NI
NI
MCB8
MCB8
0.1UF/16V
0.1UF/16V
GNDGND
12
NI
NI
MCB17
NI
NI
MCB17
15PF/50V
15PF/50V
NPO 5%
NPO 5%
GND
MR77
MR77
4.7K
4.7K
NI
NI
1 2
MR21
MR21
4.7K
4.7K
NI
NI
1 2
GND GNDG ND GND
a
a
Pericom PI3VDP411LS
NOTE:
g
g
EQ0
(Pin34)
(Pin35)
0
0
1
1
MR33
MR33
4.7K
4.7K
NI
NI
1 2
MR22
MR22
4.7K
4.7K
NI
NI
t
t
1 2
GND
EQ1 Equalization
0
1
0
1
r
r
(dB)
3
7.2
10
12
12
I
I
MCB11
MCB11
0.1UF/16V
0.1UF/16V
GND GND GND
NOTE:
DDC_EN Passgate
0V
3.3V
+3P3V+3P3V+3P3V
MR34
MR34
4.7K
4.7K
NI
NI
1 2
o
o
MR19
MR19
4.7K
4.7K
NI
NI
1 2
1 2
n
n
1 2
NOTE:
OE* IN_D Termination
1
0
12
I
I
MCB12
MCB12
0.1UF/16V
0.1UF/16V
MR31
MR31
4.7K
4.7K
NI
NI
MR20
MR20
4.7K
4.7K
NI
NI
3
DVI_VDD3 P3V
12
I
I
MCB13
MCB13
0.1UF/16V
0.1UF/16V
MU2_SDA
MU2_SCL
Disable
Enable
+3P3V+3P3V
MR32
MR32
C
C
4.7K
4.7K
NI
NI
1 2
ANALOG2 _R_1
FUN_R1
FUN_R2
FUN_R3
FUN_R4
MR29
MR29
4.7K
4.7K
NI
NI
1 2
Hi-Z
50ohm
Add HDMI LEVEL SHIFTER to FS
IIII
IIII
MU2
MU2
MU2
MU2
MU2MU2
MU2MU2
2
VCC1
26
VCC5
15
VCC3
21
VCC4
11
VCC2
33
VCC6
46
VCC8
40
VCC7
7
HPD#
8
SDA
9
SCL
32
DDC_EN
39
IN_D1+
38
IN_D1-
42
IN_D2+
41
IN_D2-
45
IN_D3+
44
IN_D3-
48
IN_D4+
47
IN_D4-
n
n
25
OE#
o
o
10
CG_2
3
CG_0
4
CG_1
34
EQ_0
35
EQ_1
ASM144 2T
ASM144 2T
OUT_D Outputs
Hi-Z
Active
HPD_SINK
SDA_SINK
SCL_SINK
OUT_D1+
OUT_D1-
OUT_D2+
OUT_D2-
OUT_D3+
OUT_D3-
f
f
OUT_D4+
OUT_D4-
REXT
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
30
29
28
22
23
19
20
16
i
i
17
13
14
6
1
5
12
24
18
36
31
27
43
37
49
50
51
52
53
d
d
REXT_DVI_ R
2
2009.09.28 shawn
This power name from +5V_DVI change to +5V.
+5V
I
I
MR25
MR25
2.2K
2.2K
NI
NI
MCB14
MCB14
15PF/50V
15PF/50V
NPO 5%
NPO 5%
e
e
12
I
I
MR30
MR30
3K
3K
1%
1%
12
I
I
MR11
MR11
2.2K
2.2K
12
NI
NI
MCB15
MCB15
15PF/50V
15PF/50V
NPO 5%
NPO 5%
MC3
MC3
NI
NI
t
t
OUT_D1
1 2
X7R 10%
X7R 10%
0.1UF/16V
0.1UF/16V
n
n
MC6
MC6
NI
NI
OUT_D2
1 2
X7R 10%
X7R 10%
0.1UF/16V
0.1UF/16V
MC10
MC10
NI
NI
OUT_D3
1 2
X7R 10%
X7R 10%
0.1UF/16V
0.1UF/16V
MC12
MC12
NI
NI
OUT_D4
1 2
X7R 10%
X7R 10%
0.1UF/16V
0.1UF/16V
GND
If using Pericom PI3VDP411LS Level Shifter,
NOTE:
tie to GND(0 ohm) or internal pull-up 3.3V.
If using Parade PS8101QFN48GTR Level Shifter,
NOTE:
tie to GND throught 499ohm 1% and instal MR33.
If using Chrontel CH71863A_CF Level Shifter,
NOTE:
tie to GND throught 1.3k ohm and instal MR31,MR32.
12
12
GND GND
GND
HPD_SINK status (+5V tolerance)
NOTE:
HI
LOW
a
a
i
i
NI
NI
MR12
MR12
1 2
390
390
NI
NI
MR26
MR26
1 2
390
390
NI
NI
MR27
MR27
1 2
390
390
NI
NI
MR28
MR28
1 2
390
390
plugged
unplugged
DVI_HP_D ETECT [30]
DVI_DDCA _DATA [ 30]
DVI_DDCA_ CLK [30]
l
l
DVI_TXC_ P [30]
DVI_TXC_ N [30]
DVI_TXD0 _P [30 ]
DVI_TXD0 _N [30]
DVI_TXD1 _P [30 ]
DVI_TXD1 _N [30]
DVI_TXD2 _P [30 ]
DVI_TXD2 _N [30]
PEGATRON DT-MB RESTRICTED SECRET
PEGATRON DT-MB RESTRICTED SECRET
PEGATRON DT-MB RESTRICTED SECRET
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Engineer:
IPX41-D3
IPX41-D3
IPX41-D3
1
HDMI LEVEL SHIFTER
HDMI LEVEL SHIFTER
HDMI LEVEL SHIFTER
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
29 54Thursday, December 10, 2009
29 54Thursday, December 10, 2009
29 54Thursday, December 10, 2009
Rev
Rev
Rev
1.02
1.02
1.02
A
Page 30
5
NI
NI
MU6
MU6
CM1213 _04SO
CM1213 _04SO
CH1
CH1
1
VN
VN
2
CH2 CH3
CH2 CH3
3
1
NI
NI
MD10
MD10
BAT54SW
BAT54SW
3 4
DVI_TXD0 _P
DVI_TXD0 _N
DVI_TXD1 _P
DVI_TXD1 _N
DVI_TXC_ P
DVI_TXC_ N
D D
C C
B B
DVI_DDCA _DATA[29]
DVI_DDCA_ CLK[29]
A A
GND
DVI_TXD0 _P[29]
DVI_TXD0 _N[29]
DVI_TXD1 _P[29]
DVI_TXD1 _N[29]
DVI_TXD2 _P[29]
DVI_TXD2 _N[29]
DVI_TXC_ P[29]
DVI_TXC_ N[29]
+5V
2
5
CH4
CH4
DVI_TXD2 _PDVI_TXD2 _N
6
VP
VP
5
DVI_TXC_ PDVI_TXC_N
3 4
1 2
3 4
1 2
1 2
3 4
3 4
1 2
1
2
NI
NI
MD9
MD9
BAT54SW
BAT54SW
3
DVI_DDCA _DATA
DVI_DDCA_ CLK
P
P
0 Ohm
0 Ohm
14
0 Ohm
0 Ohm
0 Ohm
0 Ohm
14
0 Ohm
0 Ohm
0 Ohm
0 Ohm
1 4
0 Ohm
0 Ohm
0 Ohm
0 Ohm
14
0 Ohm
0 Ohm
GND
e
e
23
23
2 3
23
+5V
MR13B
5%
MR13B
5%
NI
NI
90OHM/1 00MHZ
90OHM/1 00MHZ
ML7
ML7
ML7
ML7
ML7ML7
ML7ML7
MR13A
5%
MR13A
5%
MR14B
5%
MR14B
5%
NI
NI
90OHM/1 00MHZ
90OHM/1 00MHZ
ML8
ML8
ML8
ML8
ML8ML8
ML8ML8
MR14A
5%
MR14A
5%
MR15A
5%
MR15A
5%
ML9
ML9
ML9
ML9
ML9ML9
ML9ML9
90OHM/1 00MHZ
90OHM/1 00MHZ
NI
NI
MR15B
5%
MR15B
5%
MR16B
5%
MR16B
5%
NI
NI
90OHM/1 00MHZ
90OHM/1 00MHZ
ML10
ML10
ML10
ML10
ML10ML10
ML10ML10
MR16A
5%
MR16A
5%
g
g
MR75 0IMR75 0
1 2
I
MR76 0IMR76 0
1 2
I
4
NI
NI
MU5
MU5
CM1213 _04SO
CM1213 _04SO
CH1
CH1
DVI_TXD0 _N DVI_TXD0 _P
DVI_TXD1 _P DVI_TX D1_N
GND
I
I
RR_HDM I_TXD0_P
RR_HDM I_TXD0_N
I
I
I
I
RR_HDM I_TXD1_P
RR_HDM I_TXD1_N
I
I
I
I
RR_HDM I_TXD2_PDVI_TXD2 _P
RR_HDM I_TXD2_NDVI_TXD2_N
I
I
I
I
RR_HDMI_T XC_P
RR_HDMI_T XC_N
I
I
RR_HDM I_TXD0_P
RR_HDM I_TXD0_N
RR_HDM I_TXD1_P
RR_HDM I_TXD1_N
a
a
RR_HDM I_TXD2_P
RR_HDM I_TXD2_N
RR_HDMI_T XC_P
RR_HDMI_T XC_N
RR_HDMI_D DCA_DATA
RR_HDM I_DDCA_CLK
4
t
t
GND
1
VN
VN
2
CH2 CH3
CH2 CH3
3 4
IIII
IIII
o
o
J124
J124
J124
J124
J124J124
J124J124
r
r
7
TMDA_DATA0+
9
TMDA_DATA0-
4
TMDA_DATA1+
6
TMDA_DATA1-
1
TMDA_DATA2+
TMDA_DATA2-3TMDA_DATA1_SHIELD
10
TMDA_CLOCK+
12
TMDA_CLOCK-
16
SDA
15
SCL
13
CEC
17
DDC/CEC_GROUND
14
RESERVED
CH4
CH4
6
VP
VP
5
n
n
+5V_POWER
TMDA_DATA0_SHIELD
TMDA_DATA2_SHIELD
TMDA_TMDA_CLOCK_SHIELD
HPDET
P_GND1
P_GND2
P_GND3
P_GND4
NP_NC
HDMI_CON _19P
HDMI_CON _19P
3
+5V
C
C
18
8
5
2
11
GND
19
20
21
22
23
24
GND
3
o
o
I
MR58 0IMR58 0
1 2
2
NOTE:
Level Shifter is internal 100K ohm pull down.
HPDET status
NOTE:
High Plugged
Low
n
n
HPDET_RHPDET_R R
f
f
Unplugged
i
i
d
d
12
I
I
VCB5
VCB5
0.1UF/16V
0.1UF/16V
GND
12
I
I
MR59
MR59
100K
100K
GND
e
e
NOTE:
Level Shifter is internal
100K ohm pull down.
2
n
n
+5V_VGA_H DMI
DVI_HP_D ETECT [29]
l
l
a
a
i
i
t
t
PEGATRON DT-MB RESTRICTED SECRET
PEGATRON DT-MB RESTRICTED SECRET
PEGATRON DT-MB RESTRICTED SECRET
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Pr oject Name
Size Pr oject Name
Size Pr oject Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
IPX41-D3
IPX41-D3
IPX41-D3
1
HDMI PORT
HDMI PORT
HDMI PORT
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
30 54Thursday, D ecember 10, 2009
30 54Thursday, D ecember 10, 2009
30 54Thursday, D ecember 10, 2009
Rev
Rev
Rev
1.02
1.02
1.02
Page 31
5
D D
URN5B
0Ohm
0Ohm
5%
5%
I
I
14
0Ohm
0Ohm
5%
5%
I
I
0Ohm
0Ohm
5%
5%
I
I
14
0Ohm
0Ohm
5%
5%
I
I
URN5B
23
NI
NI
UL5
UL5
90OHM/1 00MHz/300mA
90OHM/1 00MHz/300mA
URN5A
URN5A
URN6B
URN6B
23
UL6
UL6
90OHM/1 00MHz/300mA
90OHM/1 00MHz/300mA
NI
NI
URN6A
URN6A
GND
3 4
USBN0[20]
USBP0[20]
1 2
C C
3 4
USBN1[20]
USBP1[20]
1 2
4
NI
NI
UU3
UU3
CM1213 _04SO
CM1213 _04SO
CH1
CH1
1
2
3 4
6
5
VN
VN
CH2 CH3
CH2 CH3
3
2009/10/07 shawn
Part from 12X05824B040 change to 12X05824B000.
J16
J16
1P-
VCC1
1P-
LP0-
LP0+
LP1-
LP1+
CH4
CH4
VP
VP
+5VSB
C
C
3 4
7 8
9 11
GND GND
n
n
o
o
1P+
1P+
2P-
2P-
2P+
2P+
SIDE_G11
SIDE_G9
SIDE_G11
SIDE_G9
SIDE_G12
SIDE_G12
SIDE_G10
SIDE_G10
USB_CON _2X4P
USB_CON _2X4P
I
I
f
f
VCC1
12
GND1
GND1
GND
VCC2
VCC2
56
GND2
GND2
GND
d
d
1210
i
i
2
12
e
e
GND
+SBV012 3
n
n
I
I
GND
UC3
UC3
0.1UF/16V
0.1UF/16V
a
a
2009.08.19 shawn
12
UCE3 from 470uF change to 330uF.
i
i
I
I
+
+
UCE3
UCE3
330UF/6.3 V
330UF/6.3 V
t
t
l
l
I
I
UF3
UF3
1.6A/6V
1.6A/6V
I
I
UF7
UF7
1.6A/6V
1.6A/6V
1
+5V_DUA L_USB_R
12
12
B B
r
r
t
t
a
a
g
g
e
e
P
P
A A
5
4
o
o
n
n
PEGATRON DT-MB RESTRICTED SECRET
DOUBLE USB CON.
DOUBLE USB CON.
DOUBLE USB CON.
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Pr oject Name
Size Pr oject Name
Size Pr oject Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
Engineer:
IPX41-D3
IPX41-D3
IPX41-D3
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
31 54Thursday, D ecember 10, 2009
31 54Thursday, D ecember 10, 2009
31 54Thursday, D ecember 10, 2009
1
Rev
Rev
Rev
1.02
1.02
1.02
Page 32
5
D D
URN9A
0Ohm
0Ohm
5%
5%
I
I
1 4
0Ohm
0Ohm
5%
5%
I
I
0Ohm
0Ohm
5%
5%
I
I
1 4
0Ohm
0Ohm
5%
5%
I
I
0Ohm
0Ohm
5%
5%
I
I
14
0Ohm
0Ohm
5%
5%
I
I
0Ohm
0Ohm
5%
5%
I
I
14
0Ohm
0Ohm
5%
5%
I
I
URN9A
UL9
UL9
90OHM/1 00MHz/300mA
90OHM/1 00MHz/300mA
NI
NI
2 3
URN9B
URN9B
URN10A
URN10A
UL10
UL10
90OHM/1 00MHz/300mA
90OHM/1 00MHz/300mA
NI
NI
2 3
URN10B
URN10B
URN11B
URN11B
23
NI
NI
90OHM/1 00MHz/300mA
90OHM/1 00MHz/300mA
UL11
UL11
URN11A
URN11A
URN12B
URN12B
23
NI
NI
90OHM/1 00MHz/300mA
90OHM/1 00MHz/300mA
UL12
UL12
P
P
URN12A
URN12A
GND
GND
e
e
1 2
USBN4[20]
USBP4[20]
C C
USBN5[20]
USBP5[20]
USBN6[20]
B B
USBP6[20]
USBN7[20]
A A
USBP7[20]
3 4
1 2
3 4
3 4
1 2
3 4
1 2
5
4
I
I
UU5
UU5
CM1213 _04SO
CM1213 _04SO
CH1
CH1
1
VN
VN
2
CH2 CH3
CH2 CH3
3 4
I
I
UU6
UU6
CM1213 _04SO
CM1213 _04SO
CH1
CH1
1
VN
VN
2
a
a
CH2 CH3
CH2 CH3
3 4
g
g
4
3
+SBV456 7
2009.010.05 shawn
f
f
I
I
UCB4
UCB4
0.1UF/16V
0.1UF/16V
12
Add UCE6 for front USB droop issue.
I
I
+
+
UCE6
UCE6
330UF/6.3 V
330UF/6.3 V
GND
d
d
i
i
12
I
I
+
+
UCE5
UCE5
330UF/6.3 V
330UF/6.3 V
2009.08.19 shawn
UCE5 from 470uF change to 330uF.
GND
12
I
I
UCB3
UCB3
0.1UF/16V
0.1UF/16V
I
I
P24
P24
1
2
10
2
10
3
LP5LP5+
GND
o
o
LP7LP7+LP6+
GND
LP4LP4+
+5VSB
CH4
CH4
6
VP
VP
5
LP6-
n
n
o
o
r
r
+5VSB
CH4
CH4
6
t
t
VP
VP
5
3 4
5 6
7 8
HEADER _2X5P_K9
HEADER _2X5P_K9
GND
USB HEADER.
COLOR = White
I
I
C
C
P150
P150
1
3 4
5 6
7 8
HEADER _2X5P_K9
HEADER _2X5P_K9
GND
USB HEADER.
COLOR = White
GND
2009.08.19 shawn
P24, P150 color change to white.
+SBV456 7
n
n
12
GND
2
e
e
2
n
n
I
I
UF5
UF5
1.6A/6V
1.6A/6V
I
I
UF6
UF6
1.6A/6V
1.6A/6V
l
l
a
a
i
i
t
t
+5V_DUA L_USB_F
12
12
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Pr oject Name
Size Pr oject Name
Size Pr oject Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
+5VSB
12
NI
NI
YR26
YR26
0
0
mx_r0805
mx_r0805
1
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
IPX41-D3
IPX41-D3
IPX41-D3
1
USB HEADER CON.
USB HEADER CON.
USB HEADER CON.
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
32 54Thursday, D ecember 10, 2009
32 54Thursday, D ecember 10, 2009
32 54Thursday, D ecember 10, 2009
Rev
Rev
Rev
1.02
1.02
1.02
Page 33
5
D D
4
SATA CONNECTOR FOR CPC
SATA CONNECTOR FOR CPC
SATA CONNECTOR FOR CPCSATA CONNECTOR FOR CPC
ICH_SATA LED#[21]
1
2
I
I
TD2
TD2
BAT54AW
BAT54AW
3
3
HD_LED# [42]
2
n
n
t
t
i
i
a
a
l
l
1
C C
SATA CON.
COLOR = Orange
I
I
P60
P60
8
9
SATA_CO N_7P
SATA_CO N_7P
B B
A A
P_GND1
P_GND2
1
1
2
3
4
5
6
7
SATA_TX P0_C
2
SATA_TX N0_C
3
4
SATA_RX N0_C
5
SATA_RX P0_C
6
7
GND GND
P
P
TC17 0.01 UF/25V X7R 10%
TC17 0.01 UF/25V X7R 10%
1 2
I
I
TC18 0.01 UF/25V X7R 10%
TC18 0.01 UF/25V X7R 10%
1 2
I
I
TC19 0.01 UF/25V X7R 10%
TC19 0.01 UF/25V X7R 10%
1 2
I
I
TC20 0.01 UF/25V X7R 10%
TC20 0.01 UF/25V X7R 10%
1 2
I
I
g
g
e
e
a
a
t
t
r
r
SATA_TX P0 [21]
SATA_TX N0 [21]
SATA_RX N0 [21]
SATA_RX P0 [21]
o
o
n
n
C
C
o
o
SATA CON.
COLOR = Orange
I
I
P61
P61
8
1
P_GND1
2
f
f
3
4
5
9
P_GND2
SATA_CO N_7P
SATA_CO N_7P
6
7
n
n
i
i
1
2
3
4
5
6
7
d
d
SATA_TX P1_C
SATA_TX N1_C
SATA_RX N1_C
SATA_RX P1_C
e
e
TC21 0.01 UF/25V X7R 10%
TC21 0.01 UF/25V X7R 10%
1 2
I
I
TC22 0.01 UF/25V X7R 10%
TC22 0.01 UF/25V X7R 10%
1 2
I
I
TC23 0.01 UF/25V X7R 10%
TC23 0.01 UF/25V X7R 10%
1 2
I
I
TC24 0.01 UF/25V X7R 10%
TC24 0.01 UF/25V X7R 10%
1 2
I
I
SATA_TX P1 [21]
SATA_TX N1 [21]
SATA_RX N1 [21]
SATA_RX P1 [ 21]
PEGATRON DT-MB RESTRICTED SECRET
SATA2 FOR CPC
SATA2 FOR CPC
SATA2 FOR CPC
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Pr oject Name
Size Pr oject Name
Size Pr oject Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Engineer:
IPX41-D3
IPX41-D3
IPX41-D3
1
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
33 54Thursday, D ecember 10, 2009
33 54Thursday, D ecember 10, 2009
33 54Thursday, D ecember 10, 2009
1.02
1.02
1.02
Rev
Rev
Rev
Page 34
5
A
RTL8111DL Switc hing regulator
PIN
PIN N AME
48
REG_OU T
4
FB12
43
ENSWRE G
44,45
D D
VDDRE G
8103EL Pin
DVDD3.3V
AVDD3.3V
DVDD1.2V
+1.2V_OUT
I/O
O
I
I
P
29,37
1
10,13,30,36
19,45,48
Function
Regulator output
Feedback pin
3.3V : Enable ; 0V : disable
3.3V power pin
Layout Guide:
+1P2V_OUT & +1P2OUT wider than 60mil
LL1&LR18 place near 200mil to LAN
LCB6&LCB7 place near 300mil to LAN
8111DL Pin
29,37
DVDD3.3V
1,40
AVDD3.3V
13,36
DVDD1.2V
10,30,39
AVDD1.2V
19EVDD1.2V
48+1.0V_OUT
+3P3VSB+1P2 V_VDD
Layout Guide: +3P3VSB wider than 40mil
LC2~LC5 place near 200mil to LAN
+1P2V_O UT
0
0
1 2
I
I
LR4
LR4
/8103_NI
/8103_NI
C C
0
0
1 2
I
I
LR6
LR6
/8103_NI
/8103_NI
LJP1
1 2
SHORTPIN
SHORTPIN
+3P3V
12
B B
12
GND GND GN D
e
e
P
P
4
LR1 0
1 2
I /8103_NI
I /8103_NI
LR2 0
1 2
NI /8103_I
NI /8103_I
+3P3VSB
+1P2V_V DD
I
I
12
LCB8
LCB8
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND GND GND GND GND
NOBOMLJP1
NOBOM
LAN_RXN[20]
LAN_RXP[20]
LAN_TXN[20]
I
I
LR8
LR8
1K
1K
I
I
LR10
LR10
15K
15K
LAN_TXP[20]
CK_100M _LAN[6]
CK_100M _LAN#[6]
PCIEX1_R ST#[24, 39]
g
g
WAK E#[22,24,25]
a
a
mx_r0603LR1 0
mx_r0603
mx_r0603LR2 0
mx_r0603
12
GND GN D G ND GND
12
GND GN D
12
12
I
I
I
LCB2
LCB2
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
I
I
LCB6
LCB6
22UF/6.3V
22UF/6.3V
X5R 10%
X5R 10%
mx_c1206
mx_c1206
/8103_NI
/8103_NI
I
I
LCB9
LCB9
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
t
t
I
LCB3
LCB3
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
I
I
12
LCB7
LCB7
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
I
I
12
LCB10
LCB10
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
LC2 0. 1UF/16V X7R 10%
LC2 0. 1UF/16V X7R 10%
1 2
I
I
LC1 0. 1UF/16V X7R 10%
LC1 0. 1UF/16V X7R 10%
1 2
I
I
o
o
r
r
12
NI
NI
LC3
LC3
10PF/50V
10PF/50V
NPO 5%
NPO 5%
CK_25M _LAN[6]
2009.08.14 shawn
LCB17 from 22uF 20% (11X23A226160)
change to 22uF 10% (11X23A226150)
+SW REG/+1P2VOUT
I
I
LCB17
LCB17
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c1206
mx_c1206
/8103_NI
/8103_NI
I
I
LCB4
LCB4
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
LL1
LL1
/8103NI
/8103NI
4.7UH/1.7A
4.7UH/1.7A
I
I
0
0
1 2
LR18
LR18
NI
NI
/8103_I
/8103_I
I
I
LCB11
LCB11
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
I
I
LCB18
LCB18
1UF/16V
1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
I
I
LR12
LR12
2.49K
2.49K
1%
1%
12
I
I
LCB1
LCB1
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
12
I
I
LCB5
LCB5
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
+1P2OUT
21
I
I
12
LCB12
LCB12
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
+1P2V_E VDD
I
I
12
LCB13
LCB13
1UF/16V
1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
C
C
LAN_RXN _C
LAN_RXP _C
LAN_ISOL ATEB
LANRSET
FB12
12
GND GND
12
12
12
GND GND
n
n
12
3
44
45
29
37
40
48
13
36
30
10
39
19
21
20
16
15
17
18
28
26
27
46
41
42
I
I
LU2
LU2
VDDSR2
VDDSR1
VDD33_1
VDD33_2
1
AVDD33_1
AVDD33_2
SROUT12
DVDD12_1
DVDD12_2
DVDD12_3
AVDD12_1
AVDD12_2
EVDD12
4
o
o
FB12
HSON
HSOP
HSIN
HSIP
REFCLK_P
REFCLK_N
ISOLATEB
LANWAKEB
PERSTB
RSET
CKTAL1
CKTAL2
RTL8111D L_GR
RTL8111D L_GR
MDIN0
MDIP0
MDIN1
MDIP1
MDIN2
MDIP2
MDIN3
MDIP3
EECS
LED0
LED1/EESK
LED2/EEDI/AUX
LED3/EEDO
n
n
CLKREQB
ENSR
EGND
GND2
GND1
GND3
GND4
f
f
NC1
NC2
3
2
6
5
9
8
12
11
32
38
35
34
33
i
i
O/D
25
43
23
24
22
7
14
31
47
LAN_EECS
LAN_EEDI
LAN_EEDO
d
d
ENSW REG
GND
NI
NI
LR7
LR7
10KOhm
10KOhm
e
e
/8103_I
/8103_I
1 2
GND
+3P3VSB
2
+3P3VSB
12
I
I
LR5
LR5
3.6K
3.6K
n
n
12
I
I
LR9
LR9
0
0
/8103_NI
/8103_NI
12
NI
NI
LR11
LR11
0
0
GND
+3P3VSB
12
t
t
1
LAN_MDI0_ N [35]
LAN_MDI0_ P [35]
LAN_MDI1_ N [35]
LAN_MDI1_ P [35]
LAN_MDI2_ N [35]
LAN_MDI2_ P [35]
LAN_MDI3_ N [35]
LAN_MDI3_ P [35]
l
NI
NI
LR26
LR26
4.7K
4.7K
i
i
l
a
a
REALTEK _ACTLED# [35]
REALTEK_ LINK100# [ 35]
REALTEK_ LINK1G# [35]
NOTE:
If using eFuse funtion,
NI LU2 directly
NOTE: LED MODE
(LEDS1, LEDS0) = (1, 1) DEFAULT
(LEDS1, LEDS0) = (0, 1) ==> For this schematic
NOTE: 8111DL[PIN43]
3.3V enable internal regulator
0V disable internal regulator
PEGATRON DT-MB RESTRICTED SECRET
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
IPX41-D3
IPX41-D3
IPX41-D3
Engineer:
AR8121 CONTROLLER
AR8121 CONTROLLER
AR8121 CONTROLLER
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
34 54Thursday, D ecember 10, 2009
34 54Thursday, D ecember 10, 2009
34 54Thursday, D ecember 10, 2009
1.02
1.02
1.02
Rev
Rev
Rev
A
Page 35
5
IIII
IIII
UU7
UU7
CM1213 _04SO
CM1213 _04SO
CH1
CH1
1
VN
VN
2
CH2 CH3
CH2 CH3
3 4
CH1
CH1
1
VN
VN
2
CH2 CH3
CH2 CH3
3 4
10/2 modify
LAN_MDI0_ P[34]
LAN_MDI0_ N[34]
LAN_MDI1_ P[34]
LAN_MDI1_ N[34]
LAN_MDI2_ P[34]
LAN_MDI2_ N[34]
LAN_MDI3_ P[34]
LAN_MDI3_ N[34]
GND
GND
USBN2[20]
USBP2[20]
USBN3[20]
USBP3[20]
LAN_MDI2_ P
LAN_MDI3_ N
5
D D
C C
B B
A A
IIII
IIII
UU8
UU8
CM1213 _04SO
CM1213 _04SO
I
I
3 4
0Ohm
0Ohm
5%
5%
14
I
I
1 2
0Ohm
0Ohm
5%
5%
I
I
3 4
0Ohm
0Ohm
5%
5%
14
I
I
1 2
0Ohm
0Ohm
5%
5%
CH4
CH4
LAN_MDI1_ PLAN_MDI1_N
6
VP
VP
5
LAN_MDI0_ PLAN_MDI0_NLAN_MDI 0_N
CH4
CH4
LAN_MDI2_ N
6
VP
VP
5
LAN_MDI3_ P
URN13B
URN13B
23
NI
NI
90OHM/1 00MHz/300mA
90OHM/1 00MHz/300mA
UL13
UL13
URN13A
URN13A
URN14B
URN14B
23
NI
NI
90OHM/1 00MHz/300mA
90OHM/1 00MHz/300mA
UL14
UL14
URN14A
URN14A
P
P
e
e
+5VSB
2009.08.10 shawn
LCB25 near to UU7.
12
I
I
LCB25
LCB25
0.1UF/16V
0.1UF/16V
GND
+5VSB
2009.08.10 shawn
LCB26 near to UU8.
12
I
I
LCB26
LCB26
0.1UF/16V
0.1UF/16V
GND
GND
g
g
4
09/11 modify
+3P3VSB
12
I
I
LR20
LR20
200
200
mx_r0603
mx_r0603
ICH_ACT_C TRL
REALTEK _ACTLED#[34] REALTEK_ LINK100# [34]
o
CH4
CH4
6
VP
VP
5
r
r
o
+5VSB
NI
NI
NI
NI
NINI
NINI
UU4
UU4
CM1213 _04SO
CM1213 _04SO
CH1
CH1
1
VN
VN
2
a
a
CH2 CH3
CH2 CH3
3 4
4
t
t
LAN + Dual USB CONNECTOR
12
I
I
LC15
LC15
1000PF/ 50V
1000PF/ 50V
X7R 10%
X7R 10%
GND
12
I
I
LC12
LC12
1000PF/ 50V
1000PF/ 50V
X7R 10%
X7R 10%
GND
8/19 modify
LP2-
n
n
LP2+
LP3-
LP3+
3
12XA05MYJG40
giga LAN connector
/Change to 12XA070YG040 for 10/100
/Change to 12XA070YG040 for 10/100
I
I
J9
J9
JACK_USB /LAN_GIGA
JACK_USB /LAN_GIGA
19
ACTLEDP
Y
Y
20
ACTLEDN
10
TD1+
11
TD1-
12
TD2+
13
TD2-
14
TD3+
15
TD3-
16
TD4+
17
TD4-
C
C
6
1P-
7
1P+
2
2P-
3
2P+
3
VCC_CTR
GND_CTR
LANGND30
LANGND29
LANGND26
LANGND25
o
o
USBGND28
USBGND27
USBGND24
USBGND23
LILEDP
G
G
LILEDN
n
n
VCC1
GND1
VCC2
GND2
21
22
9
18
f
f
30
29
26
25
5
8
1
4
28
27
24
23
LINKLED# _Q
VCC_CTR
GND_CTR
i
i
GND
GND
12
I
I
LC11
LC11
1000PF/ 50V
1000PF/ 50V
X7R 10%
X7R 10%
GND
12
I
I
LC16
LC16
1000PF/ 50V
1000PF/ 50V
X7R 10%
X7R 10%
GND
8/19 modify
d
d
12
I
I
LR22
LR22
0
0
/8102E_NI
/8102E_NI
GND GND
12
GND
8/19 modify8/19 modify
NI
NI
UCB6
UCB6
0.1UF/16V
0.1UF/16V
2
e
e
NI
NI
12
LCB23
LCB23
0.1UF/16V
0.1UF/16V
/8102E_I
/8102E_I
8/29 modify
+SBV012 3
2009.08.10 shawn
UCB5 removed.
2
n
n
12
NI
NI
LCB22
LCB22
0.01UF/25 V
0.01UF/25 V
X7R 10%
X7R 10%
/8102E_I
/8102E_I
GND
REALTEK_ LINK1G# [34]
l
l
a
a
i
i
t
t
PEGATRON DT-MB RESTRICTED SECRET
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Pr oject Name
Size Pr oject Name
Size Pr oject Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
IPX41-D3
IPX41-D3
IPX41-D3
1
RJ45+USB CONN.
RJ45+USB CONN.
RJ45+USB CONN.
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
35 54Thursday, D ecember 10, 2009
35 54Thursday, D ecember 10, 2009
35 54Thursday, D ecember 10, 2009
Rev
Rev
Rev
1.02
1.02
1.02
Page 36
5
D D
Change to alc 662
AZ_SDATA _IN2[ 22]
AZ_SDATA _OUT[22]
AZ_SYNC[22]
AZ_RST#[22]
AZ_BITCLK[22]
AD48
AD48
I
I
1
2
+5VSB
2009.10.01 shawn
C C
+12V
B B
12
GND
A A
AR7, AR8, AC26, ACB3, and AQ1 removed.
I
I
AU2
AU2
8
7
6
5
AGND
I
I
ACB7
ACB7
10UF/16V
10UF/16V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
1 2
PLACE NEAR fron t audio CODEC FOR E MI
Vout
Vin
GND1
GND4
GND2
GND3
NC1
NC2
78L05
78L05
1.00 use it to avoid the power unstable
1 2
I
I
AR9
AR9
1M
1M
NI
NI
AC41
AC41
100PF/5 0V
100PF/5 0V
NPO 5%
NPO 5%
1 2
I
I
AR69
AR69
0
0
5
1 2
HDA_1P 5V
1 2
GND
BAT54CW
BAT54CW
3
1
2
3
4
GNDAGND
+3P3V
AR37
AR37
237 OHM
237 OHM
1%
1%
I
I
12
I
AR38
AR38
200 Ohm
200 Ohm
1%
1%
I
I
I
ACB8
ACB8
0.1UF/16V
0.1UF/16V
Y5V +80-20%
Y5V +80-20%
GND
1 2
Already install ACE21, so NI ACE14
+5VA_AZ
2009.10.01 shawn
ACE11 EL CAP 100uF/16V removed.
AGND
I
12
I
I
AR11
AR11
20K
20K
1%
1%
I
12
ACB6
ACB6
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
AGNDAG ND
P
P
12
NI
NI
ACB1
ACB1
0.1UF/16V
0.1UF/16V
Y5V +80-20%
Y5V +80-20%
I
I
AR1
AR1
33
33
12
NI
NI
AC3
AC3
10PF/50V
10PF/50V
NPO 5%
NPO 5%
GND GND
3
3
I
I
D
D
AQ3
AQ3
AP2306G N
AP2306G N
1
1
G
G
S
S
2
2
VREF_FILT
e
e
12
AGND
NI
NI
AC4
AC4
22PF/50V
22PF/50V
NPO 5%
NPO 5%
12
+
+
I
I
ACE10
ACE10
100uF/16 V
100uF/16 V
AQ3_G
NOBOM
NOBOM
NOBOM
NOBOM
g
g
4
NOBOM
NOBOM
12
I
I
ACB2
ACB2
0.1UF/16V
0.1UF/16V
Y5V +80-20%
Y5V +80-20%
GNDG ND
RSDATA_IN 0
12
AGND
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
12
I
I
AC2
AC2
0.1UF/16V
0.1UF/16V
NOBOM
NOBOM
GND
T2122 TPC2 6b
T2122 TPC2 6b
T2123 TPC2 6b
T2123 TPC2 6b
4
T2121 TPC2 6b
T2121 TPC2 6b
GND
NI
NI
ACB4
ACB4
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
AGND
T2124 TPC2 6b
T2124 TPC2 6b
T2120 TPC2 6b
T2120 TPC2 6b
T2071 TPC2 6b
T2071 TPC2 6b
T2118 TPC2 6b
T2118 TPC2 6b
T2081 TPC2 6b
T2081 TPC2 6b
Y5V +80-20%
Y5V +80-20%
T2119 TPC2 6b
T2119 TPC2 6b
a
a
1
1
1
GND
12
NI
NI
AC8
AC8
10PF/50V
10PF/50V
NPO 5%
NPO 5%
+5VA
12
NI
NI
ACB5
ACB5
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
1
1
1
1
1
1
t
t
TP_CODE C_33
ALC_JD REF
o
o
r
r
TP_CODE C_45
TP_CODE C_46
3
SURR-R(PORT-A-R)
SURR-L(PORT-A-L)
MIC1-R(PORT-B-R)
MIC1-L(PORT-B-L)
LINE1-R(PORT-C-R)
LINE1-L(PORT-C-L)
FRONT-R(PORT-D-R)
FRONT-L(PORT-D-L)
CENTER(PORT-G-L)
LFE(PORT-G-R)
LINE2-R(PORT-E-R)
LINE2-L(PORT-E-L)
MIC2-L(PORT-F-L)
MIC2-R(PORT-F-R)
o
o
C
C
MIC2-VREFO
LINE2-VREFO
MIC1-VREFO-R
MIC1-VREFO-L
NC1
SenseA
SenseB
NC5
SPDIFO
EAPD
41
39
MIC1_RC
22
MIC1_LC I_MIC1_L_C
21
LIN1_RC I_LIN1_R_C
24
LIN1_LC
23
FRONT_R C
36
FRONT_LC
35
TP_CODE C_44
43
TP_CODE C_43
44
F_LIN2_RC
15
F_LIN2_LC
14
MIC2_LC
16
MIC2_RC
17
f
f
TP_CODE C_37
37
n
n
13
34
30
31
TP_CODE C_29
29
32
28
SPDIF_OU T_A
48
TP_CODE C_47
47
i
i
I
I
I
I
I
I
I
I
d
d
AGND
TP_CODE C_2
TP_CODE C_3
TP_CODE C_18
TP_CODE C_19
TP_CODE C_20
TP_CODE C_12
I
I
AU22
AU22
AU22
AU22
AU22AU22
AU22AU22
33
NC4
1
DVDD1
9
DVDD_IO
4
DVSS1
7
DVSS2
8
SDATA-IN
5
SDATA-OUT
10
SYNC
11
RESET#
6
BCLK
25
AVDD1
38
AVDD2
26
AVSS1
42
AVSS2
2
GPIO0
3
GPIO1
18
CD-L
19
CD-GND
20
CD-R
12
PCBEEP
n
n
40
JDREF
27
VREF
45
NC2
46
NC3
ALC662-G R
ALC662-G R
SPDIF OUT1 CONNECTOR
I
I
AL99
I
I
12
AC37
AC37
100PF/5 0V
100PF/5 0V
NPO 5%
NPO 5%
AL99
120Ohm/10 0Mhz/0.6A
120Ohm/10 0Mhz/0.6A
21
AR70 0 Ohm 5%
AR70 0 Ohm 5%
I
SPDIF_OU T_A R_SPDIF_ OUT_A SPDIF_O_ L
I
1 2
3
GND
12
NI
NI
AR71
AR71
200
200
5%
5%
2
AC11 4.7UF/6. 3V
AC11 4.7UF/6. 3V
1 2
X5R 10%
1 2
1 2
1 2
+
+
1 2
+
+
1 2
+
+
e
e
1 2
+
+
1 2
1 2
1 2
T2088
T2088
1
TPC26b
TPC26b
T2087
T2087
1
TPC26b
TPC26b
I
I
AC38
AC38
0.1UF/16V
0.1UF/16V
Y5V +80-20%
Y5V +80-20%
X5R 10%
X5R 10%
X5R 10%
X5R 10%
X5R 10%
X5R 10%
X5R 10%
T2084
T2084
T2085
T2085
1
1
TPC26b
TPC26b
TPC26b
TPC26b
n
n
X5R 10%
X5R 10%
T2086
T2086
X5R 10%
X5R 10%
1
TPC26b
TPC26b
NOBOM
NOBOM
NOBOM
NOBOM
I
I
P22
P22
1
3
4
HEADER _1X4P_K2
HEADER _1X4P_K2
GNDGNDGND
2
AC18 4.7UF/6. 3V
AC18 4.7UF/6. 3V
AC5 4.7U F/6.3V
AC5 4.7U F/6.3V
I
I
AC7 4.7U F/6.3V
AC7 4.7U F/6.3V
I
I
ACE4 100uF/16V
ACE4 100uF/16V
ACE5 100uF/16V
ACE5 100uF/16V
ACE6 100uF/16V
ACE6 100uF/16V
I
I
ACE7 100uF/16V
ACE7 100uF/16V
I
I
ACE8 4.7UF/6.3V
ACE8 4.7UF/6.3V
I
I
ACE9 4.7UF/6.3V
ACE9 4.7UF/6.3V
I
I
+5V
12
AR30 75
AR30 75
I
I_MIC1_R_C
I_LIN1_L_C
I_FRONT_ R_C
I_FRONT_ L_C
2009.08.14 shawn
AR53~AR56 from 22K 5% change to 22K 1%
NOBOM
NOBOM
NOBOM
NOBOM
t
t
R_LIN2_RC
R_LIN2_LC
I_MIC2_L_C
I_MIC2_R_C
NOBOM
NOBOM
I
1 2
AR31 75
AR31 75
I
I
1 2
AR34 75
AR34 75
I
I
1 2
AR35 75
AR35 75
I
I
1 2
AR15 75
AR15 75
I
I
1 2
1 2
AR16 75
AR16 75
l
l
I
I
a
a
i
i
AR2 75
AR2 75
I
I
1 2
1 2
AR5 75
AR5 75
I
I
AR4 1KIAR4 1K
I
1 2
1 2
AR6 1KIAR6 1K
I
PEGATRON DT-MB RESTRICTED SECRET
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
12
12
I
I
AR73
AR73
22K
22K
1%
1%
AGND AGND
IPX41-D3
IPX41-D3
IPX41-D3
1
MIC1_R_C [37]
MIC1_L_C [37]
LIN1_R_C [37]
LIN1_L_C [37]
FRONT_R _C [ 37]
FRONT_L _C [37]
I
I
AR74
AR74
22K
22K
1%
1%
LIN2_R_C [37]
LIN2_L_C [37]
MIC2_L_C [37]
MIC2_R_C [37]
SENSE_A [37]
SENSE_B [37]
MIC2_VREF [37]
LIN2_VRE F [37]
MIC1_VRE F_R [37]
MIC1_VRE F_L [37]
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
1
Rear_Mic
Rear_LineIn
Rear_LineOut
Front_LineOut
Front_MIC
ALC662 A UDIO CODEC
ALC662 A UDIO CODEC
ALC662 A UDIO CODEC
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
36 54Thursday, D ecember 10, 2009
36 54Thursday, D ecember 10, 2009
36 54Thursday, D ecember 10, 2009
Rev
Rev
Rev
1.02
1.02
1.02
Page 37
5
I
I
AD47
AD47
BAW 56WPT
BAW 56WPT
MIC2_VREF[36]
D D
LIN2_VRE F[36]
MIC2_L_C[36]
MIC2_R_C[36]
LIN2_R_C[36]
LIN2_L_C[36]
C C
LIN1_L_C[36]
LIN1_R_C[ 36]
FRONT_L _C[36]
SENSE_A[36]
FRONT_R _C[ 36]
MIC1_L_C[36]
MIC1_R_C[36]
B B
MIC1_VRE F_L[36]
MIC1_VRE F_R[36]
3
I
I
AD46
AD46
BAW 56WPT
BAW 56WPT
3
MIC2_VRE F_R
2
MIC2_VRE F_L
1
LIN2_VRE F_R
2
LIN2_VRE F_L
1
12
12
AGND AG ND AGND
AR10 4 .7K
AR10 4 .7K
1 2
I
I
AR19 4 .7K
AR19 4 .7K
1 2
I
I
I
I
AR56
AR56
22K
22K
1%
1%
I
I
AR55
AR55
22K
22K
1%
1%
1 2
4.7KOHM
4.7KOHM
3 4
4.7KOHM
4.7KOHM
5 6
4.7KOHM
4.7KOHM
7 8
4.7KOHM
4.7KOHM
12
I
I
AR54
AR54
22K
22K
1%
1%
AGND
I
I
I
I
I
I
AR24&AR25&AR26
Place near to codec
4
ARN140A
5%IMX_4R8 P0402ARN140A
5%IMX_4R8 P0402
ARN140B
5%IMX_4R8 P0402ARN140B
5%IMX_4R8 P0402
ARN140C
5%IMX_4R8 P0402ARN140C
5%IMX_4R8 P0402
ARN140D
5%IMX_4R8 P0402ARN140D
5%IMX_4R8 P0402
AR60 0Imx_r0603AR60 0Imx_r0603
AR61 0Imx_r0603AR61 0Imx_r0603
2009.08.14 shawn
12
AR53~AR56 from 22K 5% change to 22K 1%
I
I
AR53
AR53
22K
22K
1%
1%
AL5/AL6/AL11/AL8/AL9/AL10;Please use 09X131216000
instead of 0 ohm if you found have EMI issue
AR26 10K 1%
AR26 10K 1%
1 2
AR24 5.1K 1%
AR24 5.1K 1%
1 2
AR25 20K 1%
AR25 20K 1%
1 2
AL83 120Ohm/ 100Mhz/0.6A
AL83 120Ohm/ 100Mhz/0.6A
I
I
AL84 120Ohm/ 100Mhz/0.6A
AL84 120Ohm/ 100Mhz/0.6A
I
I
t
t
21
21
1 2
1 2
AL5 0VPmx_r0603AL5 0VPmx_r0603
1 2
AL6 0VPmx_r0603AL6 0VPmx_r0603
1 2
AL7 0VPmx_r0603AL7 0VPmx_r0603
1 2
AL8 0VPmx_r0603AL8 0VPmx_r0603
1 2
AL9 0VPmx_r0603AL9 0VPmx_r0603
1 2
AL10 0VPmx_r0603AL10 0VPmx_r0603
1 2
o
o
r
r
n
n
12
AGND
3
I
I
AC15
AC15
100PF/5 0V
100PF/5 0V
NPO 5%
NPO 5%
12
I
I
AC12
AC12
100PF/5 0V
100PF/5 0V
NPO 5%
NPO 5%
o
o
12
I
I
AC19
AC19
100PF/5 0V
100PF/5 0V
NPO 5%
NPO 5%
n
n
12
I
I
AC14
AC14
100PF/5 0V
100PF/5 0V
NPO 5%
NPO 5%
AGND AG ND AGND AG ND
C
C
12
I
I
AC17
AC17
100PF/5 0V
100PF/5 0V
NPO 5%
NPO 5%
12
I
I
AC20
AC20
100PF/5 0V
100PF/5 0V
NPO 5%
NPO 5%
12
I
I
AC13
AC13
100PF/5 0V
100PF/5 0V
NPO 5%
NPO 5%
MIC2_L
MIC2_R
LIN2_R
LIN2_L
f
f
12
AUDIO HEADER
Color = GREEN
1
3 4
5 6
7
9 10
d
d
i
i
I
I
AC21
AC21
100PF/5 0V
100PF/5 0V
NPO 5%
NPO 5%
AGNDAGND AGNDAGND AGNDAGND
I
I
P23
P23
2
MIC_JD
LIN_JD
HEADER _2X5P_K8
HEADER _2X5P_K8
e
e
12
I
I
AC22
AC22
100PF/5 0V
100PF/5 0V
NPO 5%
NPO 5%
2
n
n
AGND
12
I
I
AC23
AC23
100PF/5 0V
100PF/5 0V
NPO 5%
NPO 5%
+3P3V
12
I
I
AR52
AR52
10K
10K
I
I
I
I
i
i
12
AR21&AR22 Place near to codec
NI
NI
AC16
AC16
t
t
0.1UF/16V
0.1UF/16V
Y5V +80-20%
Y5V +80-20%
GND
LIN1_L
LIN1_JD
LIN1_R
FRONT_L
FRONT_J D
FRONT_R
MIC1_L
MIC1_JD
MIC1_R
AGND
1 2
a
a
1 2
I
I
J83
J83
AUDIO_3IN 1_AZA_13P
AUDIO_3IN 1_AZA_13P
L
L
32
33
PORT3
PORT3
34
R
R
35
L
L
22
23
PORT2
PORT2
24
R
R
25
L
L
2
3
PORT1
PORT1
4
R
R
5
1
G1
P_GND1
P_GND1
G2
P_GND2
P_GND2
G3
P_GND3
P_GND3
G4
P_GND4
P_GND4
l
l
AR5820K 1%
AR5820K 1%
AR5739.2K 1%
AR5739.2K 1%
B
B
L
L
P
P
P1
NP_NC1
NP_NC1
2009.08.10 shawn
JP2 removed for EMI concern.
1
F_AUDIO_D ET# [22]
SENSE_B [36]
a
a
2009.08.11 shawn
AC10 removed by EMI request.
AR59 change to short pin.
g
g
e
e
P
P
A A
PLACE NEAR fron t audio header FOR EMI
5
1 2
NOBOM
NOBOM
AR59
AR59
SHORTPIN
SHORTPIN
4
GNDAGND GNDAGND
PLACE NEAR AUDI O Connector FOR EMI
NI
NI
AC34
AC34
100PF/5 0V
100PF/5 0V
NPO 5%
NPO 5%
1 2
I
I
AR65
AR65
0
0
1 2
3
AGND
PEGATRON DT-MB RESTRICTED SECRET
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
2
IPX41-D3
IPX41-D3
IPX41-D3
Engineer:
AUDIO CONN
AUDIO CONN
AUDIO CONN
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
1
Rev
Rev
Rev
1.02
1.02
37 54Thursday, D ecember 10, 2009
37 54Thursday, D ecember 10, 2009
37 54Thursday, D ecember 10, 2009
1.02
Page 38
5
4
3
2
1
+5VSB
SLP_S4#[19 ,22,39]
D D
2009.08.10 shawn
EC10 removed.
C C
12
GND
+VCORE
12
NI
NI
EC15
EC15
0.1UF/16V
0.1UF/16V
GND GND
12
NI
NI
NI
EC1
EC1
0.1UF/16V
0.1UF/16V
NI
EC2
EC2
0.1UF/16V
0.1UF/16V
GND GND
+3P3VSB
for RTCR ST# cros s moat
for RTCR ST# cros s moat
for RTCR ST# cros s moatfor RTCRST# cr oss moat
12
NI
NI
EC19
EC19
0.1UF/16V
0.1UF/16V
GND
12
NI
NI
EC16
EC16
0.1UF/16V
0.1UF/16V
12
NI
NI
EC3
EC3
0.1UF/16V
0.1UF/16V
12
NI
NI
EC17
EC17
0.1UF/16V
0.1UF/16V
GND GND
12
+1P1V_FS B_VTT
NI
NI
EC18
EC18
0.1UF/16V
0.1UF/16V
+12V
12
GND
+3P3V
2009.08.14 shawn
Add EC20, EC21 for F_USB signal.
GND GND GN D GN D GND GND GND
12
NI
NI
EC4
EC4
0.1UF/16V
0.1UF/16V
GND
2009.08.10 shawn
EC12, EC13, EC14 removed.
12
NI
NI
EC11
EC11
0.1UF/16V
0.1UF/16V
GND GND
12
12
I
I
EC20
EC20
0.1UF/16V
0.1UF/16V
NI
NI
EC12
EC12
0.1UF/16V
0.1UF/16V
I
I
EC21
EC21
0.1UF/16V
0.1UF/16V
+1P5V_D UAL
12
GND GND GND GND
12
NI
NI
EC13
EC13
0.1UF/16V
0.1UF/16V
NI
NI
EC6
EC6
0.1UF/16V
0.1UF/16V
2009.10.06 shawn
Add EC12, EC13.
2009.10.06 shawn
Add EC22 ~ EC26.
12
I
I
EC22
EC22
0.1UF/16V
0.1UF/16V
12
NI
NI
EC7
EC7
0.1UF/16V
0.1UF/16V
12
12
NI
NI
EC8
EC8
0.1UF/16V
0.1UF/16V
12
I
I
EC23
EC23
0.1UF/16V
0.1UF/16V
C
C
I
I
EC24
EC24
0.1UF/16V
0.1UF/16V
12
NI
NI
EC9
EC9
0.1UF/16V
0.1UF/16V
+1P1V_C ORE
12
NI
NI
EC27
EC27
0.1UF/16V
0.1UF/16V
GND GND
12
I
I
EC25
EC25
0.1UF/16V
0.1UF/16V
o
o
2009.10.06 shawn
Add EC27, EC28.
12
NI
NI
EC28
EC28
0.1UF/16V
0.1UF/16V
12
I
I
EC26
EC26
0.1UF/16V
0.1UF/16V
n
n
f
f
i
i
+5V
12
GND GND
d
d
NI
NI
EC29
EC29
0.1UF/16V
0.1UF/16V
e
e
2009.10.07 shawn
Add EC29, EC30.
12
NI
NI
EC30
EC30
0.1UF/16V
0.1UF/16V
n
n
t
t
i
i
a
a
l
l
B B
r
r
t
t
a
a
g
g
e
e
P
P
A A
5
4
o
o
n
n
PEGATRON DT-MB RESTRICTED SECRET
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Pr oject Name
Size Pr oject Name
Size Pr oject Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
IPX41-D3
IPX41-D3
IPX41-D3
Engineer:
EMI CAP
EMI CAP
EMI CAP
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
38 54Thursday, D ecember 10, 2009
38 54Thursday, D ecember 10, 2009
38 54Thursday, D ecember 10, 2009
1
Rev
Rev
Rev
1.02
1.02
1.02
Page 39
5
+3P3V
D D
+3P3VSB
2009.08.10 shawn
O2CB3 removed.
Pin 3: SERIRQ
Please check if this pin need
be pull-up on chipset side!
LAD3[22,43]
LAD2[22,43]
LAD1[22,43]
LAD0[22,43]
LFRAME#[22 ,43]
C C
B B
A A
PLTRST#[13,22,43]
CK_33M_SI O[6]
SERIRQ[21,43]
Pin 14/15/16/17：OD Pin
1.Please check if this pin need be pull-up
on the other side!
2.If not used, please PU to standby power
Please check if another side already
Pull-up
CPUFAN_ PWM[41]
F_FAN_PW M[41]
CPUFAN_ TACH[41]
F_CHAFA N_TACH[41]
NOTE
O2Q2 MOS Selection
Base on your plateform
Please check Power guy
+5VSB
12
+
+
I
I
O2CE1
O2CE1
100uF/16 V
100uF/16 V
GND GND GND
：
O2R1 0 Ohm 5%NImx_r1206O2R1 0 Ohm 5%NImx_r1206
1 2
I
I
O2Q2
O2Q2
DSG
DSG
5
6
7
8
SI4835DDY-T1- E3
SI4835DDY-T1- E3
4
3
2
1
GND
GND
+5VSB_A TX
VSB_GATE
12
I
I
O2C4
O2C4
10UF/16V
10UF/16V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
WDT function selection.
1(Default): (I nternal pull high) WDT disable.
0: (External pull down) WD T enable.
5
12
I
I
O2CB1
O2CB1
0.1UF/16V
0.1UF/16V
12
I
I
O2CB4
O2CB4
0.1UF/16V
0.1UF/16V
+5VSB_A TX
12
I
I
O2R65
O2R65
10K
10K
12
I
I
O2R66
O2R66
1K
1K
12
I
I
O2C3
O2C3
1UF/10V
1UF/10V
mx_c0603
mx_c0603
+3P3VSB
12
I
I
O2CB2
O2CB2
0.1UF/16V
0.1UF/16V
GND
+3P3V
EUP_CTRL1# (PIN20)
You can use this pin for other power plane control
P
P
+BATT
12
12
NI
NI
O2R37
O2R37
10K
10K
I
I
O2CB5
O2CB5
0.1UF/16V
0.1UF/16V
GND
12
NI
NI
O2CB6
O2CB6
0.1UF/16V
0.1UF/16V
KBDATA[40]
KBCLK[40]
MSDATA[40]
MSCLK[40]
RST_KB[21]
A20GATE[21]
EVENT_IN# (PIN19)
You can use this pin for WOL
CK_48M_SI O[6]
e
e
12
NI
NI
O2CB7
O2CB7
0.1UF/16V
0.1UF/16V
GNDGND
LPC_SMI#[22]
：
g
g
+3P3VSB
4
+5VSB_A TX
：
a
a
I
I
O2R64 4.7K
O2R64 4.7K
1 2
NI
NI
O2R69 1K
O2R69 1K
1 2
GND
4
For EUP6.0 used
GND
+3P3V+ 3P3V
12
12
NI
NI
NI
NI
O2R35
O2R35
O2R36
O2R36
10K
10K
10K
10K
+3P3V
12
r
r
I
I
O2R6
O2R6
4.7K
4.7K
t
t
RI#
WDT _EN#
I
I
02X2E000L000
O2U1
O2U1
1
VCC
25
VSB
+5VSB_ATX:
FROM POWER SUPPLY
38
5VSB_IN/CHASSIS
48
AVSB
37
VBAT
11
GND1
65
GND2
8
LAD3
7
LAD2
6
LAD1
5
LAD0
4
LFRAM#
2
LRESET#
9
PCICLK
3
SERIRQ
14
KDAT/GPIO10
15
KCLK/GPIO11
16
MDAT/GPIO12
17
MCLK/GPIO13
12
KBRST#
13
GA20
62
CPUFANOUT
64
SYSFANOUT1/GPIO34
61
CPUFANIN
63
SYSFANIN1
o
o
For EUP6.0 used
19
GPIO21/OVT#/SYSFANIN2/EVENT_IN#
20
GPIO22/SYSFANOUT2/CTRL1#
26
CTRL0#
10
CLKIN
21
GPIO23/WDTRST#/SYSFANIN2
53
DCD#/GPIO00
54
RI#/GPIO01
55
CTS#/GPIO02
58
DSR#/GPIO05
60
SIN/GPIO07
57
RTS#/GPIO04/WDT_EN
F71808EU
F71808EU
PECI_REQ/TSICLK/IBXCLK/GPIO33
n
n
3
RSMRST#
PSIN#/GPIO27
PSOUT#/GPIO14
SLP_S3#
SLP_S5#
PWROK
3VSBSW#
GPIO20/PME#
GPIO24/LEDVSB
GPIO25/LEDVCC
RESETCON#/GPIO26
DTR#/GPIO03/FAN40_100
SOUT/GPIO06/Config4E_2E
PECI/TSIDAT/IBXDAT/GPIO32
AGND/D-
C
C
VDIMM/VIN3
VLDT/VIN2
CPUVCORE/VIN1
RESETOUT1#
RESETOUT2#
VLDT_EN/GPIO31
VCORE_EN/GPIO30
3
O2R9 4.7 K
O2R9 4.7 K
I
I
O2R10 4.7K
O2R10 4.7K
I
I
1 2
O2R11 4.7K
O2R11 4.7K
1 2
I
I
O2R13 4.7K
O2R13 4.7K
1 2
I
I
1 2
36
31
32
34
PSON#
33
30
+3P3V +3P3VSB
+3P3VSB
12
12
NI
NI
O2R79
O2R79
4.7K
4.7K
f
f
12
I
I
O2C2
O2C2
2200PF/ 50V
2200PF/ 50V
X7R 10%
X7R 10%
+3P3V
12
12
I
I
O2R14
O2R14
4.7K
4.7K
d
d
12
I
I
i
i
O2R4
O2R4
1K
1K
GNDGND
+VCORE
12
I
I
O2R30
O2R30
1K
1K
GND
12
I
I
O2C9
O2C9
0.1UF/16V
0.1UF/16V
I
I
O2R44
O2R44
GND
4.7K
4.7K
Note：Pin28 is OD
Pin
12
NI
NI
O2R3
O2R3
1K
1K
1
1
I
I
O2R12
O2R12
4.7K
4.7K
35
24
18
22
23
RSTIN#
Front pannel header already pull-high to +3VSB.
RSTIN#
27
FAN40_1 00
56
CONFIG4E _2E
59
52
51
n
n
41
D1+
o
o
39
SYSTIN
40
D2+
I
I
O2C25
O2C25
0.1UF/16V
0.1UF/16V
42
VIN5
VIN4
43
44
45
46
47
28
29
50
49
1 2
GND
+12V(VIN3)
+5V(VIN2)
VCORE(VIN1)
VREF
I
I
O2D1
O2D1
BAT54AW
BAT54AW
3
SYS_RESE T# [8,22,42]
e
e
3
3
C
C
I
I
B
B
O2Q1
O2Q1
PMBS39 06
PMBS39 06
E
E
2
2
12
I
I
O2C10
O2C10
0.1UF/16V
0.1UF/16V
2
n
n
+5V +12V
12
I
I
O2R100
O2R100
22K
22K
1%
1%
12
I
I
O2R101
O2R101
10K
10K
1%
1%
GND
2
+5VSB_A TX
+3P3VSB
2
SLP_S3# [22]
1
ATX_PW RGD [45]
PWR GD_SIO_OUT [13, 22]
+3VSBSW [53]
LPC_PME# [22]
t
t
12
I
I
O2C1
O2C1
2200PF/ 50V
2200PF/ 50V
X7R 10%
X7R 10%
12
JP3
JP3
SHORTPIN
SHORTPIN
NOBOM
NOBOM
GND
12
I
I
O2C11
O2C11
0.1UF/16V
0.1UF/16V
PCIEX1_R ST# [24,34]
PCIE16_R ST# [25]
GNDGND GN D
Note:
1.PS_IN# and PS_OUT# must PU to +5VSB_ATX
2.Please check if another side already have a
pull-up resistor!
RSMRST # [22 ]
PWR BTN# [42]
SB_PW RBTN# [22]
PSON# [45]
SLP_S3# [22]
SLP_S4# [19,22 ,38]
a
a
i
i
PIN56
PIN59
PECI [8]
12
I
I
O2R102
O2R102
56K
56K
1%
1%
12
I
I
O2R103
O2R103
10K
10K
1%
1%
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Pin 22/23: LEDVSB/LEDVCC
Please check if another side already
have a pull-up resistor!
S0/S1
1
l
l
0
Only S3
high
PULL DOWN
FAN SPEED
：：：：
100%
Config 2E
Disable KBC
This short pin please near SIO
1 2
NOBOM
NOBOM
JP1
JP1
SHORTPIN
SHORTPIN
For AMD power sequence
VIN1 VIN2 VIN3 VIN4
internal pull-down 225K ohm
IPX41-D3
IPX41-D3
IPX41-D3
1
S4/S5
S3
PULL UP
(Internal Pull Up)
FAN SPEED
：：：：
(Default)
40%
Config 4E
Enable KBC
Note：Pin51 / Pin52
1.For Intel IBX platform,
connect to SM Link1
for Thermal application
2.Please make sure
another side already PU
TRD_CPU _P [8]
TRD_CPU _N [ 8]
SIO F71808EU
SIO F71808EU
SIO F71808EU
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
1
Rev
Rev
Rev
1.02
1.02
39 54Thursday, D ecember 10, 2009
39 54Thursday, D ecember 10, 2009
39 54Thursday, D ecember 10, 2009
1.02
Page 40
5
ADD FOR PS/2 WAKE ON IN S5
4
3
2
1
D D
+5V_DUA L_USB_R
12
Note:
The +5V_DUAL_US B_B power trace
width must have 40 mils or more
C C
B B
NI
NI
YR27
YR27
0
0
mx_r0805
mx_r0805
+5VSB
12
I
I
YR24
YR24
0
0
mx_r0805
mx_r0805
R_+5V_K BMS
I
I
YF2
YF2
1.1A/6V
1.1A/6V
1 2
+5V_KBMS
12
GND
I
I
YCB2
YCB2
0.1UF/16V
0.1UF/16V
GND
I
I
J68
J68
MINI_DIN_6PX 2
MINI_DIN_6PX 2
10
VCC2
9
GND2
13
SIDE_G13
14
SIDE_G14
4
VCC1
3
GND1
15
SIDE_G15
16
SIDE_G16
17
SIDE_G17
PS2_MOUSE
PS2_MOUSE
MDATA
MCLK
NC3
NC4
PS2_KB
PS2_KB
KDATA
KCLK
NC1
NC2
PS/2 KEYBOARD & MOUSE FOR CPC
7
11
8
12
1
5
2
6
n
n
C
C
CMSDAT A
CMSCLK
CKBDATA
CKBCLK
o
o
n
n
YL6 120O hm/100Mhz/0.6 A
YL6 120O hm/100Mhz/0.6 A
2 1
I
I
YL7 120O hm/100Mhz/0.6 A
YL7 120O hm/100Mhz/0.6 A
2 1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
f
f
d
d
i
i
YL8 120O hm/100Mhz/0.6 A
YL8 120O hm/100Mhz/0.6 A
2 1
YL9 120O hm/100Mhz/0.6 A
YL9 120O hm/100Mhz/0.6 A
2 1
YC5 150PF/5 0V NPO 5%
YC5 150PF/5 0V NPO 5%
1 2
YC6 150PF/5 0V NPO 5%
YC6 150PF/5 0V NPO 5%
1 2
YC7 150PF/5 0V NPO 5%
YC7 150PF/5 0V NPO 5%
1 2
YC8 150PF/5 0V NPO 5%
YC8 150PF/5 0V NPO 5%
1 2
e
e
n
n
MDAT
I
I
MCLK
I
I
KDAT
I
I
KCLK
I
I
GND
t
t
YRN3C
YRN3C
YRN3D
YRN3D
YRN3A
YRN3A
YRN3B
YRN3B
i
i
a
a
5 6
33
33
7 8
33
33
1 2
33
33
3 4
33
33
l
l
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
34
12
78
56
+5V_KBMS
MSDATA [39]
MSCLK [39]
KBDATA [39]
KBCLK [39]
YRN4B
YRN4B
I
I
YRN4A
YRN4A
I
I
YRN4D
YRN4D
I
I
YRN4C
YRN4C
I
I
o
o
r
r
t
t
a
a
g
g
e
e
P
P
A A
PEGATRON DT-MB RESTRICTED SECRET
KB & MS FOR CPC
KB & MS FOR CPC
KB & MS FOR CPC
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Engineer:
IPX41-D3
IPX41-D3
IPX41-D3
1
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
40 54Thursday, December 10, 2009
40 54Thursday, December 10, 2009
40 54Thursday, December 10, 2009
Rev
Rev
Rev
1.02
1.02
1.02
Page 41
5
D D
+12V_4P
C C
+12V_4P
B B
4
12
GND
12
GND
NI
NI
CB1
CB1
0.01UF/25 V
0.01UF/25 V
X7R 10%
X7R 10%
NI
NI
CB2
CB2
0.01UF/25 V
0.01UF/25 V
X7R 10%
X7R 10%
GND
GND
a
a
t
t
12
I
I
C37
C37
100PF/5 0V
100PF/5 0V
NPO 5%
NPO 5%
GND
12
I
I
C24
C24
100PF/5 0V
100PF/5 0V
r
r
NPO 5%
NPO 5%
GND
12
GND
12
o
o
GND
CPU FAN CON.
COLOR = White
W/POST
I
I
P70
P70
WAF ER_HD_4P
WAF ER_HD_4P
1
1
2
2
3
3
4
4
5
NC
CPUFAN_ PWM_C
CFAN_D
I
I
C22
C22
100PF/5 0V
100PF/5 0V
NPO 5%
NPO 5%
CHASSIS FAN CON.
COLOR = White
W/POST
I
I
P8
P8
WAF ER_HD_4P
WAF ER_HD_4P
1
1
2
2
3
3
4
4
5
NC
C
C
F_CHAFAN _PWM_C
F_SFAN _D
n
n
I
I
C26
C26
100PF/5 0V
100PF/5 0V
NPO 5%
NPO 5%
3
12
I
I
R14
R14
4.7K
4.7K
+3P3V
o
o
12
I
I
R20
R20
4.7K
4.7K
I
I
R3
R3
150
150
mx_r0805
mx_r0805
1 2
I
I
R4
R4
1.5K
1.5K
n
n
I
I
R7
R7
150
150
mx_r0805
mx_r0805
1 2
I
I
R8
R8
1.5K
1.5K
12
12
+5V
1
f
f
+5V
1
3
2
i
i
3
2
I
I
D1
D1
BAT54CW
BAT54CW
d
d
I
I
D3
D3
BAT54CW
BAT54CW
2
+5V+3P3V
12
I
I
R2
R2
1K
1K
e
e
+5V
12
I
I
R5
R5
1K
1K
n
n
t
t
i
i
a
a
l
l
1
CPUFAN_ PWM [39]
CPUFAN_ TACH [39]
F_FAN_PW M [39]
F_CHAFA N_TACH [39]
g
g
e
e
P
P
A A
PEGATRON DT-MB RESTRICTED SECRET
FAN CIRCUIT
FAN CIRCUIT
FAN CIRCUIT
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Pr oject Name
Size Pr oject Name
Size Pr oject Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Engineer:
IPX41-D3
IPX41-D3
IPX41-D3
1
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
41 54Thursday, D ecember 10, 2009
41 54Thursday, D ecember 10, 2009
41 54Thursday, D ecember 10, 2009
Rev
Rev
Rev
1.02
1.02
1.02
Page 42
5
4
3
2
1
NI
NI
NI
NI
NINI
NINI
R10
R10
0
0
mx_r0603
mx_r0603
+5V_DU AL
12
3
3
C
C
E
E
2
2
GND
+5V_DU AL
12
e
e
3
3
C
C
E
E
2
2
GNDGNDGND
IIII
IIII
R13
R13
220 Ohm
220 Ohm
mx_r0603
mx_r0603
NI
NI
Q1
Q1
PMBS39 04
PMBS39 04
B
1
B
1
SIO_LED1_ G
n
n
IIII
IIII
R6
R6
220 Ohm
220 Ohm
mx_r0603
mx_r0603
I
I
Q3
Q3
PMBS39 04
PMBS39 04
B
1
B
1
SIO_LED2_ G
t
t
a
a
i
i
R11
R11
1 2
4.7K
4.7K
I
I
NI
NI
R15
R15
1K
1K
l
l
R_SIO_LE D2_G
12
+3P3VSB
12
3
3
C
C
E
E
2
2
GND
I
I
R24
R24
1K
1K
I
I
Q4
Q4
PMBS39 04
PMBS39 04
B
B
1
1
+3P3VSB
12
NI
NI
R12
R12
1K
1K
R_R_SIO_ LED2_G
I
I
R23
R23
1K
1K
+3P3VSB
12
PLED_P [22]
12
NI
NI
R44
R44
1K
1K
PLED_N [22]
INTEL CONTROL PANEL / LED
D D
+3P3VSB +5V
C C
HD_LED#[33]
SYS_RESE T#[8,22 ,39]
B B
12
CIRCUITRY
I
I
R17
R17
4.7K
4.7K
12
12
IIII
IIII
R16
R16
220 Ohm
220 Ohm
mx_r0603
mx_r0603
HDLED+
R42 100 1%
R42 100 1%
I
I
1 2
I
I
C1
C1
0.1UF/16V
0.1UF/16V
FP_SYS_R ESET#
I
I
P5
P5
HEADER _2X5P_K10
HEADER _2X5P_K10
1
2
3 4
5 6
7 8
9
FP_LED+
FP_LEDFP_PW RBTN#
GND
PWRBTN# pull-high to +5VSB_ATX
R43 100 1%
R43 100 1%
I
I
1 2
12
C2
C2
1000PF/ 50V
1000PF/ 50V
X7R 10%
X7R 10%
n
n
PWR BTN# [39]
f
f
NI
NI
C3
C3
0.1UF/16V
0.1UF/16V
12
NI
NI
C4
C4
0.1UF/16V
0.1UF/16V
o
o
n
n
12
I
I
GND GNDGND GND
C
C
i
i
d
d
1 2
o
o
r
r
t
t
a
a
g
g
e
e
P
P
A A
5
4
3
SUPPORT
SINGLE
COLOR
DUAL
COLOR
2
R10FRONT POWER LED COLOR
Q2 R6 R11
I
NI NI NI
I I INI
PEGATRON DT-MB RESTRICTED SECRET
FRONT_PANEL
FRONT_PANEL
FRONT_PANEL
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Pr oject Name
Size Pr oject Name
Size Pr oject Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Engineer:
IPX41-D3
IPX41-D3
IPX41-D3
1
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
42 54Thursday, D ecember 10, 2009
42 54Thursday, D ecember 10, 2009
42 54Thursday, D ecember 10, 2009
1.02
1.02
1.02
Rev
Rev
Rev
Page 43
5
4
3
2
1
TPM
+3P3V
LR25
LR25
0
0
1 2
CK_33M_T PM
LFRAME#
LPC_RST #_TPM
LAD3
LAD0
I
I
2009.08.13 shawn
VC16 removed.
D D
+3P3VSB
CK_33M_T PM[6]
LFRAME#[22 ,39]
PLTRST#[13,22,39]
LAD3[22, 39]
LAD0[22, 39]
LPCPD#[22]
Debug Port
C C
LAD0[ 22,39]
LAD1[ 22,39]
LAD2[ 22,39]
LAD3[ 22,39]
LFRAME#[22 ,39]
CK_33M_D EBUG[ 6]
B B
SPI_CS#[22]
SPI_MISO[22]
FWH _WP#[22]
SPI_MOSI[22]
SPI_CLK[22]
+3P3VSB
I
I
P12
P12
HEADER _2X10P_K4
HEADER _2X10P_K4
2
1
3
6
5
7
9
11
13
15
17
19
NI
NI
FPC_CON _1X12P
FPC_CON _1X12P
1212SIDE1
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
SIDE2
DP1
DP1
GND GND
g
g
e
e
LAD2
8
LAD1
10
12
14
SERIRQ
16
18
20
GND
2009.09.28 shawn
Add debug port for BIOS RD debug.
13
14
a
a
LAD2 [22,39]
LAD1 [22,39]
SERIRQ [21,39]
CLKRUN# [22]
r
r
t
t
n
n
F3R8 47
F3R8 47
I
I
o
o
12
C
C
o
o
d
d
i
i
f
f
n
n
SPI BIOS ROM - 8Mbit
FU1
FU1
1
CS#
VCC
2
SO
HOLD#
3
WP#
SCLK
GND4SI
IC_SCK_8 P
IC_SCK_8 P
I
I
GND
ADD BIOS ROM
MFG_NE T[22]
e
e
8
7
6
5
n
n
Add MFG header 7/30
NOBOM
NOBOM
SP78
SP78
3
4
6
PEGATRO N_MFG
PEGATRO N_MFG
GND
a
a
i
i
t
t
+3P3VSB
SPI_HOLD #R_SPI_MISO
12
I
I
F3CB1
F3CB1
0.1UF/16V
0.1UF/16V
GND
GPI1
GPI2
GND
NP_NC1
NP_NC2
NP_NC3
l
l
+3P3VSB
1
2
5
12
I
I
F3R6
F3R6
8.2K
8.2K
I
I
BIOS_FU1
BIOS_FU1
1
8
1
8
2
7
2
7
BIOS
BIOS
3
6
3
6
4 5
4 5
MX25L80 05PC-15G
MX25L80 05PC-15G
P
P
A A
PEGATRON DT-MB RESTRICTED SECRET
SPI FLASH - 8M
SPI FLASH - 8M
SPI FLASH - 8M
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Pr oject Name
Size Pr oject Name
Size Pr oject Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Engineer:
IPX41-D3
IPX41-D3
IPX41-D3
1
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
43 54Thursday, D ecember 10, 2009
43 54Thursday, D ecember 10, 2009
43 54Thursday, D ecember 10, 2009
Rev
Rev
Rev
1.02
1.02
1.02
Page 44
5
4
3
2
1
External RTC Circuitry CLEAR CMOS
+3P3VSB
D D
BAT R303_D8
1 2
I
I
R33
R33
1K
XBT1
XBT1
BATT_HOLDE R
BATT_HOLDE R
I
I
1K
1%
1%
I
I
BATT1
BATT1
3V/220mA h
3V/220mA h
KTS
KTS
LITHIUM BATT
LITHIUM BATT
CR2032
CR2032
Battery Socket
C C
2
GND
13
1
2
BAT54CW
BAT54CW
I
I
D20
D20
+BATT
3
12
GND
NI
NI
C18
C18
1UF/10V
1UF/10V
mx_c0603
mx_c0603
I
I
CLRTC1
CLRTC1
1
2
3
HEADER _1X3P
HEADER _1X3P
GND
I
I
R34 24.9K 1%
R34 24.9K 1%
1 2
GND
12
I
I
C19
C19
1UF/10V
1UF/10V
mx_c0603
mx_c0603
RTCRST# [2 2]
SPEAKER
SB_PWR
+5VSB
NI
NI
R18
R18
300 OHM
300 OHM
5%
5%
SB_PWR
1 2
12
CR1
CR1
+
+
GREEN
GREEN
NI
NI
B B
NOBOM
NOBOM
H1
H1
SCREW HOLE_160_H P
SCREW HOLE_160_H P
1
GND1
2
GND2
3
GND3
4
GND4
GND8
GND7
GND6
GND5
9
NC
8
7
6
5
GND
NOBOM
NOBOM
H3
H3
SCREW HOLE_160_H P
SCREW HOLE_160_H P
1
GND1
2
GND2
GND8
3
GND3
GND7
4
GND4
GND6
GND5
g
g
9
NC
a
a
8
7
6
5
t
t
r
r
o
o
NOBOM
NOBOM
H4
H4
SCREW HOLE_160_H P
SCREW HOLE_160_H P
1
GND1
2
GND2
3
GND3
4
GND4
n
n
NC
GND8
GND7
GND6
GND5
9
8
7
6
5
I
I
CLRTC1:12
CLRTC1:12
MINI_JUMPER
MINI_JUMPER
CMOS RTC
1-2
Default
CLEAR2-3
I=5/(100+40)=35.7mA
I
o
o
R37
1KOhm
SPKR[22]
C
C
1KOhm
NOBOM
NOBOM
H2
H2
SCREW HOLE_160_H P
SCREW HOLE_160_H P
1
2
3
4
n
n
5%IR37
5%
SPKR_B
12
GND1
NC
GND2
GND8
GND3
GND7
GND4
GND6
GND5
f
f
PMBS39 04
PMBS39 04
9
8
7
6
5
i
i
I
I
Q9
Q9
B
1
B
1
+5V
I
I
d
d
R36
R36
1 2
100
100
mx_r0805
mx_r0805
SPKR_O
3
3
C
C
E
E
2
2
GND
e
e
BUZZ
P7
P7
1
2
AC_1205G
AC_1205G
I
I
12
NI
NI
CB99
CB99
0.1UF/16V
0.1UF/16V
GND
n
n
Max 40mA
40Ohm
t
t
i
i
a
a
l
l
e
GND GND GND GND GND
P
P
A A
5
e
4
AGND AGND
GND
ONLY FOR SCREW
HOLE
3
PEGATRON DT-MB RESTRICTED SECRET
Title :
Title :
Title :
RTC / CMOS / SPKR
RTC / CMOS / SPKR
RTC / CMOS / SPKR
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Pr oject Name
Size Pr oject Name
Size Pr oject Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Engineer:
IPX41-D3
IPX41-D3
IPX41-D3
1
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
44 54Thursday, D ecember 10, 2009
44 54Thursday, D ecember 10, 2009
44 54Thursday, D ecember 10, 2009
Rev
Rev
Rev
1.02
1.02
1.02
Page 45
5
NOTE:
ATX_PWRGD internal pull high in PSU
+5V
D D
ATX_PW RGD[39]
12
I
I
P1R2
P1R2
8.2K
8.2K
12
I
I
P1C1
P1C1
470PF/5 0V
470PF/5 0V
X7R 10%
X7R 10%
GND
GND
4
ATX POWER_24P SUPPLY CONNECTOR
I
I
P1
GNDG ND
P1
POW ER_CON_2X12 P
POW ER_CON_2X12 P
1
+3V1
2
+3V2
3
GND1
4
+5V1
5
GND2
6
+5V2
7
GND3
8
PWR0K
9
5VSB
10
+12V1
11
+12V2
12
+3V3
12
I
I
P1CB2
P1CB2
0.1UF/16V
0.1UF/16V
+5V
GND
+3P3V
12
12
I
I
P1CB4
P1CB4
0.1UF/16V
0.1UF/16V
I
I
P1CB5
P1CB5
0.1UF/16V
0.1UF/16V
All of the Caps Around the ATX Power Connector
+5VSB_A TX+12V
12
I
I
P1CB1
P1CB1
0.1UF/16V
0.1UF/16V
GND GNDGND
3
+5V +3P3V
25
13
+3V4
14
-12V
hold1
15
GND4
16
PSON#
17
GND5
18
GND6
19
GND7
20
-5V
21
+5V3
22
+5V4
23
+5V5
24
GND8
hold2
26
GND
12
I
I
P1CB6
P1CB6
0.1UF/16V
0.1UF/16V
2
12
I
I
P1CB8
P1CB8
0.1UF/16V
0.1UF/16V
n
n
12
GND
t
t
P1_PSON#
I
I
P1C2
P1C2
470PF/5 0V
470PF/5 0V
X7R 10%
X7R 10%
i
i
a
a
l
l
I
I
P1R3
P1R3
47
47
1
12
PSON# [39]
C C
i
i
f
f
n
n
o
o
C
C
B B
a
a
g
g
e
e
P
P
A A
VRM POWER_4P SUPPLY CONNECTOR
r
r
t
t
o
o
n
n
2
1
GND
I
I
P3
P3
4
2
4
3
1
3
5
NP_NC
POW ER_CON_2X2P
POW ER_CON_2X2P
2009.08.11 shawn
P1CB9 removed.
+12V_4P
12
GND
NI
NI
P1CB10
P1CB10
0.1UF/16V
0.1UF/16V
d
d
e
e
2009.08.04 shawn
→ Remove E70, E71 header and jumper
→ Add ATXL1 ~ 4 0805 short pin for keep the +12V trace width.
+12V_4P+12V
ATXL1 0
ATXL1 0
1 2
NOBOM
NOBOM
mx_r0805_shor t
mx_r0805_shor t
ATXL2 0
ATXL2 0
1 2
NOBOM
NOBOM
mx_r0805_shor t
mx_r0805_shor t
ATXL3 0
ATXL3 0
1 2
NOBOM
NOBOM
mx_r0805_shor t
mx_r0805_shor t
ATXL4 0
ATXL4 0
1 2
NOBOM
NOBOM
mx_r0805_shor t
mx_r0805_shor t
PEGATRON DT-MB RESTRICTED SECRET
ATX POWER
ATX POWER
ATX POWER
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Pr oject Name
Size Pr oject Name
Size Pr oject Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
IPX41-D3
IPX41-D3
IPX41-D3
Engineer:
Ttepic Zhu
Ttepic Zhu
Ttepic Zhu
45 54Thursday, D ecember 10, 2009
45 54Thursday, D ecember 10, 2009
45 54Thursday, D ecember 10, 2009
1
Rev
Rev
Rev
1.02
1.02
1.02
Page 46
5
D D
12
GND
0
12
0
RT_ADJ _A
+VTT_O UT_R
12
PR64
PR64
180K
180K
1%
1%
I
I
12
I
I
PR122
PR122
820
820
1%
1%
+VTT_O UT_R
12
I
I
PR15
PR15
1K
1K
CPU_PSI[8]
NI
NI
PR65
PR65
100K
100K
1%
1%
I
I
PR56
PR56
0
0
1 2
NI
NI
PC64
PC64
120PF/5 0V
120PF/5 0V
NPO 5%
NPO 5%
12
I
I
PR123
PR123
1 2
100 Ohm 1%
100 Ohm 1%
VRM_VC C5_A
P
P
12
I
I
PC72
PC72
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
12
GND
e
e
12
I
I
PC40
PC40
1UF/16V
1UF/16V
X7R 10%
X7R 10%
+VTT_O UT_R
12
I
I
PR117
PR117
1K
1K
12
NI
NI
PC66
PC66
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
C C
+VCORE
NOBOM
NOBOM
PJP17
PJP17
SHORTPIN
SHORTPIN
1 2
CPU : AN5
VCC_MB _SENSE[8]
VSS_MB_S ENSE[8]
CPU : AN6
GND
1 2
NOBOM
NOBOM
PJP18
PJP18
SHORTPIN
SHORTPIN
B B
A A
Vcore_PJ P11_A
Vcore_PJ P12_A
PR54 1KOhm 1%I PR 54 1KOhm 1%I
1 2
PC71 0. 1UF/16V X7R 10%
PC71 0. 1UF/16V X7R 10%
1 2
NI
NI
PR112 10K 3%
PR112 10K 3%
1 2
I
I
GND
I
I
PC31
PC31
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
1 2
GND
5
VRM_PW RGD[8,22]
PR126 15 OHM 1%
PR126 15 OHM 1%
I
I
1 2
PR118 0
PR118
I
I
1 2
I
I
PC33
PC33
0.01UF/25 V
0.01UF/25 V
X7R 10%
X7R 10%
PR108 0
PR108
I
I
1 2
PR102 15 OHM 1%
PR102 15 OHM 1%
I
I
1 2
I
I
PR120
PR120
6.8K
6.8K
1%
1%
1 2
12
I
I
PR114
PR114
180K
180K
1%
1%
GND GND GN D GND GND GN D GND
4
I
+12V_4P
12
GND
+VTT_O UT_R
NI
NI
PR14
PR14
0
0
1 2
PC74
PC74
1000PF/ 50V
1000PF/ 50V
I
I
X7R 10%
X7R 10%
12
820PF/5 0V
820PF/5 0V
PC26
PC26
I
I
X7R 10%
X7R 10%
12
I
I
NI
NI
PC67
PC67
120PF/5 0V
120PF/5 0V
NPO 5%
NPO 5%
12
I
I
PC61
PC61
680PF/5 0V
680PF/5 0V
X7R 10%
X7R 10%
a
a
GND GND
g
g
PR61 10K 1%
PR61 10K 1%
1 2
I
I
PR125 845KOHM 1 %I PR 125 845KOHM 1%I
1 2
VRM_VC C5_A
VRM_IMON FB_A
VRM_IMON_ A
4
I
PR121
PR121
4.7
4.7
mx_r0603
mx_r0603
1 2
NI
NI
PCB15
PCB15
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
RCVID[0..7][8]
+VTT_O UT_R
12
I
I
PR16
PR16
1K
1K
VID_SELEC T[8]
I
I
PR101
RC_COM P_A
I
I
PC29 5.6PF/50 V NPO 0.25PF
PC29 5.6PF/50 V NPO 0.25PF
RC_VOU T_A
I
I
1 2
X_VOUT_A
I
I
PR52 1.2K Ohm 1%
PR52 1.2K Ohm 1%
1 2
PC44 0. 1UF/16V X7R 10%
PC44 0. 1UF/16V X7R 10%
PC38 5600PF /25V X7R1 0%I PC 38 5600PF/25V X7R10%I
I
I
PC27 150PF/ 50V NPO 5%
PC27 150PF/ 50V NPO 5%
PR101
1 2
12
I
I
1 2
PR103 1. 3KOHM 1%
PR103 1. 3KOHM 1%
1 2
12
12
R_ADJ_ A
r
r
t
t
1 2
12
I
I
PC28
PC28
1000PF/ 50V
1000PF/ 50V
X7R 10%
X7R 10%
1 2
12
I
I
PCB16
PCB16
0.47UF/16 V
0.47UF/16 V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
GND G ND
12
I
I
PR110
PR110
1K
1K
24.9KOHM 1%
24.9KOHM 1%
PR13 0 Ohm 5%
PR13 0 Ohm 5%
n
n
o
o
I
I
PR55
PR55
1.8KOHM
1.8KOHM
1%
1%
PR124 169 OHM 1%
PR124 169 OHM 1%
I
I
VRM_IMAX _A
VRM_OF S_A
12
NI
NI
PR67
PR67
240K
240K
1%
1%
3
IIII
IIII
PU207
PU207
PU207
PU207
PU207PU207
PU207PU207
VRM_VC C_C
RCVID0
RCVID1
RCVID2
RCVID3
RCVID4
RCVID5
RCVID6
RCVID7
R_VRM_P SI#
VRM_EN
VRM_FB_A
VRM_COM P_A
VRM_VO UT_A
VRM_QR 2_A
VRM_FBR TN_A
VRM_SS_A
VRM_QR 1_A
VRM_AD J_A
12
VRM_IMAXP SI_A VRM_RT
12
PR53
PR53
150 Ohm
150 Ohm
1%
1%
1 2
I
I
31
49
45
44
43
42
41
40
39
38
46
47
37
36
48
C
C
I
I
PC62
PC62
100PF/5 0V
100PF/5 0V
NPO 5%
NPO 5%
11
10
24
12
13
I
I
PC59
PC59
1000PF/ 50V
1000PF/ 50V
X7R 10%
X7R 10%
3
VCC12
GND
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
VIDSEL
PSI#
EN/VTT
PWRGD
6
FB
5
COMP
VOUT
3
o
o
QR2
1
FBRTN
4
SS/EN
2
QR1
9
ADJ
IMAXPSI
IMAX
7
OFS
VCC5
IMONFB
IMON
RT8857GQ W
RT8857GQ W
BOOT1
UGATE1
PHASE1
LGATE1
ISP1
ISN1
BOOT2
UGATE2
PHASE2
LGATE2
ISP2
ISN2
PWM3
ISP3
n
n
ISN3
PWM4
ISP4
ISN4
VRHOT
TSEN
RT
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
35
34
33
32
21
20
27
28
29
30
18
19
26
17
f
f
16
25
14
15
22
23
8
50
51
52
53
54
55
56
57
GND
R_ISEN1+ _A
R_ISEN1-_A
R_ISEN2+ _A
R_ISEN2-_A
i
i
R_ISEN3+ _A
R_ISEN3-_A
VRM_TSE N
2
I
I
PR17 820 OHM 1%
PR17 820 OHM 1%
1 2
PR12 1K Ohm 1%I PR12 1KO hm 1%I
1 2
e
e
d
d
I
I
PR106 1. 2KOhm 1%
PR106 1. 2KOhm 1%
1 2
PR111
PR111
VRM_IS4
1 2
0
0
NOBOM
NOBOM
mx_r0603_shor t
mx_r0603_shor t
GND
2
n
n
VRM_VC C5_A
VRM_VR HOT [48]
12
I
I
PR63
PR63
33K
33K
1%
1%
12
I
I
PR116
PR116
5.6K
5.6K
1%
1%
1UF/16V
1UF/16V
PC32
PC35
PC70
X7R 10%I mx_c0603PC 32
X7R 10%I mx_c0603
12
l
l
12
I
I
PR66
PR66
5.6K
5.6K
1%
1%
1UF/16V
1UF/16V
X7R 10%I mx_c0603PC 35
X7R 10%I mx_c0603
12
12
I
I
PR62
PR62
5.6K
5.6K
1%
1%
1UF/16V
1UF/16V
X7R 10%I mx_c0603PC 70
X7R 10%I mx_c0603
12
PR107 1.8K 1%
PR107 1.8K 1%
1 2
NI
NI
PC73 0.1UF /16V X7R 10%
PC73 0.1UF /16V X7R 10%
I
I
PR104 10K 3%
PR104 10K 3%
1 2
I
I
I
I
PR109
PR109
1.8K
1.8K
1%
1%
1 2
t
t
12
i
i
12
12
I
I
PC6
PC6
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
a
a
I
I
PC39
PC39
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
I
I
PC30
PC30
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
Place PR101 near PQ23
PEGATRON DT-MB RESTRICTED SECRET
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
IPX41-D3
IPX41-D3
IPX41-D3
1
12
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
1
VRM_BO OT1_C [ 47]
VRM_UG ATE1_C [47]
VRM_PH ASE1_C [47]
VRM_LGA TE1_C [47]
ISEN1+_A [47]
ISEN1-_A [47]
GND
VRM_BO OT2_C [ 47]
VRM_UG ATE2_C [47]
VRM_PH ASE2_C [47]
VRM_LGA TE2_C [47]
ISEN2+_A [47]
ISEN2-_A [47]
GND
VRM_PW M3_A [48]
ISEN3+_A [48]
ISEN3-_A [48]
GND
VRM_VC C5_A
GND
VCORE CONTROLLER
VCORE CONTROLLER
VCORE CONTROLLER
Ttepic_Zhu
Ttepic_Zhu
Ttepic_Zhu
46 54Thursday, D ecember 10, 2009
46 54Thursday, D ecember 10, 2009
46 54Thursday, D ecember 10, 2009
Rev
Rev
Rev
1.02
1.02
1.02
Page 47
5
4
3
2
1
+12V_4P
I
I
PL79
PL79
0.4UH/25 A
0.4UH/25 A
21
D D
I
I
PC77
1 2
1 2
g
g
PC77
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
I
I
PC81
PC81
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
a
a
t
t
1 2
1 2
r
r
VP
VP
PR139
PR139
0
0
mx_r0603
mx_r0603
VP
VP
PR144
PR144
0
0
mx_r0603
mx_r0603
o
o
VRM_UG R1_C
12
I
I
PR140
PR140
8.2K
8.2K
VRM_UG R2_C
12
I
I
PR145
PR145
n
n
8.2K
8.2K
C
C
2
2
1
1
G
G
3
3
2
2
1
1
G
G
3
3
GND
o
o
2
2
1
1
G
G
3
3
2
2
1
1
G
G
3
3
GND
I
I
D
D
PQ30
PQ30
AOD452
AOD452
S
S
D
D
I
I
PQ31
PQ31
AOD472
AOD472
S
S
n
n
I
I
D
D
PQ33
PQ33
AOD452
AOD452
S
S
D
D
I
I
PQ32
PQ32
AOD472
AOD472
S
S
I
I
PD9
PD9
BAT54CW
BAT54CW
1
3
2
VRM_BO OT1_C[4 6]
VRM_UG ATE1_C[46]
VRM_PH ASE1_C[46]
1
2
VRM_BO OT2_C[4 6]
VRM_UG ATE2_C[46]
VRM_PH ASE2_C[46]
VRM_LGA TE2_C[46]
VRM_LGA TE1_C[46]
I
I
PD10
PD10
BAT54CW
BAT54CW
3
C C
B B
A A
I
I
PR138
PR138
1
1
mx_r0603
mx_r0603
1 2
I
I
PR143
PR143
1
1
mx_r0603
mx_r0603
1 2
P
P
VRM_BO OT1_RC_C
VRM_BO OT2_RC_C
e
e
12
GND
12
12
i
i
f
f
GND
+12V_VCO RE_VIN
12
GND
12
12
GND
I
I
PCB43
PCB43
4.7UF/16V
4.7UF/16V
X7R 20%
X7R 20%
mx_c1206
mx_c1206
I
I
PC79
PC79
4700PF/ 50V
4700PF/ 50V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
I
I
PR142
PR142
1 Ohm
1 Ohm
5%
5%
d
d
mx_r1206
mx_r1206
I
I
PCB44
PCB44
4.7UF/16V
4.7UF/16V
X7R 20%
X7R 20%
mx_c1206
mx_c1206
I
I
PC82
PC82
4700PF/ 50V
4700PF/ 50V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
I
I
PR147
PR147
1 Ohm
1 Ohm
5%
5%
mx_r1206
mx_r1206
12
+
+
GND GND GND
VRM_SN 1_C
e
e
VRM_SN 2_C
PCE208
PCE208
270UF/1 6V
270UF/1 6V
NI
NI
n
n
GND
GND
12
I
I
PC80
PC80
680PF/5 0V
680PF/5 0V
X7R 10%
X7R 10%
ISEN1+_A[46]
ISEN1-_A[46]
12
I
I
PC84
PC84
680PF/5 0V
680PF/5 0V
X7R 10%
X7R 10%
ISEN2+_A[46]
ISEN2-_A[46]
12
+
+
PCE203
PCE203
270UF/1 6V
270UF/1 6V
I
I
mx_c0603
mx_c0603
mx_c0603
mx_c0603
t
t
12
+
+
i
i
PCE210
PCE210
270UF/1 6V
270UF/1 6V
I
I
a
a
1 2
1 2
+12V_VCO RE_VIN
l
l
I
I
PL80
PL80
0.3UH/48 A
0.3UH/48 A
NOBOM
NOBOM
PJP20
PJP20
SHORTPIN
SHORTPIN
I
I
PL81
PL81
0.3UH/48 A
0.3UH/48 A
NOBOM
NOBOM
PJP22
PJP22
SHORTPIN
SHORTPIN
+VCORE
21
NOBOM
NOBOM
PJP21
PJP21
SHORTPIN
SHORTPIN
1 2
21
NOBOM
NOBOM
PJP23
PJP23
SHORTPIN
SHORTPIN
1 2
PEGATRON DT-MB RESTRICTED SECRET
VCORE DRIVER-1
VCORE DRIVER-1
VCORE DRIVER-1
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
IPX41-D3
IPX41-D3
IPX41-D3
Engineer:
Ttepic_Zhu
Ttepic_Zhu
Ttepic_Zhu
47 54Thursday, D ecember 10, 2009
47 54Thursday, D ecember 10, 2009
1
47 54Thursday, D ecember 10, 2009
Rev
Rev
Rev
1.02
1.02
1.02
Page 48
5
4
3
2
1
+12V_4P
I
I
PD11
PD11
BAT54CW
BAT54CW
1
3
D D
C C
+VCORE
12
I
I
+
+
PCE48
PCE48
820UF/2.5 V
820UF/2.5 V
GND
B B
+VCORE
2
I
I
PR151
PR151
4.7
4.7
VRM_PW M3_A[46]
mx_r0603
mx_r0603
1 2
VRM_VC C5_A
PR105
PR105
1 2
0
0
NOBOM
NOBOM
mx_r0603_shor t
mx_r0603_shor t
2009.08.19 shawn
PC63, PC68 from 4.7uF change to 2.2uF.
12
I
I
PC63
PC63
2.2UF/6.3 V
2.2UF/6.3 V
X5R 10%
X5R 10%
mx_c0603
mx_c0603
12
I
I
PC68
PC68
2.2UF/6.3 V
2.2UF/6.3 V
X5R 10%
X5R 10%
mx_c0603
mx_c0603
12
I
I
PC75
PC75
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
I
I
PR148
PR148
1
1
mx_r0603
mx_r0603
1 2
VRM_BO OT3_C
PU9_OD#
DRI_VCC3_ B
12
GND
12
I
I
PC76
PC76
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
+VCORE
VRM_BO OT3_RC_C
I
I
PC87
PC87
0.47UF/16 V
0.47UF/16 V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
+VCORE
1
2
3
12
I
I
PC78
PC78
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
BOOT
PWM
OD#
VCC4LGATE
IIII
IIII
PU9
PU9
PU9
PU9
PU9PU9
PU9PU9
UGATE
RT9618P S
RT9618P S
+VCORE
1 2
PHASE
PGND
12
a
a
I
I
PC85
PC85
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
8
7
6
5
I
I
PC83
PC83
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
+VCORE
GND
t
t
VRM_UG3_C
r
r
VP
VP
PR149
PR149
0
0
mx_r0603
mx_r0603
1 2
VRM_PH ASE3_C
VRM_LG3 _C
o
o
VRM_UG R3_C
12
I
I
PR150
PR150
8.2K
8.2K
VRM_VR HOT[46]
HFORCE PH#[8]
PROCHO T#[8]
n
n
C
C
PR146
PR146
I
I
o
o
130Ohm
130Ohm
r0603_h2 4
r0603_h2 4
1%
1%
12
PMBS39 04
PMBS39 04
2
2
D
D
1
1
G
G
S
S
3
3
2
2
D
D
1
1
G
G
S
S
3
3
GND
n
n
PQ100
PQ100
B
1
B
1
I
I
+12V_VCO RE_VIN
I
I
PQ35
PQ35
AOD452
AOD452
2009.08.04 shawn
PQ35 from FDU8780_F071 (DIP) change to AOD452 (SMD) to avoid thermal issue.
I
I
PQ34
PQ34
AOD472
AOD472
3
3
C
C
E
E
2
2
GND
f
f
3
3
PQ117
PQ117
C
C
E
E
2
2
GND
GND
+3P3V
12
i
i
PMBS39 04
PMBS39 04
B
1
B
1
VRM_VR HOT2VRM_VR HOT1
I
I
12
I
I
PCB45
PCB45
4.7UF/16V
4.7UF/16V
X7R 20%
X7R 20%
mx_c1206
mx_c1206
12
I
I
PC86
PC86
4700PF/ 50V
4700PF/ 50V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
VRM_SN 3_C
12
I
I
PR152
PR152
1 Ohm
1 Ohm
5%
5%
mx_r1206
mx_r1206
d
d
I
I
PR135
PR135
1K
1K
PR153
PR153
130Ohm
130Ohm
r0603_h2 4
r0603_h2 4
1%
1%
I
I
e
e
12
12
I
I
PC88
PC88
680PF/5 0V
680PF/5 0V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
GND
n
n
ISEN3+_A[46]
ISEN3-_A[46]
t
t
i
i
a
a
l
l
1 2
I
I
PL82
PL82
0.3UH/48 A
0.3UH/48 A
NOBOM
NOBOM
PJP24
PJP24
SHORTPIN
SHORTPIN
+VCORE
21
NOBOM
NOBOM
PJP25
PJP25
SHORTPIN
SHORTPIN
1 2
12
I
I
I
I
+
+
+
+
PCE41
PCE41
PCE40
PCE40
820UF/2.5 V
820UF/2.5 V
820UF/2.5 V
820UF/2.5 V
A A
GND
I
I
+
+
PCE42
PCE42
820UF/2.5 V
820UF/2.5 V
5
I
I
+
+
PCE43
PCE43
820UF/2.5 V
820UF/2.5 V
12
NI
NI
+
+
PCE47
PCE47
820UF/2.5 V
820UF/2.5 V
2009.08.04 shawn
Remove PCE44, reference IPX41 design.
12
12
12
12
+
+
NI
NI
PCE39
PCE39
220UF/2V
220UF/2V
BOTTOM
BOTTOM
P
P
GND
12
+
+
NI
NI
PCE45
PCE45
220UF/2V
220UF/2V
e
e
BOTTOM
BOTTOM
GND
12
g
g
+
+
NI
NI
PCE46
PCE46
220UF/2V
220UF/2V
BOTTOM
BOTTOM
GND
4
GND
12
I
I
PCB46
PCB46
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c1206
mx_c1206
12
12
12
I
I
PCB47
PCB47
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c1206
mx_c1206
I
I
PCB48
PCB48
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c1206
mx_c1206
NI
NI
PCB49
PCB49
22UF/6.3V
22UF/6.3V
X5R 10%
X5R 10%
mx_c1206
mx_c1206
12
I
I
PCB50
PCB50
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c1206
mx_c1206
+CPU VCORE OUTPUT CAPs
11X23A106150
12
12
12
I
I
PCB51
PCB51
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c1206
mx_c1206
3
NI
NI
PCB52
PCB52
22UF/6.3V
22UF/6.3V
X5R 10%
X5R 10%
mx_c1206
mx_c1206
NI
NI
PCB53
PCB53
22UF/6.3V
22UF/6.3V
X5R 10%
X5R 10%
mx_c1206
mx_c1206
12
NI
NI
PCB54
PCB54
22UF/6.3V
22UF/6.3V
X5R 10%
X5R 10%
mx_c1206
mx_c1206
12
NI
NI
PCB55
PCB55
22UF/6.3V
22UF/6.3V
X5R 10%
X5R 10%
mx_c1206
mx_c1206
12
2
I
I
PCB56
PCB56
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c1206
mx_c1206
12
I
I
PCB57
PCB57
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c1206
mx_c1206
12
12
NI
NI
PCB58
PCB58
22UF/6.3V
22UF/6.3V
X5R 10%
X5R 10%
mx_c1206
mx_c1206
PEGATRON DT-MB RESTRICTED SECRET
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
I
I
PCB59
PCB59
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c1206
mx_c1206
12
NI
NI
PCB60
PCB60
22UF/6.3V
22UF/6.3V
X5R 10%
X5R 10%
mx_c1206
mx_c1206
IPX41-D3
IPX41-D3
IPX41-D3
Engineer:
Engineer:
Engineer:
12
NI
NI
PCB61
PCB61
22UF/6.3V
22UF/6.3V
X5R 10%
X5R 10%
mx_c1206
mx_c1206
Title :
Title :
Title :
1
12
12
NI
NI
PCB62
PCB62
22UF/6.3V
22UF/6.3V
X5R 10%
X5R 10%
mx_c1206
mx_c1206
VCORE DRIVER-2
VCORE DRIVER-2
VCORE DRIVER-2
Ttepic_Zhu
Ttepic_Zhu
Ttepic_Zhu
48 54Thursday, D ecember 10, 2009
48 54Thursday, D ecember 10, 2009
48 54Thursday, D ecember 10, 2009
NI
NI
PCB63
PCB63
22UF/6.3V
22UF/6.3V
X5R 10%
X5R 10%
mx_c1206
mx_c1206
Rev
Rev
Rev
1.02
1.02
1.02
Page 49
5
+3P3V ==> +1P1V_CORE (10A)
D D
C C
+12V
12
I
I
PR95
I
I
PD8
PD8
BAT54CW
BAT54CW
1
3
1 2
I
I
PU8
PU8
APW 7120
APW 7120
BOOT
UGATE
GND
LGATE
I
I
PC56
PC56
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
PHASE
OCSET
2
VCC
B B
1P1V_BS T_C
1P1V_HG _D
1P1V_LG _D
A A
GND GND
1
2
3
4
5
FB
1P1V_PH ASE_C
8
1P1V_OC SET_A
7
1P1V_FB _C
6
1P1V_VC C_C
5
1P1V_VC C_C
P
P
PR95
4.7
4.7
mx_r0603
mx_r0603
12
I
I
PC57
PC57
e
e
0.47UF/16 V
0.47UF/16 V
mx_c0603
mx_c0603
X7R 10%
X7R 10%
GND
4
1P1V_HG _D
Please this shortpin close to
low-side MOSFET drain pin
1P1V_OC SET_R
12
I
I
PR98
PR98
17.4KOHM
17.4KOHM
1%
1%
OCP Point: 49.8A
t
t
a
a
g
g
4
12
I
I
PR100
PR100
1.96K
1.96K
1%
1%
+3P3V
12
I
I
PCB39
PCB39
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
r
r
1 2
NOBOM
NOBOM
PR93
PR93
0
0
mx_r0603_shor t
mx_r0603_shor t
1 2
o
o
I
I
PL7
PL7
1UH/22A 0.2
1UH/22A 0.2
1P1V_HGR _D
12
NOBOM
NOBOM
PJP9
PJP9
SHORTPIN
SHORTPIN
12
I
I
PR96
PR96
8.2K
8.2K
GND
n
n
I
I
PR99
PR99
750 OHM
750 OHM
1%
1%
12
12
NI
NI
PC58
PC58
0.47UF/16 V
0.47UF/16 V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
21
I
I
PR94
PR94
8.2K
8.2K
C
C
3
2009.08.04 shawn
Remove input voltage +12V option.
+3P3V_VIN
2
2
D
D
I
I
PQ25
PQ25
1
1
AOD452
AOD452
G
G
S
S
3
3
2
2
D
D
1
1
G
G
S
S
3
3
GND GND
+3P3V
3
2009.08.04 shawn
PQ25 from FDU8780_F071 (DIP) change to AOD452 (SMD)
2009.08.04 shawn
PQ27 from IPS06N03LAG (DIP) removed
I
I
PQ26
PQ26
AOD452
AOD452
2009.08.04 shawn
PQ26 from IPS06N03LAG (DIP) change to AOD452 (SMD)
o
o
I
I
PR158
PR158
1K
1K
1 2
GND
12
n
n
12
PR157
PR157
619 OHM
619 OHM
I
I
1 2
1%
1%
I
I
PC53
PC53
4700PF/ 50V
4700PF/ 50V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
f
f
+1P1V_S N_C
I
I
PR97
PR97
1
1
mx_r1206
mx_r1206
12
I
I
PCB70
PCB70
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
12
I
I
PC52
PC52
X5R 10%
X5R 10%
10UF/6.3V
10UF/6.3V
mx_c0805
mx_c0805
GND GND
d
d
i
i
+5VSB
12
I
I
PR130
PR130
1K
1K
3
3
C
C
I
I
B
1
B
1
PQ41
PQ41
PMBS39 04
PMBS39 04
E
E
2
2
2
12
I
I
+
+
PCE25
PCE25
560UF/6.3 V
560UF/6.3 V
2009.08.11 shawn
PCE25 from EL CAP 1800u/6.3V change to PL CAP 560u/6.3V for layout space issue.
l
l
a
a
i
i
t
t
n
n
I
I
PL8
PL8
1.2UH/29 A
1.2UH/29 A
e
e
12
NI
NI
PC54
PC54
680PF/5 0V
680PF/5 0V
X7R 10%
X7R 10%
GND GNDGND
1P1V_FB 1_C
B
1
B
1
12
NI
NI
PCB71
PCB71
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GNDGND
GND
1P1V_OC SET_A
3
3
C
C
I
I
PQ40
PQ40
PMBS39 04
PMBS39 04
E
E
2
2
2
21
12
12
+
+
+
+
PCE27
PCE27
1500UF/6 .3V
1500UF/6 .3V
I
I
GND
modify 8/1
PEGATRON DT-MB RESTRICTED SECRET
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
PCE28
PCE28
1500UF/6 .3V
1500UF/6 .3V
I
I
12
I
I
PC55
PC55
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
IPX41-D3
IPX41-D3
IPX41-D3
+1.1V
1
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
1
+1P1V_C ORE
1 2
+1P1V_CORE
+1P1V_CORE
+1P1V_CORE
Ttepic_Zhu
Ttepic_Zhu
Ttepic_Zhu
49 54Thursday, D ecember 10, 2009
49 54Thursday, D ecember 10, 2009
49 54Thursday, D ecember 10, 2009
PJP10
PJP10
SHORTPIN
SHORTPIN
NOBOM
NOBOM
Rev
Rev
Rev
1.02
1.02
1.02
Page 50
5
4
3
2
1
+1P5V_DUAL ==> +1P1V_FSB_VTT (1.5A)
D D
+3P3VSB
12
I
I
PR68
PR68
17.4K
t
t
17.4K
1%
1%
12
I
I
PR73
PR73
10K
10K
1%
1%
1
1
r
r
12
GNDGND
3
3
D
D
I
I
PQ22
PQ22
2N7002
2N7002
G
G
S
S
2
2
GND
o
o
I
I
PCB36
PCB36
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
n
n
+1P1V_FS B_VTT_REF_A
C
C
NI
+3P3VSB
GND
1
1
12
I
I
PR82
PR82
1K
1K
3
3
C
C
I
I
PQ28
PQ28
PMBS39 04
PMBS39 04
E
E
2
2
3
3
G
G
2
2
GND
+1P1V_E N_A
D
D
NI
NI
PQ13
PQ13
2N7002
2N7002
S
S
+1P1V_FS B_VTT
12
I
I
PR72
PR72
62
62
NI
NI
PR75
PR75
1K
1K
+1P1V_C ORE
R_VTT_S EL
I
I
PR154
PR154
1K
1K
1 2
VTT_SE LECT[8]
C C
H--->1.206
L--->1.101
B B
1 2
12
NI
NI
PR70
PR70
1K
1K
VTT_SE LECT#
3
3
C
C
NI
NI
B
1
B
1
PQ14
PQ14
PMBS39 04
PMBS39 04
E
E
2
2
GND
+3P3VSB
B
1
B
1
12
I
I
PCB42
PCB42
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
NI
PR71
PR71
68.1K
68.1K
1%
1%
1 2
12
NI
NI
PCB64
PCB64
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
I
I
PU6
PU6
LM358
LM358
A+
A+
3
A-
A-
2
B+
B+
5
B-
B-
6
+1P1V_FS B_VTT_FB_A
o
o
8
VCC
VCC
+
+
1
AO
AO
-
-
+
+
BO
BO
7
4
-
-
GND
GND
n
n
+12V_4P
+1P1V_FS B_VTT_CON_A
12
I
I
PC41
PC41
470PF/5 0V
470PF/5 0V
X7R 10%
X7R 10%
GND
d
d
i
i
f
f
12
I
I
PCB37
PCB37
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
1 2
1 2
e
e
+1P5V_D UAL
2009.08.04 shawn
PQ25 from FDU8780_F071 (DIP) change to AOD452 (SMD)
2
2
D
D
l
l
I
I
PQ12
PQ12
1
1
FDU878 0_F071
PR74
PR74
10K
10K
1%
1%
PC96
PC96
I
I
2200PF/ 50V
2200PF/ 50V
X7R 10%
X7R 10%
I
I
I
I
t
t
PR76
PR76
1K
1K
1%
1%
n
n
2009.08.04 shawn
PCE17 from EL CAP 1800u/6.3V change to PL CAP 820u/2.5V for layout space issue.
2009.08.11 shawn
PCE17 from EL CAP 1800u/6.3V change to PL CAP 560u/6.3V for layout space issue.
a
a
i
i
PJP19
PJP19
+1P1V_FS B_VTT_PJP_A
12
1 2
SHORTPIN
SHORTPIN
NOBOM
NOBOM
G
G
3
3
FDU878 0_F071
S
S
+1P1V_FS B_VTT
GND
12
I
I
+
+
PCE17
PCE17
560UF/6.3 V
560UF/6.3 V
2009.08.04 shawn
PD5 removed.
a
a
g
g
e
e
P
P
A A
PEGATRON DT-MB RESTRICTED SECRET
+1P1V_FSB_VTT_LDO
+1P1V_FSB_VTT_LDO
+1P1V_FSB_VTT_LDO
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
IPX41-D3
IPX41-D3
IPX41-D3
Engineer:
Ttepic_Zhu
Ttepic_Zhu
Ttepic_Zhu
50 54Thursday, D ecember 10, 2009
50 54Thursday, D ecember 10, 2009
1
50 54Thursday, D ecember 10, 2009
Rev
Rev
Rev
1.02
1.02
1.02
Page 51
5
+1P5V_DUAL ==> +1P5V_ICH (2A)
4
3
2
1
+1P5V_ICH (2A) For G41 DDR3 Platform
+1P5V_D UAL+12 V
D D
567
G
G
4
GND
8
SD
SD
123
12
I
I
PC903
PC903
10UF/6.3V
10UF/6.3V
mx_c0805
mx_c0805
X5R 10%
X5R 10%
I
I
PQ29
PQ29
IRF8707PBF
IRF8707PBF
I
I
PR907
PR907
8.2KOHM
8.2KOHM
+1P5V_ICH_GATE_A
1 2
12
NI
NI
PCB901
PCB901
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
C C
B B
2009.12.10 shawn
PQ29 change to 07X50S211059
PCE714 removed
GND GND
2009.08.04 shawn
Reference IPM41-GS solution. For G41 DDR3 platform.
+1P5V_ICH
12
I
I
PC902
PC902
10UF/6.3V
10UF/6.3V
mx_c0805
mx_c0805
X5R 10%
X5R 10%
I
I
PD902
PD902
BAT54CW
BAT54CW
3
e
e
2
1
g
g
a
a
+1P1V_FS B_VTT
r
r
t
t
o
o
n
n
+5VSB ==> +3P3VSB (1.5A)
+5VSB
C
C
12
I
I
PCB30
PCB30
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
2009.08.04 shawn
→ Removed switch regulator solution.
→ Add Linear regulator solution.
+1P5V_D UAL
o
o
I
I
PQ10
PQ10
LIN REG, 1085
LIN REG, 1085
3
VIN
+1P5V_DUAL ==> +0P75V_VTT_DDR (2A)
PR57
PR57
100KOHM
100KOHM
1%
1%
I
I
+0P75V_ REF_A
PR58
PR58
100KOHM
100KOHM
1%
1%
I
I
n
n
1
12
GND
VOUT
ADJ
3P3VSB_A DJ
NI
NI
PC47
PC47
0.1UF/16V
0.1UF/16V
+5V
9
GND2
8
NC3
7
NC2
6
VCNTL
5
NC1
12
12
I
IIII
IIII
PC37
PC37
1000PF/ 50V
1000PF/ 50V
X7R 10%
X7R 10%
f
f
2
I
PCB28
PCB28
1UF/16V
1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
GNDGNDGND GNDGN D
d
d
i
i
12
I
I
PR81
PR81
120
120
1%
1%
PCE16
PCE16
820UF/6.3 V
820UF/6.3 V
12
I
I
PR85
PR85
200
200
1%
1%
GND
e
e
12
+
+
I
I
GND
n
n
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
I
I
RT9045G SP
RT9045G SP
+3P3VSB
I
I
PCB31
PCB31
PU4
PU4
GND1
REFEN
VOUT
GND
VIN
t
t
12
1
2
3
4
i
i
12
a
a
I
I
PCB29
PCB29
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
l
l
+1P5V_D UAL
2009.08.04 shawn
PC99 removed.
GND
12
NI
NI
PC100
PC100
10UF/6.3V
10UF/6.3V
GND GND
+0P75V_V TT_DDR
I
I
12
PC98
PC98
10UF/6.3V
10UF/6.3V
I
I
12
PC97
PC97
10UF/6.3V
10UF/6.3V
P
P
A A
PEGATRON DT-MB RESTRICTED SECRET
+0P9V_VTT_DDR_LDO
+0P9V_VTT_DDR_LDO
+0P9V_VTT_DDR_LDO
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
IPX41-D3
IPX41-D3
IPX41-D3
Engineer:
Ttepic_Zhu
Ttepic_Zhu
Ttepic_Zhu
51 54Thursday, D ecember 10, 2009
51 54Thursday, D ecember 10, 2009
1
51 54Thursday, D ecember 10, 2009
Rev
Rev
Rev
1.02
1.02
1.02
Page 52
5
4
3
2
1
+5V_DU AL
D D
+5V_DUAL
C C
B B
1P5V_DU AL_BST_C
1P5V_DU AL_HG_D
1P5V_DU AL_LG_D
GND GND GND
1
2
3
4
+12V_4P
I
I
PD7
PD7
BAT54CW
BAT54CW
3
I
I
PC49
PC49
0.1UF/16V
0.1UF/16V
mx_c0603
mx_c0603
X7R 10%
X7R 10%
1 2
I
I
PU7
PU7
APW 7120
APW 7120
BOOT
UGATE
GND
LGATE
PHASE
OCSET
VCC
I
I
PD6
PD6
BAT54CW
BAT54CW
2
1
1
2
8
7
6
FB
5
1P5V_DU AL_PWM_C
3
1P5V_DU AL_PHASE_C
1P5V_DU AL_OCSET_A
1P5V_DU AL_FB_A
1P5V_DU AL_VCC_C
12
I
I
PR87
PR87
4.7
4.7
mx_r0603
mx_r0603
12
I
I
PC50
PC50
0.47UF/16 V
0.47UF/16 V
mx_c0603
mx_c0603
X7R 10%
X7R 10%
e
e
g
g
12
NI
NI
PCB38
PCB38
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND GND GN D
a
a
I
I
PL5
PL5
1UH/14A
1UH/14A
VP
VP
PR28
PR28
0 Ohm
0 Ohm
mx_r0603
mx_r0603
1 2
1P5V_DUA L_OCSET1_A
OCP=23~25A
I
I
PR90
PR90
17.4KOHM
17.4KOHM
1%
1%
2009/10/29
1 2
PR90 from 13Kohm change to 17.4Kohm for OCP fine tune.
o
o
r
r
t
t
12
21
n
n
PR92
PR92
2.1KOHM
2.1KOHM
1%
1%
I
I
+1P5V_DU AL_VIN
1P5V_DU AL_HGR_D
12
I
I
PR86
PR86
8.2K
8.2K
NOBOM
NOBOM
PJP27
PJP27
SHORTPIN
SHORTPIN
12
NI
NI
PR113
PR113
8.2K
8.2K
1
1
12
1
1
C
C
PR91
PR91
2KOhm
2KOhm
1%
1%
I
I
1 2
NI
NI
PC51
PC51
0.47UF/16 V
0.47UF/16 V
mx_c0603
mx_c0603
X7R 10%
X7R 10%
12
Irms=5.86A
12
I
I
PC45
PC45
10UF/6.3V
10UF/6.3V
mx_c0805
mx_c0805
X5R 10%
X5R 10%
2
2
D
D
I
I
PQ23
PQ23
FDU878 0_F071
FDU878 0_F071
G
G
S
S
3
3
2009.08.04 shawn
PQ23, PQ24 from AOD452 (SMD) change to FDU8780_F071 (DIP)
12
I
I
PC46
PC46
4700PF/ 50V
4700PF/ 50V
mx_c0603
mx_c0603
X7R 10%
X7R 10%
2
2
D
D
I
I
PQ24
PQ24
FDU878 0_F071
FDU878 0_F071
G
G
S
S
3
3
o
o
1P5V_DU AL_FB1_A
+1P5V_D UAL_SN_C
12
I
I
PR89
PR89
n
n
1
1
mx_r1206
mx_r1206
GNDGNDGND
f
f
i
i
12
I
I
+
+
PCE20
PCE20
560UF/6.3 V
560UF/6.3 V
12
NI
NI
e
e
PC90
PC90
680PF/5 0V
680PF/5 0V
X7R 10%
X7R 10%
d
d
GND GND GND GND
+5V_DUAL → +1P5V_DUAL (12A)
l
l
a
a
i
i
t
t
I
I
PL6
PL6
1UH/22A 0.2
1UH/22A 0.2
n
n
I
I
PR6
PR6
0 Ohm
0 Ohm
mx_r0603
mx_r0603
1 2
21
12
I
I
PC89
PC89
10UF/6.3V
10UF/6.3V
mx_c0805
mx_c0805
X5R 10%
X5R 10%
I=3.2A / V=18.9mV
12
I
I
+
+
PCE33
PCE33
820UF/2.5 V
820UF/2.5 V
ESR=7mΩ
ESR=7mΩ
+1P5V_D UAL
12
I
I
+
+
PCE29
PCE29
820UF/6.3 V
820UF/6.3 V
ESR=36mΩ
ESR=36mΩ
+1P5V_D UAL_FB2_A
12
NOBOM
NOBOM
PJP26
PJP26
SHORTPIN
SHORTPIN
P
P
A A
PEGATRON DT-MB RESTRICTED SECRET
+1P5V_DUAL_SW
+1P5V_DUAL_SW
+1P5V_DUAL_SW
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
IPX41-D3
IPX41-D3
IPX41-D3
Engineer:
Ttepic_Zhu
Ttepic_Zhu
Ttepic_Zhu
52 54Thursday, D ecember 10, 2009
52 54Thursday, D ecember 10, 2009
1
52 54Thursday, D ecember 10, 2009
Rev
Rev
Rev
1.02
1.02
1.02
Page 53
5
D D
4
+5V_DUAL _MAIN_GATE
+5V_DUA L_AUX_GATE
3
+5V_DUAL_USB_R......3A
+5VSB
2
YR23 0NImx_r0805YR23 0NImx_r0805
1 2
I
I
PQ17
PQ17
APM9932C KC
APM9932C KC
1
S1 D1
S1 D1
2
N
N
D1
D1
G1
G1
3
S2G2D2
S2G2D2
P
P
D2
D2
1
+5V_DUAL_USB_R+5V
KB/MS connect to +5V_DUAL_USB_R
8
7
6
54
+5V_DUAL_USB_F......3A
YR25 0NImx_r0805YR25 0NImx_r0805
1 2
I
I
PQ20
PQ20
APM9932C KC
APM9932C KC
1
S1 D1
S1 D1
2
G1
G1
3
S2G2D2
C C
d
i
i
d
Layout Notice: 3~4via for +5V, 2via for +5VSB,
large shape for +5V_DUAL
f
f
n
n
o
o
C
C
+5V
+12V_4P
I
1 2
g
g
+5VSB
1 2
4
I
PR77
PR77
8.2K
8.2K
B
1
B
1
a
a
I
I
PR79
PR79
8.2K
8.2K
B
1
B
1
+5V_DUAL _MAIN_GATE
3
3
C
C
r
r
I
I
PQ16
PQ16
E
E
PMBS39 04
PMBS39 04
t
t
2
2
GND
+5V_DUA L_AUX_GATE
3
3
C
C
I
I
PQ19
PQ19
PMBS39 04
PMBS39 04
E
E
2
2
GND
o
o
+5VSB
n
n
B B
I
I
PR78
PR78
1K
1K
1 2
1
S0/S1
0
A A
S3
S0/S5
+3VSBSW[39]
5
I
I
PR80
PR80
1K
1K
1 2
P
P
+5V_DUAL _MAIN
12
NI
NI
PC42
PC42
2200PF/ 50V
2200PF/ 50V
X7R 10%
X7R 10%
GND
e
e
+5V_DUA L_AUX
12
NI
NI
PC43
PC43
2200PF/ 50V
2200PF/ 50V
X7R 10%
X7R 10%
GND
+5V_DUAL.....A for DRAM
3
3
S
S
IIII
IIII
G
G
FDU878 0_F071
FDU878 0_F071
1
1
PQ15
PQ15
D
D
2
2
Layout Notice: 7~8via for +5V, 2via for +5VSB,
large shape for +5V_DUAL
+5V_DUAL
PR83
PR83
200 OHM
200 OHM
1%
1%
1 2
I
I
GND
3
2009.08.04 shawn
PCE19 removed.
1
1
3
3
G
G
2
2
D
D
I
I
PQ18
PQ18
NTR450 2PT1G
NTR450 2PT1G
S
S
S2G2D2
e
e
2
+5V_DUAL_USB_F+5V+5VSB
8
n
n
7
N
N
D1
D1
6
54
P
P
D2
D2
t
t
i
i
l
l
a
a
PEGATRON DT-MB RESTRICTED SECRET
+1P1V_FSB_VTT_LDO
+1P1V_FSB_VTT_LDO
+1P1V_FSB_VTT_LDO
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
IPX41-D3
IPX41-D3
IPX41-D3
Engineer:
Ttepic_Zhu
Ttepic_Zhu
Ttepic_Zhu
53 54Thursday, D ecember 10, 2009
53 54Thursday, D ecember 10, 2009
1
53 54Thursday, D ecember 10, 2009
Rev
Rev
Rev
1.02
1.02
1.02
Page 54
5
D D
4
3
2
n
n
t
t
i
i
a
a
l
l
1
C C
i
i
f
f
n
n
o
o
C
C
B B
r
r
t
t
a
a
g
g
e
e
P
P
A A
o
o
n
n
d
d
e
e
PEGATRON DT-MB RESTRICTED SECRET
+3P3V_PCIE&+3P3V_LAN
+3P3V_PCIE&+3P3V_LAN
+3P3V_PCIE&+3P3V_LAN
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON COMPUTER INC
PEGATRON COMPUTER INC
PEGATRON COMPUTER INC
Size Pr oject Name
Size Pr oject Name
Size Pr oject Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Engineer:
IPX41-D3
IPX41-D3
IPX41-D3
1
Hemine_He
Hemine_He
Hemine_He
54 54Thursday, D ecember 10, 2009
54 54Thursday, D ecember 10, 2009
54 54Thursday, D ecember 10, 2009
Rev
Rev
Rev
1.02
1.02
1.02
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