PEGATRON IPX41-D3 Schematic

5

IPX41-D3

D D

Intel Pentium processor

Conroe-L/Conroe/Wolfdate

VGA

C C

B B

A A

PCI Express
X16 SLOT

HDMI

PCI Express
X1 SLOT

Audio

ALC662

USB2.0

8 ports

LAN

Realtek
RTL8111DL

PCI-E X4

PCI-E X16

PCI-E X1

Azalia Link

480Mb/s

e

e

PCI-E X1

P

P

www.schematic-x.blogspot.com

4

Revision:1.02

LGA775

HOST BUS

INTEL

GMCH

EagleLake

DMI Link

INTEL

ICH7

t

t

a

a

g

g

SPI

r

r

SPI

Channel A

Channel B

SATA

o

o

n

n

LPC

3

53.+5V_DUAL53

545554.+3P3V_PCIE&+3P3V_LAN

56

DDR3 DIMM A1

DDR3 DIMM B1

f

f

n

n

o

o

SATA1

SATA2

C

C

SUPER I/O

Fintek F71808EU

PS2 KB/MS
FAN Control
H/W Monitor

i

i

d

d

2

e

e

01

01.Block Diagram

02

02.ECN CONTROL TABLE

03.Power Sequence

03

04.Power Flow

04
05

05.Clock Distribution

06.CLOCK06

07

07.PROCESSOR LGA775 1 - 3

08

08.PROCESSOR LGA775 2 - 3

09

09.PROCESSOR LGA775 3 - 3

10

10.INTEL EAGLELAKE 1 - 7

11

11.INTEL EAGLELAKE 2 - 7

12

12.INTEL EAGLELAKE 3 - 7

13

13.INTEL EAGLELAKE 4 - 7

14

14.INTEL EAGLELAKE 5 - 7

15

15.INTEL EAGLELAKE 6 - 7

16.INTEL EAGLELAKE 7 - 7

16

17.DDR3 CHANNEL A

17

i

i

18

18.DDR3 CHANNEL B

t

t

19

19.DDR3 TERMINATION A&B

20

n

n

20.INTEL ICH7 1 - 4

21

21.INTEL ICH7 2 - 4

22

22.INTEL ICH7 3 - 4

23

23.INTEL ICH7 4 - 4

24

24.PCI EXPRESS X1 SLOT

25

25.PCI EXPRESS X16 SLOT

26

26.INTEGRATED VGA PORT

27.DVI/HDMI CONTROL

27

28.DVI&HDMI / PCIE MUX

28

29.DVI&HDMI LEVEL SHIFTER

29

303230.DVI&HDMI CONNECTOR
31

31.USB CON.

32.USB HEADER CONNECTOR

33

33.SATA CONNECTOR FOR CPC

34

34.Realtek RTL8111DL

35.RJ-45+USB CONNECTOR

35

36.REALTEK ALC662 AZALIA CODEC

36

37.REAR AUDIO CONNECTOR

37
38

38.EMI CAP

39.SUPER I/O - F71808EU

39

40.PS2 KB &MS CONNECTOR FOR CPC

40

41.FAN CIRCUIT

41

42.FRONT PANEL CIRCUIT FOR CPC

42

43.SPI SERIAL FLASH LPC DEGUG

43

44.RTC / CMOS / SPKR/SCREW HOLE

44

45.ATX POWER_24P CONNECTOR

45
46

46.VCORE CONTROLLER

47

47.VCORE DRIVER1

48

48.VCORE DRIVER2

49

49.+1P1V_CORE

50

50.+1P1V_FSB_VTT

51

51.VTT_DDR&3P3VSB SWITCHING&1P5

52

52.+1P5V_DUAL

l

l

a

a

<Variant Name>

<Variant Name>

<Variant Name>

PEGATRON CORP.

PEGATRON CORP.

PEGATRON CORP.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

IPX41-D3

IPX41-D3

IPX41-D3

1

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

Block Diagram

Block Diagram

Block Diagram

Ttepic Zhu

Ttepic Zhu

Ttepic Zhu

1 54Thursday, December 10, 2009

1 54Thursday, December 10, 2009

1 54Thursday, December 10, 2009

1.02

Rev

Rev

Rev

5

ECN Control Table

ECN Control Table

ECN Control TableECN Control Table

4

3

2

1

D D

C C

B B

ECN No.

ECN No.

ECN No.ECN No.

DATE

DATE Schematics Revision

DATEDATE

Subject

Subject

SubjectSubject

n

n

C

C

Schematics Revision BOM Part Number

Schematics RevisionSchematics Revision

d

d

i

i

f

f

n

n

o

o

e

e

BOM Part Number PCB

BOM Part NumberBOM Part Number

l

l

a

a

i

i

t

t

n

n

PCBA

PCBA

PCBAPCBA
Revision

Revision

RevisionRevision

PCB

PCBPCB
Revision

Revision

RevisionRevision

o

o

r

r

t

t

a

a

g

g

e

e

P

P

A A

<Variant Name>

<Variant Name>

<Variant Name>

Title :

Title :

Title :

ECN

ECN

ECN

Ttepic Zhu

Ttepic Zhu

Engineer:

Engineer:

PEGATRON CORP.

PEGATRON CORP.

PEGATRON CORP.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

IPX41-D3

IPX41-D3

IPX41-D3

Engineer:

Ttepic Zhu

2 54Thursday, December 10, 2009

2 54Thursday, December 10, 2009

1

2 54Thursday, December 10, 2009

1.02

1.02

1.02

Rev

Rev

Rev

5

A

4

3

PCIRST#

2

1

3.3V

o

o

3.3V

8

PLTRST#

PSON#

7

PWROK

Power
Supply

6

8

n

n

8

f

f

PWROK_PS

PCIRST#_PCIEX16

PCIRST#_PCIEX1

d

d

i

i

/X

e

e

PCI Express X16

9

t

t

n

n

PCI Express X1

9

PCIRST#

3.3V

i

i

3.3V

a

a

l

l

8

GMCH

D D

C C

User press
Reset
button

10

B B

CPURST#

User press
Ctrl+Alt+Del

User press
Power
button

RSTCON#

Default

CPU

User
Clear
CMOS

PWRBTN#

Default

RTCRST#

CPUPWRGD

HINIT#

RTCRST#

1

Vcore

a

a

8

3

Super IO

3.3V

3.3V

RST_KB

RSMRST#

2

3.3V

3.3V

3.3V

3.3V

3.3V

o

o

r

r

t

t

Vcore

5

SLP_S3#

3.3V

ICH7

n

n

RTL8111DL

PWROK

7

5

SLP_S4#

3.3V

PLTRST#

Buffer Out

4

IO_PWRBTN#

3.3V

PLTRST#

C

C

3.3V

PCIRST#

g

g

e

e

P

P

1.02

1.02

1.02

A

Rev

Rev

Rev

<Variant Name>

<Variant Name>

<Variant Name>

Title :

Title :

Title :

Power Sequence

Power Sequence

Power Sequence

Ttepic Zhu

Ttepic Zhu

Engineer:

Engineer:

PEGATRON CORP.

PEGATRON CORP.

PEGATRON CORP.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

IPX41-D3

IPX41-D3

IPX41-D3

Engineer:

Ttepic Zhu

3 54Thursday, December 10, 2009

3 54Thursday, December 10, 2009

3 54Thursday, December 10, 2009

5

A

ATX12V

NCP5392MNR2G

3Phases

D D

ATXPWR

S0

VCORE_EN

I max.=75A.
TDC: 60A.
TDP:65W.(6)

4

VCORE

I max.=75A.
TDC: 60A.
TDP:65W.(6)

3

2

1

+5VSB

C C

+5V

+3VSBSW (S3)

+12V

B B

+3.3V

APM9932CKC

S0/S3/S5

APM9932CKC

S0/S3/S5

AOD452*2

S3/S5:+5VS B

S0/S3

APW7120+AOD452*2

e

e

g

g

+5V_DUAL_USB_R

+5V_DUAL_USB_F

LIN REG,1085

S0/S3/S5

+5V_DUAL

r

r

t

t

a

a

+1P1V_CORE

o

o

Io: 9A

Io: 3A

Io: 3A

+3P3VSB

Switch

APW7120KE_TRL

S0/S1/S3

n

n

Io: 1.5A

o

o

C

C

+1P5V_DUAL

Io

f

f

S0/S1: 12A

n

n

i

i

d

d

VTT_SELEC T

+12V

a

a

i

i

t

t

n

n

e

e

Io: 6.0A

+1P5V_DUAL

LM358 +
FDU8780_F071

S0

AOD472

S0

RT9045GSP +0P75V_VTT_DDR

S0

Io: 1.5A

+1P1V_FSB_VTT

Io: 1.5A

+1P5_ICH

Io
S0:1A

l

l

P

P

NOTE:

Linear REG

Switch REG

<Variant Name>

<Variant Name>

<Variant Name>

Title :

Title :

Title :

Power Flow

Power Flow

Power Flow

Ttepic Zhu

Ttepic Zhu

Engineer:

Engineer:

PEGATRON CORP.

PEGATRON CORP.

PEGATRON CORP.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

IPX41-D3

IPX41-D3

IPX41-D3

Engineer:

Ttepic Zhu

4 54Thursday, December 10, 2009

4 54Thursday, December 10, 2009

4 54Thursday, December 10, 2009

1.02

1.02

1.02

A

Rev

Rev

Rev

5

A

4

3

2

1

200/266/333 MHz

ICS
SLG8XP548T

D D

14.318 MHz

XTAL

C C

200/266/333 MHz

100 MHz

96 MHz

100 MHz

100 MHz

33 MHz

14.318 MHz

CK_FSB_CPU/#

CK_FSB_NB/#

CK_96M_DREF/#

CK_100M_PCIEX16/#100 MHz

CK_100M_ICH/#

CK_100M_SATA/#

CK_48M_USB48 MHz

CK_33M_ICH

CK_14M_ICH

CK_33M_SIO33 MHz

C

C

CPU

MCH

EagleLake

PCIEX16

ICH7

o

o

Super I/O

n

n

f

f

i

i

d

d

e

e

n

n

t

t

i

i

a

a

l

l

n

o

o

n

CK_PCIE_SLOT1/#100 MHz

CK_100M_LAN/#

PCIEX1_1

LAN

<Variant Name>

<Variant Name>

<Variant Name>

Clock Distribution

Clock Distribution

Clock Distribution

Title :

Title :

Title :

Engineer:

Engineer:

PEGATRON CORP.

PEGATRON CORP.

PEGATRON CORP.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

IPX41-D3

IPX41-D3

IPX41-D3

Engineer:

Ttepic Zhu

Ttepic Zhu

Ttepic Zhu

B B

r

r

t

t

a

a

g

g

e

e

P

P

100 MHz

A

Rev

Rev

Rev

1.02

1.02

5 54Thursday, December 10, 2009

5 54Thursday, December 10, 2009

5 54Thursday, December 10, 2009

1.02

5

+3P3V

CKL1 600O hm/100Mhz/0.5A

mx_l0603CKL1 600O hm/100Mhz/0.5A

mx_l0603

NI

NI

+3P3VSB

CKL2 600O hm/100Mhz/0.5A

I

D D

C C

B B

A A

I

PCB40

PCB40

PCB

PCB

PCB_BOA RD

PCB_BOA RD

I

I

21

mx_l0603CKL2 600O hm/100Mhz/0.5A

mx_l0603

21

2009.08.04 shawn
Clock gen power change to +3P3VSB for WOL function.

+CLKVCC3

VRMPW RGD_ICH[22]

SMB_CLK _S[17,18,22,2 4,25]

SMB_DAT A_S[17,18,22,2 4,25]

5

+CLKVCC3

12

I

I

CKCB2

CKCB2

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%

GND

NOTE:

CKR2 CKR10

2009.08.04 shawn
CKCB19 removed.

12

12

NI

NI

I

I

CKCB11

CKCB11

CKCB12

CKCB12

10UF/6.3V

10UF/6.3V

10UF/6.3V

10UF/6.3V

X5R 10%

X5R 10%

X5R 10%

X5R 10%

mx_c0805

mx_c0805

mx_c0805

mx_c0805

GND GND

GND

GND

2009.08.04 shawn
LR24 0ohm VP removed.

e

e

P

P

12

12

GND

NI

NI

CKC10

CKC10
33PF/50V

33PF/50V

NPO 5%

NPO 5%

GND

NI

NI

CKC11

CKC11
33PF/50V

33PF/50V

NPO 5%

NPO 5%

4

12

12

GND

PIN17 PIN18

25MHz

12

I

I

CKCB13

CKCB13

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%

12

NI

NI

CKCB17

CKCB17

4.7UF/6.3 V

4.7UF/6.3 V

X5R 10%

X5R 10%
mx_c0805

mx_c0805

2009.08.04 shawn
LR19 0ohm VP removed.

g

g

12

I

I

CKC8

CKC8
33PF/50V

33PF/50V

NPO 5%

NPO 5%

GND GND GND

I

I

CKCB3

CKCB3

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%

GND

GND

1 2

1 2

4

I

I

CKCB4

CKCB4

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%

25MHzNI I

12

I

I

CKCB9

CKCB9

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%

12

I

I

CKCB14

CKCB14

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%

12

I

I

CKCB18

CKCB18

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%

GND

a

a

I

I

Y1

Y1

14.318Mh z

14.318Mh z

GND

GND

3

3

12

I

I

CKCB5

CKCB5

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%

+CLKVCC3

GND

12

I

I

CKCB15

CKCB15

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%

GNDGND

VDD48_BW

r

r

t

t

CLK_PW RGD

OSC_CK14 M_XTALIN
OSC_CK14 M_XTALOUT

12

I

I

CKC9

CKC9
33PF/50V

33PF/50V

NPO 5%

NPO 5%

VDDPCI

VDD_PL L3
VDD_SRC

VDDCPU

VDDREF

12

I

I

CKR2

CKR2
10K

10K

VOUT_VDDI O

VDD_IO_9 6

+VDD_IO

12

I

I

CKCB16

CKCB16

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%

o

o

GND

12

GNDGND

I

I

CKCB6

CKCB6

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%

GND

GND

IIII

IIII

CKU2

CKU2

CKU2

CKU2

CKU2CKU2

CKU2CKU2

2

VDD_PCI

16

VDD_PLL3

31

VDD_SRC

47

VDD_CPU

53

VDD_REF

8

VSS_PCI

23

VSS_SRC1

34

VSS_SRC2

44

VSS_CPU

50

VSS_REF

40

SEL_24.576MHz

12

VDD_I/O_3.3

20

VDD_PLL3_I/O

26

VDD_SRC_I/O1

37

VDD_SRC_I/O2

41

VDD_CPU_I/O

19

VSS_PLL3

15

VSS_I/O

n

n

9

VDD_48

11

VSS_48

48

CKPWRGD/PD#

52

XTAL_IN

51

XTAL_OUT

56

SCL

55

SDA

CLOCK Gen. IN06

CLOCK Gen. IN06

C

C

3

CPU_0

CPU_0#

CPU_1_AMT

CPU_1_AMT#

SRC_8/CPU_ITP

SRC_8#/CPU_ITP#

SRC_7

SRC_7#

SRC_6

SRC_6#

PCI_STOP#/SRC_5

CPU_STOP#SRC_5#

SRC_4

SRC_4#

SRC_3

SRC_3#

SRC_2

SRC_2#

25MHz_0_F

25MHz_1/24.576MHz

SRC_0/DOT_96

SRC_0#/DOT_96#

ITP_EN/PCI_5

PCI_4/SRC_5_EN

PCI_3
PCI_2
PCI_1
PCI_0

o

o

FS_A/48MHz_0

FS_B/TEST_MODE

REF/FS_C/TEST_SEL

3

RCPUHC LK

46

RCPUHC LK#

45

RMCHHCL K

43

RMCHHC LK#

42

39
38

RCK_100M_ ICH

36

RCK_100M _ICH#

35

RCK_10 0M_PE16

33

RCK_100 M_PE16#

32

RCK_100 M_PE1

30

RCK_10 0M_PE1#

29

RCK_100M _MCH

27

RCK_100 M_MCH#

28

RCK_100 M_LAN

24

RCK_10 0M_LAN#

25

RCK_100 M_SATA

21

RCK_100 M_SATA#

22

R_LAN_2 5M

17
18

RCK_96M_ DREF

13

RCK_96M _DREF#

14

PCIF5/ITP_EN(Pin7):
1: CPU_ITP

PCI4/SRC5_EN(Pin6):
1: SRC5 Output

PCI_5

7

CK_33M_P CI4

6

RCK_33M_ SIO

5

RCK_33M _DBG

4

RCK_33M_ ICH

f

n

n

RCK_48M _USB

FSLB

RCK_14M_ ICH

f

Del CK_48_SIO to FS

CK_48M_U SB

3
1

PCI3/CFG0(Pin5):
Strap for SATA PLL
1: PLL2, SS OFF

PCI2/TME(Pin4):
1: SR enable

10

49

54

0

0
0

0

NOBOM

NOBOM
NOBOM

NOBOM

I
I

0

0
0

0

NOBOM

NOBOM
NOBOM

NOBOM

0

0
0

0

NOBOM

NOBOM
NOBOM

NOBOM

0

0
0

0

NOBOM

NOBOM
NOBOM

NOBOM

0

0
0

0

NOBOM

NOBOM
NOBOM

NOBOM

0

0
0

0

NOBOM

NOBOM
NOBOM

NOBOM

0

0
0

0

NOBOM

NOBOM
NOBOM

NOBOM

CKR1 33

CKR1 33

1 2

I

I

0

0
0

0

NOBOM

NOBOM
NOBOM

NOBOM

12

NI

NI

CKR68

CKR68

4.7K

4.7K

i

i

12

NI

NI

CKR64

CKR64

4.7K

4.7K

GND GND GND

+CLKVCC3

12

I

I

CKR67

CKR67

4.7K

4.7K

d

d

12

NI

NI

CKR61

CKR61

4.7K

4.7K

12

NI

NI

CKC12

CKC12
10PF/50V

10PF/50V

NPO 5%

NPO 5%

GND

2

CKR23

CKR23

12

CKR22

CKR22

12

CKR210ICKR210

12

CKR240ICKR240

12

CKR5

CKR5

12

CKR6

CKR6

12

CKR7

CKR7

12

CKR8

CKR8

12

CKR10

CKR10

12

CKR11

CKR11

12

CKR9

CKR9

12

CKR14

CKR14

12

CKR12

CKR12

12

CKR13

CKR13

12

CKR20

CKR20

12

CKR19

CKR19

12

t

CKR25

CKR25

12

CKR26

CKR26

12

12

e

e

I

I

CKR66

CKR66

4.7K

4.7K

12

NI

NI

CKR60

CKR60

4.7K

4.7K

2009.08.04 shawn
Add CKR41 for SIO CK_48M_SIO clock.
CKR40, CKR41 change to 22ohm.

I

I
I

I

CKR39 33

CKR39 33

I

I

NOTE:

Single End damping resistor
Single Load => 33 OHM
Double Load => 22 OHM

2

t

n

n

12

NI

NI

CKC5

CKC5
10PF/50V

10PF/50V

NPO 5%

NPO 5%

GND

CKR41 22 OHM 5%

CKR41 22 OHM 5%

1 2

CKR40 22 OHM 5%

CKR40 22 OHM 5%

1 2

1 2

1

CPUHCLK [7]
CPUHCLK # [7]

MCHHCL K [10]
MCHHCL K# [10]

CK_100M_ ICH [20]
CK_100M_ ICH# [20]

CK_100M _PE16 [25]
CK_100M _PE16# [25]

CK_100M _PE1 [24]
CK_100M _PE1# [24]

CK_100M _MCH [10]
CK_100M_ MCH# [10]

CK_100M _SATA [21]
CK_100M _SATA# [21]

i

i

CK_96M_ DREF [ 13]
CK_96M_ DREF# [13]

l

l

CK_100M _LAN [34]
CK_100M _LAN# [34]

a

a

CK_25M _LAN [34]

1 2

I

1 2

I

1 2

I

1 2

NI

2009.08.13 shawn
CKC6 removed.

AR72 1KIAR72 1K

I

1 2

AR27 1KIAR27 1K

I

1 2

AR28 1KIAR28 1K

I

1 2

PEGATRON DT-MB RESTRICTED SECRET

PEGATRON CORP.

PEGATRON CORP.

PEGATRON CORP.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

2009.08.04 shawn
CKR1 form NI change to I for LAN 25M clock.

NOTE:

PCIF_5 is dedicated for ICH
PCI4 is for the shortest route
PCI3 is for the longest route

SR5833ISR5833
SR5933ISR5933
SR5733ISR5733
SR6033NISR6033

12

NI

NI

CKC3

CKC3
10PF/50V

10PF/50V

NPO 5%

NPO 5%

GND GND

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

IPX41-D3

IPX41-D3

IPX41-D3

GND

12

NI

NI

CKC4

CKC4
10PF/50V

10PF/50V

NPO 5%

NPO 5%

12

NI

NI

CKC13

CKC13
10PF/50V

10PF/50V

NPO 5%

NPO 5%

1

CK_33M_SI O [39]
CK_33M_T PM [43 ]
CK_33M_IC H [20]
CK_33M_D EBUG [43]

CLOCK CK505

CLOCK CK505

CLOCK CK505

Ttepic Zhu

Ttepic Zhu

Ttepic Zhu

FSBSEL0 [ 8,13]

CK_48M_SI O [39]
CK_48M_U SB [20]

FSBSEL1 [ 8,13]

CK_14M_IC H [22]

FSBSEL2 [ 8,13]

6 54Thursday, December 10, 2009

6 54Thursday, December 10, 2009

6 54Thursday, December 10, 2009

Rev

Rev

Rev

1.02

1.02

1.02

5

I

I

XU1A

XU1A

SOCKET77 5/ATX

HA#[3..35][10]

HA#3
HA#4
HA#5
HA#6

D D

HREQ#[0..4][10]

HADSTB0#[10]

HT2

HT2
HT7

HT7

NOBOM

NOBOM
NOBOM

NOBOM

C C

B B

A A

NOBOM

NOBOM
NOBOM

NOBOM

HRS#[0..2][10]

CPURES ET#[10]

HA#[3..35][10]

TPC26b

TPC26b
TPC26b

TPC26b

HADSTB1#[10]

TPC26b

TPC26b
TPC26b

TPC26b

CPUHCLK[6]
CPUHCLK #[6]

HT12

HT12
HT13

HT13

1
1

1
1

5

HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15 CPU_TP _AD3
HA#16

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

CPU_TP_ N4
CPU_TP_ P5

HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

HA#32
HA#33
HA#34
HA#35

CPU_TP _AC4
CPU_TP _AE4

HRS#2
HRS#1
HRS#0

+VTT_O UT_R

12

I

I

HR13

HR13
62

62

12

NI

NI

HC1

HC1
22PF/50V

22PF/50V

NPO 5%

NPO 5%

GND

SOCKET77 5/ATX

L5

A03#

P6

A04#

M5

A05#

L4

A06#

M4

A07#

R4

A08#

T5

A09#

U6

A10#

T4

A11#

U5

A12#

U4

A13#

V5

A14#

V4

A15#

W5

A16#

K4

REQ0#

J5

REQ1#

M6

REQ2#

K6

REQ3#

J6

REQ4#

R6

ADSTB0#

N4

RSVD1

P5

RSVD2

AB6

A17#

W6

A18#

Y6

A19#

Y4

A20#

AA4

A21#

AD6

A22#

AA5

A23#

AB5

A24#

AC5

A25#

AB4

A26#

AF5

A27#

AF4

A28#

AG6

A29#

AG4

A30#

AG5

A31#

AH4

A32#

AH5

A33#

AJ5

A34#

AJ6

A35#

AD5

ADSTB1#

AC4

RSVD3

AE4

RSVD4

A3

RS2#

F5

RS1#

B3

RS0#

F28

BCLK0

G28

BCLK1

G23

RESET#

P

P

REV=1.3

REV=1.3

e

e

ADS#

BNR#

HIT#

RSP#

BPRI#
DBSY#
DRDY#

HITM#
IERR#

INIT#
LOCK#
TRDY#
BINIT#

DEFER#

MCERR#

AP0#

AP1#

DP0#
DP1#
DP2#
DP3#

BR0#

GTLREF1

GTLREF0

GTLREF2

GTLREF3

g

g

FC10

FC15

4

+1P1V_FS B_VTT

12

I

I

HR1

HR1
62

62

D2
C2
D4

CPU_TP_ H4

H4
G8
B2
C1
E4

HIERR#

AB2
P3
C3
E3
AD3
G7

CPU_TP _AB3

AB3

CPU_TP_ U2

U2

CPU_TP_ U3

U3

CPU_TP_J 16

J16

CPU_TP _H15

H15

CPU_TP _H16

H16

CPU_TP_J 17

J17

F3

H2

CPU_GTL REF0

H1

1 2

F2

G10

a

a

CPU_MC H_GTLREF

E24

CPU_GTL REF_SEL

H29

12

NI

NI

HCB5

HCB5
220PF/5 0V

220PF/5 0V

X7R 10%

X7R 10%

GND

4

RMA1

RMA1

NOBOM

NOBOM

SMD4X25_ NP

SMD4X25_ NP

RMA1 is soldermask on trace for RMA

1

purpose. Place on suitable location where

1

can be easily reached by Probe

HADS# [10]
HBNR# [10]
HIT# [10]

HBPRI# [10]
HDBSY# [10]
HDRDY# [10]
HITM# [10]

HINIT# [21]
HLOCK# [10]
HTRDY# [10]

HDEFER# [10]

HT9

HT9
HT10

HT10

1

NOBOM

NOBOM

1

NOBOM

NOBOM

TPC26b

TPC26b

HT11

HT11

TPC26b

TPC26b

HT5

HT5

1

NOBOM

NOBOM

HT6

HT6

1

NOBOM

NOBOM

TPC26b

TPC26b

HT1

HT1

1

NOBOM

NOBOM

TPC26b

TPC26b

1

NOBOM

NOBOM

TPC26b

TPC26b
TPC26b

TPC26b

I

I

HR5

HR5
10

12

NI

NI

HCB2

HCB2
220PF/5 0V

220PF/5 0V

X7R 10%

X7R 10%

o

o

HT39

HT39

1

HT14

HT14

TPC26b

TPC26b

1

TPC26b

TPC26b

10

I

I

HR6

HR6
10

10

n

n

NOBOM

NOBOM

NOBOM

NOBOM

12

12

CPU_GTL REF1

12

NI

NI

HCB1

HCB1
220PF/5 0V

220PF/5 0V

X7R 10%

X7R 10%

GND GND GNDGND

NOTE:

Place near CPU

NJP11

NJP11

NJP10

NJP10

SHORTPIN _RECT

SHORTPIN _RECT

SHORTPIN _RECT

SHORTPIN _RECT

NOBOM

NOBOM

NOBOM

NOBOM

1 2

r

r

t

t

+VTT_O UT_L

12

I

I

HR2

HR2
62

62

CPU_GTL REF1_R

CPU_GTL REF0_R

12

I

I

HCB3

HCB3
1UF/10V

1UF/10V

mx_c0603

mx_c0603

3

HT8

HT8

1

NOBOM

NOBOM

TPC26b

TPC26b

HT3

HT3

1

NOBOM

NOBOM

TPC26b

TPC26b

HT4

HT4

1

NOBOM

NOBOM

TPC26b

TPC26b

HBREQ0# [10]

+VTT_O UT_L

12

12

12

I

I

HCB4

HCB4
1UF/10V

1UF/10V

mx_c0603

mx_c0603

C

C

3

+VTT_O UT_L

12

I

I

HR4

HR4

57.6

57.6

1%

1%

12

I

I

HR8

HR8
100

100

1%

1%

o

o

GNDGND

HD#[0..63][10]

I

I

2009.08.04 shawn

HR3

HR3

HR3 from 49.9ohm change to 57.6ohm

57.6

57.6

1%

1%

n

n

I

I

HR7

HR7
100

100

1%

1%

i

i

HD#[0..63][10] HD#[0..63] [10]

f

f

HDBI0#[10]

HDSTBN0 #[10]
HDSTBP0#[10]

d

d

HDBI1#[10]

HDSTBN1 #[10]
HDSTBP1#[10]

2

I

I

XU1B

XU1B

SOCKET77 5/ATX

SOCKET77 5/ATX

HD#0

B4

A10
A11
B10
C11

B12
C12
D11

E10
D10
F11
F12
D13
E13
G13
F14
G14
F15
G15

G11

G12
E12

C5
A4
C6
A5
B6
B7
A7

D8

A8

C8
B9

G9

F8
F9
E9
D7

D00#
D01#
D02#
D03#
D04#
D05#
D06#
D07#
D08#
D09#
D10#
D11#
D12#
D13#
D14#
D15#

DBI0#

a

a

i

i

t

t

DSTBN0#
DSTBP0#

D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#

DBI1#

DSTBN1#
DSTBP1#

REV=1.3

REV=1.3

NOTE:

ICH_GPIOA

PEGATRON DT-MB RESTRICTED SECRET

PEGATRON CORP.

PEGATRON CORP.

PEGATRON CORP.

Size Pr oject Name

Size Pr oject Name

Size Pr oject Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7 HD#39
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15

n

n

e

e

HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31

2

D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#

l

l

DBI2#

DSTBN2#
DSTBP2#

D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DBI3#

DSTBN3#
DSTBP3#

Default is 0.63*VTT

ICH_GPIOB

G16
E15
E16
G18
G17
F17
F18
E18
E19
F20
E21
F21
G21
E22
D22
G22

D19

G20
G19

D20
D17
A14
C15
C14
B15
C18
B16
A17
B18
C21
B21
B19
A19
A22
B22

C20

A16
C17

0

10

01

11

1

HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38

HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47

HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

GTLREF

0.615*VTT0

0.63*VTT

0.65*VTT

0.67*VTT

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

IPX41-D3

IPX41-D3

IPX41-D3

1

HD#[0..63] [10]

HDBI2# [10]

HDSTBN2 # [10]
HDSTBP2# [10]

HDBI3# [10]

HDSTBN3 # [10]
HDSTBP3# [10]

COMMENTS

HQ1 off, HQ2 on
HQ3 off, HQ4 on
HQ1 off, HQ2 on
HQ3 on, HQ4 off
HQ1 on, HQ2 off
HQ3 off, HQ4 on
HQ1 on, HQ2 off
HQ3 on, HQ4 off

INTEL LGA-775 1 - 3

INTEL LGA-775 1 - 3

INTEL LGA-775 1 - 3

Ttepic Zhu

Ttepic Zhu

Ttepic Zhu

7 54Thursday, December 10, 2009

7 54Thursday, December 10, 2009

7 54Thursday, December 10, 2009

Rev

Rev

Rev

1.02

1.02

1.02

5

PLACE NEAR SB

+1P1V_FS B_VTT

PLACE COMPONENTS AS CLOSE AS
POSSIBLE TO CPU SOCKET. THE
TRACE WIDTH TO CAPS MUST BE
NO SMALLER THAN 12 MIL.

D D

C C

+VTT_O UT_R

RCVID[0..7][46]

B B

VID_SELEC T[46]

VCC_MB _SENSE[46]

VSS_MB_S ENSE[46]

+VCORE

A A

SMI#[21]
A20M#[21]

HFERR#[21]
INTR[21]
NMI[21]
IGNNE#[21]
STPCLK#[21]

NOBOM

NOBOM

NOBOM

NOBOM

NOBOM

NOBOM

NOTE:

The VCCIO PLL Filter Circuit is no longer
needed since Conroe CPU

HRN2C

680

680
680

680
680

680
680

680

680

680
680

680
680

680
680

680

NOBOM

NOBOM

NOBOM

NOBOM

HRN2C
HRN1A

HRN1A
HRN1D

HRN1D
HRN2D

HRN2D

HRN2A

HRN2A
HRN2B

HRN2B
HRN1B

HRN1B
HRN1C

HRN1C

HT32

HT32

TPC26b

TPC26b

5

GND

5 6

I

I

1 2

I

I

7 8

I

I

7 8

I

I

1 2

I

I

3 4

I

I

3 4

I

I

5 6

I

I

TRD_CPU _P[39]
TRD_CPU _N[39]

HT31

HT31

TPC26b

TPC26b

1

1

12

I

I

HR17

HR17
62

62

HT42

HT42

TPC26b

TPC26b

HT43

HT43

1

TPC26b

TPC26b

HT44

HT44

1

TPC26b

TPC26b

VCC_SEN _AN3

VSS_SEN _AN4

HT42

1

HT43

HT44

RCVID0
RCVID1
RCVID2
RCVID3
RCVID4
RCVID5
RCVID6
RCVID7

GND

GND

P

P

I

I

XU1C

XU1C

SOCKET77 5/ATX

SOCKET77 5/ATX

P2

SMI#

K3

A20M#

R3

FERR#/PBE#

K1

LINT0

L1

LINT1

N2

IGNNE#

M3

STPCLK#

A23

VCCA

B23

VSSA

C23

VCCIOPLL

AM2

VID0

AL5

VID1

AM3

VID2

AL6

VID3

AK4

VID4

AL4

VID5

AM5

VID6

AM7

VID7

AN7

VID_SECECT

AE8

SKTOCC#

AL1

THERMDA

AK1

THERMDC

AJ7

VSS_AJ7

AH7

VSS_AH7

AN5

VCC_MB_REGULATION

AN6

e

e

VSS_MB_REGULATION

AN3

VCC_SENSE

AN4

VSS_SENSE

AL8

VCC_D_SENSE

AL7

VSS_D_SENSE

4

( CPU_SLP )

BOOTSELECT

g

g

REV=1.3

REV=1.3

4

If NOT support C3/ C4, these 4 signals

Note:

can be NC with a PU resistor

Install HR24 for pin: L2

PM_SLP#

DPSLP#

Install HR22 for pin: P1

CPU_PSI

Install HR36 for pin: Y3

DPRSTP#

Install HR37 for pin: T2

TESTHI0

F26

TESTHI00
TESTHI01
TESTHI10
TESTHI11

TESTHI13
TESTHI02
TESTHI03
TESTHI04
TESTHI05
TESTHI06
TESTHI07
TESTHI08
TESTHI09

COMP0
COMP1
COMP2
COMP3
COMP4
COMP5
COMP6
COMP7
COMP8

TESTHI12

RSVD33
RSVD34
RSVD35
RSVD36
RSVD12
RSVD21

RSVD9

MSID0

MSID1

LL_ID1

LL_ID0

PECI

IMPSEL

a

a

FORCEPR#

PWRGOOD

PROCHOT#

THERMTRIP#

TESTHI1

W3

TESTHI10

H5

TESTHI11

P1

TESTHI13

L2

TESTHI2_7

F25
G25
G27
G26
G24
F24

TESTHI8

G3

TESTHI9

G4

HCOMP0

A13

HCOMP1

T1

HCOMP2

G2

HCOMP3

R1

HCOMP4

J2

HCOMP5

T2
Y3

HCOMP7

AE3

HCOMP8

B13

TESTHI12

W2

HR48

HR48

NI

NI

CPU_RSV D33

G1

CPU_TP_R C2

CPU_TP_R C2

U1

CPU_TP_R C3

A24

CPU_TP_R C4

E29

CPU_TP _AH2

AH2

CPU_TP_ G6

G6

CPU_TP _F29

F29

MSID0

W1

MSID1

V1

CPU_LL_ID 1

AA2

CPU_LL_ID 0

V2

CPU_BOO T

Y1

VRDSEL

AL3

o

NC

t

t

o

G5

r

r

IMPSEL_F 6

F6

AK6

N1

AL2

M2

THERMALTRIP# NEED A PULL UP RESISTOR NEAR SB

HR41 51

HR41 51

I

I

HR19 51

HR19 51

I

I

HR20 51

HR20 51

I

I

HR22 51

HR22 51

I

I

HR24 51

HR24 51

I

I

HR23 51

HR23 51

I

I

HR25 51

HR25 51

I

I

HR44 51

HR44 51

I

I

HR49 49.9 1%

HR49 49.9 1%

I

I

HR46 49.9 1%

HR46 49.9 1%

I

I

HR28 49.9 1%

HR28 49.9 1%

I

I

HR33 49.9 1%

HR33 49.9 1%

I

I

HR32 49.9 1%

HR32 49.9 1%

NI

NI

HR37 49.9 1%

HR37 49.9 1%

I

I

HR36 49.9 1%

HR36 49.9 1%

I

I

HR47 49.9 1%

HR47 49.9 1%

NI

NI

HR39 24.9 1%

HR39 24.9 1%

I

I

HR21 51

HR21 51

I

I

0

0

12

HR54 51

HR54 51

I

I

1
1

TPC26b

TPC26b

1

TPC26b

TPC26b

1

TPC26b

TPC26b

1

TPC26b

TPC26b

1

TPC26b

TPC26b
TPC26b

TPC26b

+VTT_O UT_L

12

NI

NI

HR53

HR53
62

62

n

n

12

I

I

HR56

HR56
51

51

GND

3

+1P1V_FS B_VTT

12
12
12
12

12
12

1 2
1 2

CPU_PSI [46]

1 2
1 2
1 2
1 2

12
12
12
12

1 2

12

12

HT21

HT21
HT15

HT15

NOBOM

NOBOM

HT22

HT22

NOBOM

NOBOM

HT16

HT16

NOBOM

NOBOM

HT24

HT24

NOBOM

NOBOM

HT25

HT25

NOBOM

NOBOM
NOBOM

NOBOM

HR641K

HR641K

1 2

12

NI

NI

HR50

HR50
51

51

GND

HT29

HT29

1

NOBOM

NOBOM

TPC26b

TPC26b

HT30

HT30

1

NOBOM

NOBOM

TPC26b

TPC26b

PECI [39]

+VTT_O UT_R +VTT_OUT _L +V TT_OUT_R

12

I

I

HR61

HR61
130

130

1%

1%

+VTT_O UT_L

GND

NI

NI

GND

12

NI

NI

HR51

HR51

o

o

51

51

C

C

GND

12

GND

12

12

NI

NI

HR62

HR62
100

100

12

NI

NI

HCB16

HCB16

0.1UF/16V

0.1UF/16V

GND

3

+VTT_O UT_L

I

I

HR55

HR55
51

51

I

I

HR63

HR63
130

130

1%

1%

+VTT_O UT_R

I

I
I

I
I

I

+VTT_O UT_R

I

I
I

I
I

SYS_RESE T#[22,39,42]

f

f

1 2

VRM_PW RGD[22,46]

FSBSEL0[6, 13]
FSBSEL1[6, 13]
FSBSEL2[6, 13]

HFORCE PH# [48]

CPUPW RGD [22]

PROCHO T# [48]

H_THMTR IP# [21]

I
I

I
I

I
I

I

+1P1V_FS B_VTT

+VTT_O UT_R

+VTT_O UT_L

HR60 5 1

HR60 5 1

I

I

n

n

BOOTSELECT:
Install PD resistor to
prevent PSC SMF CDM PSL
CPU from booting

HR18 49.9 1%

HR18 49.9 1%

1 2

HR43 49.9 1%

HR43 49.9 1%

1 2

HR42 49.9 1%

HR42 49.9 1%

1 2

12

I

I

HR26

HR26

49.9

49.9

1%

1%

GND

HR30 51

HR30 51

1 2

HR29 51

HR29 51

1 2

HR31 51

HR31 51

1 2

HR34 51

HR34 51

1 2

HR35 51

HR35 51

1 2

HR38 51

HR38 51

1 2

e

e

d

NOBOM

NOBOM

i

i

NOBOM

NOBOM

NOBOM

NOBOM

NOBOM

NOBOM
NOBOM

NOBOM
NOBOM

NOBOM
NOBOM

NOBOM
NOBOM

NOBOM

d

HT23

HT23
HT17

HT17

TPC26b

TPC26b
TPC26b

TPC26b

HT18

HT18

HT19

HT19

TPC26b

TPC26b

HT26

HT26
HT20

HT20

TPC26b

TPC26b

HT27

HT27

TPC26b

TPC26b

HT28

HT28

TPC26b

TPC26b
TPC26b

TPC26b
TPC26b

TPC26b

HR57 470 1%

HR57 470 1%

1 2

I

I

HR59 470 1%

HR59 470 1%

1 2

I

I

HR58 470 1%

HR58 470 1%

1 2

I

I

2009.08.14 shawn
HR57, HR58, HR59 from 470 5% change to 470 1%.

2

I

I

XU1D

XU1D

SOCKET77 5/ATX

SOCKET77 5/ATX

TCK

AE1

TCK

TDI

AD1

TDI

TDO

AF1

TDO

TMS

AC1

TMS

TRST#

AG1

t

t

AJ2

AJ1
AD2
AG2

AF2
AG3

AC2

AK3

AJ3

N5
C9
E7

AE6

D16

A20

E23

AM6

G29

H30
G30

TRST#

i

i

BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#

DBR#

ITPCLK<0>
ITPCLK<1>

RSVD17
RSVD18
RSVD19
RSVD20
RSVD22
RSVD23
RSVD31

VTTPWRGD

BSEL0
BSEL1
BSEL2

a

a

REV=1.3

REV=1.3

12

I

I

HR27

HR27

49.9

49.9

1%

1%

GND

BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#

n

n

CPU_ITPH CLK

1

CPU_ITPHC LK#

1

CPU_TP_ N5

1

H_BPM1 _2
CPU_TP_ E7

1

CPU_TP _AE6

1

CPU_TP _D16

1

CPU_TP _A20

1

CPU_TP _E23

1

+VTT_O UT_R +1P5V_ICH

12

I

I

HR52

HR52
680

680

12

NI

NI

HC2

HC2
100PF/5 0V

100PF/5 0V

NPO 5%

NPO 5%

GND

VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8

VTT9
VTT10
VTT11
VTT12
VTT13

l

l

VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24

VTT_OUT1

VTT_OUT2

VCC_PLL

2009.10.22 shawn
+CPU_VCCPLL floating, change power net name to +1P5V_ICH.

VTT_SEL

1

NOTE:

FSB_VTT Net Name changed

+1P1V_FS B_VTT

A29
B25
B29
B30
C29
A26
B27
C28
A25
A28
A27
C30
A30
C25
C26
C27
B26
D27
D28
D25
D26
B28
D29
D30

+VTT_O UT_R

AA1

J1

D23

F27

+VTT_O UT_L

12

NI

NI

HCB13

HCB13

0.1UF/16V

0.1UF/16V

GND GND

12

I

I

HCB14

HCB14

0.01UF/25 V

0.01UF/25 V

X7R 10%

X7R 10%

GNDGND

VTT_SE LECT [50]

12

12

PEGATRON DT-MB RESTRICTED SECRET

INTEL LGA-775 2 - 3

INTEL LGA-775 2 - 3

INTEL LGA-775 2 - 3

Title :

Title :

Title :

Engineer:

Engineer:

PEGATRON CORP.

PEGATRON CORP.

PEGATRON CORP.

Size Pr oject Name

Size Pr oject Name

Size Pr oject Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Engineer:

IPX41-D3

IPX41-D3

IPX41-D3

1

Ttepic Zhu

Ttepic Zhu

Ttepic Zhu

8 54Thursday, December 10, 2009

8 54Thursday, December 10, 2009

8 54Thursday, December 10, 2009

NI

NI

HCB12

HCB12

0.1UF/16V

0.1UF/16V

NI

NI

HCB15

HCB15
10UF/6.3V

10UF/6.3V

X5R 10%

X5R 10%
mx_c0805

mx_c0805

Rev

Rev

Rev

1.02

1.02

1.02

5

4

3

2

1

+VCORE

D D

I

I

I

XU1E

XU1E

SOCKET77 5/ATX

SOCKET77 5/ATX

AA8

VCC1

AB8

VCC2

AC23

VCC3

AC24

VCC4

AC25

VCC5

AC26

VCC6

AC27

VCC7

AC28

VCC8

AC29

VCC9

AC30

VCC10

AC8

VCC11

AD23

VCC12

AD24

VCC13

AD25

VCC14

AD26

VCC15

AD27

VCC16

AD28

VCC17

AD29

VCC18

AD30

VCC19

AD8

C C

B B

A A

AE11
AE12
AE14
AE15
AE18
AE19
AE21
AE22
AE23

AE9
AF11
AF12
AF14
AF15
AF18
AF19
AF21
AF22

AF8

AF9
AG11
AG12
AG14
AG15
AG18
AG19
AG21
AG22
AG25
AG26
AG27
AG28
AG29
AG30

AG8

AG9

VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56

REV=1.3

REV=1.3

VCC112
VCC111
VCC110
VCC109
VCC108
VCC107
VCC106
VCC105
VCC104
VCC103
VCC102
VCC101
VCC100

VCC99
VCC98
VCC97
VCC96
VCC95
VCC94
VCC93
VCC92
VCC91
VCC90
VCC89
VCC88
VCC87
VCC86
VCC85
VCC84
VCC83
VCC82
VCC81
VCC80
VCC79
VCC78
VCC77
VCC76
VCC75
VCC74
VCC73
VCC72
VCC71
VCC70
VCC69
VCC68
VCC67
VCC66
VCC65
VCC64
VCC63
VCC62
VCC61
VCC60
VCC59
VCC58
VCC57

AM14
AM12
AM11
AL9
AL30
AL29
AL26
AL25
AL22
AL21
AL19
AL18
AL15
AL14
AL12
AL11
AK9
AK8
AK26
AK25
AK22
AK21
AK19
AK18
AK15
AK14
AK12
AK11
AJ9
AJ8
AJ26
AJ25
AJ22
AJ21
AJ19
AJ18
AJ15
AJ14
AJ12
AJ11
AH9
AH8
AH30
AH29
AH28
AH27
AH26
AH25
AH22
AH21
AH19
AH18
AH15
AH14
AH12
AH11

I

XU1F

XU1F

SOCKET77 5/ATX

SOCKET77 5/ATX

AM15

VCC113

AM18

VCC114

AM19

VCC115

AM21

VCC116

AM22

VCC117

AM25

VCC118

AM26

VCC119

AM29

VCC120

AM30

VCC121

AM8

VCC122

AM9

VCC123

AN11

VCC124

AN12

VCC125

AN14

VCC126

AN15

VCC127

AN18

VCC128

AN19

VCC129

AN21

VCC130

AN22

VCC131

AN25

VCC132

AN26

VCC133

AN29

VCC134

AN30

VCC135

AN8

VCC136

AN9

VCC137

J10

VCC138

J11

VCC139

J12

VCC140

J13

VCC141

J14

VCC142

J15

VCC143

J18

VCC144

J19

VCC145

J20

VCC146

J21

VCC147

J22

VCC148

J23

VCC149

J24

VCC150

J25

VCC151

J26

VCC152

J27

VCC153

J28

VCC154

J29

VCC155

J30

VCC156

J8

VCC157

J9

VCC158

K30

VCC159

K29

VCC160

K28

VCC161

K27

VCC162

K26

VCC163

K25

VCC164

K24

VCC165

K23

VCC166

K8

VCC167

Y8

VCC168

P

P

REV=1.3

REV=1.3

NOBOM

NOBOM
NOBOM

NOBOM
NOBOM

NOBOM
NOBOM

NOBOM

e

e

NOBOM

NOBOM
NOBOM

NOBOM

VCC225
VCC224
VCC223
VCC222
VCC221
VCC220
VCC219
VCC218
VCC217
VCC216
VCC215
VCC214
VCC213
VCC212
VCC211
VCC210
VCC209
VCC208
VCC207
VCC206
VCC205
VCC204
VCC203
VCC202
VCC201
VCC200
VCC199
VCC198
VCC197
VCC196
VCC195
VCC194
VCC193
VCC192
VCC191
VCC190
VCC189
VCC188
VCC187
VCC186
VCC185
VCC184
VCC183
VCC182
VCC181
VCC180
VCC179
VCC178
VCC177
VCC176
VCC175
VCC174
VCC173
VCC172
VCC171
VCC170
VCC169

g

g

L8
M23
M24
M25
M26
M27
M28
M29
M30
M8
N23
N24
N25
N26
N27
N28
N29
N30
N8
P8
R8
T23
T24
T25
T26
T27
T28
T29
T30
T8
U23
U24
U25
U26
U27
U28
U29
U30
U8
V8
W23
W24
W25
W26
W27
W28
W29
W30
W8
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y30

a

a

HT33

HT33
HT34

HT34

1

HT35

HT35

1

TPC26b

TPC26b

HT36

HT36

1

TPC26b

TPC26b

HT37

HT37

1

TPC26b

TPC26b

HT38

HT38

1

TPC26b

TPC26b

1

TPC26b

TPC26b
TPC26b

TPC26b

r

r

t

t

CPU_TP_ D1
CPU_TP _D14
CPU_TP_ E5
CPU_TP_ E6
CPU_TP _F23
CPU_TP_ J3

o

o

GND

I

I

XU1G

XU1G

SOCKET77 5/ATX

SOCKET77 5/ATX

AF28

VSS1

AF27

VSS2

AF26

VSS3

AF25

VSS4

AF24

VSS5

AF23

VSS6

AF20

VSS7

AF17

VSS8

AF16

VSS9

AF13

VSS10

AF10

VSS11

AE7

VSS12

AE5

VSS13

AE30

VSS14

AE29

VSS15

AE28

VSS16

AE27

VSS17

AE26

VSS18

AE25

VSS19

AE24

VSS20

AE20

VSS21

AE2

VSS22

AE17

VSS23

AE16

VSS24

AE13

VSS25

AE10

VSS26

AD7

VSS27

AD4

VSS28

AC7

VSS29

AC3

VSS30

AC6

VSS31

AB7

VSS32

AB30

VSS33

AB29

VSS34

AB28

VSS35

AB27

VSS36

AB26

VSS37

AB25

VSS38

AB24

VSS39

AB23

VSS40

AB1

VSS41

AA7

VSS42

AA6

VSS43

AA30

VSS44

AA3

VSS45

AA29

VSS46

AA28

VSS47

AA27

VSS48

AA26

VSS49

AA25

VSS50

A12

VSS51

A15

VSS52

A18

VSS53

A2

VSS54

A21

VSS55

A6

VSS56

A9

VSS57

n

n

AA23

VSS58

AA24

VSS59

AF29

VSS60

D1

RSVD27

D14

RSVD28

E5

RSVD29

E6

RSVD30

F23

RSVD37

J3

RSVD32

C

C

REV=1.3

REV=1.3

VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140

AF3
AF30
AF6
AF7
AG10
AG13
AG16
AG17
AG20
AG23
AG24
AG7
AH1
AH10
AH13
AH16
AH17
AH20
AH23
AH24
AH3
AH6
AJ10
AJ13
AJ16
AJ17
AJ20
AJ23
AJ24
AJ27
AJ28
AJ29
AJ30
AJ4
AK10
AK13
AK16
AK17
AK2
AK20
AK23
AK24
AK27
AK28
AK29
AK30

o

o

AK5
AK7
AL10
AL13
AL16
AL17
AL20
AL23
AL24
AL27
AL28
AM1
AM10
AM13
AM16
AM17
AM20
AM23
AM24
AM27
AM28
AM4
AN1
AN10
AN13
AN16
AN17
AN2
AN20
AN23
AN24
AN27
AN28
B1

n

n

GND

f

f

GND

B11
B14
B17
B20
B24

B5

B8
C10
C13
C16
C19
C22
C24

C4

C7
D12
D15
D18
D21
D24

D3

D5

D6

D9
E11
E14
E17

E2
E20
E25
E26
E27
E28

E8
F10

i

i

F13
F16
F19
F22

F4

F7
H10
H11
H12
H13
H14
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28

H3

H6

I

I

XU1H

XU1H

SOCKET77 5/ATX

SOCKET77 5/ATX

VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172

d

d

VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200

REV=1.3

REV=1.3

VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228

e

e

VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265

Y7
Y5
Y2
W7
W4
V7
V6
V30
V3
V29
V28
V27
V26
V25
V24
V23
U7
T7
T6
T3
R7
R5
R30
R29
R28

n

n

R27
R26
R25
R24
R23
R2
P7
P4
P30
P29
P28
P27
P26
P25
P24
P23
N7
N6
N3
M7
M1
L7
L6
L30
L3
L29
L28
L27
L26
L25
L24
L23
K7
K5
K2
J7
J4
H9
H8
H7

t

t

i

i

GND

a

a

l

l

I

I

XU1I

XU1I

SOCKET77 5/ATX

SOCKET77 5/ATX

1

RM_POST_NC1

2

RM_POST_NC2

3

RM_POST_NC3

4

RM_POST_NC4

REV=1.3

REV=1.3

PEGATRON DT-MB RESTRICTED SECRET

INTEL LGA-775 3 - 3

INTEL LGA-775 3 - 3

INTEL LGA-775 3 - 3

Title :

Title :

Title :

Engineer:

Engineer:

PEGATRON CORP.

PEGATRON CORP.

PEGATRON CORP.

Size Pr oject Name

Size Pr oject Name

Size Pr oject Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

IPX41-D3

IPX41-D3

IPX41-D3

1

Ttepic Zhu

Ttepic Zhu

Ttepic Zhu

9 54Thursday, December 10, 2009

9 54Thursday, December 10, 2009

9 54Thursday, December 10, 2009

Rev

Rev

Rev

1.02

1.02

1.02

5

I

I

NU1A

AA35

AA37
AA36

H39

N39
N35
N37

N40
M45
R35

R36
R34
R37
R39
U38

U34
U40

Y36
U35

U37
Y37
Y34
Y38

G38
K35

C43
G39

C39
B39
B40

K31

K25

C32
D32
D30

G44
K44
H45
H40

H37
H42

G43

G42

D27

P30
P29

N25

L36
L37
J38
F40

L38
L43

J41

T36

T37

T34

J39

J40
T39

J31
F33

J25

F26

J42
L40
J43

L42
J44

L44

NU1A

FSB_AB_3
FSB_AB_4
FSB_AB_5
FSB_AB_6
FSB_AB_7
FSB_AB_8
FSB_AB_9
FSB_AB_10
FSB_AB_11
FSB_AB_12
FSB_AB_13
FSB_AB_14
FSB_AB_15
FSB_AB_16
FSB_AB_17
FSB_AB_18
FSB_AB_19
FSB_AB_20
FSB_AB_21
FSB_AB_22
FSB_AB_23
FSB_AB_24
FSB_AB_25
FSB_AB_26
FSB_AB_27
FSB_AB_28
FSB_AB_29
FSB_AB_30
FSB_AB_31
FSB_AB_32
FSB_AB_33
FSB_AB_34
FSB_AB_35

FSB_REQB_0
FSB_REQB_1
FSB_REQB_2
FSB_REQB_3
FSB_REQB_4

FSB_ADSTBB_0
FSB_ADSTBB_1

FSB_DSTBPB_0
FSB_DSTBNB_0
FSB_DINVB_0

FSB_DSTBPB_1
FSB_DSTBNB_1
FSB_DINVB_1

FSB_DSTBPB_2
FSB_DSTBNB_2
FSB_DINVB_2

FSB_DSTBPB_3
FSB_DSTBNB_3
FSB_DINVB_3

FSB_ADSB
FSB_TRDYB
FSB_DRDYB
FSB_DEFERB
FSB_HITMB
FSB_HITB
FSB_LOCKB
FSB_BREQ0B
FSB_BNRB
FSB_BPRIB
FSB_DBSYB

FSB_RSB_0
FSB_RSB_1
FSB_RSB_2

FSB_CPURSTB

P

P

HPL_CLKINN
HPL_CLKINP

RSVD21

EAGLELA KE

EAGLELA KE

FSB

FSB

REV=1.4

REV=1.4

FSB_DB_0
FSB_DB_1
FSB_DB_2
FSB_DB_3
FSB_DB_4
FSB_DB_5
FSB_DB_6
FSB_DB_7
FSB_DB_8

FSB_DB_9
FSB_DB_10
FSB_DB_11
FSB_DB_12
FSB_DB_13
FSB_DB_14
FSB_DB_15
FSB_DB_16
FSB_DB_17
FSB_DB_18
FSB_DB_19
FSB_DB_20
FSB_DB_21
FSB_DB_22
FSB_DB_23
FSB_DB_24
FSB_DB_25
FSB_DB_26
FSB_DB_27
FSB_DB_28
FSB_DB_29
FSB_DB_30
FSB_DB_31
FSB_DB_32
FSB_DB_33
FSB_DB_34
FSB_DB_35
FSB_DB_36
FSB_DB_37
FSB_DB_38
FSB_DB_39
FSB_DB_40
FSB_DB_41
FSB_DB_42
FSB_DB_43
FSB_DB_44
FSB_DB_45
FSB_DB_46
FSB_DB_47
FSB_DB_48
FSB_DB_49
FSB_DB_50
FSB_DB_51
FSB_DB_52
FSB_DB_53
FSB_DB_54
FSB_DB_55
FSB_DB_56
FSB_DB_57
FSB_DB_58
FSB_DB_59
FSB_DB_60
FSB_DB_61
FSB_DB_62
FSB_DB_63

FSB_SWING

FSB_RCOMP

e

e

FSB_DVREF

FSB_ACCVREF

HA#[3..35][ 7] HD#[0..63] [7]

D D

C C

HREQ#[0..4][7]

HADSTB0#[7]
HADSTB1#[7]

HDSTBP0#[7]
HDSTBN0 #[7]
HDBI0#[7]

HDSTBP1#[7]
HDSTBN1 #[7]
HDBI1#[7]

HDSTBP2#[7]
HDSTBN2 #[7]
HDBI2#[7]

HDSTBP3#[7]
HDSTBN3 #[7]
HDBI3#[7]

B B

A A

HRS#[0..2][7]

CPURES ET#[7]

MCHHCL K#[6]
MCHHCL K[6]

NOBOM

NOBOM

HADS#[7]
HTRDY#[7]
HDRDY#[7]
HDEFER#[7]
HITM#[7]
HIT#[7]
HLOCK#[7]
HBREQ0#[7]
HBNR#[7]
HBPRI#[7]
HDBSY#[7]

NT3

NT3

1

TPC26b

TPC26b

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HA#32
HA#33
HA#34
HA#35

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

HRS#0
HRS#1
HRS#2

TP_MCH_ N25

5

4

F44
C44
D44
C41
E43
B43
D40
B42
B38
F38
A38
B37
D38
C37
D37
B36
E37
J35
H35
F37
G37
J33
L33
G33
L31
M31
M30
J30
G31
K30
M29
G30
J29
F29
H29
L25
K26
L29
J26
M26
H26
F25
F24
G25
H24
L24
J24
N24
C28
B31
F35
C35
B35
D35
D31
A34
B32
F31
D28
A29
C30
B30
E27
B28

B24

A23

g

g

C22
B23

4

3

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

HXSW ING

HXRCOM P

a

a

MCH_GT LREF0

r

r

t

t

12

I

I

NR5

NR5

16.5

16.5

1%

1%

GND

12

NI

NI

NCB2

NCB2
220PF/5 0V

220PF/5 0V

X7R 10%

X7R 10%

GND GND GND

MCH_GTL REF0 W/S =10/7

MCH_GTL REF0 W/S =10/7

MCH_GTL REF0 W/S =10/7MCH_GTL REF0 W/S =10/7

1

SDVO_CTRL_DATA

1

SDVO CARD PRESENT, PEG DISABLE

0

SDVO DISABLE(DEFAULT)

0

n

n

12

GND

12

HXSW ING_R

I

I

NCB1

NCB1

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%

R_MCH_G TLREF0

I

I

NCB3

NCB3
1UF/16V

1UF/16V

X7R 10%

X7R 10%
mx_c0603

mx_c0603

HXSWING W/S=10/ 10

HXSWING W/S=10/ 10

HXSWING W/S=10/ 10HXSWING W/S=10/ 10

HXRCOMP W/S=10/ 7

HXRCOMP W/S=10/ 7

HXRCOMP W/S=10/ 7HXRCOMP W/S=10/ 7

I

I

NR4

NR4
51

51

o

o

12

I

I

NR8

NR8
51

51

12

C

C

+1P1V_FS B_VTT

3

NT43 T PC26b

NT43 T PC26b

NT42 TPC 26b

NT42 TPC 26b

NOBOM

NOBOM
NOBOM

NOBOM

o

o

12

I

I

NR3

NR3
301

301

1%

1%

12

I

I

NR6

NR6
100

100

1%

1%

GND

CK_100M _MCH[6]
CK_100M_ MCH#[ 6]

NOBOM

NOBOM

NOBOM

NOBOM

n

n

+1P1V_FS B_VTT

12

I

I

NR7

NR7

57.6

57.6

1%

1%

12

I

I

NR9

NR9
100

100

1%

1%

TPC26b

TPC26b
TPC26b

TPC26b

EXP_RXP0[25]
EXP_RXN0[25]
EXP_RXP1[25]
EXP_RXN1[25]
EXP_RXP2[25]
EXP_RXN2[25]
EXP_RXP3[25]
EXP_RXN3[25]
EXP_RXP4[25]
EXP_RXN4[25]
EXP_RXP5[25]
EXP_RXN5[25]
EXP_RXP6[25]
EXP_RXN6[25]
EXP_RXP7[28]
EXP_RXN7[28]
EXP_RXP8[25]
EXP_RXN8[25]
EXP_RXP9[25]
EXP_RXN9[25]
EXP_RXP 10[25]
EXP_RXN 10[25]
EXP_RXP 11[25]
EXP_RXN 11[25]
EXP_RXP 12[25]
EXP_RXN 12[25]
EXP_RXP 13[25]
EXP_RXN 13[25]
EXP_RXP 14[25]
EXP_RXN 14[25]
EXP_RXP 15[25]
EXP_RXN 15[25]

DMI_RXP0[20]
DMI_RXN0[20]
DMI_RXP1[20]
DMI_RXN1[20]
DMI_RXP2[20]
DMI_RXN2[20]
DMI_RXP3[20]
DMI_RXN3[20]

NT1

NT1
NT2

NT2

1
1

f

f

TP_SDVO_ DATA

1

TP_SDVO _CLK

1

TP_MCH_ AD13

i

i

D9
E9

J13

G13

AB13
AD13

F6

G7

H6

G4

J6
J7
L6
L7

N9

N10

N7
N6
R7
R6

R9
R10
U10

U9

U6

d

d

U7
AA9

AA10

R4

P4
AA7
AA6

AB10

AB9
AB3
AA2

AD10
AD11

AD7
AD8
AE9

AE10

AE6
AE7
AF9
AF8

2

I

I

NU1B

NU1B

EXP_CLKP
EXP_CLKN

SDVO_CTRLDATA
SDVO_CTRLCLK

RSVD2
RSVD4

PEG_RXP_0
PEG_RXN_0
PEG_RXP_1
PEG_RXN_1
PEG_RXP_2
PEG_RXN_2
PEG_RXP_3
PEG_RXN_3
PEG_RXP_4
PEG_RXN_4
PEG_RXP_5

n

n

PEG_RXN_5
PEG_RXP_6
PEG_RXN_6
PEG_RXP_7

e

e

PEG_RXN_7
PEG_RXP_8
PEG_RXN_8
PEG_RXP_9
PEG_RXN_9
PEG_RXP_10
PEG_RXN_10
PEG_RXP_11
PEG_RXN_11
PEG_RXP_12
PEG_RXN_12
PEG_RXP_13
PEG_RXN_13
PEG_RXP_14
PEG_RXN_14
PEG_RXP_15
PEG_RXN_15

DMI_RXP_0
DMI_RXN_0
DMI_RXP_1
DMI_RXN_1
DMI_RXP_2
DMI_RXN_2
DMI_RXP_3
DMI_RXN_3

EAGLELA KE

EAGLELA KE

2

SDVO

SDVO

PCIE

PCIE

DMI

DMI

REV=1.4

REV=1.4

EXP_RCOMPO

EXP_COMPI

EXP_ICOMPO

EXP_RBIAS

PEG_TXP_0
PEG_TXN_0
PEG_TXP_1
PEG_TXN_1
PEG_TXP_2

i

i

PEG_TXN_2
PEG_TXP_3

t

t

PEG_TXN_3
PEG_TXP_4
PEG_TXN_4
PEG_TXP_5
PEG_TXN_5
PEG_TXP_6
PEG_TXN_6
PEG_TXP_7
PEG_TXN_7
PEG_TXP_8
PEG_TXN_8
PEG_TXP_9

PEG_TXN_9
PEG_TXP_10
PEG_TXN_10
PEG_TXP_11
PEG_TXN_11
PEG_TXP_12
PEG_TXN_12
PEG_TXP_13
PEG_TXN_13
PEG_TXP_14
PEG_TXN_14
PEG_TXP_15
PEG_TXN_15

DMI_TXP_0
DMI_TXN_0
DMI_TXP_1
DMI_TXN_1
DMI_TXP_2
DMI_TXN_2
DMI_TXP_3
DMI_TXN_3

1

+1P1V_C ORE

12

I

I

NR1

NR1

49.9

49.9

1%

1%

l

l

12

NOTE:

Breakout W/S:10/6
W/S:10/10

I

I

NR2

NR2
750

750

1%

1%

EXP_TX P0 [ 25]
EXP_TX N0 [25]
EXP_TX P1 [ 25]
EXP_TX N1 [25]
EXP_TX P2 [ 25]
EXP_TX N2 [25]
EXP_TX P3 [ 25]
EXP_TX N3 [25]
EXP_TX P4 [ 28]
EXP_TX N4 [28]
EXP_TX P5 [ 28]
EXP_TX N5 [28]
EXP_TX P6 [ 28]
EXP_TX N6 [28]
EXP_TX P7 [ 28]
EXP_TX N7 [28]
EXP_TX P8 [ 25]
EXP_TX N8 [25]
EXP_TX P9 [ 25]
EXP_TX N9 [25]
EXP_TXP 10 [25]
EXP_TXN 10 [25]
EXP_TXP 11 [25]
EXP_TXN 11 [25]
EXP_TXP 12 [25]
EXP_TXN 12 [25]
EXP_TXP 13 [25]
EXP_TXN 13 [25]
EXP_TXP 14 [25]
EXP_TXN 14 [25]
EXP_TXP 15 [25]
EXP_TXN 15 [25]

DMI_TXP0 [20]
DMI_TXN0 [20]
DMI_TXP1 [20]
DMI_TXN1 [20]
DMI_TXP2 [20]
DMI_TXN2 [20]
DMI_TXP3 [20]
DMI_TXN3 [20]

EXP_RCO MP

Y7
Y8
Y6

EXP_RBIA STP_MCH_ AB13

AG1

GND

C11
B11
A10

a

a

B9
C9
D8
B8
C7
B7
B6
B3
B4
D2
C2
H2
G2
J2
K2
K1
L2
P2
M2
T2
R1
U2
V2
W4
V3
AA4
Y4
AC1
AB2

NOTE:

Check Eaglelake PDG for detai if wanna
support Integrated HDMI/DVI/DP

AC2
AD2
AD4
AE4
AE2
AF2
AF4
AG4

PEGATRON DT-MB RESTRICTED SECRET

Title :

Title :

Title :

EAGLELAKE 1- 7

EAGLELAKE 1- 7

EAGLELAKE 1- 7

Engineer:

Engineer:

PEGATRON CORP.

PEGATRON CORP.

PEGATRON CORP.

Size Pr oject Name

Size Pr oject Name

Size Pr oject Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

Engineer:

IPX41-D3

IPX41-D3

IPX41-D3

1

Ttepic Zhu

Ttepic Zhu

Ttepic Zhu

10 54Thursday, December 10, 2009

10 54Thursday, December 10, 2009

10 54Thursday, December 10, 2009

Rev

Rev

Rev

1.02

1.02

1.02

5

M_CHA_MAA [1..14][17]

D D

M_CHA_C AS#[17]
M_CHA_R AS#[17]

M_CHA_B A0[17]
M_CHA_B A1[17]
M_CHA_B A2[17]

M_CHA_C S#0[1 7]

NOBOM

NOBOM

M_CHA_C KE0[17]
M_CHA_C KE1[17]

M_CHA_O DT0[17]
M_CHA_O DT1[17]

NOBOM

C C

B B

P

P

A A

5

NOBOM

M_CHA_C LK0[1 7]
M_CHA_C LK0#[17]

M_CHA_C LK2[1 7]
M_CHA_C LK2#[17]

NOBOM

NOBOM
NOBOM

NOBOM

NOBOM

NOBOM
NOBOM

NOBOM
NOBOM

NOBOM

e

e

4

HT49

HT49

1

HT48

HT48

1

HT45

HT45

1

HT47

HT47

1

HT46

HT46

1

HT40

HT40

1

HT41

HT41

1

g

g

4

M_CHA_M AA1
M_CHA_M AA2
M_CHA_M AA3
M_CHA_M AA4
M_CHA_M AA5
M_CHA_M AA6
M_CHA_M AA7
M_CHA_M AA8
M_CHA_M AA9
M_CHA_M AA10
M_CHA_M AA11
M_CHA_M AA12
M_CHA_M AA13
M_CHA_M AA14

N27146 510

N27146 424

N27146 426
N27146 514

N27146 515
N27146 428
N27146 516

a

a

t

t

r

r

I

I

NU1C

NU1C

BC41

DDR_A_MA_0

BC35

DDR_A_MA_1

BB32

DDR_A_MA_2

BC32

DDR_A_MA_3

BD32

DDR_A_MA_4

BB31

DDR_A_MA_5

AY31

DDR_A_MA_6

BA31

DDR_A_MA_7

BD31

DDR_A_MA_8

BD30

DDR_A_MA_9

AW43

DDR_A_MA_10

BC30

DDR_A_MA_11

BB30

DDR_A_MA_12

AM42

DDR_A_MA_13

BD28

DDR_A_MA_14

AW42

DDR_A_WEB

AU42

DDR_A_CASB

AV42

DDR_A_RASB

AV45

DDR_A_BS_0

AY44

DDR_A_BS_1

BC28

DDR_A_BS_2

AU43

DDR_A_CSB_0

AR40

DDR_A_CSB_1

AU44

DDR_A_CSB_2

AM43

DDR_A_CSB_3

BB27

DDR_A_CKE_0

BD27

DDR_A_CKE_1

BA27

DDR_A_CKE_2

AY26

DDR_A_CKE_3

AR42

DDR_A_ODT_0

AM44

DDR_A_ODT_1

AR44

DDR_A_ODT_2

AL40

DDR_A_ODT_3

AY37

DDR_A_CK_0

BA37

DDR_A_CKB_0

AW29

DDR_A_CK_1

AY29

DDR_A_CKB_1

AU37

DDR_A_CK_2

AV37

DDR_A_CKB_2

AU33

DDR_A_CK_3

AT33

DDR_A_CKB_3

AT30

DDR_A_CK_4

AR30

DDR_A_CKB_4

AW38

DDR_A_CK_5

AY38

DDR_A_CKB_5

o

o

EAGLELA KE

EAGLELA KE

DDR_A

DDR_A

n

n

REV=1.4

REV=1.4

DDR_A_DQS_0

DDR_A_DQSB_0

DDR_A_DM_0

DDR_A_DQ_0
DDR_A_DQ_1
DDR_A_DQ_2
DDR_A_DQ_3
DDR_A_DQ_4
DDR_A_DQ_5
DDR_A_DQ_6
DDR_A_DQ_7

DDR_A_DQS_1

DDR_A_DQSB_1

DDR_A_DM_1

DDR_A_DQ_8

DDR_A_DQ_9
DDR_A_DQ_10
DDR_A_DQ_11
DDR_A_DQ_12
DDR_A_DQ_13
DDR_A_DQ_14
DDR_A_DQ_15

DDR_A_DQS_2

DDR_A_DQSB_2

DDR_A_DM_2

DDR_A_DQ_16
DDR_A_DQ_17
DDR_A_DQ_18
DDR_A_DQ_19
DDR_A_DQ_20
DDR_A_DQ_21
DDR_A_DQ_22
DDR_A_DQ_23

DDR_A_DQS_3

DDR_A_DQSB_3

DDR_A_DM_3

DDR_A_DQ_24
DDR_A_DQ_25
DDR_A_DQ_26
DDR_A_DQ_27
DDR_A_DQ_28
DDR_A_DQ_29
DDR_A_DQ_30
DDR_A_DQ_31

DDR_A_DQS_4

DDR_A_DQSB_4

DDR_A_DM_4

DDR_A_DQ_32
DDR_A_DQ_33
DDR_A_DQ_34
DDR_A_DQ_35

C

C

DDR_A_DQ_36
DDR_A_DQ_37
DDR_A_DQ_38
DDR_A_DQ_39

DDR_A_DQS_5

DDR_A_DQSB_5

DDR_A_DM_5

DDR_A_DQ_40
DDR_A_DQ_41
DDR_A_DQ_42
DDR_A_DQ_43
DDR_A_DQ_44
DDR_A_DQ_45
DDR_A_DQ_46
DDR_A_DQ_47

DDR_A_DQS_6

DDR_A_DQSB_6

DDR_A_DM_6

DDR_A_DQ_48
DDR_A_DQ_49
DDR_A_DQ_50
DDR_A_DQ_51
DDR_A_DQ_52
DDR_A_DQ_53
DDR_A_DQ_54
DDR_A_DQ_55

DDR_A_DQS_7

DDR_A_DQSB_7

DDR_A_DM_7

DDR_A_DQ_56
DDR_A_DQ_57
DDR_A_DQ_58
DDR_A_DQ_59
DDR_A_DQ_60
DDR_A_DQ_61
DDR_A_DQ_62
DDR_A_DQ_63

3

BC5
BD4
BC3

BC2
BD3
BD7
BB7
BB2
BA3
BE6
BD6

BB9
BC9
BD9

BB8
AY8
BD11
BB11
BC7
BE8
BD10
AY11

BD15
BB15
BD14

BB14
BC14
BC16
BB16
BC11
BE12
BA15
BD16

AR22
AT22
AV22

AW21
AY22
AV24
AY24
AU21
AT21
AR24
AU24

AH43
AH42
AK42

AL41
AK43
AG42
AG44
AL42
AK44
AH44
AG41

AD43
AE42
AE45

AF43
AF42
AC44
AC42
AF40
AF44
AD44
AC41

Y43
Y42
AA45

AB43
AA42
W42
W41
AB42
AB44
Y44
Y40

T44
T43
T42

V42
U45
R40
P44
V44
V43
R41
R44

3

M_CHA_D Q0
M_CHA_D Q1
M_CHA_D Q2
M_CHA_D Q3
M_CHA_D Q4
M_CHA_D Q5
M_CHA_D Q6
M_CHA_D Q7

M_CHA_D Q8
M_CHA_D Q9
M_CHA_D Q10
M_CHA_D Q11
M_CHA_D Q12
M_CHA_D Q13
M_CHA_D Q14
M_CHA_D Q15

M_CHA_D Q16
M_CHA_D Q17
M_CHA_D Q18
M_CHA_D Q19
M_CHA_D Q20
M_CHA_D Q21
M_CHA_D Q22
M_CHA_D Q23

M_CHA_D Q24
M_CHA_D Q25
M_CHA_D Q26
M_CHA_D Q27
M_CHA_D Q28
M_CHA_D Q29
M_CHA_D Q30
M_CHA_D Q31

o

o

M_CHA_D Q32
M_CHA_D Q33
M_CHA_D Q34
M_CHA_D Q35
M_CHA_D Q36
M_CHA_D Q37
M_CHA_D Q38
M_CHA_D Q39

M_CHA_D Q40
M_CHA_D Q41
M_CHA_D Q42
M_CHA_D Q43
M_CHA_D Q44
M_CHA_D Q45
M_CHA_D Q46
M_CHA_D Q47

M_CHA_D Q48
M_CHA_D Q49
M_CHA_D Q50
M_CHA_D Q51
M_CHA_D Q52
M_CHA_D Q53
M_CHA_D Q54
M_CHA_D Q55

M_CHA_D Q56
M_CHA_D Q57
M_CHA_D Q58
M_CHA_D Q59
M_CHA_D Q60
M_CHA_D Q61
M_CHA_D Q62
M_CHA_D Q63

n

n

f

f

M_CHA_D QS0 [17]
M_CHA_D QS0# [17]
M_CHA_D M0 [17]

M_CHA_D QS1 [17]
M_CHA_D QS1# [17]
M_CHA_D M1 [17]

M_CHA_D QS2 [17]
M_CHA_D QS2# [17]
M_CHA_D M2 [17]

M_CHA_D QS3 [17]
M_CHA_D QS3# [17]

d

d

M_CHA_D M3 [17]

i

i

M_CHA_D QS4 [17]
M_CHA_D QS4# [17]
M_CHA_D M4 [17]

M_CHA_D QS5 [17]
M_CHA_D QS5# [17]
M_CHA_D M5 [17]

M_CHA_D QS6 [17]
M_CHA_D QS6# [17]
M_CHA_D M6 [17]

M_CHA_D QS7 [17]
M_CHA_D QS7# [17]
M_CHA_D M7 [17]

2

e

e

2

n

n

M_CHA_DQ[ 0..63] [17]

l

l

a

a

i

i

t

t

PEGATRON DT-MB RESTRICTED SECRET

PEGATRON CORP.

PEGATRON CORP.

PEGATRON CORP.

Size Pr oject Name

Size Pr oject Name

Size Pr oject Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

IPX41-D3

IPX41-D3

IPX41-D3

1

EAGELLAKE 2 - 7

EAGELLAKE 2 - 7

EAGELLAKE 2 - 7

Ttepic Zhu

Ttepic Zhu

Ttepic Zhu

11 54Thursday, December 10, 2009

11 54Thursday, December 10, 2009

11 54Thursday, December 10, 2009

Rev

Rev

Rev

1.02

1.02

1.02

5

M_CHB_MAA [0..14][18]

D D

C C

DDR_REF NEED RO UTING
Width/Spacing: 12/12 mils

+1P5V_D UAL

DDR3_DR AM_PWRO K[19]

e

e

I

I

NCB4

NCB4

0.1UF/16V

0.1UF/16V

12

I

I

NR11

NR11
1K

1K

1%

1%

12

I

I

NR12

NR12
1K

1K

1%

1%

GND GND

5

12

I

I

NCB5

NCB5

0.1UF/16V

0.1UF/16V

090420 add by TSL

12

I

I

NCB115

NCB115
1UF/10V

1UF/10V

mx_c0603

mx_c0603

GND

P

P

12

B B

GND

MCH_DDR_RPU, MC H_DDR_RPD, MCH_DDR_SPU, MCH_DDR_SPD

NEED ROUTING LE SS THEN 1000MIL LEN GTH.

WIDTH/SPACING = 10/10 MIL

A A

4

M_CHB_W E#[18]
M_CHB_C AS#[18]
M_CHB_R AS#[18]

M_CHB_B A0[18]
M_CHB_B A1[18]
M_CHB_B A2[18]

M_CHB_C S#0[1 8]
M_CHB_C S#1[1 8]

M_CHB_C KE0[18]
M_CHB_C KE1[18]

M_CHB_O DT0[18]
M_CHB_O DT1[18]

M_CHB_C LK0[1 8]
M_CHB_C LK0#[18]

M_CHB_C LK2[1 8]
M_CHB_C LK2#[18]

M_CHA_C S#1[1 7]
M_CHA_M AA0[17]

M_CHA_W E#[17]

DDR3_DR AMRST#[17,18]

+1P5V_D UAL

12

g

g

GND

+1P5V_D UAL

12

GND GND

NOBOM

NOBOM

NOBOM

NOBOM
NOBOM

NOBOM

NOBOM

NOBOM

NOBOM

NOBOM
NOBOM

NOBOM

NOBOM

NOBOM
NOBOM

NOBOM
NOBOM

NOBOM
NOBOM

NOBOM

NOBOM

NOBOM

NOBOM

NOBOM
NOBOM

NOBOM

I

I

NCB6

NCB6

0.1UF/16V

0.1UF/16V

I

I

NCB7

NCB7

0.1UF/16V

0.1UF/16V

4

1

1
1

1

1
1

1
1
1
1

1

1
1

I

I

NR13

NR13

1 2

a

a

80.6

80.6

1%

1%

I

I

NR15

NR15

1 2

80.6

80.6

1%

1%

3

I

I

NU1D

NU1D

M_CHB_M AA0
M_CHB_M AA1
M_CHB_M AA2
M_CHB_M AA3
M_CHB_M AA4
M_CHB_M AA5
M_CHB_M AA6
M_CHB_M AA7
M_CHB_M AA8
M_CHB_M AA9
M_CHB_M AA10
M_CHB_M AA11
M_CHB_M AA12
M_CHB_M AA13
M_CHB_M AA14

N27146 430

HT53

HT53

N27146 431

HT55

HT55

N27146 432

HT58

HT58

N27146 434

HT61

HT61

N27146 435

HT50

HT50

N27146 436

HT54

HT54

N27146 437

HT57

HT57

N27146 438

HT60

HT60

N27146 439

HT62

HT62

N27146 440

HT51

HT51

N27146 442

HT59

HT59

N27146 445

HT52

HT52

N27146 446

HT56

HT56

DDR_VRE F M_CHB_D Q40

o

o

r

r

t

t

MCH_DD R_RPU
MCH_DD R_RPD

12

I

I

NR17

NR17

80.6

80.6

1%

1%

GND

MCH_DD R_SPU
MCH_DD R_SPD

12

I

I

NR16

NR16
249

249

1%

1%

BD24

DDR_B_MA_0

BB23

DDR_B_MA_1

BB24

DDR_B_MA_2

BD23

DDR_B_MA_3

BB22

DDR_B_MA_4

BD22

DDR_B_MA_5

BC22

DDR_B_MA_6

BC20

DDR_B_MA_7

BB20

DDR_B_MA_8

BD20

DDR_B_MA_9

BC26

DDR_B_MA_10

BD19

DDR_B_MA_11

BB19

DDR_B_MA_12

BE38

DDR_B_MA_13

BA19

DDR_B_MA_14

BD36

DDR_B_WEB

BC37

DDR_B_CASB

BD35

DDR_B_RASB

BD26

DDR_B_BS_0

BB26

DDR_B_BS_1

BD18

DDR_B_BS_2

BB35

DDR_B_CSB_0

BD39

DDR_B_CSB_1

BB37

DDR_B_CSB_2

BD40

DDR_B_CSB_3

BC18

DDR_B_CKE_0

AY20

DDR_B_CKE_1

BE17

DDR_B_CKE_2

BB18

DDR_B_CKE_3

BD37

DDR_B_ODT_0

BC39

DDR_B_ODT_1

BB38

DDR_B_ODT_2

BD42

DDR_B_ODT_3

AY33

DDR_B_CK_0

AW33

DDR_B_CKB_0

AV31

DDR_B_CK_1

AW31

DDR_B_CKB_1

AW35

DDR_B_CK_2

AY35

DDR_B_CKB_2

AT31

DDR_B_CK_3

AU31

DDR_B_CKB_3

AP31

DDR_B_CK_4

AP30

DDR_B_CKB_4

AW37

DDR_B_CK_5

AV35

DDR_B_CKB_5

AR43

DDR3_A_CSB1

BB40

DDR3_A_MA0

AT44

DDR3_A_WEB

AV40

DDR3_B_ODT3

AR6

DDR3_DRAM_PWROK

BC24

DDR3_DRAMRSTB

AN29

RSVD7

n

n

AN30

RSVD8

AJ33

RSVD5

AK33

RSVD6

BB44

DDR_VREF

BA43

DDR_RPU

AY42

DDR_RPD

BC44

DDR_SPU

BC43

DDR_SPD

DDR_B

DDR_B

EAGLELA KE

EAGLELA KE

C

C

REV=1.4

REV=1.4

DDR_B_DQSB_0

DDR_B_DQSB_1

DDR_B_DQSB_2

DDR_B_DQSB_3

DDR_B_DQSB_4

DDR_B_DQSB_5

DDR_B_DQSB_6

DDR_B_DQSB_7

3

DDR_B_DQS_0

DDR_B_DM_0

DDR_B_DQ_0
DDR_B_DQ_1
DDR_B_DQ_2
DDR_B_DQ_3
DDR_B_DQ_4
DDR_B_DQ_5
DDR_B_DQ_6
DDR_B_DQ_7

DDR_B_DQS_1

DDR_B_DM_1

DDR_B_DQ_8

DDR_B_DQ_9
DDR_B_DQ_10
DDR_B_DQ_11
DDR_B_DQ_12
DDR_B_DQ_13
DDR_B_DQ_14
DDR_B_DQ_15

DDR_B_DQS_2

DDR_B_DM_2

DDR_B_DQ_16
DDR_B_DQ_17
DDR_B_DQ_18
DDR_B_DQ_19
DDR_B_DQ_20
DDR_B_DQ_21
DDR_B_DQ_22
DDR_B_DQ_23

DDR_B_DQS_3

DDR_B_DM_3

DDR_B_DQ_24
DDR_B_DQ_25
DDR_B_DQ_26
DDR_B_DQ_27
DDR_B_DQ_28
DDR_B_DQ_29
DDR_B_DQ_30
DDR_B_DQ_31

DDR_B_DQS_4

o

o

DDR_B_DM_4

DDR_B_DQ_32
DDR_B_DQ_33
DDR_B_DQ_34
DDR_B_DQ_35
DDR_B_DQ_36
DDR_B_DQ_37
DDR_B_DQ_38
DDR_B_DQ_39

DDR_B_DQS_5

DDR_B_DM_5

DDR_B_DQ_40
DDR_B_DQ_41
DDR_B_DQ_42
DDR_B_DQ_43
DDR_B_DQ_44
DDR_B_DQ_45
DDR_B_DQ_46
DDR_B_DQ_47

DDR_B_DQS_6

DDR_B_DM_6

DDR_B_DQ_48
DDR_B_DQ_49
DDR_B_DQ_50
DDR_B_DQ_51
DDR_B_DQ_52
DDR_B_DQ_53
DDR_B_DQ_54
DDR_B_DQ_55

DDR_B_DQS_7

DDR_B_DM_7

DDR_B_DQ_56
DDR_B_DQ_57
DDR_B_DQ_58
DDR_B_DQ_59
DDR_B_DQ_60
DDR_B_DQ_61
DDR_B_DQ_62
DDR_B_DQ_63

AW8
AW9
AY6

M_CHB_D Q0

AV7

M_CHB_D Q1

AW4

M_CHB_D Q2

BA9

M_CHB_D Q3

AU11

M_CHB_D Q4

AU7

M_CHB_D Q5

AU8

M_CHB_D Q6

AW7

M_CHB_D Q7

AY9

AT15
AU15
AR15

M_CHB_D Q8

AY13

M_CHB_D Q9

AP15

M_CHB_D Q10

AW15

M_CHB_D Q11

AT16

M_CHB_D Q12

AU13

M_CHB_D Q13

AW13

M_CHB_D Q14

AP16

M_CHB_D Q15

AU16

AR20
AR17
AU17

M_CHB_D Q16

AY17

M_CHB_D Q17

AV17

M_CHB_D Q18

AR21

M_CHB_D Q19

AV20

M_CHB_D Q20

AP17

M_CHB_D Q21

AW16

M_CHB_D Q22

AT20

M_CHB_D Q23

AN20

AU26
AT26
AV25

M_CHB_D Q24

AT25

M_CHB_D Q25

AV26

M_CHB_D Q26

AU29

M_CHB_D Q27

AV29

M_CHB_D Q28

AW25

M_CHB_D Q29

AR25

M_CHB_D Q30

n

n

AP26

M_CHB_D Q31

AR29

AR38
AR37
AU39

M_CHB_D Q32

AR36

M_CHB_D Q33

AU38

M_CHB_D Q34

AN35

M_CHB_D Q35

AN37

M_CHB_D Q36

AV39

M_CHB_D Q37

AW39

M_CHB_D Q38

AU40

M_CHB_D Q39

AU41

AK34
AL34
AL37

AL35

M_CHB_D Q41

AL36

M_CHB_D Q42

AK36

M_CHB_D Q43

AJ34

M_CHB_D Q44

AN39

M_CHB_D Q45

AN40

M_CHB_D Q46

AK37

M_CHB_D Q47

AL39

AF37
AF36
AJ35

M_CHB_D Q48

AJ38

M_CHB_D Q49

AJ37

M_CHB_D Q50

AF38

M_CHB_D Q51

AE37

M_CHB_D Q52

AK40

M_CHB_D Q53

AJ40

M_CHB_D Q54

AF34

M_CHB_D Q55

AE35

AB35
AD35
AD37

M_CHB_D Q56

AD40

M_CHB_D Q57

AD38

M_CHB_D Q58

AB40

M_CHB_D Q59

AA39

M_CHB_D Q60

AE36

M_CHB_D Q61

AE39

M_CHB_D Q62

AB37

M_CHB_D Q63

AB38

Add DIMM B to
FS

d

d

i

i

f

f

2

M_CHB_D QS1 [18]
M_CHB_D QS1# [18]
M_CHB_D M1 [18]

M_CHB_D QS2 [18]
M_CHB_D QS2# [18]
M_CHB_D M2 [18]

e

e

M_CHB_D QS3 [18]
M_CHB_D QS3# [18]
M_CHB_D M3 [18]

M_CHB_D QS4 [18]
M_CHB_D QS4# [18]
M_CHB_D M4 [18]

M_CHB_D QS5 [18]
M_CHB_D QS5# [18]
M_CHB_D M5 [18]

M_CHB_D QS6 [18]
M_CHB_D QS6# [18]
M_CHB_D M6 [18]

M_CHB_D QS7 [18]
M_CHB_D QS7# [18]
M_CHB_D M7 [18]

2

M_CHB_D QS0 [18]
M_CHB_D QS0# [18]
M_CHB_D M0 [18]

t

t

n

n

1

M_CHB_DQ[ 0..63] [18]

l

l

a

a

i

i

PEGATRON DT-MB RESTRICTED SECRET

Title :

Title :

Title :

EAGLELAKE 3 - 7

EAGLELAKE 3 - 7

EAGLELAKE 3 - 7

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Pr oject Name

Size Pr oject Name

Size Pr oject Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

Engineer:

IPX41-D3

IPX41-D3

IPX41-D3

1

Ttepic Zhu

Ttepic Zhu

Ttepic Zhu

Rev

Rev

Rev

1.02

1.02

12 54Thursday, December 10, 2009

12 54Thursday, December 10, 2009

12 54Thursday, December 10, 2009

1.02

5

NRN25A 8.2K

FSBSEL0[6,8]
FSBSEL1[6,8]

D D

Add PCIE_B4 for DVI and HDMI to FS

PCIE_B4[25,27,28,29]

EXP_EN_H DR[25]

NOTE:

C C

DUALX8 1x16 PCIe 2x8 PCIe DUALX8 ENABLE

MTYPE NOT

EXP_SLR

ITPM_EN#

+1P1V_C L

12

B B

12

GND GND

A A

1 2

NOBOM

NOBOM

HIGH DESCRIPTIONLOWPIN

CONCURRENT

PRESENCE
NORMAL
ATX

ENABLE

I

I

NR35

NR35
1K

1K

CLINK VREF TARGET=0.349V

1%

1%

12

I

I

I

I

NR38

NR38

NCB8

NCB8

470

470

0.1UF/16V

0.1UF/16V

1%

1%

5

FSBSEL2[6,8]

NR661K

NR661K

12

NI

NI

NR760

NR760

12

NI

NI

NR30

NR30
1K

1K

GND

CONCURRENT

PRESENCE PCIe CARD IN

BTX

DISABLETCEN TLS CONFIDENTAL ITY

NRN25A 8.2K
NRN25B 8.2K

NRN25B 8.2K
NRN25C 8.2K

NRN25C 8.2K

NOBOM

NOBOM
NOBOM

NOBOM

12

NI

NI

NR75

NR75
1K

1K

PCI-E/SDVOEXP_SM NOT

PRIMARY SLOT
PCI-E LANE RESE RVALRESERVE

iTPM EnableENABLEDI SABLE

PLTRST#[22,39,43]

PWR GD_SIO_OUT[22,39]

P

P

NOBOM

NOBOM
NOBOM

NOBOM
NOBOM

NOBOM
NOBOM

NOBOM

NRN25D 8.2K

NRN25D 8.2K

12

NI

NI

NR32

NR32
1K

1K

12
34
56
78

NT13

NT13
NT14

NT14

1
1

TPC26b

TPC26b
TPC26b

TPC26b

12

NI

NI

NR22

NR22
1K

1K

NR80 3KI1%NR80 3KI1%

1 2

2009.08.14 shawn
NR80 from 3K 5% change to 3K 1%.

e

e

NT38

NT38
NT39

NT39

1

NT40

NT40

1

TPC26b

TPC26b

NT41

NT41

1

TPC26b

TPC26b

1

TPC26b

TPC26b
TPC26b

TPC26b

I

I
I

I
I

I

I

I

12

NI

NI

NR23

NR23
1K

1K

NOBOM

NOBOM
NOBOM

NOBOM
NOBOM

NOBOM
NOBOM

NOBOM
NOBOM

NOBOM
NOBOM

NOBOM
NOBOM

NOBOM
NOBOM

NOBOM
NOBOM

NOBOM
NOBOM

NOBOM
NOBOM

NOBOM
NOBOM

NOBOM
NOBOM

NOBOM
NOBOM

NOBOM
NOBOM

NOBOM
NOBOM

NOBOM
NOBOM

NOBOM
NOBOM

NOBOM
NOBOM

NOBOM
NOBOM

NOBOM
NOBOM

NOBOM

g

g

GND

12

12

TPC26b

TPC26b
TPC26b

TPC26b
TPC26b

TPC26b
TPC26b

TPC26b
TPC26b

TPC26b
TPC26b

TPC26b
TPC26b

TPC26b
TPC26b

TPC26b
TPC26b

TPC26b
TPC26b

TPC26b
TPC26b

TPC26b
TPC26b

TPC26b
TPC26b

TPC26b
TPC26b

TPC26b
TPC26b

TPC26b
TPC26b

TPC26b
TPC26b

TPC26b
TPC26b

TPC26b
TPC26b

TPC26b
TPC26b

TPC26b
TPC26b

TPC26b

4

NI

NI

NR24

NR24
1K

1K

NT15

NT15
NT16

NT16

1

NT17

NT17

1

NT25

NT25

1

NT18

NT18

1

NT19

NT19

1

NT20

NT20

1

NT21

NT21

1

NT22

NT22

1

NT23

NT23

1

NT24

NT24

1

NT27

NT27

1

NT28

NT28

1

NT29

NT29

1

NT30

NT30

1

NT31

NT31

1

NT32

NT32

1

NT33

NT33

1

NT34

NT34

1

NT35

NT35

1

NT36

NT36

1
1

CL_VREF

CL_RST#

I

I

a

a

NR81

NR81

1.5K

1.5K

TP_MCH _A45
TP_MCH_ B2
TP_MCH_ BE1
TP_MCH_ BE45

4

MCH_BS EL0
MCH_BS EL1
MCH_BS EL2

EXP_EN
DUALX8_ EN
TP_MCH_ M20
TP_MCH_ N17
MTYPE
EXP_SM
EXP_SLR
ITPM_EN#

TCEN

12

NI

NI

NR28

NR28
1K

1K

GNDG NDGND GND GNDGND

TP_MCH_ M17
TP_MCH_ G20
TP_MCH_ J16
TP_MCH_ M16
TP_MCH_ J15
TP_MCH_ J20
TP_MCH_ AR7
TP_MCH_ AN10
TP_MCH_ AN11
TP_MCH_ AN9
TP_MCH_ R31
TP_MCH_ R32
TP_MCH_ U30
TP_MCH_ U31
TP_MCH_ R15
TP_MCH_ R14
TP_MCH _T15
TP_MCH _T14
TP_MCH_ AB15
TP_MCH _L13
TP_MCH _L11

t

t

F17
G16
P15

G15

F20
M20
N17
K16
H17

F15

L17

J17

AN17

A44
BD1

BD45

BE2

BE44

B14
B45

AK15
AD42
AN16

W30

AW44

R42
U32

M17
G20

J16

M16

J15
J20

AR7

AN10
AN11

AN9
R31
R32
U30
U31
R15
R14

T15

T14

AB15

L13

L11

AN13

AY4
AY2

AW2

r

r

AN8

A45

B2

BE1

BE45

I

I

NU1E

NU1E

BSEL0
BSEL1
BSEL2

RSVD12
DUALX8_Enable
ALLZTEST
XORTEST
RSVD16
EXP_SM
EXP_SLR
ITPM_ENB
CEN

NC9
NC1
NC13
NC14
NC15
NC16
NC11
NC12
NC7
NC4
NC8
NC19
NC10
NC17
NC18

RSVD20
BSCANTEST
RSVD14
RSVD19
RSVD13
RSVD15
JTAG_TDI
JTAG_TDO
JTAG_TCK
JTAG_TMS
RSVD24
RSVD25
RSVD28
RSVD29
RSVD23
RSVD22
RSVD27
RSVD26
RSVD3
RSVD18
RSVD17

CL_VREF

o

o

CL_DATA
CL_CLK
CL_RSTB
CL_PWROK

RSVD1
RSVD9
RSVD10
RSVD11

EAGLELA KE

EAGLELA KE

DPL_REFSSCLKINP
DPL_REFSSCLKINN

n

n

MISC

MISC

REV=1.4

REV=1.4

CRT_HSYNC
CRT_VSYNC

CRT_RED

CRT_GREEN

CRT_BLUE

CRT_IRTN

VGA

VGA

CRT_DDC_DATA

CRT_DDC_CLK

DAC_IREF

DPL_REFCLKINP

DPL_REFCLKINN

C

C

RSTINB

PWROK

ICH_SYNCB

HDA_BCLK
HDA_RSTB

HDA_SDI

HDA_SDO

HDA_SYNC

DDPC_CTRLCLK

DDPC_CTRLDATA

DPRSTPB

SLPB

3

VGA_HSYN C_3P3V

D14

VGA_VSYN C_3P3V

C14

B18
D18
C18
F13

L15
M15

DACREFS ET

B15

PLACED RESISTOR
CLOSE TO THE GM CH
WITHIN 500 MIL
LENGTH

E15

o

o

D15

DPL_REF SSCLKP

G8
G9

AN6

PWR OK_R

AR4

K15

AU4
AV4

R_SDATA_ IN1

AU2
AV1
AU3

NOTE:

For port C

HDMI PORTC DDC Control CLK
HDMI PORTC DDC Control DATA

J11
F11

NB_DPRS TP#

P43

NB_SLP#

P42

3

I

I
I

I

2009.09.28 shawn
NC1, NC2, NC3 from NI change to 10pF for EMI issue.

PLACED CAPACITO R CLOSE TO
GMCH FOR EMI

n

n

NR37 0

NR37 0

VP

VP

DDPC_CT RL_CLK [25, 29]

DDPC_CT RL_DATA [25, 29]

NT44

NT44

1

TPC26b

TPC26b

NR18 33

NR18 33

1 2

NR21 33

NR21 33

1 2

12

f

f

NOBOM

NOBOM

12

I

I

NC1

NC1
10PF/50V

10PF/50V

NPO 5%

NPO 5%

I

I

I

I

NC2

NC2
10PF/50V

10PF/50V

NPO 5%

NPO 5%

12

d

d

NR33

NR33
1K

1K

i

i

1%

1%

GND

12

NR44 33

NR44 33

1 2

12

GNDGND GNDGND

e

e

I

I

CK_96M_ DREF [ 6]
CK_96M_ DREF# [6]

PWR GD_SIO_OUT [22, 39]

ICH_SYNC# [22]

+VTT_O UT_L

12

I

I

SR29

SR29

49.9

49.9

1%

1%

2

VGA_HSYNC [26]
VGA_VSYNC [26]

1 2

VGA_RED _NB
VGA_GRE EN_NB
VGA_BLU E_NB

12

12

I

I

I

I

NR25

NR25

NR26

I

I

NC3

NC3
10PF/50V

10PF/50V

NPO 5%

NPO 5%

GND GND

i

i

PLACED RESISTOR CLOSE TO

t

t

GMCH WITHIN 250 MIL LENGTH

n

n

DDCA_DA TA [26]
DDCA_CL K [26 ]

NOTE:

Change NR33 and NR25~NR27 to 0 OHM for non-Graphics SKU,
KEEP PU resistor VR14~15 for DDCDATA/CLK

+1P1V_C ORE

12

I

I

NR39

NR39
10K

10K

GND

12

NI

NI

SCB49

SCB49
10PF/50V

10PF/50V

NPO 5%

NPO 5%

GND

BITCLK_MC H [22]
AZRST#_M CH [22]
SDATA_IN 1 [22]
SDATA_OU T_MCH [22]
AZ_SYNC_MC H [22]

If not support C3/C4,
NC DPRSTP# and pull high
Refer to Eaglelake PDG 2.0

2

NR26

150

150

150

150

1%

1%

1%

1%

l

l

a

a

NOTE:

PIN G8 G9 are required to be connected
to 100MHz SRC of CK505 if Display Port
supported.

Add for HDMI to FS

PEGATRON DT-MB RESTRICTED SECRET

PEGATRON CORP.

PEGATRON CORP.

PEGATRON CORP.

Size Pr oject Name

Size Pr oject Name

Size Pr oject Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

1 2

1 2

12

I

I

NR27

NR27
150

150

1%

1%

GND

PLTRST# [22 ,39,43]

IPX41-D3

IPX41-D3

IPX41-D3

1

NOBOM

NOBOM

PJP14

PJP14

SHORTPIN

SHORTPIN

NOBOM

NOBOM

PJP15

PJP15

SHORTPIN

SHORTPIN

NOBOM

NOBOM

PJP16

PJP16
SHORTPIN

SHORTPIN

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

1

VGA_RED [26]

VGA_GRE EN [26]

VGA_BLUE [26]

EAGLELAKE 4 - 7

EAGLELAKE 4 - 7

EAGLELAKE 4 - 7

Ttepic Zhu

Ttepic Zhu

Ttepic Zhu

13 54Thursday, December 10, 2009

13 54Thursday, December 10, 2009

13 54Thursday, December 10, 2009

Rev

Rev

Rev

1.02

1.02

1.02

5

+1P1V_C ORE

D D

+1P1V_C ORE

+1P1V_C ORE

C C

+1P1V_C ORE

+1P1V_C ORE

+1P1V_C ORE

B B

A A

I

I

NL7

NL7

2.2UH/25 0mA

2.2UH/25 0mA

mx_l0805

mx_l0805

21

NL5

NL5

0.27UH/1 70mAImx_l0603

0.27UH/1 70mAImx_l0603

21

12

I

I

NCB31

NCB31

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%

12

NI

NI

NCB34

NCB34

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%

5

12

NI

NI

NCB32

NCB32

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%

12

I

I

NCB35

NCB35

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%

12

GNDGND GND

12

GNDGND GND

I

I

NCB33

NCB33

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%

NI

NI

NCB36

NCB36

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%

+1P1V_C ORE

12

NI

NI

NCB37

NCB37

P

P

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%

GND

e

e

4

g

g

+1P5V_ICH

4

12

NI

NI

NCB9

NCB9
10UF/6.3V

10UF/6.3V

X5R 10%

X5R 10%
mx_c0805

mx_c0805

GND

12

NI

NI

NCB13

NCB13
10UF/6.3V

10UF/6.3V

X5R 10%

X5R 10%
mx_c0805

mx_c0805

GND

12

I

I

NCB18

NCB18
10UF/6.3V

10UF/6.3V

X5R 10%

X5R 10%
mx_c0805

mx_c0805

GND

12

I

I

NCE1

NCE1
10UF/6.3V

10UF/6.3V

X5R 10%

X5R 10%
mx_c0805

mx_c0805

GND GND

12

I

I

NCE2

NCE2
10UF/6.3V

10UF/6.3V

X5R 10%

X5R 10%
mx_c0805

mx_c0805

GND

t

t

a

a

12

GND

12

GND

12

GND

12

12

GND

r

r

+1P1V_G PLLD

NI

NI

NCB10

NCB10

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%

NI

NI

NCB14

NCB14

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%

I

I

NCB23

NCB23

2.2UF/6.3 V

2.2UF/6.3 V

X5R 10%

X5R 10%
mx_c0603

mx_c0603

I

I

NCB27

NCB27

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%

I

I

NCB30

NCB30

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%

+1P1V_G PLL

+1P1V_M PLL

+1P1V_H PLL

+1P1V_D PLLB

+1P1V_D PLLA

o

o

+3P3V

12

NI

NI

NCB38

NCB38

4.7UF/6.3 V

4.7UF/6.3 V

X5R 10%

X5R 10%
mx_c0805

mx_c0805

GND GND

n

n

+1P1V_C L

12

I

I

NCB39

NCB39

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%

C

C

3

3

+1P1V_C ORE

o

o

+1P1V_H PLL_D

AA19
AA21
AA23
AA25
AA27
AA29
AA30
AB20
AB22
AB24
AB26
AB29
AB30
AC16
AC17
AC19
AC21
AC23
AC25
AC27
AC29
AD16
AD17
AD20
AD22
AD24
AD26
AD29
AE16
AE17
AE19
AE21
AE23
AE25
AE27
AE29

AF16
AF17
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
AF27
AF29

n

n

AG16
AG17
AG20
AG22
AG24
AG26
AG29

AJ16
AJ17
AJ19
AJ21
AJ23
AJ25

I

I

NU1F

NU1F

f

f

R25

B12

B16

A21

B22

U33

C20

D20

E19

AR2

EAGLELA KE

EAGLELA KE

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40

d

d

VCC41
VCC42

i

i

VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC68

VCCDPLL_EXP

VCCAPLL_EXP

VCCA_MPLL

VCCA_HPLL

VCCD_HPLL

VCCA_DPLLB

VCCA_DPLLA

VCC3_3

VCC_HDA

REV=1.4

REV=1.4

VCC69
VCC70
VCC71
VCC72
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC73
VCC74
VCC22
VCC50
VCC64
VCC65
VCC66
VCC67

e

e

VCC88

POWER

POWER

VCC_EXP1
VCC_EXP2
VCC_EXP3
VCC_EXP4
VCC_EXP5
VCC_EXP6
VCC_EXP7
VCC_EXP8

VCC_EXP9
VCC_EXP10
VCC_EXP11
VCC_EXP13
VCC_EXP14
VCC_EXP15
VCC_EXP16
VCC_EXP17
VCC_EXP19
VCC_EXP20
VCC_EXP21
VCC_EXP22
VCC_EXP23
VCC_EXP24
VCC_EXP25
VCC_EXP26
VCC_EXP30
VCC_EXP31
VCC_EXP32
VCC_EXP33
VCC_EXP34
VCC_EXP35
VCC_EXP36
VCC_EXP37
VCC_EXP38
VCC_EXP12
VCC_EXP18
VCC_EXP27
VCC_EXP28
VCC_EXP29

VCCAVRM_EXP

2

R26
R27
R29
T21
T24
T25
T26
T27
T29
U21
U22
U23
U24
U25
U26
U27
U29
W19
W21
W23
W25
W27
W29
Y20
Y22
Y24
Y26
T22
T23
AC4
AF3
F9

n

n

H4
L3
P3
V4

AA14
AA15
AB14
AC15
AD14
AD15
AE14
AE15
AF14
AF15
AG15
AJ10
AJ11
AJ12
AJ13
AJ14
AJ6
AJ7
AJ8
AJ9
AK10
AK11
AK12
AK13
AK6
AK7
AK8
AK9
U14
U15
W15
Y14
Y15
AJ1
AJ2
AK2
AK3
AK4

AG2

2

2009.08.14 shawn
NCB11, NCB12, NCB24 from 22uF 20% (11X23A226160)
change to 22uF 10% (11X23A226150)

+1P1V_C ORE

12

12

GND

i

i

12

t

t

GND

12

I

I

NCB65

NCB65

4.7UF/6.3 V

4.7UF/6.3 V

X5R 10%

X5R 10%
mx_c0805

mx_c0805

2009.08.19 shawn
NCB65, NCB28, NCB29 from 2.2uF change to 4.7uF.

VCCAVR M_EXP_RVCC_AZA

12

NI

NI

NCB76

NCB76

4.7UF/6.3 V

4.7UF/6.3 V

X5R 10%

X5R 10%

mx_c0805

mx_c0805

GND

I

I

I

I

NCB11

NCB11

NCB24

NCB24

10UF/6.3V

10UF/6.3V

10UF/6.3V

10UF/6.3V

X5R 10%

X5R 10%

X5R 10%

X5R 10%

mx_c1206

mx_c1206

mx_c1206

mx_c1206

GND

l

l

a

a

12

I

I

I

I

NCB19

NCB19

NCB20

NCB20

1UF/16V

1UF/16V

1UF/16V

1UF/16V

X7R 10%

X7R 10%

X7R 10%

X7R 10%

mx_c0603

mx_c0603

mx_c0603

mx_c0603

GND

+1P1V_PC IEXPRESS

12

I

I

NCB28

NCB28

4.7UF/6.3 V

4.7UF/6.3 V

X5R 10%

X5R 10%
mx_c0805

mx_c0805

VP

VP

+1P1V_C ORE

NR79

NR79
0

0

mx_r0603

mx_r0603

1 2

NI

NI

+1P5V_ICH

NR78

NR78
0

0

mx_r0603

mx_r0603

1 2

PEGATRON CORP.

PEGATRON CORP.

PEGATRON CORP.

Size Pr oject Name

Size Pr oject Name

Size Pr oject Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

GND

GND

12

I

I

NCB12

NCB12
10UF/6.3V

10UF/6.3V

X5R 10%

X5R 10%
mx_c1206

mx_c1206

12

I

I

NCB16

NCB16
10UF/6.3V

10UF/6.3V

X5R 10%

X5R 10%
mx_c0805

mx_c0805

12

GNDGNDGND

I

I

NCB29

NCB29

4.7UF/6.3 V

4.7UF/6.3 V

X5R 10%

X5R 10%
mx_c0805

mx_c0805

Engineer:

Engineer:

Engineer:

IPX41-D3

IPX41-D3

IPX41-D3

1

NOBOM

NOBOM

NJP1

NJP1
SHORTPIN _RECT

SHORTPIN _RECT

NOBOM

NOBOM

NJP2

NJP2
SHORTPIN _RECT

SHORTPIN _RECT

NOBOM

NOBOM

NJP5

NJP5
SHORTPIN _RECT

SHORTPIN _RECT

NOBOM

NOBOM

NJP6

NJP6
SHORTPIN _RECT

SHORTPIN _RECT

Title :

Title :

Title :

1

+1P1V_C ORE

12

12

12

12

EAGLELAKE 5 - 7

EAGLELAKE 5 - 7

EAGLELAKE 5 - 7

Ttepic Zhu

Ttepic Zhu

Ttepic Zhu

14 54Thursday, December 10, 2009

14 54Thursday, December 10, 2009

14 54Thursday, December 10, 2009

Rev

Rev

Rev

1.02

1.02

1.02

5

4

3

2

1

12

I

I

NCB46

NCB46

2.2UF/6.3 V

2.2UF/6.3 V

X5R 10%

X5R 10%
mx_c0603

mx_c0603

12

I

I

NCB42

NCB42

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%

12

I

I

NCB57

NCB57

2.2UF/6.3 V

2.2UF/6.3 V

X5R 10%

X5R 10%
mx_c0603

mx_c0603

a

a

12

NI

NI

NCB75

NCB75
1UF/16V

1UF/16V

X7R 10%

X7R 10%
mx_c0603

mx_c0603

4

+1P1V_FS B_VTT

12

NI

NI

NCB67

NCB67

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%

t

t

VCCCML_ DDR

r

r

o

o

GND

Place near GMCH

I

I

NCB40

NCB40

2.2UF/6.3 V

2.2UF/6.3 V

X5R 10%

X5R 10%
mx_c0603

mx_c0603

NI

NI

NCB49

NCB49

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%

I

I

NCB55

NCB55

2.2UF/6.3 V

2.2UF/6.3 V

X5R 10%

X5R 10%
mx_c0603

mx_c0603

I

I

NR60

NR60

40.2

40.2

1%

1%
mx_r0603

mx_r0603

I

I

NR62

NR62

39.2

39.2

1%

1%
mx_r0603

mx_r0603

I

I

NL12

NL12

0.1UH/30 0mA

0.1UH/30 0mA

mx_l0603

mx_l0603

12

I

I

NCB45

NCB45

2.2UF/6.3 V

2.2UF/6.3 V

X5R 10%

X5R 10%
mx_c0603

mx_c0603

12

NI

NI

NCB41

NCB41

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%

12

I

I

NCB56

NCB56

2.2UF/6.3 V

2.2UF/6.3 V

X5R 10%

X5R 10%
mx_c0603

mx_c0603

GND GNDGND

12

I

I

NCB62

NCB62
1UF/16V

1UF/16V

X7R 10%

X7R 10%
mx_c0603

mx_c0603

GNDGND

e

e

21

GNDGNDGND

GNDGNDGND

g

g

GND

D D

C C

+1P5V_D UAL

12

I

I

NCB43

NCB43

2.2UF/6.3 V

2.2UF/6.3 V

X5R 10%

X5R 10%
mx_c0603

mx_c0603

+3P3V

NL10

NL10

0.27UH/1 70mAImx_l0603

0.27UH/1 70mAImx_l0603

B B

A A

Place a via in between cap and GMCH on
GND trace.It means that the GND fo r cap
has to be independent

12

I

I

NCB53

NCB53

2.2UF/6.3 V

2.2UF/6.3 V

X5R 10%

X5R 10%
mx_c0603

mx_c0603

21

+1P5V_ICH

+1P1V_C L

+3P3V_D AC_FB

5

12

12

+

+

12

I

I

NCB54

NCB54

2.2UF/6.3 V

2.2UF/6.3 V

X5R 10%

X5R 10%
mx_c0603

mx_c0603

GNDGNDGND GND

I

I

12

NCE3

NCE3
330UF/6.3 V

330UF/6.3 V

GND GND

12

12

12

I

I

NCB44

NCB44

2.2UF/6.3 V

2.2UF/6.3 V

X5R 10%

X5R 10%
mx_c0603

mx_c0603

2009.09.29 shawn
NL10 from short-pin change to 0.27uF
NCE3 from NI change to I
Add NCB66 and NCB67
Remove NR58 short pin

I

I

NCB66

NCB66
10UF/6.3V

10UF/6.3V

X5R 10%

X5R 10%

12

mx_c0805

mx_c0805

12

GND

P

P

I

I

NU1G

NU1G

A25

VTT_FSB1

B25

VTT_FSB2

B26

VTT_FSB3

C24

VTT_FSB4

C26

VTT_FSB5

D22

VTT_FSB6

D23

VTT_FSB7

D24

VTT_FSB8

E23

VTT_FSB9

F21

VTT_FSB10

F22

VTT_FSB11

G21

VTT_FSB12

G22

VTT_FSB13

H21

VTT_FSB14

H22

VTT_FSB15

J21

VTT_FSB16

J22

VTT_FSB17

K21

VTT_FSB18

K22

VTT_FSB19

L21

VTT_FSB20

L22

VTT_FSB21

M21

VTT_FSB22

M22

VTT_FSB23

N20

VTT_FSB24

N21

VTT_FSB25

N22

VTT_FSB26

P20

VTT_FSB27

P21

VTT_FSB28

P22

VTT_FSB29

P24

VTT_FSB30

R20

VTT_FSB31

R21

VTT_FSB32

R22

VTT_FSB33

R23

VTT_FSB34

R24

VTT_FSB35

AP44

VCC_SM1

AT45

VCC_SM2

AV44

VCC_SM3

AY40

VCC_SM4

BA41

VCC_SM5

BB39

VCC_SM6

BD21

VCC_SM7

BD25

VCC_SM8

BD29

VCC_SM9

BD34

VCC_SM10

BD38

VCC_SM11

BE23

VCC_SM12

BE27

VCC_SM13

BE31

VCC_SM14

BE36

VCC_SM15

B19

VCCA_DAC1

D19

VCCA_DAC2

n

n

A17

VCCA_EXP

B20

VCCDQ_CRT

B17

VSS179

AM30

VCCCML_DDR

EAGLELA KE

EAGLELA KE

C

C

REV=1.4

REV=1.4

3

VCC_SMCLK1
VCC_SMCLK2
VCC_SMCLK3
VCC_SMCLK4

VCC_CL2
VCC_CL3
VCC_CL5
VCC_CL6

VCC_CL9
VCC_CL10
VCC_CL12
VCC_CL13
VCC_CL15
VCC_CL23
VCC_CL38
VCC_CL58
VCC_CL65
VCC_CL66
VCC_CL67
VCC_CL69
VCC_CL70
VCC_CL71
VCC_CL72
VCC_CL73
VCC_CL74
VCC_CL75
VCC_CL84
VCC_CL85
VCC_CL78
VCC_CL79
VCC_CL83

VCC_CL1

VCC_CL4

VCC_CL7

VCC_CL8
VCC_CL11
VCC_CL14
VCC_CL16
VCC_CL17
VCC_CL21
VCC_CL22
VCC_CL25

o

o

VCC_CL26
VCC_CL27
VCC_CL28
VCC_CL29
VCC_CL30
VCC_CL31
VCC_CL32
VCC_CL33
VCC_CL34
VCC_CL35
VCC_CL36
VCC_CL37
VCC_CL39
VCC_CL40
VCC_CL41
VCC_CL55
VCC_CL42
VCC_CL44
VCC_CL46
VCC_CL47
VCC_CL48
VCC_CL49
VCC_CL50
VCC_CL51
VCC_CL52
VCC_CL45
VCC_CL53
VCC_CL54
VCC_CL56
VCC_CL57
VCC_CL59
VCC_CL60
VCC_CL61
VCC_CL62
VCC_CL63
VCC_CL64
VCC_CL68
VCC_CL76
VCC_CL77
VCC_CL43
VCC_CL18
VCC_CL24
VCC_CL19
VCC_CL20
VCC_CL80
VCC_CL82
VCC_CL81

AK32
AL31
AL32
AM31

AA32
AA33
AB32
AB33
AD32
AD33
AE32
AE33
AF32
AJ32
AK31
AL30
AM15
AM16
AM17
AM20
AM21
AM22
AM24
AM25
AM26
AM29
Y32
Y33
AP1
AP2
Y31
AA31
AB31
AC31
AD31
AE31
AF31
AG30

n

n

AG31
AJ30
AJ31
AK16
AK17
AK19
AK20
AK21
AK22
AK23
AK24
AK25
AK26
AK27
AK29
AK30
AL1
AL10
AL11
AL26
AL12
AL15
AL17
AL19
AL2
AL20
AL21
AL22
AL23
AL16
AL24
AL25
AL27
AL29
AL4
AL5
AL6
AL7
AL8
AL9
AM2
AM3
AM4
AL14
AJ15
AK14
AJ27
AJ29
W31
Y30
Y29

f

f

VCCCK_D DR

d

d

i

i

12

I

I

NCB47

NCB47

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%

BOTTOM

BOTTOM

GND

n

n

e

e

12

NI

NI

NCB50

NCB50

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%

GND

BACKSIDE CAPS F OR SPECIFIC +1P1V_C ORE GMCH

2

NI

NI

NR57 1

NR57 1

1 2

BOTTOM

NI

NI

+1P1V_C L +1P1V_C ORE

i

i

t

t

12

I

I

NCB51

NCB51
10UF/6.3V

10UF/6.3V

X5R 10%

X5R 10%
mx_c0805

mx_c0805

GND GND

12

NI

NI

NCB63

NCB63
1UF/16V

1UF/16V

X7R 10%

X7R 10%
mx_c0603

mx_c0603

BOTTOM

BOTTOM

GND

12

NI

NI

NCB71

NCB71
1UF/16V

1UF/16V

X7R 10%

X7R 10%
mx_c0603

mx_c0603

BOTTOM

BOTTOM

GND GND GND

BOTTOM

NR56 1

NR56 1

1 2

BOTTOM

BOTTOM

l

l

a

a

NOBOM

NOBOM

NJP9

NJP9

12

SHORTPIN _RECT

SHORTPIN _RECT

NOBOM

NOBOM

NJP8

NJP8

12

SHORTPIN _RECT

SHORTPIN _RECT

NOBOM

NOBOM

NJP7

NJP7

12

SHORTPIN _RECT

SHORTPIN _RECT

12

I

I

NCB52

NCB52
10UF/6.3V

10UF/6.3V

X5R 10%

X5R 10%
mx_c0805

mx_c0805

12

GND

12

12

NI

NI

NI

NCB64

NCB64
1UF/16V

1UF/16V

X7R 10%

X7R 10%
mx_c0603

mx_c0603

BOTTOM

BOTTOM

NI

NI

NCB72

NCB72
1UF/16V

1UF/16V

X7R 10%

X7R 10%
mx_c0603

mx_c0603

BOTTOM

BOTTOM

PEGATRON CORP.

PEGATRON CORP.

PEGATRON CORP.

Date: Sheet of

Date: Sheet of

Date: Sheet of

NI

NCB69

NCB69
1UF/16V

1UF/16V

X7R 10%

X7R 10%
mx_c0603

mx_c0603

BOTTOM

BOTTOM

GND

PEGATRON DT-MB RESTRICTED SECRET

Size Pr oject Name

Size Pr oject Name

Size Pr oject Name

A3

A3

A3

V_CKDDR _R

12

NI

NI

NCB70

NCB70
1UF/16V

1UF/16V

X7R 10%

X7R 10%
mx_c0603

mx_c0603

BOTTOM

BOTTOM

GND

12

NI

NI

NCB74

NCB74
1UF/16V

1UF/16V

X7R 10%

X7R 10%
mx_c0603

mx_c0603

BOTTOM

BOTTOM

IPX41-D3

IPX41-D3

IPX41-D3

+1P5V_D UAL

12

GND

+1P1V_C ORE

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

1

NI

NI

NCB48

NCB48
10UF/6.3V

10UF/6.3V

X5R 10%

X5R 10%
mx_c0805

mx_c0805

BOTTOM

BOTTOM

EAGLELAKE 6 - 7

EAGLELAKE 6 - 7

EAGLELAKE 6 - 7

Ttepic Zhu

Ttepic Zhu

Ttepic Zhu

15 54Thursday, December 10, 2009

15 54Thursday, December 10, 2009

15 54Thursday, December 10, 2009

Rev

Rev

Rev

1.02

1.02

1.02

5

NU1H

I

NU1H

I

A12

VSS1

A15

VSS2

A19

VSS3

A27

VSS4

A31

VSS6

A36

VSS7

A40

VSS8

D D

C C

B B

A A

AA1
AA11
AA12
AA13
AA20
AA22
AA24
AA26
AA34
AA38
AA40
AA44

AA8
AB11
AB12
AB19
AB21
AB23
AB25
AB27
AB34
AB36
AB39

AB4

AB6

AB7

AB8
AC20
AC22
AC24
AC26
AC45

AC5
AD12
AD19
AD21
AD23
AD25
AD27

AD3
AD34
AD36
AD39

AD6

AD9

AE1
AE11
AE20
AE22
AE24
AE26
AE34
AE38
AE40
AE44

AE8

AF10
AF11
AF12
AF13
AF33
AF35
AF39

AG19
AG21
AG23
AG25
AG27
AG45

AG5

AH2

AH3

AH4

AJ20
AJ22
AJ24

AU20
AA16
AA17
AB16
AB17

AF6
AF7

N16
P16
P17
R16
R17
R19
R30

VSS12
VSS13
VSS14
VSS15
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95

VSS143
VSS16
VSS17
VSS29
VSS30
VSS286
VSS294
VSS295
VSS301
VSS302
VSS303
VSS305

EAGLELA KE

EAGLELA KE

5

GND

GND

REV=1.4

REV=1.4

VSS116
VSS118
VSS119
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS172
VSS142
VSS144
VSS145
VSS146
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS159
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS173
VSS174
VSS175
VSS176
VSS177
VSS180
VSS181
VSS182
VSS183
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS193
VSS194
VSS196
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS206
VSS207
VSS158
VSS211
VSS213
VSS251
VSS100

VSS99
VSS98
VSS97
VSS96

VSS359
VSS358
VSS345
VSS344
VSS338
VSS337
VSS336
VSS335
VSS319
VSS317
VSS316
VSS315
VSS314

AP20
AP22
AP24
AP29
AP45
AR10
AR11
AR13
AR16
AR26
AR3
AR31
AR33
AR35
AR39
AR8
AR9
AT1
AT11
AT13
AT17
AT2
AT24
AT29
AY15
AT35
AU22
AU25
AU30
AU9
AV11
AV13
AV15
AV16
AV2
AV21
AV30
AV38
AV8
AV9
AW11
AW17
AW20
AW22
AW24
AW26
AW3
AW30
AY1
AY16
AY21
AY25
AY30
AY45
B21
B27
B29
B34
BA23
BA5
BB21
BB25
BB28
BB6
BD12
BD17
BD43
BD8
BE10
BE15
BE19
BE21
BE25
BE29
BE34
BE40
AV33
C3
C5
H38
AJ45
AJ44
AJ39
AJ36
AJ26

Y17
Y16
W17
W16

P

P

U20
U19
U17
U16
T30
T20
T19
T17
T16

e

e

GNDGND

4

g

g

4

a

a

AK35
AK38
AK39

AL38
AL44

AL45
AN33
AN36
AN38

t

t

AN7

A8
D11
D16
D21
D25
D26
D39

D6

D7
B10

E3
E31
E41

E5

F16

F2

F30

F4

F42
F45

F8
G11
G17
G24
G26
G29

G3

G35

H1
H11
H13
H15
H16
H20
H25
H30
H31
H33
H44

H7

H8

H9

J3

J37

J4
J5
J8

J9
K11
K13
K17
K20
K24
K29
K33
K45

L10

r

r

L16
L20
L26
L30
L35
L39

L4
L8
L9

M1
M24
M25
M44
N11
N13
N26
N29
N30
N33
N36

F1

C45

C1

I

I

NU1I

NU1I

VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS112
VSS113
VSS114
VSS115
VSS11
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS178
VSS222
VSS223
VSS224
VSS225
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267

o

o

VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS287
VSS288
VSS289
VSS290
VSS291
VSS226
VSS212
VSS209

EAGLELA KE

EAGLELA KE

GND

GND

REV=1.4

REV=1.4

VSS160
VSS149
VSS148
VSS120
VSS117
VSS111
VSS210
VSS292
VSS293
VSS296
VSS297
VSS298
VSS299
VSS300
VSS304
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS318
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS339
VSS340
VSS341
VSS342
VSS343
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS360
VSS361
VSS362
VSS363

n

n

VSS364
VSS365
VSS366
VSS367
VSS368
VSS369
VSS108

VSS64
VSS109
VSS147
VSS110

VSS63
VSS107

VSS5
VSS9

VSS10
VSS184
VSS191
VSS192
VSS195
VSS197
VSS205
VSS208

NC3
NC2
NC6
NC5

AV6
AU6
AU5
AP25
AP21
AN26
C16
N38
N8
P25
P26
P31
R11
R12
R2
R38
R45
R5
R8
T10
T11
T12
T13
T3
T31
T32
T33
T35
T38
T4
T40
T6
T7
T8
T9
U1
U11
U12
U13
U36
U39
U44
U8
W1
W2
W20
W22
W24
W26
W44
W45
W5
Y10
Y11

C

C

Y12
Y13
Y19
Y2
Y21
Y23
Y25
Y27
Y3
Y35
Y39
Y9
AN22
AE13
AN24
AU35
AN25
AE12
AN21
A3
A43
A6
B44
BC1
BC45
BD2
BD44
BE3
BE43

AD30
AC30
AF30
AE30

3

3

GNDGND

o

o

n

n

f

f

2

EAGLELAKE-P/Q/G

13G070110360 HEATSINK 42.2*42 .2*30mm SILVER

13G070183000 HEATSINK 42.3 *42.3*30mm G LUE

13G070308012 HEATSINK 42.3*42 .3*30mm SILVER

HEATSINK 1

HEATSINK 1

1
2
3
4

i

i

t

t

I

I

i

i

GND

I

I

CLIP1

CLIP1

d

d

ANCHOR_ CLIP

ANCHOR_ CLIP

e

e

2

HEATSINK_ 2ANCHOR

HEATSINK_ 2ANCHOR

I

I

n

n

CLIP2

CLIP2

ANCHOR_ CLIP

ANCHOR_ CLIP

1

l

l

a

a

PEGATRON DT-MB RESTRICTED SECRET

Title :

Title :

Title :

EAGLELAKE 7 - 7

EAGLELAKE 7 - 7

EAGLELAKE 7 - 7

Engineer:

Engineer:

PEGATRON CORP.

PEGATRON CORP.

PEGATRON CORP.

Size Pr oject Name

Size Pr oject Name

Size Pr oject Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

Engineer:

IPX41-D3

IPX41-D3

IPX41-D3

1

Ttepic Zhu

Ttepic Zhu

Ttepic Zhu

16 54Thursday, December 10, 2009

16 54Thursday, December 10, 2009

16 54Thursday, December 10, 2009

1.02

1.02

1.02

Rev

Rev

Rev

5

NOTE:

Below 4 signals are different connection in Eaglelake platform
Channel A : CS1/WE/MA0
Channel B : ODT3 (G41 No ODT3)

D D

M_CHA_M AA0
M_CHA_M AA1
M_CHA_M AA2
M_CHA_M AA3
M_CHA_M AA4
M_CHA_M AA5
M_CHA_M AA6
M_CHA_M AA7
M_CHA_M AA8
M_CHA_M AA9
M_CHA_M AA10 M_CHA_D Q53
M_CHA_M AA11
M_CHA_M AA12
M_CHA_M AA13

NOTE:

Check clock source if Eaglelake
implemented

M_CHA_C LK0[11]
M_CHA_C LK0#[11]
M_CHA_C LK2[11]
M_CHA_C LK2#[11]

06/03 Important! follow Intel MRC code,

C C

B B

A A

only DIMMA need.

M_CHA_C S#1[12]
M_CHA_C S#0[11]

M_CHA_C KE1[11]
M_CHA_C KE0[11]

M_CHA_B A2[11]
M_CHA_B A1[11]
M_CHA_B A0[11]

SMB_DAT A_S[6,18,22,24,25]
SMB_CLK _S[6,18,22,24,25]

M_CHA_W E#[12]
M_CHA_R AS#[11]
M_CHA_C AS#[11]

M_CHA_O DT1[11]
M_CHA_O DT0[11]

DDR3_DR AMRST#[12,18]

M_CHA_D M7[11]

M_CHA_D M5[11] M_CHA_D QS4 [11]

M_CHA_D M4[11]

M_CHA_D M3[11]

M_CHA_D M2[11]

M_CHA_D M1[11]

M_CHA_D M0[11]

5

M_CHA_M AA14

GND

GND

DIMMA0A

DIMMA0A

188

A0

181

A1

61

A2

180

A3

59

A4

58

A5

178

A6

56

A7

177

A8

175

A9

70

A10/AP

55

A11

174

A12

196

A13

172

A14

171

A15

63

CK1P/NU

64

CK1N/NU

184

CK0P

185

CK0N

76

CS1#

193

CS0#

169

CKE1

50

CKE0

52

BA2

190

BA1

71

BA0

238

SDA

118

SCL

165

CB7

164

CB6

159

CB5

158

CB4

46

CB3

45

CB2

40

CB1

39

CB0

237

SA1

117

SA0

73

WE#

192

RAS#

74

CAS#

77

ODT1

195

ODT0

168

RESET#

161

DM8/DQS17P

162

NC/DQS17N

230

DM7/DQS16P

231

NC/DQS16N

221

DM6/DQS15P

222

NC/DQS15N

212

DM5/DQS14P

213

NC/DQS14N

203

DM4/DQS13P

204

NC/DQS13N

152

DM3/DQS12P

153

NC/DQS12N

143

DM2/DQS11P

P

P

144

NC/DQS11N

134

DM1/DQS10P

135

NC/DQS10N

125

DM0/DQS9P

126

NC/DQS9N

43

NC/DQS8P

42

NC/DQS8N

198

FREE1

187

FREE2

49

FREE3

48

FREE4

DDR3_DIMM _240P

DDR3_DIMM _240P

I

I

e

e

4

XMM1 COLOR: BLU E

234

DQ63

233

DQ62

228

DQ61

227

DQ60

115

DQ59

114

DQ58

109

DQ57

108

DQ56

225

DQ55

224

DQ54

219

DQ53

218

DQ52

106

DQ51

105

DQ50

100

DQ49

99

DQ48

216

DQ47

215

DQ46

210

DQ45

209

DQ44

97

DQ43

96

DQ42

91

DQ41

90

DQ40

207

DQ39

206

DQ38

201

DQ37

200

DQ36

88

DQ35

87

DQ34

82

DQ33

81

DQ32

156

DQ31

155

DQ30

150

DQ29

149

DQ28

37

DQ27

36

DQ26

31

DQ25

30

DQ24

147

DQ23

146

DQ22

141

DQ21

140

DQ20

28

DQ19

27

DQ18

22

DQ17

21

DQ16

138

DQ15

137

DQ14

132

DQ13

131

DQ12

19

DQ11

18

DQ10

13

DQ9

12

DQ8

129

DQ7

128

DQ6

123

DQ5

122

DQ4

10

DQ3

9

DQ2

4

DQ1

3

DQ0

112

DQS7P

a

a

111

DQS7N

103

DQS6P

102

DQS6N

94

DQS5P

g

g

93

DQS5N

85

DQS4P

84

DQS4N

34

DQS3P

33

DQS3N

25

DQS2P

24

DQS2N

16

DQS1P

15

DQS1N

7

DQS0P

6

DQS0N

79

RESERVED

68

NC/PAR_IN

NC/TEST4

53
167

4

NC/ERR_OUT

M_CHA_D Q63
M_CHA_D Q62
M_CHA_D Q61
M_CHA_D Q60
M_CHA_D Q59
M_CHA_D Q58
M_CHA_D Q57
M_CHA_D Q56
M_CHA_D Q55
M_CHA_D Q54

M_CHA_D Q52
M_CHA_D Q51
M_CHA_D Q50
M_CHA_D Q49
M_CHA_D Q48
M_CHA_D Q47
M_CHA_D Q46
M_CHA_D Q45
M_CHA_D Q44
M_CHA_D Q43
M_CHA_D Q42
M_CHA_D Q41
M_CHA_D Q40
M_CHA_D Q39
M_CHA_D Q38
M_CHA_D Q37
M_CHA_D Q36
M_CHA_D Q35
M_CHA_D Q34
M_CHA_D Q33
M_CHA_D Q32
M_CHA_D Q31
M_CHA_D Q30
M_CHA_D Q29
M_CHA_D Q28
M_CHA_D Q27
M_CHA_D Q26
M_CHA_D Q24
M_CHA_D Q25
M_CHA_D Q23
M_CHA_D Q22
M_CHA_D Q21
M_CHA_D Q20
M_CHA_D Q19
M_CHA_D Q18
M_CHA_D Q17
M_CHA_D Q16
M_CHA_D Q15
M_CHA_D Q14
M_CHA_D Q13
M_CHA_D Q12
M_CHA_D Q11
M_CHA_D Q10
M_CHA_D Q9
M_CHA_D Q8
M_CHA_D Q7
M_CHA_D Q6
M_CHA_D Q5
M_CHA_D Q4
M_CHA_D Q3
M_CHA_D Q2
M_CHA_D Q1
M_CHA_D Q0

t

t

M_CHA_D QS7 [11]
M_CHA_D QS7# [11]
M_CHA_D QS6 [11]
M_CHA_D QS6# [11]
M_CHA_D QS5 [11]M_CHA_D M6[11]
M_CHA_D QS5# [11]

M_CHA_D QS4# [11]
M_CHA_D QS3 [11]
M_CHA_D QS3# [11]
M_CHA_D QS2 [11]
M_CHA_D QS2# [11]
M_CHA_D QS1 [11]
M_CHA_D QS1# [11]
M_CHA_D QS0 [11]
M_CHA_D QS0# [11]

r

r

o

o

SWAP DATA signal

n

n

C

C

3

3

o

o

n

n

+1P5V_D UAL + 1P5V_DUAL

+0P75V_V TT_DDR

12

GND GND

i

i

f

f

12

I

I

D3R17

D3R17
1K

1K

1%

1%

12

I

I

D3R18

D3R18
1K

1K

1%

1%

GND

GND GND GND

I

I

D3CB17

D3CB17

4.7UF/6.3 V

4.7UF/6.3 V

X5R 10%

X5R 10%
mx_c0805

mx_c0805

d

d

12

I

I

D3R15

D3R15
1K

1K

1%

1%

12

I

I

D3R16

D3R16
1K

1K

1%

1%

2

M_CHA_DQ[ 0..63] [11]

M_CHA_MAA [1..14] [11]

M_CHA_M AA0 [12]

DIMMA0B

+1P5V_D UAL +1P5V_D UAL

n

n

12

I

I

e

e

D3CB18

D3CB18

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%

GND

DIMM_CA_ VREF_A

DIMM_VRE F_A

12

12

I

I

D3CB6

D3CB6

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%

2

I

I

D3CB5

D3CB5

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%

DIMMA0B

78

VDD10

75

VDD9

72

VDD8

69

VDD7

66

VDD6

65

VDD5

62

VDD4

60

VDD3

57

t

t

VDD2

54

VDD1

51

VDD0

240

VTT2

120

VTT1

113

GND27

110

GND26

107

GND25

104

GND24

101

GND23

98

GND22

95

GND21

92

GND20

89

GND19

86

GND18

83

GND17

80

GND16

47

GND15

44

GND14

41

GND13

38

GND12

35

GND11

32

GND10

29

GND9

26

GND8

23

GND7

20

GND6

17

GND5

14

GND4

11

GND3

8

GND2

5

GND1

2

GND0

67

VREFCA

1

VREFDQ

DDR3_DIMM _240P

DDR3_DIMM _240P

I

I

i

i

l

l

197

VDD21

194

VDD20

191

VDD19

189

VDD18

a

a

186

VDD17

183

VDD16

182

VDD15

179

VDD14

176

VDD13

173

VDD12

170

VDD11

239

GND59

235

GND58

232

GND57

229

GND56

226

GND55

223

GND54

220

GND53

217

GND52

214

GND51

211

GND50

208

GND49

205

GND48

202

GND47

199

GND46

166

GND45

163

GND44

160

GND43

157

GND42

154

GND41

151

GND40

148

GND39

145

GND38

142

GND37

139

GND36

136

GND35

133

GND34

130

GND33

127

GND32

124

GND31

121

GND30

119

GND29

116

GND28

241

NP_NC1

242

NP_NC2

243

NP_NC3

236

VDDSPD

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Pr oject Name

Size Pr oject Name

Size Pr oject Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

GND

1

+3P3V

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

IPX41-D3

IPX41-D3

IPX41-D3

1

DDR3 DIMMA

DDR3 DIMMA

DDR3 DIMMA

Ttepic Zhu

Ttepic Zhu

Ttepic Zhu

17 54Thursday, December 10, 2009

17 54Thursday, December 10, 2009

17 54Thursday, December 10, 2009

Rev

Rev

Rev

1.02

1.02

1.02