Pegatron IPPLP-RH Schematic

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IPPLP-RH

PAGE

01
02
03

D D

04
05
06
07
08~13
14
15~16
17
18
19~24
25
26
27
28
29

C C

30
31
32
33
34
35
36
37
38
39
40
41
42
43

B B

44
45
46
47
48
49
50
51~52
53
54
55
56
57
58

A A

59
60
61
62
63
64~66
67

BLOCK DIAGRAM
CLOCKS DISTRIBUTION
SIGNAL & RESET MAP
CHANGE HISTORY
POWER FLOW
POWER DISTRIBUTION
POWER SEQUENCE
Haswell LGA-1150
VGA DEBUG
DDR3 CHANNEL A&B
DDR3 TERMINATION A&B
N/A
INTEL_PCH(1~6)
N/A
SM BUS & SPI ROM
ME DISABLE
MINI-PCIE SLOT-1(WLAN)
MINI-PCIE SLOT-3(mSATA)
CARD READER
INTEL CLARKVILLE
LAN JACK
SIDE USB3.0 PORT
REAR USB3.0 PORT
REAR USB3.0 PORT
REAR USB2.0 PORT
TOUCH & WEBCAM
N/A
SATA CONN
AUDIO CODEC ALC3661
AMP
REAR LINE OUT& GHS CONNECTOR
N/A
SIO SMSC5555
N/A
SCREW HOLE
FAN CIRCUIT
COM PORT
DEBUG LED
APS/LPC DEBUG
SCALAR_TSUMU88BDC2
LVDS & CONVERTER CONN
SCALAR LCD ENABLE
FRONT PANEL
HDMI IN
HDMI LEVEL SHIFT
HDMI OUT
G-SENSOR
DP REDRIVER
DP CONN
TPM
DC IN
VCORE CONTROLLER
3P3_LAN,12V,1P5V_PCH,3P3V_BG

TITLE

5

Revision: B00

GPU MARS

USB3.0 x 4
USB2.0 x 2

USB3.0 x 2

<Rear>

<Side>

Intel WGI217LM

10/100/1000

WLAN/MSATA
(NGFF)

68
69
70
71
72
73 N/A
74 +3P3V_WLAN & +3P3V_mSATA
75
76
77
78
79~85
86~89 VRAM
90 +1P8V

92

5V, 3P3V, 1P5V, 5V_Dual
+1P05V_PCH & +1P22V
+5VSB, +3P3VA
+5VSB, +12VSB
+1P5V_DUAL , +VTT_DDR

N/A
CPU XDP DEBUG CONNECTOR
PCH XDP DEBUG CONNECTOR
N/A
GPU

3P3V_GPU&+0P95V91
+1P35V_GPU & +1P05V_ME 95 TP

4

WiFi
MSATA
Webcam

Touch

RJ 45

Card Reader
OZ777FJ2LN

XDP

PCIE X8

USB

PCIE BUS

100MHz

PCIE BUS

PCIE BUS/SATA

XDP

SMSC5555

93~94 VDDC CONTROLLER
95 SIDE KEY
96 CONVERTER BOARD

3

Intel Processor

Haswell

LGA-1150 Pin Socket

TDP = 65W

DMI

INTEL

Lynx Point

PCH

708 Pin

23mm X 22mm

LPC BUS

33MHz

ST33ZP24AR28PVSP

LPC BUS

33MHz

TPM

2

Channel A

Channel B

DDIB(Port B)

TMDS(Port C)

TMDS(Port D)

PS8201 HDMI OUT

SATA BUS

SPI

HD Audio

DIGI
MIC

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

Dual Channel DDR3 MEMORY x 2 Slots

DDR3 SO-DIMM 1333/1600

DDR3 SO-DIMM 1333/1600

PS8330B

TSUMU88BDC2

LVDS

HDMI IN

HDMI 3.0G

SATA 3.0
SATA 3.0

SPI FLASH

ALAZIA AUDIO
ALC3661

UNIVERSAL JACK

64Mb+32Mb

REAR LINE OUT
(RE-TASKING)

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

1

DP

23" LCD

TPA3131MP

SPK.
5W per
Channel

BLOCK DIAGRAM

BLOCK DIAGRAM

BLOCK DIAGRAM

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D D

Intel Processor

Haswell

LGA-1150 Pin Socket

Intel

Platform Controller Hub

Lynx Point

CK_100M_PE16/#

NVidia

GPU (N14E-GE)

CLKOUT_PEG_A_P/N

BCLK/#_0

SSC_DPLL_REF_CLK/#

SB_CK[0~1]/#

C C

SA_CK[0~1]/#

M_CHA_CLK[0~1]/#

M_CHB_CLK[0~1]/#

B B

DPLL_REF_CLK/#

BCLK_ITP_P/N

XMM1

XMM2

CPU XDP

PCH XDP

CK_100M_DMI/#

CK_135M_DP/#

CK_135M_DPNS/#

CK_100M_CPU_XDP

CLKOUT_DMI_P/N

CLKOUT_DP_P/N

CLKOUT_DPNS_P/N

CLKOUT_PCIE0_P/N

CLKOUT_PCIE1_P/N

CLKOUT_PCIE5_P/N

CLKOUT_PCIE2_P/N

CLKOUT_ITPXDP_P/N

CLKOUT_PCIE7_P/N

CLKOUTTFLEX2

HDA_BCLK

CLKOUTTFLEX3

CLKOUT_33MHZ2

SPI_CLK

CLKOUT_33MHZ3

CK_100M_PE1/#

CK_100M_PE2/#

CK_100M_PE2/#

RL_CK_100M_LAN/#

CK_48M_CR

AZ_BITCLK (24MHz)

CK_48M_SIO

CK_33M_SIO

SPI_CLK

CK_33M_DEBUG

PCIEx1 Slot(Half)

PCIEx1 Slot(Full)

PCIEx1 Slot(Full)

REALTEK

RTL8111GA

CARD READER

AUDIO CODEC ALC663

SIO IT8772E

SPI ROM

LPC Debug Header

25 MHz

CLKOUT_33MHZ4

CKKIN_PCILOOPBACK

CK_33M_PCIFB

XTAL25_IN RTCX

A A

32.768KHz25MHz

5

4

3

2

<CORE DESIGN>

<CORE DESIGN>

<CORE DESIGN>

PEGATRON DT-MB RESTRICTED SECRET

CLCOK DISTRIBUTION

CLCOK DISTRIBUTION

CLCOK DISTRIBUTION

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

IPPLP-TH

IPPLP-TH

IPPLP-TH

Engineer:

1

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

297Friday, January 17, 2014

297Friday, January 17, 2014

297Friday, January 17, 2014

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LAN 8111E

PERSTB

PCI_Express x 16

<23>PCIE_RST#

<23>PCIE_RST#

PWRGD

D D

PCI_Express x 1

PERST#

PCI_Express x 1

<23>PCIE_RST#

<23>PCIE_RST#

PCIE_RST#

PLTRST#

PERST#

<23>PCIE_RST#

<23>PCIE_RST#

EtronTech EJ168 USB3.0

P_RST_

Card Reader RTS5209-GR

PERST#

LPC DEBUG HEADER

<23>PLTRST_CPU#

Intel AMT 7.0 and DSW supported

RESET_SWITCH

PCH PROCESSOR

POWER_SWITCH

<4>PWRBTN#

ITE Tech SIO IT8772E

PANSWH#

PCIRST1#

HDA_RST#

AZ_RST#

RESET#

PCIRST#

C C

2X12 ATX PSU

<12>PSON#

PSON#

PWROK

B B

<14>ATX_PWRGD

PSON#

ATXPG_IN

LRESET#

KRST# RCIN#

RSMRST#

PWRON# PWRBTN#

SUSB#(S3#) SLP_S3#

SUSC#(S4#)

SUSWARN#

SUSACK#

DPWROK

RST_KB#

<7>RSMRST#

<4>SB_PWRBTN#

<11>SLP_S3#

<10>SLP_S4#

<8>SUS_WARN#

<9>SUS_ACK#

<3>PCH_DPWROK

<15>PWROK

<22>PLTRST#

PLTRST#

RSMRST#

SLP_S4#

SUSWARN#

SUSACK#

DPWROK

PWROK

DRAMPWROK

RTCRST#

PROCPWRGD

<1>RTCRST#

CPU SVID buffers are Hi-Z once +1P05V_CPUIO is
stable and UNCOREPWRGOOD = 0

PWRGD3

APWROK

<5>SLP_SUS#

SLP_SUS#

AUDIO

ALC663-VA4

SYS_RESET#

<16>DRAM_PWROK

BATTERY

<17>CPUPWRGD

<15~20>SVIDs

DBR#SYS_RESET#

RESET#

SM_DRAMPWROK

UNCOREPWRGOOD

VIDSOUT/VIDSCLK

VCORE

<13>

RT8204LGQW

ONBOARD POWER

STANDBY POWER

<6>

+5VSB

APWROK

SYS_PWROK

<21>VRM_PWRGD

+3P3VSB

A A

CHIP

<2>+5VA

RT8239CGQW

SOCKET or SLOT

5

4

3

Vcore Controller

VDIO/VCLK

VR_RDY

RT8859AGQW

VCORE

EN

2

<20>VCORE

<13>+1P05V_CPUIO

<CORE DESIGN>

<CORE DESIGN>

<CORE DESIGN>

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

IPPLP-TH

IPPLP-TH

IPPLP-TH

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

1

SIGNAL&RESET MAP

SIGNAL&RESET MAP

SIGNAL&RESET MAP

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Schematics Change History

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Version

Date

Comments

2012/11/19 PCIEX16 RVS(20121119_2100)

D D

C C

B B

A A

CAD Note:

Default component footprint is SMD 0402, Y5V, 5% type. Difference footprint show on schematics.
Property: BOM
I = Installed Part.
NI = Not Installed Part.

5

PROTO = PROTO Phase Only.
VP = Virtual Part.

4

3

2

<CORE DESIGN>

<CORE DESIGN>

<CORE DESIGN>

PEGATRON DT-MB RESTRICTED SECRET

CHANGE HISTORY

CHANGE HISTORY

CHANGE HISTORY

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

IPPLP-TH

IPPLP-TH

IPPLP-TH

Engineer:

1

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

497Friday, January 17, 2014

497Friday, January 17, 2014

497Friday, January 17, 2014

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Rev

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+12V_CPU

D D

+12VSA

C C

TPS51631+CSD97374
Vcore:3Phase

TPS51225
H/N-MOS 9mOhmx1
L/N-MOS 6mOhmx1

TPS51225
H/N-MOS 9mOhmx1
L/N-MOS 6mOhmx1

SPDT/Switch

18.62A

SPDT/Switch

14.6A

SPDT/Switch

SPDT/Switch

SPDT/Switch

SPDT/Switch

+VDD Imax=90A/TDC=120A (S0,S1)

+12V Imax=9A/TDC=6.3A (S0,S1)

+5VSB Imax=0.1A (S0~S5)

+5V_DUAL Imax=12.1A/TDC=8.5A
(S0,S1,S3)

+5V Imax=6.42A/TDC=4.5A (S0,S1)

+3P3VA Imax=0.44A/TDC=0.3A
(S0-S5)

+3P3V Imax=8.57A/TDC=6A
(S0,S1)

+3P3V_ME Imax=0.045A (S0,S1)

+3P3V_LAN Imax=0.188A (S0~S5)

SPDT/Switch

SPDT/Switch

B B

TPS51216
H/N-MOS 9mOhmx1
L/N-MOS 6mOhmx2

TPS51216

RT9025

RT9025

+3P3VSB Imax=5.4A/TDC=3.8A
(S0~S5)

+3P3V_BG Imax=0.028A (S0~S5)

+1P5V_DUAL Imax=11.74A/TDC=8.2A
(S0,S1,S3)

+VTT Imax=1.57A/TDC=1.1A (S0,S1)

+1P5V_PCH Imax=0.357A/TDC=0.258A
(S0,S1)

+1P50V_PCH Imax=1A/TDC=0.65A
(S0,S1)

+1P22V Imax=0.4A/TDC=0.28A
(S0,S1)

0.62A

A A

RT8153
H/N-MOS 9mOhmx2
L/N-MOS 6mOhmx2

5.3A

+NVVD Imax=37.5A/TDC=25A (S0,S1)

PEGATRON DT-MB RESTRICTED SECRET

POWER FLOW

POWER FLOW

POWER FLOW

Title :

Title :

Switching

SPDT/SwitchLinear

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

IPPLP-TH

IPPLP-TH

IPPLP-TH

Title :

Engineer:

Engineer:

Engineer:

1

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

597Friday, January 17, 2014

597Friday, January 17, 2014

597Friday, January 17, 2014

Rev

Rev

Rev

A00

A00

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D D

+VCORE

VDDQ

VCCST

+1P05V_PCH

+1P05V_PCH

-> 95A(TDC) - 65W

-> 4.2A(Imax) - W

-> 300mA(Imax) - W

PCH Lynx Point

-> 1.312A (VCC)- W

-> 0.306A(VCCCLK) - W

+12V

+3P3V

+3P3VSB

+12V

+3P3V

+3P3VSB

+1P05V_PCH

-> 3.629A(VCCIO) - W

CPU Sandy Bridge

C C

+1V_CPU2PCH

+1P05V_ME

-> 0.004A(V_PROC_IO) - W

-> 0.67A(VCCASW) - W

+3P3VSB

+1P05V_LAN

+1P5V_PCH

PCI Express x 1

-> 5A - 60W

-> 3A - 9.9W

WAKE -> 0.375A - 1.24W
No WAKE-> 20mA - 66mW

PCI Express x 16

-> 5.5A - 66W

-> 3.0A - 9.9W

WAKE -> 0.375A - 1.24W
No WAKE-> 20mA - 66mW

REALTEK 8111FA

-> 70mA - 231mW

-> 300mA - 315mW

+5V_DUAL_B/F

+5V

+12V

+3P3V_ME

Rear(USB3*4) -> 4A - 20W

Front(USB3*1 USB2*1) -> 2.5A - 12.5W

Internal(USB2) -> 3A - 15W

-> mA - mW

-> mA - mW

-> 1.2A - 14.4W

-> 40mA - 132mW

USB 12 PORTS

HDMI

FANS

SPI

-> 0.183A(VCCVRM) - W

+1P5V_PCH

+3P3V_BG

+3P3V

+3P3V

B B

+3P3V_ME

+3P3VSB

-> 0.0133A(VCC3_3) - W

-> 0.133A(VCC3_3) - W

-> 0.055A(VCCCLK3_3) - W

-> 0.022A(VCCSPI) - W

-> 0.261A(VCCSUS3_3) - W

-> 0.07A(VCCDAC1_5) - W

+3P3V

+5VSB

+3P3V

SIO IT8772E

-> 200mA - mW

ALC663 Codec

-> 45mA - 225mW

-> 25mA - 82.5mW

-> 0.01(VCCSUSHDA)A - W

+3P3VA

+BATT

A A

5

-> 0.015A(VCCDSW3_3) - W

RTC(G3) -> 6uA - 0.0198mW

<CORE DESIGN>

<CORE DESIGN>

<CORE DESIGN>

PEGATRON DT-MB RESTRICTED SECRET

POWER DISTRIBUTION

POWER DISTRIBUTION

POWER DISTRIBUTION

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

4

3

2

Date: Sheet of

IPPLP-TH

IPPLP-TH

IPPLP-TH

Engineer:

1

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

697Friday, January 17, 2014

697Friday, January 17, 2014

697Friday, January 17, 2014

Rev

Rev

Rev

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S5 to S0 Power Sequence

DPWROK
SLP_SUS#

+5VSB / +3P3VSB

D D

RSMRST#
SUSWARN#
SUSACK#
SLP_LAN#
SLP_A#
+1P05V_ME
SLP_S5#
SLP_S4#
SLP_S3#
APWROK

C C

+12V / +5V
+3P3V
+1P5V_DUAL

+1P05V_CPUIO

+1P8V_SFR
VCCSA_VID

+0P925V_SA

VCORE EN

B B

VIDSCLK / VIDSOUT

VIDALERT#

ATX_PWRGD

BCLK / PCIE CLOCKS

DRAM_PWROK

CPUPWRGD

+VCORE

VRM_PWRGD

A A

PLTRST#

5

DSW exit

30uS

30uS

>1mS

PSU: <=20mS

=500mS

=50mS

UNCOREPWRGOOD must be stable (low) at this time

CPU SVID buffers are Hi-Z once VCCIO is
stable and Uncorepowergood = 0

CPU SVID buffers are Hi-Z once VCCIO is
stable and Uncorepowergood = 0

PSU: 100ms~500ms

4

UNCOREPWRGOOD assertion

VCCSA_VID[0] FINAL

Recommended that +0P925V_SA ramp after +1P05V_CPUIO has ramped to ensure VCCSA_VID[0] is stable

<5mS

Typ 60uS

MISC ACK0/1...

Set VID
slow packet status packet

ACK0/1...

Get Reg

ACK0/1...

<600uS

<1uS

1mS

Min 10 PCIe BCLKs

<5uS

<2mS

3

2

+0P925V_SA FINAL

Pay
load

>400uS

5mS

<5mS

1~100mS

<CORE DESIGN>

<CORE DESIGN>

<CORE DESIGN>

PEGATRON DT-MB RESTRICTED SECRET

POWER SEQUENCE

POWER SEQUENCE

POWER SEQUENCE

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

IPPLP-TH

IPPLP-TH

IPPLP-TH

Engineer:

1

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

797Friday, January 17, 2014

797Friday, January 17, 2014

797Friday, January 17, 2014

Rev

Rev

Rev

A00

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M_CHA_DQ[0..63][15]

M_CHA_DQS0[15]
M_CHA_DQS0#[15]

D D

M_CHA_DQS1[15]
M_CHA_DQS1#[15]

M_CHA_DQS2[15]
M_CHA_DQS2#[15]

C C

M_CHA_DQS3[15]
M_CHA_DQS3#[15]

M_CHA_DQS4[15]
M_CHA_DQS4#[15]

B B

A A

5

M_CHA_DQS5[15]
M_CHA_DQS5#[15]

M_CHA_DQS6[15]
M_CHA_DQS6#[15]

M_CHA_DQS7[15]
M_CHA_DQS7#[15]

4

M_CHA_DQ0
M_CHA_DQ1
M_CHA_DQ2
M_CHA_DQ3
M_CHA_DQ4
M_CHA_DQ5
M_CHA_DQ6
M_CHA_DQ7

M_CHA_DQ8
M_CHA_DQ9
M_CHA_DQ10
M_CHA_DQ11
M_CHA_DQ12
M_CHA_DQ13
M_CHA_DQ14
M_CHA_DQ15

M_CHA_DQ16
M_CHA_DQ17
M_CHA_DQ18
M_CHA_DQ19
M_CHA_DQ20
M_CHA_DQ21
M_CHA_DQ22
M_CHA_DQ23

M_CHA_DQ24
M_CHA_DQ25
M_CHA_DQ26
M_CHA_DQ27
M_CHA_DQ28
M_CHA_DQ29
M_CHA_DQ30
M_CHA_DQ31

M_CHA_DQ32
M_CHA_DQ33
M_CHA_DQ34
M_CHA_DQ35
M_CHA_DQ36
M_CHA_DQ37
M_CHA_DQ38
M_CHA_DQ39

M_CHA_DQ40
M_CHA_DQ41
M_CHA_DQ42
M_CHA_DQ43
M_CHA_DQ44
M_CHA_DQ45
M_CHA_DQ46
M_CHA_DQ47

M_CHA_DQ48
M_CHA_DQ49
M_CHA_DQ50
M_CHA_DQ51
M_CHA_DQ52
M_CHA_DQ53
M_CHA_DQ54
M_CHA_DQ55

M_CHA_DQ56
M_CHA_DQ57
M_CHA_DQ58
M_CHA_DQ59
M_CHA_DQ60
M_CHA_DQ61
M_CHA_DQ62
M_CHA_DQ63

4

AE39
AE38

AD38
AD39

AF38

AF39
AD37
AD40

AF37

AF40

AJ39

AJ38
AH40

AH39
AK38
AK39
AH37
AH38
AK37
AK40

AN39
AN38

AM40
AM39
AP38
AP39
AM37
AM38
AP37
AP40

AV36
AU36

AV37

AW37

AU35
AV35
AT37
AU37
AT35

AW35

AV5

AW5

AY6
AU6
AV4
AU4

AW6

AV6

AW4

AY4

AP3
AP2

AR1
AR4
AN3
AN4
AR2
AR3
AN2
AN1

AK3
AK2

AL1
AL4
AJ3
AJ4
AL2
AL3
AJ2
AJ1

AF3
AF2

AG1
AG4
AE3
AE4
AG2
AG3
AE2
AE1

I

XU1A
LGA_1150P

SA_DQS0
SA_DQSN0

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7

SA_DQS1
SA_DQSN1

SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15

SA_DQS2
SA_DQSN2

SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23

SA_DQS3
SA_DQSN3

SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31

SA_DQS4
SA_DQSN4

SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39

SA_DQS5
SA_DQSN5

SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47

SA_DQS6
SA_DQSN6

SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55

SA_DQS7
SA_DQSN7

SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

DDR3_A

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8

SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15

SA_WE#
SA_CAS#
SA_RAS#

SA_BS0
SA_BS1
SA_BS2

SA_CS#0
SA_CS#1
SA_CS#2
SA_CS#3

SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3

SA_ODT0
SA_ODT1
SA_ODT2
SA_ODT3

SA_CK0

SA_CKN0

SA_CK1

SA_CKN1

SA_CK2

SA_CKN2

SA_CK3

SA_CKN3

SM_DRAMRST#

RSVD16
RSVD13
RSVD19

SA_DQS8

SA_DQSN8

SA_ECC_CB0
SA_ECC_CB1
SA_ECC_CB2
SA_ECC_CB3
SA_ECC_CB4
SA_ECC_CB5
SA_ECC_CB6
SA_ECC_CB7

AU13
AV16
AU16
AW17
AU17
AW18
AV17
AT18
AU18
AT19
AW11
AV19
AU19
AY10
AT20
AU21

AU11
AU9
AU12

AV12
AY11
AT21

AU14
AV9
AU10
AW8

AV22
AT23
AU22
AU23

AW10
AY8
AW9
AU8

AY15
AY16
AW15
AV15
AV14
AW14
AW13
AY13

AK22

AW12
AV20
AW27

AV32
AU32

AW33
AV33
AU31
AV31
AT33
AU33
AT31
AW31

3

3

M_CHA_MAA0
M_CHA_MAA1
M_CHA_MAA2
M_CHA_MAA3
M_CHA_MAA4
M_CHA_MAA5
M_CHA_MAA6
M_CHA_MAA7
M_CHA_MAA8
M_CHA_MAA9
M_CHA_MAA10
M_CHA_MAA11
M_CHA_MAA12
M_CHA_MAA13
M_CHA_MAA14
M_CHA_MAA15

M_CHA_WE# [15]
M_CHA_CAS# [15]
M_CHA_RAS# [15]

M_CHA_BA0 [15]
M_CHA_BA1 [15]
M_CHA_BA2 [15]

M_CHA_CS#0 [15]
M_CHA_CS#1 [15]

M_CHA_CKE0 [15]
M_CHA_CKE1 [15]

M_CHA_ODT0 [15]
M_CHA_ODT1 [15]

M_CHA_CLK0 [15]
M_CHA_CLK0# [15]
M_CHA_CLK1 [15]
M_CHA_CLK1# [15]

2

M_CHA_MAA[0..15] [15]

2

DDR3_DRAMRST# [15]

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

1

DDR3_A 1-6

DDR3_A 1-6

DDR3_A 1-6

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

897Friday, January 17, 2014

897Friday, January 17, 2014

897Friday, January 17, 2014

Rev

Rev

Rev

A00

A00

A00

Vinafix.com

5

M_CHB_DQ[0..63][16]

M_CHB_DQS0[16]
M_CHB_DQS0#[16]

D D

M_CHB_DQS1[16]
M_CHB_DQS1#[16]

M_CHB_DQS2[16]
M_CHB_DQS2#[16]

C C

M_CHB_DQS3[16]
M_CHB_DQS3#[16]

M_CHB_DQS4[16]
M_CHB_DQS4#[16]

B B

A A

5

M_CHB_DQS5[16]
M_CHB_DQS5#[16]

M_CHB_DQS6[16]
M_CHB_DQS6#[16]

M_CHB_DQS7[16]
M_CHB_DQS7#[16]

4

M_CHB_DQ0
M_CHB_DQ1
M_CHB_DQ2
M_CHB_DQ3
M_CHB_DQ4
M_CHB_DQ5
M_CHB_DQ6
M_CHB_DQ7

M_CHB_DQ8
M_CHB_DQ9
M_CHB_DQ10
M_CHB_DQ11
M_CHB_DQ12
M_CHB_DQ13
M_CHB_DQ14
M_CHB_DQ15

M_CHB_DQ16
M_CHB_DQ17
M_CHB_DQ18
M_CHB_DQ19
M_CHB_DQ20
M_CHB_DQ21
M_CHB_DQ22
M_CHB_DQ23

M_CHB_DQ24
M_CHB_DQ25
M_CHB_DQ26
M_CHB_DQ27
M_CHB_DQ28
M_CHB_DQ29
M_CHB_DQ30
M_CHB_DQ31

M_CHB_DQ32
M_CHB_DQ33
M_CHB_DQ34
M_CHB_DQ35
M_CHB_DQ36
M_CHB_DQ37
M_CHB_DQ38
M_CHB_DQ39

M_CHB_DQ40
M_CHB_DQ41
M_CHB_DQ42
M_CHB_DQ43
M_CHB_DQ44
M_CHB_DQ45
M_CHB_DQ46
M_CHB_DQ47

M_CHB_DQ48
M_CHB_DQ49
M_CHB_DQ50
M_CHB_DQ51
M_CHB_DQ52
M_CHB_DQ53
M_CHB_DQ54
M_CHB_DQ55

M_CHB_DQ56
M_CHB_DQ57
M_CHB_DQ58
M_CHB_DQ59
M_CHB_DQ60
M_CHB_DQ61
M_CHB_DQ62
M_CHB_DQ63

4

AF35
AF34

AE34
AE35
AG35
AH35
AD34
AD35
AG34
AH34

AL33

AK33

AL34
AL35

AK31

AL31
AK34
AK35
AK32

AL32

AP33
AN33

AN34
AP34
AN31
AP31
AN35
AP35
AN32
AP32

AN28
AN29

AM29
AM28
AR29
AR28

AL29

AL28
AP29
AP28

AN12
AN13

AR12
AP12

AL13

AL12
AR13
AP13
AM13
AM12

AP8

AR8

AR9
AP9
AR6

AP6
AR10
AP10

AR7

AP7

AL8

AM8
AM9

AL9

AL6

AL7
AM10

AL10

AM6
AM7

AG7
AG6

AH6
AH7

AE6

AE7

AJ6

AJ7

AF6

AF7

I

XU1B
LGA_1150P

SB_DQSP0
SB_DQSN0

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7

SB_DQSP1
SB_DQSN1

SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15

SB_DQSP2
SB_DQSN2

SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23

SB_DQSP3
SB_DQSN3

SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31

SB_DQSP4
SB_DQSN4

SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39

SB_DQSP5
SB_DQSN5

SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47

SB_DQSP6
SB_DQSN6

SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55

SB_DQSP7
SB_DQSN7

SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

SB_ECC_CB0
SB_ECC_CB1
SB_ECC_CB2
SB_ECC_CB3
SB_ECC_CB4
SB_ECC_CB5
SB_ECC_CB6
SB_ECC_CB7

DDR3_B

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8

SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15

SB_WE#
SB_CAS#
SB_RAS#

SB_BS0
SB_BS1
SB_BS2

SB_CS#0
SB_CS#1
SB_CS#2
SB_CS#3

SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3

SB_ODT0
SB_ODT1
SB_ODT2
SB_ODT3

SB_CK0

SB_CKN0

SB_CK1

SB_CKN1

SB_CK2

SB_CKN2

SB_CK3

SB_CKN3

RSVD7

SB_DQSP8
SB_DQSN8

AL19
AK23
AM22
AM23
AP23
AL23
AY24
AV25
AU26
AW25
AP18
AY25
AV26
AR15
AV27
AY28

AK16
AP16
AM18

AK17
AL18
AW28

AP17
AN15
AN17
AL15

AW29
AY29
AU28
AU29

AM17
AL16
AM16
AK15

AM20
AM21
AP22
AP21
AN20
AN21
AP19
AP20

AB39
AB40

AL20

AN25
AN26

AM26
AM25
AP25
AP26
AL26
AL25
AR26
AR25

3

M_CHB_MAA0
M_CHB_MAA1
M_CHB_MAA2
M_CHB_MAA3
M_CHB_MAA4
M_CHB_MAA5
M_CHB_MAA6
M_CHB_MAA7
M_CHB_MAA8
M_CHB_MAA9
M_CHB_MAA10
M_CHB_MAA11
M_CHB_MAA12
M_CHB_MAA13
M_CHB_MAA14
M_CHB_MAA15

12

HC1

0.022UF/16V

SB_VDQ_RC

X7R/+/-10%

I

12

HR1

24.9 OHM

1%

I

GND GND

NOTE:

Low pass filter to
cancel the noise during
switch
between CPU driven and
on board driven.

3

M_CHB_WE# [16]
M_CHB_CAS# [16]
M_CHB_RAS# [16]

M_CHB_BA0 [16]
M_CHB_BA1 [16]
M_CHB_BA2 [16]

M_CHB_CS#0 [16]
M_CHB_CS#1 [16]

M_CHB_CKE0 [16]
M_CHB_CKE1 [16]

M_CHB_ODT0 [16]
M_CHB_ODT1 [16]

M_CHB_CLK0 [16]
M_CHB_CLK0# [16]
M_CHB_CLK1 [16]
M_CHB_CLK1# [16]

12

HC2

0.022UF/16V

SA_VDQ_RC

X7R/+/-10%

I

12

HR2

24.9 OHM

1%

I

M_CHB_MAA[0..15] [16]

2

DIMM_DQ_VREF_A [15]
DIMM_DQ_VREF_B [16]

1

PEGATRON DT-MB RESTRICTED SECRET

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

1

DDR3_B 2-6

DDR3_B 2-6

DDR3_B 2-6

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

997Friday, January 17, 2014

997Friday, January 17, 2014

997Friday, January 17, 2014

Rev

Rev

Rev

A00

A00

A00

Vinafix.com

5

4

3

2

1

I

XU1C
LGA_1150P

E15

PEG_RXP0

F15

PEG_RXN0

D D

PEG_RXP[0..7][79]

PEG_RXN[0..7][79]

C C

B B

DMI_RXP0[19]
DMI_RXN0[19]

DMI_RXP1[19]
DMI_RXN1[19]

DMI_RXP2[19]
DMI_RXN2[19]

DMI_RXP3[19]
DMI_RXN3[19]

D14

PEG_RXP1

E14

PEG_RXN1

E13

PEG_RXP2

F13

PEG_RXN2

D12

PEG_RXP3

E12

PEG_RXN3

E11

PEG_RXP4

F11

PEG_RXN4

F10

PEG_RXP5

G10

PEG_RXN5

E9

PEG_RXP6

F9

PEG_RXN6

F8

PEG_RXP7

G8

PEG_RXN7

D3

PEG_RXP8

PEG_RXN7 PEG_TXN7
PEG_RXP6

PEG_RXN6
PEG_RXP5

PEG_RXN5
PEG_RXP4

PEG_RXN4
PEG_RXP3

PEG_RXN3
PEG_RXP2

PEG_RXN2
PEG_RXP1

PEG_RXN1
PEG_RXP0

PEG_RXN0

D4
E4

E5
F5

F6

G4
G5

H5
H6

J4
J5

K5
K6

L4
L5

U3
T3

U1
V1

W2

V2
Y3

W3

PEG_RXN8
PEG_RXP9

PEG_RXN9
PEG_RXP10

PEG_RXN10
PEG_RXP11

PEG_RXN11
PEG_RXP12

PEG_RXN12
PEG_RXP13

PEG_RXN13
PEG_RXP14

PEG_RXN14
PEG_RXP15

PEG_RXN15

DMI_RXP0
DMI_RXN0

DMI_RXP1
DMI_RXN1

DMI_RXP2
DMI_RXN2

DMI_RXP3
DMI_RXN3

PEG

DMI

PEG_TXP10
PEG_TXN10

PEG_TXP11
PEG_TXN11

PEG_TXP12
PEG_TXN12

PEG_TXP13
PEG_TXN13

PEG_TXP14
PEG_TXN14

PEG_TXP15
PEG_TXN15

PEG_RCOMP

PEG_TXP0
PEG_TXN0

PEG_TXP1
PEG_TXN1

PEG_TXP2
PEG_TXN2

PEG_TXP3
PEG_TXN3

PEG_TXP4
PEG_TXN4

PEG_TXP5
PEG_TXN5

PEG_TXP6
PEG_TXN6

PEG_TXP7
PEG_TXN7

PEG_TXP8
PEG_TXN8

PEG_TXP9
PEG_TXN9

DMI_TXP0
DMI_TXN0

DMI_TXP1
DMI_TXN1

DMI_TXP2
DMI_TXN2

DMI_TXP3
DMI_TXN3

A12
B12

B11
C11

C10
D10

B9
C9

C8
D8

B7
C7

A6
B6

B5
C5

E1

PEG_TXP7

E2
F2

PEG_TXP6

F3

PEG_TXN6

G1

PEG_TXP5

G2

PEG_TXN5

H2

PEG_TXP4

H3

PEG_TXN4

J1

PEG_TXP3

J2

PEG_TXN3

K2

PEG_TXP2

K3

PEG_TXN2

M2

PEG_TXP1

M3

PEG_TXN1

L1

PEG_TXP0

L2

PEG_TXN0

P3

H_PEG_RCOMP

AA4
AA5

AB3
AB4

AC5
AC4

AC1
AC2

+VCOMP_OUT

12

1%
I

PEG_TXP[0..7] [79]

PEG_TXN[0..7] [79]

HR4

24.9 OHM

NOTE:

W/S=12/15 mil, length<400mil

DMI_TXP0 [19]
DMI_TXN0 [19]

DMI_TXP1 [19]
DMI_TXN1 [19]

DMI_TXP2 [19]
DMI_TXN2 [19]

DMI_TXP3 [19]
DMI_TXN3 [19]

NOBOM
NOBOM

HT2
HT3

FDI_CSYNC[19]

CK_135M_DP#[21]
CK_135M_DP[21]

FDI_INT[19]

1

TP_CPU_RSVD_K11

1

TP_CPU_RSVD_J12

I

XU1D
LGA_1150P

D16

FDI_CSYNC

D18

DISP_INT

U5

SSC_DPLL_REF_CLKN

U6

SSC_DPLL_REF_CLKP

K11

RSVD_TP11

J12

RSVD_TP8

FDI

EDP_DISP_UTIL

DP

FDI_TX0N0
FDI_TX0P0

FDI_TX0N1
FDI_TX0P1

DP_RCOMP

DDIB_TXP0

DDIB_TXN0

DDIB_TXP1

DDIB_TXN1

DDIB_TXP2

DDIB_TXN2

DDIB_TXP3

DDIB_TXN3

DDIC_TXP0
DDIC_TXN0
DDIC_TXP1
DDIC_TXN1
DDIC_TXP2
DDIC_TXN2
DDIC_TXP3
DDIC_TXN3

DDID_TXP0
DDID_TXN0
DDID_TXP1
DDID_TXN1
DDID_TXP2
DDID_TXN2
DDID_TXP3
DDID_TXN3

B14
A14

C13
B13

E16

TP_EDP_DISP_UTIL

R4

CPU_DP_COMPPEG_RXP7

E17
F17
F18
G18
G19
H19
F20
G20

D19
E19
C20
D20
D21
E21
C22
D22

B15
C15
A16
B16
B17
C17
A18
B18

1

+VCOMP_OUT

12

HR3

24.9 OHM

1%
I

DP out

Scalar

HDMI OUT

HT1

NOBOM

DP_TXP0_RD_IN [60]
DP_TXN0_RD_IN [60]
DP_TXP1_RD_IN [60]
DP_TXN1_RD_IN [60]
DP_TXP2_RD_IN [60]
DP_TXN2_RD_IN [60]
DP_TXP3_RD_IN [60]
DP_TXN3_RD_IN [60]

HDMIC_TMDSC_DATA2 [51]
HDMIC_TMDSC_DATA2# [51]
HDMIC_TMDSC_DATA1 [51]
HDMIC_TMDSC_DATA1# [51]
HDMIC_TMDSC_DATA0 [51]
HDMIC_TMDSC_DATA0# [51]
HDMIC_TMDSC_CLK [51]
HDMIC_TMDSC_CLK# [51]

HDMI_TXP2 [57]

HDMI_TXN2 [57]
HDMI_TXP1 [57]

HDMI_TXN1 [57]

HDMI_TXP0 [57]

HDMI_TXN0 [57]
HDMI_CLKP [57]

HDMI_CLKN [57]

D1

RSVD_TP7
RSVD_TP5
RSVD_TP4
RSVD_TP1

A A

TP_H_RSVD_D1

C2

TP_H_RSVD_C2

B3

TP_H_RSVD_B3

A4

TP_H_RSVD_A4

1

HT4
HT5
HT6
HT7

NOBOM
NOBOM
NOBOM
NOBOM

1
1
1

PEGATRON DT-MB RESTRICTED SECRET

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

1

PCIE/DMI/DP 3-6

PCIE/DMI/DP 3-6

PCIE/DMI/DP 3-6

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

10 97Friday, January 17, 2014

10 97Friday, January 17, 2014

10 97Friday, January 17, 2014

Rev

Rev

Rev

A00

A00

A00

Vinafix.com

5

+1V_CPUIOOUT

12

HR12

90.9Ohm

1%

D D

NOTE:

C C

The 20 CFG[19:0] signals should be length matched as a
group to within 25ps of flight time.

Stub on these nets should be limited to
less than 50ps in length.

VIDSCLK[64]
VIDSOUT[64]
VIDALERT#[64]

1 2

XDP_PLTRST_CPU#[76]

PLTRST_CPU#[20]
CPUPWRGD[22]
DRAM_PWROK[22]

1 2

XDP_CPUPWRGD#[76]

R1 0 Ohm PROTO

PECI_SIO[44]

CATERR#[49]

PROCHOT#[44,64]

H_THMTRIP#[20,80]
PM_SYNC[20]
SKTOCC#[22]

PROTO

HR10 1K 1%

mx_r0402_small

12

I

12

HR18
10KOhm

1%

GND GND

GND GND

NOTE:

CFG[17:0] are internal PU

CFG[1:0]: Reserved configuration
lane.
CFG[2]: PCIE* Static x16 Lane
Numbering Reversal.
x1 = Normal operation
x0 = Lane numbers reversed.
CFG[3]: PCIE* Static x4 Lane
Numbering Reversal.
x1 = Normal operation

B B

x0 = Lane numbers reversed
CFG[4]: Reserved configuration
lane.
CFG[6:5]: PCIE* Bifurcation:
x00 = 1 x8, 2 x4 PCIE*
x01 = reserved
x10 = 2 x8 PCIE*
x11 = 1 x16 PCIE*
CFG[19:7]: Reserved configuration
lanes.

A A

HSW_STRAP[22,77]

5

PRIVACY_MSR_EN_N[76]

NI
NI

NI
NI
NI
NI
NI
NI
NI
NI
NI
NI

NI
NI
NI
NI
NI
NI

GND

CPU_CFG[0..15][76]

mx_r0402_small

HR29 1KOhm
HR30 1KOhm
HR31 1K 1%Imx_r0402_small
HR32 1KOhm
HR33 1KOhm
HR34 1KOhm
HR35 1KOhm
HR36 1KOhm
HR38 1KOhm
HR37 1KOhm
HR39 1KOhm
HR40 1KOhm
HR41 1KOhm

HR42 1KOhm
HR44 1KOhm
HR45 1KOhm
HR46 1KOhm
HR47 1KOhm
HR48 1KOhm

HSW_PCUSTB_DN1[76]
HSW_PCUSTB_DP1[76]
HSW_PCUSTB_DP0[76]
HSW_PCUSTB_DN0[76]

+3P3V

12

NI

HR57
1K

1%

NI

I

12

I

HC3
47PF/50V

NPO 5%

X7R/+/-10%
NI

12

NI

SC138
10PF/50V

NPO/+/-5%

GND

PROTO

SR633 1K 1%

12
12
12
12
12
12
12
12
12
12
12
12
12

12
12
12
12
12
12

NI

HR59
10K

1 2

12

HR5
110 Ohm

HC4

0.1UF/16V

H_CFG13

4

12

1%
I

+1P5V_DUAL

12

12

12

I

12

B

1

4

HR6
75 OHM

I

HR14

1.8KOHM

1%

I

HR19

3.3KOHM

1%

HR23
51 OHM

+3P3VSB

12

GND

1 2

HR13

44.2 OHM

1%
I

+1V_CPUIOOUT

12

PROTO

HR24
1K

1%
mx_r0402_small

NOBOM
NOBOM

NI

HR55
10K

H_CFG13#

3

C

NI

HQ2

E

PMBS3904

2

3

I

XU1E
LGA_1150P

AB35
AK21

W6
W5

C38
C37
B37

M39

V4
V5

BCLKN
BCLKP

DPLL_REF_CLKN
DPLL_REF_CLKP

VIDSCLK
VIDSOUT
VIDALERT#

RESET#
PWRGOOD
SM_DRAMPWROK

VCC_SENSE
VSS_SENSE

VCOMP_OUT

PWR_DEBUG

CK_100M_DMI#[21]
CK_100M_DMI[21]

CK_135M_DPNS#[21]
CK_135M_DPNS[21]

CPU_VIDALERT#

12

HR8
100 Ohm

NI

GND

NI

12

HC5
180PF/50V

NPO 5%

GND

VCC126

SM_VREF

TDO
TCK

TMS

TRST#
PRDY#

PREQ#

DBR#

E40
F40

P4
M8
AB38
N40

F39
F38

TDI

D39
E39
E37

L39
L37
G40

H_DBR#

VCC_SENSE [64]
VSS_SENSE [64]

+VCOMP_OUT

PROTO

+VCORE

1 2

HR20 0

MISC

G39

BPM#0

J39

N37

PECI

M36

CATERR#

K38

PROCHOT#

F37

THERMTRIP#

P36

PM_SYNC

D38

SKTOCC#

AA37
AA36

W38

AA34

W34

W36

Y38

V39
U39
U40
V38
T40
Y35

V37
Y34
U38

V35
Y37
Y36
V36

K8

J10

RSVD_TP19
RSVD_TP20

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG19
CFG18

3

1

TP_H_RSVD_K8

HT14

1

TP_H_RSVD_J10

HT16

CPU_CFG0
CPU_CFG1
CPU_CFG2
CPU_CFG3
CPU_CFG4
CPU_CFG5
CPU_CFG6
CPU_CFG7
CPU_CFG8
CPU_CFG9
CPU_CFG10
CPU_CFG11
CPU_CFG12
CPU_CFG13
CPU_CFG14
CPU_CFG15

12

NI

HR51
1K

HQ6_C

3

C

B

1

NI

E

HQ1

2

PMBS3904

GND

BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7

RSVD42
RSVD36

FC_K9
RSVD23
RSVD30
RSVD22
RSVD12

RSVD_TP21
RSVD_TP22

VSS478

VSS479
RSVD_TP13
RSVD_TP10

RSVD3
RSVD_TP3
RSVD_TP2

RSVD5

RSVD43

RSVD2

RSVD46
RSVD34
RSVD32
RSVD35
RSVD33
RSVD45
RSVD39
RSVD38
RSVD37

TESTLO_P6

TESTLO_N5

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

CFG_RCOMP

VSS420

RSVD
VSS418
VSS354
VSS414
VSS363

G38

TP_H_BPM#2

H37

TP_H_BPM#3

H38

TP_H_BPM#4

J38

TP_H_BPM#5

K39

TP_H_BPM#6

K37

TP_H_BPM#7

T35

TP_H_RSVD_T35

M38

TP_H_RSVD_M38

K9
H15

TP_H_RSVD_H15

J9

TP_H_RSVD_J9

H14

TP_H_RSVD_H14

AV2

TP_H_RSVD_AV2

J16

TP_H_RSVD_J16

H16

TP_H_RSVD_H16

V7

TP_H_RSVD_V7

AB6

TP_H_RSVD_AB6

K13

TP_H_RSVD_K13

J8

TP_H_RSVD_J8

AB36

TP_H_RSVD_AB36

AW2

TP_H_RSVD_AW2

AV1

TP_H_RSVD_AV1

AC8

TP_H_RSVD_AC8

U8

TP_H_RSVD_U8

AB33

TP_H_RSVD_AB33

Y8

TP_H_RSVD_Y8

M10

TP_H_RSVD_M10

L10

TP_H_RSVD_L10

M11

TP_H_RSVD_M11

L12

TP_H_RSVD_L12

W8

TP_H_RSVD_W8

R33

TP_H_RSVD_R33

P33

TP_H_RSVD_P33

N35

1P05V_PECI_VCOM

P6

CPU_TESTLOW1

N5

CPU_TESTLOW2

R1

CPU_SM_RCOMP_0

P1

CPU_SM_RCOMP_1

R2

CPU_SM_RCOMP_2

H40

H_CFG_RCOMP

N39
T8
N33
J11
M9
J7

1
1
1
1
1
1

1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1

TP_VSS_T8

NOTE: NC on pin T8

+1P05V_PCH

12

12

GND

HT8
HT9
HT10
HT11
HT12
HT13

HT15
HT17

HT18
HT19
HT20
HT21
HT22
HT23
HT24
HT25
HT26
HT27
HT28
HT29
HT30
HT31
HT32
HT33
HT34
HT35
HT36
HT37
HT38
HT39
HT40
HT41

HR50 49.9 OHM1%I
HR52 49.9 OHM1%I

HR53 100 Ohm 1%I
HR54 75 OHM 1%I
HR56 100 Ohm 1%I

HT42

2

HR7
150 Ohm

1%
I

HR15
10KOhm

NI

NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM

NOBOM
NOBOM

NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM

1 2
1 2

1 2
1 2
1 2

NOBOM

2

1 2

HR9 0

NI

+1V_CPUIOOUT

H_PRDY# [76]
H_PREQ# [76]
SYS_RESET# [22,50,76,77]

HSW_XDP_MBP0 [76]
HSW_XDP_MBP1 [76]

+1V_VCCST

HR49

0 OhmNI

12

1%
I

GNDGND

+1P05V_PCH

12

GND

HR58

49.9 OHM

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

H_SM_VREF [16]
XDP_PWR_DEBUG [76]

12

12

HR16
51 OHM

NI

HR21
51 OHM

PROTO

GNDGND

12

12

HR17
51 OHM

NI

HR22
51 OHM

PROTO

TDO [76]
TDI [76]
TCK [76]
TMS [76]
TRST# [76]

NOTE:

Place near CPU

HC6

1 2

0.1UF/16V

NI

GND

PEGATRON DT-MB RESTRICTED SECRET

Title :

Title :

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Title :

Engineer:

Engineer:

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

1

MISC 4-6

MISC 4-6

MISC 4-6

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

11 97Friday, January 17, 2014

11 97Friday, January 17, 2014

11 97Friday, January 17, 2014

Rev

Rev

Rev

A00

A00

A00

Vinafix.com

5

I

XU1F
LGA_1150P

RSVD1

VCC21
VCC23
VCC97
VCC96
VCC86
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC83
VCC85
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93

VCC116

VCC94

VCC95
VCC100
VCC101
VCC102
VCC103
VCC104
VCC105
VCC106
VCC107
VCC108
VCC109
VCC110
VCC111
VCC113
VCC114
VCC118
VCC117
VCC119
VCC120
VCC121
VCC122
VCC123
VCC124
VCC125

VDDQ1

VDDQ2

VDDQ3

VDDQ4

VDDQ5

VDDQ6

VDDQ7

VDDQ8

VDDQ9

VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VDDQ22
VDDQ23
VDDQ24
VDDQ25
VDDQ26

L40
AB8

C31
C33
L16
L15
J35
H33
H35
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
J32
J34
K19
K21
K23
K25
K27
K29
K31
M13
K33
K35
L19
L20
L21
L22
L23
L24
L25
L26
L27
L28
L29
L30
L32
L33
M17
M15
M19
M21
M23
M25
M27
M29
M33

AJ12
AJ13
AJ15
AJ17
AJ20
AJ21
AJ24
AJ25
AJ28
AJ29
AJ9
AT17
AT22
AU15
AU20
AU24
AV10
AV11
AV13
AV18
AV23
AV8
AW16
AY12
AY14
AY9

VCCIO_OUT

D D

VCC 70A

C C

B B

A A

+VCORE

+VCORE

G33
B25
B27
B29
B31

B33
G31
B35
C24
C25
C26
C27
C28
C29
C30
C32
C34
C35
D25
D27
D29
D31
E33
D33
E31
D35
E24
E25
E26
E27
E28
E29
E30
E32
E34

E35

G22
G23
G24
G25
G26
G27
G28
G29
G30
G32
G34
G35
H23
H25
H27
H29
H31

L31
L18
L17
J33
A24
A25
A26
A27
A28
A29
A30

J31

F23
F25
F27
F29
F31

F33
F35

L34

P8

VCC127

VCC112
VCC99
VCC98
VCC84
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC62
VCC8
VCC9
VCC10
VCC11
VCC82
VCC12
VCC60
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC22
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC41
VCC30
VCC39
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC40
VCC42
VCC44
VCC45
VCC46
VCC47
VCC48
VCC43
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC61
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC115

+1V_CPUIOOUT

VCCIO_OUT 300mA

R_+1V_CPU2PCH

12

+VCORE

+1P5V_DUAL

X5R/+/-10%
mx_c0603

GND

+1P05V_PCH

VDDQ 4.2A

HR60

1 2

0 Ohm NI

NI

HCB1

4.7UF/6.3V

VP

VP

4

+1V_VCCST

VCCIO2PCH 100mA

+1V_CPU2PCH+1V_VCCST

12

R2 0

mx_r0603

mx_r0603

12

R3 0

+1V_CPU2PCH

GND

12

NI

SCB1

0.1UF/16V

GND

12

NI

SCB2

0.1UF/16V

3

I

XU1G
LGA_1150P

A13

GND

A15
A17
A23
A11

AA3
AA33
AA35
AA38

AA6

AA7

AA8
AB34

AB37

AB5

AB7

AC3
AC33
AC34
AC35
AC36
AC37
AC38
AC39
AC40

AC6

AC7

AD1

AD2

AD3
AD33
AD36

AD4

AD5

AD6

AD7

AD8
AE33
AE36
AE37
AE40

AE5

AE8

AF1
AF33
AF36

AF4

AF5

AF8
AG33
AG36
AG37
AG38
AG39
AG40

AG5

AG8

AH1

AH2

AH3
AH33
AH36

AH4

AH5

AH8

AJ11
AJ14
AJ16
AJ18
AJ19
AJ22
AJ23
AJ26
AJ27
AJ30
AJ31
AJ32
AJ33

VSS2
VSS3
VSS4
VSS5
VSS1
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14

A5

VSS6
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29

A7

VSS7
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161

AJ34
AJ35
AJ36
AJ37
AJ40
AJ5
AJ8
AK1
AK10
AK11
AK12
AK13
AK14
AK18
AK19
AK24
AK25
AK26
AK27
AK28
AK29
AK30
AK36
AK4
AK5
AK6
AK7
AK8
AK9
AL11
AL14
AL17
AL21
AL22
AL24
AL27
AL30
AL36
AL37
AL38
AL39
AL40
AL5
AM1
AM11
AM14
AM15
AM19
AM2
AM24
AM27
AM3
AM30
AM31
AM32
AM33
AM34
AM35
AM36
AM4
AM5
AN10
AN11
AN14
AN16
AN18
AN19
AN22
AN23
AN24
AN27
AN30
AN36
AN37
AN40
AN5
AN6
AN7
AN8
AN9
AP1

2

I

XU1H
LGA_1150P

AP11

GND

GND

AP14
AP15
AP24
AP27
AP30
AP36

AP4

AP5
AR11
AR14
AR16
AR17
AR18
AR19
AR20
AR21
AR22
AR23
AR24
AR27
AR30
AR31
AR32
AR33
AR34
AR35
AR36
AR37
AR38
AR39
AR40

AR5

AT1

AT10
AT11
AT12
AT13
AT14
AT15
AT16

AT2

AT24
AT25
AT26
AT27
AT28
AT29

AT3

AT30
AT32
AT34
AT36
AT38
AT39

AT4

AT5

AT6

AT7

AT8

AT9

AU2
AU25

AU3
AU30
AU34
AU38

AU5

AU7

AV21
AV28

AV3

AV30
AV34
AV38

AV7
AW26

AW3

AW30

VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240

VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS254
VSS255
VSS256
VSS257
VSS259
VSS260
VSS261
VSS262
VSS272
VSS273
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS271
VSS252
VSS253
VSS270
VSS291
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS301
VSS302
VSS292
VSS293
VSS297
VSS294
VSS295
VSS296
VSS298
VSS299
VSS258
VSS300
VSS303
VSS314
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS315
VSS316
VSS317
VSS284
VSS318
VSS332
VSS319

AW32
AW34
AW36
AW7
AY17
AY23
AY26
AY27
AY30
AY5
AY7
B24
B26
B28
B30
B34
B36
B4
B8
C4
C6
C12
C14
C16
C18
C19
C21
C23
C36
B10
B23
C3
D9
D11
D13
D15
D17
D2
D23
D24
D26
D28
D30
D34
D36
D37
D5
D6
D7
E7
E8
E10
E18
E3
E20
E22
E23
E36
E38
B32
E6
F1
F32
F12
F14
F16
F19
F21
F22
F24
F26
F28
F30
F34
F36
F4
D32
F7
G9
G11

1

GND

PEGATRON DT-MB RESTRICTED SECRET

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

1

VCC 5 - 6

VCC 5 - 6

VCC 5 - 6

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

12 97Friday, January 17, 2014

12 97Friday, January 17, 2014

12 97Friday, January 17, 2014

Rev

Rev

Rev

A00

A00

A00

Vinafix.com

5

4

3

2

1

I

XU1I
LGA_1150P

G12

VSS320

G13

VSS321

G14

VSS322

G16

VSS324

D D

C C

B B

H11
G17
G21

H13
H22
H32
G36
G37

G15
H10

H17
H18
H20
H21
H24
H26
H28
H30
H34
H36
H39

K10
K14

K18
K20
K22
K24
K26
K28
K30
K34
K36

K40

K17
M12
M14
M18
M16
M20
M22
M24
M26
M28
M30
M32
M34
M37

VSS335
VSS325
VSS326

G3

VSS327
VSS336
VSS341
VSS346
VSS328
VSS329

G6

VSS330

G7

VSS331
VSS323

H1

VSS333
VSS334
VSS337
VSS338
VSS339
VSS340
VSS342
VSS343
VSS344
VSS345
VSS347
VSS348
VSS349

H4

VSS350

H7

VSS351

H8

VSS352

H9

VSS353

J19

VSS357

J20

VSS358

J3

VSS359

J18

VSS356
VSS365
VSS366

J36

VSS360

J37

VSS361

J6

VSS362

K1

VSS364
VSS370
VSS371
VSS372
VSS373
VSS374
VSS375
VSS376
VSS378
VSS379

K4

VSS380
VSS381

K7

VSS382

L7

VSS391

L8

VSS392

L9

VSS393

L11

VSS383

L3

VSS386

L13

VSS384

L14

VSS385

L35

VSS387

L38

VSS389

L6

VSS390

M1

VSS394
VSS369
VSS395
VSS396
VSS398
VSS397
VSS399
VSS400
VSS401
VSS402
VSS403
VSS404
VSS405
VSS406
VSS408

VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8

VSS409
VSS410
VSS411
VSS412
VSS413
VSS367
VSS368
VSS415
VSS416
VSS417
VSS423
VSS419
VSS421
VSS422
VSS377
VSS425
VSS426
VSS428
VSS431
VSS432
VSS424
VSS433
VSS388
VSS434
VSS438
VSS439
VSS440
VSS441
VSS443
VSS444
VSS445
VSS407
VSS449
VSS450
VSS451
VSS452
VSS453
VSS442
VSS455
VSS456
VSS457
VSS460
VSS461
VSS462
VSS427
VSS463
VSS464
VSS466
VSS467
VSS468
VSS469
VSS470
VSS471
VSS472
VSS473
VSS474

VSS475
VSS476
VSS477
VSS480

M4
M40
M5
M6
M7
K15
K16
N1
N2
N3
N7
N34
N4
N6
K32
P2
P34
P38
P5
P7
N8
R3
L36
R35
R40
R5
R6
R7
T1
T2
T33
M35
T39
T4
T5
T6
T7
R8
U2
U33
U34
U37
U4
U7
P35
V3
V33
V40
V6
V8
W1
W33
W35
W37
W4
W7

Y33
Y4
Y5
Y6

AU40
AV39
AW38
AY3
B38
B39
C40
D40

GND

I

ILM1

PT44A69-6411

12

VCCST_PWROKVCCST_PWROKVCCST_PWROK

1%

PWROK[20,22,44]

R46.04KOHM

I

EMI

1%

12

R5

2.67KOHM

I

1 2

GND GND

NI

C1
470PF/50V

X7R 10%

NOTE:

The resistirs need near the CPU pin (Within 1.5")

NI

BP1

1

NP_NC1

3

NP_NC3

INTEL_1156_BP

AY18
AW24
AW23

AV29

AV24

AU39

AU27

AU1
AT40
AK20

T34

R34

H12

Y7

J40
J17
J15

1
2
3
4
5
6
7

I

XU1J
LGA_1150P

RSVD20
RSVD18
RSVD17
RSVD15
RSVD14
RSVD11
RSVD10
RSVD9
RSVD8
RSVD6
FC_Y7
RSVD41
RSVD40
RSVD29
RSVD28
RSVD26
RSVD21

NP_NC1
NP_NC2
NP_NC3
NP_NC4
NP_NC5
NP_NC6
NP_NC7

RSVD_TP12

RSVD_TP9

RSVD_TP16
RSVD_TP15

RSVD_TP17

RSVD_TP6

RSVD_TP14

VSS458
VSS430

VSS436
VSS447
VSS465

VSS437
VSS448

VSS459
VSS429

VSS446
VSS435

VSS355

NP_NC2

NP_NC4

K12
J13

P37
N38

R36
C39

N36

U35
P40

R38
T37
V34

R39
T38

U36
P39

T36
R37

J14

2

1
1

GND

NOTE: (CPU)

Part

HT45

NOBOM

HT46

NOBOM

Standard

PE115027_4041_01F_INTEL

mx_socket_1150p
(with 4 screws)

Symbol

4

GND

A A

PEGATRON DT-MB RESTRICTED SECRET

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

1

VSS 6 - 6

VSS 6 - 6

VSS 6 - 6

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

13 97Friday, January 17, 2014

13 97Friday, January 17, 2014

13 97Friday, January 17, 2014

Rev

Rev

Rev

A00

A00

A00

Vinafix.com

5

D D

C C

4

3

2

1

+3P3V +3P3V

B B

GPU_DEBUG_VGA_BLU[80]

12

NI

VR32
150

1%

GND

A A

GPU_HSYNC[80]

GPU_DDCVGACLK[80]

12

VR27

2.2KOHM

NI

17

SIDE1

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

SIDE2

WtoB_CON_2X8P

GND GND

J214

1
3
5
7

9
11
13
15

NI

+5V

1
3
5
7
9
11
13
15

12

VR39

2.2KOHM

NI

GPU_VSYNC [80]

GPU_DDCVGADATA [80]

GPU_DEBUG_VGA_GRN [80]

12

NI

VR37
150

1%

GND

GPU_DEBUG_VGA_RED [80]

12

NI

VR38
150

1%

GND

PEGATRON DT-MB RESTRICTED SECRET

VGA DEBUG

VGA DEBUG

1

VGA DEBUG

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

14 97Friday, January 17, 2014

14 97Friday, January 17, 2014

14 97Friday, January 17, 2014

Rev

Rev

Rev

A00

A00

A00

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

Vinafix.com

5

4

3

2

1

XMM1 9.2H(STD)

D D

I

DIMM1A

GND

GND

12

NI

SC2
150PF/50V

NPO 5%
mx_c0402_small

GNDGND

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12/BC#

119

A13

80

A14

78

A15

102

CK1

104

CK1#

101

CK0

103

CK0#

121

S1#

114

S0#

120

ODT1

116

ODT0

113

WE#

110

RAS#

115

CAS#

79

BA2

108

BA1

109

BA0

74

CKE1

73

CKE0

201

SA1

197

SA0

188

DQS7

186

DQS#7

171

DQS6

169

DQS#6

154

DQS5

152

DQS#5

137

DQS4

135

DQS#4

64

DQS3

62

DQS#3

47

DQS2

45

DQS#2

29

DQS1

27

DQS#1

12

DQS0

10

DQS#0

187

DM7

170

DM6

153

DM5

136

DM4

63

DM3

46

DM2

28

DM1

11

DM0

202

SCL

200

SDA

DDR3_DIMM_204P

0

1

2

3

4

5

6

7

M_CHA_MAA0
M_CHA_MAA1
M_CHA_MAA2
M_CHA_MAA3
M_CHA_MAA4
M_CHA_MAA5
M_CHA_MAA6
M_CHA_MAA7
M_CHA_MAA8
M_CHA_MAA9
M_CHA_MAA10
M_CHA_MAA11
M_CHA_MAA12
M_CHA_MAA13
M_CHA_MAA14
M_CHA_MAA15

M_CHA_CLK1[8]
M_CHA_CLK1#[8]
M_CHA_CLK0[8]
M_CHA_CLK0#[8]

M_CHA_CS#1[8]

C C

B B

9,60,76,77]
9,60,76,77]

A A

SMB_CLK_RESUME
SMB_DATA_RESUME

M_CHA_CS#0[8]
M_CHA_ODT1[8]

M_CHA_ODT0[8]
M_CHA_WE#[8]

M_CHA_RAS#[8]
M_CHA_CAS#[8]

M_CHA_BA2[8]
M_CHA_BA1[8]
M_CHA_BA0[8]

M_CHA_CKE1[8]
M_CHA_CKE0[8]

M_CHA_DQS7[8]
M_CHA_DQS7#[8]
M_CHA_DQS6[8]
M_CHA_DQS6#[8]
M_CHA_DQS5[8]
M_CHA_DQS5#[8]
M_CHA_DQS4[8]
M_CHA_DQS4#[8]
M_CHA_DQS3[8]
M_CHA_DQS3#[8]
M_CHA_DQS2[8]
M_CHA_DQS2#[8]
M_CHA_DQS1[8]
M_CHA_DQS1#[8]
M_CHA_DQS0[8]
M_CHA_DQS0#[8]

NI

SC1

150PF/50V

NPO 5%

mx_c0402_small

12

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

RESET#

5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194

30

M_CHA_DQ5
M_CHA_DQ4
M_CHA_DQ2
M_CHA_DQ3
M_CHA_DQ1
M_CHA_DQ0
M_CHA_DQ7
M_CHA_DQ6
M_CHA_DQ8
M_CHA_DQ9
M_CHA_DQ10
M_CHA_DQ11
M_CHA_DQ13
M_CHA_DQ12
M_CHA_DQ14
M_CHA_DQ15
M_CHA_DQ16
M_CHA_DQ17
M_CHA_DQ19
M_CHA_DQ18
M_CHA_DQ21
M_CHA_DQ20
M_CHA_DQ23
M_CHA_DQ22
M_CHA_DQ25
M_CHA_DQ24
M_CHA_DQ26
M_CHA_DQ27
M_CHA_DQ28
M_CHA_DQ29
M_CHA_DQ30
M_CHA_DQ31
M_CHA_DQ36
M_CHA_DQ37
M_CHA_DQ38
M_CHA_DQ35
M_CHA_DQ32
M_CHA_DQ33
M_CHA_DQ39
M_CHA_DQ34
M_CHA_DQ40
M_CHA_DQ41
M_CHA_DQ43
M_CHA_DQ47
M_CHA_DQ44
M_CHA_DQ45
M_CHA_DQ46
M_CHA_DQ42
M_CHA_DQ49
M_CHA_DQ48
M_CHA_DQ55
M_CHA_DQ54
M_CHA_DQ52
M_CHA_DQ53
M_CHA_DQ51
M_CHA_DQ50
M_CHA_DQ61
M_CHA_DQ60
M_CHA_DQ56
M_CHA_DQ57
M_CHA_DQ63
M_CHA_DQ62
M_CHA_DQ59
M_CHA_DQ58

12

D3CB6

0.1UF/6.3V

MLCC/+/-10%

GND

I

0~7

8~15

16~23

24~31

32~39

40~47

48~55

56~63

DDR3_DRAMRST#_R [16]

HR61

1 2

0Ohm

5%
NOBOM

M_CHA_MAA[0..15] [8]
M_CHA_DQ[0..63] [8]

DIMM_CA_VREF_A[16]
DIMM_DQ_VREF_A[9]

DDR3_DRAMRST# [8]

1 2

12

GND

+1P5V_DUAL

R6

NI

C3
10UF/6.3V

GND

12

2OHMI

12

I

D3R1
1KOhm

1%

I

D3R3
1KOhm

1%

12

I

D3CB3

0.1UF/6.3V

MLCC/+/-10%

+1P5V_DUAL

12

12

GNDGND

I

D3R2
1K

1%
mx_r0402_small

I

D3R4
1K

1%
mx_r0402_small

DIMM_DQ_VREF_A_R

12

I

D3CB5

0.1UF/6.3V

MLCC/+/-10%

GND

GND

I

DIMM1B

75

VDD1

81

VDD3

87

VDD5

93

VDD7

99

VDD9

105

VDD11

111

VDD13

117

VDD15

123

VDD17

2

VSS1

8

VSS3

13

VSS5

19

VSS7

25

VSS9

31

VSS11

37

VSS13

43

VSS15

48

VSS17

54

VSS19

60

VSS21

65

VSS23

71

VSS25

127

VSS27

133

VSS29

138

VSS31

144

VSS33

150

VSS35

155

VSS37

161

VSS39

167

VSS41

172

VSS43

178

VSS45

184

VSS47

189

VSS49

195

VSS51

198

EVENT#

125

TEST

77

NC1

122

NC2

126

VREFCA

1

VREFDQ

DDR3_DIMM_204P

VDD2
VDD4
VDD6

VDD8
VDD10
VDD12
VDD14
VDD16
VDD18

VSS2
VSS4
VSS6

VSS8
VSS10
VSS12
VSS14
VSS16
VSS18
VSS20
VSS22
VSS24
VSS26
VSS28
VSS30
VSS32
VSS34
VSS36
VSS38
VSS40
VSS42
VSS44
VSS46
VSS48
VSS50
VSS52

GND1
GND2

NP_NC1
NP_NC2

VTT1

VTT2

VDDSPD

76
82
88
94
100
106
112
118
124

3
9
14
20
26
32
38
44
49
55
61
66
72
128
134
139
145
151
156
162
168
173
179
185
190
196

207
208

205
206

203
204

199

C300

10PF/50V

NPO/+/-5%

+1P5V_DUAL+1P5V_DUAL

+VTT_DDR

GND

+3P3V

I

12

C301

10PF/50V

GND

NPO/+/-5%

12

12

D3CB4

0.1UF/6.3V

MLCC/+/-10%

GND

I

GND

I

D3CB1

0.1UF/6.3V

MLCC/+/-10%

12

I

D3CB2

4.7UF/6.3V

MLCC/+/-10%

12

I

GNDGND

PEGATRON DT-MB RESTRICTED SECRET

DDR3 CHANNEL A

DDR3 CHANNEL A

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

DDR3 CHANNEL A

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

1

Rev

Rev

Rev

A00

A00

15 97Friday, January 17, 2014

15 97Friday, January 17, 2014

15 97Friday, January 17, 2014

A00

Vinafix.com

5

XMM2 5.2H(STD)

D D

I

DIMM2A

M_CHB_MAA0
M_CHB_MAA1
M_CHB_MAA2
M_CHB_MAA3
M_CHB_MAA4
M_CHB_MAA5
M_CHB_MAA6
M_CHB_MAA7
M_CHB_MAA8
M_CHB_MAA9
M_CHB_MAA10
M_CHB_MAA11
M_CHB_MAA12
M_CHB_MAA13
M_CHB_MAA14
M_CHB_MAA15

M_CHB_CLK1[9]
M_CHB_CLK1#[9]
M_CHB_CLK0[9]
M_CHB_CLK0#[9]

M_CHB_CS#1[9]

C C

+3P3V

B B

9,60,76,77]
9,60,76,77]

A A

SMB_CLK_RESUME
SMB_DATA_RESUME

M_CHB_CS#0[9]
M_CHB_ODT1[9]

M_CHB_ODT0[9]
M_CHB_WE#[9]

M_CHB_RAS#[9]
M_CHB_CAS#[9]

M_CHB_BA2[9]
M_CHB_BA1[9]
M_CHB_BA0[9]

M_CHB_CKE1[9]
M_CHB_CKE0[9]

NI

12

SC3
150PF/50V

NPO 5%
mx_c0402_small

5

GND

M_CHB_DQS7[9]
M_CHB_DQS7#[9]
M_CHB_DQS6[9]
M_CHB_DQS6#[9]
M_CHB_DQS5[9]
M_CHB_DQS5#[9]
M_CHB_DQS4[9]
M_CHB_DQS4#[9]
M_CHB_DQS3[9]
M_CHB_DQS3#[9]
M_CHB_DQS2[9]
M_CHB_DQS2#[9]
M_CHB_DQS1[9]
M_CHB_DQS1#[9]
M_CHB_DQS0[9]
M_CHB_DQS0#[9]

98
97
96
95
92
91
90
86
89
85

107

84
83

119

80
78

102
104
101
103

121
114

120
116

113
110
115

79
108
109

74

73
201

197

188
186
171
169
154
152
137
135

64

62

47

45

29

27

12

10
187

170
153
136

63

46

28

11
202

200

DDR3_DIMM_204P

GND

12

NI

SC4
150PF/50V

NPO 5%
mx_c0402_small

GNDGND

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15

CK1
CK1#
CK0
CK0#

S1#
S0#

ODT1
ODT0

WE#
RAS#
CAS#

BA2
BA1
BA0

CKE1
CKE0

SA1
SA0

DQS7
DQS#7
DQS6
DQS#6
DQS5
DQS#5
DQS4
DQS#4
DQS3
DQS#3
DQS2
DQS#2
DQS1
DQS#1
DQS0
DQS#0

DM7
DM6
DM5
DM4
DM3
DM2
DM1
DM0

SCL
SDA

0

1

2

3

4

5

6

7

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

RESET#

5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194

30

M_CHB_DQ1
M_CHB_DQ0
M_CHB_DQ2
M_CHB_DQ3
M_CHB_DQ4
M_CHB_DQ5
M_CHB_DQ6
M_CHB_DQ7

M_CHB_DQ8
M_CHB_DQ9
M_CHB_DQ10
M_CHB_DQ11
M_CHB_DQ12
M_CHB_DQ13
M_CHB_DQ14

M_CHB_DQ15
M_CHB_DQ16
M_CHB_DQ17
M_CHB_DQ18
M_CHB_DQ19
M_CHB_DQ20
M_CHB_DQ21
M_CHB_DQ22
M_CHB_DQ23

M_CHB_DQ24

M_CHB_DQ25

M_CHB_DQ26

M_CHB_DQ27

M_CHB_DQ28

M_CHB_DQ29

M_CHB_DQ30

M_CHB_DQ31
M_CHB_DQ32
M_CHB_DQ33
M_CHB_DQ34
M_CHB_DQ35
M_CHB_DQ36
M_CHB_DQ37
M_CHB_DQ38
M_CHB_DQ39

M_CHB_DQ40

M_CHB_DQ41

M_CHB_DQ42

M_CHB_DQ43

M_CHB_DQ44

M_CHB_DQ45

M_CHB_DQ46

M_CHB_DQ47
M_CHB_DQ48
M_CHB_DQ49
M_CHB_DQ50
M_CHB_DQ51
M_CHB_DQ52
M_CHB_DQ53
M_CHB_DQ54
M_CHB_DQ55

M_CHB_DQ56

M_CHB_DQ57

M_CHB_DQ58

M_CHB_DQ59

M_CHB_DQ60

M_CHB_DQ61

M_CHB_DQ62

M_CHB_DQ63

GND

4

12

I

D3CB11

0.1UF/6.3V

MLCC/+/-10%

4

0~7

8~15

16~23

24~31

32~39

40~47

48~55

56~63

M_CHB_MAA[0..15] [9]
M_CHB_DQ[0..63] [9]

DIMM_CA_VREF_B[16]
DIMM_DQ_VREF_B[9]

DDR3_DRAMRST#_R [15]

R7 2OHMI

GND

12

12

GND

+1P5V_DUAL

NI

C7
10UF/6.3V

1 2

I

C8
10UF/6.3V

3

+1P5V_DUAL

12

I

D3CB10

0.1UF/6.3V

MLCC/+/-10%

12

I

D3R6
1K

1%
mx_r0402_small

12

I

D3R8
1K

1%
mx_r0402_small

GNDGND

R8 2OHMI

GND

1 2

12

I

C11

0.022UF/16V

MLCC/+/-10%

12

I

R9

24.9 OHM

1%

DIMM_DQ_VREF_B_R

12

I

C9
10UF/6.3V

GND

12

I

D3R5
1KOhm

1%

12

I

D3R7
1KOhm

1%

GND

H_SM_VREF[11]

3

GND

12

2

GND

C10

2.2UF/6.3V

X5R 10%
I

2

HR62 0Ohm 5%NOBOM
HR63 0Ohm 5%NOBOM

DIMM2B

75

VDD1

81

VDD3

87

VDD5

93

VDD7

99

VDD9

105

VDD11

111

VDD13

117

VDD15

123

VDD17

2

VSS1

8

VSS3

13

VSS5

19

VSS7

25

VSS9

31

VSS11

37

VSS13

43

VSS15

48

VSS17

54

VSS19

60

VSS21

65

VSS23

71

VSS25

127

VSS27

133

VSS29

138

VSS31

144

VSS33

150

VSS35

155

VSS37

161

VSS39

167

VSS41

172

VSS43

178

VSS45

184

VSS47

189

VSS49

195

VSS51

198

EVENT#

125

TEST

77

NC1

122

NC2

126

VREFCA

1

VREFDQ

DDR3_DIMM_204P

I

1 2
1 2

1

+1P5V_DUAL+1P5V_DUAL

76

VDD2

82

VDD4

88

VDD6

94

VDD8

100

VDD10

106

VDD12

112

VDD14

118

VDD16

124

VDD18

3

VSS2

9

VSS4

14

VSS6

20

VSS8

26

VSS10

32

VSS12

38

VSS14

44

VSS16

49

VSS18

55

VSS20

61

VSS22

66

VSS24

72

VSS26

128

VSS28

134

VSS30

139

VSS32

145

VSS34

151

VSS36

156

VSS38

162

VSS40

168

VSS42

173

VSS44

179

VSS46
VSS48
VSS50
VSS52

GND1
GND2

NP_NC1
NP_NC2

VTT1
VTT2

VDDSPD

185
190
196

207
208

205
206

GND

203
204

199

I

12

C302

10PF/50V

NPO/+/-5%

GND

DIMM_CA_VREF_A [15]
DIMM_CA_VREF_B [16]

+3P3V

10PF/50V

NPO/+/-5%

12

D3CB9

0.1UF/6.3V

MLCC/+/-10%

GND

C303

I

GND

12

I

C6
10PF/50V

I

12

GND

D3CB7

0.1UF/6.3V

MLCC/+/-10%

I

12

D3CB8

4.7UF/6.3V

MLCC/+/-10%

PEGATRON DT-MB RESTRICTED SECRET

DDR3 CHANNEL B

DDR3 CHANNEL B

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

DDR3 CHANNEL B

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

1

16 97Friday, January 17, 2014

16 97Friday, January 17, 2014

16 97Friday, January 17, 2014

+VTT_DDR

12

I

GNDGND

Rev

Rev

Rev

A00

A00

A00

Vinafix.com

5

D D

+1P5V_DUAL

4

3

2

1

12

GND

C C

12

GND GND

12

NI

D3CB12

0.1UF/6.3V

MLCC/+/-10%

GND GND GND GND

12

NI

D3CB19

0.1UF/6.3V

MLCC/+/-10%

NI

D3CB13

0.1UF/6.3V

MLCC/+/-10%

NI

D3CB20

0.1UF/6.3V

MLCC/+/-10%

12

NI

D3CB14

0.1UF/6.3V

MLCC/+/-10%

12

I

D3CB21
1UF/6.3V

X5R/+/-10%

GND GNDGND GNDGND

12

12

NI

D3CB15

0.1UF/6.3V

MLCC/+/-10%

I

D3CB22
1UF/6.3V

X5R/+/-10%

12

12

NI

D3CB16

0.1UF/6.3V

MLCC/+/-10%

NI

D3CB23

0.1UF/6.3V

MLCC/+/-10%

12

NI

D3CB17

0.1UF/6.3V

MLCC/+/-10%

GND GND

12

I

D3CB24
1UF/6.3V

X5R/+/-10%

12

NI

D3CB18

0.1UF/6.3V

MLCC/+/-10%

12

NI

D3CB25

0.1UF/6.3V

MLCC/+/-10%

NOTE:

Place those cap close to CH A DIMM0

NOTE:

Place those cap close to CH B DIMM0

Place those cap between CH A DIMM1 and CH B DIMM0

12

B B

+1P5V_DUAL

12

I

D3CB32
22UF/6.3V

X5R/+/-20%

GND GND GNDGND GNDGND

12

NI

D3CB33
22UF/6.3V

X5R/+/-20%

I

D3CB26
22UF/6.3V

X5R/+/-20%

12

D3CB34
22UF/6.3V

X5R/+/-20%

12

NI

I

D3CB27
22UF/6.3V

X5R/+/-20%

12

12

NI

D3CB35
22UF/6.3V

X5R/+/-20%

I

D3CB28
22UF/6.3V

X5R/+/-20%

12

12

D3CB36
22UF/6.3V

X5R/+/-20%

I

I

D3CB29
22UF/6.3V

X5R/+/-20%

12

X5R/+/-20%

12

I

D3CB30
22UF/6.3V

X5R/+/-20%

I

D3CB37
22UF/6.3V

12

12

D3CB38
22UF/6.3V

X5R/+/-20%

I

D3CB31
22UF/6.3V

X5R/+/-20%

I

12

D3CB39
22UF/6.3V

X5R/+/-20%

I

A A

5

GND GND GND GND GND GND GND GND

Place those cap inside CPU SOCKET cavity

4

3

PEGATRON DT-MB RESTRICTED SECRET

DDR3 TERMINATION

DDR3 TERMINATION

DDR3 TERMINATION

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

1

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

17 97Friday, January 17, 2014

17 97Friday, January 17, 2014

17 97Friday, January 17, 2014

Rev

Rev

Rev

A00

A00

A00

Vinafix.com

5

D D

C C

4

3

2

1

B B

A A

<CORE DESIGN>

<CORE DESIGN>

<CORE DESIGN>

PEGATRON DT-MB RESTRICTED SECRET

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

1

XXXXXX

XXXXXX

XXXXXX

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

18 97Friday, January 17, 2014

18 97Friday, January 17, 2014

18 97Friday, January 17, 2014

Rev

Rev

Rev

A00

A00

A00

Vinafix.com

5

U1A

DMI_TXN0[10]
DMI_TXP0[10]
DMI_RXN0[10]
DMI_RXP0[10]

DMI_TXN1[10]
DMI_TXP1[10]
DMI_RXN1[10]

D D

C C

DMI_RXP1[10]
DMI_TXN2[10]

DMI_TXP2[10]
DMI_RXN2[10]
DMI_RXP2[10]

DMI_TXN3[10]
DMI_TXP3[10]
DMI_RXN3[10]
DMI_RXP3[10]

+1P5V_PCH +1P5V_PCH

12

12

I
1%

12

SR1

7.5KOHM

I

SR3
10KOhm

I
1%

12

SR2

7.5KOHM

DMI_RCOMP
PCIE_RCOMP

CLKIN_DMI_N
CLKIN_DMI_P

I

SR4
10KOhm

C20

G24
H24
D21

G26
B22
C22

K26
A24

B24

B19
C13

G22

L24
K24

B20

B21
F26

L26

F22

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

DMI_RCOMP
PCIE_RCOMP

CLKIN_DMI_N
CLKIN_DMI_P

DMI

4

AV10

USB2n0

AU10

USB2p0

AV11

USB2n1

AW11

USB2p1

AN14

USB2n2

AP14

USB2p2

AJ16

USB2n3

AK16

USB2p3

AU15

USB2n4

AV15

USB2p4

AU12

USB2n5

AT12

USB2p5

AV14

USB2n6

AW14

USB2p6

AU17

USB2n7

AT17

USB2p7

AW16

USB2n8

AV16

USB2p8

AN16

USB2n9

AP16

USB2p9

AJ18

USB2n10

AK18

USB2p10

AP18

USB2n11

AN18

USB2p11

AW18

USB2n12

AV18

USB2p12

AP20

USB2n13

AN20

USB2p13

3

USBN0 [33]
USBP0 [33]

USBN1 [33]
USBP1 [33]

USBN2 [34]
USBP2 [34]

USBN3 [34]
USBP3 [34]

USBN4 [35]
USBP4 [35]

USBN5 [35]
USBP5 [35]

USBN6 [37]
USBP6 [37]

USBN7 [37]
USBP7 [37]

USBN8 [36]
USBP8 [36]

USBN9 [36]
USBP9 [36]

USBN11 [28]
USBP11 [28]

USBN12 [29]
USBP12 [29]

Side USB3.0 Port

Rear USB3.0 Port

To Touch Conn
To Camera Conn

Rear USB2.0 Port

To WIFI
To MSATA

2

1

GND GND

USB3_RXN3[34]
USB3_RXP3[34]
USB3_TXN3[34]
USB3_TXP3[34]

USB3_RXN4[34]
USB3_RXP4[34]
USB3_TXN4[34]
USB3_TXP4[34]

LAN_PE1_RXN4[31]
LAN_PE1_RXP4[31]
LAN_PE1_TXN4[31]
LAN_PE1_TXP4[31]

B B

WLAN_PE1_RXP5[28]
WLAN_PE1_TXN5[28]
WLAN_PE1_TXP5[28]

WLAN_PE1_RXN6[28]
WLAN_PE1_RXP6[28]
WLAN_PE1_TXP6[28]
WLAN_PE1_TXN6[28]

CR_PE1_RXN7[30]
CR_PE1_RXP7[30]
CR_PE1_TXN7[30]
CR_PE1_TXP7[30]

K14
B12
B11

G14
D11
C11

H11

L14

F14

F11

J11
L11

G9

G3
G5

PERn1/USB3Rn3
PERp1/USB3Rp3
PETn1/USB3Tn3
PETp1/USB3Tp3

PERn2/USB3Rn4
PERp2/USB3Rp4
PETn2/USB3Tn4
PETp2/USB3Tp4

PERn3
PERp3

B9

PETn3

A9

PETp3
PERn4

PERp4

B8

PETn4

C8

PETp4
PERn5

F9

PERp5

B7

PETn5

A7

PETp5

F7

PERn6

H7

PERp6

E1

PETn6

D2

PETp6

K6

PERn7

K8

PERp7
PETn7
PETp7

J2

PERn8

J3

PERP8

H2

PETn8

H1

PETp8

PCIE

USB

USB3Rn1
USB3Rp1
USB3Tn1
USB3Tp1

USB3Rn2
USB3Rp2
USB3Tn2
USB3Tp2

USB3Rn5
USB3Rp5
USB3Tn5
USB3Tp5

USB3Rn6
USB3Rp6
USB3Tn6
USB3Tp6

OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43

OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14

TACH6/GPIO70
TACH7/GPIO71

CLKIN_DOT96_N
CLKIN_DOT96_P

USBRBIAS#

USBRBIAS

F20
G20
B18
C18

G18
H18
B15
B16

K20
L20
D15
C15

L18
K18
B14
A14

AE40
AF37
AD39
AD40
AF39
AC41
AF40
AG40

AK28
AT34

AP11

CLKIN_DOT_96N

AM11

CLKIN_DOT_96P

AV20
AU20

NOTE: USBRBIAS trace length < 500mil

Place those cap close to Conn side

NOTE:

1 2

SR16 10KOhmI

1 2

SR17 10KOhmI

USBRBIAS

1 2

SR19 22.6 OHM

I

1%

USB3_RXN1 [33]
USB3_RXP1 [33]
USB3_TXN1 [33]
USB3_TXP1 [33]

USB3_RXN2 [33]
USB3_RXP2 [33]
USB3_TXN2 [33]
USB3_TXP2 [33]

USB3_RXN5 [35]
USB3_RXP5 [35]
USB3_TXN5 [35]
USB3_TXP5 [35]

USB3_RXN6 [35]
USB3_RXP6 [35]
USB3_TXN6 [35]
USB3_TXP6 [35]

Native Sus
Native Sus
Native Sus
Native Sus
Native Sus
Native Sus
Native Sus
Native Sus

Native Core IPU 20K
Native Core IPU 20K

GND

+3P3VSB +3P3VSB

+3P3VSB +3P3VSB

12

RN34A10KOHM

I

56

34

RN34B10KOHM

I

+3P3V

RN34C10KOHM

12

I

SR621
10KOhm

I

+3P3V

12

SR12
10KOhm

78

RN34D10KOHM

I

I

OC0# [33,77]WLAN_PE1_RXN5[28]
OC1# [34,77]
OC2# [35,77]
OC3# [77]
OC4# [36,77]
OC5# [77]

CONFIG_2 [29,77]

EPSA_BIST# [51]
LVDS_CBL_DET_PIN14# [53]

CONFIG_3 [29,77]

NOTE:

Place those cap close to Conn side

SR207.5KOHM

3

+1P5V_PCH

<CORE DESIGN>

<CORE DESIGN>

<CORE DESIGN>

PEGATRON DT-MB RESTRICTED SECRET

PCI/SM/SPI/RTC 1-9

PCI/SM/SPI/RTC 1-9

PCI/SM/SPI/RTC 1-9

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

IPPLP-TH

IPPLP-TH

IPPLP-TH

Engineer:

1

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

19 97Friday, January 17, 2014

19 97Friday, January 17, 2014

19 97Friday, January 17, 2014

Rev

Rev

Rev

A00

A00

A00

A A

5

N1
N2

P2
P3

LYNX_POINT

I

FDI_RXN0
FDI_RXP0

FDI_RXN1
FDI_RXP1

FDI

FDI_RCOMP
FDI_CSYNC

4

FDI_INT

Rev 1.1

K2
L2
L3

FDI_RCOMP

I

1%

FDI_CSYNC [10]
FDI_INT [10]

12

Vinafix.com

5

+3P3VSB

NI

I

0 Ohm

1 2

PWROK[13,22,44]

D D

GPIO_WIRELESS_ALERT#[28]

C C

+3P3V_GPU

B B

CONFIG_0[29,77]

DATA1[51]

G_SENOER_INTER#[59]

TRIGGER_PIN#[51]

GPS_DISABLE#[29]

A A

APWROK[91]

I

SCALAR_MODE#[40]

Touch_CBL_DET#[37]

sideBrd_CLB_DET#[55]

GND

GND

+3P3V

GND

DATA0[51]

1

1

G

GPU_PWR_DET#

32

3

D

Q9427
2N7002

S

2

I_GPU

GND

+3P3V

12

APR11

+3P3V

RN1A10KOHM I

RN1B10KOHM I

1 2

3 4

APR160 Ohm

12

NI

I_UMA

I

SR38
10KOhm

1%

APR210 Ohm

12

7 8

RN33D 10KOHM

3 4

RN33B 10KOHM

5 6

RN33C 10KOHM

1 2

RN33A 10KOHM

0 Ohm

CK_33M_PCIFB[21]

RN1C10KOHM I

RN1D10KOHM I

5 6

7 8

I
I
I
I

12

APR36

PLTRST#[31,44,50,62]

R10

4.7KOHM

1 2

+3P3V

12

I

SR22
10KOhm

1%

S_GPI_CHASSIS_ID1
S_GPI_CHASSIS_ID0

BRD_ID2

+3P3V

RN3B8.2KOhmI

RN2A8.2KOhmI

RN2B8.2KOhmI

RN3D8.2KOhmI

7 8

3 4

1 2

3 4

NOTE:

Reserve for Intel 8 Series Chipset Family SKUs

5

4

CL_CLK[28]

CL_DATA[28]

CL_RST#[28]

APR2010KOhmNI 1%

12

GND

GPU_PWR_DET#

S_GPI_CHASSIS_ID2

RN3A8.2KOhmI

RN2D8.2KOhmI

RN3C8.2KOhmI

RN2C8.2KOhmI

7 8

5 6

5 6

1 2

NOBOM
NOBOM
NOBOM
NOBOM

4

3

U1B

CLINK

U36

CL_CLK

U35

CL_DATA

U34

CL_RST#

AA32

NI

AL31
AM31
AP31
AV30

AP28
AT31
AM28
AV34
AT30
AV35

AJ31

L38
H41
R31
L40

AP2
AT2
AP1

AA31

M40
AU29
AU27

AW28

AV27
AR30
AV29
AV28
AT27

AM22
AA37

A2
A3
B2
B1
C3

APWROK

FAN

PWM0
PWM1
PWM2
PWM3

TACH0/GPIO17
TACH1/GPIO1
TACH2/GPIO6
TACH3/GPIO7
TACH4/GPIO68
TACH5/GPIO69

SST

GPIO

SCLOCK/GPIO22
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48

EDP

eDP_BKLTCTL
eDP_BKLTEN
eDP_VDDEN

PCI

PME#
GPIO35/NMI#
PIRQA#
PIRQB#
PIRQC#
PIRQD#
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

CLKIN_33MHZLOOPBACK
PLTRST#

TP1
TP2
TP4
TP3
TD_IREF

LYNX_POINT

I

12

SC5
10PF/50V

NPO/+/-5%

GND

IPU 20K
IPU 20K
IPU 20K
IPU 20K
IPU 20K
IPU 20K

+3P3VSB

12

GND

GPI Core
GPI Core
GPI Core
GPI Core
GPI Core
GPI Core

SSTCTL

IPD 10K

12

NI

SC6
10PF/50V

NPO/+/-5%

GND

GPI Core
GPI Core
GPI Core
GPI Core

NI

SR39
10K

PME#

GPO Core

GPI Core
GPI Core
GPI Core
GPI Core

1

TP_PCH_A2

ST4

1

TP_PCH_A3

ST5

1

TP_PCH_B2

ST6

1

TP_PCH_B1

ST7

PCH_TD_IREF PCH_GPIO55

12

SR48

I

8.2KOHM

1%

SATA_RXN0
SATA_RXP0
SATA_TXN0
SATA_TXP0

SATA_RXN1
SATA_RXP1
SATA_TXN1
SATA_TXP1

SATA_RXN2
SATA_RXP2
SATA_TXN2
SATA_TXP2

SATA_RXN3
SATA_RXP3
SATA_TXN3
SATA_TXP3

SATA_RXN4/PERn1

SATA_RXP4/PERp1

SATA_TXN4/PETn1
SATA_TXP4/PETp1

SATA_RXN5/PERn2

SATA_RXP5/PERp2

SATA_TXN5/PETn2
SATA_TXP5/PETp2

SATA

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA2GP/GPIO36
SATA3GP/GPIO37
SATA4GP/GPIO16
SATA5GP/GPIO49

SATA_RCOMP

SATALED#

CLKIN_SATA_N
CLKIN_SATA_P

HOST

PLTRST_PROC#

SERIRQ

THRMTRIP#

PMSYNCH

GPIO50
GPIO51
GPIO52
GPIO53
GPIO54
GPIO55

Rev 1.1

3

TP14

RCIN#

PECI

B28
A28
F31
H31

D30
C30
B34
C34

A31
B31
B35
D35

B32
C32
G33
F33

A26
B26
L28
K28

C27
B27
G28
F28

M37

GPI Core

J40
H40
N41
M39
N40

GPI Core
GPI Core
GPI Core
GPI Core
GPI Core

IPU 20K
IPD 20K
IPD 20K

NOTE:

SATA_RCOMP trace
length < 500mil

D33

SATA_RCOMP

J39

H35

CLKIN_SATA_N

H36

CLKIN_SATA_P

+1P05V_PCH

I

HR64
1K 1%

mx_r0402_small

F41
N30
K36
G39
C40
G40

IPD 0.35K

F40

AH26
AU31
AJ26
AV31
AW33
R30

GPI Core
IPU 20K

IPU 20K
GPI Core

12

12

GND

SATA_Strap_0
SATA_Strap_1

12

GND

12

GND GND

NI

SC7
47PF/50V

NPO/+/-5%

GPO CoreIPU 20K
GPI Core
GPO Core

GPO CoreIPU 20K

SATA_RXN0 [39]
SATA_RXP0 [39]

SATA_TXN0 [39]
SATA_TXP0 [39]

SATA_RXN1 [39]
SATA_RXP1 [39]

SATA_TXN1 [39]
SATA_TXP1 [39]

SATA_RXN4 [29]
SATA_RXP4 [29]

SATA_TXN4 [29]
SATA_TXP4 [29]

SATA_RXN5 [29]

+3P3V +3P3V +3P3V

SATA_RXP5 [29]

SATA_TXN5 [29]
SATA_TXP5 [29]

12

NI

SR614
10KOhm

1%
+1P5V_PCH

12

I

SR35

7.5KOHM

1%

12

I

I

SR36

SR37

10KOhm

10KOhm

1%

1%

12

+3P3V +3P3V

NI

SC8
47PF/50V

NPO/+/-5%

GND

12

12

NI

SR49
1K

GNDGND

I

SR23
10KOhm

1%

12

I

SR45

8.2KOHM

1%

NI

SR50
1K

2

NOTE:

GPIO51 Description

H81 Support SATA600Port0~1:

0

1

1

Boot select straps

GPIO19

0

1

LPC

SPI

NOTE:

GPIO37 is for TLS confidentiality
1: Enable TLS
0: Disable TLS

NOTE:

Check front panel spec to decide install
those parts or not.

+3P3V +3P3V +3P3V

12

I

SR24
10KOhm

1%

12

NI

SR25
1K 1%

mx_r0402_small

5%PROTO

3 4

0 Ohm

12

I

SR46

8.2KOHM

1%

12

I

SR26
1K 1%

mx_r0402_small

SR616 10KOhm I1%
SR617 10KOhm NI1%

5%PROTO

1 2

0 Ohm

RN28B

12

I

SR40
10KOhm

1%

+3P3V

12

I

SR47

8.2KOHM

1%

12

I

SR27
10KOhm

1%

5%PROTO

3 4

0 Ohm

RN28A

OBSDATA_C1 [50,77]

12

I

SR41
10KOhm

1%

12

NI

SC9
47PF/50V

NPO/+/-5%

GND

12

I

SR28
10KOhm

1%

1 2
1 2

SR611 0 OhmPROTO

RN27B

OBSDATA_C2 [77]

+3P3V+3P3V+3P3V

12

1 2

APR270 Ohm

1 2

APR280 Ohm

1 2

1 2

I

SR42
10KOhm

1%

BRD_ID0 [77]

GND
GND

I

SATA_Strap [20,29]

I

SATA_Strap [20,29]

5%PROTO

RN27A

0 Ohm

OBSDATA_C3 [77]

OBSDATA_D0 [77]

HD_LED_IN# [55]

PLTRST_CPU# [11]

A20GATE [44]
RST_KB# [44]
SERIRQ [44,62]
H_THMTRIP# [11,80]

PM_SYNC [11]

ODD_2ndHDD_CBL_DET# [39]

K_GNT#1 [50]

converter_CBL_DET# [53]

PCH_GPIO53 [41]

SCL_FW_DATA [51,52]

OBSDATA_D1 [77]

PEGATRON DT-MB RESTRICTED SECRET

PCIE/USB/DMI 2-9

PCIE/USB/DMI 2-9

PCIE/USB/DMI 2-9

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

IPPLP-TH

IPPLP-TH

IPPLP-TH

Engineer:

1

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

20 97Friday, January 17, 2014

20 97Friday, January 17, 2014

20 97Friday, January 17, 2014

Rev

Rev

Rev

A00

A00

A00

Vinafix.com

5

+3P3V

4

3

2

1

NI

MR41

2.2KOHM

DDPB_AUXN_DP_IN[60]
DDPB_AUXP_DP_IN[60]

DDPC_HPD_HDMI[51]

GND

DDC_CLK_DP_IN[60]
DDC_DATA_DP_IN[60]

DDPB_HPD_DP_OUT[60]

DDPC_CTRL_CLK[51,52]

DDPC_CTRL_DATA[51,52]

NPO/+/-5%

12

I

SC12
10PF/50V

GND GNDGND

12

C94129510PF/50V I

HDMI_CTRL_CLK[57]
HDMI_CTRL_DATA[57]

HDMI_DDPD_HPD[57]

GND

1 2

SR68 1MImx_r0603_h24

1 3

2

5

D D

C C

B B

A A

1 2

NPO/+/-5%

+1P5V_PCH

12

I

Y10
25MHZ

4

GND

I

SR65
10KOhm

1%

NI

MR40

2.2KOHM

1 2

S1C47

NI

12

0.1UF/16V

X7R 10%

12

C654610PF/50V NI

I

SR64

7.5K

1%

1 2

PCH_CLKIN_BCLK_GND0#
PCH_CLKIN_BCLK_GND0

12

I

SR66
10KOhm

1%

GNDGND GND

XTAL_25M_PCH_IN
XTAL_25M_PCH_OUT

12

I

SC13
10PF/50V

IPD 20K

DIFFCLK_BIASREF

REFCLK14IN

12

I

SR67
10KOhm

1%

AK6
AK8

AM1

AJ5
AJ2

AG7
AG6

AN3
AM2

AH5

AG11
AG10

AN4
AN2

AJ4

R11

G16
F16

AR7

N7
N6

4

U1C

DDPB_AUXN
DDPB_AUXP

DDPB_CTRLCLK
DDPB_CTRLDATA

DDPB_HPD

DDPC_AUXN
DDPC_AUXP

DDPC_CTRLCLK
DDPC_CTRLDATA

DDPC_HPD

DDPD_AUXN
DDPD_AUXP

DDPD_CTRLCLK
DDPD_CTRLDATA

DDPD_HPD

DIFFCLK_BIASREF

CLKIN_GND_N
CLKIN_GND_P

REFCLK14IN

XTAL25_IN
XTAL25_OUT

LYNX_POINT

I

DP

VGA_VSYNC
VGA_HSYNC

VGA_DDC_CLK

VGA_DDC_DATA

VGA_GREEN

VGA_BLUE

CLOCK

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKOUT_DP_N

CLKOUT_DP_P

CLKOUT_DPNS_N
CLKOUT_DPNS_P

CLKOUT_ITPXDP_N

CLKOUT_ITPXDP_P

CLKOUT_PCIE_N0
CLKOUT_PCIE_P0

CLKOUT_PCIE_N1
CLKOUT_PCIE_P1

CLKOUT_PCIE_N2
CLKOUT_PCIE_P2

CLKOUT_PCIE_N3
CLKOUT_PCIE_P3

CLKOUT_PCIE_N4
CLKOUT_PCIE_P4

CLKOUT_PCIE_N5
CLKOUT_PCIE_P5

CLKOUT_PCIE_N6
CLKOUT_PCIE_P6

CLKOUT_PCIE_N7
CLKOUT_PCIE_P7

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

CLKOUT_33MHZ0
CLKOUT_33MHZ1
CLKOUT_33MHZ2
CLKOUT_33MHZ3
CLKOUT_33MHZ4

CLKOUTFLEX0/GPIO64
CLKOUTFLEX1/GPIO65
CLKOUTFLEX2/GPIO66
CLKOUTFLEX3/GPIO67

VGA_RED

DAC_IREF
VGA_IRTN

Rev 1.1

AH2
AH3

AL2
AL3

AC2
AE2
AC3

AF5
AG4

GNDGND

NOTE:

DAC_IREF should be as short as
possible to prevent noise coupling and IR drop

VGA_IRTN provides the return current path to the VGA DAC signals.
This should be routed out and tied directly to the MB ground plane

R2
T2

T3
T5

W2
U2

U6
U7

AE10
AE11

AC6
AC7

AC11
AC10

W11
W10

Y4
Y2

W7
W6

AA7
AA6

R6
R7

AA3
AA2

AE6
AE7

AV5
AV7
AU2
AN9
AU5

AV8
AT9
AV9
AU8

PCH_CLKOUT_PCI0

IPD 20K

PCH_CLKOUT_PCI1

IPD 20K
IPD 20K

PCH_CLKOUT_PCI3

IPD 20K

PCH_CLKOUT_PCI4

IPD 20K
IPD 20K

TP_CLKOUTFLEX1_GPIO65

IPD 20K
IPD 20K

TP_CLKOUTFLEX3_GPIO67

IPD 20K

SR619 10KOhm I1%

3

1 2

SR615
10KOhmI1%

1 2

+3P3V

+3P3V

DATA2 [51]

SCL_FW_CLK [51,52]

CK_100M_DMI# [11]
CK_100M_DMI [11]

CK_135M_DP# [10]
CK_135M_DP [10]

CK_135M_DPNS# [11]
CK_135M_DPNS [11]

CK_100M_CPUXDP# [76]
CK_100M_CPUXDP [76]

CK_100M_PE1# [28]
CK_100M_PE1 [28]

CK_100M_LAN# [31]
CK_100M_LAN [31]

CK_100M_CR# [30]
CK_100M_CR [30]

CK_100M_MSATA# [29]
CK_100M_MSATA [29]

CK_100M_PE2# [28]
CK_100M_PE2 [28]

GPU_CLKOUT_PEG_A# [79]
GPU_CLKOUT_PEG_A [79]

1 2

SR70 22 OHM 1%I

1 2

SR69 22 OHM 1%I

1 2

SR71 22 OHM 1%I

1 2

SR72 22 OHM 1%I

1 2

SR73 22 OHM 1%I

1 2

SR74 22 OHMNI

NOTE:

CLKOUT_DPNS_P/N
135 MHz differential clock with No SSC for
embedded DisplayPort* (eDP*)

WIFI
LAN
CraReader
MSATA

12

SCB3
10PF/50V

2

CK_33M_SIO [44]
CK_33M_TPM [62]

CK_33M_LPC [50]
CK_33M_PCIFB [20]

CK_14M_SIO [44]

NI

SCB6
10PF/50V

IPPLP-TH

IPPLP-TH

IPPLP-TH

GND GNDGNDGND GNDGND

12

NI

SCB7
10PF/50V

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

12

NI

12

NI

SCB4
10PF/50V

<CORE DESIGN>

<CORE DESIGN>

<CORE DESIGN>

PEGATRON DT-MB RESTRICTED SECRET

Date: Sheet of

Date: Sheet of

Date: Sheet of

12

I

SCB5
10PF/50V

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

12

NI

SCB8
10PF/50V

SATA/HOST/FAN 3-9

SATA/HOST/FAN 3-9

SATA/HOST/FAN 3-9

1

CK_14M_TPM [62]

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

21 97Friday, January 17, 2014

21 97Friday, January 17, 2014

21 97Friday, January 17, 2014

Rev

Rev

Rev

A00

A00

A00

Vinafix.com

5

+3P3V

12

SR75

10KOhm

NI
5%

D D

P217
HEADER_1X2P

I

+3P3VSB

AZ_SDATA_OUT[40]

AZ_SYNC[40]
AZ_BITCLK[40]
AZ_RST#[40,42]

C C

9,60,76,77]
9,60,76,77]

B B

A A

SMB_CLK_RESUME
SMB_DATA_RESUME

SML0_LANNFC_CLK[31]
SML0_LANNFC_DATA[31]

GPIO_WIRELESS_DISABLE#[28]

SIO_SMLINK_CLK[44]
SIO_SMLINK_DATA[44]

CPUPWRGD[11]
DRAM_PWROK[11]
PWROK[13,20,44]

VRM_PWRGD[44,64,76]

RSMRST#[44,77]
PCH_DPWROK[44,77]

P216

HEADER_1X2P

+BATT

1 2

R13 20K 1%Imx_r0402_small

1 2

R14 20K 1%Imx_r0402_small

+3P3VA

I

12

C19
1UF/6.3V

X5R 10%
mx_c0603

12

GND

GND

12

GND GND GND GND

BT_DISABLE#[28]

TMIN_SHIFT[44]

SYS_RESET#[11,50,76,77]

1
2

SW50_R

1 2

BAT R303_D8

XBT1
BATT_HOLDER

NI

SC14
10PF/50V

NPO/+/-5%

SPI_CS1#[26]
SPI_CS0#[26]
SPI_MOSI[26]
SPI_MISO[26]
SPI_CLK[26]
SPI_IO2[26]

SPI_IO3[26]

R12 4.7KOHMI

C17 1UF/6.3V MLCC/+/-10%mx_c0603I
C15 1UF/6.3V MLCC/+/-10%mx_c0603I

I

R15
1KOhm

1%

mx_r0402

5

12

NI

SC15
10PF/50V

NPO/+/-5%

+3P3VSB

12

12

150PF/50V

NPO/+/-5%

1 2
1 2

1 2

Critical

BATT1

3V/220mAh

KTS

LITHIUM BATT

CR2032

DATA3[51]

NOTE:

HDA_SDO
Disable ME in Manufacturing Mode

--> connect to High.

E50_1

2

1

SR89 1K 1%

I

mx_r0402_small

SR90 33 OHM

I

SR91 33 OHM

I

SR93 33 OHM

I

SR94 33 OHM

I

12

12

+3P3VSB +3P3VSB +3P3VSB +3P3VSB +3P3VSB

12

I

SR111

2.2KOHM

12

NI

SC18

150PF/50V

NPO/+/-5%

+3P3V

RTCRST# [50]

I

D1

1
2

BAT54CW

NI

NI

SC17

SC16

10PF/50V

10PF/50V

NPO/+/-5%

NPO/+/-5%

I

I

SR112

SR113

499 Ohm

4.7KOHM

1 2

1 2

12

12

NI

NI

SC20

SC19

150PF/50V

150PF/50V

NPO/+/-5%

NPO/+/-5%

12
12

GND

AZ2025-01H

+BATT

NI

12

AD7

3

AZ2025-01H

12

I

SC27
18PF/50V

NPO 5%

GND

AZ_SDATA_IN[40]

1 2

1 2
1 2
1 2
1 2

12

I

I

SR115

SR114
499 Ohm

2.2KOHM

12

NI

NI

SC22

SC21

150PF/50V

NPO/+/-5%

PR11KOhm1%

I

R112.2KOHM I

AD8

GND GND

1 2

SR131 10M MX_R0603

I

1 4

XTAL:0708-0006000,0708-000L000

4

NI

SR76

5%

10KOhm

LAD0[44,50,62]
LAD1[44,50,62]
LAD2[44,50,62]
LAD3[44,50,62]

LFRAME#[44,50,62]

HDA_SDO_R [27]

HDA_SYNC_R
HDA_BITCLK_24MHZ_R
HDA_AZRST#_R

12

I

SR116

2.2KOHM

12

NI

SC23
150PF/50V

NPO/+/-5%

GNDGNDGNDGNDGNDGND

1 2

C12 100KOHM 1%I

1 2

C13 150PF/50VNI

1 2

C14 15PF/50VNI

1 2

C18 39PF/50VNI

1 2

C16 180PF/50V

I

12

SRTCRST#

NI

RTCRST#

Y5 32.768Khz

2

3

I

GNDGND GND

4

+3P3V

12

IPU 20K
IPU 20K
IPU 20K
IPU 20K
IPU 20K
IPU 20K

IPD 20K
IPD 20K
IPD 20K
IPD 20K

IPD 20K
IPD 20K

IPU 20K
IPU 20K
IPU 20K
IPD 20K
IPU 20K

IPU 20K
IPU 20K

Native Sus

Native Sus
Native Sus

Native Sus
Native Sus

+BATT+BATT

12

SR124
390KOHM

I

I

PCH_INTVRMEN

NPO 5%

PCH_RTCX1
PCH_RTCX2

12

I

SC28
18PF/50V

NPO 5%

U1D

AK26

LDRQ1#/GPIO23

AN24

LAD0

AP26

LAD1

AJ24

LAD2

AN26

LAD3

AK22

LDRQ0#

AP24

LFRAME#

AT26

HDA_SDI0

AV22

HDA_SDI1

AT22

HDA_SDI2

AW23

HDA_SDI3

AU22

HDA_SDO

AV24

HDA_SYNC

AV23

HDA_BCLK

AU24

HDA_RST#

R40

SPI_CS2#

R35

SPI_CS1#

R38

SPI_CS0#

P40

SPI_MOSI

R36

SPI_MISO

U39

SPI_CLK

U40

SPI_IO2

U37

SPI_IO3

AG36

SMBCLK

AG32

SMBDATA

AG31

SMBALERT#/GPIO11

AE32

SML0CLK

AE35

SML0DATA

AG35

SML0ALERT#/GPIO60

AK36

SML1CLK/GPIO58

AK33

SML1DATA/GPIO75

AJ39

SML1ALERT#/PCHHOT#/GPIO74

12

SR125
390KOHM

AM41

DSWVEN

DSWVRMEN

AV36

INTVRMEN

D40

PROCPWRGD

AE38

DRAMPWROK

AT40

PWROK

W31

SYS_PWROK

N36

SYS_RESET#

AM40

RSMRST#

AV38

DPWROK

AR39

SRTCRST#

AR38

RTCRST#

AN40

RTCX1

AN39

RTCX2

LYNX_POINT

I

LPC

AUDIO

SPI

3

BMBUSY#/GPIO0

GPIO32

DOCKEN#/GPIO33

GPIO34

LAN_PHY_PWR_CTRL/GPIO12

HDA_DOCK_RST#/GPIO13

SLP_WLAN#/GPIO29

ACPRESENT/GPIO31

PCIECLKRQ0#/GPIO73
PCIECLKRQ1#/GPIO18

PCIECLKRQ2#/GPIO20/SMI#

PCIECLKRQ3#/GPIO25
PCIECLKRQ4#/GPIO26
PCIECLKRQ5#/GPIO44
PCIECLKRQ6#/GPIO45
PCIECLKRQ7#/GPIO46

SUSWARN#/SUSPWRNACK/GPIO30

GPIO8

GPIO15
GPIO24
GPIO28

GPIO27

JTAG_TMS
JTAG_TDO

JTAG_TDI

JTAG_TCK

TP20

GPIO57
GPIO72

SUSACK#

SUSCLK/GPIO62

SUS_STAT#/GPIO61

WAKE#

INTRUDER#

SPKR

PWRBTN#

TP21
SLP_S3#
SLP_S4#

SLP_S5#/GPIO63

SLP_A#

SLP_LAN#

SLP_SUS#

Rev 1.1

3

2

+3P3V +3P3V +3P3V +3P3VSB+3P3VSB +3P3VSB +3P3VA +3P3VA

12

I

SR77
10KOhm

1%

G38

GPI Core

N32

GPO Core

AV26

GPO Core

N34

GPI Core

AC40

GPO Sus

AL40

Native Sus

AN22

GPI Sus

AC32

GPO Sus

AE34

GPO Sus

V41

GPO Sus

AL39

GPI DSW

AU34
AM36

W34

Native Sus

P39

Native Core

P37

Native Core

AA39

Native Sus

W35

Native Sus

AA36

Native Sus

W32

Native Sus

AA40

Native Sus

W40

IPU 20K

Y38
W39

IPU 20K

Y40

IPD 20K

W37

AC36

GPI Sus

AJ40
AG41

Native Sus

AJ37

IPU 20K

W36

Native Sus

AD37

Native Sus

AE36

RI#

AK34
AR41
R32

IPD 20K

AK41

IPU 20K

AC35
AK40
AT35
AA35

Native Sus

AN37
AU36
AK38

NI

SR79
10KOhm

1%

IPU 20K

IPU 20KGPI DSW
IPD 20KGPI DSW

+3P3VSB +3P3V

12

I

SR95

10KOhm

1%

IPU 20K
IPU 20K

12

NI

SR119
10KOhm

1%

GND

IPU 20KNative Sus

PCH_SUSWARN#

+3P3VSB

12

I

SR127
10KOhm

1%

12

NI

SC25
10PF/50V

NPO/+/-5%

GND

TP_SLP_S0#

12

12

I

SR80

SR81

10KOhm

10KOhm

1%

12

NI

SR92
10KOhm

1%

12

I

SR96

GND

10KOhm

1%

PCH_JTAG_TMS [77]
PCH_JTAG_TDO [77]
PCH_JTAG_TDI [77]
PCH_JTAG_TCK [77]
PCH_JTAG_RST [77]

12

NI

SC26

0.1UF/16V

GND

1

ST16

NOBOM

I

1%

12

12

I

SR82
10KOhm

1%

MFG_MODE#

12

RN35A10KOHM

I

GND

SR207 0 Ohm PROTO

+3P3VSB

12

I

SR120
10KOhm

1%

PWRBTN# [44,50,55,76,77]

SLP_S3# [44,50,67,72,74]
SLP_S4# [44,50,68,72]
KEY_A_PWR [74]
SLP_A# [44,50,68,91]
SLP_LAN# [67]
SLP_SUS# [44,70,71]

2

+3P3VSB

34

RN35B10KOHM

I

BRD_ID1

1 2

12

I

SR84
10KOhm

1%

CLR_PWD#

56

78

RN35C10KOHM

RN35D10KOHM

I

I

OBSDATA_D3 [77]

+3P3VA

12

I

SR122
10KOhm

1%

12

+3P3VA

NI

SC24
10PF/50V

12

NPO/+/-5%

GND

12

GND

<CORE DESIGN>

<CORE DESIGN>

<CORE DESIGN>

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

12

I

SR87
10KOhm

1%

SR103 0 Ohm PROTO

1%

12

SR61810KOhm1% I

+3P3VSB

12

SR613
10KOhm

+BATT

12

I

SR128

I

SR129

10KOhm

1M

1%

NI

SC139
10PF/50V

NPO/+/-5%

IPPLP-TH

IPPLP-TH

IPPLP-TH

I

SR88
10KOhm

1%

1 2

I

1%

1

12

I_GPU

0 Ohm

1 2

APR12

SR10210KOhm

12

+3P3VSB

NI

GPURST_GPIO8 [79]

S_PECI_REQ# [44]

GPUPW_EN [71,91,93]
BRIGHTNESS_DISABLE# [51]

1

ST135

P215:12

MINI_JUMPER

I

NOBOM

HSW_STRAP [11,77]
LAN_DISABLE# [31]
LVDS_CBL_DET_PIN24# [53]
PRE_OS_BIST# [51]
SKTOCC# [11]
DEVSLP [29]
SLP_WLAN# [74]
LAN_WAKE# [31]

HEADER_1X2P

SPKR_CBL_DET# [41]
MSATA_CLKREQ# [29]
OBSDATA_D2 [77]
Mode_button# [51,55]
CAMERA_CBL_DET# [37]
ME_Disable# [27]
INTRUD_CBL_DET# [53,55]
WLAN_CLKREQ# [28]

P215

I

NOTE:

SUSCLK/GPIO62
PLL On-Die Voltage
Regulator Enable should
be NC for internal
VccVRM

WWAN_DISABLE# [29]

VOLUME_DISABLE# [51]

SUS_CLK [28,29,44]
CONFIG_1 [29]

O_IO_PME# [44]
WAKE# [28,29]
Alarm_open# [53,55]
SPKR [41]

AUDIO/LPC/MISC 4-9

AUDIO/LPC/MISC 4-9

AUDIO/LPC/MISC 4-9

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

1

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

22 97Friday, January 17, 2014

22 97Friday, January 17, 2014

22 97Friday, January 17, 2014

GND

1
2

Rev

Rev

Rev

A00

A00

A00

Vinafix.com

5

4

3

2

1

U1E

+1P05V_PCH

12

I

GND

SC30

0.1UF/6.3V

MLCC/+/-10%

D D

NOTE:

Pin AF19, AF20, AF22, AF23 are connected
to on bottom layer only. Not connected on
VCC layer to avoid noise coupling.

I

I

SCB14
1UF/6.3V

SL1
10UH/125mA

mx_l0805

12

I

SCB15
1UF/6.3V

X5R/+/-10%

21

VCCCLK 0.306 A

NI

SCB16
1UF/6.3V

X5R/+/-10%

12

GND GND GNDGND GND GND

SCB17
1UF/6.3V

X5R/+/-10%

12

I

+1P05V_PCH

+1P05V_PCH

C C

12

X5R/+/-10%

VCCIO 3.629 A

12

GND GNDGND GND GND GND

B B

A A

I

SCB25
10UF/6.3V

X5R 10%
mx_c0805

12

12

GND GNDGND

12

I

SCB26
10UF/6.3V

X5R 10%
mx_c0805

DCPSUSBYP_RC DCPSUSBYP

12

I

SCB48
1UF/16V

X7R 10%

mx_c0603

12

NI

SCB27
1UF/6.3V

X5R/+/-10%

SR133 5.1 OHM

I1%

12

I

SCB49

0.1UF/6.3V

MLCC/+/-10%

5

12

X5R/+/-10%

+1V_CPU2PCH

12

I

SCB29
1UF/6.3V

I

SCB28
1UF/6.3V

X5R/+/-10%

PCH_INTERNAL_VRM_DCPRTC
PCH_INTERNAL_VRM_DCPSST

I

SCB50

0.1UF/6.3V

MLCC/+/-10%

VCCCORE 1.29 A

12

12

SCB18
1UF/6.3V

X5R/+/-10%

12

SCB30
1UF/6.3V

X5R/+/-10%

I

SC29

0.1UF/6.3V

MLCC/+/-10%

GND GND

I

I

GND GND

+1P05V_ME

GND

12

GNDGND GND

12

12

12

12

12

NI

SC31

0.1UF/6.3V

MLCC/+/-10%

12

I

SCB9
10UF/6.3V

X5R 10%
mx_c0805

NI

SCB19
1UF/6.3V

X5R/+/-10%

I

SCB31
1UF/6.3V

X5R/+/-10%

12

GND

12

I

SCB10
1UF/16V

X7R 10%
mx_c0603

I

SCB20
1UF/6.3V

X5R/+/-10%

NI

SCB32
1UF/6.3V

X5R/+/-10%

VCCASW 0.67 A

12

GND

I

SCB39
1UF/6.3V

X5R/+/-10%

I

SCB38
10UF/6.3V

X5R 10%
mx_c0805

NI

SC32

0.1UF/6.3V

MLCC/+/-10%

V_PROC_IO 0.004 A

12

I

SCB44
1UF/16V

X7R 10%
mx_c0603

NOBOM

NOBOM
NOBOM

12

0.1UF/6.3V

MLCC/+/-10%

GNDGND

SCB45

ST18

ST19
ST20

I

12

SCB46

0.1UF/6.3V

MLCC/+/-10%

GND

1

TP_PCH_VCCSUS

1

TP_DCPSUS1

1

TP_DCPSUS2

I

NOTE:

Caps can be removed on DcpSus
(pin AE30, P19 and AJ22)
if Internal VRM is used.

4

AA19
AA20
AB16
AB17
AB19
AB20
AD16

W17
W19
W23
W25

AC12

AB1

W14
AB2

AA16

W16

AF19
AF20
AF22
AF23

AP22

M14

AA23
AA25
AA26
AB22
AB23
AB25
AB26
AD17
AD19
AD20
AD22
AD23

W26

AD25

AF25

AU40
AU41

AJ22

AW35

AH28
AE30

V17
V19
V20
V22
V23
V25

U12
V14

T16
V16

P14
P16
P17
P22
P23
P25
P26
P28
T19
T20

C39

P19

VCC11
VCC12
VCC14
VCC15
VCC16
VCC17
VCC18
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10

VCCIO12

VCC13

VCCCLK2
VCCCLK3
VCCCLK5
VCCCLK8
VCCCLK7
VCCCLK6
VCCCLK1
VCCCLK4

VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCUSBPLL
VCCIO1

VCCASW2
VCCASW3
VCCASW4
VCCASW5
VCCASW6
VCCASW7
VCCASW8
VCCASW9
VCCASW10
VCCASW11
VCCASW12
VCCASW13
VCCASW1
VCCASW14
VCCASW15

V_PROC_IO

DCPSUSBYP1
DCPSUSBYP2

DCPSUS2
DCPRTC
DCPSST
DCPSUS1
DCPSUS3

LYNX_POINT

I

DMI_IREF

FDI_IREF

ICLK_IREF

PCIE_IREF

SATA_IREF

VCCVRM6
VCCVRM2

VCCVRM10

VCCVRM7
VCCVRM3
VCCVRM4

VCCVRM11

VCCVRM9
VCCVRM8
VCCVRM5
VCCVRM1

VCCADAC1_5

VCCADACBG3_3

VCC3_3_1
VCC3_3_6

VCCCLK3_3_3
VCCCLK3_3_4
VCCCLK3_3_5
VCCCLK3_3_6
VCCCLK3_3_7

VCCCLK3_3_8
VCCCLK3_3_10
VCCCLK3_3_12
VCCCLK3_3_13

VCCCLK3_3_1

VCCCLK3_3_2

VCCCLK3_3_9
VCCCLK3_3_11

VCC3_3_2
VCC3_3_3
VCC3_3_4
VCC3_3_5

VCCSPI

VCCSUSHDA
VCCSUS3_3_7
VCCSUS3_3_8
VCCSUS3_3_2
VCCSUS3_3_3
VCCSUS3_3_4
VCCSUS3_3_5
VCCSUS3_3_6
VCCSUS3_3_1
VCCSUS3_3_9

VCCDSW3_3_1
VCCDSW3_3_2
VCCDSW3_3_3

VCCRTC

Rev 1.1

+1P5V_PCH

A19
N11
N10
B13
A33

B37
A38
K1
B39
A39
A40
T14
C2
C1
B4
A4

AF2

AE1
B6
AW21

AM7
AM9
AP5
AP7
AR4
AT5
AV4
AW4
AW9
AG12
AK11
AV3
AW3

U30
W30
AF26
AG1

VCCSPI 0.022 A

R41

AW26
AM33
AN33
AH18
AH20
AH22
AJ20
AK20
P20
AP35

AV39
AW38
AW39

AP33

GND

+3P3V_ME

See Page 67

12

SCB36
1UF/6.3V

X5R/+/-10%

I

GND

+3P3VA

VCCDSW3_3 0.015 A

12

0.1UF/6.3V

MLCC/+/-10%

GND

12

SCB51

0.1UF/6.3V

MLCC/+/-10%

GND GND

3

NOTE:

Backup 09X241023060 1UH/300mA(0805)

and install 10uF for External VRM

NOTE:

Backup 09X241031260 10UH/125mA(0805)

and install 10uF/1Ω for External VRM

VCCVRM 0.183 A

VCCADAC3_3 0.0133 A/ VCCADAC1_5 0.07A

+3P3V_BG

VCC3_3 0.0133 A

See Page 66

12

GND

I

SCB47

I

I

SCB11

0.1UF/6.3V

+BATT

12

X5R/+/-10%

12

I

SCB12
1UF/6.3V

X5R/+/-10%

GND

VCCCLK3_3 0.055 A

12

12

12

I

SCB21
1UF/6.3V

X5R/+/-10%

SCB33

0.1UF/6.3V

MLCC/+/-10%

I

SCB22
1UF/6.3V

X5R/+/-10%

GNDGND GND GND

12

I

SCB34

0.1UF/6.3V

MLCC/+/-10%

GND

VCCSUS 0.261 A

I

SCB40

0.1UF/6.3V

MLCC/+/-10%

I

12

SCB41

0.1UF/6.3V

MLCC/+/-10%

12

SCB52
1UF/6.3V

12

X5R/+/-10%

+3P3V

12

I

X5R/+/-10%

GNDGND

12

I

X5R/+/-10%

GNDGNDGND GND

I

SCB23
1UF/6.3V

I

SCB35
1UF/6.3V

I

SCB42
1UF/6.3V

+3P3V

12

+3P3VSB

12

I

SCB24
1UF/6.3V

X5R/+/-10%

I

SCB43
1UF/6.3V

X5R/+/-10%

12

I

SCB13

0.1UF/6.3V

MLCC/+/-10%

GND

GND

NOTE:

PCH power plane isolation

<CORE DESIGN>

<CORE DESIGN>

<CORE DESIGN>

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

PEGATRON DT-MB RESTRICTED SECRET

VGA/DP/HDMI 5-9

VGA/DP/HDMI 5-9

VGA/DP/HDMI 5-9

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

IPPLP-TH

IPPLP-TH

IPPLP-TH

Engineer:

1

+1P5V_PCH

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

23 97Friday, January 17, 2014

23 97Friday, January 17, 2014

23 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Vinafix.com

5

4

3

2

1

U1F

D9

VSS21

E12

VSS44

E3

VSS40

E31

VSS45

E35

VSS46

E38

VSS47

E4

VSS41

D D

C C

B B

A A

5

E5

VSS42

E7

VSS43

F18

VSS48

F24

VSS49

F35

VSS50

F37

VSS51

F38

VSS52

G2

VSS53

H14

VSS58

H16

VSS59

H20

VSS60

H22

VSS61

H26

VSS62

H28

VSS63

H33

VSS64

H34

VSS65

H38

VSS66

H4

VSS54

H6

VSS55

H8

VSS56

H9

VSS57

J31

VSS68

J37

VSS69

J5

VSS67

K31

VSS72

K4

VSS70

K9

VSS71

L37

VSS73

L41

VSS74

M16

VSS75

M18

VSS76

M20

VSS77

M22

VSS78

M24

VSS79

M26

VSS80

M28

VSS81

N31

VSS84

N35

VSS85

N38

VSS86

N4

VSS82

N8

VSS83

R1

VSS87

R10

VSS89

R34

VSS90

R8

VSS88

T17

VSS91

T22

VSS92

T23

VSS93

T25

VSS94

T26

VSS95

T28

VSS96

U1

VSS97

U31

VSS100

U32

VSS101

U4

VSS98

U8

VSS99

V26

VSS102

V28

VSS103

V38

VSS104

V40

VSS105

W12

VSS109

W20

VSS110

W22

VSS111

W28

VSS112

W3

VSS106

W5

VSS107

W8

VSS108

Y1

VSS113

Y41

VSS114

D12

VSS22

D13

VSS23

D14

VSS24

D16

VSS25

D18

VSS26

D19

VSS27

D20

VSS28

D22

VSS29

D24

VSS30

D25

VSS31

D26

VSS32

D27

VSS33

D28

VSS34

D31

VSS35

D32

VSS36

D8

VSS20

D7

VSS19

D6

VSS18

D4

VSS17

D37

VSS38

D34

VSS37

C6

VSS12

C37

VSS14

C25

VSS13

GND GND

LYNX_POINT

I

VSS1
VSS2
VSS3

VSS4
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS115
VSS116
VSS127
VSS128
VSS126
VSS131
VSS133
VSS134
VSS129
VSS130
VSS135
VSS136
VSS137
VSS140
VSS141
VSS138
VSS142
VSS139
VSS144
VSS145
VSS146
VSS147
VSS148
VSS150
VSS151
VSS152
VSS149
VSS153
VSS154
VSS155
VSS156
VSS158
VSS159
VSS157
VSS161
VSS162
VSS160
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS163
VSS164
VSS165
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS184
VSS183
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS181
VSS182
VSS200
VSS201
VSS204
VSS205
VSS207
VSS212
VSS211

VSS6

VSS5

VSS7

VSS8

VSS9

Rev 1.1

A12
A16
A21
A35
AA10
AA11
AA12
AA14
AA17
AA22
AA28
AA30
AA34
AA5
AA8
AB14
AB28
AB4
AC30
AC34
AC38
AC5
AC8
AD14
AD26
AD28
AE12
AE31
AE4
AE41
AE8
AF14
AF16
AF17
AF28
AG2
AG30
AG34
AG38
AG8
AH14
AH16
AJ1
AJ28
AK24
AK37
AK9
AL11
AL37
AL5
AM14
AM16
AM18
AM20
AM24
AM26
AM35
AM38
AM4
AM6
AM8
AN28
AP4
AP9
AR11
AR35
AR37
AT11
AT10
AT14
AT15
AT16
AT18
AT20
AT21
AT23
AT24
AT28
AT29
AT33
AT36
AT38
AT7
AT8
AU3
AU39
AV12
AV17
AV33
AW30
AW7
B25
B3
B30
B33
B38

GND

4

AT41

AU1

AV40
AV41

AW2

AW40

AT1

AV1
AV2

B40
B41
C41

D41

D1

U1G

VSS180
VSS198
VSS199
VSS202
VSS203
VSS208
VSS209
VSS210
VSS213
VSS10
VSS11
VSS15
VSS16
VSS39

LYNX_POINT

I

TP19
TP18
TP23
TP24

TP9
TP8

TP22

TP11

TP6

TP25

TP17
TP13
TP12

TP7

TP16

TP5
TP15
TP10

VSS132

VSS143
VSS206

Rev 1.1

3

U11
U10
AJ14
AK14
K34
K33
AH24

L16
K16
AM34

R12
N12
L22
K22

R4
K5
P5
L5

AC31

AF3
AV21

TP_PCH_TP19
TP_PCH_TP18
TP_PCH_TP23

TP_PCH_TP9
TP_PCH_TP8
TP_PCH_TP22

TP_PCH_TP11
TP_PCH_TP6
TP_PCH_TP25

TP_PCH_TP17
TP_PCH_TP13
TP_PCH_TP12
TP_PCH_TP7

TP_PCH_TP16
TP_PCH_TP5
TP_PCH_TP15
TP_PCH_TP10

GND

GND

1

ST21

NOBOM

1

ST22

NOBOM

1

ST23

NOBOM

1

ST24

NOBOM

1

ST25

NOBOM

1

ST26

NOBOM

1

ST27

NOBOM

1

ST28

NOBOM

1

ST29

NOBOM

1

ST30

NOBOM

1

ST31

NOBOM

1

ST32

NOBOM

1

ST33

NOBOM

1

ST34

NOBOM

1

ST35

NOBOM

1

ST36

NOBOM

1

ST37

NOBOM

1

ST38

NOBOM

Remove Heatsink

Solder Pad Recommendation

NOTE:

PEGATRON DT-MB RESTRICTED SECRET

CLK/NVRAM/FDI 6-9

CLK/NVRAM/FDI 6-9

CLK/NVRAM/FDI 6-9

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

IPPLP-TH

IPPLP-TH

IPPLP-TH

Engineer:

1

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

24 97Friday, January 17, 2014

24 97Friday, January 17, 2014

24 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Vinafix.com

5

4

3

2

1

12

SC119

0.1UF/6.3V

+1P5V_DUAL

12

NI

GND

SC118

0.1UF/6.3V

+VDDC

NI

GND

12

SC121

0.1UF/6.3V

+VDDC

NI

GND

12

SC120

0.1UF/6.3V

+12V_CPU

12

NI

GND

SC141

0.1UF/6.3V

+12VSA

12

NI

GND

SC142

0.1UF/6.3V

1 2

SC110 0.1UF/6.3V

NI

1 2

SC111 0.1UF/6.3V

NI

1 2

SC112 0.1UF/6.3V

NI

1 2

SC140 0.1UF/6.3V

I

1 2

SC143 0.1UF/6.3V

D D

C C

NI

AGNDGND

+5V_DUAL +5V_DUAL +5V_DUAL +5V_DUAL

SC114

0.1UF/6.3V

12

NI

GNDGNDGNDGND

NI

12

SC116

0.1UF/6.3V

NI

12

SC115

0.1UF/6.3V

12

NI

SC113

0.1UF/6.3V

+12VBDC_VIN

12

SC144
22UF/16V

X5R/+/-20%

NI

GND

+1P5V_DUAL

NI

GND

B B

A A

PEGATRON DT-MB RESTRICTED SECRET

PCH_DPWROK & SLP_SUS

PCH_DPWROK & SLP_SUS

PCH_DPWROK & SLP_SUS

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

1

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

25 97Friday, January 17, 2014

25 97Friday, January 17, 2014

25 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Vinafix.com

5

I

P13:12

D D

C C

MINI_JUMPER

SPI_CS1#[22]
SPI_CS0#[22]
SPI_MISO[22]
SPI_IO2[22]

SPI_MOSI[22]
SPI_CLK[22]
SPI_IO3[22]

I

P13:34

MINI_JUMPER

NI
NI

1
3
5
7
9

11

1 2
1 2

P13

2
4

8
10
12

HEADER_2X6P_K6

I

F3R50
F3R60

+3P3V_ME

GND

4

+3P3V_ME

12

I

F3R3
1K

1%
mx_r0402_small

1 2

F3R7 33 OHMI1%

1 2

F3R8 33 OHMI1%

1 2

F3R9 33 OHMI1%

1 2

F3R10 33 OHMI1%

1 2

F3R11 33 OHMI1%

1 2

F3R12 33 OHMI1%

1 2

F3R13 33 OHMI1%

1 2

F3R14 33 OHMI1%

1 2

F3R15 33 OHMI1%

1 2

F3R16 33 OHMI1%

+3P3V_ME

12

3

I

F3R2
1K

1%
mx_r0402_small

Dual_SPI_CS1#_E19
Dual_SPI_DO
Dual_FWH_WP#

SPI_CS0#_E19
SPI_DO
FWH_WP#

GND

GND

J132

1

CS#

2

DO(IO1)

3

WP#(IO2)

4

GND

W25Q32FVSSIQ

I

J131

1

CS#

2

DO(IO1)

3

WP#(IO2)

4

GND

W25Q64FVSSIQ

I

VCC

HOLD#(IO3)

CLK

DI(IO0)

VCC

CLK

DI(IO0)

HOLD#/RESET#(IO3)

8
7
6
5

8
7
6
5

SPI_HOLD#
SPI_CK
SPI_DI

2

+3P3V_ME

Dual_SPI_HOLD#
Dual_SPI_CK
Dual_DI

+3P3V_ME

12

12

I

F3R1
1K

1%
mx_r0402_small

I

F3R4
1K

1%
mx_r0402_small

GND

12

GND

12

I

F3CB1

0.1UF/6.3V

I

F3CB3

0.1UF/6.3V

+3P3V_ME

12

GND

+3P3V_ME

12

GND

I

F3CB2
1UF/6.3V

X5R/+/-10%

I

F3CB4
1UF/6.3V

X5R/+/-10%

1

B B

A A

PEGATRON DT-MB RESTRICTED SECRET

SM BUS & SPI ROM

SM BUS & SPI ROM

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

SM BUS & SPI ROM

1

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

26 93Friday, January 17, 2014

26 93Friday, January 17, 2014

26 93Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Vinafix.com

5

A

4

3

2

1

ME Disable

D D

C C

ME_Disable#[22]

SR135

1 2

10KOhmI1%

PCH_GPIO26_R

I

PMBS3906

1

Q1

B

+3P3V

12

PCH_GPIO26_R_C

2
E

C
3

SR134
1KOhm

I
1%

HDA_SDO_R [22]

B B

<CORE DESIGN>

<CORE DESIGN>

<CORE DESIGN>

PEGATRON DT-MB RESTRICTED SECRET

Title :

Title :

Title :

ME DISABLE

ME DISABLE

ME DISABLE

Shrek_Tseng

Shrek_Tseng

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

IPPLP-TH

IPPLP-TH

IPPLP-TH

Engineer:

Shrek_Tseng

27 97Friday, January 17, 2014

27 97Friday, January 17, 2014

27 97Friday, January 17, 2014

Rev

Rev

Rev

A00

A00

A00

A

Vinafix.com

5

4

3

2

1

D D

NPO/+/-5% NI

12

12

GND

GND

NI

R60372

49.9 OHM

1%

C941289
10PF/50V

NPO/+/-5%

NI

+3V_WLAN

C C

B B

C31510PF/50V

CARD_DET#[44]

LED6

+

1 2

WHITE

GPIO_WIRELESS_DISABLE#[22]

GPIO_WIRELESS_ALERT#[20]

+3P3VSB
+3P3VSB

+3V_WLAN

12

12

LED#_WLAN_9MA

NI

SMB_DATA_RESUME[15,16,22,29,44,59,60,76,77]
SMB_CLK_RESUME[15,16,22,29,44,59,60,76,77]

1 2

SR117 10KOhmI1%

1 2

SR118 10KOhmI1%

NI

R60258

49.9 OHM

1%

LED#_BTLED#_BT_9MA

CL_RST#[20]
CL_DATA[20]
CL_CLK[20]

SUS_CLK[22,29,44]

PCIE_RST#[29,30,44]

BT_DISABLE#[22]

LED5

+

1 2

NI

WHITE

NI

1 2

APR26

0 Ohm

C941265 180PF/50V

GND

1 2

LED#_WLAN

CARD_DET#_R

I

APR25
0 Ohm

1 2
1 2
1 2

I

12

NPO 5%

12

I

C316
10PF/50V

NPO/+/-5%

GND

Mini-PCIE Slot (Half Card) for Wifi

GND

+3V_WLAN

I

S1C60

0.1UF/6.3V

MLCC/+/-10%

C941282 0.1UF/6.3V X5R/+/-10%NI

12

GND

GND

APR310 Ohm

NI

APR300 Ohm

NI

APR290 Ohm

NI

GPIO_WIRELESS_ALERT#_R

APR150 Ohm

NI

12

S1C58

0.1UF/6.3V

MLCC/+/-10%

12

I

S1C61

0.1UF/6.3V

MLCC/+/-10%

GND GND

12

CL_RST#_R
CL_DATA_R
CL_CLK_R

12

I

GNDGND

S1C59

0.1UF/6.3V

MLCC/+/-10%

12

I

78

J218

2

2

4

4

6

6

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

54

56

56

58

58

60

60

62

62

64

64

66

66

68

68

70

70

72

72

74

74

MINI_PCIE_67P

79

I

NP_NC1

NP_NC2

GND

76

1
3

SIDE1

5
7

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75

SIDE2

77

1
3
5
7

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

WLAN_PE1_TXP6_C

61

WLAN_PE1_TXN6_C

63
65
67
69
71
73
75

GND

D+
D-

GND

GND

WLAN_PE1_TXP5_C
WLAN_PE1_TXN5_C

GND

GND

GND

GND

GND

GND

GND

12
12

12
12

TC260.1UF/6.3VMLCC/+/-10% I
TC250.1UF/6.3VMLCC/+/-10% I

TC280.1UF/6.3VMLCC/+/-10% I
TC270.1UF/6.3VMLCC/+/-10% I

WLAN_PE1_TXP5 [19]
WLAN_PE1_TXN5 [19]

WLAN_PE1_RXP5 [19]
WLAN_PE1_RXN5 [19]

CK_100M_PE1 [21]
CK_100M_PE1# [21]

WLAN_CLKREQ# [22]
WAKE# [22,29]

WLAN_PE1_TXP6 [19]
WLAN_PE1_TXN6 [19]

WLAN_PE1_RXP6 [19]
WLAN_PE1_RXN6 [19]

CK_100M_PE2 [21]
CK_100M_PE2# [21]

USBP11 [19]

USBN11 [19]

H=4mm

A A

5

4

I

H2
CT217B160D130

GND

PEGATRON DT-MB RESTRICTED SECRET

NGFF KEY A(WLAN)

NGFF KEY A(WLAN)

NGFF KEY A(WLAN)

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

3

2

Date: Sheet of

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

1

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

28 97Friday, January 17, 2014

28 97Friday, January 17, 2014

28 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Vinafix.com

5

D D

+3P3V_MSATA

12

NI

R60257

49.9 OHM

1%

LED4

+

SR605
10KOhm

SMB_DATA_RESUME[15,16,22,28,44,59,60,76,77]
SMB_CLK_RESUME[15,16,22,28,44,59,60,76,77]

1 2

WHITE

DEVSLP_SSD_SLEEP_MODE

NI

1%

PCIE_RST#[28,30,44]

MSATA_CLKREQ#[22]

WAKE#[22,28]

SUS_CLK[22,28,44]

LED#_WWAN_9MA

C C

DEVSLP

]

B B

0 Ohm

NI

1 2

APR13

12

GND

WWAN_DISABLE#[22]

NI

GPS_DISABLE#[20]

GND

APR43 0 Ohm

NI

APR44 0 Ohm

NI

+3P3V_MSATA

12

C941263

0.1UF/6.3V

X5R/+/-10%

GND GND

12

NI

NI

C941264
180PF/50V

NPO 5%

1 2
1 2
1 2

+3P3V_MSATA

LED#_WWAN_9MA_OD

X5R/+/-10%

4

APR140 Ohm

12

NI

NI

C941262

0.1UF/6.3V

WAKE#_R
MFG_DATA
MFG_CLK

12

X5R/+/-10%

GND

NI

C941261

0.1UF/6.3V

J220

78

NP_NC1

2

2

4

4

6

6

8

8

10

10

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

54

56

56

58

58

60

60

62

62

64

64

66

66

68

68

70

70

72

72

74

74

79

NP_NC2

MINI_PCI_67P

NI

SIDE1

SIDE2

3

76
1

1

3

3

5

5

7

7

9

9

11

11

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

53

55

55

57

57

59

59

61

61

63

63

65

65

67

67

69

69

71

71

73

73

75

75

77

GND

CONFIG_3 [19,77]

CONFIG_0 [20,77]

SATA_RXN5_C
SATA_RXP5_C

SATA_TXN5_C
SATA_TXP5_C

SATA_RXP4_C
SATA_RXN4_C

SATA_TXN4_C
SATA_TXP4_C

CONFIG_1 [22]

CONFIG_2 [19,77]

SATA_Strap [20]

2

USBP12 [19]
USBN12 [19]

12

TC240 Ohm

NI

12

12
12

12
12

12
12

TC230 Ohm

TC210.1UF/6.3VMLCC/+/-10% NI
TC220.1UF/6.3VMLCC/+/-10% NI

TC170 Ohm
TC180 Ohm

TC190.1UF/6.3VMLCC/+/-10% NI
TC200.1UF/6.3VMLCC/+/-10% NI

SATA_RXN5 [20]

NI

SATA_RXP5 [20]
SATA_TXN5 [20]

SATA_TXP5 [20]

NI

SATA_RXP4 [20]

NI

SATA_RXN4 [20]
SATA_TXN4 [20]

SATA_TXP4 [20]

CK_100M_MSATA# [21]
CK_100M_MSATA [21]

1

D17

2N7002

32

3

D

1

1

G

S

2

NI

PEGATRON DT-MB RESTRICTED SECRET

NGFF KEY B(MSATA)

NGFF KEY B(MSATA)

NGFF KEY B(MSATA)

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

3

2

Date: Sheet of

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

1

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

29 97Friday, January 17, 2014

29 97Friday, January 17, 2014

29 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

32

3

D

D18

1

CONFIG_1 CONFIG_0

A A

5

4

H=4mm

NI

H1
CT217B160D130

GND

1

2N7002

G

S

2

NI

GND GND

Vinafix.com

5

12

I

C20

4.7UF/6.3V

X5R/+/-10%

GND GND

+3P3V

D D

12

I

C21

4.7UF/6.3V

X5R/+/-10%

GND GND GND GND GND

GND

C C

B B

A A

12

SCB53

0.1UF/6.3V

MLCC/+/-10%

12

I

SCB56

0.1UF/6.3V

MLCC/+/-10%

5

I

+3P3V+3P3V

12

GND

C304.7UF/6.3VX5R/+/-10% I
SCB600.1UF/6.3VMLCC/+/-10% I
SCB620.1UF/6.3VMLCC/+/-10% I
SCB630.1UF/6.3VMLCC/+/-10% I

GND
GND

12
12
12
12

L1

600Ohm/100Mhz/0.5A I

I

C22

4.7UF/6.3V

X5R/+/-10%

CR_PE1_TXP7[19]
CR_PE1_TXN7[19]

CR_PE1_RXP7[19]
CR_PE1_RXN7[19]

CK_100M_CR#[21]
CK_100M_CR[21]

PCIE_RST#[28,29,44]

12

21

GND GND

12

12

GND

SD_WP[30]

SD_CD#[30]

SCB54

0.1UF/6.3V

MLCC/+/-10%

C23

4.7UF/6.3V

X5R/+/-10%

C234
5pF/50V

NPO/+/-0.25PF

+3P3V

4

12

I

I

SC41 0.1UF/6.3V MLCC/+/-10%I
SC42 0.1UF/6.3V MLCC/+/-10%I

SC43 0.1UF/6.3V MLCC/+/-10%I
SC44 0.1UF/6.3V MLCC/+/-10%I

NI

0.1UF/6.3V

MLCC/+/-10%

12

0.1UF/6.3V

MLCC/+/-10%

L2 0Ohm 5%NOBOM

12

C284.7UF/6.3VX5R/+/-10% I

12
12

GND

+3P3V

1 2

I

SCB55

9

27

1

GND

42
23
13
11
10

41
36

31
28

1
4
6

5
7

8
2

3
15
14
16
17
18

X5R/+/-10%

5pF/50VNPO/+/-0.25PF NI

12

SCB57

1 2

C290.1UF/6.3VMLCC/+/-10% I
C310.1UF/6.3VMLCC/+/-10% I

12
12

12
12

NI

R232
10KOhm

1%

4

I

I

+3P3V

SCB58

+3P3V

0.1UF/6.3V

MLCC/+/-10%

12

R18191Ohm1% I

CR_PE1_TXP7_C
CR_PE1_TXN7_C

CR_PE1_RXP7_C
CR_PE1_RXN7_C

1 2

SR137 10KOhmI1%

NOBOM

SD_D1[30]
SD_CLK[30]
SD_D1#[30]

SD_CMD[30]
SD_D0#[30]

SD_D3[30]

SD_D0[30]

SD_D2[30]

T27

+3P3V

12

R24

100KOHM

I
1%

SD_D1_RCLK#[30]

SD_D0_RCLK[30]

U3A

PE_33VCCAIN
UHSII_33VCCAIN
SD_33VCCD
SD_SKT_33VIN
AUX_33VIN
MAIN_LDO_VIN
MAIN_LDO_12VOUT

CORE_12VCCD
UHSII_12VCCAIN_1

UHSII_12VCCAIN_2
UHSII_12VCCAIN_3

PE_12VCCAIN
PE_REXT
PE_RXP

PE_RXM
PE_TXP

PE_TXM
PE_REFCLKM

PE_REFCLKP
PE_RST#_GATE#
MAIN_LDO_EN
DEV_WAKE#
CLKREQ#
IO0_LDOSEL

OZ777FJ2LN

I

C33

4.7UF/6.3V

3

SD_WPI
SD_CD#

SD_CLK

SD_CMD

MMC_D7
MMC_D6
MMC_D5
MMC_D4

SD_D3
SD_D2
SD_D1
SD_D0

SD_D1P
SD_D1M
SD_D0M

SD_D0P

SD_REXT

LED#

GND1

CR_3V3CR_1V8

12
25

22
24

20
21

43
45

39
40
44
46
47
48
37
38

29
30
32
33
34
35

26

19
49

I

C34

4.7UF/6.3V

X5R/+/-10%

12

SD_CLK_B

R17 22 OHM 1%I

SD_D3_R

SD_D2_R
SD_D1_RCLK#_R
SD_D0_RCLK_R

GND

12

SCB65

0.1UF/6.3V

MLCC/+/-10%

GND

I

C24

4.7UF/6.3V

X5R/+/-10%

1 2

1%
I

GND

I

R19 22 OHM 1%I
R20 22 OHM 1%I
R21 22 OHM 1%I
R22 22 OHM 1%I

1 2

12

AUX_LDO_CAP

SD_IO_LDO_CAP

SD_SKT_33VOUT
SD_SKT_18VOUT

SD_RCLK_M

SD_RCLK_P

I

12

I

0.1UF/6.3V

MLCC/+/-10%

C370

12

12

SCB64

GNDGND GND GND

3

CR_3V3CR_1V8

12

C25
1UF/6.3V

X5R/+/-10%

GNDGND

1 2
1 2
1 2
1 2

R23

4.7KOHM

J56

1

WP_WP_

2

DAT1_RCLK-_

3

DAT0_RCLK+_DAT

4

_VSS5_

5

VSS2_VSS2_VSS

6

_D1+_

7

CLK_CLK

8

_D1-_

9

VDD_VDD1_VDD

10

_VDD2_

11

VSS1_VSS1_VSS

12

CD_CD_

13

_VSS4_

14

CMD_CMD

15

_D0-_

16

CD/DAT3_RSV

17

_D0+_

18

DAT2-__

19

_VSS3_

20

GND_GND_GND

CR_SOCKET_20P

I

I

2

C26

4.7UF/6.3V

X5R/+/-10%

CR8

WHITE

NI

2

I

+

SD_CLK_B

12

GND GND GND

12

I

SCB59

0.1UF/6.3V

MLCC/+/-10%

21

23

P_GND3

P_GND4

22

24

P_GND1

P_GND2

12

R178

300 Ohm

NI

mx_r0603

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

GND

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

12

C27
1UF/6.3V

X5R/+/-10%

12

1

L84

I

300Mhz

112

I

+3P3V

2

GND

3

SD_WP [30]

SD_CMD [30]

SCB61

0.1UF/6.3V

MLCC/+/-10%

SD_D3 [30]
SD_D2 [30]
SD_D1_RCLK# [30]
SD_D0_RCLK [30]

SD_D1 [30]
SD_D1# [30]
SD_D0# [30]
SD_D0 [30]

GND

GND

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

I

GND

1

SD_CLK [30]

12

NI

C32
5pF/50V

NPO/+/-0.25PF

GNDGND

SD_CD# [30]

12

I

12

SR136
1MOhm

5%

U3B

50

GND2

51

GND3

52

GND4

53

GND5

54

GND6

55

GND7

56

GND8

57

GND9

OZ777FJ2LN

I

CARD READER

CARD READER

CARD READER

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

30 97Friday, January 17, 2014

30 97Friday, January 17, 2014

30 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Vinafix.com

5

4

3

2

1

LED2
LED1
LED0

13
14

17
18

20
21

23
24

25
27
26

1

RSVD1_VCC3P3

2
3
6

35
33
32
34

GLAN_TCK
GLAN_TMS
GLAN_TDI
GLAN_TDO

+3P3V_LAN

12

I

LR1

4.7KOHM

12

I

LR5
10KOhm

1%

LAN_MDI0_P [32]
LAN_MDI0_N [32]

LAN_MDI1_P [32]
LAN_MDI1_N [32]

LAN_MDI2_P [32]
LAN_MDI2_N [32]

LAN_MDI3_P [32]
LAN_MDI3_N [32]

LINK_UP# [32]
LINK_1000# [32]
LAN_ACT# [32]

+3P3V_LAN

12

NI

LR2
10KOhm

5%

LAN_WAKE# [22]

LAN_DISABLE# [22]

12

GND

NI

LR4
10KOhm

5%

+3P3V_LAN+3P3V_LAN

12

I

LR6
10KOhm

1%

1

LT1

1

LT2

NOBOM
NOBOM

GND

正式料號

15
19
29

LCB4
1UF/6.3V

X5R/+/-10%

I

11
16
22
37
40
43
46
47

48
36

44
45

38
39

41
42

U4

5

VDD3P3_IN

4

VDD3P3_4

VDD3P3_15
VDD3P3_19
VDD3P3_29

7

CTRL_0P9/CTRL1P0

8

VDD0P9_8
VDD0P9_11
VDD0P9_16
VDD0P9_22
VDD0P9_37
VDD0P9_40
VDD0P9_43
VDD0P9_46
VDD0P9_47

CLK_REQ_N
PE_RST_N

PE_CLKP
PE_CLKN

PETp
PETn

PERp
PERn

+3P3V_LAN

D D

12

I

LL1

4.7uH

GND

I

LCB1
10KOhm

1%

21

12

NI

LCB9

0.1UF/16V

Keep short and width

LAN_CTRL10

LAN_COREVDD

12

NI

LCB10

0.1UF/16V

C35
68PF/50V

NPO/+/-5%
NI

LAN_PE1_RXP4_C
LAN_PE1_RXN4_C

LAN_PE1_TXP4_C
LAN_PE1_TXN4_C

+3P3V_LAN

GND

12

12

I

LR3
10KOhm

1%

LAN_CLKREQ#

12

GND

I

LCB2
22UF/6.3V

MLCC/+/-20%

12

I

LCB6

0.1UF/6.3V

12

I

LCB3

0.1UF/6.3V

GND

mx_l1210_h106

12

GND GND GND GNDGNDGND

12

NI

LCB7

0.1UF/16V

I
I

I
I

NI

LCB8

0.1UF/16V

1 2

LC1 0.1UF/16V MLCC/+/-10%

1 2

LC2 0.1UF/16V MLCC/+/-10%

1 2

LC3 0.1UF/16V MLCC/+/-10%

1 2

LC4 0.1UF/16V MLCC/+/-10%

12

GND

CK_100M_LAN[21]
CK_100M_LAN#[21]

12

LAN_PE1_RXP4[19]
LAN_PE1_RXN4[19]

LAN_PE1_TXP4[19]
LAN_PE1_TXN4[19]

I

LCB5
22UF/6.3V

mx_c0805
X5R 20%

PLTRST#[20,44,50,62]

C C

B B

:0200-00SC0DE

MDI_PLUS0

MDI_MINUS0

MDI_PLUS1

MDI_MINUS1

MDI_PLUS2

MDI_MINUS2

MDI_PLUS3

MDI_MINUS3

RSVD1_VCC3P3

LANWAKE_N

LAN_DISABLE_N

SVR_EN_N

JTAG_TCK
JTAG_TMS

JTAG_TDI

JTAG_TDO

SML0_LANNFC_CLK[22]
SML0_LANNFC_DATA[22]

LAN_XTAL_IN

LAN_XTAL_OUT

C37

C36

15PF/50V

15PF/50V

1 2

A A

5

1 2

NI

NI

GNDGND

12

I

C38
10PF/50V

Y11 25MHZ

I

1 3

2

4

GND

GNDGND

12

4

I

AC1
10PF/50V

28
31

10

9

SMB_CLK
SMB_DATA

XTAL_IN
XTAL_OUT

WGI217LM

I

3

TEST_EN

RBIAS

GND
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8

30
12
49

50
51
52
53
54
55
56
57

LAN_TEST_ENABLE
LAN_RBIAS

12

GND GND

GND

I

LR7

3.01KOHM

1%

12

I

LR8
1K 1%

mx_r0402_small

PEGATRON DT-MB RESTRICTED SECRET

INTEL CLARKVILLE

INTEL CLARKVILLE

INTEL CLARKVILLE

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

1

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

31 97Friday, January 17, 2014

31 97Friday, January 17, 2014

31 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Vinafix.com

5

NI

5%

12

LAN_MDI0_P[31]

D D

LAN_MDI0_N[31]

LAN_MDI1_P[31]

LAN_MDI1_N[31]
LAN_MDI2_P[31]

LAN_MDI2_N[31]

C C

LAN_MDI3_P[31]

LAN_MDI3_N[31]

B B

LINK_1000#[31]

LRN2A

LRN1A

LRN1B

LRN2B

LRN3A

LRN3B

LRN4A

LRN4B

14

14

NI

NI

0Ohm

0Ohm

0Ohm

0Ohm

14

14

5%

5%

5%

0Ohm

0Ohm

0Ohm

0Ohm

NI

5%

5%

5%

NI

5%

NI

I

23

90OHM/100MHZ/330mA
L66

34

12

I

23

90OHM/100MHZ/330mA
L67

34

12

NI

I

23

90OHM/100MHZ/330mA
L68

34

NI

12

I

23

90OHM/100MHZ/330mA
L69

34

+3P3V_LAN

12

12

LINK_1000#_D

32

3

D

1

1

G

S

2

I

LR10
150Ohm

5%

LR11

49.9 OHM

1%

I

Q2
2N7002

I

4

+5VA

LAN_ACT#[31]

12

I

LC5

0.1UF/6.3V

MLCC/+/-10%

GND

LAN_CTR

I

12

LCB11

0.1UF/6.3V

MLCC/+/-10%

12

I

LC7

0.1UF/6.3V

MLCC/+/-10%

GND

GND

I

12

LCB12
1UF/16V

X7R 10%
mx_c0603_small

GNDGND

LINK_1000#_R

12

I

LC8

0.1UF/6.3V

MLCC/+/-10%

+3P3V_LAN

12

LR9
150 OHM

5%
I

LANLED2

12

I

LC6
470PF/50V

X7R 10%
mx_c0402_small

GND

LAN_MDI0_P_C
LAN_MDI0_N_C
LAN_MDI1_P_C
LAN_MDI1_N_C

LAN_MDI2_P_C
LAN_MDI2_N_C
LAN_MDI3_P_C
LAN_MDI3_N_C

R10

LAN_MDI3_P_C

LAN_MDI2_N_C

J2

L1

L1

L2

L2

R1

R1

R2

R2

R3

R3

R4

R4

R5

R5

R6

R6

R7

R7

R8

R8

R9

R9
R10

L3

L3

ORANGE

L4

L4

LAN_JACK_14P

I

3

YELLOW

GREEN

UU1

CM1213_04SO

CH4

6
5

VP

P_GND2

NP_NC2

NP_NC1

P_GND1

2
4

3
1

NI

1
2
34

CH1

LAN_MDI3_N_C

VN

CH2CH3

LAN_MDI2_P_C

GND

GND

+5VA

2

CH4

UU2

6
5

VP

CM1213_04SO

1

NI

CH1

1

LAN_MDI1_N_CLAN_MDI1_P_C

VN

2

CH2CH3

34

LAN_MDI0_P_CLAN_MDI0_N_C

GND

LINK_UP#[31]

A A

PEGATRON DT-MB RESTRICTED SECRET

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

1

LAN JACK

LAN JACK

LAN JACK

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

32 97Friday, January 17, 2014

32 97Friday, January 17, 2014

32 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Vinafix.com

5

4

3

2

1

NOTE:

0722-0066000 ESD PROTECTION SOT1059 NXP/IP4284CZ10-TB
0722-003Y000 ESD PROTECTION TSLP-9-1 INFINEON/ESD5V3U4U-HDMI

I

3 4

1 2

UC1 0.1UF/6.3V

D D

C C

USB3_TXP1[19]

USB3_TXN1[19]

USB3_RXP1[19]

USB3_RXN1[19]

USBP0[19]

USBN0[19]

I

UC2 0.1UF/6.3V

I

1 2

MLCC/+/-10%

MLCC/+/-10%

USB3_TX_P1_C

90OHM/100MHZ/330mA

90OHM/100MHZ/330mA

USB3

USB3_TX_N1_C

USB3

UL1

NI

1 2

3 4

UL2

NI

1 2

14

0Ohm

5%

14

23

I

0Ohm

5%

I

0Ohm

5%

14

23

I

0Ohm

5%

I

23

90OHM/100MHZ/330mA
L3

RN4B

RN4A

RN5B

RN5A

R_LP0+

R_LP0-

UU3

1

TMDS_CH1-

2

TMDS_CH1+

3

GND1

4

TMDS_CH2­TMDS_CH2+5NC1

I

IP4284CZ10-TB

10

NC4

9

NC3

8

GND2

7

NC2

6

I

U6

CM1213_04SO

CH1

1

VN

2

CH2 CH3

3 4

CH4

6
5

VP

R_USBH_TX1+_CON

R_USBH_TX1-_CON

GNDGND

R_USBH_RX1+_CON

R_USBH_RX1-_CON

+5VA

+USBV0

GND

J212

13

P_GND4

11

P_GND2

9

9

1

1

8

8

2

2

7

7

3

3

6

6

4

4

5

5

10

P_GND1

12

P_GND3

USB_CON_9P

I

+USBV0

12

GND

Co-lay USB connecter
1213-00LH000 USB3.0
1213-00LN000 USB2.0

I

CB1

0.1UF/6.3V

GND

12

C39
10UF/6.3V

I

GND

12

12

I

UR1

8.2KOHM

I

UR2
15KOhm

U5

1.1A/6V

I

+5V_DUAL

12

OC0# [19,33,77]

Gold flash only

USBP1[19]

B B

USBN1[19]

1 2

UC3 0.1UF/6.3V

USB3_TXP2[19]

USB3_TXN2[19]

A A

USB3_RXP2[19]

USB3_RXN2[19]

I

1 2

UC4 0.1UF/6.3V

I

5

USB3_TX_P2_C

MLCC/+/-10%

90OHM/100MHZ/330mA

USB3_TX_N2_C

MLCC/+/-10%

NI

90OHM/100MHZ/330mA

USB3

UL3

UL4

NI

14

3 4

0Ohm

5%

14

1 2

0Ohm

5%

3 4

0Ohm

5%

14

1 2

0Ohm

5%

I

23

90OHM/100MHZ/330mA
L4

I

RN6B

23

I

RN6A

I

RN7B

23

I

RN7A

4

R_LP1+

R_LP1-

GND

I

UU4

1

TMDS_CH1-

2

TMDS_CH1+

3

GND1

4

TMDS_CH2­TMDS_CH2+5NC1

IP4284CZ10-TB

USB3

NC4
NC3

GND2

NC2

+USBV1

R_USBH_TX2+_CON

J221

GND

13

P_GND4

11

P_GND2

9

9

1

1

8

8

2

2

7

7

3

3

6

6

4

4

5

5

10

P_GND1

12

P_GND3

USB_CON_9P

I

R_USBH_TX2-_CON

10
9
8
7
6

GNDGND

R_USBH_RX2+_CON

R_USBH_RX2-_CON

3

+USBV1

12

GND

I

CB2

0.1UF/6.3V

GND

12

C40
10UF/6.3V

I

12

12

GND

I

UR3

8.2KOHM

I

UR4
15KOhm

U7

1.1A/6V

I

PEGATRON DT-MB RESTRICTED SECRET

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

IPPLP-TH

IPPLP-TH

IPPLP-TH

Engineer:

1

+5V_DUAL

12

OC0# [19,33,77]

SIDE USB3.0 PORT

SIDE USB3.0 PORT

SIDE USB3.0 PORT

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

33 97Friday, January 17, 2014

33 97Friday, January 17, 2014

33 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Vinafix.com

5

4

3

2

1

3 4

NI

1 2

USB3_TXP3[19]

D D

USB3_TXN3[19]

USB3_RXP3[19]

USB3_RXN3[19]

C C

USBP2[19]

USBN2[19]

USBP3[19]

USBN3[19]

B B

USB3_TXP4[19]

USB3_TXN4[19]

A A

USB3_RXP4[19]

USB3_RXN4[19]

UC5 0.1UF/6.3V

NI

1 2

UC6 0.1UF/6.3V

UC7 0.1UF/6.3V

NI

UC8 0.1UF/6.3V

NI

5

MLCC/+/-10%

MLCC/+/-10%

1 2

1 2

USB3_TX_P3_C

USB3_TX_N3_C R_USBH_TX3-_CON

USB3_TX_P4_C

MLCC/+/-10%

USB3_TX_N4_C R_USBH_TX4-_CON

MLCC/+/-10%

NI

NI

NI

NI

NI

NI

NI

NI

1 2

3 4

1 2

3 4

1 2

3 4

1 2

0Ohm

5%

14

0Ohm

5%

0Ohm

5%

14

0Ohm

5%

14

14

0Ohm

5%

14

0Ohm

5%

0Ohm

5%

14

0Ohm

5%

RN8B

23

NI

UL5
90OHM/100MHZ/330mA

RN8A

RN9B

23

NI

UL6
90OHM/100MHZ/330mA

RN9A

I

23

90OHM/100MHZ/330mA
L5

I

23

90OHM/100MHZ/330mA
L6

RN10B

23

NI

UL7
90OHM/100MHZ/330mA

RN10A

RN11B

23

UL8

NI

90OHM/100MHZ/330mA

RN11A

4

NI

UU5

1

TMDS_CH1-

2

TMDS_CH1+

3

GND1

4

TMDS_CH2­TMDS_CH2+5NC1

IP4284CZ10-TB

R_LP2+

R_LP2-

GND

R_LP3+

R_LP3-

NI

UU6

1

TMDS_CH1-

2

TMDS_CH1+

3

GND1

4

TMDS_CH2­TMDS_CH2+5NC1

IP4284CZ10-TB

NC4
NC3

GND2

NC2

NC4
NC3

GND2

NC2

10
9
8
7
6

10
9
8
7
6

GNDGND

I

U9

CM1213_04SO

CH1

1

VN

2

CH2 CH3

3 4

CH4

6
5

VP

R_USBH_TX4+_CON

GNDGND

R_USBH_RX4+_CON

R_USBH_RX4-_CON

3

R_USBH_TX3+_CON

R_USBH_RX3+_CON

R_USBH_RX3-_CON

GND

+5VA

GND

I

J223
USB_CON_9P

9

SSTX+

8

SSTX-

7

GND_DRAIN

6

SSRX+

5

SSRX-

4

GND

I

J211
USB_CON_9P

9

SSTX+

8

SSTX-

7

GND_DRAIN

6

SSRX+

5

SSRX-

4

GND

P_GND1
P_GND2
P_GND3
P_GND4

VBUS

+5V_DUAL

+USBV2

+USBV2

1

VBUS

2

D-

3

D+

10

P_GND1

11

P_GND2

12

P_GND3

13

P_GND4

+USBV3

1
2

D-

3

D+

10
11
12
13

12

GND GND

+USBV3

12

GND

I

CB3

0.1UF/6.3V

I

CB4

0.1UF/6.3V

GND

12

12

I

C41
10UF/6.3V

I

C42
10UF/6.3V

GND

GND

12

12

12

12

I

UR5

8.2KOHM

I

UR6
15KOhm

I

UR7

8.2KOHM

I

UR8
15KOhm

U8

1.1A/6V

I

U10

1.1A/6V

I

12

OC1# [19,34,77]

+5V_DUAL

12

OC1# [19,34,77]

PEGATRON DT-MB RESTRICTED SECRET

REAR USB3.0 PORT

REAR USB3.0 PORT

REAR USB3.0 PORT

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

IPPLP-TH

IPPLP-TH

IPPLP-TH

Engineer:

1

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

34 97Friday, January 17, 2014

34 97Friday, January 17, 2014

34 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Vinafix.com

5

4

3

2

1

3 4

NI

1 2

USB3_TXP5[19]

USB3_TXN5[19]

D D

USB3_RXP5[19]

USB3_RXN5[19]

C C

USBP4[19]

USBN4[19]

UC9 0.1UF/6.3V

NI

UC10 0.1UF/6.3V

1 2

MLCC/+/-10%

MLCC/+/-10%

NI

14

USB3_TX_P5_C

USB3_TX_N5_C

23

90OHM/100MHZ/330mA
L7

NI

NI

NI

NI

1 2

3 4

1 2

0Ohm

5%

2 3

0Ohm

5%

0Ohm

5%

2 3

0Ohm

5%

RN12B

NI

UL9
90OHM/100MHZ/330mA

1 4

RN12A

RN13B

NI

UL10
90OHM/100MHZ/330mA

1 4

RN13A

R_LP4+

R_LP4-

NI

UU7
IP4284CZ10-TB

1

TMDS_CH1-

2

TMDS_CH1+

3

GND1

4

TMDS_CH2­TMDS_CH2+5NC1

NC4
NC3

GND2

NC2

GND

10
9
8
7
6

R_USBH_TX5+_CON

R_USBH_TX5-_CON

GNDGND

R_USBH_RX5+_CON

R_USBH_RX5-_CON

I

U12

CM1213_04SO

CH1

1

VN

2

CH2 CH3

3 4

VBUS

+USBV4

1
2

D-

3

D+

10
11
12
13

+USBV4

12

GND

NI

CB5

0.1UF/6.3V

GND

12

NI

C43
10UF/6.3V

GND

12

12

NI

UR9

8.2KOHM

NI

UR10
15KOhm

U11

1.1A/6V

NI

+5V_DUAL

12

OC2# [19,35,77]

NI

J224
USB_CON_9P

9

SSTX+

8

SSTX-

7

GND_DRAIN

6

SSRX+

5

SSRX-

4

GND

GND

CH4

6
5

VP

+5VA

P_GND1
P_GND2
P_GND3
P_GND4

I

14

USBP5[19]

USBN5[19]

B B

NI

1 2

USB3_TXP6[19]

USB3_TXN6[19]

USB3_RXP6[19]

A A

USB3_RXN6[19]

UC11 0.1UF/6.3V

NI

UC12 0.1UF/6.3V

1 2

5

MLCC/+/-10%

MLCC/+/-10%

23

90OHM/100MHZ/330mA
L8

NI

USB3_TX_P6_C

USB3_TX_N6_C

NI

NI

NI

3 4

0Ohm

5%

2 3

1 2

0Ohm

5%

3 4

0Ohm

5%

2 3

1 2

0Ohm

5%

R_LP5+

R_LP5-

RN14B

NI

UL11
90OHM/100MHZ/330mA

1 4

RN14A

RN15B

NI

UL12
90OHM/100MHZ/330mA

1 4

RN15A

+5V_DUAL

+USBV5

R_USBH_TX6+_CON

12

CB6

R_USBH_TX6-_CON

NI

UU8
IP4284CZ10-TB

1

TMDS_CH1-

2

TMDS_CH1+

3

GND1

4

TMDS_CH2­TMDS_CH2+5NC1

4

NC4
NC3

GND2

NC2

10
9
8
7
6

GNDGND

R_USBH_RX6+_CON

R_USBH_RX6-_CON

3

GND

I

J225
USB_CON_9P

9

SSTX+

8

SSTX-

7

GND_DRAIN

6

SSRX+

5

SSRX-

4

GND

P_GND1
P_GND2
P_GND3
P_GND4

VBUS

+USBV5

1
2

D-

3

D+

10
11
12
13

2

0.1UF/6.3V

GND

12

I

I

CE1
10UF/6.3V

GND

<Core Design>

<Core Design>

<Core Design>

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

12

I

UR11

8.2KOHM

12

I

UR12
15KOhm

GND

IPPLP-TH

IPPLP-TH

IPPLP-TH

U13

1.1A/6V

I

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

1

12

OC2# [19,35,77]

REAR USB3.0 PORT

REAR USB3.0 PORT

REAR USB3.0 PORT

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

35 97Friday, January 17, 2014

35 97Friday, January 17, 2014

35 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Vinafix.com

5

D D

C C

USBN8[19]

USBP8[19]

USBN9[19]

USBP9[19]

90OHM/100MHZ/330mA

90OHM/100MHZ/330mA

L9

I

1 4

2 3

I

L10

1 4

2 3

4

LP8-

LP8+

+5VA

CH4

VP

LP9-

LP9+

GND

CM1213_04SO

CH1

1
2
3 4

U15

I

6
5

VN

CH2 CH3

3

+USBV89

GND

+USBV89

J210

1

1

P_GND4

2

2

P_GND3

3

3

P_GND2

44P_GND1

USB_CON_1X4P

I

J222

1

1

P_GND4

2

2

P_GND3

3

3

P_GND2

44P_GND1

USB_CON_1X4P

I

2

+USBV89

8
7
6
5

8
7
6
5

NI

GNDGND

12

+

CB32
100UF/16V

12

GND

I

CB7

0.1UF/6.3V

GND

12

I

C44

10UF/6.3V

GND

12

12

I

UR13

8.2KOHM

I

UR14
15KOhm

1 2

U14

2A/6V

I

1

+5V_DUAL

OC4# [19,77]

GND

B B

A A

5

4

3

GND

<Core Design>

<Core Design>

<Core Design>

PEGATRON DT-MB RESTRICTED SECRET

REAR USB2.0 PORT

REAR USB2.0 PORT

REAR USB2.0 PORT

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

IPPLP-TH

IPPLP-TH

IPPLP-TH

Engineer:

1

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

36 97Friday, January 17, 2014

36 97Friday, January 17, 2014

36 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Vinafix.com

5

4

3

2

1

Touch Power Connector

D D

Touch Panel Connector

I

C C

Camera Module Connector

B B

USBN7[19]

USBP7[19]

12

I

D2

A A

L06ESDU5V0CE2

5

USBN6[19]

USBP6[19]

3 4

0Ohm

5%

14

1 2

0Ohm

5%

LP7-LP7+ DMIC-DATADMIC-CLK

12

I

D3
L06ESDU5V0CE2

GNDGND GNDGND

23

1 2

3 4

I

RN17B

90OHM/100MHZ/330mA
UL14

NI

I

RN17A

12

I

D4
AZ2025-01H

0Ohm

5%

1 4

0Ohm

5%

4

RN16A

90OHM/100MHZ/330mA
UL13

NI

2 3

I

RN16B

LP7-

LP7+

CAMERA_CBL_DET#[22]

DMIC-DATA[40]

DMIC-CLK[40]

12

D5
AZ2025-01H

LP6-

NPO/+/-5% I

NI

UD1
PGB1010603NR

GND

12

GND

12

NI

UD2
PGB1010603NR

12

I

AC37
22PF/50V

NPO/+/-5%

GND GND

LP6+

Touch_CBL_DET#[20]

AR26 33 OHMI1%

I

12

GND GND GND

1 2

3

+5V_DUAL

12

UF1

1.1A/6V

12

TOUCH_PWR

C30410PF/50V

I

I

12

NI

AC38

4.7UF/10V

X5R/+/-10%

GND

1 2

UCB1

0.1UF/6.3V

MLCC/+/-10%

NPO/+/-5% I

12

GND

AR1 33 OHMI1%

I

AC2
22PF/50V

NPO/+/-5%

GND

1
2
3
4
5

12

AC36

4.7UF/10V

X5R/+/-10%

I

WAFER_BOX_5P

P16

12

I

2

+3P3V

12

C30510PF/50V

R_DMIC-DATA

12

GND

I

UF2

1.1A/6V

DMIC-CLK_C

UCB2
470PF/50V

X7R 10%
I

Install MLCC 1UF/10V(0402) X5R 10%
1AX200271000
1A20-00A6600
1A20-00A7C00
1A20-00A5D00
1A20-00WTA00

P464

1

1

2

2

3

3

4

4

5

5

6

6

7
8

GND

<CORE DESIGN>

<CORE DESIGN>

<CORE DESIGN>

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

7

SIDE1

8

SIDE2

WtoB_CON_8P

Critical

9
10

IPPLP-TH

IPPLP-TH

IPPLP-TH

GND

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

1

TOUCH & WEBCAM

TOUCH & WEBCAM

TOUCH & WEBCAM

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

37 97Friday, January 17, 2014

37 97Friday, January 17, 2014

37 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Vinafix.com

5

D D

C C

4

3

2

1

B B

A A

PEGATRON DT-MB RESTRICTED SECRET

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

1

XXXXXX

XXXXXX

XXXXXX

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

38 97Friday, January 17, 2014

38 97Friday, January 17, 2014

38 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Vinafix.com

5

4

3

2

1

SATA CONNECTOR

NOTE:

Place those Cap close to Conn sode
To Conn distance are less then 500mils

D D

C C

+5V

SATA_TXP0[20]
SATA_TXN0[20]

SATA_RXN0[20]
SATA_RXP0[20]

21

L8270Ohm/100Mhz I

1 2

TC9 0.01UF/25V X7R 10%

I

1 2

TC10 0.01UF/25V X7R 10%

I

1 2

TC11 0.01UF/25V X7R 10%

I

1 2

TC12 0.01UF/25V X7R 10%

I

12

I

C45

0.1UF/6.3V

MLCC/+/-10%

GND GND

12

C306
10PF/50V

NPO/+/-5%

I

SATA_TXP0_C
SATA_TXN0_C

SATA_RXN0_C
SATA_RXP0_C

GND

P60 SATA_CON_22P

NP_NC3

S1

S1

S2

S2

NP_NC1

S3

S3

S4

S4

S5

S5

S6

S6

S7

S7

P1

P1

P2

P2

P3

P3

P4

P4

P5

P5

P6

P6

P7

P7

P8

P8

P9

P9

P10

P10

P11

P11

P12

P12

P13

P13

P14

P14

P15

NP_NC2

P15

NP_NC4

I

3
1

2
4

B B

GND

COLOR = WHITE

P61

1

1 2

TC14 0.01UF/25V X7R 10%

SATA_TXP1[20]
SATA_TXN1[20]

SATA_RXN1[20]
SATA_RXP1[20]

A A

I

1 2

TC13 0.01UF/25V X7R 10%

I

1 2

TC15 0.01UF/25V X7R 10%

I

1 2

TC16 0.01UF/25V X7R 10%

I

SATA_TXP1_C
SATA_TXN1_C

SATA_RXN1_C
SATA_RXP1_C SATA_CON3_5V

GND

GND1

2

TX+

3

TX-

4

GND2

5

RX-

6

RX+

7

GND3

SATA_CON_7P

HOLD1

HOLD2

8

9

ODD EJECT

+5V

21

ODD_2ndHDD_CBL_DET#[20]

L1170Ohm/100Mhz I

12

NI

C47
10UF/6.3V

MLCC/+/-10%

GND GND

1 2

12

I

C48

0.1UF/6.3V

MLCC/+/-10%

C46
10PF/50V

I

12

GND

I

C49

0.1UF/6.3V

MLCC/+/-10%

GND

WAFER_HD_1X4P

1
2
3
4 5

ODD-PWR

I

HF

PEGATRON DT-MB RESTRICTED SECRET

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

1

SATA CONN

SATA CONN

SATA CONN

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

39 97Friday, January 17, 2014

39 97Friday, January 17, 2014

39 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Vinafix.com

5

1

1

1

4

3

2

1

ALC3661 CODEC

I

GND

AGND

AGND

AGND

AU1A
ALC3661-CG-A3

11

DVDD

7

DVDD-IO

49

GND

8

SDATA-IN

4

SDATA-OUT

9

SYNC

6

RESETB

5

BCLK

10

REGREF

14

EAPD

15

SPDIF-OUT

16

SPDIF-IN

2

PCBEEP

12

GPIO0/DMIC-CLK

13

GPIO1/DMIC-DATA

17

GPIO2/Combo-Jack1

3

GPIO3/Combo-Jack2

39

LDO-IN

42

AVSS2

23

HVDD

25

DVDD-IO-CP

22

AVSS1

20

CPVEE

28

CPVREF

SURR-R(PORT-A-R)

SURR-L(PORT-A-L)

MIC1-R(PORT-B-R)

MIC1-L(PORT-B-L)/MIC-CAP

LINE1-R(PORT-C-R)

LINE1-L(PORT-C-L)

FRONT-R(PORT-D-R)

FRONT-L(PORT-D-L)

LINE2-IN-R(PORT-E-R)/SLEEVE

LINE2-IN-L(PORT-E-L)/RING2

MIC2-VREFO

LFE(PORT-G-R)
CEN(PORT-G-L)

SenseA

SenseB

MIC2-R(PORT-F-R)

MIC2-L(PORT-F-L)

LINE2-VREFO

MIC1-VREFO

CBP
CBN

JDREF

LDO-CAP

VREF

VRP

I

AU1B
ALC3661-CG-A3

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8

3

27
26

37
36

46
45

44
43

32
31

1

18
19

34

33

48
47
29
30

24
21
35
40
41
38

50
51
52
53
54
55
56
57

AC41
10UF/6.3V

X5R/+/-20%

MIC-CAP

AMP_LINE_OUTR_C
AMP_LINE_OUTL_C

SENSE_B

CBP
CBN
JDREF
LDO-CAP
VREF
VRP

I

12

AGND

GND

ForMICquality

1 2

AC6 10UF/6.3VI

1 2

C50 0 Ohm

I

1 2

C51 0 Ohm

I

Tracewidth>40mils

ClosetoPin33

1 2

AR5 5.1KOHM 1%I

1 2

AR6 10KOhmI1%

1 2

AR20 2.2KOHM 1%I

1 2

AR21 2.2KOHM 1%I

I

4.5V

12

NI

+

AC20
100UF/6.3V

TAN/Lf_T=2000hrs_105C/+/-20%

ClosetoPin38
MUSTusePOSCAPorPLcap.
ForDELLperformanceand
DAC/ADCperformanceinCodec.

12

AC21

2.2UF/6.3V

X5R/+/-10%

I

2

AC14

1 2

1UF/6.3V

X5R/+/-10%

12

AGND

I

AC22
10UF/6.3V

X5R/+/-20%

12

AGNDAGND

HPOUT1_R [42]
HPOUT1_L [42]

AGND

LINE1-R [42]
LINE1-L [42]

AMP_LINE_OUTR [41]
AMP_LINE_OUTL [41]

SLEEVE [40,42]
RING2 [40,42]

MIC2-VREFO [42]

HPOUT2_R [42]
HPOUT2_L [42]

HPOUT1_JD [42]
HPOUT2_JD [42]

MIC2-R [42]

MIC2-L [42]
SLEEVE [40,42]
LINE1-VREFO [42]

RING2 [40,42]

I

AC23

0.1UF/6.3V

MLCC/+/-10%

12

I

AR9
20KOhm

1%

AGNDAGND

ToGlobalHeadset

ToRearLineOUT

ToAmplifier

FromGlobalHeadset

ToGlobalHeadset

ToRearHeadphone

FromGlobalHeadset

FromRearHeadphone

FromGlobalHeadset

ToGlobalHeadset

ClosetoPin35

PEGATRON-BU5 RESTRICTED SECRET

AUDIO CODEC ALC366

AUDIO CODEC ALC366

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

Engineer:

IMPLP-TH

IMPLP-TH

IMPLP-TH

AUDIO CODEC ALC366

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

40 97Friday, January 17, 2014

40 97Friday, January 17, 2014

1

40 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

+3P3V

I

12

AC3

D D

AZ_SDATA_IN[22]
AZ_SDATA_OUT[22]
AZ_SYNC[22]
AZ_RST#[22,42]
AZ_BITCLK[22]

12

AC7
22PF/50V

NPO/+/-5%

GND

1 2

C C

B B

NI

VP

GND

A A

AMP_DISABLE_CODE#[41]

DMIC-CLK[37]
DMIC-DATA[37]

SCALAR_MODE#[20]

NOBOM

S1
SHORTPIN

1 2

1 2

AC15 0.1UF/16V

AR7 0

1 2

X7R 10%

+3P3V

AGND

5

R27 0 OhmI

+3P3V

12

SR2110KOhm I

I

12

NI

AC11

22PF/50V

NPO/+/-5%

GND

D519

AZ5125-01H

GND

12

AC16

10UF/6.3V

AGND

10UF/6.3V

X5R/+/-20%

GND GND GND

12

NI

AC8
22PF/50V

NPO/+/-5%

GND GND

ClosetoPin12

1 2

AR4 0

+5VSB

I

I

APR47

1 2

NI

APR46

1 2

12

12

0.1UF/6.3V

MLCC/+/-10%

+5VA

NI

mx_r0805

I

AC17

mx_r0805

0

0

AGND

AGNDAGND

12

0.1UF/6.3V

MLCC/+/-10%

12

AC9
22PF/50V

NPO/+/-5%

12

AC12
10UF/6.3V

X5R/+/-20%

12

4

I

AC4

I

AR3
33

1 2

NI

SPDIF_OUT[51]

I

I

AC18

10UF/6.3V

12

AC5

0.1UF/6.3V

MLCC/+/-10%

SDATA_IN_R

REGREF

I

12

AC10
10UF/6.3V

X5R/+/-20%

GND

R_DMIC-CLK

ClosetoPin39

12

AC13

0.1UF/6.3V

MLCC/+/-10%

AGND

12

0.1UF/6.3V

MLCC/+/-10%

AGND

CPVEE

12

I

AC24

1UF/6.3V

X5R/+/-10%

AGND

I

I

AC19

1.8V

I

Vinafix.com

5

I

C950
1UF/16V

X7R/+/-10%

1 2

1 2

AMP_DISABLE_CODE#[40]

R29 0 Ohm

12

R48

100KOHM

1%

12

I

R47

5.6KOHM

1%

GND

R58 0 Ohm

I

NI

R52
10KOhm

1%

I

R57
10KOhm

1%

C74

1 2

0.1UF/6.3V

NI

C78

1 2

0.1UF/6.3V

NI

D D

C C

1 2

R31 0 Ohm

AMP_LINE_OUTL[40]

B B

AM0
AM1
AM2

+12V_HDD

12

I

C79
1UF/16V

A A

X7R/+/-10%

GND

5

I

+12V_HDD +12V_HDD +12V_HDD

NI

R50
10KOhm

1%

1 2

I

R53
10KOhm

1%

1 2

GND GND GND

C73

1 2

0.1UF/6.3V

NI

C77

1 2

0.1UF/6.3V

NI

SIO_SPEAKER[44]

AMP_LINE_OUTR[40]

12

AGND

12

NI

R32
10K

mx_r0402_small

AGND

NI

R51
10KOhm

1%

1 2

I

R54
10KOhm

1%

1 2

AGNDGND AGND AGNDGND GND

1 2

I

NI

1 2

SPKR[22]

4

+3P3V

12

R28
1KOhm

I
1%

12

X5R/+/-10%

1 2

D511

2N7002

C86 1UF/6.3VX5R/+/-10% I

12

C87 1UF/6.3VX5R/+/-10% I

12

R33
0 Ohm

5%

I

AGNDAGND

PLIMIT
GVDD
GAIN

AGND

12

1

1

G

12

+3P3V

3

2

GND

12

2N7002

32

D

S

I

R60385
10KOhm

1%

D516

I

GND

1

1

12

NEGATIVE_LEFT

AMP_MUTE

R49 100KOHM

+3P3VA

12

R168
100KOHM

AMP_MUTE

32

3

D

G

S

2

I

I

AC40

0.1UF/6.3V

MLCC/+/-10%

GND

C76

1 2

0.1UF/6.3V

NI

12

R30
10KOhm

1%

NI

12

I

R25

4.75KOHM

12

I

R100

1.69KOHM

C135 1UF/6.3V

I

5%

L+ POSTIVE_LEFT

PCH_GPIO53[20]

1 2

0.1UF/6.3V

1 2

0.1UF/6.3V

4

C75

NI

C80

NI

C67 100PF/50VNPO 5%

I

C89 1UF/6.3VX5R/+/-10% I

GND

1 2

I

1%

AGNDGND

3

NEGATIVE_RIGHT

1
2
3
4
5
6
7
8

AM2

1%
NI

C136

0.1UF/16V

X7R 10%

3

2

+12V_HDD

1 2

C258 0.01UF/25V

I

1 2

C137 0.1UF/16VIX7R 10%

1 2

R202 10 OHM NI

12

GND

32

31

30

29

33

U2A

SDZ

INPR

INNR

GND5

12

FAULTZ

AM19AM010SYNC11AVCC12PVCC113PVCC214BSPL15OUTPL

AM1

AM0

I

C145

0.1UF/16V

X7R 10%

GND GNDGND

PLIMIT
GVDD
GAIN/SLV
AGND
INNL
INPL
MUTE
AM2

TPA3131MP

I

+12V_HDD

I

OUT_P_RIGHT_B OUT_P_RIGHT_L
OUT_N_RIGHT_B OUT_N_RIGHT_L
OUT_P_LEFT_B OUT_P_LEFT_L
OUT_N_LEFT_B OUT_N_LEFT_L

C351 330PF/50V NI
C235 0.22UF/16V I

27

26

25

BSPR

PVCC428PVCC3

OUTPR

GND4

OUTNR

BSNR
GND3
GND2
BSNL

OUTNL

GND1

16

12

C142

0.01UF/25V

I

L78
L79
L80
L81

12

OUT_P_RIGHT

24
23
22
21
20
19
18
17

+12V_HDD

12

21

600Ohm/100MhzI

21

600Ohm/100MhzI

21

600Ohm/100MhzI

21

600Ohm/100MhzI

GND

GND

GND

1 2

R210 10 OHMNI
C355 330PF/50VNI
C139 0.22UF/16VI

12

+

CE7
100UF/16V

TAN/Lf_T=2000hrs_105c/+/-20%

I
GND

C147 1000PF/50VX7R/+/-10%I
C148 1000PF/50VX7R/+/-10%I
C149 1000PF/50VX7R/+/-10%I
C150 1000PF/50VX7R/+/-10%I

GND
GND

GND

C233 0.22UF/16V

C138 0.22UF/16VI
C353 330PF/50VNI

R204 10 OHMNI

GND

12
12

1 2
1 2
1 2
1 2

2

1 2

600Ohm/100Mhz

L77

I

12

I

GND

12
12

600Ohm/100Mhz

I

GND
GND
GND
GND

1

21

OUT_P_RIGHT_B

600Ohm/100Mhz

L74

21

I

C352 330PF/50V NI
R203 10 OHM NI

I

GND

L75

21

<Variant Name>

<Variant Name>

<Variant Name>

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

12

1 2

600Ohm/100Mhz

L76

21

OUT_P_LEFT_BOUT_P_LEFT

GND

SPKR_CBL_DET#[22]

IPPLP-TH

IPPLP-TH

IPPLP-TH

OUT_P_LEFT_L
OUT_N_LEFT_L

GND

OUT_N_RIGHT_L
OUT_P_RIGHT_L

OUT_N_LEFT_BOUT_N_LEFT

U2B

34
35
36
37
38
39
40
41

TPA3131MP

I

Engineer:

Engineer:

Engineer:

OUT_N_RIGHT_BOUT_N_RIGHT

GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13

WAFER_HD_1X6P

12

GND

Title :

Title :

Title :

1

P89

1
2
3
4
5
6

I

I

C232

0.1UF/6.3V

MLCC/+/-10%

AMP

AMP

AMP

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

41 97Friday, January 17, 2014

41 97Friday, January 17, 2014

41 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Vinafix.com

5

4

3

2

GND GND

1

REAR LINE-OUT

SupportRe‐TaskingFunction

LINE1-L[40]

D D

C C

LINE1-R[40]

HPOUT2_R[40]
HPOUT2_L[40]

LINE1-VREFO[40]

HPOUT2_JD[40]

X5R/+/-10% NI

1 2

X5R/+/-10% NI

1 2

AR14 20 OHM 1%I
AR15 20 OHM 1%I

2

PD1

3

1

NI

BAT54AW

AC254.7UF/10V

AC264.7UF/10V

GLOBAL HEAD SET CONNECTOR

X5R/+/-10% I

1 2

1 2

AC294.7UF/10V

AC304.7UF/10V

MIC2-L[40]

MIC2-R[40]

X5R/+/-10% I

ClosetoCODEC

B B

SLEEVE[40]
RING2[40]
HPOUT1_R[40]
HPOUT1_L[40]

HPOUT1_JD[40]

PD2

MIC2-VREFO[40]

3

I

BAT54AW

AR22 20 OHM 1%I
AR23 20 OHM 1%I

2
1

1%

1%

1 2
1 2

1 2

1 2

12

HR694.7KOHM

12

HR704.7KOHM

R3875 OHM

I

R3975 OHM

I

I

AZ_RST#[22,40]

mx_r0402_small

I1%
I1%

1 2
1 2

分支點

AR19

1 2

1K1%

1%

1%

1 2

1 2

12

HR674.7KOHM

12

HR684.7KOHM

1

1

R3675 OHM

NI

R3775 OHM

NI

NI1%
NI1%

+3P3VA

12

AR17

100KOHM

I
1%

1

32

3

D

I

G

AQ3

S

2

2N7002

AGND

denpendlayout

32

3

D

I

AQ2

1

2N7002

G

S

2

AGND

GND GND GND GND

I

AD6
AZ2025-01H

1 2

12

NPO/+/-5%

I

AC31
470PF/50V

NPO 5%

1 2

APR55 0Imx_r0805
APR54 0Imx_r0805

12

I

AC32
470PF/50V

NPO/+/-5%

NPO 5%

I

AD1
AZ2025-01H

1 2

12

I

AC27
100PF/50V

NPO 5%

AGND AGND

GlobalHeadset
(Supported4PiniPhone/Nokiaheadset,Headphone)
(Supported3PinHeadphone,Micphone)

I

AD3
AZ2025-01H

1 2
1 2

1 2

12

1 2

12

I

AC33
680PF/50V

MLCC/+/-10%

I

AD2
AZ2025-01H

HPOUT2_R_C
HPOUT2_L_C

I

AC28
100PF/50V

NPO 5%

I

AD4
AZ2025-01H

1 2

12

AGNDAGNDAGNDAGND

I

AD5
AZ2025-01H

I

AC34
680PF/50V

MLCC/+/-10%

LINEOUT

J110

1

1

5

5

4

4

3

3

2

2

6

P_GND1

7

P_GND2

8

P_GND3

PHONE_JACK_5P

I

GND

AGND

COMBOAUDIO

I

J27

PHONE_JACK_6P

SLEEVE_B
RING2_B
R_HPOUT_R
R_HPOUT_L

GND

AGND

4
3
2
1

5
6
7

MS

8
9

NP_NC

10

GHS JACK
12X141608000 -->12X141940000

A A

PEGATRON DT-MB RESTRICTED SECRET

REAR LINE OUT& GHS CONN

REAR LINE OUT& GHS CONN

REAR LINE OUT& GHS CONN

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

IPPLP-TH

IPPLP-TH

IPPLP-TH

Engineer:

1

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

42 97Friday, January 17, 2014

42 97Friday, January 17, 2014

42 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Vinafix.com

5

D D

C C

4

3

2

1

B B

A A

PEGATRON DT-MB RESTRICTED SECRET

XXXXXX

XXXXXX

XXXXXX

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

IPPLP-TH

IPPLP-TH

IPPLP-TH

Engineer:

1

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

43 97Friday, January 17, 2014

43 97Friday, January 17, 2014

43 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Vinafix.com

5

D D

GND GND

NI

SCB71
10PF/50V

1 2

1 2

SMB_CLK_RESUME[15,16,22,28,29,59,60,76,77]
SMB_DATA_RESUME[15,16,22,28,29,59,60,76,77]
SIO_SMLINK_DATA[22]
SIO_SMLINK_CLK[22]

12

O2CB11

0.1UF/6.3V

MLCC/+/-10%

+12V_ENG#[67]

O2R13

8.2KOHM

1%
I

O2R14
10KOhm

1%
I

+3P3VSB

I

GND

12

12

NI

SCB73
10PF/50V

GND GND

1

1

+3P3V

12

RO1

8.2KOHM

12

RO2

7.15KOHM

+3P3V

12

12

NI

SCB74
10PF/50V

32

3

G

2

GND

+1P05V_PCH

RO3

8.2KOHM

RO4

7.15KOHM

SIO_PECI_R

12

NI

SC45
15PF/50V

NPO 5%

+1P5V_DUAL

5

C1

B2

O2Q3
MBT3904DW1T1G

Ic=200mA/150mW

I

C2

O_DTR2#_R

GND

+3P3V

12

GND

+12V_CPU

GND

O2R3

8.2KOHM

1%
I

O2R8
680Ohm

1%
I

5VA MONITOR

+12VSA

12

OR3

56.2K

I

12

OR2
10KOhm

GND

GND

MBT3904DW1T1G

Ic=200mA/150mW

+3P3VA

12

I

O2R11

30KOHM

1%

VRM_PWRGD[22,64,76]

1%

V5_ALW_MON

I

12

1%

GND

O2Q1

I

I

AC39

2.2UF/6.3V

X5R/+/-10%

5

B2

C2

O_TXD2_R

+3P3V

12

30KOHM

5

GND

I

O2R15

1%

O_RTS2#_R

6

C1

E1E2B1

123 4

6

E1E2B1

123 4

C C

B B

A A

4

GND

12

12

I

SCB66
180PF/50V

SUS_CLK[22,28,29]

CK_14M_SIO[21]

LAD0[22,50,62]
LAD1[22,50,62]
LAD2[22,50,62]
LAD3[22,50,62]

NI

SCB72
10PF/50V

D

S

I

PQ9503
2N7002

PECI_SIO[11]

I

O2CB15

0.1UF/6.3V

MLCC/+/-10%

+3P3V

LFRAME#[22,50,62]
PLTRST#[20,31,50,62]
CK_33M_SIO[21]

SERIRQ[20,62]

O_IO_PME#[22]

SLP_A#[22,50,68,91]

+1V_VCCST

12

12

I

OR7

GND

10KOhm

1%

12

GND

+3P3VSB

SLP_SUS#[22,70,71]

GND

+3P3VSB

12

O_TXD2_R

O_TXD2_R

+1P05V_ME

TMIN_SHIFT[22]

O2CB14

0.1UF/16V

1 2

NI

GND

6

C1

E1E2B1

123 4

6

C1

E1E2B1

123 4

4

+3P3V

12

5

B2

+3P3V_ME

5

B2

I

O2R12
30KOHM

+5V

O2Q2
MBT3904DW1T1G

Ic=200mA/150mW

I

C2

O2Q6
MBT3904DW1T1G

Ic=200mA/150mW

I

C2

SIO_SPEAKER[41]

PWRBTN#[22,50,55,76,77] PROCHOT# [11,64]

NPO 5%

1 2

OR1 1K 1%Imx_r0402_small

I

0.1UF/6.3V
O2CB10

MLCC/+/-10%

SLP_S3#[22,50,67,72,74]
SLP_S4#[22,50,68,72]

PCH_DPWROK[22,77]

NI

+3P3VA

12

O2CB12

0.1UF/6.3V

MLCC/+/-10%

GND

I

SR139
10KOhm

1%

12

GND

SIO_TX0

+3P3V

12

12

GND

O_TXD2_R

PCIE_RST#[28,29,30]
GPU_RST#[79]

PS_ON#[63]

RSMRST#[22,77]

C81 180PF/50V

I

GND GND

SR138 10KOhmI1%

12

SCB75 10PF/50V

I

+3P3VA

12

I

O2CB13

0.1UF/6.3V

MLCC/+/-10%

GND

O2R4 10KOhmI

GND

O2R5 10KOhmI

O2R6 1K 1%Imx_r0402_small

O2R7 100PF/50V NPO 5%

NI

I

O2R10
330KOhm

O2R16
2KOhm

O2R17
33KOHM

1%

I

I

SCB67
10PF/50V

1 2

O2R1 43.2OHMI

PWROK[13,20,22]

1 2

1 2
1 2

1 2

1 2

12

NPO 5%

NOBOM
NOBOM
NOBOM
NOBOM

NOBOM
NOBOM
NOBOM
NOBOM

NOBOM

1%
1%

GND

NOBOM

O_YELLOW#[55]
O_GREEN#[55]

12

NI

SCB68
10PF/50V

S_PECI_REQ#[22]

PECI_READY

OT13

SIO_SUS3_ON#[70,71]

OT17
OT18
OT19
OT20

OT21
OT22
OT23
OT24

OT25

12

I

O2R9

8.2KOHM

GND

12

NI

SCB69
10PF/50V

SIO_PECI_R

1

GP035

C82 180PF/50V

I

V5_ALW_MON
SIO_SUSWARN

1

GP111

1

GP112

1

GP113

1

GP114

1

GP001

1

GP002

1

GP003

1

GP117

O_FP_CBL_DET#
O_AUD_PCSPKR_DET#

1

GP042

O_SPEAKER

3

GNDGNDGNDGND

12

NI

SCB70
10PF/50V

12

R636100KOHM 1% I

12

NPO 5%

SIO_TRST#

C85 4.7UF/6.3V

I

GND

REMOTE2+

REMOTE2-

3

+3P3V

12

I

O2CB8

0.1UF/6.3V

MLCC/+/-10%

GND

U17

21

CLK32

9

CLOCK1

10

LAD0

11

LAD1

12

LAD2

13

LAD3

14

LFRAME#

16

LRESET#

18

PCICLK

1

SER_IRQ

77

GP041/IO_PME#

128

(SLP_M#)GP071/IO_SMI#

72

GP036/SMB_CLK1

74

GP040/SMB_DAT1

27

SMBDAT2/GP010

28

SMBCLK2/GP011

22

(H_CPURST#)GP005/PECI_REQUEST#

31

PECI_VREF

32

PECI/LVSMB_CLK1

33

PECI_READY/LVSMB_DAT1

53

PCI_RST_1#/GP026

54

PCI_RST_2#/GP027

55

PS_ON#/GP030

59

PWR_GOOD_3V/GP033

60

RSMRST#

69

LATCHED_BF_CUT/GP035

125

PWRGD_PS

29

V3_S5

123

SLP_S3#

71

SLP_S4#

124

SLP_S5#/GP066

30

DPWROK/GP013

17

V5_ALW_MON

70

SUS_WARN#/GP004

73

SLP_SUS#

76

SUS3V_ON#/GP076

58

SUS3V_FON#/GP032

75

SUS5V_ON#/GP075

62

V3_DUAL1

63

GP111

64

GP112

65

GP113

66

GP114

67

V3_DUAL2

4

GP000

5

GP001

7

GP002

8

GP003

15

GP117

25

YELLOW#/GP006

26

GREEN#/GP007

35

(TMIN_SHIFT)GP014

36

PWRBTN#/GP015

52

(FP_CBL_DET#)GP025

56

(PC_SPKR_DET)GP031

78

GP042

126

TRST#

127

SPEAKER[DIAG_EN#]/GP070

SCH5555 I

12

CAP1

12

O2C1

I

2200PF/50V

X7R 10%

+3P3VA

6

VCC

I

O2CB1

0.1UF/6.3V

MLCC/+/-10%

+BATT

106

122

V3_DUAL324V3_DUAL434V3_DUAL557V3_DUAL679V3_DUAL7

V3_DUAL8

Each pin closely place
one Caps.

12

+3P3VA

23

VBAT

(THERM_THRESH)GP024/PWM3

PROCHOT_IN#/PROCHOT_OUT#/GP016

CAP12VSS13VSS219VSS337VSS461VSS568VSS692VSS7

119

GND GNDGND

3
C

B

1

E
2

12

I

O2CB3

O2CB2

0.1UF/6.3V

0.1UF/6.3V

MLCC/+/-10%

MLCC/+/-10%

12

12

I

O2CB9

0.1UF/6.3V

MLCC/+/-10%

GND

47

GND

SDAT_1/GP120

SDAT/GP121

HV3_DUAL

SCLK_1/GP122

SCLK/GP123

DDC_DAT_5V/GP100

DDC_DAT_2P5V/GP101

DDC_CLK_5V/GP102

DDC_CLK_2P5V/GP103

GP104
GP105
GP106
GP107

PCIAUX_CTRL#/GP124

PCIAUX_GATE/GP125

GP126

SUS_ACK_EN#/GP127

BACKFEED_CUT#/GP116

DCD1#/GP043
DSR1#/GP044

RXD1/GP045

RTS1#/GP046

(5V_PRSNT)GP047/TXD1

CTS1#/GP050
DTR1#/GP051

RI1#/GP052

GP053
GP054
GP055

(PWR2_PRSNT)GP056

(MB_REG_PG)GP057

GP060

(MEM_REG_PG)GP061

GP062

MCLK
MDAT

GP063/KBDRST#

GP064/A20M

TACH1/GP017
TACH2/GP020
TACH3/GP021

GP022/PWM1
GP023/PWM2

Remote1+

Remote1­Remote2a+/Remote2b­Remote2a-/Remote2b+

HVSS42AVSS

20

O2Q4

12

O2C2

PMBS3904

100PF/50V

I

NPO 5%

12

I

I

O2CB7

0.1UF/6.3V

MLCC/+/-10%

80
81
82
83
84
85
86
87
88
89
90
91
93
94
95
96
97

98
99
100
101
102
103
104
105

107
108
109
110
111
112
113
114

115

KCLK

116

KDAT

117
118
120
121

39
40
41

49
50
51

48

V_IN

43
44
45
46

38

NI

2

12

I

O2CB4

0.1UF/6.3V

0.1UF/6.3V

MLCC/+/-10%

MLCC/+/-10%

Pin102:PRE_POST
Diagnostics function as
+5V_PRESENT. (No used)

SIO_OUT_SMB_DATA_CORE
SIO_IN_SMB_DATA_RESUME
SIO_OUT_SMB_CLK_CORE
SIO_IN_SMB_CLK_RESUME

1

O_DCD1#_R

1

O_DSR1#_R

1

O_RTS1#_R

1

O_CTS1#_R

1

O_DTR1#_R

1

O_RI1#_R

1

GP053

1

GP054

1

GP055

1

GP060

1

GP062

1 2

I

3 4

I

5 6

I

7 8

I

V_IN

REMOTE2+
REMOTE2-

2

12

O2CB6

0.1UF/6.3V

MLCC/+/-10%

1
1
1
1

1 2
1 2

NOBOM
NOBOM

NOBOM
NOBOM

NOBOM
NOBOM

NOBOM
NOBOM
NOBOM

NOBOM
NOBOM

RN22A
RN22B
RN22C
RN22D

RST_KB# [20]
A20GATE [20]

O2R2 8.2KOHMI

REMOTE1+ [80]
REMOTE1- [80]

12

GND

I

GND

OT1
OT2
OT3
OT4

+3P3V

1%

+3P3VSB

1 2

NI

C83
47PF/50V

12

NOBOM
NOBOM
NOBOM
NOBOM

SMSC_GP124 [74]

+3P3VSB

CARD_DET# [28]

O_RTS2#_R
O_TXD2_R

O_DTR2#_R

+3P3V

12

I

R199

4.7KOHM

REMOTE1+

REMOTE1-

I

O2CB5

OR8 10KOhmI
OR9 10KOhmI1%

OT5
OT6

OT7
OT8

OT9
OT10

OT11
OT12
OT14

OT15
OT16

10KOHM
10KOHM
10KOHM
10KOHM

2
E

C
3

+3P3V

12

I

R46

4.7KOHM

GND

B

1 2

I

3 4

I

5 6

I

7 8

I

CPUFAN_TACH [47]
Supply_TACH [47]
GPUFAN_TACH [47]

CPUFAN_PWM [47]
Supply_PWM [47]

GPUFAN_PWM [47]

12

I_GPU

C84
100PF/50V

NPO/+/-5%

O2Q5
PMBS3904

I

12

1

SIO_RX0 [48,51]
SIO_TX0 [48,51]

+3P3V

RN18A

10KOHM

RN18B

10KOHM

RN18C

10KOHM

RN18D

10KOHM

O2C4

NI

100PF/50V

NPO 5%

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Size Project Name

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A2

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A2

Date: Sheet of

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IPPLP-TH

IPPLP-TH

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1

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

SIO SMSC5555

SIO SMSC5555

SIO SMSC5555

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

44 97Friday, January 17, 2014

44 97Friday, January 17, 2014

44 97Friday, January 17, 2014

Rev

Rev

Rev

A00

A00

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D D

C C

4

3

2

1

B B

A A

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XXXXXXX

Shrek_Tseng

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Shrek_Tseng

45 97Friday, January 17, 2014

45 97Friday, January 17, 2014

45 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

Vinafix.com

5

D D

NOBOM

H13
C315D157N

1

NP_NC

2

GND1

3

GND2

4

GND3

NOBOM

H14
C315D157N

1

NP_NC

2

GND1

3

GND2

4

GND3

GND8
GND7
GND6
GND5
GND4

GND8
GND7
GND6
GND5
GND4

9
8
7
6
5

9
8
7
6
5

1
2
3
4

GND GND

1
2
3
4

NOBOM

H3
C315D157N

NP_NC
GND1
GND2
GND3

NOBOM

H7
C315D157N

NP_NC
GND1
GND2
GND3

GND8
GND7
GND6
GND5
GND4

GND8
GND7
GND6
GND5
GND4

4

NOBOM

H4
C315D157N

9
8
7
6
5

9
8
7
6
5

1

NP_NC

2

GND1

3

GND2

4

GND3

GNDGND GND

NOBOM

H8
C315D157N

1

NP_NC

2

GND1

3

GND2

4

GND3

GND8
GND7
GND6
GND5
GND4

GND8
GND7
GND6
GND5
GND4

9
8
7
6
5

9
8
7
6
5

3

NOBOM

H5
C315D157N

1

NP_NC

GND8

2

GND1

GND7

3

GND2

GND6

4

GND3

GND5
GND4

GND

GND GND

NOBOM

H9
C315D157N

1

NP_NC

2

GND1

3

GND2

4

GND3

GND8
GND7
GND6
GND5
GND4

2

NOBOM

H6
C315D157N

9
8
7
6
5

9
8
7
6
5

1

NP_NC

2

GND1

3

GND2

4

GND3

GND GND

NOBOM

H10
C315D157N

1

NP_NC

2

GND1

3

GND2

4

GND3

GND8
GND7
GND6
GND5
GND4

GND8
GND7
GND6
GND5
GND4

9
8
7
6
5

9
8
7
6
5

1

C C

B B

A A

GND GND

GPU SHOLE

1

C126D126N

1

C126D126N

1

C126D126N

1

C126D126N

GND GND

H24

NOBOM

H25

NOBOM

H26

NOBOM

H27

NOBOM

GND GND

NOBOM

H12
C315D157N

1

NP_NC

2

GND1

3

GND2

4

GND3

GND GND

H28

1

C224D224N

H29

1

C224D224N

H30

1

C252D252N

H31

1

C224D224N

GND8
GND7
GND6
GND5
GND4

NOBOM

NOBOM

NOBOM

9
8
7
6
5

GND GND

GND GND

GND GND

NOBOM

H11
C315D157N

1

NP_NC

2

GND1

3

GND2

4

GND3

GND8
GND7
GND6
GND5
GND4

9
8
7
6
5

<Core Design>

<Core Design>

<Core Design>

PEGATRON DT-MB RESTRICTED SECRET

Title :

Title :

Title :

SCREW HOLE

SCREW HOLE

SCREW HOLE

Shrek_Tseng

Shrek_Tseng

1

Shrek_Tseng

46 97Friday, January 17, 2014

46 97Friday, January 17, 2014

46 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

IPPLP-TH

IPPLP-TH

IPPLP-TH

Engineer:

Vinafix.com

5

CPU FAN CONNECTOR

D D

CPUFAN_PWM[44]

CPUFAN_TACH[44]

+3P3V

I

FR1

4.7KOHM

1%

FR3 1.2KOhmI

4

FD1

BAT54CW

+3P3V

I

2

+3P3V

12

FR2

12

I
5%

150 OHM

12

1 2

I

R62

4.7KOHM

3

1

CPUFAN_PWM_C

CPUFAN_TACH_C

3

Critical

P70

1

1

2

2

3

3

4

4

5

NC

WAFER_HD_4P

FCB1

100PF/50V

12

I

100PF/50V

FCB2

12

I

2

+12V_HDD

12

I

CB171
10UF/25V

X5R 10%
mx_c0805

GND

GND

1

+12V_HDD

3

S

I_GPU

Q20
APM3095PUC

D

2

PROTO

Q22

WtoB_CON_1X3P

APM3095PUC

HOLD1

HOLD2

I

GND

45

P77

1
2
3

12

WAFER_HD_3P

4

NC

SENSE

+12V

GND

P41

I_GPU

12

I_GPU

CB172
10UF/25V

X5R 10%
mx_c0805

GND

SPLFAN_PWR

PROTO

CE860
10UF/6.3V

X5R/+/-20%

1
2

GPUFAN_PWR

3

GPUFAN_TACH_D

SPLFAN_TACH_D

GND

12

12

I_GPU

CB164

0.1UF/16V

GND

+5V

PROTO

CB167

0.1UF/6.3V

12

12

GND

GND

12

GND

I

R188

4.7KOHM

PROTO

CB17

0.1UF/16V

I_GPU

CB165
10PF/50V

NPO/+/-5%

D8

1
2

BAT54AW

I

D510

1
2

BAT54AW

I_GPU

3

3

GPUFAN_TACH [44]

Supply_TACH [44]

GND

I

U18

LM358

A+

3
2
5
6

12

VCC

+

A-

-

B+

+

B-

-

GND

I_GPU

C941288
1000PF/50V

X7R 10%

12

8
1

AO

BO

12

SPLFAN_G

7
4

GND

1 2

GPU FAN CONNECTOR

+3P3V

C C

GPUFAN_PWM[44]

B B

+3P3V

12

Supply_PWM[44]

A A

PROTO

R179

4.7KOHM

12

I_GPU

R60214

4.7KOHM

1 2

1 2

PROTO

R143
100KOHM

I_GPU

R136
100KOHM

12

PROTO

CB108

2.2UF/6.3V

X5R 10%

GND

12

CB107

2.2UF/6.3V

X5R 10%

GND

I_GPU

SPLFAN_VB+
SPLFAN_VB-

GND

SPLFAN_VB-

12

PROTO

R60373
10KOhm

1%

MXMFAN_VB+

12

I_GPU

R139
10KOhm

1%

MXMFAN_VB-

I_GPU

R135
30K

1%

PROTO

CB109
1000PF/50V

X7R 10%

SPLFAN_VB+

+12V_HDD

12

GND

MXMFAN_G

SPLFAN_G

R14430K1% PROTO

I

CB83

0.1UF/16V

+12V_HDD

12

+12V_HDD

12

PROTO

R60392

4.7KOHM

I_GPU

R60216

4.7KOHM

+12V_HDD

3

1

G

2

1

G

S

D

PEGATRON DT-MB RESTRICTED SECRET

GND

POWER SUPPLY FAN CONNECTOR

5

4

GND

3

GND

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

IPPLP-TH

IPPLP-TH

IPPLP-TH

Engineer:

Title :

Title :

Title :

1

FAN CIRCUIT

FAN CIRCUIT

FAN CIRCUIT

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

47 97Friday, January 17, 2014

47 97Friday, January 17, 2014

47 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Vinafix.com

5

D D

1 2

C336 10UF/6.3VPROTO

U9421

1
2

1 2

C333 10UF/6.3VPROTO

1 2

C334 10UF/6.3VPROTO

12

C C

PROTO

C335

10UF/6.3V

GND

3
4
5
6
7

PROTO

C1+

VCC

V+

GND

C1-

T1OUT

C2+

R1IN

C2-

R1OUT

V-

T1IN

T2OUT

T2IN

R2IN8R2OUT

MAX3232ECAE

4

+5V

12

PROTO

16
15
14
13
12
11
10
9

C337

0.1UF/6.3V

MLCC/+/-10%

S1R43 0

NI

S1R44 0

NI

GND

1 2
1 2

3

SIO_RX0 [44,51]
SIO_TX0 [44,51]

1
2

J193

HEADER_1X2P

PROTO

2

1

B B

A A

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Title :

Engineer:

Engineer:

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Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

1

COM PORT

COM PORT

COM PORT

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

48 97Friday, January 17, 2014

48 97Friday, January 17, 2014

48 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Vinafix.com

5

4

3

2

1

+5VA : GREEN
+5VSB : GREEN

+3P3VA

D D

NI

R79

2.2KOHM

CATERR#[11]

C C

1 2

+3P3V

12

NI

R72
300 Ohm

mx_r0603

HIERR#_G

3

C

B

1

NI

Q9

E

PMBS3904

2

12

NI

+

CR4
RED

SMD

GNDGND

12

NI

R73
300 Ohm

mx_r0603

12

+

CR5
GREEN

NI

GND GND

+5VA

GND

12

12

+

NI

R74
300 Ohm

mx_r0603

CR22
GREEN

NI

+5VSB

12

12

+

NI

R75
300 Ohm

mx_r0603

CR1
GREEN

NI

+3P3VSB

12

12

+

GND

NI

R76
300 Ohm

mx_r0603

CR2
GREEN

NI

+5V +3P3V

GND

12

12

+

NI

R77
300 Ohm

mx_r0603

CR6
GREEN

NI

12

12

GND

NI

R78
300 Ohm

mx_r0603

+

CR7
GREEN

NI

B B

A A

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Title :

Title :

Title :

Engineer:

Engineer:

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Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

1

DEBUG LED

DEBUG LED

DEBUG LED

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

49 97Friday, January 17, 2014

49 97Friday, January 17, 2014

49 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Vinafix.com

5

4

3

2

1

Debug Card CON

+3P3V

13

SIDE214SIDE1

2
4
6
8
10
12

SIDE416SIDE3

ZIF_CON_12P

15

P12

1

1

3

3

5

5

7

7

9

9

11

11

GND

D D

LAD0[22,44,50,62]
LAD1[22,44,50,62]
LAD2[22,44,50,62]
LAD3[22,44,50,62]

LFRAME#[22,44,50,62]

CK_33M_LPC[21,50]

C C

2
4
6

8
10
12

I

CK_33M_LPC[21,50]

PLTRST#[20,31,44,62]

LAD0[22,44,50,62]
LAD1[22,44,50,62]
LAD2[22,44,50,62]
LAD3[22,44,50,62]

LFRAME#[22,44,50,62]

OBSDATA_C1[20,77]

CON3

1

2

3

4

5

6

7

8

9

10

11

12

13

14

BOX_HEAD_2X7P

15

PROTO

F_LPC_DEBUG

0 Ohm

NI

1 2

APR1

1 2

APR2
0 Ohm

NI

+5V

12

GNDGND

O2R18

8.2KOHM

1%NI

NI

Ic=200mA/150mW

MBT3904DW1T1G

O2Q7

12

GND

F_LPC_DEBUG

NI

CB20

0.1UF/16V

34

C2

AR25
1KOhm

NI

12

GND GND

O2Q3_AR35

1

2

E1E2B1

C1

B2

5

6

I

APR3
10KOhm

1%

GND

8.2KOHM

12

O2R19

12

AR24
1KOhm

NI

1%NI

I

APR4
10KOhm

1%

F_LPC_DEBUG

+3P3V

K_GNT#1 [20]

APS

B B

+3P3VSB+3P3VSB+3P3VA

PROTO

P466

1

2
4
6
8
10
12
14

HEADER_2X7P

SLP_S3#_APS

GND

3

1 2

APR6 0 Ohm

SLP_S4#[22,44,68,72]
RTCRST#[22]

PWRBTN#[22,44,55,76,77]

SYS_RESET#[11,22,76,77]

A A

5

PROTO

1 2

APR8 0 Ohm

PROTO

1 2

APR10 0 Ohm

PROTO

1 2

APR9 0 Ohm

PROTO

SLP_S4#_APS SLP_A#_APS
RTCRST#_APS

PWRBTN#_APS
SYS_RESET#_APS

5
7

9
11
13

4

PROTO
PROTO

1 2

APR5 0 Ohm

1 2

APR7 0 Ohm

SLP_S3# [22,44,67,72,74]
SLP_A# [22,44,68,91]

3

PEGATRON DT-MB RESTRICTED SECRET

Title :

Title :

Title :

APS/LPC DEBUG

APS/LPC DEBUG

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

APS/LPC DEBUG

1

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

50 97Friday, January 17, 2014

50 97Friday, January 17, 2014

50 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Vinafix.com

5

3

I

+3P3V

D D

S1L1
30 Ohm/100Mhz

mx_l0603

21

+1P22V

12

S1C15
10UF/6.3V

GND GND GND

I

S1L2
30Ohm/100Mhz

mx_l0603

21

*ALLRESISTORAREMX_R0402_SMALLFOOTPRINT

+3P3V

1 2

PR4 0Ohm 5%NOBOM

+3P3V

1 2

C C

+1P22V

I

S1L5

+3P3V

30Ohm/100Mhz

mx_l0603

21

12

I

S1C25
10UF/6.3V

B B

S1C35 can NI if power noise test pass

FromExternal
HDMIIn

DDPC_HPD_HDMI[21]
DDPC_CTRL_CLK[21,52]
DDPC_CTRL_DATA[21,52]

FromPCH

FromInternal
CPUHDMIIn

A A

5

PRE_OS_BIST#[22]
EPSA_BIST#[19]

HDMIC_TMDSC_DATA0#[10]
HDMIC_TMDSC_DATA0[10]
HDMIC_TMDSC_DATA1#[10]
HDMIC_TMDSC_DATA1[10]
HDMIC_TMDSC_DATA2#[10]
HDMIC_TMDSC_DATA2[10]
HDMIC_TMDSC_CLK#[10]
HDMIC_TMDSC_CLK[10]

HDMI_LS_CLK[52]
HDMI_LS_CLK#[52]
HDMI_LS_D2[52]
HDMI_LS_D2#[52]
HDMI_LS_D1[52]
HDMI_LS_D1#[52]
HDMI_LS_D0[52]
HDMI_LS_D0#[52]

PR301 0Ohm 5%NOBOM

I

S1L4
30Ohm/100Mhz

mx_l0603

2 1

12

NI

S1C26

0.1UF/16V

X7R/+/-10%

12

S1C22
10UF/6.3V

GND GND GND

12

NI

S1C27

0.1UF/16V

X7R/+/-10%

HDMI_IN_HPD[56]
HDMI_IN_DDC_CLK[56]
HDMI_IN_DDC_DATA[56]
HDMI_IN_TX0N[56]
HDMI_IN_TX0P[56]
HDMI_IN_TX1N[56]
HDMI_IN_TX1P[56]
HDMI_IN_TX2N[56]
HDMI_IN_TX2P[56]
HDMI_IN_CLKN[56]
HDMI_IN_CLKP[56]

1 2
3 4
5 6
7 8

GND

1 2

S1C39 0.1UF/6.3V

I

1 2

S1C40 0.1UF/6.3V

I

1 2

S1C41 0.1UF/6.3V

I

1 2

S1C42 0.1UF/6.3V

I

1 2

S1C43 0.1UF/6.3V

I

1 2

S1C44 0.1UF/6.3V

I

1 2

S1C45 0.1UF/6.3V

I

1 2

S1C46 0.1UF/6.3V

I

I

GND GND

NOBOM
NOBOM

GND GND

I

100Ohm
100Ohm
100Ohm
100Ohm

MLCC/+/-10%

4

ClosetoScalar

12

0.1UF/6.3V

MLCC/+/-10%

12

NI

S1C13
10UF/6.3V

X5R 10%
mx_c0805_small

ST609
ST610

12

I

S1C18
10UF/6.3V

12

I

S1C20
10UF/6.3V

12

S1C23

0.1UF/6.3V

MLCC/+/-10%

12

S1C28

0.1UF/6.3V

MLCC/+/-10%

RN23A
RN23B
RN23C
RN23D

4

I

S1C11

I

I

5%I
5%I
5%I
5%I

12

I

S1C12

0.1UF/6.3V

MLCC/+/-10%

SADC_1P2V

12

I

S1C14

0.1UF/6.3V

MLCC/+/-10%

1
1

12

I

S1C19

0.1UF/6.3V

MLCC/+/-10%

GNDGND

12

I

S1C21

0.1UF/6.3V

MLCC/+/-10%

12

I

S1C24

0.1UF/6.3V

MLCC/+/-10%

12

I

S1C29

0.1UF/6.3V

MLCC/+/-10%

GNDGNDGNDGNDGND

S_DDPC_CTRL_CLK
S_DDPC_CTRL_DATA
S_BIOS_Corruption
S_BIST_ON

S_BIST_ON

12

S1C640.1UF/6.3V

NI

SAVDD_33

GND

SAVDD_AU

SAVDD_EAR

SVDDC_1P2V

SVDDP_3P3V

I

S1U1

9

AVDD_33_1

24

AVDD_33_2

23

GND1

34

GND2

44

GND3

55

GND4

66

GND5

78

GND6

112

GND7

129

GND8

96

GND_BST

18

AVDDL_DVI

25

BIN0M

26

BIN0P

27

GIN0M

28

GIN0P

29

SOGIN0

30

RIN0M

31

RIN0P

32

HSYNC0

33

VSYNC0

38

LINE_IN_L/AUMUTE/GPIO_AU0

39

LINE_IN_R/AUSCK/GPIO_AU1

37

AVDD_AUSDM

47

AVDD_EAR

54

VDDC1

109

VDDC2

56

VDDP1

77

VDDP2

98

VDDP3

111

VDDP4

126

GPIO31

127

DDCD_CK/RS232_RX1/GPIO32

128

DDCD_DA/RS232_TX1/GPIO33

3

RXA0N

4

RXA0P

5

RXA1N

6

RXA1P

7

RXA2N

8

RXA2P

1

RXACN

2

RXACP

21

GPIO36

19

DDCDB_CK/GPIO34

20

DDCDB_DA/GPIO35

123

GPIO26

114

GPIO20

12

RXB0N

13

RXB0P

14

RXB1N

15

RXB1P

16

RXB2N

17

RXB2P

10

RXBCN

11

RXBCP

89

NC1

90

NC2

91

NC3

92

NC4

93

NC5

94

NC6

95

NC7

97

NC8

99

NC9

100

NC10

TSUMU88BDC2-1

3

AUVAG/AUMCK/GPIO_AU4

AUVRM/SPDIFO/GPIO_AU5

LINE_OUT_R/AUWS/GPIO_AU3

LINE_OUT_L/AUSD/GPIO_AU2

EAR_OUT_L

EAR_OUT_R

NC19
NC18
NC17
NC16
NC15
NC14

RESET

NC13
NC12
NC11

SAR2/GPIO_SAR2
SAR1/GPIO_SAR1

GPIO25

CEC/GPIO27

GPIO21

GPIO37

GPIO30

GPIO00
SAR0/GPIO_SAR0
SAR3/GPIO_SAR3

GPIO24/PWM6

HOLDZ/GPIO11

GPIO22/PWM4
GPIO23/PWM5
GPIO02/PWM1

GPIO01/PWM0/SPDIFO

DDCA_CK/RS232_RX0/GPIO40
DDCA_DA/RS232_TX0/GPIO41

GPIO03

MIIC_SCL/GPIO04

MIIC_SDA/GPIO05

WPZ/GPIO10

SCK
SDO

CSZ

LVB0P

LVB0M

LVB1P

LVB1M

LVB2P

LVB2M

LVBCKP

LVBCKM

LVB3P

LVB3M

LVA0P

LVA0M

LVA1P

LVA1M

LVA2P

LVA2M

LVACKP

LVACKM

LVA3P

LVA3M

XOUT

3

42

43
41

40
46

45
110

108
107
106
105
104

50
103

102
101

117
116
122
124
113

22

125
51
115
118
121

65
119
120
53
52

35
36

57
58
59

64
63
62

SDI

61
60

88
87
86
85
84
83
82
81
80
79
76
75
74
73
72
71
70
69
68
67

48

49

XIN

1

ST612

SPDIF_OUT_C

1

S1T1

1

S1T3

1

S1T4

1

+5V

12

12

S1C17

0.1UF/6.3V

MLCC/+/-10%

S_OSD_UP
S_Mode_button#
S_OSD_DOWN#
BRIGHTNESS_DISABLE#_R
VOLUME_DISABLE#_R

TRIGGER_PIN_R
DATA0_R
DATA1_R
DATA2_R

Pansel_SEL_1_R
S_PANEL_BIST_ON
S_SCL_LCDEN
SCL_BL_PWM_R
SCL_BL_EN_R

DDCA_SCL
DDCA_SDA

X-OUT

X-IN

GND GNDGND

S1T2

I

S1C16
10UF/6.3V

12

I

GNDGND

S1R53 4.7KOHM

I1%

S1R8 4.7K

NI

S1R9 4.7KOHM

I

S1R42 100 Ohm 1%I

3 4
5 6
7 8
1 2

S1R54 100 Ohm

I

S1R18 100 Ohm 1%I
S1R20 4.7KOHM

I

S1R21 0

I

S1R22 0

I

S1R23 0

I

S1R24 0

I

S1R30 0Ohm 5%NOBOM

1 3

12

I

S1C30
18PF/50V

NPO 5%

NOBOM

AC35 0.1UF/6.3V MLCC/+/-10%I

NOBOM
NOBOM

NOBOM
NOBOM

I

S1R1
10KOhm

1%

1 2
1 2

1 2

1 2

100Ohm
100Ohm
100Ohm
100Ohm

1 2

3 4

100Ohm

5 6

100Ohm

7 8

100Ohm

1 2
1 2

1 2
1 2

1 2
1 2

1 2

2

4

2

1 2

I
I
I

NI

1 2

100Ohm

3 4

100Ohm

5 6

100Ohm

7 8

100Ohm

1 2

100Ohm

1%

RN25B

5%I

RN25C

5%I

DATA1_RR

RN25D

5%I

RN26A

5%I

1%

Pansel_SEL_1_RR

RN26B

5%I

RN26C

5%I

RN26D

5%I

1%

EEPROM_WP [52]
DDPCTL_CLK [52]
DDPCTL_DAT [52]

SL_WP_N [52]
SL_CLK [52]
SL_SDIN [52]
SL_SDOUT [52]
SL_CS_N [52]

LVDS_U0P_NB [53]
LVDS_U0N_NB [53]
LVDS_U1P_NB [53]
LVDS_U1N_NB [53]
LVDS_U2P_NB [53]
LVDS_U2N_NB [53]
LVDS_UCLKP_NB [53]
LVDS_UCLKN_NB [53]
LVDS_U3P_NB [53]
LVDS_U3N_NB [53]
LVDS_L0P_NB [53]
LVDS_L0N_NB [53]
LVDS_L1P_NB [53]
LVDS_L1N_NB [53]
LVDS_L2P_NB [53]
LVDS_L2N_NB [53]
LVDS_LCLKP_NB [53]
LVDS_LCLKN_NB [53]
LVDS_L3P_NB [53]
LVDS_L3N_NB [53]

I

Y4

14.318MHZ

2

RN24A
RN24B
RN24C
RN24D
RN25A

12

S_OSD_UP
S_Mode_button#
S_OSD_DOWN#

12

S1R504.7K

12

S1R494.7K

12

S1R484.7K

12

S1R514.7K

5%I

OSD_UP [55]

5%I

Mode_button# [22,55]

5%I

OSD_DOWN# [55]

5%I

BRIGHTNESS_DISABLE# [22]

5%I

+3P3V

DDPC_WP# [52,56]

GND

APR520 Ohm

I

1 2

APR530 Ohm

I

1 2

GND

SIO_TX0 [44,48]
SIO_RX0 [44,48]

SCL_FW_CLK [21,52]
SCL_FW_DATA [20,52]

ToScalarEEPROM

ToScalarSPIROM

ToLVDSCONN.

I

S1C31
18PF/50V

NPO 5%

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

SPDIF_OUT [40]

1 2

CB168 0.1UF/6.3V MLCC/+/-10% I

1 2

CB169 0.1UF/6.3V MLCC/+/-10% I

1 2

CB170 0.1UF/6.3V MLCC/+/-10% I

+3P3V

VOLUME_DISABLE#[22]

PQ9510

NI

2N7002

3 2

D

3

1

1

G

GND

S

GND

2

FromLVDS&DualCONN.

DATA3 [22]
TRIGGER_PIN# [20]
DATA0 [20]
DATA1 [20,51]
DATA2 [21]

Pansel_SEL_1 [51,53]
PANEL_BIST_ON [53]
SCL_LCDEN [54]
SCL_BL_PWM [53]
SCL_BL_EN [53]

ToPCH

DATA1_RR

ToLVDS&DualCONN.

Pansel_SEL_1_RR

APR500 Ohm

NI

1 2

APR510 Ohm

NI

12

Pansel_SEL_1 [51,5

DATA1 [20,51]

ToSIO

ToScalarDebug

PEGATRON DT-MB RESTRICTED SECRET

SCALAR_TSUMU88BDC2 - 1

SCALAR_TSUMU88BDC2 - 1

SCALAR_TSUMU88BDC2 - 1

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

1

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

51 97Friday, January 17, 2014

51 97Friday, January 17, 2014

51 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Vinafix.com

5

4

3

2

1

SCALARSPIROM SCALARHDMILEVELSHIFT(CostReduce)

CostReducedLevelShifterMotherboardTopologyformaxdatarateof1.65Gb/s
ActiveLevelShifterMotherboardTopologyformaxdatarateof2.97Gb/s

5% I

HDMI_LS_D2#[51]
HDMI_LS_D2[51]
HDMI_LS_D1#[51]
HDMI_LS_D1[51]
HDMI_LS_D0#[51]
HDMI_LS_D0[51]
HDMI_LS_CLK#[51]
HDMI_LS_CLK[51]

3 4

5% I

1 2

5% I

7 8

5% I

5 6

5% I

3 4

5% I

1 2

5% I

7 8

5% I

5 6

680OHM
680OHM
680OHM
680OHM
680OHM
680OHM
680OHM
680OHM

RN29B
RN29A
RN29D
RN29C
RN30B
RN30A
RN30D
RN30C

+3P3V

12

I

32

3

I

D

AQ4
2N7002

1

1

HDMI_Pull_down

G

S

2

R623

4.7KOHM

1%

12

C628

0.1UF/16V

X7R 10%
NI

S1R32

8.2KOHM

1%
I

+3P3V

12

GND

4Mbit

I

S1U2
SST SPI 4Mb

8
7
6
5

I

S1C32

0.1UF/6.3V

MLCC/+/-10%

VCC
HOLD#
CLK
DIO

CS#

WP#
GND

1
2

DO

3
4

GND

GND

12

S1R33

100KOHM

I
1%

SL_CS_N [51]
SL_SDOUT [51]

SL_WP_N [51]

+3P3V

12

D D

SL_CLK[51]
SL_SDIN[51]

SCALAREEPROM

+3P3V

+3P3V+3P3V

C C

EEPROM_WP[51]
DDPCTL_CLK[51]
DDPCTL_DAT[51]

S1R37 100 Ohm 1%I
S1R38 100 Ohm 1%I

1 2
1 2

12

I

S1R34

3.3KOHM

1%

12

I

S1R35

3.3KOHM

1%

12

I

S1R36

3.3KOHM

1%

I2C_MCL

I2C_MDA

+3P3V

12

GND

16Kbit

I

S1U3
EEPROM 16Kb

8

VCC

7

WP

6

SCL

5

SDA

I

S1C33

0.1UF/6.3V

MLCC/+/-10%

GND

1

A0

2

A1

3

A2

4

GND

B B

A A

OSDPowerButtonwakeupfromScreenoff

SCALARDEBUGPORT

PROTO

S1J1
WtoB_CON_1X3P

5

SIDE2

SCL_FW_DATA[20,51]
SCL_FW_CLK[21,51]

5

3

3

2

2

1

1

4

SIDE1

GND

4

INTELDISPLAYEDID

DDPC_CTRL_CLK[21,51]

DDPC_CTRL_DATA[21,51]

DDPC_WP#[51,56]

3

+3P3V

I

MR1

2.2KOHM

1%

2

12

I

MR2

2.2KOHM

1%

B

1

GND

3

C

I

MQ1
PMBS3904

E
2

12

1 2

MR5 4.7KOHM

I1%

+3P3V+3P3V

GND

12

12

MR3

100KOHM

I
1%

MR4

100KOHM

NI
1%

+3P3V

GND

12

0.1UF/6.3V

MLCC/+/-10%

2Kbit

I

MU1
EEPROM 2Kb

8

VCC

7

WP

6

SCL

5

SDA

I

MC1

GND

1

A0

2

A1

3

A2

4

GND

PEGATRON DT-MB RESTRICTED SECRET

SCALAR_TSUMU88BDC2 - 2

SCALAR_TSUMU88BDC2 - 2

SCALAR_TSUMU88BDC2 - 2

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

IPPLP-TH

IPPLP-TH

IPPLP-TH

Engineer:

1

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

52

52

52

Rev

Rev

Rev

A00

A00

A00

97Friday, January 17, 2014

97Friday, January 17, 2014

97Friday, January 17, 2014

Vinafix.com

5

O

O

O

4

3

GND

2

1

P172

D D

C C

LVDS_L0N_NB[51]

LVDS_L0P_NB[51]

LVDS_CBL_DET_PIN14#[19] LVDS_CBL_DET_PIN24# [22]

LVDS_L1N_NB[51]

LVDS_L1P_NB[51]
LVDS_L2N_NB[51]

LVDS_L2P_NB[51]

PANEL_BIST_ON[51]

LVDS_LCLKN_NB[51]

LVDS_LCLKP_NB[51]

LVDS_L3N_NB[51]
LVDS_L3P_NB[51]

GND

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

WTOB_CON_30P

SIDE2

SIDE1

32
2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

31

0.1UF/6.3V

MLCC/+/-10%

GND

12

I

CB22

GND GND

CB21

10PF/50V

12

I

LVDS_U0N_NB [51]
LVDS_U0P_NB [51]

LVDS_U1N_NB [51]
LVDS_U1P_NB [51]

LVDS_U2N_NB [51]
LVDS_U2P_NB [51]

LVDS_UCLKN_NB [51]
LVDS_UCLKP_NB [51]

LVDS_U3N_NB [51]
LVDS_U3P_NB [51]

+5V_LCD

CONVERTER CONN.

+12V_HDD

Inverter Conn.

I

12

INV_CON1_12V

12

I

C98

0.1UF/6.3V

MLCC/+/-10%

C970.1UF/16V

GND

B B

SCL_BL_EN[51]

SCL_BL_PWM[51]

A A

5

GND

X7R 10%

12

C99
15PF/50V

MLCC/+/-5%
NI

GND

4

GND

F1
4A/32V

1 2

J109

1
2

I

3
5

6
7
8
9410

WAFER_HD_1X9P

I

C100

1 2

NI
I

GND

0.1UF/6.3V

MLCC/+/-10%
I

1 2

APR49 0 Ohm

1 2

APR48 0 Ohm

converter_CBL_DET# [20]

Alarm_open# [22,55]
Pansel_SEL_1 [51]

INTRUD_CBL_DET# [22,55]

PEGATRON DT-MB RESTRICTED SECRET

Title :

Title :

Title :

LVDS & CONVERTER C

LVDS & CONVERTER C

LVDS & CONVERTER C

Shrek_Tseng

Shrek_Tseng

1

Shrek_Tseng

53 97Friday, January 17, 2014

53 97Friday, January 17, 2014

53 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

3

2

Date: Sheet of

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

Vinafix.com

5

D D

4

3

2

1

PANEL Controllor

+12V_HDD

+5V +5V_LCD

R81
1K

1%

mx_r0402_small

1 2

I

12

GND

1

1

G

NI

C96

0.1UF/16V

12

32

3

D

2

C C

R85

8.2KOHM

1%

1 2

I

SCL_LCDEN[51]

B B

GND

CHECK PANEL SPEC

Q10
30mOhm/10V SOT-23

3 2

S

D

3

Critical

1 2

R82 10KOhmI1%

S

I

R83
10KOhm

1%

Q12
2N7002

I

1

PMBS3904

I

R84

1 2

3

Q11

10 Ohm

C

5%

B

I

E
2

GNDGND GND

2

G

1

1

12

I

C95
1UF/16V

X7R 10%
mx_c0603_small

A A

PEGATRON DT-MB RESTRICTED SECRET

SCALAR LCD ENABLE

SCALAR LCD ENABLE

1

SCALAR LCD ENABLE

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

A00

A00

54 97Friday, January 17, 2014

54 97Friday, January 17, 2014

54 97Friday, January 17, 2014

A00

Rev

Rev

Rev

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

Vinafix.com

5

4

3

2

1

GND

D D

OSD_UP[51]
OSD_DOWN#[51]

12

D512
AZ2025-01H

I

Mode_button#[22,51]

HR71
680Ohm

1%

I

+3P3V

1 2

+3P3V

12

12

sideBrd_CLB_DET#[20]

R61
75 OHM

I

D513
AZ2025-01H

I

PWRBTN#[22,44,50,76,77]

D19

GND

AZ2025-01H

I

HD_LED_IN#[20]

C C

HD_LED_IN# HDD_LED+ PWR_LED- PWR_LED+

12

1 2

NPO 5%

I

HDD_LED+

0.1UF/6.3V

C90
100PF/50V

PWR_LED+
PWR_LED-

I

C91

MLCC/+/-10%

GND

12

D514
AZ2025-01H

I

J213

12

SIDE2

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

12

12

I

CB9

0.1UF/6.3V

MLCC/+/-10%

GND GND GND

12

12

D515
AZ2025-01H

I

I

CB10

0.1UF/6.3V

MLCC/+/-10%

12

I

CB11

0.1UF/6.3V

MLCC/+/-10%

WTOB_CON_10P

GND

11

SIDE1

I

2011/6/9

GND

修改

PWR_LED-

PWR_LED+

Q9428

2N7002

Q9429

2N7002

+3P3VSB

I

+3P3VSB

12

32

D

S

I

S

GND

3

2

12

32

D

I

R55

49.9 OHM

1%

3

1

G

2

I

R59

49.9 OHM

1%

1

1

G

1

Q4

2N7002

Q5

2N7002

+3P3VSB

D

S

I

GND

+3P3VSB

D

S

I

12

32

3

2

12

32

3

2

I

R60393
10KOhm

1%

1

1

G

I

R60394
10KOhm

1%

1

1

G

+3P3VSB

12

+3P3VSB

12

I

R56
10KOhm

1%

I

R60
10KOhm

1%

O_YELLOW# [44]

O_GREEN# [44]

B B

A A

GND GND GND GND

Alarm_open#[22,53]

INTRUD_CBL_DET#[22,53]

12

GND

NI

C92

0.1UF/6.3V

MLCC/+/-10%

GND

3
2
1

4 5

HOLD2

P305
WtoB_CON_1X3P

NI

HOLD1

Lanikai
Only

GND

GND

PEGATRON DT-MB RESTRICTED SECRET

Title :

Title :

Title :

FRONT PANEL

FRONT PANEL

1

FRONT PANEL

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

55 97Friday, January 17, 2014

55 97Friday, January 17, 2014

55 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

Vinafix.com

5

34

HDMI_IN_TX2P[51]

HDMI_IN_TX2N[51]

D D

HDMI_IN_TX1P[51]

HDMI_IN_TX1N[51]

HDMI_IN_TX0P[51]

C C

HDMI_IN_TX0N[51]

HDMI_IN_CLKP[51]

HDMI_IN_CLKN[51]

B B

VP

MRN1B

VP

1 4

MRN1A

VP

MRN2B

VP

1 4

MRN2A

VP

MRN3B

VP

1 4

MRN3A

VP

MRN4B

VP

1 4

MRN4A

0

0

0

0

0

0

0

0

90OHM/100MHZ/330mA
ML1

NI

2 3

12

34

90OHM/100MHZ/330mA
ML2

NI

2 3

12

34

90OHM/100MHZ/330mA
ML3

NI

2 3

12

GND

34

90OHM/100MHZ/330mA
ML4

NI

2 3

12

EXTERNAL HDMI IN EDID

I

MU4

EEPROM 2Kb

1
2
3
4

GND

HDMI_IN_DDC_CLK[51]
HDMI_IN_DDC_DATA[51]

A A

DDPC_WP#[51,52]

I

MR13

4.7KOHM

1 2

5

+5V_EDID

12

I

MR12
10KOhm

1%

3

1%

C

B

1

I

MQ3

E

PMBS3904

2

GND

8

A0

VCC

7

A1

WP

6

A2

SCL

5

GND

SDA

2Kbit

+5V_EDID

12

GND

GND

CH1

CH2 CH3

I

MC2

0.1UF/6.3V

MLCC/+/-10%

4

NI

MU3
CM1213_04SO

1

VN

2
3 4

+5V_EDID

12

I

MR7

4.7KOHM

1%

4

NI

MU2
CM1213_04SO

CH1

1

VN

2

CH2 CH3

3 4

+5V_EDID

CH4

6
5

VP

12

MR8

4.7KOHM

CH4

6
5

I

1%

MR10 100 Ohm 1%I
MR9 100 Ohm 1%I

VP

1 2
1 2

+5VA

HDMI_IN_TX2P_R

HDMI_IN_TX2N_R

+5VA

HDMI_IN_TX1P_R

HDMI_IN_TX1N_R

HDMI_IN_TX0P_R

HDMI_IN_TX0N_R

+5V_HDMI_IN

12

+5VA

GND

1

2

GND
NI

MD3

3

BAV99W-L

3

12

I

CB31
10PF/50V

+5VA

HDMI_IN_DDC_CLK_R
HDMI_IN_DDC_DATA_R

2

1

3

BAV99W-L

GND

GND
NI

MD1

3

0.1UF/6.3V

MLCC/+/-10%

HDMI_IN_DDC_CLK_R
HDMI_IN_DDC_DATA_R

HDMI_IN_HPD_R

I

MCB2

HDMI_IN_TX2P_R
HDMI_IN_TX2N_R

HDMI_IN_TX1P_R
HDMI_IN_TX1N_R

HDMI_IN_TX0P_R
HDMI_IN_TX0N_R

HDMI_IN_CLKP_RHDMI_IN_CLKP_R
HDMI_IN_CLKN_RHDMI_IN_CLKN_R

HDMI_IN_HPD_R

J136

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

HDMI_CON_19P

I

BAV99W-L

P_GND2

P_GND3

P_GND1

D16

2

+5V

+5V_EDID

21

22

20

+5VA

2

NI

3

12

I

MCB1

0.1UF/6.3V

MLCC/+/-10%

GND

GNDGND

1

GND

+5V_HDMI_IN

12

mx_r0402_small

12

GND

I

MR6
1K1%

S1R39 100 Ohm 1%I
MR37

100KOHM

I
1%

1 2

2

3

I

1

+5V_HDMI_IN

1

D15
BAT54CW

HDMI_IN_HPD [51]

PEGATRON DT-MB RESTRICTED SECRET

HDMI IN

HDMI IN

HDMI IN

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

1

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

56 97Friday, January 17, 2014

56 97Friday, January 17, 2014

56 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Vinafix.com

5

D D

4

3

2

1

12
34
56
78

NI
NI
NI
NI

1 2
1 2

1 2
1 2
1 2
1 2

1 2
1 2

GNDGND

+3P3V

NI

I

GND

12

12

HR323

4.7KOHM

HPDINV

HR324

4.7KOHM

+3P3V

I

NI

GND

12

12

GND

GND

HR317

4.7KOHM

HR318

4.7KOHM

GND

+3P3V

HDMI_TXN2_C
HDMI_TXP2_C

HDMI_TXN1_C
HDMI_TXP1_C
HDMI_TXN0_C
HDMI_TXP0_C

HDMI_CLKN_C
HDMI_CLKP_C

12

SC1300.1UF/6.3V

12

SC1310.1UF/6.3V

HR315 4.7KOHM

I

GND

+3P3V

I

I

12

SC1320.1UF/6.3V

1 2

+3P3V

I

+3P3V

NI

NI

GND

12

12

HR320

4.7KOHM

OVS

HR321

4.7KOHM

MC33

GND

1

IN_D1-

2

IN_D1+

3

VCC3

4

IN_D2-

5

IN_D2+

6

IN_D3-

7

IN_D3+

8

VCC4

9

IN_D4-

10

IN_D4+

I

12

10PF/50V

NI

12

SC1370.1UF/6.3V

I

GND

OVS

DDC_EN

HPDINV

38

39

40

41

36

37

NC3

OVS

VCC7

GND1

HPDINV

DDC_EN

NC111VCC112SRC13I2C_EN14Vsadj15HPD_SOURCE16SDA_SOURCE17SCL_SOURCE18VCC219NC2

12

1%
I

GND

+3P3V

33

34

35

SDA_SINK

HPD_SINK

HR319

4.02KOHM

SC136 0.1UF/6.3V

I

GND

31

32

VCC8

OE_N

OUT_D1-

SCL_SINK

OUT_D1+

VCC5

OUT_D2-

OUT_D2+

OUT_D3-

OUT_D3+

VCC6

OUT_D4-

OUT_D4+

20

+3P3V

SC133 0.1UF/6.3V

I

1 2

U9418A
SN75DP139RSBR

30
29
28
27
26
25
24
23
22
21

1 2

GND

+3P3V

1 2

SC134 0.1UF/6.3V

I

1 2

SC135 0.1UF/6.3V

I

+3P3V

I

MR39

2.2KOHM

GND

1 2

HDMI_HOTPLUG_DET [58]

HDMI_CTRL_DATA_LS [58]

HDMI_CTRL_CLK_LS [58]

GND

GND

I

MR38

2.2KOHM

1 2

HDMI_CTRL_CLK [21]
HDMI_CTRL_DATA [21]

HDMI_DDPD_HPD [21]

HDMI_TXN2_LS_OUT [58]
HDMI_TXP2_LS_OUT [58]

HDMI_TXN1_LS_OUT [58]
HDMI_TXP1_LS_OUT [58]
HDMI_TXN0_LS_OUT [58]
HDMI_TXP0_LS_OUT [58]

HDMI_CLKN_LS_OUT [58]
HDMI_CLKP_LS_OUT [58]

+3P3V

12

HR316

4.7KOHM

DDC_EN

I

12

HR322

4.7KOHM

NI

C C

+3P3V +3P3V

7 8

NI

5 6

NI

3 4

NI

1 2

NI

HDMI_TXN2[10]
HDMI_TXP2[10]

HDMI_TXN1[10]
HDMI_TXP1[10]
HDMI_TXN0[10]
HDMI_TXP0[10]

HDMI_CLKN[10]
HDMI_CLKP[10]

B B

49.9OHM

49.9OHM

49.9OHM

49.9OHM

RN36D
RN36C
RN36B
RN36A

GND

RN37A

RN37B
RN37C
RN37D

U9418B

42

GND2

43

GND3

44

GND4

45

GND5

46

GND6

SN75DP139RSBR

I

GND7
GND8
GND9

49.9OHM

49.9OHM

49.9OHM

49.9OHM

MC26 0.1UF/6.3V

I

MC25 0.1UF/6.3V

I

MC28 0.1UF/6.3V

I

MC27 0.1UF/6.3V

I

MC30 0.1UF/6.3V

I

MC29 0.1UF/6.3V

I

MC31 0.1UF/6.3V

I

MC32 0.1UF/6.3V

I

47
48
49

A A

PEGATRON DT-MB RESTRICTED SECRET

HDMI LEVEL SHIFT

HDMI LEVEL SHIFT

HDMI LEVEL SHIFT

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

1

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

57 97Friday, January 17, 2014

57 97Friday, January 17, 2014

57 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Vinafix.com

5

D D

HDMI_TXP2_LS_OUT[57]

C C

1 2

+5V_HDMI

I

MR15

2.2KOHM

MR14

2.2KOHM

1 2

B B

HDMI_CTRL_CLK_LS[57,58]
HDMI_CTRL_DATA_LS[57,58]

HDMI_TXN2_LS_OUT[57]

HDMI_TXP1_LS_OUT[57]

HDMI_TXN1_LS_OUT[57]

HDMI_TXP0_LS_OUT[57]

HDMI_TXN0_LS_OUT[57]

HDMI_CLKP_LS_OUT[57]

HDMI_CLKN_LS_OUT[57]

I

12

NI

MC22
470PF/50V

X7R 10%

4

3 4

MRN5B

MRN5A

MRN6B

MRN6A

MRN7B

MRN7A

MRN8B

MRN8A

12

NI

MC21
470PF/50V

X7R 10%

GNDGND

0

2 3

1 2

0

3 4

0

2 3

1 2

0

3 4

0

2 3

1 2

0

3 4

0

2 3

1 2

0

+5VA

VP

90OHM/100MHZ/330mA
ML8

NI

1 4

VP

VP

90OHM/100MHZ/330mA
ML7

NI

1 4

VP

VP

90OHM/100MHZ/330mA
ML6

NI

1 4

VP

VP

90OHM/100MHZ/330mA
ML5

NI

1 4

VP

2

HDMI_TMDS_DATA2_P

HDMI_TMDS_DATA2_N

HDMI_TMDS_DATA1_P

HDMI_TMDS_DATA1_N

HDMI_TMDS_DATA0_P

HDMI_TMDS_DATA0_N

HDMI_TMDS_CLK_P

HDMI_TMDS_CLK_N

3

NI

BAV99W-L
MD8

1

GND

3

NI

+5VA

BAV99W-L
MD7

1

2

GND

3

GND

GND

J137

HDMI_TMDS_DATA2_P
HDMI_TMDS_DATA2_N

HDMI_TMDS_DATA1_P
HDMI_TMDS_DATA1_N

HDMI_TMDS_DATA0_P
HDMI_TMDS_DATA0_N

HDMI_TMDS_CLK_P
HDMI_TMDS_CLK_N

+5V_HDMI

HDMI_HOTPLUG_DET[57]

HDMI_CTRL_CLK_LS[57,58]
HDMI_CTRL_DATA_LS[57,58]

12

I

MCB3

0.1UF/6.3V

+5VA

3

NI

BAV99W-L
MD4

1

2

GND

I

R60212
20KOhm

1 2

GND

GND

1

1

2

2

P_GND2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

P_GND3

12

12

13

13

14

14

15

15

16

16

17

17

18

18

P_GND1

19

19

HDMI_CON_19P

I

GND

12

NI

MC23
470PF/50V

X7R 10%

GND

2

MU5

HDMI_TMDS_DATA0_P HDMI_TMDS_DATA0_P
HDMI_TMDS_DATA0_N HDMI_TMDS_DATA0_N

HDMI_TMDS_CLK_P HDMI_TMDS_CLK_P
HDMI_TMDS_CLK_N

HDMI_TMDS_DATA1_N HDMI_TMDS_DATA1_N
HDMI_TMDS_DATA1_P HDMI_TMDS_DATA1_P

HDMI_TMDS_DATA2_N
HDMI_TMDS_DATA2_P

21

22

20

GND

1

TMDS_CH1-

2

TMDS_CH1+

3

GND1

4

TMDS_CH2­TMDS_CH2+5NC1

NI

IP4284CZ10-TB

MU6

1

TMDS_CH1-

2

TMDS_CH1+

3

GND1

4

TMDS_CH2­TMDS_CH2+5NC1

NI

IP4284CZ10-TB

GND2

GND2

NC4
NC3

NC2

NC4
NC3

NC2

10
9
8
7
6

+5V_HDMI

10
9
8
7
6

HDMI_TMDS_CLK_N

HDMI_TMDS_DATA2_N
HDMI_TMDS_DATA2_P

12

I

M1C2

0.1UF/6.3V

MLCC/+/-10%

GND

1

GND

GND

+12V_HDD+5V

12

I

SR626
10KOhm

12

I

12

SR627
10KOhm

GND

GND

I

VF2

1.1A/6V

1 2

2

S

G

1

1

I

D

VQ12

3

AP2306GN

3 2

I

VCB154

0.1UF/16V

X7R 10%

A A

PEGATRON DT-MB RESTRICTED SECRET

<Core Design>

<Core Design>

<Core Design>

Title :

Title :

Title :

HDMI OUT

HDMI OUT

HDMI OUT

Engineer:

Shrek_Tseng

Engineer:

Shrek_Tseng

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A2

A2

A2

IPPLP-TH

IPPLP-TH

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

IPPLP-TH

1

Shrek_Tseng

58 97Friday, January 17, 2014

58 97Friday, January 17, 2014

58 97Friday, January 17, 2014

Rev

Rev

Rev

A00

A00

A00

Vinafix.com

5

D D

4

3

2

1

C C

SMB_DATA_RESUME[15,16,22,28,29,44,60,76,77]

G_SENOER_INTER#[20]

B B

GND
GND

GND

+3P3V

12

MCB50.1UF/6.3V NI

12

MCB60.1UF/6.3V NI

12

MCB40.1UF/6.3V NI

U9419

1

ADDR

2

SDA

3

IO_VDD1

4

RSVD

5

INT

6

GND1

KXTJ2-1009

NI

SCL

IO_VDD2

VDD2
GND3
GND2
VDD1

+3P3V

12
11
10
9
8
7

GNDGND

1 2

MCB9 0.1UF/6.3V

NI
NI

1 2

MCB7 0.1UF/6.3V

12

NI

MCB8

0.1UF/6.3V

GND

GND

GND

SMB_CLK_RESUME [15,16,22,28,29,44,60,76,77]

A A

PEGATRON DT-MB RESTRICTED SECRET

<Core Design>

<Core Design>

<Core Design>

Title :

Title :

Title :

G-SENSOR

G-SENSOR

G-SENSOR

Shrek_Tseng

Shrek_Tseng

1

Shrek_Tseng

59 97Friday, January 17, 2014

59 97Friday, January 17, 2014

59 97Friday, January 17, 2014

Rev

Rev

Rev

A00

A00

A00

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

IPPLP-TH

IPPLP-TH

IPPLP-TH

Engineer:

Vinafix.com

5

D D

+3P3V

4

3

2

1

12

HR332

4.7KOHM

1%

NI

DP_CFG1

12

HR333

4.7KOHM

1%

NI

C C

B B

GND

+3P3V

+3P3V

12

12

GND

S1C56 0.01UF/25V

NI

S1C55 0.01UF/25V

NI

S1C54 0.01UF/25V

NI

SMB_CLK_RESUME[15,16,22,28,29,44,59,76,77]
SMB_DATA_RESUME[15,16,22,28,29,44,59,76,77]

HR325

4.7KOHM

1%

NI

I2C_ADDR

HR329

4.7KOHM

1%

NI

1 2
1 2
1 2

+3P3V

GND

GND
GND
GND

GND

GND

DDPB_HPD_DP_OUT[21]

DDPB_HPD_DP_IN[61]

12

HR334

4.7KOHM

1%

NI

DP_PEQ DP_CFG0

12

HR335

4.7KOHM

1%

NI

1 2

APR32 0 Ohm

NI

1 2

APR33 0 Ohm

NI

CONFIG1[61]

+3P3V

12

12

GND

HR336

4.7KOHM

1%

NI

HR337

4.7KOHM

1%

NI

12

S1C572.2UF/6.3VX5R 10% NI

I2C_ADDR

12

HR3284.99KOhm

GND

DP_PEQ
DP_CFG0

NI

50
51
52
53

PS8330BQFN48GTR-A0

U21B

EPAD1
EPAD2
EPAD3
EPAD4

NI

GND

49

48

47

46

45

44

43

41

NC3

IN3P

IN3N

OUT3N13OUT3P

NC4

14

16

15

IN2N

OUT2N

42

NC2

IN2P

IN1P

IN1N

OUT2P17GND118OUT1N19OUT1P20NC521OUT0N22OUT0P

GND

U21A

EPAD

1

VDD33_1

2

CEXT

3

I2C_ADDR

4

SCL_CTL/PEQ

5

SDA_CTL/CFG0

6

VDD33_2

7

REXT

8

CAD_SRC

9

HPD_SRC

10

CAD_SNK

11

HPD_SNK

12

VDD33_3

PS8330BQFN48GTR-A0 NI

DP_CFG1

40

39

IN0N

CFG1

AUX_SRCN

38

37

NC1

IN0P

VDD33_6

RST#
SDA_DDC
SCL_DDC

VDD33_5

GND3

AUX_SRCP
AUX_SNKP

AUX_SNKN

PD#

VDD33_4

GND2

23

24

GND

36
35
34
33
32
31
30
29
28
27
26
25

DP_TXN3_RD_IN_C

DP_TXP3_RD_IN_C

DP_TXN2_RD_IN_C

DP_TXP2_RD_IN_C

DP_TXN1_RD_IN_C

DP_TXP1_RD_IN_C

DP_TXN0_RD_IN_C
DP_TXP0_RD_IN_C

DP_RST#

GND

SC100 0.1UF/6.3V

NI

SC101 0.1UF/6.3V

NI

1 2
1 2

+3P3V

12

SC1090.1UF/6.3V

NI

12

SC1080.1UF/6.3V

NI

12

SC1070.1UF/6.3V

NI

12

SC1060.1UF/6.3V

NI

12

SC1050.1UF/6.3V

NI

12

SC1040.1UF/6.3V

NI

12

SC1030.1UF/6.3V

NI

12

SC1020.1UF/6.3V

NI

S1C62 0.1UF/6.3V
S1C53 0.1UF/6.3V
S1C37 0.1UF/6.3V

12
12
12

DP_TXP0_RD_OUT [61]
DP_TXN0_RD_OUT [61]

DP_TXP1_RD_OUT [61]
DP_TXN1_RD_OUT [61]

DP_TXP2_RD_OUT [61]
DP_TXN2_RD_OUT [61]

DP_TXP3_RD_OUT [61]
DP_TXN3_RD_OUT [61]

DP_TXN3_RD_IN [10]
DP_TXP3_RD_IN [10]

DP_TXN2_RD_IN [10]
DP_TXP2_RD_IN [10]

DP_TXN1_RD_IN [10]
DP_TXP1_RD_IN [10]

DP_TXN0_RD_IN [10]
DP_TXP0_RD_IN [10]

NI

GND

NI

GND

NI

GND

DDC_DATA_DP_IN [21]

DDC_CLK_DP_IN [21]

DDPB_AUXP_DP_IN [21]

DDPB_AUXN_DP_IN [21]
DDPB_AUXP_DP_OUT [61]
DDPB_AUXN_DP_OUT [61]

DP_RST#

+3P3V

12

12

GND

NI

HR327
10KOhm

1%

S1C63

2.2UF/6.3V

X5R 10%
NI

A A

PEGATRON DT-MB RESTRICTED SECRET

DP REDRIVER

DP REDRIVER

DP REDRIVER

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

IPPLP-TH

IPPLP-TH

IPPLP-TH

Engineer:

1

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

60 93Friday, January 17, 2014

60 93Friday, January 17, 2014

60 93Friday, January 17, 2014

1.00

1.00

1.00

Rev

Rev

Rev

Vinafix.com

5

4

3

2

1

DP_TXP0_RD_OUT[60]

NI

1 2

SC64 0.1UF/6.3V

ML_LANE_0P

NOTE:

Install M1Q6 and M1R7
on Intel Ibex Peak platform

DP_TXN0_RD_OUT[60]

D D

DP_TXP1_RD_OUT[60]

DP_TXN1_RD_OUT[60]

DP_TXP2_RD_OUT[60]

C C

DP_TXN2_RD_OUT[60]

DP_TXP3_RD_OUT[60]

DP_TXN3_RD_OUT[60]

B B

DDPB_AUXP_DP_OUT[60]
DDPB_AUXN_DP_OUT[60]

NI

SC66 0.1UF/6.3V

NI

SC67 0.1UF/6.3V

NI

SC68 0.1UF/6.3V

NI

SC69 0.1UF/6.3V

NI

SC70 0.1UF/6.3V

NI

SC71 0.1UF/6.3V

NI

1 2

1 2

1 2

1 2

1 2

1 2

SR142
100KOHM

1%
NI

GND

GND

GND

1 2

NI

M1U1

CM1213_04SO

CH1

1

VN

2

CH2 CH3

3 4

3 4

CH2CH3

2

VN

1

CH1

DP

NI

M1U2

CM1213_04SO

DP

CH4

6
5

VP

5
6

VP

CH4

1 2

SC65 0.1UF/6.3V

+5VA

ML_LANE_0N

ML_LANE_1P

ML_LANE_1N

ML_LANE_2P

ML_LANE_2N

+5VA

ML_LANE_3P

ML_LANE_3N

J125

1
3
4
6
7

9
10
12

15
17

ML_LANE_0P
ML_LANE_0N
ML_LANE_1P
ML_LANE_1N
ML_LANE_2P
ML_LANE_2N
ML_LANE_3P
ML_LANE_3N

AUX_CH_P
AUX_CH_N

DP_PWR

RETURN

HOT_PLUG_DETECT

Pass gate to prevent back-drive

when sink device is on and

PCH is powered down

+12V_HDD

+3P3V

2

S

NI

AP2306GN

MQ4

+3P3V_DP

20

12

NI

M1C1

0.1UF/6.3V

MLCC/+/-10%

19

18

GND

GND

NI

M1F1

1.1A/6V

12

DP_3P3V_PWR_FUSE

DDPB_HPD_DP_IN [60]

D

3

3 2

NI

VCB155

0.1UF/16V

X7R 10%

G

1

1

12

NI

SR628

10KOhm

12

10KOhm

GNDGND

NI

SR629

12

SR144

1%

13

14

12

4.99Mohm

NI

GND

CONFIG1

CONFIG2

DISPLAY_CON_20P

NI

GND_0
GND_1
GND_2
GND_3
GND_4

P_GND1
P_GND2
P_GND3

2
5
8
11
16

21
22
23

GND

PEGATRON DT-MB RESTRICTED SECRET

DP CONN

DP CONN

DP CONN

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

1

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

61 97Friday, January 17, 2014

61 97Friday, January 17, 2014

61 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

SR143
100KOHM

A A

5

+3P3V_DP

1%

1 2

NI

4

CONFIG1[60]

12

NI

SR141
1MOhm

5%

GND

3

Vinafix.com

5

D D

4

3

2

1

TPM_12
TPM_14

R105
0 Ohm

NI

+3P3V

12

NI

CB24

0.1UF/6.3V

MLCC/+/-10%

GND

12

GND

R106
0 Ohm

NI

NI

U20

1

NC1

2

NC2

3

NC3

4

GND1

5

NC4

6

NC5

7

PP

8

NC6

9

NC7

10

VPS1

11

GND2

12

NC8

13

NC9

14

NC10

ST33ZP24AR28PVOG

NC14

SERIRQ

LAD0
NC13
VPS2
LAD1

LFRAME#

LCLK
LAD2
NC12

GND3

LAD3

LRESET#

NC11

+3P3V

12

NI

CB25
10UF/6.3V

GND GND

28

Pin28 DO NOT CONEECT

27
26
25

TPM_25

TPM_19

CLKRUN#

NI

4.7K

NI

NI

12

R104

GND

24
23
22
21
20
19
18
17
16
15

12

NI

CB26

0.1UF/6.3V

MLCC/+/-10%

12

GND

1 2

+3P3V

NI

CB27

0.1UF/16V

X7R 10%

R940 Ohm

12

R990 Ohm

TPM_28

GND

+3P3V

12

NI

R89

4.7KOHM

LRESET#

0.1UF/16V

CB30

SERIRQ [20,44]

LAD0 [22,44,50]

LAD1 [22,44,50]

LFRAME# [22,44,50]

LAD2 [22,44,50]

LAD3 [22,44,50]

12

+12V_HDD

1

1

G

2

S

R1020 Ohm

TQ1

3

32

D

AP2306GN

PLTRST# [20,31,44,50]

NI

GND

12

NI

NI

SR140

8.2KOHM

12

NI

GND

CB28

0.1UF/16V

NI

CK_33M_TPM [21]

12

GND

+3P3VSB

12

+3P3V

R90
0 Ohm

NI

1 2

GND

C C

CK_14M_TPM[21]

B B

12

GND

NI

C101
1UF/16V

MLCC/+/-10%

R91 0 Ohm NI
R92 0 Ohm NI

R97 0 Ohm NI

NI

R88
0 Ohm

I_ATMEL

12
12

12

R103
0 Ohm

1 2

GND GND GND

NI

CB23
10UF/6.3V

1 2

GND GND

TPM_1
TPM_2
TPM_3

TPM_5_POWER

TPM_8

12

NI

12

CB29

0.1UF/6.3V

MLCC/+/-10%

TPM_9

A A

PEGATRON DT-MB RESTRICTED SECRET

TPM

TPM

TPM

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

IPPLP-TH

IPPLP-TH

IPPLP-TH

Engineer:

1

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

62 97Friday, January 17, 2014

62 97Friday, January 17, 2014

62 97Friday, January 17, 2014

1.00

1.00

1.00

Rev

Rev

Rev

Vinafix.com

5

4

3

2

1

+5VA

I

R1231

J164

9

1

5

2

6

3

D D

GND GND

C C

7
8

10

POWER_CON_8P

I

Pin define

4

需要確認

12

I

C941020

4.7UF/10V

X5R/+/-10%

GND GND

4.7KOHM

1 2

12

C941021

4.7UF/10V

X5R/+/-10%

I

Power_OK [67,74]

PS_ON# [44]

NOBOM

NOBOM

NOBOM

ST99
TPC26b

ST98
TPC26b

ST97
TPC26b

1

1

1

+12VSA
IMAX=14.5A
Trace Width>435mil

+12VBDC_VIN

12

PC18

0.1UF/16V

X7R 10%
I

GND

+12V_CPU
IMAX=12A

PL32

21

150Ohm/100Mhz/5A

I

PL23

21

150Ohm/100Mhz/5A

I

PL24

21

150Ohm/100Mhz/5A

I

+12VSA

12

GND

PC8

0.1UF/16V

X7R 10%
NI

Trace Width>350mil

+12VADC_VIN

P3

2

12

I

PC399
10PF/50V

B B

1

GND

4

2

4

3

1

3

5

NP_NC

POWER_CON_4P

I

I

C395
10PF/50V

NPO/+/-5%

GND

PL34

150Ohm/100Mhz/5A

PL26

150Ohm/100Mhz/5A

PL25

PC27

0.1UF/16V

X7R 10%
I

150Ohm/100Mhz/5A

12

12

GND

+12V_CPU

21

I

21

I

21

I

12

PC7

0.1UF/16V

X7R 10%
NI

GND

A A

PEGATRON DT-MB RESTRICTED SECRET

DC IN

DC IN

1

DC IN

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

63 97Friday, January 17, 2014

63 97Friday, January 17, 2014

63 97Friday, January 17, 2014

Rev

Rev

Rev

A00

A00

A00

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

IPPLP-TH

IPPLP-TH

IPPLP-TH

Engineer:

Vinafix.com

5

4

3

+1V_CPUIOOUT

2

1

VCORE_VCC_C

1 2

+5V

D D

1 2

47 OHM

mx_r0402

1%

PJP7

SHORTPIN

SHORTPIN

NOBOM

PJP8

SHORTPIN

SHORTPIN

NOBOM

NI

PR18

NI

PR67

I

PR108

NI

PR120

NI

PR191

I

PC72

I

PR10

NI

PR16

12

12

1 2
1 2

1 2
1 2

1 2

I

PR77

I

PR47

NI

PC34

I

PR48

I

PR76

12

+1V_CPUIOOUT

+1P05V_PCH

+3P3V

VRM_PWRGD[22,44,76]

+3P3V

+1V_CPUIOOUT

1 2

I

PR8

C C

GND

+VCORE

VCC_SENSE[11]

GND

VSS_SENSE[11]

GND

B B

Setting Iout

GND

Vupper=0.8V
Vlower=0.3V

[5/4] For BOM merge

+12V_CPU

0 Ohm

mx_r0402 5%

1KOhm

1%

mx_r0402

1KOhm

1%

mx_r0402

1KOhm

1%

mx_r0402

1KOhm

1%

mx_r0402

470PF/50V

mx_c0402
MLCC/+/-10%

1KOhm

1%

mx_r0402

12

200KOHM

1%

mx_r0402

1 2

1 2

1 2

1 2

1 2

100 Ohm

mx_r0402

0 Ohm

mx_r0402

12

0.1UF/16V

X7R 10%

0 Ohm

mx_r0402

100 Ohm

mx_r0402

I

12

PR49

41.2KOHM

1%

[11/27] For VRHOT fine tune

GND

GND
GND

1 2

I

PR9

1%

5%

5%

1%

I

PC89
470PF/50V

mx_c0402
MLCC/+/-10%

1 2

1%

I

PR126

7.32KOHM

I

PR3

I

PC11

1 2

I

PR7

I

PC73

1 2

NI

PR68

I

PC2

NI

PC122

1 2

3.74K Ohm

I

mx_r0402

PR17

1%

I

PC65

I

PC201

12

1000PF/50V

mx_c0402

MLCC/+/-10%

offset=5*PR60/(PR60+PR46)

1 2

I

PR64

I

PC88

1 2

NI

+5V

PR46

For Vcore VRHOT#
Close to Vcore Phase1 H/S-MOS(PQ68)

I

PR380

12

I

PRT6
100KOhm

mx_r0402
1%

1 2

1 2

1 2

12

12

12

12

2.2 Ohm

mx_r0805

4.7UF/6.3V

mx_c0603

1KOhm

mx_r0402

0.01UF/25V

mx_c0402

1KOhm

mx_r0402

0.1UF/16V

mx_c0402

MLCC/+/-10%

0.1UF/16V

mx_c0402

MLCC/+/-10%

VCORE_DIFFOUT_A

0 Ohm

mx_r0402 5%

47PF/50V

mx_c0402
MLCC/+/-5%

1.74KOHM

1%

4700PF/25V

mx_c0402
MLCC/+/-10%

0 Ohm

mx_r0402

VCORE_TSENSE_A

0 Ohm

mx_r0402

5%

12

GNDGND

5%

VCORE_VCC_C

MLCC/+/-10%

1%

VCORE_VRMP_A

MLCC/+/-10%

VCORE_EN_A

1%

GND

VCORE_PWRGD_A

GND

VCORE_COMP_A

VCORE_FB_A

VCORE_VSP_A

VCORE_VSN_A

5%

VCORE_IOUT_A

I

PC236

0.1UF/16V

mx_c0402

MLCC/+/-10%

GND

2

27

1

7

30

28

29

32

31

26

8
34
35
36
37
33

PU4

I

VCC

VRMP

ENABLE

VR_RDY

DIFFOUT

COMP

FB

VSP

VSN

IOUT

TSENSE
GND1
GND2
GND3
GND4
FLAG/GND

NCP81102

SDIO

SCLK

ALERT#

VR_HOT#

DRON

PWM1/INT_SEL

CSN1
CSP1

PWM2/VBOOT

CSN2
CSP2

PWM3/IMAX

CSN3
CSP3

PWM4/ROSC

CSN4
CSP4

CSSUM

CSCOMP

ILIM

CSREF

4

VCORE_SDIO

6

VCORE_SCLK

5

VCORE_ALERT

3

VR_HOT_#A

13

VCORE_DRON_A

12

VCORE_PWM1_A

15

VCORE_CSN1_A

14

VCORE_CSP1_A

10

VCORE_PWM2_A

19

VCORE_CSN2_A

18

VCORE_CSP2_A

11

VCORE_PWM3_A

17

VCORE_CSN3_A

16

VCORE_CSP3_A

9

VCORE_PWM4_A

21

VCORE_CSN4A_A

20

VCORE_CSP4_A

23

VCORE_CSSUM

24

VCORE_CSCOMP

25

VCORE_ILIM_A

22

VCORE_CSREF_A

GND

12

12

GND

1 2

I

PR95

22.6KOHM

Setting OCP=150A

1 2

I

PC216

I

PR5
110 Ohm

mx_r0402

1%

NI

PC6376
47PF/50V

NPO 5%

mx_c0402

CSP1_A[64,65]

CSP2_A[64,65]

CSP3_A[64,66]

CSP4_A[64]

1%mx_r0402

1000PF/50V

mx_c0402

MLCC/+/-10%

12

12

GND

12

I

PR6

54.9 OHM

mx_r0402
1%

NI

PC6375
47PF/50V

NPO 5%

mx_c0402

Setting PWM frequency, 300kHz

For thermal compensation
close to Vcore choke

NI

PR209
75 OHM

mx_r0402

1%

1 2

PR259

Setting Address=0000H

1 2

I

PR82

1 2

PR125

Setting VBOOT=1.7V

1 2

I

PR83

1 2

PR260

Setting Vcore IMAX=70A

1 2

I

PR87

1 2

PR257

1 2

PR163

1 2

I

PR93

1 2

I

PRT4

1 2

I

PR109

1 2

I

PR119

1 2

I

PR124

1 2

NI

PR153

12

GND

68KOHM

1%Imx_r0402

3.3KOHM

1%

69.8KOHM

1%Imx_r0402

3.3KOHM

1%

59KOHMI

1%

3.3KOHM

1%

20K

1%Imx_r0402

4.7KOHM

1%NImx_r0402

49.9KOHM

mx_r0402

100KOhm

mx_r0402
1%

10 OHM

mx_r0402

10 OHM

mx_r0402

10 OHM

mx_r0402

10 OHM

mx_r0402

I

PC12

0.1UF/16V

mx_c0402

MLCC/+/-10%

VIDSOUT [11]
VIDSCLK [11]
VIDALERT# [11]

NI

PC103

GND

1 2

PR75

1 2

I

PC218

GND

1 2

PR84

1 2

I

PC220

GND

1 2

PR85

1 2

I

PC223

GND

1 2

PR122

1 2

NI

PC258

[11/20] For VR fine tune

1 2

1%

PR123

I

PC91

I

PC213

1%
1%
1%
1%

12

0.01UF/25V

X7R 5%

12

12

100KOHM

1%NImx_r0402

0.1UF/16V

mx_c0402

MLCC/+/-10%

100KOHM

1%NImx_r0402

0.1UF/16V

mx_c0402

MLCC/+/-10%

100KOHM

1%NImx_r0402

0.1UF/16V

mx_c0402

MLCC/+/-10%

100KOHM

1%NImx_r0402

0.1UF/16V

mx_c0402

MLCC/+/-10%

110KOHMI

1%

470PF/50V

NPO/+/-5%

NPO 5%

2200PF/50V

X7R 10%

1 2

I

PC105

GND

PR378

3/4 Phase Option

I

PR379

1 2

I

PR96

1 2

I

PR121

1 2

I

PR86

1 2

NI

PR166

47PF/50V

MLCC/+/-5%

12

0 Ohm

5%NImx_r0402

12

0 Ohm

mx_r0402

GND

PROCHOT# [11,44]

VCORE_DRON_A [65,66]

VCORE_PWM1_A [65]

VCORE_CSN1_A [64,65]

VCORE_PWM2_A [65]

VCORE_CSN2_A [64,65]

VCORE_PWM3_A [66]

VCORE_CSN3_A [64,66]

1

ST253

VCORE_CSN4_A [64]

5%

100KOhm

mx_r0603/1%

100KOhm

mx_r0603/1%

100KOhm

mx_r0603/1%

100KOhm

mx_r0603/1%

VCORE_CSN1_A [64,65]
VCORE_CSN2_A [64,65]
VCORE_CSN3_A [64,66]
VCORE_CSN4_A [64]

VCORE_VCC_C

NOBOM

CSP1_A [64,65]
CSP2_A [64,65]

CSP3_A [64,66]

CSP4_A [64]

A A

<Variant Name>

<Variant Name>

<Variant Name>

VCORE CONTROLLER

VCORE CONTROLLER

VCORE CONTROLLER

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

1

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

64 97Friday, January 17, 2014

64 97Friday, January 17, 2014

64 97Friday, January 17, 2014

Rev

Rev

A00

A00

A00

Rev

Vinafix.com

5

+12V_CPU

D D

12

I

PR193

2.2 Ohm

mx_r0603
5%

VCORE_PWM1_A[64]
VCORE_DRON_A[64,65,66]

CORE_PWM1_VCC_B

I

12

PC9
1UF/16V

mx_c0603
X7R 10%

C C

GND

+12V_CPU

1 2

I

PR194
51 OHM

mx_r0402
5%

CORE_PWM1_BOOT_R_C

12

I

PR25

2.2 Ohm

mx_r0805
5%

PWM1_BOOT_C

DREN1DREN1

1
2
3

I

PC6332

I

PU25

NCP81161MNTBG

FLAG

BST

DRVH

PWM

SW

EN

GND

VCC4DRVL

9
8
7
6
5

12

0.1UF/25V

mx_c0603

GND

4

X7R 10%

CORE_PWM1_HG_D
CORE_PWM1_SW_S

CORE_PWM1_LG_D

I

PR15

I

PR60215

1 2

1 2

0 Ohm

mx_r0805
5%

12

PR192

8.2KOHM

1%
I

CORE_PWM1_LG_D_R

0 Ohm

mx_r0805
5%

12

PR195

8.2KOHM

GND

3

2

+12V_CPU

1

VCORE
Imax=95A/TDC=55A

I

PQ533

54

BSC889N03LS

876

5
D

S

G

123

CORE_PWM1_HG_D_R

12

NI

PC8791
1000PF/50V

mx_c0402
MLCC/+/-10%

NI

PQ532

54

BSC883N03LS

876

5
D

S

G

123

12

NI

PC8789

1%
I

1000PF/50V

mx_c0402

MLCC/+/-10%

GND

GND

I

PQ531

54

BSC883N03LS

5
D

S

G

876

123

GND

12

I

PR287
1

mx_r1206

PWM1_SN_D

12

I

PC282
4700PF/50V

X7R 10%
mx_c0603

GND

12

I

PC322
10UF/25V

X5R 10%
mx_c0805

CSP1_A[64]
VCORE_CSN1_A[64]

GND

12

GNDGND

NI

12

PC81
680PF/50V

mx_c0402
X7R 10%

I

PC320
10UF/25V

X5R 10%
mx_c0805

12

GND

12

+12V_CPU

I

PC107
10PF/50V

I

PL7

0.36UH

30A/60A/1.05mohm

PJP5207
SHORTPIN

NOBOM

SHORTPIN

+VCORE

21

12

I

PC353

12

PJP5206
SHORTPIN

NOBOM

SHORTPIN

22UF/6.3V

X5R 20%
mx_c0805_small

GND

I

PC337
10UF/25V

X5R 10%
mx_c0805

CSP2_A[64]
VCORE_CSN2_A[64]

GND

12

I

PC323
10UF/25V

X5R 10%
mx_c0805

GNDGND

I

PL8

0.36UH

30A/60A/1.05mohm

21

12

PJP5205

12

NI

PC82
680PF/50V

mx_c0402
X7R 10%

SHORTPIN

NOBOM

SHORTPIN

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

12

PJP5208
SHORTPIN

NOBOM

SHORTPIN

Title :

Title :

Title :

1

+VCORE

12

I

PC351
22UF/6.3V

X5R 20%
mx_c0805_small

GND

VCORE DRIVER 1

VCORE DRIVER 1

VCORE DRIVER 1

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

65 97Friday, January 17, 2014

65 97Friday, January 17, 2014

65 97Friday, January 17, 2014

1.00

1.00

1.00

Rev

Rev

Rev

12

I

PR304
1

mx_r1206

PWM2_SN_D

12

I

PC283
4700PF/50V

X7R 10%
mx_c0603

GND

2

12

I

PQ536

54

BSC889N03LS

876

5
D

S

B B

12

I

PR167

2.2 Ohm

mx_r0603
5%

VCORE_PWM2_A[64]
VCORE_DRON_A[64,65,66]

CORE_PWM2_VCC_B

I

12

PC10
1UF/16V

X7R 10%
mx_c0603

A A

GND

5

1 2

I

PR189
51 OHM

mx_r0402
5%

CORE_PWM2_BOOT_R_C

12

I

PR20

2.2 Ohm

mx_r0805
5%

PWM2_BOOT_CPWM2_BOOT_C

DREN2

I

PU26

NCP81161MNTBG

1
2
3

BST
PWM
EN
VCC4DRVL

I

PC13

FLAG

DRVH

GND

12

0.1UF/25V

mx_c0603

9
8
7

SW

6
5

GND

X7R 10%

CORE_PWM2_HG_DCORE_PWM2_HG_D
CORE_PWM2_SW_SCORE_PWM2_SW_S

CORE_PWM2_LG_DCORE_PWM2_LG_D

4

I

PR38

I

PR34

1 2

1 2

0 Ohm

mx_r0805
5%

0 Ohm

mx_r0805
5%

CORE_PWM2_HG_D_R

12

CORE_PWM2_LG_D_R

12

GND

PR196

8.2KOHM

1%
I

3

12

GND

PR190

8.2KOHM

1%
I

NI

PC8793
1000PF/50V

mx_c0402
MLCC/+/-10%

12

NI

PC8792
1000PF/50V

mx_c0402
MLCC/+/-10%

NI

PQ537

54

BSC883N03LS

5
D

G

G

123

I

PQ535

54

876

S

123

GND

BSC883N03LS

5
D

S

G

876

123

GND

Vinafix.com

5

4

3

2

1

+12V_CPU

12

I

PR305
1

mx_r1206

PWM3_SN_D

12

I

PC319
4700PF/50V

X7R 10%
mx_c0603

12

CSP3_A[64]
VCORE_CSN3_A[64]

+12V_CPU

I

PC19

FLAG

BST

DRVH
PWM
EN

GND

VCC4DRVL

NI

12

PC170
22UF/6.3V

MLCC/+/-20%

mx_c0805

0.1UF/25V

mx_c0603
X7R 10%

SW

12

9
8
7

CORE_PWM3_SW_S

6
5

CORE_PWM3_LG_D

GND

I

12

PC202
22UF/6.3V

MLCC/+/-20%

mx_c0805

I

PR19
0 Ohm

mx_r0805
5%

I

PR27
0 Ohm

mx_r0805
5%

1 2

1 2

CORE_PWM3_HG_D_R

CORE_PWM3_LG_D_R

12

GND

PR200

8.2KOHM

1%
I

PR187

8.2KOHM

1%

1 2

I

12

NI

PC8795
1000PF/50V

mx_c0402
MLCC/+/-10%

GND

12

NI

PC8796
1000PF/50V

mx_c0402
MLCC/+/-10%

G

NI

PQ534

54

BSC883N03LS

5
D

S

123

GND

876

D D

CORE_PWM3_BOOT_R

12

I

PR198

2.2 Ohm

mx_r0603
5%

VCORE_PWM3_A[64]
VCORE_DRON_A[64,65]

CORE_PWM3_VCC_B

I

12

PC63
1UF/16V

mx_c0603
X7R 10%

C C

GND

+VCORE

12

I

PR165

2.2 Ohm

mx_r0805
5%

PWM3_BOOT CORE_PWM3_HG_D

1 2

I

PR197
51 OHM

mx_r0402
5%

DREN3

I

PU27

NCP81161MNTBG

1
2
3

Place all 0805 MLCC inside CPU Socket.

I

12

PC166
22UF/6.3V

MLCC/+/-20%

mx_c0805

I

12

PC167
22UF/6.3V

MLCC/+/-20%

mx_c0805

I

12

PC168
22UF/6.3V

MLCC/+/-20%

mx_c0805

NI

12

PC169
22UF/6.3V

MLCC/+/-20%

mx_c0805

I

PQ526

54

BSC889N03LS

5
D

S

G

I

PQ529

54

BSC883N03LS

5
D

S

G

876

123

876

123

GND

GND

I

PC350
10UF/25V

X5R 10%
mx_c0805

12

GND

12

GNDGND

NI

PC83
680PF/50V

mx_c0402
X7R 10%

I

PC338
10UF/25V

X5R 10%
mx_c0805

12

GND

I

PL6

0.36UH

30A/60A/1.05mohm

12

PJP5210
SHORTPIN

NOBOM

SHORTPIN

I

PC115
10PF/50V

+VCORE

21

12

PJP48
SHORTPIN

NOBOM

SHORTPIN

12

I

PC354
22UF/6.3V

X5R 20%
mx_c0805_small

GND

+VCORE

B B

I

12

PC203
22UF/6.3V

MLCC/+/-20%

mx_c0805

I

12

PC171
22UF/6.3V

MLCC/+/-20%

mx_c0805

A A

I

12

PC176
22UF/6.3V

MLCC/+/-20%

mx_c0805

I

12

PC364
22UF/6.3V

MLCC/+/-20%

mx_c0805

I

12

PC172
22UF/6.3V

MLCC/+/-20%

mx_c0805

I

12

PC177
22UF/6.3V

MLCC/+/-20%

mx_c0805

5

I

12

PC363
22UF/6.3V

MLCC/+/-20%

mx_c0805

I

12

PC173
22UF/6.3V

MLCC/+/-20%

mx_c0805

I

12

PC178
22UF/6.3V

MLCC/+/-20%

mx_c0805

I

12

PC359
22UF/6.3V

MLCC/+/-20%

mx_c0805

I

12

PC174
22UF/6.3V

MLCC/+/-20%

mx_c0805

I

12

PC6378
22UF/6.3V

MLCC/+/-20%

mx_c0805

I

12

PC358
22UF/6.3V

MLCC/+/-20%

mx_c0805

I

12

PC6377
22UF/6.3V

MLCC/+/-20%

mx_c0805

I

12

PC6379
22UF/6.3V

MLCC/+/-20%

mx_c0805

GND

12

I

+

PCE731
560UF/6.3V

8mohm 4.7A

GND

+VCORE

I

12

PC179
22UF/6.3V

MLCC/+/-20%

mx_c0805

GND

4

12

I

+

PCE732
560UF/6.3V

8mohm 4.7A

I

12

PC182
22UF/6.3V

MLCC/+/-20%

mx_c0805

Place MLCC at top socket edge.

12

I

+

PCE733
560UF/6.3V

8mohm 4.7A

I

12

PC6347
22UF/6.3V

MLCC/+/-20%

mx_c0805

3

12

I

+

PCE734
560UF/6.3V

8mohm 4.7A

I

12

PC186
22UF/6.3V

MLCC/+/-20%

mx_c0805

12

I

+

PCE735
560UF/6.3V

8mohm 4.7A

<Variant Name>

<Variant Name>

<Variant Name>

VCORE DRIVER 2

VCORE DRIVER 2

VCORE DRIVER 2

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

1

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

66 97Friday, January 17, 2014

66 97Friday, January 17, 2014

66 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Vinafix.com

5

3

3

3

%

4

3

2

1

+12V/Imax:10A/TDC:7A

Vdroop: 7A*18mohm=126mV

+12VSA

+3.3V_LAN
Imax=0.188A

D D

12

PR60230

8.2KOHM

1%
I

3P3V_LAN_PMOS

3

C

I

B

1 2

SLP_LAN#[22]

C C

PR37 8.2KOHM

1%I

GND

PQ13_BASE

I

12

PC32

4.7UF/6.3V

X5R 10%
mx_c0603_small

1

PQ13
PMBS3904

E
2

GND

Vdroop: 0.188A*218mohm=40mV

12

GND

1

PC28

0.1UF/6.3V

MLCC/+/-10%

PR60238
15KOhm

I

1 2

+3P3VA+5VA

2

I

S

PQ9488
AP2307GN

Rdson=85mohm@Vth=-3V

G

D

Id=-4A/Pd=1.38W

3

I

+3P3V_LAN

12

I

PC604

0.1UF/6.3V

X7R 10%

GND

+5VSB

Power_OK[63,74]

12

12

NI

PC315

0.1UF/16V

X7R 10%

12

PR43
10KOhm

I

I
1%

100KOHM
PR284

+12V_HB_C

12

I

PC314
1UF/16V

X7R 10%
mx_c0603

12

I

PR286

30KOHM

1%

32

3

D

1

1

G

S

2

I

PQ256
2N7002

I

PQ140

S

1
2
3
4

G

SI4835DDY-T1-GE3

+12V_ENG# [44]

+12V

I

GND

12

PL201

1UH/14A

I

PR285
10KOhm

8
7
6
5

D

+12V_HDD

21

12

NI

+

PCE418
270UF/16V

PL/Lf_T=2000hrs_105c/+/-20

GND

ATX_PWRGD

GND

GND

+3P3V_BG/Imax:0.028A

+3P3V

+1P5V_PCH/Imax:0.36A

B B

+3P3V

12

12

A A

GND

Vdroop: 0.36A*27.6mohm=19mV

+5VSB

12

I

PR60231

8.2KOHM

1%

PC321
1UF/6.3V

X5R/+/-10%

I

PR350

100KOHM

I
1%

3

C

B

1

I

PQ593

E

PMBS3904

2

GND

5

1 2

I

1 2

PR484

mx_r0402_small

1%

3

I

PQ585
30mOhm/10V SOT-23

3 2

S

D

3

2

G

1

1

NI

PR60236
100KOHM

1%

1 2

GND

4

+1P5V_PCH

12

NI

PC601

0.1UF/6.3V

X7R 10%

GND

+1P5V_PCH

PR89 1K 1%

NI

1 2

SLP_S3#[22,44,50,72,74]

PR185 10KOhmNI

I

PR377
20KOhm

1%

I

PQ595
2N7002

+1P5V_DUAL

+12V_HDD

12

32

3

D

1

12

GND

1

PC335
1UF/6.3V

X5R/+/-10%

I

G

S

2

GND

+3P3V_BG_ENRR PQ589_B

12

0

mx_r0603

0.05

NI

PR186
2KOhm

PQ596_B

+3P3V_BG

12

GNDGND

NI

PC147

4.7UF/6.3V

mx_c0603
MLCC/+/-10%

1

1

+3P3VSB

B

B

GND

12

3

C

E
2

3

C

E
2

NI

PR309

4.7KOHM

1%

NI

PQ589
PMBS3904

NI

PQ596
PMBS3904

PR181 10KOhmNI

1 2

2

1%

Vdroop: 0.028A*27.6mohm=0.7mV

+12V_HDD

12

NI

PR375
10KOhm

1%

+3P3V_BG_G

3

C

NI

B

1

PQ588
PMBS3904

E
2

GND

<Core Design>

<Core Design>

<Core Design>

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

12

NI

PR184
51KOHM

1%

GND

IPPLP-TH

IPPLP-TH

IPPLP-TH

GND

1

1

12

NI

PC324

0.1UF/6.3V

MLCC/+/-10%

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

1

+3P3V

32

3

D

NI

PQ570
30mOhm/10V SOT-23

G

S

2

+3P3V_BG

12

NI

PC602

0.1UF/16V

mx_c0402
MLCC/+/-10%

GND

3P3_LAN,12V,1P5V_PCH,

3P3_LAN,12V,1P5V_PCH,

3P3_LAN,12V,1P5V_PCH,

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

67 97Friday, January 17, 2014

67 97Friday, January 17, 2014

67 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Vinafix.com

5

4

3

2

1

+5V/Imax:6.42A/TDC:4.5A

D D

+12V_HDD

12

12

I

PC96
1UF/16V

X7R 10%
mx_c0603

GND

C C

Vdroop: 4.5A*9mohm=40.5mV Vdroop: 6A*9mohm=54mV

+12V_HDD

12

12

GND

I

PR80
20KOhm

1%

+5V_EN

+5VSB

I

PQ14
SM3119NAUC-TRG

Vgs=10v@9mohm

2 3

D

2

1

1

S

G

+5V

3

12

I

PC640582

0.1UF/16V

X7R/+/-10%

+3P3V/Imax:8.57A/TDC:6A

I

PQ16

+3P3VA

SM3119NAUC-TRG

I

PR81
20KOhm

1%

I

PC97
1UF/16V

X7R 10%
mx_c0603

Vgs=10v@9mohm

2 3

D

2

1

1

+3P3V_EN[74]

1 2

NI

PC640578

0.1UF/6.3V

X7R 10%

I

PR485
0

mx_r0603

+3P3V_ME

+3P3V

S

3

G

12

GNDGND

+3P3V_ME/Imax:0.03A

Vdroop: 0.03A*27.6mohm=1mV

+3P3VSB

+12VSA

12

1

1

G

NI

PR320
20KOhm

1%

32

3

D

NI

PQ591
2N7002

S

2

GND

IPPLP-TH

IPPLP-TH

IPPLP-TH

+3P3V_ME_ENR_R

B B

+5VSB

I

PC284
10UF/6.3V

X5R 10%

1 2

mx_c0805_small

GND

+12VSA

1 2

A A

SLP_S4#[22,44,50,72]

PR102 0Ohm 5%NOBOM

5

Vdroop = 8.5A*13.8m = 117mV

I

PQ607
SM3119NAUC-TRG

Vgs=10v@9mohm

2 3

D

2

1

1

12

NI

PC937

0.01UF/25V

X7R 10%

GND

GND

+5V_DUAL

S

3

G

12

1%

12

GND

3
2

1

I

RN47A4

E

3

2

1

E

PQ919

PR103 10KOhm

I

12

I

PC333
1UF/16V

X7R 10%
mx_c0603_small

GND

4

4

C

B

5

C

5

4

PR934

100KOHM

I
1%

I

PC259
10UF/6.3V

X5R 10%

1 2

mx_c0805_small

GND

3

NI

1 2

SLP_A#[22,44,50,91]

PR317
10KOhm

+3P3V_ME_ENRR

1%

GND

12

NI

PC330

0.1UF/16V

MLCC/+/-10%

2

1

+12VSA

1

G

3

2

GND

12

32

D

S

NI

PR318

100KOHM

NI

PQ592
2N7002

1%

+3P3V_ME_ENR

12

NI

PR319
100KOHM

1%

GND

<Core Design>

<Core Design>

<Core Design>

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

+5V_DUAL / TDC:8.5A

NI

PQ590
30mOhm/10V SOT-23

3 2

D

3

12

NI

PR321

100KOHM

1%

GND GND

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

1

+3P3V_ME

S

2

G

1

1

12

5V, 3P3V, 1P5V, 5V_Dual

5V, 3P3V, 1P5V, 5V_Dual

5V, 3P3V, 1P5V, 5V_Dual

12

NI

PC331

0.1UF/16V

MLCC/+/-10%

GND

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

68 97Friday, January 17, 2014

68 97Friday, January 17, 2014

68 97Friday, January 17, 2014

NI

PC663

0.1UF/6.3V

X7R 10%

Rev

Rev

Rev

A00

A00

A00

Vinafix.com

5

V

V

V

4

3

2

1

+1P05V_PCH Imax=6A

12

GND

I

PC80
10UF/6.3V

X5R 10%
mx_c0805

12

I

PC256
10UF/6.3V

X5R 10%
mx_c0805

Pd=4.2*(1.5-1.05)=1.89W

+1P05V_PCH

12

NI

PC257
10UF/6.3V

X5R 10%
mx_c0805

GND

+1P5V_DUAL

D D

+1P5V_DUAL_PG[72]

C C

+5V

1 2

12

GND GNDGND

I

GND

I

PR384
10KOhm

1%

I

PC369

0.1UF/16V

X7R 10%

10KOhm

1%

I

PU302

1

EN

2

GND

3

FB

APL5611CI-TRG

I

+1P05V_PCH_FB1_A

I

PR66

I

PC640576

1 2

12

PR115

6

VCC

5

DRV

4

SS

12

PC78 270PF/50V

3.16KOhm

1%

12

2200PF/50V

X7R 10%

X7R/+/-10%

+5V

12

PC253
1UF/6.3V

X5R/+/-10%

I

GND

+1P05V_PCH_DRI_C

+1P05V_PCH_SS_A

12

I

PC79

0.01UF/25V

X7R 10%

+1P05V_PCH_FB2_A

1 2

12

Vout=0.8(1+3.16/10)=1.052V

I

PR60249

PR299

5.76KOhm

1%
I

+1P05V_PCH_FB

PC50
680PF/50V

MLCC/+/-10%
I

1 2

100 Ohm

mx_r0805

12

NI

PR42

8.2KOHM

5%

SHORTPIN

NOBOM

1

PJP312

1

G

23

2

D

I

PQ125
SM3119NAUC-TRG

Vgs=10v@9mohm

S

3

12

12

I

PC255
10UF/6.3V

X5R 10%
mx_c0805

GND GND

B B

A A

+3P3V

12

12

GND

I

PR662
2KOhm

1%

PC667

0.1UF/16V

I

GND

12

12

NI

2.2 OHM
PR665

PC659

0.1UF/16V

I

+5V

12

I

2.2 OHM
PR666

+1P5V_DUAL+5VSB

I

GND

12

PC654

10UF/6.3V

I

GND

PU303

1

PGOOD

2

EN

3

VIN

4

VDD

RT9025_25PSP

1 2

PR175
10KOhmI1%

GND2
GND1

ADJ

VOUT

9
8
7
6
5

NC

GND

+1P22V_ADJ

PR110

1 2

I

5.36KOHM 1%

12

I

PC657 0.047UF/16V

+1P22V Imax=0.4A

Pd=2*(1.5-1)=1W
Vdroop: 1.94A*25mOhm=48mV

GND

12

NI

PC658
10UF/6.3V

X5R 10%

+1P22V

GND

12

I

PC666

10UF/6.3V

X5R 10%

Vout=((6.34K/10K)+1)*0.75V=1.22V

+1P05V_PCH & +1P22

+1P05V_PCH & +1P22

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

IPPLP-TH

IPPLP-TH

IPPLP-TH

Engineer:

1

+1P05V_PCH & +1P22

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

69

69

69

Rev

Rev

Rev

A00

A00

A00

97Friday, January 17, 2014

97Friday, January 17, 2014

97Friday, January 17, 2014

Vinafix.com

5

I

I

+5VA

+3P3VREF

NI

PR488

100KOHM

I
1%

NI

PC336

0.1UF/50V

X7R 10%
mx_c0603

5

PR330

2.2

mx_r1206_h26

1 2

12

I

PC43
1UF/6.3V

X5R 10%
mx_c0603

GND GND

1 2

I1%

GND

PR113 154KOHM

1 2

I1%

GND

PR112 154KOHM

1 2

APR45 0 Ohm

+5VA

12

PR487

100KOHM

I
1%

32

3

D

I

1

1

PQ568

G

2N7002

S

2

GNDGND

12

12

1UF/6.3VI

X5R 10%

PR288 10KOhmI

PC332

5V3V_VIN_C

12

X7R/+/-10%

GND

12

I

PC41
1UF/6.3V

X5R 10%
mx_c0603

1%

I

PC325
1UF/16V

ENTRIP1ENTRIP1

ENTRIP2ENTRIP2

5V3V_EN2

GND

+12VSA

D D

C C

SLP_SUS#[22,44,71]

B B

SIO_SUS3_ON#[44,71]

A A

+5VA

12

12

+5VA

GND

PU305
TPS51225CRUKR

12

VIN

13

VREG5

3

VREG3

7

PGOOD

19

VCLK

1

CS1

5

CS2

20

EN1

6

EN2

21

GND0

22

GND1

23

GND2

4

4

VBST1

DRVH1

SW1

DRVL1

VO1

VFB1

VBST2

DRVH2

SW2

DRVL2

VFB2

17

16

18

15

14

2

VFB = 2V

9

10

8

11

4

VFB = 2V

+5VSB_BST_C

+5VSB_HG_D

+5VSB_PHASE_D

+5VSB_LG_D

+5VSB_VO1_A

+5VSB_FB_A

+3P3VA_BST_C

+3P3VA_HG_D

+3P3VA_PHASE_D5V3V_EN1

+3P3VA_LG_D

+3P3VA_FB_A

NI

PC472

2.2PF/50V

NPO/+/-0.25PF

1 2

I

PR225

2.2

mx_r0805

1 2

GND

+5VSB_BST_RC_C

I

PR71
0

mx_r0805

1 2

I

PR72

1 2

PC341 0.1UF/16VIX7R 10%

NI

PC473

2.2PF/50V

NPO/+/-0.25PF

1 2

I

PR221

2.2

mx_r0805

1 2

12

I

PR73

I

PR199
15K

1%

1 2

+3P3VSB_BST_RC_C

I

PR74

NI

PC67
47PF/50V

NPO 5%

PR212
10KOhmI1%

1 2

GND

1 2

0

mx_r0805

1 2

12

12

3

GND

PC48

1 2

0.1UF/25V

I
X7R/+/-10%

8.2KOHM

0

mx_r0805

8.2KOHM

PC69 47PF/50VNPO 5%

NI

15.4KOhm

1%

12

I

PR224
10KOhm

1%

GND

PC70

0.1UF/25V

I
X7R/+/-10%

0

mx_r0805

3

PR60

1%
I

PR61

1%
I

12

GND

GND

GND

12

GND

12

+5VSB_HG_R_D

1 2

+5VSB_LG_R_D

12

1 2

GND

I

PR182

+3P3VA_HG_R_D

PR210

8.2KOHM

1%

1 2

I

+3P3VA_LG_R_D

12

PR63

8.2KOHM

1%

1 2

I

GND

I

PC109

0.1UF/16V

X7R 10%

12

NI

PC101
1000PF/50V

X7R/+/-10%

I

PQ104

NTMFS4839NHT1G

NI

PC492

2.2PF/50V

NPO/+/-0.25PF

12

I

PC39

0.1UF/16V

X7R 10%

GND

12

NI

PC102
1000PF/50V

X7R/+/-10%

I

PQ102

NTMFS4839NHT1G

NI

PC493

2.2PF/50V

NPO/+/-0.25PF

G

G

I

PQ566

54

BSC889N03LS

5
D

S

G

54

5
D

G

I

PQ563

54

BSC889N03LS

5
D

S

123

54

5
D

S

123

GND

876

123

876

S

123

876

12

876

12

GND

+5VSB_FBR

12

+3P3VA_SN_D

12

GNDGND

2

I

PR332
1

mx_r1206

+5VSB_SN_D

I

PC339
4700PF/50V

X7R/+/-10%

I

PR333
1

mx_r1206

I

PC344
4700PF/50V

X7R/+/-10%

2

GND

12

GND

PC352
22UF/25V

12

I

I

PL5

3.3UH/14A/25A

I

PC342
22UF/25V

I

PL4

3.3UH/14A/25A

1

+5VSB/ Max:18.6A / TDC:13A

Fsw = 300kHz
Iin=6.48A
Delta I = 3.24A
ripple = 44mV
OCP = 30A
Eff=93%
H/S =1.4W
L/S = 0.92 W

I

PCE27
220UF/6.3V

ESR=18mOhm

12

GND

+12VSA

+12VSA

I

PC640573
22UF/25V

21

GND

12

I

PC343
10UF/6.3V

X5R 10%
mx_c0805

GND

12

+

+3P3VA/ Max:16.6A / TDC:11.6A

I

PC640572
22UF/25V

21

Fsw = 300kHz
Iin=4.58A
Delta I = 2.66A
ripple = 36mV
OCP =24A
Eff=90.6%
H/S =0.64 W
L/S =0.71W

12

I

PC346
10UF/6.3V

X5R 10%
mx_c0805

GND

GND

12

+

I

PCE30

220UF/6.3V

ESR=18mOhm

+3P3VA_FBR

12

GND

PEGATRON DT-MB RESTRICTED SECRET

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

IPPLP-TH

IPPLP-TH

IPPLP-TH

Engineer:

1

+5VSB

12

+5VSB , +3P3VA

+5VSB , +3P3VA

+5VSB , +3P3VA

12

NOBOM

PJP520
SHORTPIN

NOBOM

PJP302
SHORTPIN

+3P3VA

12

NOBOM

PJP304
SHORTPIN

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

70 97Friday, January 17, 2014

70 97Friday, January 17, 2014

70 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Vinafix.com

5

G

G

G

D D

SIO_SUS3_ON#[44,70]

C C

SLP_SUS#[22,44,70]

X7R 10%

4

PR60250 0 Ohm

NI

GND

PR60241 0 Ohm

I

1 2

PC6405850.1UF/6.3V

12

1 2

NI

PR60251
10KOhm

1%

NI

1

1

+3P3VA

3

G

2

GND

3

12

+3P3VA

32

D

NI

PQ9508
2N7002

S

12

NI

PC21

0.047UF/16V

X7R/+/-10%

GND

I

PQ141

S

1
2
3
4

G

SI4835DDY-T1-GE3

8
7
6
5

D

+3P3VSB

12

GND

NI

PC640580

0.1UF/6.3V

X7R 10%

2

+3P3VSB/TDC:3.8A

Vdroop =3.8A*35mohm = 133mV

1

GPU POWER DISCHARGE

+3P3V_GPU

12

NI

R60387
330Ohm

+3P3V_GPU_DISCH_A

B B

+3P3VSB

12

NI

100KOhm
R60366

GPU MAINPOWER_DISCH_G

32

3

D

NI

PQ23

1

1

A A

GPUPW_EN[22,91,93]

5

2N7002

G

S

2

GND

32

3

D

NI

PQ28

1

1

2N7002

G

S

2

GND

4

+1P5V_GPU

1

1

G

3

2

12

+1P5V_GPU_DISCH_A

32

D

S

NI

R60384
330Ohm

NI

PQ26
2N7002

12

NI

R60383
330Ohm

+0P95V_DISCH_A

32

3

D

NI

PQ10

1

1

2N7002

G

S

2

GNDGND

+VDDC+0P95V

12

NI

R60382
330Ohm

+VDDC_DISCH_A

32

3

D

NI

PQ21

1

1

2N7002

G

S

2

GND

3

+1P8V_MXM

1

1

G

GND

12

+1P8V_MXM_DISCH_A

32

3

D

S

2

NI

R60386
330Ohm

NI

PQ27
2N7002

<Variant Name>

<Variant Name>

<Variant Name>

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

IPPLP-TH

IPPLP-TH

IPPLP-TH

Engineer:

+3P3VSB & GPU DISCHAR

+3P3VSB & GPU DISCHAR

+3P3VSB & GPU DISCHAR

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

71 97Friday, January 17, 2014

71 97Friday, January 17, 2014

71 97Friday, January 17, 2014

1

Rev

Rev

Rev

A00

A00

A00

Vinafix.com

5

4

3

2

1

+1P5V_DUAL / Max:28A / TDC:19.6A

+12VSA

Fsw = 300kHz
Iin = 4.47A
Delta I = 5.34A
ripple = 38mV
OCP = 30A
Eff=86%
H/S=1.13W
L/S =1.65W

+1P5V_DUAL

12

NI

+

PCE419
560UF/6.3V

8mohm 4.7A

GND

+1P5V_DUAL & +VTT_DDR

+1P5V_DUAL & +VTT_DDR

+1P5V_DUAL & +VTT_DDR

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

72 97Friday, January 17, 2014

72 97Friday, January 17, 2014

72 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

12

GND

12

GND

NI

PC474

2.2PF/50V

NPO/+/-0.25PF

1 2

I

PR342

2.2

mx_r0805

1 2

I

PR158
0

mx_r0805

1 2

1 2

I

PC181
10UF/6.3V

X5R/+/-20%
mx_c0603

I

PC361

0.22UF/16V

X7R/+/-10%

3

I

PR344
0

mx_r0805

+1P5V_DUAL

12

PC9503

0.1UF/25V

I
X7R/+/-10%

12

GND

12

NI

PC183
10UF/6.3V

X5R/+/-20%
mx_c0603

GND

GND

JP1

1 2

SHORTPIN_RECT

NOBOM

PR347

8.2KOHM

1%
I

GND

12

PR343

8.2KOHM

1%
I

I

PQ527
SM3116NAUC-TRG

1

12

NI

PC494

1000PF/50V

X7R/+/-10%

1

G

12

NI

PC104
1000PF/50V

X7R/+/-10%

I

PQ528
SM3116NAUC-TRG

23

2

D

S

3

GND

12

NI

PC495

1000PF/50V

X7R/+/-10%

NOBOM

PJP511
SHORTPIN

12

GND

12

I

PR345
1

mx_r0805

+1P5V_DUAL_SN_D

12

I

PC355
4700PF/50V

X7R/+/-10%

I

PC640575

NI

PC640574
10UF/25V

X7R 10%
mx_c0805_small

GND

1

1

G

1

1

G

GNDGND

23

2

D

S

3

I

PQ525
SM3119NAUC-TRG

23

2

D

S

3

12

I

PC329
10UF/25V

X7R 10%
mx_c0805_small

GND

GND

+VTT_DDR/Imax=1.1A/TDC=0.77A

+VTT_DDR

12

I

12

PC558
10UF/6.3V

X5R/+/-20%
mx_c0603

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

12

NI

PC356
680PF/50V

X7R 10%

12

GND

12

I

+

PCE101
270UF/16V

GND

I

PL9

0.8UH/31A

12

100PF/50V

NPO/+/-5%

I

PC556
10UF/6.3V

X5R/+/-20%
mx_c0603

IPPLP-TH

IPPLP-TH

IPPLP-TH

I

PC360
10UF/6.3V

X5R 10%
mx_c0805

21

GND

12

12

+

GND

NOBOM

PJP510
SHORTPIN

GND

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

1

I

PCE28
560UF/6.3V

8mohm 4.7A

12

+5V_DUAL

12

I

PC347

D D

+5V_DUAL +5V

12

1 2

SLP_S3#[22,44,50,67,74]

C C

B B

SLP_S4#[22,44,50,68]

NI

PR337

NI

PR339

1 2

+1P5V_DUAL_PG[69]

1K

1K

I

PR59

100KOHM

1%

+5V_DUAL

12

12

GND

I

PR340
10KOhm

1%

GND

12

I

PC349

0.1UF/16V

X7R 10%

12

I

PR55
100K

1%

12

100KOHM

GND

10UF/6.3V

X5R 10%
mx_c0805_small

GND

12

PR335

NI

PR222

10KOhm

10K

+1P5V_DUAL_S3

12

PR338

I

PC348

0.1UF/16V

I

X7R 10%

1%

GND

+1P5V_DUAL_S5

+5V_DUAL

12

NI

PR341
10K

+1P5V_DUAL_MODE

+1P5V_DUAL_TRIP

12

I

PR111
110KOHM

1%

GNDGND

+1P5V_DUAL_VREF

I

1%

PU22

12

V5IN

15

SW

VTT

+1P5V_DUAL_BST_D

14

+1P5V_DUAL_HG_D

13

+1P5V_DUAL_PHASE

11

+1P5V_DUAL_LG_D

10

GND

9

+1P5V_VDDQSNS

2

3

VBST

DRVH

17

S3

16

S5

DRVL

PGND

20

PGOOD

19

MODE

18

TRIP

6

VREF

VDDQSNS

VLDOIN

Vout=1.8*51.1/(51.1+10)=1.505V

1

4

5

+VTT_SENSE

+VTT_VTTREF

VTTSNS

1 2

PR57 10KOhmI

12

I

PC62

0.1UF/16V

X7R 10%

A A

5

1%

12

GND

I

PR58

53.6KOHM

1%

GNDGND

+1P5V_DUAL_REFIN

12

I

PC64

0.01UF/25V

X7R/+/-10%

GND

8

REFIN

7

GND1

21

GND2

22

GND3

23

GND4

24

GND5

25

GND6

TPS51216RUKR

I

4

VTTGND

VTTREF

Vinafix.com

5

D D

C C

4

3

2

1

B B

A A

<Core Design>

<Core Design>

<Core Design>

PEGATRON DT-MB RESTRICTED SECRET

XXXXXX

XXXXXX

XXXXXX

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

IPPLP-TH

IPPLP-TH

IPPLP-TH

Engineer:

1

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

73 97Friday, January 17, 2014

73 97Friday, January 17, 2014

73 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Vinafix.com

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S

S

S

4

3

2

1

MAIN POWER DISCHARGE

+5V+12V_HDD

+3P3V_WLAN
Imax=2A /TDC=1.4A

D D

1

C C

SLP_WLAN#[22] KEY_A_PWR [22]

1

G

+5VA

I

R37654
10KOhm

1%

1 2

32

3

D

S

2

GND GND

Q9310
2N7002

I

Q9311

2N7002

Vdroop: 1.4A*65mohm=91mV >3.3*0.95

R37653

1 2

20KOhm

1%
I

32

3

D

1

1

G

S

2

I

GND

12

C941013
1UF/6.3V

X5R 10%

+3P3VA

2

S

1

G

D

3

65mohm/Id=2A/Vth=1V
Id=-4A/Pd=1.38W
I

NI

12

NI

PC640583

0.1UF/6.3V

X7R 10%

GND

PQ109
AP2307GN

R4714

120Ohm

I

+3P3VA

I

12

R65

100KOHM

+3V_WLAN

21

SLP_S3#[22,44,50,67,72]

1

1%

32

3

D

12

I

PQ11

1

2N7002

G

S

2

GND

GND

12

NI

R60369
330Ohm

+12V_DISCH_A

12

NI

R60370
330Ohm

+12V_DISCHR_A

32

3

D

NI

PQ12

1

1

2N7002

G

S

2

GND GND GND

MAINPOWER_DISCH_G

NI

PC640586

0.1UF/6.3V

X7R 10%

1

1

12

32

3

D

G

2

NI

R60368
330Ohm

+5V_DISCH_A

NI

PQ22
2N7002

S

1

+3P3V

3

1

G

2

+3P3V_EN[68]

12

NI

R60367
330Ohm

+3P3V_DISCH_A

32

D

NI

PQ17
2N7002

S

32

3

D

I

PQ9509

1

1

2N7002

G

S

2

GND

+3P3V_mSATA
Imax=2.5A/TDC=1.75A

Vdroop: 1.75A*65mohm=113mV

B B

12

PR60234

8.2KOHM

1%

SMSC_GP124[44]

1 2

PR39

Power_OK[63,67]

A A

5

4

NI

0 Ohm

+3P3V_mSATA_GATE

12

GND

NI

PC35

4.7UF/6.3V

X5R 10%
mx_c0603_small

3

NI

32

3

D

PQ19

1

1

2N7002

G

S

2

NI

GND

1 2

PR60242 0Ohm 5%NOBOM

NI

PC30

0.1UF/6.3V

MLCC/+/-10%

GND

1

12

+3P3VA+5VA

2

S

PQ110
AP2307GN

G

D

3

65mohm/Id=2A/Vth=1V
Id=-4A/Pd=1.38W
NI

120Ohm

2

R60371

NI

+3P3V_MSATA

21

12

NI

PC640584

0.1UF/6.3V

X7R 10%

GND

<Core Design>

<Core Design>

<Core Design>

PEGATRON DT-MB RESTRICTED SECRET

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

IPPLP-TH

IPPLP-TH

IPPLP-TH

Engineer:

1

+3P3V_WLAN & +3P3V_M

+3P3V_WLAN & +3P3V_M

+3P3V_WLAN & +3P3V_M

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

74 97Friday, January 17, 2014

74 97Friday, January 17, 2014

74 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

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D D

C C

4

3

2

1

B B

A A

PEGATRON DT-MB RESTRICTED SECRET

XXXXXX

XXXXXX

XXXXXX

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

IPPLP-TH

IPPLP-TH

IPPLP-TH

Engineer:

1

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

75 97Friday, January 17, 2014

75 97Friday, January 17, 2014

75 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Vinafix.com

5

4

3

2

1

INTEL CPU XDP DEBUG PORT

D D

+1V_CPUIOOUT

12

NI

HCB2

0.1UF/16V

CPU_CFG[0..15][11]

H_PREQ#[11]

C C

CPU_CFG0
CPU_CFG1
CPU_CFG2
CPU_CFG3

CPU_CFG4
CPU_CFG5
CPU_CFG6
CPU_CFG7

NOTE:

CK_100M_CPUXDP[21]
CK_100M_CPUXDP#[21]

H_PRDY#[11]

HSW_XDP_MBP0[11]
HSW_XDP_MBP1[11]

1 2

HR95 0

NI

1 2

HR97 0

NI

GND

CPU_ITPCLK_HOOK4
CPU_ITPCLK#_HOOK5

Please close to each other to reduse stub.

SMB_DATA_RESUME[15,16,22,28,29,44,59,60,77]
SMB_CLK_RESUME[15,16,22,28,29,44,59,60,77]

B B

CPU_CFG8
CPU_CFG9
CPU_CFG10
CPU_CFG11

CPU_CFG12
CPU_CFG13
CPU_CFG14
CPU_CFG15

A A

5

HSW_PCUSTB_DP0[11]
HSW_PCUSTB_DN0[11]

HSW_PCUSTB_DP1[11]
HSW_PCUSTB_DN1[11]

4

XDP1

43

VCC_OBS_AB

44

VCC_OBS_CD

3

OBSFN_A0

5

OBSFN_A1

9

OBSDATA_A0

11

OBSDATA_A1

15

OBSDATA_A2

17

OBSDATA_A3

21

OBSFN_B0

23

OBSFN_B1

27

OBSDATA_B0

29

OBSDATA_B1

33

OBSDATA_B2

35

OBSDATA_B3

40

ITPCLK/HOOK4

42

ITPCLK#/HOOK5

51

SDA

53

SCL

4

OBSFN_C0

6

OBSFN_C1

10

OBSDATA_C0

12

OBSDATA_C1

16

OBSDATA_C2

18

OBSDATA_C3

22

OBSFN_D0

24

OBSFN_D1

28

OBSDATA_D0

30

OBSDATA_D1

34

OBSDATA_D2

36

OBSDATA_D3

BtoB_CON_60P

PROTO

3

TCK1
TCK0

TDO

TRSTn

TMS

HOOK0

HOOK1
HOOK2
HOOK3

HOOK6/RESET#

HOOK7/DBR#

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8

GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18

NP_NC1
NP_NC2

TDI

NOTE:

Place near XDP
connector

55
57
52
54
56
58

39

41

CPUXDP_HOOK1

45
47

CPUXDP_HOOK3

46

PLTRST_CPU#_HOOK6

48

1
2
7
8
13
14
19
20
25
26
31
32
37
38
49
50
59
60
61
62

GND

+1P05V_PCH

12

PROTO

HR91
51

12

NI

HR92
820

1%

GND

XDP_CPUPWRGD#_R

12

NI

HR94
1K

GND

NOTE:

TBD. PDG and DPDG is 1KΩ
Follow PDG 0.9 is 1KΩ

12

NI

HC8
470PF/50V

GND

1

PT156

NOBOM
NOBOM
NOBOM
NOBOM

PT157
PT158
PT159

2

1
1
1

PROTO

12

HR931K1%

mx_r0402_small

PRIVACY_MSR_EN_N [11]

GND

TCK [11]
TDO [11]
TRST# [11]
TDI [11]
TMS [11]

XDP_CPUPWRGD# [11]

HR96 3.3KOHMPROTO 1%

PROTO

<Core Design>

<Core Design>

<Core Design>

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

12

1 2

HR98 0

Engineer:

Engineer:

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

PWRBTN# [22,44,50,55,77]
XDP_PWR_DEBUG [11]
VRM_PWRGD [22,44,64]
XDP_PLTRST_CPU# [11]
SYS_RESET# [11,22,50,77]

CPU XDP DEBUG

CPU XDP DEBUG

CPU XDP DEBUG

Title :

Title :

Title :

1

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

76 97Friday, January 17, 2014

76 97Friday, January 17, 2014

76 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Vinafix.com

5

4

3

2

1

+3P3VSB

D D

+3P3VSB

C C

B B

A A

OC0#[19,33]
OC1#[19,34]
OC2#[19,35]

OC3#[19]

OC4#[19,36]

OC5#[19]
CONFIG_2[19,29]
CONFIG_3[19,29]

+1P05V_PCH

PCHXDP_ITPCLK/HOOK4

SMB_DATA_RESUME,28,29,44,59,60,76]
SMB_CLK_RESUME,28,29,44,59,60,76]

SR154 0 Ohm

PROTO

SR155 0 Ohm

PROTO

SR161 0 Ohm

PROTO

SR201 0 Ohm

PROTO

SR622 0 Ohm

PROTO

SR623 0 Ohm

PROTO

SR624 0 Ohm

PROTO

SR625 0 Ohm

PROTO

INTEL PCH XDP DEBUG PORT

XDP2

43

VCC_OBS_AB

44

12

GND

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

NI

SCB76

0.1UF/16V

HSW_STRAP[11,22]
CONFIG_0[20,29]
BRD_ID0[20]
OBSDATA_C1[20,50]
OBSDATA_C2[20]
OBSDATA_C3[20]

OBSDATA_D0[20]
OBSDATA_D1[20]
OBSDATA_D2[22]
OBSDATA_D3[22]

OBSDATA_A0
OBSDATA_A1
OBSDATA_A2
OBSDATA_A3

OBSDATA_B0
OBSDATA_B1
OBSDATA_B2
OBSDATA_B3

VCC_OBS_CD

3

OBSFN_A0

5

OBSFN_A1

9

OBSDATA_A0

11

OBSDATA_A1

15

OBSDATA_A2

17

OBSDATA_A3

21

OBSFN_B0

23

OBSFN_B1

27

OBSDATA_B0

29

OBSDATA_B1

33

OBSDATA_B2

35

OBSDATA_B3

40

ITPCLK/HOOK4

42

ITPCLK#/HOOK5

51

SDA

53

SCL

4

OBSFN_C0

6

OBSFN_C1

10

OBSDATA_C0

12

OBSDATA_C1

16

OBSDATA_C2

18

OBSDATA_C3

22

OBSFN_D0

24

OBSFN_D1

28

OBSDATA_D0

30

OBSDATA_D1

34

OBSDATA_D2

36

OBSDATA_D3

BtoB_CON_60P

PROTO

HOOK6/RESET#

HOOK7/DBR#

TCK1
TCK0

TDO

TRSTn

TMS

HOOK0

HOOK1
HOOK2
HOOK3

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8

GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18

NP_NC1
NP_NC2

55
57
52
54
56

TDI

58

39

41
45
47
46
48

1
2
7
8
13
14
19
20
25
26
31
32
37
38
49
50
59
60
61
62

PCH_JTAG_RST_R

PCHXDP_HOOK0_PWRGD

PCHXDP_HOOK6/RESET#

PCHXDP_GND18

NI

SR168
0

GND

3P3VSB_CPUXDP_JTAG

12

12

mx_r0402_small

12

SR1621K 1%

12

12

12

I

NI

SR151

SCB77

51

0.1UF/16V

GND GND GND GND

RSMRST# [22,44,77]

PWRBTN# [22,44,50,55,76,77]

PROTO

1

PT160

NOBOM
NOBOM
NOBOM
NOBOM

PT161
PT163
PT162

1
1
1

SR150 0

NI

+3P3VSB

12

NI

SR160
1K

PROTO

12

NI

SR163
0

GND

SYS_RESET# [11,22,50,76] RSMRST# [22,44,77]

12

GND

12

SR146
200

SR152
100 Ohm

I
1%

GND

12

I

SR147
200

SR158
100 Ohm

I
1%

I

SR165 0 OhmNI
SR166 1K 1%
SR167 0 OhmNI

NOTE:

Place strap resistors of TDO near to XDP connector,
and TDI and TMS near to CPU.

+3P3VSB

12

I

SR157
200

12

SR153
100 Ohm

12
12
12

I
1%

mx_r0402_small

GND

12

12

I

SR148
20KOhm

1%

I

SR159
10KOhm

1%

PCH_JTAG_TCK [22]
PCH_JTAG_TDO [22]
PCH_JTAG_RST [22]
PCH_JTAG_TDI [22]
PCH_JTAG_TMS [22]

12

NI

SCB78
1UF/10V

mx_c0603

GNDGND

PWRBTN# [22,44,50,55,76,77]
PCH_DPWROK [22,44]

<Core Design>

<Core Design>

<Core Design>

PEGATRON DT-MB RESTRICTED SECRET

PCH XDP DEBUG

PCH XDP DEBUG

PCH XDP DEBUG

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

IPPLP-TH

IPPLP-TH

IPPLP-TH

Engineer:

1

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

77 97Friday, January 17, 2014

77 97Friday, January 17, 2014

77 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Vinafix.com

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D D

C C

4

3

2

1

B B

A A

PEGATRON DT-MB RESTRICTED SECRET

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

1

XXXXXX

XXXXXX

XXXXXX

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

78 97Friday, January 17, 2014

78 97Friday, January 17, 2014

78 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Vinafix.com

5

PEG_TXP[0..7][10]

PEG_TXN[0..7]0]

1 2

1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2

1 2

1 2
1 2

12

I_GPU

R109
1K1%

mx_r0402_small

32

3

D

I_GPU

PQ597
2N7002

S

2

GND

X5R/+/-10%

X5R/+/-10%
X5R/+/-10%

X5R/+/-10%
X5R/+/-10%

X5R/+/-10%
X5R/+/-10%

X5R/+/-10%
X5R/+/-10%

X5R/+/-10%
X5R/+/-10%

X5R/+/-10%
X5R/+/-10%

X5R/+/-10%
X5R/+/-10%

X5R/+/-10%

GPU_RST_S#

PCIE_TXP0
PCIE_TXN0

PCIE_TXP1
PCIE_TXN1

PCIE_TXP2
PCIE_TXN2

PCIE_TXP3
PCIE_TXN3

PCIE_TXP4
PCIE_TXN4

PCIE_TXP5
PCIE_TXN5

PCIE_TXP6

PCIE_TXN6

PCIE_TXP7
PCIE_TXN7

I_GPU 1 2

PEG_TXP0
PEG_TXN0

I_GPU

PEG_TXP1

D D

C C

B B

GPU_RST#[44]

GPURST_GPIO8

I_GPU
I_GPU 1 2

PEG_TXN1

PEG_TXP2

I_GPU

PEG_TXN2

I_GPU

PEG_TXP3

I_GPU

PEG_TXN3

I_GPU

PEG_TXP4

I_GPU

PEG_TXN4

I_GPU

I_GPU 1 2

PEG_TXP5
PEG_TXN5

I_GPU

PEG_TXP6

I_GPU
I_GPU 1 2

PEG_TXN6

PEG_TXP7

I_GPU

PEG_TXN7

I_GPU

+3P3VSB

12

I_GPU

R114
20K

1%

32

3

D

I_GPU

1

D9

1

2N7002

G

S

2

C113 0.22UF/6.3V
C103 0.22UF/6.3V

C104 0.22UF/6.3V
C105 0.22UF/6.3V

C107 0.22UF/6.3V
C109 0.22UF/6.3V

C111 0.22UF/6.3V
C117 0.22UF/6.3V

C112 0.22UF/6.3V
C120 0.22UF/6.3V

C122 0.22UF/6.3V
C124 0.22UF/6.3V

C126 0.22UF/6.3V
C128 0.22UF/6.3V

C130 0.22UF/6.3V
C132 0.22UF/6.3V

+3P3V_GPU

1

1

G

AA38

Y37

Y35

W36

W38

V37

V35
U36

U38

T37

T35

R36

R38
P37

P35
N36

N38
M37

M35

L36

L38

K37

K35

J36

J38

H37

H35
G36

G38

F37

F35

E37

4

G1A

PART 1 0F 9

PCIE_RX0P
PCIE_RX0N

PCIE_RX1P
PCIE_RX1N

PCIE_RX2P
PCIE_RX2N

PCIE_RX3P
PCIE_RX3N

PCIE_RX4P
PCIE_RX4N

PCIE_RX5P
PCIE_RX5N

PCIE_RX6P
PCIE_RX6N

PCIE_RX7P
PCIE_RX7N

NC_PCIE_RX8P
NC_PCIE_RX8N

NC_PCIE_RX9P
NC_PCIE_RX9N

NC_PCIE_RX10P
NC_PCIE_RX10N

NC_PCIE_RX11P
NC_PCIE_RX11N

NC_PCIE_RX12P
NC_PCIE_RX12N

NC_PCIE_RX13P
NC_PCIE_RX13N

NC_PCIE_RX14P
NC_PCIE_RX14N

NC_PCIE_RX15P
NC_PCIE_RX15N

PCI EXPRESS INTERFACE

PCIE_TX0P

PCIE_TX0N

PCIE_TX1P

PCIE_TX1N

PCIE_TX2P

PCIE_TX2N

PCIE_TX3P

PCIE_TX3N

PCIE_TX4P

PCIE_TX4N

PCIE_TX5P

PCIE_TX5N

PCIE_TX6P

PCIE_TX6N

PCIE_TX7P

PCIE_TX7N

NC_PCIE_TX8P
NC_PCIE_TX8N

NC_PCIE_TX9P
NC_PCIE_TX9N

NC_PCIE_TX10P
NC_PCIE_TX10N

NC_PCIE_TX11P
NC_PCIE_TX11N

NC_PCIE_TX12P
NC_PCIE_TX12N

NC_PCIE_TX13P
NC_PCIE_TX13N

NC_PCIE_TX14P
NC_PCIE_TX14N

NC_PCIE_TX15P
NC_PCIE_TX15N

Y33
Y32

W33
W32

U33
U32

U30
U29

T33
T32

T30
T29

P33
P32

P30
P29

N33
N32

N30
N29

L33
L32

L30
L29

K33
K32

J33
J32

K30
K29

H33
H32

3

1 2

1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2

1 2

1 2
1 2

X5R/+/-10%

X5R/+/-10%
X5R/+/-10%

X5R/+/-10%
X5R/+/-10%

X5R/+/-10%
X5R/+/-10%

X5R/+/-10%
X5R/+/-10%

X5R/+/-10%
X5R/+/-10%

X5R/+/-10%
X5R/+/-10%

X5R/+/-10%
X5R/+/-10%

X5R/+/-10%

I_GPU 1 2
I_GPU

PCIE_RXP1

I_GPU
I_GPU 1 2

PCIE_RXN1

PCIE_RXP2

I_GPU

PCIE_RXN2

I_GPU

PCIE_RXP3

I_GPU

PCIE_RXN3

I_GPU

PCIE_RXP4

I_GPU

PCIE_RXN4

I_GPU

I_GPU 1 2

PCIE_RXP5
PCIE_RXN5

I_GPU

PCIE_RXP6

I_GPU
I_GPU 1 2

PCIE_RXN6

PCIE_RXP7

I_GPU

PCIE_RXN7 PEG_RXN7

I_GPU

C102 0.22UF/6.3V

PCIE_RXP0

PCIE_RXN0

C114 0.22UF/6.3V

C115 0.22UF/6.3V
C106 0.22UF/6.3V

C108 0.22UF/6.3V
C110 0.22UF/6.3V

C116 0.22UF/6.3V
C118 0.22UF/6.3V

C119 0.22UF/6.3V
C121 0.22UF/6.3V

C123 0.22UF/6.3V
C125 0.22UF/6.3V

C127 0.22UF/6.3V
C129 0.22UF/6.3V

C131 0.22UF/6.3V
C133 0.22UF/6.3V

PEG_RXP0
PEG_RXN0

PEG_RXP1
PEG_RXN1

PEG_RXP2
PEG_RXN2

PEG_RXP3
PEG_RXN3

PEG_RXP4
PEG_RXN4

PEG_RXP5
PEG_RXN5

PEG_RXP6
PEG_RXN6

PEG_RXP7

2

PEG_RXP[0..7] [10]
PEG_RXN[0..7] [10]

1

CLOCK

NI

C134
15PF/50V

AB35
AA36

AH16

AA30

PCIE_REFCLKP
PCIE_REFCLKN

TEST_PG

PERSTB

216-0842006

I_GPU

4

CALIBRATION

PCIE_CALR_TX

PCIE_CALR_RX

Y30
Y29

R1121K1%

R1101.69KOHM I_GPU

1 2

1 2

mx_r0402_small

3

I_GPU

+0P95V

+0P95V

<Variant Name>

<Variant Name>

<Variant Name>

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

B

B

B

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

IPPLP-TH

IPPLP-TH

IPPLP-TH

Engineer:

Caspian_PCIE

Caspian_PCIE

Caspian_PCIE

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

1

Rev

Rev

Rev

A00

A00

79 97Friday, January 17, 2014

79 97Friday, January 17, 2014

79 97Friday, January 17, 2014

A00

GPU_CLKOUT_PEG_A[21]

GPU_CLKOUT_PEG_A#[21]

R111

GND

A A

5

1 2

1%

I_GPU

1K

mx_r0402_small

GPU_RST_S#

12

GND

Vinafix.com

5

THE PINS WITH TEST POINTS
ARE REQUIRED TO BE ACCESSIBLE
FOR DEBUG
ACCESS TO AMD DEBUG PORT IS MANDATORY ON INITIAL PROTOTYPE DESIGNS

D D

+3P3V_GPU

12

C152
1UF/6.3V

X5R/+/-10%

I_GPU

H_THMTRIP#[11,20]

12

C153

0.1UF/6.3V

I_GPU

GND

C C

B B

+1P8V_MXM

L24

21

120Ohm/100Mhz

I_GPU

On-die thermal sensor power.
TSVDD : 1.8V @ 8mA

12

C151

10UF/6.3V

I_GPU

3 4
5 6
1 2
7 8

32

3

D

Q15

1

1

2N7002

G

12

S

2

I_GPU

GND

GND

TSVDD

GND

R155 10KOhmI_GPU 1%

+3P3V_GPU

R115 10KOhm
R116 10KOhm

GPU_CTF

I_GPU

R129
10KOhm

1%

+1P8V_MXM

R149 1K 1%

GND

NOBOM
NOBOM
NOBOM
NOBOM
NOBOM

1 2
1 2

RN31B8.2KOhmI_GPU
RN31C8.2KOhmI_GPU
RN31A8.2KOhmI_GPU
RN31D8.2KOhmI_GPU

12

12

GND

1 2

mx_r0402_small

12

NI

I_GPU 1%

I_GPU

I_GPU

I_GPU

4

S_SML1_GPU_CLK_R
S_SML1_GPU_DATA_R

GPIO_17

NVDD_VID0[93]

NVDD_VID1[93]
NVDD_VID2[93]

NVDD_VID3[93]

NVDD_VID4[93]
NVDD_VID5[93]

R140
499 Ohm

GPU_VREFG

12

R145
249OHM

1

PT4

1

PT5

1

PT6

1

PT7

1

PT8

REMOTE1+[44]
REMOTE1-[44]

TS_FDO

1%

GPIO5

C144

0.1UF/6.3V

I_GPU

H2SYNC
V2SYNC

GPIO5

GPIO_17

TESTEN

JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO

G1B

AD29

GENLK_CLK

AC29

GENLK_VSYNC

AJ21

SWAPLOCKA

AK21

SWAPLOCKB

AR8

NC_DVPCNTL_MVP_0

AU8

NC_DVPCNTL_MVP_1

AP8

DBG_CNTL0

AW8

NC_DVPCNTL_1

AR3

NC_DVPCNTL_2

AR1

NC_DVPCLK

AU1

DBG_DATA0

AU3

DBG_DATA1

AW3

DBG_DATA3_1

AP6

DBG_DATA3_2

AW5

DBG_DATA4

AU5

DBG_DATA5

AR6

DBG_DATA6

AW6

DBG_DATA7

AU6

DBG_DATA8

AT7

DBG_DATA9

AV7

DBG_DATA10

AN7

DBG_DATA11

AV9

DBG_DATA12

AT9

DBG_DATA13

AR10

DBG_DATA14

AW10

DBG_DATA15

AU10

DBG_DATA16

AP10

DBG_DATA17

AV11

DBG_DATA18

AT11

DBG_DATA19

AR12

DBG_DATA20

AW12

DBG_DATA21

AU12

DBG_DATA22

AP12

DBG_DATA23

AJ23

SMBCLK

AH23

SMBDATA

AK26

SCL

AJ26

SDA

GENERAL PURPOSE I/O

AH20

GPIO_0

AH18

GPIO_1

AN16

GPIO_2

AH17

GPIO_5_AC_BATT

AJ17

GPIO_6

AK17

GPIO_7_BLON

AJ13

GPIO_8_ROMSO

AH15

GPIO_9_ROMSI

AJ16

GPIO_10_ROMSCK

AK16

GPIO_11

AL16

GPIO_12

AM16

GPIO_13

AM14

GPIO_14_HPD2

AM13

GPIO_15_PWRCNTL_0

AK14

GPIO_16

AG30

GPIO_17_THERMAL_INT

AN14

GPIO_18

AM17

GPIO_19_CTF

AL13

GPIO_20_PWRCNTL_1

AJ14

GPIO_21

AK13

GPIO_22_ROMCSB

AN13

CLKREQB

AG32

GPIO_29

AG33

GPIO_30

AJ19

GENERICA

AK19

GENERICB

AJ20

GENERICC

AK20

GENERICD

AJ24

GENERICE

AH26

GENERICF

AH24

GENERICG

AC30

CEC_1

AK24

HPD1

AH13

DBG_VREFG

AL21

PX_EN

AD28

TESTEN

AM23

JTAG_TRSTB

AN23

JTAG_TDI

AK23

JTAG_TCK

AL24

JTAG_TMS

AM24

JTAG_TDO

AF29

DPLUS

AG29

DMINUS

AK32

GPIO_28_FDO

AL31

TS_A

AJ32

TSVDD

AJ33

TSVSS

216-0842006

MUTI GFX

THERMAL

3

PART 2 0F 9

DPA

DPB

DPC

DPD

SMBus

I2C

DAC1

BACO

DDC/AUX

DEBUG

NC_TXCAP_DPA3P

NC_TXCAM_DPA3N

NC_TX0P_DPA2P
NC_TX0M_DPA2N

NC_TX1P_DPA1P
NC_TX1M_DPA1N

NC_TX2P_DPA0P
NC_TX2M_DPA0N

NC_TXCBP_DPB3P

NC_TXCBM_DPB3N

NC_TX3P_DPB2P
NC_TX3M_DPB2N

NC_TX4P_DPB1P
NC_TX4M_DPB1N

NC_TX5P_DPB0P
NC_TX5M_DPB0N

NC_TXCCP_DPC3P
NC_TXCCM_DPC3N

NC_TX0P_DPC2P
NC_TX0M_DPC2N

NC_TX1P_DPC1P
NC_TX1M_DPC1N

NC_TX2P_DPC0P
NC_TX2M_DPC0N

NC_TXCDP_DPD3P
NC_TXCDM_DPD3N

NC_TX3P_DPD2P
NC_TX3M_DPD2N

NC_TX4P_DPD1P
NC_TX4M_DPD1N

NC_TX5P_DPD0P
NC_TX5M_DPD0N

AVSSN2

AVSSN1

AVSSN3

VDD1DI
VSS1DI

NC_SVI2_1
NC_SVI2_2
NC_SVI2_3

MLPS

DDC1CLK

DDC1DATA

DDC2CLK

DDC2DATA

NC_DDCCLK_AUX3P

NC_DDCDATA_AUX3N

NC_DDCCLK_AUX4P

NC_DDCDATA_AUX4N

NC_DDCCLK_AUX5P

NC_DDCDATA_AUX5N

NC_DDCCLK_AUX6P

NC_DDCDATA_AUX6N

DDCVGACLK

DDCVGADATA

HSYNC
VSYNC

AVSSQ

AUX1P
AUX1N

AUX2P
AUX2N

R

G

B

RSET
AVDD

NC31
NC30

NC8
NC7
NC1

NC10

NC6

PS_0

PS_1

PS_2

PS_3

AU24
AV23

AT25
AR24

AU26
AV25

AT27
AR26

AR30
AT29

AV31
AU30

AR32
AT31

AT33
AU32

AU14
AV13

AT15
AR14

AU16
AV15

AT17
AR16

AU20
AT19

AT21
AR20

AU22
AV21

AT23
AR22

AD39
AD37

AE36
AD35

AF37
AE38

AC36
AC38

AB34

GPU_RSET

AD34
AE34

GND

AC33
AC34

V13
U13
AF33
AF32
AA29
AG21

12

AC32

C231

AC31

0.1UF/6.3V

AD30

I_GPU

AD32

GND GND

AM34

PS_0

AD31

PS_1

AG31

PS_2

AD33

PS_3

AM26
AN26

AM27
AL27

AM19
AL19

AN20
AM20

AL30
AM30

AL29
AM29

AN21
AM21

AK30
AK29

AJ30

GPU_DDCVGACLK [14]

AJ31

GPU_DDCVGADATA [14]

1 2

R117 10KOhmI_GPU 1%

1 2

R118 10KOhmI_GPU 1%

GND

GND

GND

GPU_HSYNC [14]
GPU_VSYNC [14]

1 2

R124 499 Ohm

I_GPU

12

C229

GND

0.1UF/6.3V

I_GPU

GND GND

PS_0

PS_1

GND
GND

1 2

+1P8V_MXM

+1P8V_MXM

GND GND GND GND

12

C143
1UF/6.3V

X5R/+/-10%

I_GPU

12

C230

1UF/6.3V

X5R/+/-10%

I_GPU

VDDC_CT

12

R137

8.45KOhm

I_GPU

12

R146
2KOhm

I_GPU

12

R150

8.45KOhm

I_GPU

12

12

R153

C299

2KOhm

0.082UF/16V

I_GPU

NI

GND GND

GND

R121
150 Ohm

PS_2

PS_3

NI

VDDC_CT

VDDC_CTVDDC_CT

12

R299

8.45KOhm

I_GPU

12

R147

4.75KOHM

I_GPU

12

R151

8.45KOhm

I_GPU

12

R154

4.75KOHM

I_GPU

R123

R122

150 Ohm

150 Ohm

NI

NI

1 2

1 2

12

C146

0.082UF/16V

NI

GNDGNDGND

0:HYNIX (NC , 4.75K)
1:MICRON (8.45K , 2K)
2:SAMSUNG (4.53K , 2K)

GPU_DEBUG_VGA_RED [14]

GPU_DEBUG_VGA_GRN [14]

GPU_DEBUG_VGA_BLU [14]

2

1

REMOTE1+

12

NOTE:

The current numbers shown here are for reference only

For actual current, check with databook

A A

5

REMOTE1-

NI

C154
100PF/25V

<Variant Name>

<Variant Name>

<Variant Name>

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

D

D

D

Date: Sheet of

Date: Sheet of

4

3

2

Date: Sheet of

1

IPPLP-TH

IPPLP-TH

IPPLP-TH

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

Caspian_IO1

Caspian_IO1

Caspian_IO1

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

80 97Friday, January 17, 2014

80 97Friday, January 17, 2014

80 97Friday, January 17, 2014

Rev

Rev

Rev

A00

A00

A00

Vinafix.com

5

4

3

2

1

COMPONENTS SHOWN ARE EXAMPLES ONLY
AND NOT NECESSARILY QUALIFIED

D D

For Thames/Whistler/Seymour

a dedicated BEAD is required

for each DPAB_VDD18, DPCD_VDD18, DPEF_VDD18

DP/TMDS/LVDS Transmitter Power

DP mode: 1.8V@188mA per port
HDMI mode: 1.8V@237mA per port

C C

B B

+1P8V_MXM

C158

I_GPU

12

C159
1UF/6.3V

X5R/+/-10%

I_GPU

12

12

10UF/6.3V

GND GND GND

NOTE:

The current numbers shown here are for reference only

For actual current, check with databook

C160

0.1UF/6.3V

I_GPU

GND

R156

1 2

150 Ohm

I_GPU

GPU_DP_CALR

AN24
AP24
AP25
AP26
AU28
AV29

AP20
AP21
AP22
AP23
AU18
AV19

AH34

AJ34

AF34
AG34
AM37

AL38
AM32

AW28

AW18

AM39

G1H

NC11
NC19
NC20
NC21
NC24
NC26

NC15
NC16
NC17
NC18
NC23
NC25

DP_VDDR3
DP_VDDR4
DP_VDDR1
DP_VDDR2
DP_VDDR7
DP_VDDR5
DP_VDDR6

CALIBRATION

NC_DPAB_CALR

NC_DPCD_CALR

DP_CALR

PART 8 0F 9

DP_VDDCDP_VDDR

DP GND

For Thames/Whistler/Seymour

a dedicated BEAD is required

for each DPAB_VDD10, DPCD_VDD10, DPEF_VDD10

DP/TMDS/LVDS Transmitter Power

0.935V@222mA per port

NC12
NC22
NC13
NC14

AP31
AP32
AN33
AP33
AL33
AM33
AK33
AK34
AN31

AP13
AT13
AP14
AP15

AN27
AP27
AP28
AW24
AW26
AN29
AP29
AP30
AW30
AW32
AN17
AP16
AP17
AW14
AW16
AN19
AP18
AP19
AW20
AW22
AN34
AP39
AR39
AU37
AF39
AH39
AK39
AL34
AV27
AR28
AV17
AR18
AN38
AM35
AN32

DP_VDDC7
DP_VDDC8
DP_VDDC6
DP_VDDC9
DP_VDDC3
DP_VDDC4
DP_VDDC1
DP_VDDC2
DP_VDDC5

DP_VSSR8
DP_VSSR17
DP_VSSR18
DP_VSSR32
DP_VSSR33

DP_VSSR9
DP_VSSR19
DP_VSSR20
DP_VSSR34
DP_VSSR35

DP_VSSR6
DP_VSSR13
DP_VSSR14
DP_VSSR28
DP_VSSR29

DP_VSSR7
DP_VSSR15
DP_VSSR16
DP_VSSR30
DP_VSSR31
DP_VSSR11
DP_VSSR21
DP_VSSR24
DP_VSSR25

DP_VSSR1

DP_VSSR2

DP_VSSR3

DP_VSSR4
DP_VSSR27
DP_VSSR23
DP_VSSR26
DP_VSSR22
DP_VSSR12

DP_VSSR5
DP_VSSR10

+0P95V

12

C155

10UF/6.3V

I_GPU

GND GND GND

12

C156
1UF/6.3V

X5R/+/-10%

I_GPU

12

I_GPU

C157

0.1UF/6.3V

GND

216-0842006

A A

5

4

3

2

<Variant Name>

<Variant Name>

<Variant Name>

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

B

B

B

Date: Sheet of

Date: Sheet of

Date: Sheet of

IPPLP-TH

IPPLP-TH

IPPLP-TH

Engineer:

Caspian_DP A--D

Caspian_DP A--D

Caspian_DP A--D

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

81 97Friday, January 17, 2014

81 97Friday, January 17, 2014

81 97Friday, January 17, 2014

1

Rev

Rev

Rev

A00

A00

A00

Vinafix.com

5

G1G

PART 7 0F 9

AK27

VARY_BL

AJ27

LVDS CONTROL

D D

LVTMDP

C C

216-0842006

B B

DIGON

TXCBP_DPB3P

TXCBM_DPB3N

TX3P_DPB2P

TX3M_DPB2N

TX4P_DPB1P

TX4M_DPB1N

TX5P_DPB0P

TX5M_DPB0N

NC_TXOUT_U3P
NC_TXOUT_U3N

TXCAP_DPA3P

TXCAM_DPA3N

TX0P_DPA2P

TX0M_DPA2N

TX1P_DPA1P

TX1M_DPA1N

TX2P_DPA0P

TX2M_DPA0N

NC_TXOUT_L3P
NC_TXOUT_L3N

AK35
AL36

AJ38
AK37

AH35
AJ36

AG38
AH37

AF35
AG36

AP34
AR34

AW37
AU35

AR37
AU39

AP35
AR35

AN36
AP37

+1P8V_MXM

+0P95V

1 2

R158 10KOhmI_GPU
R157 10KOhmI_GPU 1 2

L26

21

120Ohm/100Mhz

I_GPU

L27

21

120Ohm/100Mhz

I_GPU

I_GPU

C170

10PF/50V

GND

SPLL_PVDD : 1.8V @ 75mA

12

C164

10UF/6.3V

I_GPU

XTAL OPTIONAL

R159

1 2

1MOhm
Y20

27MHZ

1 3

12

2

GNDGND

I_GPU

4

4

GND
GND

12

C165
1UF/6.3V

X5R/+/-10%

I_GPU

SPLL_VDDC : 0.935V @ 150mA

12

C167

10UF/6.3V

I_GPU

I_GPU

12

I_GPU

C171
10PF/50V

GND

12

GND

12

L25

330Ohm/100Mhz

I_GPU

C166

0.1UF/6.3V

I_GPU

C168
1UF/6.3V

X5R/+/-10%

I_GPU

XTALOUTXTALIN

21

SPLL_PVDD

SPLL_VDDC

12

C169

0.1UF/6.3V

I_GPU

GND

12

C161

10UF/6.3V

I_GPU

Engine Phase Lock Loop Power : Dedicated
analog power pin for engine PLL

Engine Phase Lock Loop Power
:Dedicated digital power pin for
engine PLL

12

X5R/+/-10%

3

C162
1UF/6.3V

I_GPU

GND

MPLL_PVDD+1P8V_MXM

12

I_GPU

C163

0.1UF/6.3V

AM10

AN9

AN10

AF30
AF31

H7
H8

G1I

MPLL_PVDD1
MPLL_PVDD2

SPLL_PVDD

SPLL_VDDC

SPLL_PVSS

NC_XTAL_PVDD
NC_XTAL_PVSS

216-0842006

PART 9 0F 9

2

AV33

AU34

AW34

AW35

AK10
AL10

XTALIN

XTALOUT

XTALIN

XTALOUT

PLLS/XTAL

XO_IN

XO_IN2

CLKTESTA
CLKTESTB

1

A A

5

4

3

2

<Variant Name>

<Variant Name>

<Variant Name>

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

B

B

B

Date: Sheet of

Date: Sheet of

Date: Sheet of

IPPLP-TH

IPPLP-TH

IPPLP-TH

Engineer:

Caspian_LVDS1

Caspian_LVDS1

Caspian_LVDS1

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

82 97Friday, January 17, 2014

82 97Friday, January 17, 2014

82 97Friday, January 17, 2014

1

Rev

Rev

Rev

A00

A00

A00

Vinafix.com

5

4

3

2

1

COMPONENTS SHOWN ARE EXAMPLES ONLYAND NOT NECESSARILY QUALIFIED

For Thames/Whistler/Seymour
NC_PCIE_VDDR and NC_BIF_VDDC should be tied with PCIE_VDDR

AA31
AA32
AA33
AA34
W30
Y31
V28
W29

PCIE_VDDR : 1.8V @ 50mA

AB37
G30

G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28

1A

N27
T27

AA15
AA17
AA20
AA22
AA24
AA27
AB16
AB18
AB21
AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18

AH22
AH27
AH28
M26
N24
R18
R21
R23
R26
T17
T20
T22
T24
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28

AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13

12

12

C193
1UF/6.3V

I_GPU

X5R/+/-10%

X5R/+/-10%

12

12

I_GPU

C941275

2.2UF/6.3V

X5R 10%

12

12

I_GPU

C941281

2.2UF/6.3V

X5R 10%

12

C212

10UF/6.3V

I_GPU

VDDCI 0.8-1.15V @ 6A

(Isolated (clean) core power for the l/O logic)

12

C222

0.1UF/6.3V

NI

12

C194
1UF/6.3V

I_GPU

X5R/+/-10%

For Thames/Whistler/Seymour
BIF_VDDC is connected to VDDC in non BACO designs
In BACO designs, switch circuits is required so that
when GPU is operating, BIF_VDDC is connected to VDDC,
while in BACO mode, BIF_VDDC is connected to +1.0V

12

I_GPU

C941274

2.2UF/6.3V

X5R 10%

12

I_GPU

C941280

2.2UF/6.3V

X5R 10%

12

C213

10UF/6.3V

I_GPU

12

C223

0.1UF/6.3V

NI

12

12

C178

C190

1UF/6.3V

1UF/6.3V

I_GPU

C196
1UF/6.3V

I_GPU

12

I_GPU

C941272

2.2UF/6.3V

X5R 10%

12

I_GPU

C941278

2.2UF/6.3V

X5R 10%

12

10UF/6.3V

I_GPU

X5R/+/-10%

GND

12

12

C197
1UF/6.3V

I_GPU

X5R/+/-10%

X5R/+/-10%

12

I_GPU

C202

2.2UF/6.3V

X5R 10%

12

I_GPU

C941277

2.2UF/6.3V

X5R 10%

12

C216

C215

10UF/6.3V

I_GPU

I_GPU

Depending on the performace requirement
VDDCI and VDDC might require seperate regulators with a merge option on PCB
or VDDCI and VDDC can share one common regulator

In both case, VDDCI plane should be seperated with VDDC plane

12

12

C225
1UF/6.3V

X5R/+/-10%

I_GPU

X5R/+/-10%

PCIE_VDDC : 0.935V @ 1.3A (GEN3.0)

12

C195
1UF/6.3V

I_GPU

X5R/+/-10%

I_GPU

C941273

2.2UF/6.3V

X5R 10%

I_GPU

C941279

2.2UF/6.3V

X5R 10%

12

C214

10UF/6.3V

I_GPU

12

C224

0.1UF/6.3V

NI

12

C191

10UF/6.3V

I_GPU

C198
1UF/6.3V

I_GPU

12

12

C226
1UF/6.3V

X5R/+/-10%

I_GPU

12

X5R/+/-10%

I_GPU

C941270

2.2UF/6.3V

X5R 10%

I_GPU

C941276

2.2UF/6.3V

X5R 10%

12

C217

10UF/6.3V

I_GPU

12

+1P8V_MXM

C199
1UF/6.3V

I_GPU

C227
1UF/6.3V

X5R/+/-10%

I_GPU

12

I_GPU

C941271

2.2UF/6.3V

X5R 10%

12

NI

C207

2.2UF/6.3V

X5R 10%

12

C218

10UF/6.3V

I_GPU

+VDDC

GND

12

C200

10UF/6.3V

I_GPU

12

C228

10UF/6.3V

I_GPU

PCIe Digital Power Supply

12

10UF/6.3V

GND

12

C203

2.2UF/6.3V

X5R 10%

12

C208

2.2UF/6.3V

X5R 10%

+0P95V

C201

I_GPU

+VDDC

NI

NI

GND

VDDC_CT

VDDR4

AG10

AG26
AG27

AG23
AG24

AG11
AG13
AG15

AG28

AD11

AF26
AF27

AF23
AF24

AD12
AF11
AF12
AF13

AF15

AF28

AH29

AC7
AF7
AJ7

AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10

K11
K13

L12
L16
L21
L23
L26

M11
N11

R11
U11

Y11

J7
J9

K8

L7

P7

U7
Y7

G1E

MEM I/O

VDDR1_1
VDDR1_2
VDDR1_3
VDDR1_4
VDDR1_5
VDDR1_6
VDDR1_7
VDDR1_8
VDDR1_9
VDDR1_10
VDDR1_11
VDDR1_12
VDDR1_13
VDDR1_14
VDDR1_15
VDDR1_16
VDDR1_17
VDDR1_18
VDDR1_19
VDDR1_20
VDDR1_21
VDDR1_22
VDDR1_23
VDDR1_24
VDDR1_25
VDDR1_26
VDDR1_27
VDDR1_28
VDDR1_29
VDDR1_30
VDDR1_31
VDDR1_32
VDDR1_33
VDDR1_34

LEVEL

TRANSLATION

VDD_CT1
VDD_CT2
VDD_CT3
VDD_CT4

I/O

VDDR3_1
VDDR3_2
VDDR3_3
VDDR3_4

DVP

VDDR4_1
VDDR4_2
VDDR4_3
VDDR4_4

VDDR4_5
VDDR4_6
VDDR4_7
VDDR4_8

216-0842006

VOLTAGE
SENESE

FB_VDDC

FB_VDDCI

FB_GND

PART 5 0F 9

NC_BIF_VDDC1
NC_BIF_VDDC2

PCIE

BACO

CORE

ISOLATED

NC32
NC33

PCIE_PVDD

PCIE_VDDC1
PCIE_VDDC2
PCIE_VDDC3
PCIE_VDDC4
PCIE_VDDC5
PCIE_VDDC6
PCIE_VDDC7
PCIE_VDDC8

PCIE_VDDC9
PCIE_VDDC10
PCIE_VDDC11
PCIE_VDDC12

BIF_VDDC1
BIF_VDDC2

VDDC1
VDDC2
VDDC3
VDDC4
VDDC5
VDDC6
VDDC7
VDDC8

VDDC9
VDDC10
VDDC11
VDDC12
VDDC13
VDDC14
VDDC15
VDDC16
VDDC17
VDDC18
VDDC19
VDDC20
VDDC21
VDDC22
VDDC23
VDDC24
VDDC25
VDDC26

VDDC27
VDDC28
VDDC29
VDDC30
VDDC31
VDDC32
VDDC33
VDDC34
VDDC35
VDDC36
VDDC37
VDDC38
VDDC39
VDDC40
VDDC41
VDDC42
VDDC43
VDDC44
VDDC45
VDDC46
VDDC47
VDDC48
VDDC49
VDDC50
VDDC51
VDDC52
VDDC53
VDDC54
VDDC55

VDDCI1
VDDCI2
VDDCI3
VDDCI4
VDDCI5
VDDCI6
VDDCI7
VDDCI8

VDDCI9
VDDCI10
VDDCI11
VDDCI12

CORE I/O

VDDCI13
VDDCI14
VDDCI15
VDDCI16
VDDCI17
VDDCI18
VDDCI19
VDDCI20
VDDCI21
VDDCI22

NC2
NC3
NC4
NC5

+1P5V_GPU

I/O power for the
memory interface.

D D

C C

B B

VDDR1 , 1.5V @ 2A, GDDR5 900MHz

+1P8V_MXM

12

NI

C180
10UF/6.3V

L28

21

120Ohm/100Mhz

I_GPU

IO power for 3.3V pin (e.g.GPIOs)

L30

21

120Ohm/100Mhz

I_GPU

Power for DVP pins (DVPDATA_[23:0],

DVPCNTL_[2:0], DVPCLK) - external TMDS

Some caps need to change to
shorter ones.

12

NI

C181
10UF/6.3V

+3P3V_GPU

VDDR3 : 3.3V @ 60mA

L29

120Ohm/100Mhz

I_GPU

VDDR4 : 1.8V @ 300mA

12

NI

C182

2.2UF/6.3V

X5R 10%

21

12

NI

C183

2.2UF/6.3V

X5R 10%

Level translation between core and I/O,
excluding memory receivers

VDDC_CT: 1.8V @250mA

12

10UF/6.3V

12

X5R/+/-10%

12

C219

10UF/6.3V

I_GPU

C204

I_GPU

C209
1UF/6.3V

I_GPU

12

GND

12

NI

C184

2.2UF/6.3V

X5R 10%

12

1UF/6.3V

X5R/+/-10%

C210
1UF/6.3V

X5R/+/-10%

I_GPU

12

C220
1UF/6.3V

X5R/+/-10%

I_GPU

C205

I_GPU

12

NI

C185

2.2UF/6.3V

X5R 10%

12

C206

0.1UF/6.3V

I_GPU

GND

12

C211

0.1UF/6.3V

I_GPU

VDDR4 for DVPDATA[0..23]

VDDR4

GND

12

C221

0.1UF/6.3V

I_GPU

GND

NOTE:

The current numbers shown here are for reference only

For actual current, check with databook

FB_VDDC[93]

FB_GND[93]

A A

<Variant Name>

<Variant Name>

<Variant Name>

Title :

Title :

Title :

Caspian_POWER

Caspian_POWER

Caspian_POWER

Shrek_Tseng

Shrek_Tseng

Engineer:

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

Engineer:

1

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

C

C

C

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Shrek_Tseng

83 97Friday, January 17, 2014

83 97Friday, January 17, 2014

83 97Friday, January 17, 2014

Rev

Rev

Rev

A00

A00

A00

Vinafix.com

5

4

3

2

1

COMPONENTS SHOWN ARE EXAMPLES ONLY
AND NOT NECESSARILY QUALIFIED

G1F

D D

C C

B B

A A

AB39

PART 6 0F 9

GND18

E39

GND95

F34

GND109

F39

GND110

G33

GND114

G34

GND115

H31

GND117

H34

GND118

H39

GND119

J31

GND123

J34

GND124

K31

GND128

K34

GND129

K39

GND130

L31

GND137

L34

GND138

M34

GND143

M39

GND144

N31

GND151

N34

GND152

P31

GND154

P34

GND155

P39

GND156

R34

GND164

T31

GND173

T34

GND174

T39

GND175

U31

GND183

U34

GND184

V34

GND192

V39

GND193

W31

GND195

W34

GND196

Y34

GND204

Y39

GND205

GND99
GND100
GND101
GND102
GND103
GND104
GND105
GND106
GND107
GND108
GND111
GND112
GND113
GND116
GND120
GND121
GND122
GND125
GND126
GND127
GND131
GND132
GND133
GND134
GND135
GND136
GND139
GND140
GND141
GND142
GND145
GND146
GND147
GND148
GND149
GND150
GND153
GND157
GND158
GND159
GND160
GND161
GND162
GND163
GND165
GND166
GND167
GND168
GND169
GND170
GND171
GND172
GND176
GND177
GND178
GND179
GND180
GND181
GND182
GND185
GND186
GND187
GND188
GND189
GND190
GND191
GND194
GND197
GND198
GND199
GND200
GND201
GND202
GND203

GND

F15
F17
F19
F21
F23
F25
F27
F29
F31
F33

F7

F9
G2
G6
H9

J2

J27

J6

J8

K14

K7

L11
L17

L2

L22
L24

L6

M17
M22
M24

N16
N18

N2

N21
N23
N26

N6

R15
R17

R2

R20
R22
R24
R27

R6

T11
T13
T16
T18
T21
T23
T26
U15
U17

U2

U20
U22
U24
U27

U6

V11
V16
V18
V21
V23
V26

W2

W6
Y15
Y17
Y20
Y22
Y24
Y27

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8

GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND41
GND42
GND43
GND44

GND45
GND46
GND47
GND48
GND49
GND50
GND51
GND52
GND53
GND54
GND55
GND56
GND57
GND58
GND59
GND60

GND61
GND62
GND63
GND64
GND65
GND66
GND67
GND68
GND69
GND70
GND71
GND72
GND73
GND74
GND75
GND76
GND77
GND78
GND79
GND80
GND81
GND82
GND83
GND84
GND85
GND86
GND87
GND88
GND89
GND90
GND91
GND92
GND93
GND94
GND96
GND97
GND98

NC_EVDDQ2

VSS_MECH1
VSS_MECH2
VSS_MECH3

A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18
AF21
AG17
AG2
AG20

AG6
AG9
AH21
AJ10
AJ11
AJ2
AJ28
AJ6
AK11
AK31
AK7
AL11
AL14
AL17
AL2
AL20

AL23
AL26
AL32
AL6
AL8
AM11
AM31
AM9
AN11
AN2
AN30
AN6
AN8
AP11
AP7
AP9
AR5
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B7
B9
C1
C39
E35
E5
F11
F13

AG22

A39
AW1
AW39

GND

GND

5

4

216-0842006

3

2

<Variant Name>

<Variant Name>

<Variant Name>

Title :

Title :

Title :

Caspian_GND

Caspian_GND

Caspian_GND

Shrek_Tseng

Shrek_Tseng

Engineer:

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Shrek_Tseng

84 97Friday, January 17, 2014

84 97Friday, January 17, 2014

84 97Friday, January 17, 2014

1

Rev

Rev

Rev

A00

A00

A00

Vinafix.com

1

COMPONENTS SHOWN ARE EXAMPLES ONLY
AND NOT NECESSARILY QUALIFIED

RASA0#

RASA0#[86]

RASA1#

RASA1#[86]

CASA0#

CASA0#[86]

CASA1#

CASA1#[86]

WEA0#

WEA0#[86]

WEA1#

WEA1#[86]

CKEA0

CKEA0[86]

CKEA1

CKEA1[86]

CSA0#_0

CSA0#_0[86]

CSA1#_0

R388
100 Ohm

I_GPU

+1P5V_GPU

12

I_GPU

12

R389

40.2 OHM

1%

1%

GNDGND

12

X5R/+/-10%

QSA#[7..0][86]
QSA[7..0][86]

DQMA#[7..0][86]
MDA[63..0][86]

C456
1UF/6.3V

I_GPU

CSA1#_0[86]

CLKA0

CLKA0[86]

CLKA0#

CLKA0#[86]

CLKA1

CLKA1[86]

CLKA1#

CLKA1#[86]

QSA#[7..0]
QSA[7..0]
DQMA#[7..0]
MDA[63..0]
MAA[15..0]

MAA[15..0][86]

A_BA0

A_BA0[86]

A_BA1

A_BA1[86]

A_BA2

A_BA2[86]

+1P5V_GPU

12

R387

40.2 OHM

I_GPU

1%

GPU_MVREFDA

R386
100 Ohm

I_GPU

12

GPU_MVREFSA

12

C455

1%

1UF/6.3V

I_GPU

1 2

X5R/+/-10%

R9256 120 Ohm I_GPU

1 2

GNDGND

R9257 120 Ohm NI

1 2

R9253 243OHM NI

GND

A A

B B

G1C

C37

MDA0

DQA0_0

C35

MDA1

DQA0_1

A35

MDA2

DQA0_2

E34

MDA3

DQA0_3

G32

MDA4

DQA0_4

D33

MDA5

DQA0_5

F32

MDA6

DQA0_6

E32

MDA7

DQA0_7

D31

MDA8

DQA0_8

F30

MDA9

DQA0_9

C30

MDA10

DQA0_10

A30

MDA11

DQA0_11

F28

MDA12

DQA0_12

C28

MDA13

DQA0_13

A28

MDA14

DQA0_14

E28

MDA15

DQA0_15

D27

MDA16

DQA0_16

F26

MDA17

DQA0_17

C26

MDA18

DQA0_18

A26

MDA19

DQA0_19

F24

MDA20

DQA0_20

C24

MDA21

DQA0_21

A24

MDA22

DQA0_22

E24

MDA23

DQA0_23

C22

MDA24

DQA0_24

A22

MDA25

DQA0_25

F22

MDA26

DQA0_26

D21

MDA27

DQA0_27

A20

MDA28

DQA0_28

F20

MDA29

DQA0_29

D19

MDA30

DQA0_30

E18

MDA31

DQA0_31

C18

MDA32

DQA1_0

A18

MDA33

DQA1_1

F18

MDA34

DQA1_2

D17

MDA35

DQA1_3

A16

MDA36

DQA1_4

F16

MDA37

DQA1_5

D15

MDA38

DQA1_6

E14

MDA39

DQA1_7

F14

MDA40

DQA1_8

D13

MDA41

DQA1_9

F12

MDA42

DQA1_10

A12

MDA43

DQA1_11

D11

MDA44

DQA1_12

F10

MDA45

DQA1_13

A10

MDA46

DQA1_14

C10

MDA47

DQA1_15

G13

MDA48

DQA1_16

H13

MDA49

DQA1_17

J13

MDA50

DQA1_18

H11

MDA51

DQA1_19

G10

MDA52

DQA1_20

G8

MDA53

DQA1_21

K9

MDA54

DQA1_22

K10

MDA55

DQA1_23

G9

MDA56

DQA1_24

A8

MDA57

DQA1_25

C8

MDA58

DQA1_26

E8

MDA59

DQA1_27

A6

MDA60

DQA1_28

C6

MDA61

DQA1_29

E6

MDA62

DQA1_30

A5

MDA63

DQA1_31

L18

MVREFDA

L20

MVREFSA

L27

NC27

N12

NC29

AG12

NC9

M27

MEM_CALRP0

M12

NC28

AH12

NC_MEM_CALRP2

216-0842006

PART 3 0F 9
GDDR5/DDR3

2

G24

MAA0_0
MAA0_1
MAA0_2
MAA0_3
MAA0_4
MAA0_5
MAA0_6
MAA0_7
MAA1_0
MAA1_1
MAA1_2
MAA1_3

MEMORY INTERFACE A

MAA1_4
MAA1_5
MAA1_6
MAA1_7

WCKA0_0

WCKA0B_0

WCKA0_1

WCKA0B_1

WCKA1_0

WCKA1B_0

WCKA1_1

WCKA1B_1

EDCA0_0
EDCA0_1
EDCA0_2
EDCA0_3
EDCA1_0
EDCA1_1
EDCA1_2
EDCA1_3

DDBIA0_0
DDBIA0_1
DDBIA0_2
DDBIA0_3
DDBIA1_0
DDBIA1_1
DDBIA1_2
DDBIA1_3

ADBIA0
ADBIA1

CLKA0

CLKA0B

CLKA1

CLKA1B
RASA0B

RASA1B
CASA0B

CASA1B

CSA0B_0
CSA0B_1

CSA1B_0
CSA1B_1

CKEA0
CKEA1

WEA0B
WEA1B

MAA0_8
MAA1_8
MAA0_9
MAA1_9

MAA0

J23

MAA1

H24

MAA2

J24

MAA3

H26

MAA4

J26

MAA5

H21

MAA6

G21

MAA7

H19

MAA8

H20

MAA9

L13

MAA10

G16

MAA11

J16

MAA12

H16

A_BA2

J17

A_BA0

H17

A_BA1

A32

DQMA#0

C32

DQMA#1

D23

DQMA#2

E22

DQMA#3

C14

DQMA#4

A14

DQMA#5

E10

DQMA#6

D9

DQMA#7

C34

QSA0

D29

QSA1

D25

QSA2

E20

QSA3

E16

QSA4

E12

QSA5

J10

QSA6

D7

QSA7

A34

QSA#0

E30

QSA#1

E26

QSA#2

C20

QSA#3

C16

QSA#4

C12

QSA#5

J11

QSA#6

F8

QSA#7

J21

ODTA0
ODTA1

CLKA0
CLKA0#

CLKA1
CLKA1#

RASA0#
RASA1#

CASA0#
CASA1#

CSA0#_0

CSA1#_0

CKEA0
CKEA1

WEA0#
WEA1#

MAA13
MAA14
MAA15

ODTA0 [86]
ODTA1 [86]

G19

H27

G27

J14

H14

K23

K19

K20

K17

K24

K27

M13

K16

K21

J20

K26

L15

H23

J19

M21

M20

3

MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31

MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39

R403
100 Ohm

I_GPU

R402
100 Ohm

I_GPU

+1P5V_GPU

GND

+1P5V_GPU

GND

12

I_GPU

12

12

I_GPU

12

R404

40.2 OHM

1%

1%

R401

40.2 OHM

1%

1%

GND

GND

12

X5R/+/-10%

12

X5R/+/-10%

C453
1UF/6.3V

I_GPU

C454
1UF/6.3V

I_GPU

MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63

GPU_MVREFDB
GPU_MVREFSB

4

G1D

PART 4 0F 9

GDDR5/DDR3

C5

DQB0_0

C3

DQB0_1

E3

DQB0_2

E1

DQB0_3

F1

DQB0_4

F3

DQB0_5

F5

DQB0_6

G4

DQB0_7

H5

DQB0_8

H6

DQB0_9

J4

DQB0_10

K6

DQB0_11

K5

DQB0_12

L4

DQB0_13

M6

DQB0_14

M1

DQB0_15

M3

DQB0_16

M5

DQB0_17

N4

DQB0_18

P6

DQB0_19

P5

DQB0_20
DQB0_21
DQB0_22
DQB0_23
DQB0_24
DQB0_25
DQB0_26
DQB0_27
DQB0_28
DQB0_29
DQB0_30
DQB0_31
DQB1_0
DQB1_1
DQB1_2
DQB1_3
DQB1_4
DQB1_5
DQB1_6
DQB1_7
DQB1_8
DQB1_9
DQB1_10
DQB1_11
DQB1_12
DQB1_13
DQB1_14
DQB1_15
DQB1_16
DQB1_17
DQB1_18
DQB1_19
DQB1_20
DQB1_21
DQB1_22
DQB1_23
DQB1_24
DQB1_25
DQB1_26
DQB1_27
DQB1_28
DQB1_29
DQB1_30
DQB1_31

MVREFDB
MVREFSB

216-0842006

MEMORY INTERFACE B

R4
T6
T1
U4
V6
V1
V3
Y6
Y1
Y3

Y5
AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6
AJ4
AK3
AF8
AF9
AG8
AG7
AK9
AL7
AM8
AM7
AK1
AL4
AM6
AM1
AN4
AP3
AP1
AP5

Y12

AA12

MAB0_0
MAB0_1
MAB0_2
MAB0_3
MAB0_4
MAB0_5
MAB0_6
MAB0_7
MAB1_0
MAB1_1
MAB1_2
MAB1_3
MAB1_4
MAB1_5
MAB1_6
MAB1_7

WCKB0_0

WCKB0B_0

WCKB0_1

WCKB0B_1

WCKB1_0

WCKB1B_0

WCKB1_1

WCKB1B_1

EDCB0_0
EDCB0_1
EDCB0_2
EDCB0_3
EDCB1_0
EDCB1_1
EDCB1_2
EDCB1_3

DDBIB0_0
DDBIB0_1
DDBIB0_2
DDBIB0_3
DDBIB1_0
DDBIB1_1
DDBIB1_2
DDBIB1_3

ADBIB0
ADBIB1

CLKB0B

CLKB1B
RASB0B

RASB1B
CASB0B

CASB1B

CSB0B_0
CSB0B_1

CSB1B_0
CSB1B_1

CKEB0
CKEB1

WEB0B
WEB1B

MAB0_8
MAB1_8
MAB0_9
MAB1_9

DRAM_RST

P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9

H3
H1
T3
T5
AE4
AF5
AK6
AK5

F6
K3
P3
V5
AB5
AH1
AJ9
AM5

G7
K1
P1
W4
AC4
AH3
AJ8
AM3

T7
W7

L9

CLKB0

L8
AD8

CLKB1

AD7
T10

Y10
W10

AA10
P10

L10
AD10

AC10
U10

AA11
N10

AB11

T8
W8
U12
V12

AH11

DRSTDRST

5

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
B_BA2
B_BA0
B_BA1

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

QSB0
QSB1
QSB2
QSB3

QSB#[7..0][87]

QSB4
QSB5

QSB[7..0][87]

QSB6
QSB7

QSB#0
QSB#1
QSB#2
QSB#3
QSB#4
QSB#5
QSB#6
QSB#7

ODTB0

ODTB0 [87]

ODTB1

ODTB1 [87]

CLKB0
CLKB0#

CLKB1
CLKB1#

RASB0#
RASB1#

CASB0#
CASB1#

CSB0#_0

CSB1#_0

CKEB0
CKEB1

WEB0#
WEB1#

MAB13
MAB14
MAB15

25mm (max) 5mm (max) 25mm (max)

Place all these componets very close to GPU (within 25mm)
and keep all components close to each other
** This basic topology should be used for DRAM_RAT for DDR3/GDDR5

These Capacitors and Resistor values arre an example only
The series R and || cap values will depend on the DRAM loads

and will have to be calculated for differrent Memory, DRAM loads and board
to pass Reset Signal Spec

RASB0#

RASB0#[87]

RASB1#

RASB1#[87]

CASB0#

CASB0#[87]

CASB1#

CASB1#[87]

WEB0#

WEB0#[87]

WEB1#

WEB1#[87]

CSB0#_0

CSB0#_0[87]

CSB1#_0

CSB1#_0[87]

CKEB0

CKEB0[87]

CKEB1

CKEB1[87]

CLKB0

CLKB0[87]

CLKB0#

CLKB0#[87]

CLKB1

CLKB1[87]

CLKB1#

CLKB1#[87]

QSB#[7..0]
QSB[7..0]
DQMB#[7..0]

DQMB#[7..0][87]

MDB[63..0]

MDB[63..0][87]

MAB[15..0]

MAB[15..0][87]

B_BA0

B_BA0[87]

B_BA1B_BA1

B_BA1[87]

B_BA2B_BA2

B_BA2[87]

1 2

R9262

10 OHM

I_GPU

12

12

C9409

R9343

120PF/50V

4.99KOhm

I_GPU

I_GPU

GND

DRAM_RST[86,87]

R9344

1 2

51.1 OHM

I_GPU

6

7

8

C C

D D

<Variant Name>

<Variant Name>

<Variant Name>

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

D

D

D

Date: Sheet of

Date: Sheet of

1

2

3

4

5

6

7

Date: Sheet of

IPPLP-TH

IPPLP-TH

IPPLP-TH

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

8

Caspian_MEMORY

Caspian_MEMORY

Caspian_MEMORY

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

85 97Friday, January 17, 2014

85 97Friday, January 17, 2014

85 97Friday, January 17, 2014

Rev

Rev

Rev

A00

A00

A00

Vinafix.com

5

4

3

2

1

MDA[63..0][85]

D D

C C

MAA[15..0][85]

B B

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8

MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
MAA15

DQMA#[7..0][85]

DQMA#0

DQMA#1

DQMA#2

DQMA#3

DQMA#4

DQMA#5

DQMA#6

DQMA#7

QSA[7..0][85]

QSA#[7..0][85]

QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

DDR TYPE:
0315-00NF0DE--Hynix
0315-00Q10DE--Samsung
0315-00SG0DE--Micro

Should be 240
Ohms +-1%

DRAM_RST[85,86,87]

U9204

M8

VREFC_U20

H1

VREFD_U20

N3

MAA0

P7

MAA1

P3

MAA2

N2

MAA3

P8

MAA4

P2

MAA5

R8

MAA6

R2

MAA7

T8

MAA8

R3

MAA9

L7

MAA10

R7

MAA11

N7

MAA12

M2

A_BA0[85,86]

N8

A_BA1[85,86]

M3

A_BA2[85,86]

J7

CLKA0[85,86]

K7

CLKA0#[85,86]

K9

CKEA0[85,86]

K1

ODTA0[85,86]

L2

CSA0#_0[85,86]

J3

RASA0#[85,86]

K3

CASA0#[85,86]

L3

WEA0#[85,86]

F3

QSA2

C7

QSA0

E7

DQMA#2

D3

DQMA#0

G3

QSA#2

B7

QSA#0

T2
L8

12

R9265
243OHM

J1

I_GPU

L1

J9
L9
M7

MAA15 MAA15

GND

T3

MAA13

T7

MAA14

+1P5V_GPU

R9269

4.99KOhm

I_GPU

1 2

R9273

4.99KOhm

I_GPU

1 2

GND GND

R9277

4.99KOhm

I_GPU

1 2

R9281

4.99KOhm

I_GPU

1 2

GND GND

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#

BA0
BA1
BA2

CK
CK#
CKE

ODT
CS#
RAS#
CAS#
WE#

DQSL
DQSU

DML
DMU

DQSL#
DQSU#

RESET#
ZQ

NC1
NC3
NC2
NC4
NC5
NC6
NC7

H5TQ2G63DFR-11C

I_GPU

VREFC_U20

12

VREFD_U20

12

C9410

0.1UF/6.3V

I_GPU

C9414

0.1UF/6.3V

I_GPU

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VSS10
VSS11
VSS12

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

N1

VDD1

R1

VDD2

B2

VDD3

K2

VDD4

G7

VDD5

K8

VDD6

D9

VDD7

N9

VDD8

R9

VDD9

A1
C1
F1
D2
H2
A8
C9
E9
H9

E1

VSS1

M1

VSS2

P1

VSS3

T1

VSS4

J2

VSS5

B3

VSS6

G8

VSS7

J8

VSS8

A9

VSS9

M9
P9
T9

B1
D1
G1
E2
D8
E8
B9
F9
G9

CHANNEL A: 256MB/512MB DDR3

U9205

MDA18
MDA23
MDA19
MDA22
MDA16
MDA17
MDA20
MDA21

MDA3
MDA4 MDA57
MDA0 MDA63
MDA6

MDA7
MDA1

+1P5V_GPU

MDA5

+1P5V_GPU +1P5V_GPU

GND GND

Should be 240
Ohms +-1%

GND GND

M8

VREFC_U21

H1

VREFD_U21

N3

MAA0

P7

MAA1

P3

MAA2

N2

MAA3

P8

MAA4

P2

MAA5

R8

MAA6

R2

MAA7

T8

MAA8

R3

MAA9

L7

MAA10

R7

MAA11

N7

MAA12

M2

A_BA0[85,86]

N8

A_BA1[85,86]

M3

A_BA2[85,86]

J7

CLKA0[85,86]

K7

CLKA0#[85,86]

K9

CKEA0[85,86]

K1

ODTA0[85,86]

L2

CSA0#_0[85,86]

J3

RASA0#[85,86]

K3

CASA0#[85,86]

L3

WEA0#[85,86]

F3

QSA3

C7

QSA1

E7

DQMA#3

D3

DQMA#1

G3

QSA#3

B7

QSA#1

DRAM_RST[85,86,87]

T2
L8

12

R9266
243OHM

J1

I_GPU

L1
J9
L9

M7

T3

MAA13

T7

MAA14

R9270

4.99KOhm

I_GPU

R9274

4.99KOhm

I_GPU

R9278

4.99KOhm

I_GPU

R9282

4.99KOhm

I_GPU

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#

BA0
BA1
BA2

CK
CK#
CKE

ODT
CS#
RAS#
CAS#
WE#

DQSL
DQSU

DML
DMU

DQSL#
DQSU#

RESET#
ZQ

NC1
NC3
NC2
NC4
NC5
NC6
NC7

H5TQ2G63DFR-11C

I_GPU

+1P5V_GPU

1 2

1 2

GND GND
+1P5V_GPU

1 2

1 2

GND

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8

VSS9
VSS10
VSS11
VSS12

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VREFC_U21

12

VREFD_U21

12

GND

I_GPU

I_GPU

E3
F7
F2
F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

N1
R1
B2
K2
G7
K8
D9
N9
R9

A1
C1
F1
D2
H2
A8
C9
E9
H9

E1
M1
P1
T1
J2
B3
G8
J8
A9
M9
P9
T9

B1
D1
G1
E2
D8
E8
B9
F9
G9

C9411

0.1UF/6.3V

C9415

0.1UF/6.3V

MDA25
MDA24
MDA27
MDA30
MDA31
MDA29
MDA26
MDA28

MDA15
MDA11
MDA14

MDA9

MDA12

MDA8

MDA13

+1P5V_GPU

MDA10

DRAM_RST[85,86,87]

Should be 240
Ohms +-1%

VREFC_U22
VREFD_U22

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8

MAA9
MAA10
MAA11
MAA12

A_BA0[85,86]
A_BA1[85,86]
A_BA2[85,86]

CLKA1[85,86]
CLKA1#[85,86]
CKEA1[85,86]

ODTA1[85,86]
CSA1#_0[85,86]

RASA1#[85,86]
CASA1#[85,86]
WEA1#[85,86]

QSA4

QSA7

DQMA#4

DQMA#7

QSA#4

QSA#7

12

MAA15
MAA13
MAA14

R9267
243OHM

I_GPU

M8
H1

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7

M2
N8
M3

J7
K7
K9

K1
L2
J3
K3
L3

F3
C7

E7
D3

G3
B7

T2
L8

J1
L1
J9
L9
M7
T3
T7

R9271

4.99KOhm

I_GPU

R9275

4.99KOhm

I_GPU

R9279

4.99KOhm

I_GPU

R9283

4.99KOhm

I_GPU

I_GPU

U9206

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#

BA0
BA1
BA2

CK
CK#
CKE

ODT
CS#
RAS#
CAS#
WE#

DQSL
DQSU

DML
DMU

DQSL#
DQSU#

RESET#
ZQ

NC1
NC3
NC2
NC4
NC5
NC6
NC7

H5TQ2G63DFR-11C

+1P5V_GPU

1 2

1 2

GND

+1P5V_GPU+1P5V_GPU

1 2

1 2

GND GND

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8

VSS9
VSS10
VSS11
VSS12

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VREFC_U22

VREFD_U22

E3
F7
F2
F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

N1
R1
B2
K2
G7
K8
D9
N9
R9

A1
C1
F1
D2
H2
A8
C9
E9
H9

E1
M1
P1
T1
J2
B3
G8
J8
A9
M9
P9
T9

B1
D1
G1
E2
D8
E8
B9
F9
G9

12

C9412

0.1UF/6.3V

I_GPU

GND

12

C9416

0.1UF/6.3V

I_GPU

U9207

M8

VREFC_U23

H1

Should be 240
Ohms +-1%

GND

VREFD_U23

N3

MAA0

P7

MAA1

P3

MAA2

N2

MAA3

P8

MAA4

P2

MAA5

R8

MAA6

R2

MAA7

T8

MAA8

R3

MAA9

L7

MAA10

R7

MAA11

N7

MAA12

M2

A_BA0[85,86]

N8

A_BA1[85,86]

M3

A_BA2[85,86]

J7

CLKA1[85,86]

K7

CLKA1#[85,86]

K9

CKEA1[85,86]

K1

ODTA1[85,86]

L2

CSA1#_0[85,86]

J3

RASA1#[85,86]

K3

CASA1#[85,86]

L3

WEA1#[85,86]

F3

QSA6

C7

QSA5

E7

DQMA#6

D3

DQMA#5

G3

QSA#6

B7

QSA#5

T2

DRAM_RST[85,86,87]

L8

12

R9268
243OHM

J1

I_GPU

L1

J9
L9
M7

MAA15

T3

MAA13

T7

MAA14

MDA36
MDA38
MDA37
MDA39
MDA34
MDA33
MDA35
MDA32

MDA61

MDA56
MDA60
MDA58
MDA62

+1P5V_GPU

MDA59

+1P5V_GPU

GND

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#

BA0
BA1
BA2

CK
CK#
CKE

ODT
CS#
RAS#
CAS#
WE#

DQSL
DQSU

DML
DMU

DQSL#
DQSU#

RESET#
ZQ

NC1
NC3
NC2
NC4
NC5
NC6
NC7

H5TQ2G63DFR-11C

I_GPU

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VSS10
VSS11
VSS12

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

R9272

4.99KOhm

I_GPU

R9276

4.99KOhm

I_GPU

R9280

4.99KOhm

I_GPU

R9284

4.99KOhm

I_GPU

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

E3
F7
F2
F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

N1
R1
B2
K2
G7
K8
D9
N9
R9

A1
C1
F1
D2
H2
A8
C9
E9
H9

E1
M1
P1
T1
J2
B3
G8
J8
A9
M9
P9
T9

B1
D1
G1
E2
D8
E8
B9
F9
G9

GND

+1P5V_GPU

1 2

VREFC_U23

1 2

GND
+1P5V_GPU

1 2

VREFD_U23

1 2

GND GND

MDA53
MDA51
MDA55
MDA48
MDA50
MDA54
MDA52
MDA49

MDA43
MDA44
MDA40
MDA46
MDA42
MDA47
MDA41MDA2

+1P5V_GPU

MDA45

+1P5V_GPU

12

C9413

0.1UF/6.3V

I_GPU

GND

12

C9417

0.1UF/6.3V

I_GPU

CLKA0[85,86]

CLKA0#[85,86]

CLKA1[85,86]

CLKA1#[85,86]

A A

5

R9345

40.2 OHM
C9510

I_GPU

12

1 2

I_GPU

R9346

0.01UF/25V

40.2 OHM

I_GPU

1 2

R9347

40.2 OHM
C9511

I_GPU

12

1 2

I_GPU

R9348

0.01UF/25V

40.2 OHM

I_GPU

1 2

+1P5V_GPU

GND

12

12

12

C7856

C457

I_GPU

10UF/6.3V

I_GPU

1UF/6.3V

1UF/6.3V

GND

X5R/+/-10%

GND

X5R/+/-10%

12

12

12

12

12

12

C473

C469

C468

C467

C470

C471

C472

NI

NI

I_GPU

1UF/6.3V

I_GPU

I_GPU

I_GPU

I_GPU

1UF/6.3V

1UF/6.3V

1UF/6.3V

1UF/6.3V

1UF/6.3V

X5R/+/-10%

X5R/+/-10%

X5R/+/-10%

X5R/+/-10%

X5R/+/-10%

4

+1P5V_GPU

12

10UF/6.3V

GND

12

12

12

12

12

12

12

C7857

C502

I_GPU

I_GPU

1UF/6.3V

1UF/6.3V

X5R/+/-10%

X5R/+/-10%

12

C505

C506

C507

C508

C509

C504

I_GPU

C510

NI

I_GPU

I_GPU

I_GPU

I_GPU

I_GPU

1UF/6.3V

1UF/6.3V

1UF/6.3V

1UF/6.3V

1UF/6.3V

1UF/6.3V

X5R/+/-10%

X5R/+/-10%

X5R/+/-10%

X5R/+/-10%

X5R/+/-10%

X5R/+/-10%

+1P5V_GPU

12

12

C7858

I_GPU

10UF/6.3V

1UF/6.3V

GND

X5R/+/-10%

3

12

12

12

12

12

12

12

C486

C487

C485

C479

C481

C482

C483

C484

NI

I_GPU

I_GPU

I_GPU

1UF/6.3V

X5R/+/-10%

I_GPU

I_GPU

I_GPU

I_GPU

1UF/6.3V

1UF/6.3V

1UF/6.3V

1UF/6.3V

1UF/6.3V

1UF/6.3V

X5R/+/-10%

X5R/+/-10%

X5R/+/-10%

X5R/+/-10%

X5R/+/-10%

X5R/+/-10%

+1P5V_GPU

12

C7859

10UF/6.3V

GND

12

12

12

12

12

12

12

12

C499

C495

C497

C498

C638

C639

C640

C641

I_GPU

I_GPU

I_GPU

I_GPU

I_GPU

I_GPU

I_GPU

I_GPU

I_GPU

1UF/6.3V

1UF/6.3V

1UF/6.3V

1UF/6.3V

1UF/6.3V

1UF/6.3V

1UF/6.3V

1UF/6.3V

X5R/+/-10%

X5R/+/-10%

X5R/+/-10%

X5R/+/-10%

X5R/+/-10%

X5R/+/-10%

X5R/+/-10%

X5R/+/-10%

<Variant Name>

<Variant Name>

<Variant Name>

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

D

D

D

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

1

IPPLP-AZ

IPPLP-AZ

IPPLP-AZ

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

DDR3 64MX16 A

DDR3 64MX16 A

DDR3 64MX16 A

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

86 97Friday, January 17, 2014

86 97Friday, January 17, 2014

86 97Friday, January 17, 2014

Rev

Rev

Rev

A00

A00

A00

Vinafix.com

5

4

3

2

1

MDB[63..0][85]

D D

C C

B B

MAB[15..0][85]

DQMB#[7..0][85]

MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14

MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63

MAB0

MAB1

MAB2

MAB3

MAB4

MAB5

MAB6

MAB7

MAB8

MAB9

MAB10

MAB11

MAB12

MAB13

MAB14

MAB15

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

QSB[7..0][85]

QSB0

QSB1

QSB2

QSB3

QSB4

QSB5

QSB6

QSB7

QSB#[7..0][85]

QSB#0

QSB#1

QSB#2

QSB#3

QSB#4

QSB#5

QSB#6

QSB#7

Should be 240
Ohms +-1%

GND

DRAM_RST[85,86,87]

U9208

M8

VREFC_U24

H1

VREFD_U24

N3

MAB0

P7

MAB1

P3

MAB2

N2

MAB3

P8

MAB4

P2

MAB5

R8

MAB6

R2

MAB7

T8

MAB8

R3

MAB9

L7

MAB10

R7

MAB11

N7

MAB12

M2

B_BA0[85,87]

N8

B_BA1[85,87]

M3

B_BA2[85,87]

J7

CLKB0[85,87]

K7

CLKB0#[85,87]

K9

CKEB0[85,87]

K1

ODTB0[85,87]

L2

CSB0#_0[85,87]

J3

RASB0#[85,87]

K3

CASB0#[85,87]

L3

WEB0#[85,87]

F3

QSB3

C7

QSB0

E7

DQMB#3

D3

DQMB#0

G3

QSB#3

B7

QSB#0

T2
L8

12

R9289
243OHM

J1

I_GPU

L1
J9
L9

M7

MAB15MAB15 MAB15

T3

MAB13

T7

MAB14

R9293

4.99KOhm

I_GPU

R9297

4.99KOhm

I_GPU

R9301

4.99KOhm

I_GPU

R9305

4.99KOhm

I_GPU

E3

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

MDB31

DQL0

F7

MDB27

DQL1

F2

MDB25

DQL2

F8

MDB24

DQL3

H3

MDB30

DQL4

H8

MDB26

DQL5

G2

MDB29

DQL6

H7

MDB28

DQL7

D7

MDB2

DQU0

C3

MDB4

DQU1

C8

MDB1

DQU2

C2

MDB5

DQU3

A7

MDB3

DQU4

A2

MDB7

DQU5

B8

MDB0

DQU6

A3

MDB6

DQU7

N1

VDD1

R1

VDD2

B2

VDD3

K2

VDD4

G7

VDD5

K8

VDD6

D9

VDD7

N9

VDD8

+1P5V_GPU

R9

VDD9

A1
C1
F1
D2
H2
A8
C9
E9
H9

E1

VSS1

M1

VSS2

P1

VSS3

T1

VSS4

J2

VSS5

B3

VSS6

G8

VSS7

J8

VSS8

A9

VSS9

M9

VSS10

P9

VSS11

T9

VSS12

B1
D1
G1
E2
D8
E8
B9
F9
G9

GND

12

C9442

0.1UF/6.3V

I_GPU

GND

12

C9446

0.1UF/6.3V

I_GPU

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#

BA0
BA1
BA2

CK
CK#
CKE

ODT
CS#
RAS#
CAS#
WE#

DQSL
DQSU

DML
DMU

DQSL#
DQSU#

RESET#
ZQ

NC1
NC3
NC2
NC4
NC5
NC6
NC7

H5TQ2G63DFR-11C

I_GPU

+1P5V_GPU +1P5V_GPU

1 2

1 2

GND

1 2

1 2

CHANNEL B: 256MB/512MB DDR3

U9209

+1P5V_GPU

Should be 240
Ohms +-1%

GND

M8

VREFC_U25

H1

VREFD_U25

N3

MAB0

P7

MAB1

P3

MAB2

N2

MAB3

P8

MAB4

P2

MAB5

R8

MAB6

R2

MAB7

T8

MAB8

R3

MAB9

L7

MAB10

R7

MAB11

N7

MAB12

M2

B_BA0[85,87]

N8

B_BA1[85,87]

M3

B_BA2[85,87]

J7

CLKB0[85,87]

K7

CLKB0#[85,87]

K9

CKEB0[85,87]

K1

ODTB0[85,87]

L2

CSB0#_0[85,87]

J3

RASB0#[85,87]

K3

CASB0#[85,87]

L3

WEB0#[85,87]

F3

QSB2

C7

QSB1

E7

DQMB#2

D3

DQMB#1

G3

QSB#2

B7

QSB#1

T2

DRAM_RST[85,86,87]

L8

12

R9290
243OHM

J1

I_GPU

L1

J9
L9
M7
T3

MAB13MAB13

T7

MAB14

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#

BA0
BA1
BA2

CK
CK#
CKE

ODT
CS#
RAS#
CAS#
WE#

DQSL
DQSU

DML
DMU

DQSL#
DQSU#

RESET#
ZQ

NC1
NC3
NC2
NC4
NC5
NC6
NC7

H5TQ2G63DFR-11C

I_GPU

R9294

4.99KOhm

I_GPU

R9298

4.99KOhm

I_GPU

R9302

4.99KOhm

I_GPU

R9306

4.99KOhm

I_GPU

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

GND
+1P5V_GPU+1P5V_GPU

E3

MDB19

DQL0

F7

MDB18

DQL1

F2

MDB17

DQL2

F8

MDB20

DQL3

H3

MDB16

DQL4

H8

MDB23

DQL5

G2

MDB22

DQL6

H7

MDB21

DQL7

D7

MDB15

DQU0

C3

MDB11

DQU1

C8

MDB14

DQU2

C2

MDB10

DQU3

A7

MDB12

DQU4

A2

MDB8

DQU5

B8

MDB13

DQU6

A3

MDB9

DQU7

N1

VDD1

R1

VDD2

B2

VDD3

K2

VDD4

G7

VDD5

K8

VDD6

D9

VDD7

N9

VDD8

+1P5V_GPU

R9

VDD9

A1
C1
F1
D2
H2
A8
C9
E9
H9

E1

VSS1

M1

VSS2

P1

VSS3

T1

VSS4

J2

VSS5

B3

VSS6

G8

VSS7

J8

VSS8

A9

VSS9

M9

VSS10

P9

VSS11

T9

VSS12

B1
D1
G1
E2
D8
E8
B9
F9
G9

GND

1 2

VREFC_U25VREFC_U24

12

C9443

0.1UF/6.3V

I_GPU

1 2

GND

1 2

VREFD_U25VREFD_U24

12

C9447

0.1UF/6.3V

I_GPU

1 2

GND

+1P5V_GPU

U9210

M8

VREFC_U26

H1

VREFD_U26

N3

MAB0

P7

MAB1 MAB2

P3

MAB2

N2

MAB3

P8

MAB4

P2

MAB5

R8

MAB6

R2

MAB7

T8

MAB8

R3

MAB9

L7

MAB10

R7

MAB11

N7

MAB12

M2

B_BA0[85,87]

N8

B_BA1[85,87]

M3

B_BA2[85,87]

J7

CLKB1[85,87]

K7

CLKB1#[85,87]

K9

CKEB1[85,87]

K1

ODTB1[85,87]

L2

CSB1#_0[85,87]

J3

RASB1#[85,87]

K3

CASB1#[85,87]

L3

WEB1#[85,87]

F3

QSB4

C7

QSB7

E7

DQMB#4

D3

DQMB#7

G3

QSB#4

B7

QSB#7

T2

DRAM_RST[85,86,87]

L8

12

R9291

Should be 240

243OHM

Ohms +-1%

GND

J1

I_GPU

L1
J9
L9

M7

MAB15

T3

MAB13MAB13

T7

MAB14

R9295

4.99KOhm

I_GPU

R9299

4.99KOhm

I_GPU

R9303

4.99KOhm

I_GPU

R9307

4.99KOhm

I_GPU

E3

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#

BA0
BA1
BA2

CK
CK#
CKE

ODT
CS#
RAS#
CAS#
WE#

DQSL
DQSU

DML
DMU

DQSL#
DQSU#

RESET#
ZQ

NC1
NC3
NC2
NC4
NC5
NC6
NC7

H5TQ2G63DFR-11C

I_GPU

+1P5V_GPU +1P5V_GPU

1 2

1 2

GND

1 2

1 2

GND

MDB35MDB35

DQL0

F7

MDB37MDB37

DQL1

F2

MDB34MDB34

DQL2

F8

MDB39MDB39

DQL3

H3

MDB33MDB33

DQL4

H8

MDB36MDB36

DQL5

G2

MDB32MDB32

DQL6

H7

MDB38MDB38

DQL7

D7

MDB62MDB62

DQU0

C3

MDB58MDB58

DQU1

C8

MDB63MDB63

DQU2

C2

MDB56MDB56

DQU3

A7

MDB61MDB61

DQU4

A2

MDB57MDB57

DQU5

B8

MDB60MDB60

DQU6

A3

MDB59MDB59

DQU7

N1

VDD1

R1

VDD2

B2

VDD3

K2

VDD4

G7

VDD5

K8

VDD6

D9

VDD7

N9

VDD8

R9

VDD9

A1

VDDQ1

C1

VDDQ2

F1

VDDQ3

D2

VDDQ4

H2

VDDQ5

A8

VDDQ6

C9

VDDQ7

E9

VDDQ8

H9

VDDQ9

E1

VSS1

M1

VSS2

P1

VSS3

T1

VSS4

J2

VSS5

B3

VSS6

G8

VSS7

J8

VSS8

A9

VSS9

M9

VSS10

P9

VSS11

T9

VSS12

B1

VSSQ1

D1

VSSQ2

G1

VSSQ3

E2

VSSQ4

D8

VSSQ5

E8

VSSQ6

B9

VSSQ7

F9

VSSQ8

G9

VSSQ9

GND GND

VREFC_U26

12

C9444

0.1UF/6.3V

I_GPU

GND

12

C9448

0.1UF/6.3V

I_GPU

GNDGNDGND GND

+1P5V_GPU

+1P5V_GPU

Should be 240
Ohms +-1%

GND

U9211

M8

VREFC_U27

H1

VREFD_U27

N3

MAB0

P7

MAB1

P3
N2

MAB3

P8

MAB4

P2

MAB5

R8

MAB6

R2

MAB7

T8

MAB8

R3

MAB9

L7

MAB10

R7

MAB11

N7

MAB12

M2

B_BA0[85,87]

N8

B_BA1[85,87]

M3

B_BA2[85,87]

J7

CLKB1[85,87]

K7

CLKB1#[85,87]

K9

CKEB1[85,87]

K1

ODTB1[85,87]

L2

CSB1#_0[85,87]

J3

RASB1#[85,87]

K3

CASB1#[85,87]

L3

WEB1#[85,87]

F3

QSB6

C7

QSB5

E7

DQMB#6

D3

DQMB#5

G3

QSB#6

B7

QSB#5

T2

DRAM_RST[85,86,87]

L8

12

R9292
243OHM

J1

I_GPU

L1
J9
L9

M7

MAB15

T3

MAB13

T7

MAB14

R9296

4.99KOhm

I_GPU

R9300

4.99KOhm

I_GPU

R9304

4.99KOhm

I_GPU

R9308

4.99KOhm

I_GPU

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#

BA0
BA1
BA2

CK
CK#
CKE

ODT
CS#
RAS#
CAS#
WE#

DQSL
DQSU

DML
DMU

DQSL#
DQSU#

RESET#
ZQ

NC1
NC3
NC2
NC4
NC5
NC6
NC7

H5TQ2G63DFR-11C

I_GPU

1 2

1 2

GND
+1P5V_GPU+1P5V_GPU

1 2

1 2

GND

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8

VSS9
VSS10
VSS11
VSS12

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VREFC_U27

VREFD_U27VREFD_U26

E3

MDB54

F7

MDB50

F2

MDB55

F8

MDB51

H3

MDB53

H8

MDB48

G2

MDB52

H7

MDB49

D7

MDB40

C3

MDB44

C8

MDB43

C2

MDB46

A7

MDB47

A2

MDB45

B8

MDB41

A3

MDB42

+1P5V_GPU

N1
R1
B2
K2
G7
K8
D9
N9

+1P5V_GPU

R9
A1

C1
F1
D2
H2
A8
C9
E9
H9

E1
M1
P1
T1
J2
B3
G8
J8
A9
M9
P9
T9

B1
D1
G1
E2
D8
E8
B9
F9
G9

12

C9445

0.1UF/6.3V

I_GPU

GND

12

C9449

0.1UF/6.3V

I_GPU

GND

CLKB0[85,87]

R9349

40.2 OHM
C9512

I_GPU

12

1 2

R9350

40.2 OHM

CLKB0#[85,87]
CLKB1[85,87]

CLKB1#[85,87]

A A

I_GPU

1 2

R9351

40.2 OHM

I_GPU

1 2

R9352

40.2 OHM

I_GPU

1 2

5

0.01UF/25V

C9513

0.01UF/25V

GND

+1P5V_GPU

I_GPU

12

I_GPU

12

12

12

C7862

C681

NI

GND

10UF/6.3V

I_GPU

1UF/6.3V

GND

X5R/+/-10%

12

12

12

12

12

12

C6834.7U F/6.3V

C6884.7U F/6.3V

C684

C687

C686

C6894.7U F/6.3V

C685

I

X5R/+/-20%

I

I

I_GPU

I_GPU

I_GPU

I_GPU

X5R/+/-20%

X5R/+/-20%

1UF/6.3V

1UF/6.3V

1UF/6.3V

1UF/6.3V

X5R/+/-10%

X5R/+/-10%

X5R/+/-10%

X5R/+/-10%

+1P5V_GPU

12

C7863

NI

10UF/6.3V

GND

4

12

12

12

C697

C715

C699

I_GPU

I_GPU

I_GPU

1UF/6.3V

1UF/6.3V

1UF/6.3V

X5R/+/-10%

X5R/+/-10%

X5R/+/-10%

+1P5V_GPU

12

10UF/6.3V

GND

12

12

12

12

12

C7860

C651

C649

NI

I_GPU

I_GPU

1UF/6.3V

1UF/6.3V

1UF/6.3V

X5R/+/-10%

X5R/+/-10%

X5R/+/-10%

12

12

12

12

C653

C655

C652

NI

C664

C657

C654

C656

NI

I_GPU

I_GPU

I_GPU

I_GPU

I_GPU

1UF/6.3V

1UF/6.3V

1UF/6.3V

1UF/6.3V

1UF/6.3V

1UF/6.3V

X5R/+/-10%

X5R/+/-10%

X5R/+/-10%

X5R/+/-10%

X5R/+/-10%

X5R/+/-10%

3

+1P5V_GPU

12

C7861

I_GPU

10UF/6.3V

GND

12

12

12

12

C665

I_GPU

1UF/6.3V

1UF/6.3V

X5R/+/-10%

X5R/+/-10%

12

12

12

12

C669

C671

C673

C668

C670

C672

C667

NI

I_GPU

I_GPU

I_GPU

I_GPU

I_GPU

I_GPU

1UF/6.3V

1UF/6.3V

1UF/6.3V

1UF/6.3V

1UF/6.3V

1UF/6.3V

X5R/+/-10%

X5R/+/-10%

X5R/+/-10%

X5R/+/-10%

X5R/+/-10%

X5R/+/-10%

<Variant Name>

<Variant Name>

<Variant Name>

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

D

D

D

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

1

IPPLP-TH

IPPLP-TH

IPPLP-TH

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

DDR3 64MX16 B

DDR3 64MX16 B

DDR3 64MX16 B

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

87 97Friday, January 17, 2014

87 97Friday, January 17, 2014

87 97Friday, January 17, 2014

Rev

Rev

Rev

A00

A00

A00

Vinafix.com

5

D D

C C

4

3

2

1

B B

A A

<Variant Name>

<Variant Name>

<Variant Name>

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

IPPLP-TH

IPPLP-TH

IPPLP-TH

Engineer:

1

XXXXXX

XXXXXX

XXXXXX

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

88 97Friday, January 17, 2014

88 97Friday, January 17, 2014

88 97Friday, January 17, 2014

Rev

Rev

Rev

A00

A00

A00

Vinafix.com

5

D D

C C

4

3

2

1

B B

A A

<Variant Name>

<Variant Name>

<Variant Name>

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

IPPLP-TH

IPPLP-TH

IPPLP-TH

Engineer:

1

XXXXXX

XXXXXX

XXXXXX

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

89 97Friday, January 17, 2014

89 97Friday, January 17, 2014

89 97Friday, January 17, 2014

Rev

Rev

Rev

A00

A00

A00

Vinafix.com

5

A

4

3

2

1

D D

C C

B B

<Variant Name>

<Variant Name>

<Variant Name>

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

IPPLP-TH

IPPLP-TH

IPPLP-TH

Engineer:

XXXXXX

XXXXXX

XXXXXX

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

90 97Friday, January 17, 2014

90 97Friday, January 17, 2014

90 97Friday, January 17, 2014

Rev

Rev

Rev

A00

A00

A00

A

Vinafix.com

5

+3P3V_GPU
TDC=0.06A
Trace Width>70mil

D D

NVVDD_PWRGD[91,93]

C C

SLP_A#[22,44,50,68,91]

B B

A A

5

+3P3V

GPUPW_EN[22,71,91,93]

1 2

PR383 10KOhmNI

1%

GND

+12VSA

NI

PR40

PR9992 0Ohm 5%NOBOM

12

GND

NI

PR486

1 2

1 2

NI

PC368

0.1UF/16V

X7R 10%

1%

1 2

I_GPU

PQ34
30mOhm/10V SOT-23

3 2

D

3

0

12

PR11410KOhmNI

S

G

1

1

+1P05V_ME_FB1_A

0

mx_r0603

2

GPU_GATE1

GND

NI

PR65

NI

PC640568

4

RN47A4

E

3

3

2

2

1

1

E

PQ20

I_GPU

PU107

1

EN

2

GND

3

FB

APL5611CI-TRG

47PF/50V

1 2

4

+3P3V_GPU_EN

12

GND

B

NI

VCC
DRV

SS

PC76

3.16KOhm

1%

12

1000PF/50V

X7R 10%

PC134

0.1UF/16V

MLCC/+/-10%

I_GPU

4

4

C

5

C

5

6
5
4

12

MLCC/+/-5%NI

12

GND

+3P3V_GPU

I_GPU

PC136

0.1UF/16V

X7R 10%

PR155

1 2

1K 1%

mx_r0402_small

I_GPU

+5VSB

12

PC251
1UF/6.3V

X5R/+/-10%

NI

GND

+1P05V_ME_DRI_C

+1P05V_ME_SS_A

12

NI

PC77

0.01UF/25V

X7R 10%

GNDGND

+1P05V_ME_FB2_A

Vout=0.8(1+3.16/10)=1.052V

GPU_GATE13

I_GPU

12

1%

100KOHM
PR33

GND

+1P05V_ME/Imax:1A

Pd = 0.55*(3.3-1.05) = 1.2W

1 2

NI

PR60246

PR298

5.76KOhm

1%

1 2

NI

+1P05V_ME_FB

12

PC49
680PF/50V

MLCC/+/-10%
NI

3

+1P5V_GPU
IMAX=8A
Trace Width>240mil

100 Ohm

mx_r0805

12

NI

PR41

8.2KOHM

5%

SHORTPIN

NOBOM

3

PJP311

1

1

G

+3P3VA

23

2

3

12

NVVDD_PWRGD[91,93]

GPUPW_EN[22,71,91,93]

D

NI

PQ9504
SM3119NAUC-TRG

Vgs=10v@9mohm

S

+1P5V_DUAL

12

NI

PC75
10UF/6.3V

X5R 10%
mx_c0805

GND

12

NI

PC252
10UF/6.3V

X5R 10%
mx_c0805

GND GND

SLP_A#[22,44,50,68,91]

+12VSA

PR44 0Ohm 5%NOBOM

NI

PR9993

5 4

1 2

1 2

+1P05V_ME

I

PR498

12

NI

PC254
10UF/6.3V

X5R 10%
mx_c0805

+1P05V_ME

+5VA

3

1

1

G

2

GND GND

PQ530

8
7
6

D

5

BSC889N03LS

I_GPU

0

1 2

NI

PR116

12

NI

SR632

10KOhm

32

D

NI

PQ9505
2N7002

S

2

2

S

G

1
2
3

GPU_GATE2

GND

0 Ohm

1 2

12

GND

RN47A4

E

3

3

2

2

1

1

E

PQ29

I_GPU

+1P05V_PCH

22KOHM

1%

32

3

D

1

1

G

S

2

+1P5V_GPU_DR4

PC40

0.1UF/16V

MLCC/+/-10%
I_GPU

4

C

B

5

C

+1P05V_ME_POK

NI

PQ9506
2N7002

4

5

I_GPU

PR36

+1P5V_GPU_GATE

12

NI

0.1UF/6.3V

MLCC/+/-10%

GND

APWROK [20,91]

88.7KOHM

1%

12

I_GPU

PC36

0.1UF/6.3V

MLCC/+/-10%

GND

I_GPU

12

1%

100KOHM
PR35

GND

+5VSB

12

NI

PR60232

8.2KOHM

1%

+1P05V_ME_POK_G

3
C

NI

E
2

PQ15
PMBS3904

12

0.1UF/6.3V

MLCC/+/-10%

GND

IPPLP-TH

IPPLP-TH

IPPLP-TH

B

1

PC33

GND GND

<Variant Name>

<Variant Name>

<Variant Name>

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

NI

PC29

1

1

G

1

32

3

D

NI

PQ598
2N7002

S

2

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

+1P5V_GPU

APWROK [20,91]

3P3V_GPU & +1P05V_ME

3P3V_GPU & +1P05V_ME

3P3V_GPU & +1P05V_ME

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

Rev

Rev

Rev

A00

A00

A00

91 97Friday, January 17, 2014

91 97Friday, January 17, 2014

91 97Friday, January 17, 2014

Vinafix.com

5

4

3

2

1

1

1

G

GND

+3P3V

2

3

12

23

+1P5V_DUAL

54

5
D

S

G

Id=98A/Pd=57W

NI

PR273
33

mx_r0603
5%

D

S

GND

GND

I_GPU

PQ24

876

BSC883N03LS

123

12

I_GPU

12

PC206
10UF/6.3V

X5R 10%
mx_c0805

I_GPU

12

PC208
10UF/6.3V

X5R 10%
mx_c0805

I_GPU

PC205
10UF/6.3V

X5R 10%
mx_c0805

+0P95V
Imax=4.5A

P=(1.5-0.95)*3.15=1.73W

+0P95V

I_GPU

PCE33
100UF/6.3V

ESR=15m/Ir=2.7A

GNDGND

+3P3V ==> +1P8V
Imax=1A

+1P8V_MXM

FEEBACK COMPENSATION

NI

D D

C C

B B

+3P3V_GPU

12

I_GPU

PR261

24.9K

1%

Vref=3.3*10/(24.9+10)=0.9456V

12

GND GND

+3P3V_GPU

12

12

GND

12

I_GPU

PR414
10KOhm

I_GPU

PR419

10KOhm

1%

I_GPU

PR278
12K

1%

PC207

0.1UF/6.3V

1%

MLCC/+/-10%

Vref=3.3*12/(12+10)=1.8V

12

PC204

0.1UF/6.3V

MLCC/+/-10%

GND

I_GPU

I_GPU

12

NI

PC313
47PF/50V

PR442

14.7K

1%

1 2

I_GPU

12

PC209
820PF/50V

X7R 10%

+0P95V_GPU_C

12

I_GPU

PR420
15K

1%

+0P95V_GPU_REF
+0P95V_GPU_10
+1P8V_MXM_REF
+1P8V_MXM__FB_A

I_GPU

PR418

1 2

15K

1%

I_GPU

PR413
1K

1%

1 2

+1P8V_MXM__FB_R_A

I_GPU

PR417
1K

1%

1 2

NI

PC196
47PF/50V

NPO 5%

12

3
2
5
6

I_GPU

PU11
LM358

A+

+

A-

-

B+

+

B-

-

NI

PC192
47PF/50V

NPO 5%

12

NI

PC195
1500PF/50V

X7R 10%

1 2

VCC

AO

BO

GND

8
1

7
4

I_GPU

PC193
1500PF/50V

X7R 10%

1 2

GND

GND

+0P95V_GPU_R

+12VSA

12

I_GPU

PC175

0.1UF/25V

X7R 10%
mx_c0603

GND

+1P8V_MXM_FBR_A

+0P95V_GPU_25

+1P8V_MXM_GATE_A

12

GND

12

GND

I_GPU

PR416

4.7K

1%

I_GPU

PR262

4.7KOHM

1%

NOBOM

PJP54
SHORTPIN

1 2

NOBOM

PJP39
SHORTPIN

1 2

I_GPU

PQ25
SM3119NAUC-TRG

12

12

NI

NI

PC197
47PF/50V

NPO 5%

12

NI

PR454

14.7K

1%

1 2

A A

5

4

FEEBACK COMPENSATION

NI

PC198
1500PF/50V

X7R 10%

1 2

GND

3

2

PR281
33

mx_r0603

GND GND GND

I_GPU

PC210
10UF/6.3V

mx_c0805

<Variant Name>

<Variant Name>

<Variant Name>

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

NI

PCE34
100UF/6.3V

ESR=15m/Ir=2.7A

IPPLP-TH

IPPLP-TH

IPPLP-TH

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

1

+0P95V & +1P8V_MXM

+0P95V & +1P8V_MXM

+0P95V & +1P8V_MXM

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

92 97Friday, January 17, 2014

92 97Friday, January 17, 2014

92 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Vinafix.com

5

4

3

2

1

I_GPU

PR363

+VDDC_VCC_C+5V

D D

+VDDC_VCC_C

I_GPU

PR311

7.5K

1%

1 2

I_GPU

PR312
24K

1%

1 2

+3P3V

NI

PR324
10K

1%

1 2

+3P3V_GPU

12

I_GPU

PR315
10K

1%

1 2

C C

B B

NVDD_VID5[80]
NVDD_VID4[80]
NVDD_VID3[80]
NVDD_VID2[80]
NVDD_VID1[80]
NVDD_VID0[80]

GPUPW_EN[22,71,91]

NVVDD_PWRGD[91]

+3P3V_GPU

mx_r0402_small

1 2

mx_r0402_small

1 2

GND

I_GPU

PR1041
1K

NI

PR1048
1K

1%

1%

NI

PR129

+3P3V_GPU

NI

PR1046

1%

1K

mx_r0402_small

1 2

I_GPU

PR1081

1%

1K

mx_r0402_small

1 2

GND GND

0

+12VSA

+3P3V_GPU +3P3V_GPU

I_GPU

PR1080

1%

1K

mx_r0402_small

mx_r0402_small

1 2

1 2

NI

PR1045

1%

1K

mx_r0402_small

mx_r0402_small

1 2

1 2

GND

I_GPU

PR1042
1K

NI

PR1044
1K

1%

1%

12

I_GPU

PC231
1000PF/50V

X7R/+/-10%

GND

I_GPU

PR328

1

1 2

+3P3V_GPU

PR1043
1K

mx_r0402_small

1 2

PR1040
1K

mx_r0402_small

1 2

GND GND

NI

I_GPU

1%

1%

GND

PR322 0Ohm 5%NOBOM

12

PR370
10KOhm

I_GPU

+3P3V_GPU

mx_r0402_small

1 2

mx_r0402_small

1 2

2.2

mx_r0603_small

1 2

+VDDC_NTC_A

1 2

PR313 10KOhmI_GPU 1%

1 2

PC229 0.1UF/16V X7R 10%

NI

1 2

PR323 10KOhmI_GPU 1%

1 2

PR373 0

I_GPU

1%
I_GPU

1 2

PR1049

+3P3V_GPU

12

12

NI

PR368
10K

GND GND

I_GPU

PR329

154KOHM

1%

1 2

+VDDC_TON_A+VDDC_TON_L_A

1 2

PC239 0.1UF/16V X7R 10%

NI

1%

1K

I_GPU

PR1079

1%

1K

GND

12

GND

+VDDC_OCSET_A

PU13_DPRSLPVR_A

I_GPU

PR359
10KOhm

1%

+VDDC_PGOOD_A

12

NVDD_VID6_A

NVDD_VID6_A

I_GPU

PR1047

1%

1K

mx_r0402_small

1 2

I_GPU

PC228

2.2UF/6.3V

X5R 10%
mx_c0603

I_GPU

PC234

0.1UF/16V

X7R 10%

GND

I_GPU

PU306A
RT8153CLGQW

7

VCC

1

NTC/OLL

GND
GND

2

GND

3

GND

4

5

6

GND

17

GND

32

25
26
27
28
29
30
31

33

OCSET

DPRSLPVR

VRON

PGOOD

CLKEN#

TON

VRTT#

VID6
VID5
VID4
VID3
VID2
VID1
VID0

GND

PHASE
UGATE

ISEN_N

CMSET

DPRSTP#/OFS

I_GPU

PU306B
RT8153CLGQW

+5V

19

PVDD

BOOT

LGATE

PGND

COMP

VSEN

CM/PM

RGND

SOFT

GND8
GND7
GND6
GND5
GND4
GND3
GND2
GND1

12

I_GPU

PC227

2.2UF/6.3V

X5R 10%
mx_c0603

GND

24

+VDDC_BOOT_C +VDDC_BOOT_RC_C

22
23
20
21

GND

16

+VDDC_ISEN_A

ISEN

15

14

+VDDC_COMP_A

13

FB

12

11

10

9

8

18

41
40
39
38
37
36
35
34

For overshoot shutdown issue

+VDDC_FB_A

I_GPU

+VDDC_VSEN_A

+VDDC_CMSET_A

I_GPU

+VDDC_CM_A

I_GPU

+VDDC_RGND_A

I_GPU

+VDDC_SOFT_A

+VDDC_OFS_A

12

I_GPU

PC106

GND

GND

I_GPU

PR316

2.2Ohm

1%

mx_r0805_h24

1 2

I_GPU

PC235
47PF/50V

NPO 5%

1 2

1 2

I_GPU

PR327

1 2

PR325 10KOhmI_GPU

1 2

PRT2 10K 1%

1 2

PC240 0.01UF/25V X7R 10%

NI

1 2

PR336 20K 1%

1 2

PR100 56.2K

12

PC244 0.022UF/16V X7R/+/-10%I_GPU

12

PC245 0.01UF/25V X7R 10%

12

PC246 100PF/50V NPO 5%

NI

PR349

30.9KOhm

12

I_GPU

I_GPU

PR348

0.1UF/16V

10KOhm

1%

X7R 10%

For overshoot shutdown issue

GND

47KOHM

1%

1%

1 2

+VDDC_FB_R1_A

1%

+VDDC_VCC_C

I_GPU

PC230

0.1UF/25V

X7R 10%
mx_c0603

1 2

I_GPU

PC238

I_GPU

PR388
10KOhm

1%

12

I_GPU

PR371

5.1K

1%

1 2

12

GND

12

GND

120PF/50V

NPO 5%

NI

PC241
1000PF/50V

X7R 10%

NI

PC247
1000PF/50V

X7R 10%

+VDDC_PHASE_C [94]

+VDDC_UG_D [94]
+VDDC_LG_D [94]

I_GPU

PR372

12

I_GPU

PC232

0.1UF/16V

X7R 10%

12

I_GPU

PC233

0.1UF/16V

X7R 10%

GND

I_GPU

PR369

1 2

I_GPU

PR365
100 Ohm

12

NI

PC242

0.1UF/16V

X7R 10%

1 2

I_GPU

PR354
100 Ohm

12

1 2

+VDDC_VSEN_R_A

+VDDC_RGND_R_A

1 2

I_GPU

PR355

10KOhm

12

1%

NI

PC243

0.1UF/16V

X7R 10%

+VDDC_ISEN+_A [94]

+VDDC_ISEN-_A [94]

0

1 2

1 2

0

NOBOM

PJP30
SHORTPIN

NOBOM

PJP31
SHORTPIN

FB_VDDC [83]

+VDDC

GND

FB_GND [83]

A A

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A2

A2

A2

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

1

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

+VDDC CONTROLLER

+VDDC CONTROLLER

+VDDC CONTROLLER

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

93 97Friday, January 17, 2014

93 97Friday, January 17, 2014

93 97Friday, January 17, 2014

Rev

Rev

Rev

A00

A00

A00

Vinafix.com

5

D D

876

123

+VDDC_UGR_D

12

12

I_GPU

PR757

I_GPU

PR759

8.2KOHM

8.2KOHM

C C

+VDDC_UG_D[93]

+VDDC_PHASE_C[93]

+VDDC_LG_D[93]

+VDDC

I_GPU

PR78

I_GPU

PR79

1 2

1 2

0

mx_r0805

0

mx_r0805

12

GND GND

On Top Socket eadge

12

+VDDC

NI

PC108
1000PF/50V

X7R/+/-10%

NI

PC110
1000PF/50V

X7R/+/-10%

876

123

GND GND

On Top Socket Cavity

54

5
D

S

54

5
D

S

PQ101
BSC889N03LS

Id=45A/Pd=28W

G

G

4

I_GPU

I_GPU

PQ106

NTMFS4839NHT1G

GND

876

123

876

123

54

5
D

S

54

5
D

S

I_GPU

PQ105
BSC889N03LS

Id=45A/Pd=28W

G

I_GPU

PQ107

NTMFS4839NHT1G

G

+VDDC

12

I_GPU

PC640571
10UF/25V

mx_c0805
MLCC/+/-10%

GND GND

12

I_GPU

PR758
1 Ohm

5%
mx_r1206

VDDC_SN

12

I_GPU

PC790
4700PF/50V

X7R 10%
mx_c0603

+VDDC_ISEN+_A[93]
+VDDC_ISEN-_A[93]

12

I_GPU

PC289
10UF/25V

mx_c0805
MLCC/+/-10%

12

NI

PC791
680PF/50V

X7R 10%

GND

1 2

I_GPU

PL123

0.3uH/40A/72A

DCR=0.88mohm

NOBOM

PJP408
SHORTPIN

3

+VDDC
TDC=25A
Imax=37.5A

+12VSA

Fsw = 300kHz
Irms=6.48A
Delta I = 3.24A
ripple = 30mV
OCP = 30A
Eff=93%
Iin=3.57A
H/S =1.4W
L/S = 0.92 W

+VDDC

21

NOBOM

PJP407
SHORTPIN

1 2

2

1

B B

+VDDC

A A

I_GPU

12

PC111
22UF/6.3V

X5R 20%
mx_c0805_small

I_GPU

12

PC125
22UF/6.3V

X5R 20%
mx_c0805_small

I_GPU

12

PC100
22UF/6.3V

X5R 20%
mx_c0805_small

I_GPU

12

PC126
22UF/6.3V

X5R 20%
mx_c0805_small

I_GPU

12

PC112
22UF/6.3V

X5R 20%
mx_c0805_small

I_GPU

12

PC127
22UF/6.3V

X5R 20%
mx_c0805_small

NI

12

PC113
22UF/6.3V

X5R 20%
mx_c0805_small

+VDDC

I_GPU

12

PC128
22UF/6.3V

X5R 20%
mx_c0805_small

GND

5

I_GPU

12

PC114
22UF/6.3V

X5R 20%
mx_c0805_small

I_GPU

12

PC129
22UF/6.3V

X5R 20%
mx_c0805_small

GNDGND

On Bottom Socket CavityOn Bottom Socket eadge

GND

NI

12

PC120
22UF/6.3V

X5R 20%
mx_c0805_small

I_GPU

12

PC130
22UF/6.3V

X5R 20%
mx_c0805_small

I_GPU

PCE223
560UF/6.3V

8mohm 4.7A

NI

12

PC131
22UF/6.3V

X5R 20%
mx_c0805_small

12

I_GPU

+

PCE224
560UF/6.3V

8mohm 4.7A

I_GPU

12

PC132
22UF/6.3V

X5R 20%
mx_c0805_small

12

12

+

+VDDC

4

I_GPU

+

PCE225
560UF/6.3V

8mohm 4.7A

GND

I_GPU

12

PC133
22UF/6.3V

X5R 20%
mx_c0805_small

12

GND

I_GPU

+

PCE226
560UF/6.3V

8mohm 4.7A

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A2

A2

A2

Date: Sheet of

Date: Sheet of

3

2

Date: Sheet of

1

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

+VDDC CAP

+VDDC CAP

+VDDC CAP

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

94 97Friday, January 17, 2014

94 97Friday, January 17, 2014

94 97Friday, January 17, 2014

Rev

Rev

Rev

A00

A00

A00

Vinafix.com

5

D D

R_Volume

3

12

D11
AZ2025-01H

I_Sidekey

Volume

S_GND

C C

R_Bright

12

D13
AZ2025-01H

I_Sidekey

BRIGHT

113

2

I_Sidekey

113

2

I_Sidekey

TACT_SWITCH_4P

442

SW3

3

TACT_SWITCH_4P

442

SW4

S_GND

S_GND

4

HF P/N: 12X902050B30
1209-008C000
1209-007V000

HF P/N: 12X902050B30
1209-008C000
1209-007V000

3

HDD LED

2

LED1

+

R_HDD_LED+ R_HDD_LED_IN#

1 2

I_Sidekey

WHITE

12

D517
AZ2025-01H

I_Sidekey

S_GND S_GND

12

D518
AZ2025-01H

I_Sidekey

1

07XA030W0002

S_GND

B B

A A

R_MODE_ON

12

S_GND

D14
AZ2025-01H

I_Sidekey

5

Mode

3

113

TACT_SWITCH_4P

442

SW2

2

I_Sidekey

S_GND

HF P/N: 12X902050B30
1209-008C000
1209-007V000

4

R_Bright
R_Volume
R_MODE_ON

R_HDD_LED+
R_HDD_LED_IN#

PPID1

40X4_WHITE

I

3

6/22

修改成

R/A connector (

10

9
8
7
6
5
4
3
2
1

WTOB_CON_10P

I_Sidekey

S_GND S_GND

機構要求

CON8

12

SIDE2
10
9
8
7
6
5
4
3
2
1

11

SIDE1

)

PEGATRON DT-MB RESTRICTED SECRET

SIDE KEY

SIDE KEY

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

SIDE KEY

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

95 97Friday, January 17, 2014

95 97Friday, January 17, 2014

1

95 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev

Vinafix.com

5

4

3

2

1

Iin=1.48A

VIN_+12V_CVB

D D

PCON8

WAFER_HD_1X9P

I_CVB

intrusion

P467

45

WtoB_CON_1X3P

HOLD1

1
2
3

HOLD2

NI

C_GND_CVB

C C

C_GND_CVB

1
2
3
4
5

EN_A_CVB

6

DBRT_A_CVB

7

INTRUD_CBL_DET#_ID0

8

Alarm_open#_ID1

9

ID2_CVB VIN_A_CVB

C_GND_CVB

C_GND_CVB

C_GND_CVB

12

12

R60379

R60378

0 Ohm

0 Ohm

5%

5%

NI

NI

C_GND_CVB

C_GND_CVB

C_GND_CVB

C_GND_CVB

C_GND_CVB

C_GND_CVB

[LG]106.1mA~112.65mA

[SAM]116.22~123.39mA

Iin,max=2.01A

12

C9400

0.1UF/25V

X7R 10%

I_CVB

C_GND_CVB

EN_A_CVB

DBRT_L_CVB

C_GND_CVB

MLCC/+/-10%

MLCC/+/-10%

ISET_0_CVB

ISET_1_CVB

12

1%

1%

C941294
10UF/25V

X5R 10%

I_CVB

C9437

0.47UF/16V

C9438

0.47UF/16V

I_CVB

1%

I_CVB

1%

I_CVB

5%

12

I_CVB

I_CVB

12

I_CVB

R37572
10MOhmI_CVB5%

12

I_CVB

C_GND_CVBC_GND_CVB

12

12

12

12

12

12

12

C9399
10UF/25V

X5R 10%

I_CVB

C94280.1UF/25V

12

R37563

1%

200 Ohm

R37530
20KOHM

R37629
178KOHM

R37532
100KOHM

R37533
20KOHM

NI

R37636

8.45KOhm

R37646

7.68KOHM

I_CVBMLCC/+/-10%

VCC_A_CVB

ISET_CVB

12

I_CVB

COMP_CVB

C_GND_CVB

U100MP3394EF-LF-Z

15

16

1

2

5

7

3

6

17

I_CVB

L83

21

47uH

I_CVB

INDUCTOR I(sat) = 3.5A
INDUCTOR I(rms) = 3.3A

14

Gate_A_CVB Gate_B_CVB

GATE

VIN

VCC

COMP

EN

OSC

BOSC

DBRT

ISET

GND2

ISENSE

GND1

LED1

LED2

LED3

LED4

13

ISENSE_1_CVB

R37539

0.15Ohm
R37553

4

0.15Ohm

C_GND_CVB

12

OVP_CVB

OVP

11

ILED1_CVB

10

ILED2_CVB

9

ILED3_CVB

8

ILED4_CVB

SW_1

I_CVB

2.2 Ohm

12

12

I_CVB

I_CVB

1%

1%

FDS86141

4
356
2
1

Q854

Pd=0.43W

R37607

1 2

I_CVB

OCP ref =234mV/RISNS*0.8
OCP ref =2.5A

C_GND_CVB

C_GND_CVB

C_GND_CVB

C_GND_CVB

ILED(mA)=971.7/(RSET+0.4)

VIN_+12V_CVB

12

UM6K1N

12

100K

I_CVB

R60380
100K

1%

Q867B

I_CVB

R60381

1%

I_CVB

5

12

I_CVB

R60374
100K

1%

DBRT_L_CVB

34

12

R37501

37.4KOhm

1%

I_CVB

NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM

NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM

1
1
1
1
1
1
1
1
1

1
1
1
1
1
1

PT3 TPC26b
PT18 TPC26b
PT16 TPC26b
PT17 TPC26b
PT20 TPC26b
PT19 TPC26b
PT2 TPC26b
PT1 TPC26b
PT9 TPC26b

PT10 TPC26b
PT11 TPC26b
PT12 TPC26b
PT13 TPC26b
PT14 TPC26b
PT15 TPC26b

VIN_+12V_CVB
VIN_+12V_CVB
C_GND_CVB
C_GND_CVB
EN_A_CVB

B B

DBRT_L_CVB
INTRUD_CBL_DET#_ID0
Alarm_open#_ID1
ID2_CVB

ILED1_CVB
VLED_H_CVB
VLED_H_CVB
ILED2_CVB
ILED3_CVB
ILED4_CVB

A A

H32

1
2
3
4

GND2

1
2
3
4

GND1

CHSET_0_CVB[96] CHSET_1_CVB[96]

5

NP_NC
GND1
GND2
GND3

C315D157N

I_CVB

H33

NP_NC
GND1
GND2
GND3

C315D157N

I_CVB

12

GND8
GND7
GND6
GND5
GND4

GND8
GND7
GND6
GND5
GND4

NI

C9456
100PF/50V

NPO 5%

12

9
8
7
6
5

9
8
7
6
5

R37642
100KOHM

1%
I_CVB

GND2

GND1

[LG]

Q864A

UM6K1N

C_GND_CVB

2

I_CVB

R60377

1 2

0 Ohm

5%
I_CVB

R60376

1 2

0 Ohm

5%
I_CVB

ISET_0_CVB OVPSET_0_CVB

61

Q864B

UM6K1N

34

5

I_CVB

GND2C_GND_CVB

GND1

Q866B

UM6K1N

R60390

4.42KOHMNI1%

34

5

I_CVB

C_GND_CVB

4

I_CVB

61

Q867A

UM6K1N

I_CVB

R60375
20KOHM

5%

2

12

NI

C941292
100PF/50V

NPO 5%

C_GND_CVB C_GND_CVBC_GND_CVB C_GND_CVBC_GND_CVBC_GND_CVB

DBRT_A_CVB

12

12

Alarm_open#_ID1

Alarm_open#_ID1 : 1.6V Alarm_open#_ID1 : 0V

G

SD

R37620

100KOHM1%

R37632

100KOHM1%

R37634

100KOHM1%

R37635

100KOHM1%

3

OVP ref =1.23V

7
8

C_GND_CVB

12

I_CVB

12

I_CVB

12

NI

ILED4_A_CVB

12

NI

VIN_+12V_CVB

C_GND_CVBC_GND_CVB C_GND_CVB C_GND_CVB C_GND_CVB

D509

BR29

I_CVB

12

C_GND_CVB

C_GND_CVB

21

C9418
100PF/50V

NPO 5%

I_CVB

VLED_H_CVB

12

12

2.2NF/100V

R37537

C9439

249KOhm

I_CVB

1%

I_CVB

C_GND_CVB C_GND_CVB

12

12

R37638

R37651

15KOhm

I_CVB

8.06KOHM

1%

I_CVB

1%

C_GND_CVB

ILED3_A_CVB

1 2

R37633
0 Ohm

5%

I_CVB

1 2

R37428 10KOhm

R37379 39KOHM

C9341 0.1UF/25V

I_CVB

I_CVB

I_CVB

12

12

5%

5%

X7R 10%

[SAM]

61

Q865A

UM6K1N

2

R37647
100KOHM

1%
I_CVB

I_CVB

12

12

NI

C9457
100PF/50V

NPO 5%

C_GND_CVB C_GND_CVB C_GND_CVB

12

12

VIN_+12V_CVB

12

C9453

2.2UF/100V

I_CVB

R37652

16.5KOHM

OVP_GATE_CVB

C9454

2.2UF/100V

I_CVB

C_GND_CVB C_GND_CVB C_GND_CVB C_GND_CVB

I_CVB

OVPSET_1_CVB

OVPSET_0_CVB

S

2

G

[SAM]
[LG]

VIN_+12V_CVB

ISET_1_CVB OVPSET_1_CVB

34

Q865B

UM6K1N

UM6K1N

5

I_CVB

12

C9455

2.2UF/100V

I_CVB

[SAM]38.48V~42V
[LG]57.06V~62.31V

S

2

D

32

3

Q857

1

GF609SR-R

1

I_CVB

CHSET_1_CVB[96]

CHSET_0_CVB[96]

1 2

I_CVB

Alarm_open#_ID1

61

Q866A

2

I_CVB

C_GND_CVB

2

12

0.1UF/100V
C941290

NI

D

32

3

G

Q855

1

GF609SR-R

1

I_CVB

ILED2_A_CVB

R37641
100KOHM1%

C_GND_CVB C_GND_CVB

8

10

ILED1_A_CVB

SIDE19SIDE2

12

0.1UF/100V
C941291

NI

CON8007

112233445566778

WTOB_CON_8P

I_CVB

12

0.1UF/100V
C941293

NI

C_GND_CVB

Panel(23")

ILED.typ

VF

OVP

LG

110/120 mA

52.7/56.1V

59.64V

Pin NO. 4

ID 1 1

ID Level(V) 1.6 0

<CORE DESIGN>

<CORE DESIGN>

<CORE DESIGN>

PEGATRON RESTRICTED SECRET

Engineer:

Engineer:

PEGATRON COMPUTER INC

PEGATRON COMPUTER INC

PEGATRON COMPUTER INC

Size Project Name

Size Project Name

Size Project Name

A2

A2

A2

Date: Sheet of

Date: Sheet of

Date: Sheet of

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

1

120/130 mA

CONVERTER BOARD

CONVERTER BOARD

CONVERTER BOARD

Title :

Title :

Title :

SAM

34/37V

40.21V

4

1 0

Bell_Yang

Bell_Yang

Bell_Yang

96 97Friday, January 17, 2014

96 97Friday, January 17, 2014

96 97Friday, January 17, 2014

Rev

Rev

Rev

A00

A00

A00

Vinafix.com

5

4

3

2

1

PT21
PT22
PT23
PT24
PT25

PT36
PT37
PT38
PT39
PT40
PT41
PT42
PT43
PT44
PT45

PT72
PT70
PT71

PT155
PT154

+3P3VSB+5VSB

1
1
1
1
1

+1P5V_DUAL

1
1
1
1
1
1
1
1
1
1

+3P3V

1
1
1

1
1

NOBOM
NOBOM
NOBOM
NOBOM
NOBOM

NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM

NOBOM
NOBOM

NOBOM
NOBOM

NOBOM
NOBOM
NOBOM
NOBOM

NOBOM
NOBOM

NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM

NOBOM
NOBOM
NOBOM
NOBOM
NOBOM

NOBOM
NOBOM
NOBOM
NOBOM
NOBOM

NOBOM

PT153
PT152

D D

C C

B B

A A

1

PT139

1

PT144

1

PT135

1

PT134

1

PT136

1

PT143

1

PT133

1

PT138

1

PT137

1

PT140

+5V_DUAL

1

PT30

1

PT31

1

PT32

1

PT33

1

PT34

+5V

1

PT48

1

PT46

1

PT35

1

PT47

1

PT49

1

ST137

CR_1V8 CR_3V3

1
1

NOBOM
NOBOM
NOBOM
NOBOM
NOBOM

NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM

NOBOM
NOBOM
NOBOM

NOBOM
NOBOM

1

PT148

PT146
PT142
PT147
PT145
PT141

PT50
PT51
PT52
PT53
PT54
PT55
PT56
PT57
PT58
PT59

PT73
PT74

PT150
PT151

+1P05V_PCH

1
1
1
1
1

+VCORE

1
1
1
1
1
1
1
1
1
1

+3V_WLAN

1
1

+3P3V_MSATA

1
1

NOBOM

NOBOM

NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM

NOBOM
NOBOM
NOBOM
NOBOM

PT79

PT80

PT60
PT61
PT62
PT63
PT64
PT65
PT66
PT67
PT68
PT69

PT78
PT76
PT77
PT75

+3P3V_BG

1

+1P5V_PCH

1

+12V_CPU

1
1
1
1
1
1
1
1
1
1

+12V_HDD

1
1
1
1

NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM

NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM

NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM

NOBOM
NOBOM
NOBOM
NOBOM

NOBOM

PT102
PT94
PT99
PT93
PT95
PT100
PT96
PT97
PT101
PT98

PT111
PT104
PT109
PT103
PT105
PT110
PT108
PT106
PT112
PT107

PT120
PT113
PT114
PT118
PT117
PT121
PT115
PT119
PT116
PT122
PT127
PT124
PT123
PT125
PT126
PT128

PT129
PT130
PT131
PT132

PT149

1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1

1

NOBOM

NOBOM

NOBOM

NOBOM

NOBOM

+12VSA

NOBOM

NOBOM
NOBOM
NOBOM
NOBOM

NOBOM

GND

PT81

PT82

PT83

PT90

PT91

PT92

PT87
PT85
PT86
PT84

PT88

+1P05V_ME+VDDC

1

+VTT_DDR

1

+3P3V_GPU

1

+3P3V_ME

1

+3P3V_LAN

1

+1P5V_GPU

1

+0P95V

1
1
1
1

+1P8V_MXM

1

PEGATRON DT-MB RESTRICTED SECRET

TP

TP

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

IPPLP-TH

IPPLP-TH

IPPLP-TH

TP

Shrek_Tseng

Shrek_Tseng

Shrek_Tseng

97 97Friday, January 17, 2014

97 97Friday, January 17, 2014

1

97 97Friday, January 17, 2014

A00

A00

A00

Rev

Rev

Rev