Pegatron IPPLP-RH Schematic
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IPPLP-RH
PAGE
01
02
03
D D
04
05
06
07
08~13
14
15~16
17
18
19~24
25
26
27
28
29
C C
30
31
32
33
34
35
36
37
38
39
40
41
42
43
B B
44
45
46
47
48
49
50
51~52
53
54
55
56
57
58
A A
59
60
61
62
63
64~66
67
BLOCK DIAGRAM
CLOCKS DISTRIBUTION
SIGNAL & RESET MAP
CHANGE HISTORY
POWER FLOW
POWER DISTRIBUTION
POWER SEQUENCE
Haswell LGA-1150
VGA DEBUG
DDR3 CHANNEL A&B
DDR3 TERMINATION A&B
N/A
INTEL_PCH(1~6)
N/A
SM BUS & SPI ROM
ME DISABLE
MINI-PCIE SLOT-1(WLAN)
MINI-PCIE SLOT-3(mSATA)
CARD READER
INTEL CLARKVILLE
LAN JACK
SIDE USB3.0 PORT
REAR USB3.0 PORT
REAR USB3.0 PORT
REAR USB2.0 PORT
TOUCH & WEBCAM
N/A
SATA CONN
AUDIO CODEC ALC3661
AMP
REAR LINE OUT& GHS CONNECTOR
N/A
SIO SMSC5555
N/A
SCREW HOLE
FAN CIRCUIT
COM PORT
DEBUG LED
APS/LPC DEBUG
SCALAR_TSUMU88BDC2
LVDS & CONVERTER CONN
SCALAR LCD ENABLE
FRONT PANEL
HDMI IN
HDMI LEVEL SHIFT
HDMI OUT
G-SENSOR
DP REDRIVER
DP CONN
TPM
DC IN
VCORE CONTROLLER
3P3_LAN,12V,1P5V_PCH,3P3V_BG
TITLE
5
Revision: B00
GPU MARS
USB3.0 x 4
USB2.0 x 2
USB3.0 x 2
<Rear>
<Side>
Intel WGI217LM
10/100/1000
WLAN/MSATA
(NGFF)
68
69
70
71
72
73 N/A
74 +3P3V_WLAN & +3P3V_mSATA
75
76
77
78
79~85
86~89 VRAM
90 +1P8V
92
5V, 3P3V, 1P5V, 5V_Dual
+1P05V_PCH & +1P22V
+5VSB, +3P3VA
+5VSB, +12VSB
+1P5V_DUAL , +VTT_DDR
N/A
CPU XDP DEBUG CONNECTOR
PCH XDP DEBUG CONNECTOR
N/A
GPU
3P3V_GPU&+0P95V91
+1P35V_GPU & +1P05V_ME 95 TP
4
WiFi
MSATA
Webcam
Touch
RJ 45
Card Reader
OZ777FJ2LN
XDP
PCIE X8
USB
PCIE BUS
100MHz
PCIE BUS
PCIE BUS/SATA
XDP
SMSC5555
93~94 VDDC CONTROLLER
95 SIDE KEY
96 CONVERTER BOARD
3
Intel Processor
Haswell
LGA-1150 Pin Socket
TDP = 65W
DMI
INTEL
Lynx Point
PCH
708 Pin
23mm X 22mm
LPC BUS
33MHz
ST33ZP24AR28PVSP
LPC BUS
33MHz
TPM
2
Channel A
Channel B
DDIB(Port B)
TMDS(Port C)
TMDS(Port D)
PS8201 HDMI OUT
SATA BUS
SPI
HD Audio
DIGI
MIC
PEGATRON DT-MB RESTRICTED SECRET
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Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Dual Channel DDR3 MEMORY x 2 Slots
DDR3 SO-DIMM 1333/1600
DDR3 SO-DIMM 1333/1600
PS8330B
TSUMU88BDC2
LVDS
HDMI IN
HDMI 3.0G
SATA 3.0
SATA 3.0
SPI FLASH
ALAZIA AUDIO
ALC3661
UNIVERSAL JACK
64Mb+32Mb
REAR LINE OUT
(RE-TASKING)
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
IPPLP-TH
IPPLP-TH
IPPLP-TH
1
DP
23" LCD
TPA3131MP
SPK.
5W per
Channel
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
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D D
Intel Processor
Haswell
LGA-1150 Pin Socket
Intel
Platform Controller Hub
Lynx Point
CK_100M_PE16/#
NVidia
GPU (N14E-GE)
CLKOUT_PEG_A_P/N
BCLK/#_0
SSC_DPLL_REF_CLK/#
SB_CK[0~1]/#
C C
SA_CK[0~1]/#
M_CHA_CLK[0~1]/#
M_CHB_CLK[0~1]/#
B B
DPLL_REF_CLK/#
BCLK_ITP_P/N
XMM1
XMM2
CPU XDP
PCH XDP
CK_100M_DMI/#
CK_135M_DP/#
CK_135M_DPNS/#
CK_100M_CPU_XDP
CLKOUT_DMI_P/N
CLKOUT_DP_P/N
CLKOUT_DPNS_P/N
CLKOUT_PCIE0_P/N
CLKOUT_PCIE1_P/N
CLKOUT_PCIE5_P/N
CLKOUT_PCIE2_P/N
CLKOUT_ITPXDP_P/N
CLKOUT_PCIE7_P/N
CLKOUTTFLEX2
HDA_BCLK
CLKOUTTFLEX3
CLKOUT_33MHZ2
SPI_CLK
CLKOUT_33MHZ3
CK_100M_PE1/#
CK_100M_PE2/#
CK_100M_PE2/#
RL_CK_100M_LAN/#
CK_48M_CR
AZ_BITCLK (24MHz)
CK_48M_SIO
CK_33M_SIO
SPI_CLK
CK_33M_DEBUG
PCIEx1 Slot(Half)
PCIEx1 Slot(Full)
PCIEx1 Slot(Full)
REALTEK
RTL8111GA
CARD READER
AUDIO CODEC ALC663
SIO IT8772E
SPI ROM
LPC Debug Header
25 MHz
CLKOUT_33MHZ4
CKKIN_PCILOOPBACK
CK_33M_PCIFB
XTAL25_IN RTCX
A A
32.768KHz25MHz
5
4
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<CORE DESIGN>
<CORE DESIGN>
<CORE DESIGN>
PEGATRON DT-MB RESTRICTED SECRET
CLCOK DISTRIBUTION
CLCOK DISTRIBUTION
CLCOK DISTRIBUTION
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
IPPLP-TH
IPPLP-TH
IPPLP-TH
Engineer:
1
Shrek_Tseng
Shrek_Tseng
Shrek_Tseng
297Friday, January 17, 2014
297Friday, January 17, 2014
297Friday, January 17, 2014
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LAN 8111E
PERSTB
PCI_Express x 16
<23>PCIE_RST#
<23>PCIE_RST#
PWRGD
D D
PCI_Express x 1
PERST#
PCI_Express x 1
<23>PCIE_RST#
<23>PCIE_RST#
PCIE_RST#
PLTRST#
PERST#
<23>PCIE_RST#
<23>PCIE_RST#
EtronTech EJ168 USB3.0
P_RST_
Card Reader RTS5209-GR
PERST#
LPC DEBUG HEADER
<23>PLTRST_CPU#
Intel AMT 7.0 and DSW supported
RESET_SWITCH
PCH PROCESSOR
POWER_SWITCH
<4>PWRBTN#
ITE Tech SIO IT8772E
PANSWH#
PCIRST1#
HDA_RST#
AZ_RST#
RESET#
PCIRST#
C C
2X12 ATX PSU
<12>PSON#
PSON#
PWROK
B B
<14>ATX_PWRGD
PSON#
ATXPG_IN
LRESET#
KRST# RCIN#
RSMRST#
PWRON# PWRBTN#
SUSB#(S3#) SLP_S3#
SUSC#(S4#)
SUSWARN#
SUSACK#
DPWROK
RST_KB#
<7>RSMRST#
<4>SB_PWRBTN#
<11>SLP_S3#
<10>SLP_S4#
<8>SUS_WARN#
<9>SUS_ACK#
<3>PCH_DPWROK
<15>PWROK
<22>PLTRST#
PLTRST#
RSMRST#
SLP_S4#
SUSWARN#
SUSACK#
DPWROK
PWROK
DRAMPWROK
RTCRST#
PROCPWRGD
<1>RTCRST#
CPU SVID buffers are Hi-Z once +1P05V_CPUIO is
stable and UNCOREPWRGOOD = 0
PWRGD3
APWROK
<5>SLP_SUS#
SLP_SUS#
AUDIO
ALC663-VA4
SYS_RESET#
<16>DRAM_PWROK
BATTERY
<17>CPUPWRGD
<15~20>SVIDs
DBR#SYS_RESET#
RESET#
SM_DRAMPWROK
UNCOREPWRGOOD
VIDSOUT/VIDSCLK
VCORE
<13>
RT8204LGQW
ONBOARD POWER
STANDBY POWER
<6>
+5VSB
APWROK
SYS_PWROK
<21>VRM_PWRGD
+3P3VSB
A A
CHIP
<2>+5VA
RT8239CGQW
SOCKET or SLOT
5
4
3
Vcore Controller
VDIO/VCLK
VR_RDY
RT8859AGQW
VCORE
EN
2
<20>VCORE
<13>+1P05V_CPUIO
<CORE DESIGN>
<CORE DESIGN>
<CORE DESIGN>
PEGATRON DT-MB RESTRICTED SECRET
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
IPPLP-TH
IPPLP-TH
IPPLP-TH
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
1
SIGNAL&RESET MAP
SIGNAL&RESET MAP
SIGNAL&RESET MAP
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Schematics Change History
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3
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Version
Date
Comments
2012/11/19 PCIEX16 RVS(20121119_2100)
D D
C C
B B
A A
CAD Note:
Default component footprint is SMD 0402, Y5V, 5% type. Difference footprint show on schematics.
Property: BOM
I = Installed Part.
NI = Not Installed Part.
5
PROTO = PROTO Phase Only.
VP = Virtual Part.
4
3
2
<CORE DESIGN>
<CORE DESIGN>
<CORE DESIGN>
PEGATRON DT-MB RESTRICTED SECRET
CHANGE HISTORY
CHANGE HISTORY
CHANGE HISTORY
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
IPPLP-TH
IPPLP-TH
IPPLP-TH
Engineer:
1
Shrek_Tseng
Shrek_Tseng
Shrek_Tseng
497Friday, January 17, 2014
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497Friday, January 17, 2014
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+12V_CPU
D D
+12VSA
C C
TPS51631+CSD97374
Vcore:3Phase
TPS51225
H/N-MOS 9mOhmx1
L/N-MOS 6mOhmx1
TPS51225
H/N-MOS 9mOhmx1
L/N-MOS 6mOhmx1
SPDT/Switch
18.62A
SPDT/Switch
14.6A
SPDT/Switch
SPDT/Switch
SPDT/Switch
SPDT/Switch
+VDD Imax=90A/TDC=120A (S0,S1)
+12V Imax=9A/TDC=6.3A (S0,S1)
+5VSB Imax=0.1A (S0~S5)
+5V_DUAL Imax=12.1A/TDC=8.5A
(S0,S1,S3)
+5V Imax=6.42A/TDC=4.5A (S0,S1)
+3P3VA Imax=0.44A/TDC=0.3A
(S0-S5)
+3P3V Imax=8.57A/TDC=6A
(S0,S1)
+3P3V_ME Imax=0.045A (S0,S1)
+3P3V_LAN Imax=0.188A (S0~S5)
SPDT/Switch
SPDT/Switch
B B
TPS51216
H/N-MOS 9mOhmx1
L/N-MOS 6mOhmx2
TPS51216
RT9025
RT9025
+3P3VSB Imax=5.4A/TDC=3.8A
(S0~S5)
+3P3V_BG Imax=0.028A (S0~S5)
+1P5V_DUAL Imax=11.74A/TDC=8.2A
(S0,S1,S3)
+VTT Imax=1.57A/TDC=1.1A (S0,S1)
+1P5V_PCH Imax=0.357A/TDC=0.258A
(S0,S1)
+1P50V_PCH Imax=1A/TDC=0.65A
(S0,S1)
+1P22V Imax=0.4A/TDC=0.28A
(S0,S1)
0.62A
A A
RT8153
H/N-MOS 9mOhmx2
L/N-MOS 6mOhmx2
5.3A
+NVVD Imax=37.5A/TDC=25A (S0,S1)
PEGATRON DT-MB RESTRICTED SECRET
POWER FLOW
POWER FLOW
POWER FLOW
Title :
Title :
Switching
SPDT/SwitchLinear
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
IPPLP-TH
IPPLP-TH
IPPLP-TH
Title :
Engineer:
Engineer:
Engineer:
1
Shrek_Tseng
Shrek_Tseng
Shrek_Tseng
597Friday, January 17, 2014
597Friday, January 17, 2014
597Friday, January 17, 2014
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D D
+VCORE
VDDQ
VCCST
+1P05V_PCH
+1P05V_PCH
-> 95A(TDC) - 65W
-> 4.2A(Imax) - W
-> 300mA(Imax) - W
PCH Lynx Point
-> 1.312A (VCC)- W
-> 0.306A(VCCCLK) - W
+12V
+3P3V
+3P3VSB
+12V
+3P3V
+3P3VSB
+1P05V_PCH
-> 3.629A(VCCIO) - W
CPU Sandy Bridge
C C
+1V_CPU2PCH
+1P05V_ME
-> 0.004A(V_PROC_IO) - W
-> 0.67A(VCCASW) - W
+3P3VSB
+1P05V_LAN
+1P5V_PCH
PCI Express x 1
-> 5A - 60W
-> 3A - 9.9W
WAKE -> 0.375A - 1.24W
No WAKE-> 20mA - 66mW
PCI Express x 16
-> 5.5A - 66W
-> 3.0A - 9.9W
WAKE -> 0.375A - 1.24W
No WAKE-> 20mA - 66mW
REALTEK 8111FA
-> 70mA - 231mW
-> 300mA - 315mW
+5V_DUAL_B/F
+5V
+12V
+3P3V_ME
Rear(USB3*4) -> 4A - 20W
Front(USB3*1 USB2*1) -> 2.5A - 12.5W
Internal(USB2) -> 3A - 15W
-> mA - mW
-> mA - mW
-> 1.2A - 14.4W
-> 40mA - 132mW
USB 12 PORTS
HDMI
FANS
SPI
-> 0.183A(VCCVRM) - W
+1P5V_PCH
+3P3V_BG
+3P3V
+3P3V
B B
+3P3V_ME
+3P3VSB
-> 0.0133A(VCC3_3) - W
-> 0.133A(VCC3_3) - W
-> 0.055A(VCCCLK3_3) - W
-> 0.022A(VCCSPI) - W
-> 0.261A(VCCSUS3_3) - W
-> 0.07A(VCCDAC1_5) - W
+3P3V
+5VSB
+3P3V
SIO IT8772E
-> 200mA - mW
ALC663 Codec
-> 45mA - 225mW
-> 25mA - 82.5mW
-> 0.01(VCCSUSHDA)A - W
+3P3VA
+BATT
A A
5
-> 0.015A(VCCDSW3_3) - W
RTC(G3) -> 6uA - 0.0198mW
<CORE DESIGN>
<CORE DESIGN>
<CORE DESIGN>
PEGATRON DT-MB RESTRICTED SECRET
POWER DISTRIBUTION
POWER DISTRIBUTION
POWER DISTRIBUTION
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
4
3
2
Date: Sheet of
IPPLP-TH
IPPLP-TH
IPPLP-TH
Engineer:
1
Shrek_Tseng
Shrek_Tseng
Shrek_Tseng
697Friday, January 17, 2014
697Friday, January 17, 2014
697Friday, January 17, 2014
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Rev
Rev
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S5 to S0 Power Sequence
DPWROK
SLP_SUS#
+5VSB / +3P3VSB
D D
RSMRST#
SUSWARN#
SUSACK#
SLP_LAN#
SLP_A#
+1P05V_ME
SLP_S5#
SLP_S4#
SLP_S3#
APWROK
C C
+12V / +5V
+3P3V
+1P5V_DUAL
+1P05V_CPUIO
+1P8V_SFR
VCCSA_VID
+0P925V_SA
VCORE EN
B B
VIDSCLK / VIDSOUT
VIDALERT#
ATX_PWRGD
BCLK / PCIE CLOCKS
DRAM_PWROK
CPUPWRGD
+VCORE
VRM_PWRGD
A A
PLTRST#
5
DSW exit
30uS
30uS
>1mS
PSU: <=20mS
=500mS
=50mS
UNCOREPWRGOOD must be stable (low) at this time
CPU SVID buffers are Hi-Z once VCCIO is
stable and Uncorepowergood = 0
CPU SVID buffers are Hi-Z once VCCIO is
stable and Uncorepowergood = 0
PSU: 100ms~500ms
4
UNCOREPWRGOOD assertion
VCCSA_VID[0] FINAL
Recommended that +0P925V_SA ramp after +1P05V_CPUIO has ramped to ensure VCCSA_VID[0] is stable
<5mS
Typ 60uS
MISC ACK0/1...
Set VID
slow packet status packet
ACK0/1...
Get Reg
ACK0/1...
<600uS
<1uS
1mS
Min 10 PCIe BCLKs
<5uS
<2mS
3
2
+0P925V_SA FINAL
Pay
load
>400uS
5mS
<5mS
1~100mS
<CORE DESIGN>
<CORE DESIGN>
<CORE DESIGN>
PEGATRON DT-MB RESTRICTED SECRET
POWER SEQUENCE
POWER SEQUENCE
POWER SEQUENCE
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
IPPLP-TH
IPPLP-TH
IPPLP-TH
Engineer:
1
Shrek_Tseng
Shrek_Tseng
Shrek_Tseng
797Friday, January 17, 2014
797Friday, January 17, 2014
797Friday, January 17, 2014
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M_CHA_DQ[0..63][15]
M_CHA_DQS0[15]
M_CHA_DQS0#[15]
D D
M_CHA_DQS1[15]
M_CHA_DQS1#[15]
M_CHA_DQS2[15]
M_CHA_DQS2#[15]
C C
M_CHA_DQS3[15]
M_CHA_DQS3#[15]
M_CHA_DQS4[15]
M_CHA_DQS4#[15]
B B
A A
5
M_CHA_DQS5[15]
M_CHA_DQS5#[15]
M_CHA_DQS6[15]
M_CHA_DQS6#[15]
M_CHA_DQS7[15]
M_CHA_DQS7#[15]
4
M_CHA_DQ0
M_CHA_DQ1
M_CHA_DQ2
M_CHA_DQ3
M_CHA_DQ4
M_CHA_DQ5
M_CHA_DQ6
M_CHA_DQ7
M_CHA_DQ8
M_CHA_DQ9
M_CHA_DQ10
M_CHA_DQ11
M_CHA_DQ12
M_CHA_DQ13
M_CHA_DQ14
M_CHA_DQ15
M_CHA_DQ16
M_CHA_DQ17
M_CHA_DQ18
M_CHA_DQ19
M_CHA_DQ20
M_CHA_DQ21
M_CHA_DQ22
M_CHA_DQ23
M_CHA_DQ24
M_CHA_DQ25
M_CHA_DQ26
M_CHA_DQ27
M_CHA_DQ28
M_CHA_DQ29
M_CHA_DQ30
M_CHA_DQ31
M_CHA_DQ32
M_CHA_DQ33
M_CHA_DQ34
M_CHA_DQ35
M_CHA_DQ36
M_CHA_DQ37
M_CHA_DQ38
M_CHA_DQ39
M_CHA_DQ40
M_CHA_DQ41
M_CHA_DQ42
M_CHA_DQ43
M_CHA_DQ44
M_CHA_DQ45
M_CHA_DQ46
M_CHA_DQ47
M_CHA_DQ48
M_CHA_DQ49
M_CHA_DQ50
M_CHA_DQ51
M_CHA_DQ52
M_CHA_DQ53
M_CHA_DQ54
M_CHA_DQ55
M_CHA_DQ56
M_CHA_DQ57
M_CHA_DQ58
M_CHA_DQ59
M_CHA_DQ60
M_CHA_DQ61
M_CHA_DQ62
M_CHA_DQ63
4
AE39
AE38
AD38
AD39
AF38
AF39
AD37
AD40
AF37
AF40
AJ39
AJ38
AH40
AH39
AK38
AK39
AH37
AH38
AK37
AK40
AN39
AN38
AM40
AM39
AP38
AP39
AM37
AM38
AP37
AP40
AV36
AU36
AV37
AW37
AU35
AV35
AT37
AU37
AT35
AW35
AV5
AW5
AY6
AU6
AV4
AU4
AW6
AV6
AW4
AY4
AP3
AP2
AR1
AR4
AN3
AN4
AR2
AR3
AN2
AN1
AK3
AK2
AL1
AL4
AJ3
AJ4
AL2
AL3
AJ2
AJ1
AF3
AF2
AG1
AG4
AE3
AE4
AG2
AG3
AE2
AE1
I
XU1A
LGA_1150P
SA_DQS0
SA_DQSN0
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQS1
SA_DQSN1
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQS2
SA_DQSN2
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQS3
SA_DQSN3
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQS4
SA_DQSN4
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQS5
SA_DQSN5
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQS6
SA_DQSN6
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQS7
SA_DQSN7
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
DDR3_A
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
SA_WE#
SA_CAS#
SA_RAS#
SA_BS0
SA_BS1
SA_BS2
SA_CS#0
SA_CS#1
SA_CS#2
SA_CS#3
SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3
SA_ODT0
SA_ODT1
SA_ODT2
SA_ODT3
SA_CK0
SA_CKN0
SA_CK1
SA_CKN1
SA_CK2
SA_CKN2
SA_CK3
SA_CKN3
SM_DRAMRST#
RSVD16
RSVD13
RSVD19
SA_DQS8
SA_DQSN8
SA_ECC_CB0
SA_ECC_CB1
SA_ECC_CB2
SA_ECC_CB3
SA_ECC_CB4
SA_ECC_CB5
SA_ECC_CB6
SA_ECC_CB7
AU13
AV16
AU16
AW17
AU17
AW18
AV17
AT18
AU18
AT19
AW11
AV19
AU19
AY10
AT20
AU21
AU11
AU9
AU12
AV12
AY11
AT21
AU14
AV9
AU10
AW8
AV22
AT23
AU22
AU23
AW10
AY8
AW9
AU8
AY15
AY16
AW15
AV15
AV14
AW14
AW13
AY13
AK22
AW12
AV20
AW27
AV32
AU32
AW33
AV33
AU31
AV31
AT33
AU33
AT31
AW31
3
3
M_CHA_MAA0
M_CHA_MAA1
M_CHA_MAA2
M_CHA_MAA3
M_CHA_MAA4
M_CHA_MAA5
M_CHA_MAA6
M_CHA_MAA7
M_CHA_MAA8
M_CHA_MAA9
M_CHA_MAA10
M_CHA_MAA11
M_CHA_MAA12
M_CHA_MAA13
M_CHA_MAA14
M_CHA_MAA15
M_CHA_WE# [15]
M_CHA_CAS# [15]
M_CHA_RAS# [15]
M_CHA_BA0 [15]
M_CHA_BA1 [15]
M_CHA_BA2 [15]
M_CHA_CS#0 [15]
M_CHA_CS#1 [15]
M_CHA_CKE0 [15]
M_CHA_CKE1 [15]
M_CHA_ODT0 [15]
M_CHA_ODT1 [15]
M_CHA_CLK0 [15]
M_CHA_CLK0# [15]
M_CHA_CLK1 [15]
M_CHA_CLK1# [15]
2
M_CHA_MAA[0..15] [15]
2
DDR3_DRAMRST# [15]
PEGATRON DT-MB RESTRICTED SECRET
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
IPPLP-TH
IPPLP-TH
IPPLP-TH
1
DDR3_A 1-6
DDR3_A 1-6
DDR3_A 1-6
Shrek_Tseng
Shrek_Tseng
Shrek_Tseng
897Friday, January 17, 2014
897Friday, January 17, 2014
897Friday, January 17, 2014
Rev
Rev
Rev
A00
A00
A00
Vinafix.com
5
M_CHB_DQ[0..63][16]
M_CHB_DQS0[16]
M_CHB_DQS0#[16]
D D
M_CHB_DQS1[16]
M_CHB_DQS1#[16]
M_CHB_DQS2[16]
M_CHB_DQS2#[16]
C C
M_CHB_DQS3[16]
M_CHB_DQS3#[16]
M_CHB_DQS4[16]
M_CHB_DQS4#[16]
B B
A A
5
M_CHB_DQS5[16]
M_CHB_DQS5#[16]
M_CHB_DQS6[16]
M_CHB_DQS6#[16]
M_CHB_DQS7[16]
M_CHB_DQS7#[16]
4
M_CHB_DQ0
M_CHB_DQ1
M_CHB_DQ2
M_CHB_DQ3
M_CHB_DQ4
M_CHB_DQ5
M_CHB_DQ6
M_CHB_DQ7
M_CHB_DQ8
M_CHB_DQ9
M_CHB_DQ10
M_CHB_DQ11
M_CHB_DQ12
M_CHB_DQ13
M_CHB_DQ14
M_CHB_DQ15
M_CHB_DQ16
M_CHB_DQ17
M_CHB_DQ18
M_CHB_DQ19
M_CHB_DQ20
M_CHB_DQ21
M_CHB_DQ22
M_CHB_DQ23
M_CHB_DQ24
M_CHB_DQ25
M_CHB_DQ26
M_CHB_DQ27
M_CHB_DQ28
M_CHB_DQ29
M_CHB_DQ30
M_CHB_DQ31
M_CHB_DQ32
M_CHB_DQ33
M_CHB_DQ34
M_CHB_DQ35
M_CHB_DQ36
M_CHB_DQ37
M_CHB_DQ38
M_CHB_DQ39
M_CHB_DQ40
M_CHB_DQ41
M_CHB_DQ42
M_CHB_DQ43
M_CHB_DQ44
M_CHB_DQ45
M_CHB_DQ46
M_CHB_DQ47
M_CHB_DQ48
M_CHB_DQ49
M_CHB_DQ50
M_CHB_DQ51
M_CHB_DQ52
M_CHB_DQ53
M_CHB_DQ54
M_CHB_DQ55
M_CHB_DQ56
M_CHB_DQ57
M_CHB_DQ58
M_CHB_DQ59
M_CHB_DQ60
M_CHB_DQ61
M_CHB_DQ62
M_CHB_DQ63
4
AF35
AF34
AE34
AE35
AG35
AH35
AD34
AD35
AG34
AH34
AL33
AK33
AL34
AL35
AK31
AL31
AK34
AK35
AK32
AL32
AP33
AN33
AN34
AP34
AN31
AP31
AN35
AP35
AN32
AP32
AN28
AN29
AM29
AM28
AR29
AR28
AL29
AL28
AP29
AP28
AN12
AN13
AR12
AP12
AL13
AL12
AR13
AP13
AM13
AM12
AP8
AR8
AR9
AP9
AR6
AP6
AR10
AP10
AR7
AP7
AL8
AM8
AM9
AL9
AL6
AL7
AM10
AL10
AM6
AM7
AG7
AG6
AH6
AH7
AE6
AE7
AJ6
AJ7
AF6
AF7
I
XU1B
LGA_1150P
SB_DQSP0
SB_DQSN0
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQSP1
SB_DQSN1
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQSP2
SB_DQSN2
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQSP3
SB_DQSN3
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQSP4
SB_DQSN4
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQSP5
SB_DQSN5
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQSP6
SB_DQSN6
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQSP7
SB_DQSN7
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
SB_ECC_CB0
SB_ECC_CB1
SB_ECC_CB2
SB_ECC_CB3
SB_ECC_CB4
SB_ECC_CB5
SB_ECC_CB6
SB_ECC_CB7
DDR3_B
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
SB_WE#
SB_CAS#
SB_RAS#
SB_BS0
SB_BS1
SB_BS2
SB_CS#0
SB_CS#1
SB_CS#2
SB_CS#3
SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3
SB_ODT0
SB_ODT1
SB_ODT2
SB_ODT3
SB_CK0
SB_CKN0
SB_CK1
SB_CKN1
SB_CK2
SB_CKN2
SB_CK3
SB_CKN3
RSVD7
SB_DQSP8
SB_DQSN8
AL19
AK23
AM22
AM23
AP23
AL23
AY24
AV25
AU26
AW25
AP18
AY25
AV26
AR15
AV27
AY28
AK16
AP16
AM18
AK17
AL18
AW28
AP17
AN15
AN17
AL15
AW29
AY29
AU28
AU29
AM17
AL16
AM16
AK15
AM20
AM21
AP22
AP21
AN20
AN21
AP19
AP20
AB39
AB40
AL20
AN25
AN26
AM26
AM25
AP25
AP26
AL26
AL25
AR26
AR25
3
M_CHB_MAA0
M_CHB_MAA1
M_CHB_MAA2
M_CHB_MAA3
M_CHB_MAA4
M_CHB_MAA5
M_CHB_MAA6
M_CHB_MAA7
M_CHB_MAA8
M_CHB_MAA9
M_CHB_MAA10
M_CHB_MAA11
M_CHB_MAA12
M_CHB_MAA13
M_CHB_MAA14
M_CHB_MAA15
12
HC1
0.022UF/16V
SB_VDQ_RC
X7R/+/-10%
I
12
HR1
24.9 OHM
1%
I
GND GND
NOTE:
Low pass filter to
cancel the noise during
switch
between CPU driven and
on board driven.
3
M_CHB_WE# [16]
M_CHB_CAS# [16]
M_CHB_RAS# [16]
M_CHB_BA0 [16]
M_CHB_BA1 [16]
M_CHB_BA2 [16]
M_CHB_CS#0 [16]
M_CHB_CS#1 [16]
M_CHB_CKE0 [16]
M_CHB_CKE1 [16]
M_CHB_ODT0 [16]
M_CHB_ODT1 [16]
M_CHB_CLK0 [16]
M_CHB_CLK0# [16]
M_CHB_CLK1 [16]
M_CHB_CLK1# [16]
12
HC2
0.022UF/16V
SA_VDQ_RC
X7R/+/-10%
I
12
HR2
24.9 OHM
1%
I
M_CHB_MAA[0..15] [16]
2
DIMM_DQ_VREF_A [15]
DIMM_DQ_VREF_B [16]
1
PEGATRON DT-MB RESTRICTED SECRET
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Engineer:
IPPLP-TH
IPPLP-TH
IPPLP-TH
1
DDR3_B 2-6
DDR3_B 2-6
DDR3_B 2-6
Shrek_Tseng
Shrek_Tseng
Shrek_Tseng
997Friday, January 17, 2014
997Friday, January 17, 2014
997Friday, January 17, 2014
Rev
Rev
Rev
A00
A00
A00
Vinafix.com
5
4
3
2
1
I
XU1C
LGA_1150P
E15
PEG_RXP0
F15
PEG_RXN0
D D
PEG_RXP[0..7][79]
PEG_RXN[0..7][79]
C C
B B
DMI_RXP0[19]
DMI_RXN0[19]
DMI_RXP1[19]
DMI_RXN1[19]
DMI_RXP2[19]
DMI_RXN2[19]
DMI_RXP3[19]
DMI_RXN3[19]
D14
PEG_RXP1
E14
PEG_RXN1
E13
PEG_RXP2
F13
PEG_RXN2
D12
PEG_RXP3
E12
PEG_RXN3
E11
PEG_RXP4
F11
PEG_RXN4
F10
PEG_RXP5
G10
PEG_RXN5
E9
PEG_RXP6
F9
PEG_RXN6
F8
PEG_RXP7
G8
PEG_RXN7
D3
PEG_RXP8
PEG_RXN7 PEG_TXN7
PEG_RXP6
PEG_RXN6
PEG_RXP5
PEG_RXN5
PEG_RXP4
PEG_RXN4
PEG_RXP3
PEG_RXN3
PEG_RXP2
PEG_RXN2
PEG_RXP1
PEG_RXN1
PEG_RXP0
PEG_RXN0
D4
E4
E5
F5
F6
G4
G5
H5
H6
J4
J5
K5
K6
L4
L5
U3
T3
U1
V1
W2
V2
Y3
W3
PEG_RXN8
PEG_RXP9
PEG_RXN9
PEG_RXP10
PEG_RXN10
PEG_RXP11
PEG_RXN11
PEG_RXP12
PEG_RXN12
PEG_RXP13
PEG_RXN13
PEG_RXP14
PEG_RXN14
PEG_RXP15
PEG_RXN15
DMI_RXP0
DMI_RXN0
DMI_RXP1
DMI_RXN1
DMI_RXP2
DMI_RXN2
DMI_RXP3
DMI_RXN3
PEG
DMI
PEG_TXP10
PEG_TXN10
PEG_TXP11
PEG_TXN11
PEG_TXP12
PEG_TXN12
PEG_TXP13
PEG_TXN13
PEG_TXP14
PEG_TXN14
PEG_TXP15
PEG_TXN15
PEG_RCOMP
PEG_TXP0
PEG_TXN0
PEG_TXP1
PEG_TXN1
PEG_TXP2
PEG_TXN2
PEG_TXP3
PEG_TXN3
PEG_TXP4
PEG_TXN4
PEG_TXP5
PEG_TXN5
PEG_TXP6
PEG_TXN6
PEG_TXP7
PEG_TXN7
PEG_TXP8
PEG_TXN8
PEG_TXP9
PEG_TXN9
DMI_TXP0
DMI_TXN0
DMI_TXP1
DMI_TXN1
DMI_TXP2
DMI_TXN2
DMI_TXP3
DMI_TXN3
A12
B12
B11
C11
C10
D10
B9
C9
C8
D8
B7
C7
A6
B6
B5
C5
E1
PEG_TXP7
E2
F2
PEG_TXP6
F3
PEG_TXN6
G1
PEG_TXP5
G2
PEG_TXN5
H2
PEG_TXP4
H3
PEG_TXN4
J1
PEG_TXP3
J2
PEG_TXN3
K2
PEG_TXP2
K3
PEG_TXN2
M2
PEG_TXP1
M3
PEG_TXN1
L1
PEG_TXP0
L2
PEG_TXN0
P3
H_PEG_RCOMP
AA4
AA5
AB3
AB4
AC5
AC4
AC1
AC2
+VCOMP_OUT
12
1%
I
PEG_TXP[0..7] [79]
PEG_TXN[0..7] [79]
HR4
24.9 OHM
NOTE:
W/S=12/15 mil, length<400mil
DMI_TXP0 [19]
DMI_TXN0 [19]
DMI_TXP1 [19]
DMI_TXN1 [19]
DMI_TXP2 [19]
DMI_TXN2 [19]
DMI_TXP3 [19]
DMI_TXN3 [19]
NOBOM
NOBOM
HT2
HT3
FDI_CSYNC[19]
CK_135M_DP#[21]
CK_135M_DP[21]
FDI_INT[19]
1
TP_CPU_RSVD_K11
1
TP_CPU_RSVD_J12
I
XU1D
LGA_1150P
D16
FDI_CSYNC
D18
DISP_INT
U5
SSC_DPLL_REF_CLKN
U6
SSC_DPLL_REF_CLKP
K11
RSVD_TP11
J12
RSVD_TP8
FDI
EDP_DISP_UTIL
DP
FDI_TX0N0
FDI_TX0P0
FDI_TX0N1
FDI_TX0P1
DP_RCOMP
DDIB_TXP0
DDIB_TXN0
DDIB_TXP1
DDIB_TXN1
DDIB_TXP2
DDIB_TXN2
DDIB_TXP3
DDIB_TXN3
DDIC_TXP0
DDIC_TXN0
DDIC_TXP1
DDIC_TXN1
DDIC_TXP2
DDIC_TXN2
DDIC_TXP3
DDIC_TXN3
DDID_TXP0
DDID_TXN0
DDID_TXP1
DDID_TXN1
DDID_TXP2
DDID_TXN2
DDID_TXP3
DDID_TXN3
B14
A14
C13
B13
E16
TP_EDP_DISP_UTIL
R4
CPU_DP_COMPPEG_RXP7
E17
F17
F18
G18
G19
H19
F20
G20
D19
E19
C20
D20
D21
E21
C22
D22
B15
C15
A16
B16
B17
C17
A18
B18
1
+VCOMP_OUT
12
HR3
24.9 OHM
1%
I
DP out
Scalar
HDMI OUT
HT1
NOBOM
DP_TXP0_RD_IN [60]
DP_TXN0_RD_IN [60]
DP_TXP1_RD_IN [60]
DP_TXN1_RD_IN [60]
DP_TXP2_RD_IN [60]
DP_TXN2_RD_IN [60]
DP_TXP3_RD_IN [60]
DP_TXN3_RD_IN [60]
HDMIC_TMDSC_DATA2 [51]
HDMIC_TMDSC_DATA2# [51]
HDMIC_TMDSC_DATA1 [51]
HDMIC_TMDSC_DATA1# [51]
HDMIC_TMDSC_DATA0 [51]
HDMIC_TMDSC_DATA0# [51]
HDMIC_TMDSC_CLK [51]
HDMIC_TMDSC_CLK# [51]
HDMI_TXP2 [57]
HDMI_TXN2 [57]
HDMI_TXP1 [57]
HDMI_TXN1 [57]
HDMI_TXP0 [57]
HDMI_TXN0 [57]
HDMI_CLKP [57]
HDMI_CLKN [57]
D1
RSVD_TP7
RSVD_TP5
RSVD_TP4
RSVD_TP1
A A
TP_H_RSVD_D1
C2
TP_H_RSVD_C2
B3
TP_H_RSVD_B3
A4
TP_H_RSVD_A4
1
HT4
HT5
HT6
HT7
NOBOM
NOBOM
NOBOM
NOBOM
1
1
1
PEGATRON DT-MB RESTRICTED SECRET
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Engineer:
IPPLP-TH
IPPLP-TH
IPPLP-TH
1
PCIE/DMI/DP 3-6
PCIE/DMI/DP 3-6
PCIE/DMI/DP 3-6
Shrek_Tseng
Shrek_Tseng
Shrek_Tseng
10 97Friday, January 17, 2014
10 97Friday, January 17, 2014
10 97Friday, January 17, 2014
Rev
Rev
Rev
A00
A00
A00
Vinafix.com
5
+1V_CPUIOOUT
12
HR12
90.9Ohm
1%
D D
NOTE:
C C
The 20 CFG[19:0] signals should be length matched as a
group to within 25ps of flight time.
Stub on these nets should be limited to
less than 50ps in length.
VIDSCLK[64]
VIDSOUT[64]
VIDALERT#[64]
1 2
XDP_PLTRST_CPU#[76]
PLTRST_CPU#[20]
CPUPWRGD[22]
DRAM_PWROK[22]
1 2
XDP_CPUPWRGD#[76]
R1 0 Ohm PROTO
PECI_SIO[44]
CATERR#[49]
PROCHOT#[44,64]
H_THMTRIP#[20,80]
PM_SYNC[20]
SKTOCC#[22]
PROTO
HR10 1K 1%
mx_r0402_small
12
I
12
HR18
10KOhm
1%
GND GND
GND GND
NOTE:
CFG[17:0] are internal PU
CFG[1:0]: Reserved configuration
lane.
CFG[2]: PCIE* Static x16 Lane
Numbering Reversal.
x1 = Normal operation
x0 = Lane numbers reversed.
CFG[3]: PCIE* Static x4 Lane
Numbering Reversal.
x1 = Normal operation
B B
x0 = Lane numbers reversed
CFG[4]: Reserved configuration
lane.
CFG[6:5]: PCIE* Bifurcation:
x00 = 1 x8, 2 x4 PCIE*
x01 = reserved
x10 = 2 x8 PCIE*
x11 = 1 x16 PCIE*
CFG[19:7]: Reserved configuration
lanes.
A A
HSW_STRAP[22,77]
5
PRIVACY_MSR_EN_N[76]
NI
NI
NI
NI
NI
NI
NI
NI
NI
NI
NI
NI
NI
NI
NI
NI
NI
NI
GND
CPU_CFG[0..15][76]
mx_r0402_small
HR29 1KOhm
HR30 1KOhm
HR31 1K 1%Imx_r0402_small
HR32 1KOhm
HR33 1KOhm
HR34 1KOhm
HR35 1KOhm
HR36 1KOhm
HR38 1KOhm
HR37 1KOhm
HR39 1KOhm
HR40 1KOhm
HR41 1KOhm
HR42 1KOhm
HR44 1KOhm
HR45 1KOhm
HR46 1KOhm
HR47 1KOhm
HR48 1KOhm
HSW_PCUSTB_DN1[76]
HSW_PCUSTB_DP1[76]
HSW_PCUSTB_DP0[76]
HSW_PCUSTB_DN0[76]
+3P3V
12
NI
HR57
1K
1%
NI
I
12
I
HC3
47PF/50V
NPO 5%
X7R/+/-10%
NI
12
NI
SC138
10PF/50V
NPO/+/-5%
GND
PROTO
SR633 1K 1%
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
NI
HR59
10K
1 2
12
HR5
110 Ohm
HC4
0.1UF/16V
H_CFG13
4
12
1%
I
+1P5V_DUAL
12
12
12
I
12
B
1
4
HR6
75 OHM
I
HR14
1.8KOHM
1%
I
HR19
3.3KOHM
1%
HR23
51 OHM
+3P3VSB
12
GND
1 2
HR13
44.2 OHM
1%
I
+1V_CPUIOOUT
12
PROTO
HR24
1K
1%
mx_r0402_small
NOBOM
NOBOM
NI
HR55
10K
H_CFG13#
3
C
NI
HQ2
E
PMBS3904
2
3
I
XU1E
LGA_1150P
AB35
AK21
W6
W5
C38
C37
B37
M39
V4
V5
BCLKN
BCLKP
DPLL_REF_CLKN
DPLL_REF_CLKP
VIDSCLK
VIDSOUT
VIDALERT#
RESET#
PWRGOOD
SM_DRAMPWROK
VCC_SENSE
VSS_SENSE
VCOMP_OUT
PWR_DEBUG
CK_100M_DMI#[21]
CK_100M_DMI[21]
CK_135M_DPNS#[21]
CK_135M_DPNS[21]
CPU_VIDALERT#
12
HR8
100 Ohm
NI
GND
NI
12
HC5
180PF/50V
NPO 5%
GND
VCC126
SM_VREF
TDO
TCK
TMS
TRST#
PRDY#
PREQ#
DBR#
E40
F40
P4
M8
AB38
N40
F39
F38
TDI
D39
E39
E37
L39
L37
G40
H_DBR#
VCC_SENSE [64]
VSS_SENSE [64]
+VCOMP_OUT
PROTO
+VCORE
1 2
HR20 0
MISC
G39
BPM#0
J39
N37
PECI
M36
CATERR#
K38
PROCHOT#
F37
THERMTRIP#
P36
PM_SYNC
D38
SKTOCC#
AA37
AA36
W38
AA34
W34
W36
Y38
V39
U39
U40
V38
T40
Y35
V37
Y34
U38
V35
Y37
Y36
V36
K8
J10
RSVD_TP19
RSVD_TP20
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG19
CFG18
3
1
TP_H_RSVD_K8
HT14
1
TP_H_RSVD_J10
HT16
CPU_CFG0
CPU_CFG1
CPU_CFG2
CPU_CFG3
CPU_CFG4
CPU_CFG5
CPU_CFG6
CPU_CFG7
CPU_CFG8
CPU_CFG9
CPU_CFG10
CPU_CFG11
CPU_CFG12
CPU_CFG13
CPU_CFG14
CPU_CFG15
12
NI
HR51
1K
HQ6_C
3
C
B
1
NI
E
HQ1
2
PMBS3904
GND
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7
RSVD42
RSVD36
FC_K9
RSVD23
RSVD30
RSVD22
RSVD12
RSVD_TP21
RSVD_TP22
VSS478
VSS479
RSVD_TP13
RSVD_TP10
RSVD3
RSVD_TP3
RSVD_TP2
RSVD5
RSVD43
RSVD2
RSVD46
RSVD34
RSVD32
RSVD35
RSVD33
RSVD45
RSVD39
RSVD38
RSVD37
TESTLO_P6
TESTLO_N5
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
CFG_RCOMP
VSS420
RSVD
VSS418
VSS354
VSS414
VSS363
G38
TP_H_BPM#2
H37
TP_H_BPM#3
H38
TP_H_BPM#4
J38
TP_H_BPM#5
K39
TP_H_BPM#6
K37
TP_H_BPM#7
T35
TP_H_RSVD_T35
M38
TP_H_RSVD_M38
K9
H15
TP_H_RSVD_H15
J9
TP_H_RSVD_J9
H14
TP_H_RSVD_H14
AV2
TP_H_RSVD_AV2
J16
TP_H_RSVD_J16
H16
TP_H_RSVD_H16
V7
TP_H_RSVD_V7
AB6
TP_H_RSVD_AB6
K13
TP_H_RSVD_K13
J8
TP_H_RSVD_J8
AB36
TP_H_RSVD_AB36
AW2
TP_H_RSVD_AW2
AV1
TP_H_RSVD_AV1
AC8
TP_H_RSVD_AC8
U8
TP_H_RSVD_U8
AB33
TP_H_RSVD_AB33
Y8
TP_H_RSVD_Y8
M10
TP_H_RSVD_M10
L10
TP_H_RSVD_L10
M11
TP_H_RSVD_M11
L12
TP_H_RSVD_L12
W8
TP_H_RSVD_W8
R33
TP_H_RSVD_R33
P33
TP_H_RSVD_P33
N35
1P05V_PECI_VCOM
P6
CPU_TESTLOW1
N5
CPU_TESTLOW2
R1
CPU_SM_RCOMP_0
P1
CPU_SM_RCOMP_1
R2
CPU_SM_RCOMP_2
H40
H_CFG_RCOMP
N39
T8
N33
J11
M9
J7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TP_VSS_T8
NOTE: NC on pin T8
+1P05V_PCH
12
12
GND
HT8
HT9
HT10
HT11
HT12
HT13
HT15
HT17
HT18
HT19
HT20
HT21
HT22
HT23
HT24
HT25
HT26
HT27
HT28
HT29
HT30
HT31
HT32
HT33
HT34
HT35
HT36
HT37
HT38
HT39
HT40
HT41
HR50 49.9 OHM1%I
HR52 49.9 OHM1%I
HR53 100 Ohm 1%I
HR54 75 OHM 1%I
HR56 100 Ohm 1%I
HT42
2
HR7
150 Ohm
1%
I
HR15
10KOhm
NI
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
1 2
1 2
1 2
1 2
1 2
NOBOM
2
1 2
HR9 0
NI
+1V_CPUIOOUT
H_PRDY# [76]
H_PREQ# [76]
SYS_RESET# [22,50,76,77]
HSW_XDP_MBP0 [76]
HSW_XDP_MBP1 [76]
+1V_VCCST
HR49
0 OhmNI
12
1%
I
GNDGND
+1P05V_PCH
12
GND
HR58
49.9 OHM
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
H_SM_VREF [16]
XDP_PWR_DEBUG [76]
12
12
HR16
51 OHM
NI
HR21
51 OHM
PROTO
GNDGND
12
12
HR17
51 OHM
NI
HR22
51 OHM
PROTO
TDO [76]
TDI [76]
TCK [76]
TMS [76]
TRST# [76]
NOTE:
Place near CPU
HC6
1 2
0.1UF/16V
NI
GND
PEGATRON DT-MB RESTRICTED SECRET
Title :
Title :
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Title :
Engineer:
Engineer:
Engineer:
IPPLP-TH
IPPLP-TH
IPPLP-TH
1
MISC 4-6
MISC 4-6
MISC 4-6
Shrek_Tseng
Shrek_Tseng
Shrek_Tseng
11 97Friday, January 17, 2014
11 97Friday, January 17, 2014
11 97Friday, January 17, 2014
Rev
Rev
Rev
A00
A00
A00
Vinafix.com
5
I
XU1F
LGA_1150P
RSVD1
VCC21
VCC23
VCC97
VCC96
VCC86
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC83
VCC85
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC116
VCC94
VCC95
VCC100
VCC101
VCC102
VCC103
VCC104
VCC105
VCC106
VCC107
VCC108
VCC109
VCC110
VCC111
VCC113
VCC114
VCC118
VCC117
VCC119
VCC120
VCC121
VCC122
VCC123
VCC124
VCC125
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VDDQ22
VDDQ23
VDDQ24
VDDQ25
VDDQ26
L40
AB8
C31
C33
L16
L15
J35
H33
H35
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
J32
J34
K19
K21
K23
K25
K27
K29
K31
M13
K33
K35
L19
L20
L21
L22
L23
L24
L25
L26
L27
L28
L29
L30
L32
L33
M17
M15
M19
M21
M23
M25
M27
M29
M33
AJ12
AJ13
AJ15
AJ17
AJ20
AJ21
AJ24
AJ25
AJ28
AJ29
AJ9
AT17
AT22
AU15
AU20
AU24
AV10
AV11
AV13
AV18
AV23
AV8
AW16
AY12
AY14
AY9
VCCIO_OUT
D D
VCC 70A
C C
B B
A A
+VCORE
+VCORE
G33
B25
B27
B29
B31
B33
G31
B35
C24
C25
C26
C27
C28
C29
C30
C32
C34
C35
D25
D27
D29
D31
E33
D33
E31
D35
E24
E25
E26
E27
E28
E29
E30
E32
E34
E35
G22
G23
G24
G25
G26
G27
G28
G29
G30
G32
G34
G35
H23
H25
H27
H29
H31
L31
L18
L17
J33
A24
A25
A26
A27
A28
A29
A30
J31
F23
F25
F27
F29
F31
F33
F35
L34
P8
VCC127
VCC112
VCC99
VCC98
VCC84
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC62
VCC8
VCC9
VCC10
VCC11
VCC82
VCC12
VCC60
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC22
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC41
VCC30
VCC39
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC40
VCC42
VCC44
VCC45
VCC46
VCC47
VCC48
VCC43
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC61
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC115
+1V_CPUIOOUT
VCCIO_OUT 300mA
R_+1V_CPU2PCH
12
+VCORE
+1P5V_DUAL
X5R/+/-10%
mx_c0603
GND
+1P05V_PCH
VDDQ 4.2A
HR60
1 2
0 Ohm NI
NI
HCB1
4.7UF/6.3V
VP
VP
4
+1V_VCCST
VCCIO2PCH 100mA
+1V_CPU2PCH+1V_VCCST
12
R2 0
mx_r0603
mx_r0603
12
R3 0
+1V_CPU2PCH
GND
12
NI
SCB1
0.1UF/16V
GND
12
NI
SCB2
0.1UF/16V
3
I
XU1G
LGA_1150P
A13
GND
A15
A17
A23
A11
AA3
AA33
AA35
AA38
AA6
AA7
AA8
AB34
AB37
AB5
AB7
AC3
AC33
AC34
AC35
AC36
AC37
AC38
AC39
AC40
AC6
AC7
AD1
AD2
AD3
AD33
AD36
AD4
AD5
AD6
AD7
AD8
AE33
AE36
AE37
AE40
AE5
AE8
AF1
AF33
AF36
AF4
AF5
AF8
AG33
AG36
AG37
AG38
AG39
AG40
AG5
AG8
AH1
AH2
AH3
AH33
AH36
AH4
AH5
AH8
AJ11
AJ14
AJ16
AJ18
AJ19
AJ22
AJ23
AJ26
AJ27
AJ30
AJ31
AJ32
AJ33
VSS2
VSS3
VSS4
VSS5
VSS1
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
A5
VSS6
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
A7
VSS7
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
AJ34
AJ35
AJ36
AJ37
AJ40
AJ5
AJ8
AK1
AK10
AK11
AK12
AK13
AK14
AK18
AK19
AK24
AK25
AK26
AK27
AK28
AK29
AK30
AK36
AK4
AK5
AK6
AK7
AK8
AK9
AL11
AL14
AL17
AL21
AL22
AL24
AL27
AL30
AL36
AL37
AL38
AL39
AL40
AL5
AM1
AM11
AM14
AM15
AM19
AM2
AM24
AM27
AM3
AM30
AM31
AM32
AM33
AM34
AM35
AM36
AM4
AM5
AN10
AN11
AN14
AN16
AN18
AN19
AN22
AN23
AN24
AN27
AN30
AN36
AN37
AN40
AN5
AN6
AN7
AN8
AN9
AP1
2
I
XU1H
LGA_1150P
AP11
GND
GND
AP14
AP15
AP24
AP27
AP30
AP36
AP4
AP5
AR11
AR14
AR16
AR17
AR18
AR19
AR20
AR21
AR22
AR23
AR24
AR27
AR30
AR31
AR32
AR33
AR34
AR35
AR36
AR37
AR38
AR39
AR40
AR5
AT1
AT10
AT11
AT12
AT13
AT14
AT15
AT16
AT2
AT24
AT25
AT26
AT27
AT28
AT29
AT3
AT30
AT32
AT34
AT36
AT38
AT39
AT4
AT5
AT6
AT7
AT8
AT9
AU2
AU25
AU3
AU30
AU34
AU38
AU5
AU7
AV21
AV28
AV3
AV30
AV34
AV38
AV7
AW26
AW3
AW30
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS254
VSS255
VSS256
VSS257
VSS259
VSS260
VSS261
VSS262
VSS272
VSS273
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS271
VSS252
VSS253
VSS270
VSS291
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS301
VSS302
VSS292
VSS293
VSS297
VSS294
VSS295
VSS296
VSS298
VSS299
VSS258
VSS300
VSS303
VSS314
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS315
VSS316
VSS317
VSS284
VSS318
VSS332
VSS319
AW32
AW34
AW36
AW7
AY17
AY23
AY26
AY27
AY30
AY5
AY7
B24
B26
B28
B30
B34
B36
B4
B8
C4
C6
C12
C14
C16
C18
C19
C21
C23
C36
B10
B23
C3
D9
D11
D13
D15
D17
D2
D23
D24
D26
D28
D30
D34
D36
D37
D5
D6
D7
E7
E8
E10
E18
E3
E20
E22
E23
E36
E38
B32
E6
F1
F32
F12
F14
F16
F19
F21
F22
F24
F26
F28
F30
F34
F36
F4
D32
F7
G9
G11
1
GND
PEGATRON DT-MB RESTRICTED SECRET
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Engineer:
IPPLP-TH
IPPLP-TH
IPPLP-TH
1
VCC 5 - 6
VCC 5 - 6
VCC 5 - 6
Shrek_Tseng
Shrek_Tseng
Shrek_Tseng
12 97Friday, January 17, 2014
12 97Friday, January 17, 2014
12 97Friday, January 17, 2014
Rev
Rev
Rev
A00
A00
A00
Vinafix.com
5
4
3
2
1
I
XU1I
LGA_1150P
G12
VSS320
G13
VSS321
G14
VSS322
G16
VSS324
D D
C C
B B
H11
G17
G21
H13
H22
H32
G36
G37
G15
H10
H17
H18
H20
H21
H24
H26
H28
H30
H34
H36
H39
K10
K14
K18
K20
K22
K24
K26
K28
K30
K34
K36
K40
K17
M12
M14
M18
M16
M20
M22
M24
M26
M28
M30
M32
M34
M37
VSS335
VSS325
VSS326
G3
VSS327
VSS336
VSS341
VSS346
VSS328
VSS329
G6
VSS330
G7
VSS331
VSS323
H1
VSS333
VSS334
VSS337
VSS338
VSS339
VSS340
VSS342
VSS343
VSS344
VSS345
VSS347
VSS348
VSS349
H4
VSS350
H7
VSS351
H8
VSS352
H9
VSS353
J19
VSS357
J20
VSS358
J3
VSS359
J18
VSS356
VSS365
VSS366
J36
VSS360
J37
VSS361
J6
VSS362
K1
VSS364
VSS370
VSS371
VSS372
VSS373
VSS374
VSS375
VSS376
VSS378
VSS379
K4
VSS380
VSS381
K7
VSS382
L7
VSS391
L8
VSS392
L9
VSS393
L11
VSS383
L3
VSS386
L13
VSS384
L14
VSS385
L35
VSS387
L38
VSS389
L6
VSS390
M1
VSS394
VSS369
VSS395
VSS396
VSS398
VSS397
VSS399
VSS400
VSS401
VSS402
VSS403
VSS404
VSS405
VSS406
VSS408
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS409
VSS410
VSS411
VSS412
VSS413
VSS367
VSS368
VSS415
VSS416
VSS417
VSS423
VSS419
VSS421
VSS422
VSS377
VSS425
VSS426
VSS428
VSS431
VSS432
VSS424
VSS433
VSS388
VSS434
VSS438
VSS439
VSS440
VSS441
VSS443
VSS444
VSS445
VSS407
VSS449
VSS450
VSS451
VSS452
VSS453
VSS442
VSS455
VSS456
VSS457
VSS460
VSS461
VSS462
VSS427
VSS463
VSS464
VSS466
VSS467
VSS468
VSS469
VSS470
VSS471
VSS472
VSS473
VSS474
VSS475
VSS476
VSS477
VSS480
M4
M40
M5
M6
M7
K15
K16
N1
N2
N3
N7
N34
N4
N6
K32
P2
P34
P38
P5
P7
N8
R3
L36
R35
R40
R5
R6
R7
T1
T2
T33
M35
T39
T4
T5
T6
T7
R8
U2
U33
U34
U37
U4
U7
P35
V3
V33
V40
V6
V8
W1
W33
W35
W37
W4
W7
Y33
Y4
Y5
Y6
AU40
AV39
AW38
AY3
B38
B39
C40
D40
GND
I
ILM1
PT44A69-6411
12
VCCST_PWROKVCCST_PWROKVCCST_PWROK
1%
PWROK[20,22,44]
R46.04KOHM
I
EMI
1%
12
R5
2.67KOHM
I
1 2
GND GND
NI
C1
470PF/50V
X7R 10%
NOTE:
The resistirs need near the CPU pin (Within 1.5")
NI
BP1
1
NP_NC1
3
NP_NC3
INTEL_1156_BP
AY18
AW24
AW23
AV29
AV24
AU39
AU27
AU1
AT40
AK20
T34
R34
H12
Y7
J40
J17
J15
1
2
3
4
5
6
7
I
XU1J
LGA_1150P
RSVD20
RSVD18
RSVD17
RSVD15
RSVD14
RSVD11
RSVD10
RSVD9
RSVD8
RSVD6
FC_Y7
RSVD41
RSVD40
RSVD29
RSVD28
RSVD26
RSVD21
NP_NC1
NP_NC2
NP_NC3
NP_NC4
NP_NC5
NP_NC6
NP_NC7
RSVD_TP12
RSVD_TP9
RSVD_TP16
RSVD_TP15
RSVD_TP17
RSVD_TP6
RSVD_TP14
VSS458
VSS430
VSS436
VSS447
VSS465
VSS437
VSS448
VSS459
VSS429
VSS446
VSS435
VSS355
NP_NC2
NP_NC4
K12
J13
P37
N38
R36
C39
N36
U35
P40
R38
T37
V34
R39
T38
U36
P39
T36
R37
J14
2
1
1
GND
NOTE: (CPU)
Part
HT45
NOBOM
HT46
NOBOM
Standard
PE115027_4041_01F_INTEL
mx_socket_1150p
(with 4 screws)
Symbol
4
GND
A A
PEGATRON DT-MB RESTRICTED SECRET
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Engineer:
IPPLP-TH
IPPLP-TH
IPPLP-TH
1
VSS 6 - 6
VSS 6 - 6
VSS 6 - 6
Shrek_Tseng
Shrek_Tseng
Shrek_Tseng
13 97Friday, January 17, 2014
13 97Friday, January 17, 2014
13 97Friday, January 17, 2014
Rev
Rev
Rev
A00
A00
A00
Vinafix.com
5
D D
C C
4
3
2
1
+3P3V +3P3V
B B
GPU_DEBUG_VGA_BLU[80]
12
NI
VR32
150
1%
GND
A A
GPU_HSYNC[80]
GPU_DDCVGACLK[80]
12
VR27
2.2KOHM
NI
17
SIDE1
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
SIDE2
WtoB_CON_2X8P
GND GND
J214
1
3
5
7
9
11
13
15
NI
+5V
1
3
5
7
9
11
13
15
12
VR39
2.2KOHM
NI
GPU_VSYNC [80]
GPU_DDCVGADATA [80]
GPU_DEBUG_VGA_GRN [80]
12
NI
VR37
150
1%
GND
GPU_DEBUG_VGA_RED [80]
12
NI
VR38
150
1%
GND
PEGATRON DT-MB RESTRICTED SECRET
VGA DEBUG
VGA DEBUG
1
VGA DEBUG
Shrek_Tseng
Shrek_Tseng
Shrek_Tseng
14 97Friday, January 17, 2014
14 97Friday, January 17, 2014
14 97Friday, January 17, 2014
Rev
Rev
Rev
A00
A00
A00
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Engineer:
IPPLP-TH
IPPLP-TH
IPPLP-TH
Vinafix.com
5
4
3
2
1
XMM1 9.2H(STD)
D D
I
DIMM1A
GND
GND
12
NI
SC2
150PF/50V
NPO 5%
mx_c0402_small
GNDGND
98
A0
97
A1
96
A2
95
A3
92
A4
91
A5
90
A6
86
A7
89
A8
85
A9
107
A10/AP
84
A11
83
A12/BC#
119
A13
80
A14
78
A15
102
CK1
104
CK1#
101
CK0
103
CK0#
121
S1#
114
S0#
120
ODT1
116
ODT0
113
WE#
110
RAS#
115
CAS#
79
BA2
108
BA1
109
BA0
74
CKE1
73
CKE0
201
SA1
197
SA0
188
DQS7
186
DQS#7
171
DQS6
169
DQS#6
154
DQS5
152
DQS#5
137
DQS4
135
DQS#4
64
DQS3
62
DQS#3
47
DQS2
45
DQS#2
29
DQS1
27
DQS#1
12
DQS0
10
DQS#0
187
DM7
170
DM6
153
DM5
136
DM4
63
DM3
46
DM2
28
DM1
11
DM0
202
SCL
200
SDA
DDR3_DIMM_204P
0
1
2
3
4
5
6
7
M_CHA_MAA0
M_CHA_MAA1
M_CHA_MAA2
M_CHA_MAA3
M_CHA_MAA4
M_CHA_MAA5
M_CHA_MAA6
M_CHA_MAA7
M_CHA_MAA8
M_CHA_MAA9
M_CHA_MAA10
M_CHA_MAA11
M_CHA_MAA12
M_CHA_MAA13
M_CHA_MAA14
M_CHA_MAA15
M_CHA_CLK1[8]
M_CHA_CLK1#[8]
M_CHA_CLK0[8]
M_CHA_CLK0#[8]
M_CHA_CS#1[8]
C C
B B
9,60,76,77]
9,60,76,77]
A A
SMB_CLK_RESUME
SMB_DATA_RESUME
M_CHA_CS#0[8]
M_CHA_ODT1[8]
M_CHA_ODT0[8]
M_CHA_WE#[8]
M_CHA_RAS#[8]
M_CHA_CAS#[8]
M_CHA_BA2[8]
M_CHA_BA1[8]
M_CHA_BA0[8]
M_CHA_CKE1[8]
M_CHA_CKE0[8]
M_CHA_DQS7[8]
M_CHA_DQS7#[8]
M_CHA_DQS6[8]
M_CHA_DQS6#[8]
M_CHA_DQS5[8]
M_CHA_DQS5#[8]
M_CHA_DQS4[8]
M_CHA_DQS4#[8]
M_CHA_DQS3[8]
M_CHA_DQS3#[8]
M_CHA_DQS2[8]
M_CHA_DQS2#[8]
M_CHA_DQS1[8]
M_CHA_DQS1#[8]
M_CHA_DQS0[8]
M_CHA_DQS0#[8]
NI
SC1
150PF/50V
NPO 5%
mx_c0402_small
12
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
RESET#
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
30
M_CHA_DQ5
M_CHA_DQ4
M_CHA_DQ2
M_CHA_DQ3
M_CHA_DQ1
M_CHA_DQ0
M_CHA_DQ7
M_CHA_DQ6
M_CHA_DQ8
M_CHA_DQ9
M_CHA_DQ10
M_CHA_DQ11
M_CHA_DQ13
M_CHA_DQ12
M_CHA_DQ14
M_CHA_DQ15
M_CHA_DQ16
M_CHA_DQ17
M_CHA_DQ19
M_CHA_DQ18
M_CHA_DQ21
M_CHA_DQ20
M_CHA_DQ23
M_CHA_DQ22
M_CHA_DQ25
M_CHA_DQ24
M_CHA_DQ26
M_CHA_DQ27
M_CHA_DQ28
M_CHA_DQ29
M_CHA_DQ30
M_CHA_DQ31
M_CHA_DQ36
M_CHA_DQ37
M_CHA_DQ38
M_CHA_DQ35
M_CHA_DQ32
M_CHA_DQ33
M_CHA_DQ39
M_CHA_DQ34
M_CHA_DQ40
M_CHA_DQ41
M_CHA_DQ43
M_CHA_DQ47
M_CHA_DQ44
M_CHA_DQ45
M_CHA_DQ46
M_CHA_DQ42
M_CHA_DQ49
M_CHA_DQ48
M_CHA_DQ55
M_CHA_DQ54
M_CHA_DQ52
M_CHA_DQ53
M_CHA_DQ51
M_CHA_DQ50
M_CHA_DQ61
M_CHA_DQ60
M_CHA_DQ56
M_CHA_DQ57
M_CHA_DQ63
M_CHA_DQ62
M_CHA_DQ59
M_CHA_DQ58
12
D3CB6
0.1UF/6.3V
MLCC/+/-10%
GND
I
0~7
8~15
16~23
24~31
32~39
40~47
48~55
56~63
DDR3_DRAMRST#_R [16]
HR61
1 2
0Ohm
5%
NOBOM
M_CHA_MAA[0..15] [8]
M_CHA_DQ[0..63] [8]
DIMM_CA_VREF_A[16]
DIMM_DQ_VREF_A[9]
DDR3_DRAMRST# [8]
1 2
12
GND
+1P5V_DUAL
R6
NI
C3
10UF/6.3V
GND
12
2OHMI
12
I
D3R1
1KOhm
1%
I
D3R3
1KOhm
1%
12
I
D3CB3
0.1UF/6.3V
MLCC/+/-10%
+1P5V_DUAL
12
12
GNDGND
I
D3R2
1K
1%
mx_r0402_small
I
D3R4
1K
1%
mx_r0402_small
DIMM_DQ_VREF_A_R
12
I
D3CB5
0.1UF/6.3V
MLCC/+/-10%
GND
GND
I
DIMM1B
75
VDD1
81
VDD3
87
VDD5
93
VDD7
99
VDD9
105
VDD11
111
VDD13
117
VDD15
123
VDD17
2
VSS1
8
VSS3
13
VSS5
19
VSS7
25
VSS9
31
VSS11
37
VSS13
43
VSS15
48
VSS17
54
VSS19
60
VSS21
65
VSS23
71
VSS25
127
VSS27
133
VSS29
138
VSS31
144
VSS33
150
VSS35
155
VSS37
161
VSS39
167
VSS41
172
VSS43
178
VSS45
184
VSS47
189
VSS49
195
VSS51
198
EVENT#
125
TEST
77
NC1
122
NC2
126
VREFCA
1
VREFDQ
DDR3_DIMM_204P
VDD2
VDD4
VDD6
VDD8
VDD10
VDD12
VDD14
VDD16
VDD18
VSS2
VSS4
VSS6
VSS8
VSS10
VSS12
VSS14
VSS16
VSS18
VSS20
VSS22
VSS24
VSS26
VSS28
VSS30
VSS32
VSS34
VSS36
VSS38
VSS40
VSS42
VSS44
VSS46
VSS48
VSS50
VSS52
GND1
GND2
NP_NC1
NP_NC2
VTT1
VTT2
VDDSPD
76
82
88
94
100
106
112
118
124
3
9
14
20
26
32
38
44
49
55
61
66
72
128
134
139
145
151
156
162
168
173
179
185
190
196
207
208
205
206
203
204
199
C300
10PF/50V
NPO/+/-5%
+1P5V_DUAL+1P5V_DUAL
+VTT_DDR
GND
+3P3V
I
12
C301
10PF/50V
GND
NPO/+/-5%
12
12
D3CB4
0.1UF/6.3V
MLCC/+/-10%
GND
I
GND
I
D3CB1
0.1UF/6.3V
MLCC/+/-10%
12
I
D3CB2
4.7UF/6.3V
MLCC/+/-10%
12
I
GNDGND
PEGATRON DT-MB RESTRICTED SECRET
DDR3 CHANNEL A
DDR3 CHANNEL A
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Engineer:
IPPLP-TH
IPPLP-TH
IPPLP-TH
DDR3 CHANNEL A
Shrek_Tseng
Shrek_Tseng
Shrek_Tseng
1
Rev
Rev
Rev
A00
A00
15 97Friday, January 17, 2014
15 97Friday, January 17, 2014
15 97Friday, January 17, 2014
A00
Vinafix.com
5
XMM2 5.2H(STD)
D D
I
DIMM2A
M_CHB_MAA0
M_CHB_MAA1
M_CHB_MAA2
M_CHB_MAA3
M_CHB_MAA4
M_CHB_MAA5
M_CHB_MAA6
M_CHB_MAA7
M_CHB_MAA8
M_CHB_MAA9
M_CHB_MAA10
M_CHB_MAA11
M_CHB_MAA12
M_CHB_MAA13
M_CHB_MAA14
M_CHB_MAA15
M_CHB_CLK1[9]
M_CHB_CLK1#[9]
M_CHB_CLK0[9]
M_CHB_CLK0#[9]
M_CHB_CS#1[9]
C C
+3P3V
B B
9,60,76,77]
9,60,76,77]
A A
SMB_CLK_RESUME
SMB_DATA_RESUME
M_CHB_CS#0[9]
M_CHB_ODT1[9]
M_CHB_ODT0[9]
M_CHB_WE#[9]
M_CHB_RAS#[9]
M_CHB_CAS#[9]
M_CHB_BA2[9]
M_CHB_BA1[9]
M_CHB_BA0[9]
M_CHB_CKE1[9]
M_CHB_CKE0[9]
NI
12
SC3
150PF/50V
NPO 5%
mx_c0402_small
5
GND
M_CHB_DQS7[9]
M_CHB_DQS7#[9]
M_CHB_DQS6[9]
M_CHB_DQS6#[9]
M_CHB_DQS5[9]
M_CHB_DQS5#[9]
M_CHB_DQS4[9]
M_CHB_DQS4#[9]
M_CHB_DQS3[9]
M_CHB_DQS3#[9]
M_CHB_DQS2[9]
M_CHB_DQS2#[9]
M_CHB_DQS1[9]
M_CHB_DQS1#[9]
M_CHB_DQS0[9]
M_CHB_DQS0#[9]
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
102
104
101
103
121
114
120
116
113
110
115
79
108
109
74
73
201
197
188
186
171
169
154
152
137
135
64
62
47
45
29
27
12
10
187
170
153
136
63
46
28
11
202
200
DDR3_DIMM_204P
GND
12
NI
SC4
150PF/50V
NPO 5%
mx_c0402_small
GNDGND
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15
CK1
CK1#
CK0
CK0#
S1#
S0#
ODT1
ODT0
WE#
RAS#
CAS#
BA2
BA1
BA0
CKE1
CKE0
SA1
SA0
DQS7
DQS#7
DQS6
DQS#6
DQS5
DQS#5
DQS4
DQS#4
DQS3
DQS#3
DQS2
DQS#2
DQS1
DQS#1
DQS0
DQS#0
DM7
DM6
DM5
DM4
DM3
DM2
DM1
DM0
SCL
SDA
0
1
2
3
4
5
6
7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
RESET#
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
30
M_CHB_DQ1
M_CHB_DQ0
M_CHB_DQ2
M_CHB_DQ3
M_CHB_DQ4
M_CHB_DQ5
M_CHB_DQ6
M_CHB_DQ7
M_CHB_DQ8
M_CHB_DQ9
M_CHB_DQ10
M_CHB_DQ11
M_CHB_DQ12
M_CHB_DQ13
M_CHB_DQ14
M_CHB_DQ15
M_CHB_DQ16
M_CHB_DQ17
M_CHB_DQ18
M_CHB_DQ19
M_CHB_DQ20
M_CHB_DQ21
M_CHB_DQ22
M_CHB_DQ23
M_CHB_DQ24
M_CHB_DQ25
M_CHB_DQ26
M_CHB_DQ27
M_CHB_DQ28
M_CHB_DQ29
M_CHB_DQ30
M_CHB_DQ31
M_CHB_DQ32
M_CHB_DQ33
M_CHB_DQ34
M_CHB_DQ35
M_CHB_DQ36
M_CHB_DQ37
M_CHB_DQ38
M_CHB_DQ39
M_CHB_DQ40
M_CHB_DQ41
M_CHB_DQ42
M_CHB_DQ43
M_CHB_DQ44
M_CHB_DQ45
M_CHB_DQ46
M_CHB_DQ47
M_CHB_DQ48
M_CHB_DQ49
M_CHB_DQ50
M_CHB_DQ51
M_CHB_DQ52
M_CHB_DQ53
M_CHB_DQ54
M_CHB_DQ55
M_CHB_DQ56
M_CHB_DQ57
M_CHB_DQ58
M_CHB_DQ59
M_CHB_DQ60
M_CHB_DQ61
M_CHB_DQ62
M_CHB_DQ63
GND
4
12
I
D3CB11
0.1UF/6.3V
MLCC/+/-10%
4
0~7
8~15
16~23
24~31
32~39
40~47
48~55
56~63
M_CHB_MAA[0..15] [9]
M_CHB_DQ[0..63] [9]
DIMM_CA_VREF_B[16]
DIMM_DQ_VREF_B[9]
DDR3_DRAMRST#_R [15]
R7 2OHMI
GND
12
12
GND
+1P5V_DUAL
NI
C7
10UF/6.3V
1 2
I
C8
10UF/6.3V
3
+1P5V_DUAL
12
I
D3CB10
0.1UF/6.3V
MLCC/+/-10%
12
I
D3R6
1K
1%
mx_r0402_small
12
I
D3R8
1K
1%
mx_r0402_small
GNDGND
R8 2OHMI
GND
1 2
12
I
C11
0.022UF/16V
MLCC/+/-10%
12
I
R9
24.9 OHM
1%
DIMM_DQ_VREF_B_R
12
I
C9
10UF/6.3V
GND
12
I
D3R5
1KOhm
1%
12
I
D3R7
1KOhm
1%
GND
H_SM_VREF[11]
3
GND
12
2
GND
C10
2.2UF/6.3V
X5R 10%
I
2
HR62 0Ohm 5%NOBOM
HR63 0Ohm 5%NOBOM
DIMM2B
75
VDD1
81
VDD3
87
VDD5
93
VDD7
99
VDD9
105
VDD11
111
VDD13
117
VDD15
123
VDD17
2
VSS1
8
VSS3
13
VSS5
19
VSS7
25
VSS9
31
VSS11
37
VSS13
43
VSS15
48
VSS17
54
VSS19
60
VSS21
65
VSS23
71
VSS25
127
VSS27
133
VSS29
138
VSS31
144
VSS33
150
VSS35
155
VSS37
161
VSS39
167
VSS41
172
VSS43
178
VSS45
184
VSS47
189
VSS49
195
VSS51
198
EVENT#
125
TEST
77
NC1
122
NC2
126
VREFCA
1
VREFDQ
DDR3_DIMM_204P
I
1 2
1 2
1
+1P5V_DUAL+1P5V_DUAL
76
VDD2
82
VDD4
88
VDD6
94
VDD8
100
VDD10
106
VDD12
112
VDD14
118
VDD16
124
VDD18
3
VSS2
9
VSS4
14
VSS6
20
VSS8
26
VSS10
32
VSS12
38
VSS14
44
VSS16
49
VSS18
55
VSS20
61
VSS22
66
VSS24
72
VSS26
128
VSS28
134
VSS30
139
VSS32
145
VSS34
151
VSS36
156
VSS38
162
VSS40
168
VSS42
173
VSS44
179
VSS46
VSS48
VSS50
VSS52
GND1
GND2
NP_NC1
NP_NC2
VTT1
VTT2
VDDSPD
185
190
196
207
208
205
206
GND
203
204
199
I
12
C302
10PF/50V
NPO/+/-5%
GND
DIMM_CA_VREF_A [15]
DIMM_CA_VREF_B [16]
+3P3V
10PF/50V
NPO/+/-5%
12
D3CB9
0.1UF/6.3V
MLCC/+/-10%
GND
C303
I
GND
12
I
C6
10PF/50V
I
12
GND
D3CB7
0.1UF/6.3V
MLCC/+/-10%
I
12
D3CB8
4.7UF/6.3V
MLCC/+/-10%
PEGATRON DT-MB RESTRICTED SECRET
DDR3 CHANNEL B
DDR3 CHANNEL B
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Engineer:
IPPLP-TH
IPPLP-TH
IPPLP-TH
DDR3 CHANNEL B
Shrek_Tseng
Shrek_Tseng
Shrek_Tseng
1
16 97Friday, January 17, 2014
16 97Friday, January 17, 2014
16 97Friday, January 17, 2014
+VTT_DDR
12
I
GNDGND
Rev
Rev
Rev
A00
A00
A00
Vinafix.com
5
D D
+1P5V_DUAL
4
3
2
1
12
GND
C C
12
GND GND
12
NI
D3CB12
0.1UF/6.3V
MLCC/+/-10%
GND GND GND GND
12
NI
D3CB19
0.1UF/6.3V
MLCC/+/-10%
NI
D3CB13
0.1UF/6.3V
MLCC/+/-10%
NI
D3CB20
0.1UF/6.3V
MLCC/+/-10%
12
NI
D3CB14
0.1UF/6.3V
MLCC/+/-10%
12
I
D3CB21
1UF/6.3V
X5R/+/-10%
GND GNDGND GNDGND
12
12
NI
D3CB15
0.1UF/6.3V
MLCC/+/-10%
I
D3CB22
1UF/6.3V
X5R/+/-10%
12
12
NI
D3CB16
0.1UF/6.3V
MLCC/+/-10%
NI
D3CB23
0.1UF/6.3V
MLCC/+/-10%
12
NI
D3CB17
0.1UF/6.3V
MLCC/+/-10%
GND GND
12
I
D3CB24
1UF/6.3V
X5R/+/-10%
12
NI
D3CB18
0.1UF/6.3V
MLCC/+/-10%
12
NI
D3CB25
0.1UF/6.3V
MLCC/+/-10%
NOTE:
Place those cap close to CH A DIMM0
NOTE:
Place those cap close to CH B DIMM0
Place those cap between CH A DIMM1 and CH B DIMM0
12
B B
+1P5V_DUAL
12
I
D3CB32
22UF/6.3V
X5R/+/-20%
GND GND GNDGND GNDGND
12
NI
D3CB33
22UF/6.3V
X5R/+/-20%
I
D3CB26
22UF/6.3V
X5R/+/-20%
12
D3CB34
22UF/6.3V
X5R/+/-20%
12
NI
I
D3CB27
22UF/6.3V
X5R/+/-20%
12
12
NI
D3CB35
22UF/6.3V
X5R/+/-20%
I
D3CB28
22UF/6.3V
X5R/+/-20%
12
12
D3CB36
22UF/6.3V
X5R/+/-20%
I
I
D3CB29
22UF/6.3V
X5R/+/-20%
12
X5R/+/-20%
12
I
D3CB30
22UF/6.3V
X5R/+/-20%
I
D3CB37
22UF/6.3V
12
12
D3CB38
22UF/6.3V
X5R/+/-20%
I
D3CB31
22UF/6.3V
X5R/+/-20%
I
12
D3CB39
22UF/6.3V
X5R/+/-20%
I
A A
5
GND GND GND GND GND GND GND GND
Place those cap inside CPU SOCKET cavity
4
3
PEGATRON DT-MB RESTRICTED SECRET
DDR3 TERMINATION
DDR3 TERMINATION
DDR3 TERMINATION
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Engineer:
IPPLP-TH
IPPLP-TH
IPPLP-TH
1
Shrek_Tseng
Shrek_Tseng
Shrek_Tseng
17 97Friday, January 17, 2014
17 97Friday, January 17, 2014
17 97Friday, January 17, 2014
Rev
Rev
Rev
A00
A00
A00
Vinafix.com
5
D D
C C
4
3
2
1
B B
A A
<CORE DESIGN>
<CORE DESIGN>
<CORE DESIGN>
PEGATRON DT-MB RESTRICTED SECRET
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Engineer:
IPPLP-TH
IPPLP-TH
IPPLP-TH
1
XXXXXX
XXXXXX
XXXXXX
Shrek_Tseng
Shrek_Tseng
Shrek_Tseng
18 97Friday, January 17, 2014
18 97Friday, January 17, 2014
18 97Friday, January 17, 2014
Rev
Rev
Rev
A00
A00
A00
Vinafix.com
5
U1A
DMI_TXN0[10]
DMI_TXP0[10]
DMI_RXN0[10]
DMI_RXP0[10]
DMI_TXN1[10]
DMI_TXP1[10]
DMI_RXN1[10]
D D
C C
DMI_RXP1[10]
DMI_TXN2[10]
DMI_TXP2[10]
DMI_RXN2[10]
DMI_RXP2[10]
DMI_TXN3[10]
DMI_TXP3[10]
DMI_RXN3[10]
DMI_RXP3[10]
+1P5V_PCH +1P5V_PCH
12
12
I
1%
12
SR1
7.5KOHM
I
SR3
10KOhm
I
1%
12
SR2
7.5KOHM
DMI_RCOMP
PCIE_RCOMP
CLKIN_DMI_N
CLKIN_DMI_P
I
SR4
10KOhm
C20
G24
H24
D21
G26
B22
C22
K26
A24
B24
B19
C13
G22
L24
K24
B20
B21
F26
L26
F22
DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0
DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1
DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2
DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3
DMI_RCOMP
PCIE_RCOMP
CLKIN_DMI_N
CLKIN_DMI_P
DMI
4
AV10
USB2n0
AU10
USB2p0
AV11
USB2n1
AW11
USB2p1
AN14
USB2n2
AP14
USB2p2
AJ16
USB2n3
AK16
USB2p3
AU15
USB2n4
AV15
USB2p4
AU12
USB2n5
AT12
USB2p5
AV14
USB2n6
AW14
USB2p6
AU17
USB2n7
AT17
USB2p7
AW16
USB2n8
AV16
USB2p8
AN16
USB2n9
AP16
USB2p9
AJ18
USB2n10
AK18
USB2p10
AP18
USB2n11
AN18
USB2p11
AW18
USB2n12
AV18
USB2p12
AP20
USB2n13
AN20
USB2p13
3
USBN0 [33]
USBP0 [33]
USBN1 [33]
USBP1 [33]
USBN2 [34]
USBP2 [34]
USBN3 [34]
USBP3 [34]
USBN4 [35]
USBP4 [35]
USBN5 [35]
USBP5 [35]
USBN6 [37]
USBP6 [37]
USBN7 [37]
USBP7 [37]
USBN8 [36]
USBP8 [36]
USBN9 [36]
USBP9 [36]
USBN11 [28]
USBP11 [28]
USBN12 [29]
USBP12 [29]
Side USB3.0 Port
Rear USB3.0 Port
To Touch Conn
To Camera Conn
Rear USB2.0 Port
To WIFI
To MSATA
2
1
GND GND
USB3_RXN3[34]
USB3_RXP3[34]
USB3_TXN3[34]
USB3_TXP3[34]
USB3_RXN4[34]
USB3_RXP4[34]
USB3_TXN4[34]
USB3_TXP4[34]
LAN_PE1_RXN4[31]
LAN_PE1_RXP4[31]
LAN_PE1_TXN4[31]
LAN_PE1_TXP4[31]
B B
WLAN_PE1_RXP5[28]
WLAN_PE1_TXN5[28]
WLAN_PE1_TXP5[28]
WLAN_PE1_RXN6[28]
WLAN_PE1_RXP6[28]
WLAN_PE1_TXP6[28]
WLAN_PE1_TXN6[28]
CR_PE1_RXN7[30]
CR_PE1_RXP7[30]
CR_PE1_TXN7[30]
CR_PE1_TXP7[30]
K14
B12
B11
G14
D11
C11
H11
L14
F14
F11
J11
L11
G9
G3
G5
PERn1/USB3Rn3
PERp1/USB3Rp3
PETn1/USB3Tn3
PETp1/USB3Tp3
PERn2/USB3Rn4
PERp2/USB3Rp4
PETn2/USB3Tn4
PETp2/USB3Tp4
PERn3
PERp3
B9
PETn3
A9
PETp3
PERn4
PERp4
B8
PETn4
C8
PETp4
PERn5
F9
PERp5
B7
PETn5
A7
PETp5
F7
PERn6
H7
PERp6
E1
PETn6
D2
PETp6
K6
PERn7
K8
PERp7
PETn7
PETp7
J2
PERn8
J3
PERP8
H2
PETn8
H1
PETp8
PCIE
USB
USB3Rn1
USB3Rp1
USB3Tn1
USB3Tp1
USB3Rn2
USB3Rp2
USB3Tn2
USB3Tp2
USB3Rn5
USB3Rp5
USB3Tn5
USB3Tp5
USB3Rn6
USB3Rp6
USB3Tn6
USB3Tp6
OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14
TACH6/GPIO70
TACH7/GPIO71
CLKIN_DOT96_N
CLKIN_DOT96_P
USBRBIAS#
USBRBIAS
F20
G20
B18
C18
G18
H18
B15
B16
K20
L20
D15
C15
L18
K18
B14
A14
AE40
AF37
AD39
AD40
AF39
AC41
AF40
AG40
AK28
AT34
AP11
CLKIN_DOT_96N
AM11
CLKIN_DOT_96P
AV20
AU20
NOTE: USBRBIAS trace length < 500mil
Place those cap close to Conn side
NOTE:
1 2
SR16 10KOhmI
1 2
SR17 10KOhmI
USBRBIAS
1 2
SR19 22.6 OHM
I
1%
USB3_RXN1 [33]
USB3_RXP1 [33]
USB3_TXN1 [33]
USB3_TXP1 [33]
USB3_RXN2 [33]
USB3_RXP2 [33]
USB3_TXN2 [33]
USB3_TXP2 [33]
USB3_RXN5 [35]
USB3_RXP5 [35]
USB3_TXN5 [35]
USB3_TXP5 [35]
USB3_RXN6 [35]
USB3_RXP6 [35]
USB3_TXN6 [35]
USB3_TXP6 [35]
Native Sus
Native Sus
Native Sus
Native Sus
Native Sus
Native Sus
Native Sus
Native Sus
Native Core IPU 20K
Native Core IPU 20K
GND
+3P3VSB +3P3VSB
+3P3VSB +3P3VSB
12
RN34A10KOHM
I
56
34
RN34B10KOHM
I
+3P3V
RN34C10KOHM
12
I
SR621
10KOhm
I
+3P3V
12
SR12
10KOhm
78
RN34D10KOHM
I
I
OC0# [33,77]WLAN_PE1_RXN5[28]
OC1# [34,77]
OC2# [35,77]
OC3# [77]
OC4# [36,77]
OC5# [77]
CONFIG_2 [29,77]
EPSA_BIST# [51]
LVDS_CBL_DET_PIN14# [53]
CONFIG_3 [29,77]
NOTE:
Place those cap close to Conn side
SR207.5KOHM
3
+1P5V_PCH
<CORE DESIGN>
<CORE DESIGN>
<CORE DESIGN>
PEGATRON DT-MB RESTRICTED SECRET
PCI/SM/SPI/RTC 1-9
PCI/SM/SPI/RTC 1-9
PCI/SM/SPI/RTC 1-9
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
IPPLP-TH
IPPLP-TH
IPPLP-TH
Engineer:
1
Shrek_Tseng
Shrek_Tseng
Shrek_Tseng
19 97Friday, January 17, 2014
19 97Friday, January 17, 2014
19 97Friday, January 17, 2014
Rev
Rev
Rev
A00
A00
A00
A A
5
N1
N2
P2
P3
LYNX_POINT
I
FDI_RXN0
FDI_RXP0
FDI_RXN1
FDI_RXP1
FDI
FDI_RCOMP
FDI_CSYNC
4
FDI_INT
Rev 1.1
K2
L2
L3
FDI_RCOMP
I
1%
FDI_CSYNC [10]
FDI_INT [10]
12
Vinafix.com
5
+3P3VSB
NI
I
0 Ohm
1 2
PWROK[13,22,44]
D D
GPIO_WIRELESS_ALERT#[28]
C C
+3P3V_GPU
B B
CONFIG_0[29,77]
DATA1[51]
G_SENOER_INTER#[59]
TRIGGER_PIN#[51]
GPS_DISABLE#[29]
A A
APWROK[91]
I
SCALAR_MODE#[40]
Touch_CBL_DET#[37]
sideBrd_CLB_DET#[55]
GND
GND
+3P3V
GND
DATA0[51]
1
1
G
GPU_PWR_DET#
32
3
D
Q9427
2N7002
S
2
I_GPU
GND
+3P3V
12
APR11
+3P3V
RN1A10KOHM I
RN1B10KOHM I
1 2
3 4
APR160 Ohm
12
NI
I_UMA
I
SR38
10KOhm
1%
APR210 Ohm
12
7 8
RN33D 10KOHM
3 4
RN33B 10KOHM
5 6
RN33C 10KOHM
1 2
RN33A 10KOHM
0 Ohm
CK_33M_PCIFB[21]
RN1C10KOHM I
RN1D10KOHM I
5 6
7 8
I
I
I
I
12
APR36
PLTRST#[31,44,50,62]
R10
4.7KOHM
1 2
+3P3V
12
I
SR22
10KOhm
1%
S_GPI_CHASSIS_ID1
S_GPI_CHASSIS_ID0
BRD_ID2
+3P3V
RN3B8.2KOhmI
RN2A8.2KOhmI
RN2B8.2KOhmI
RN3D8.2KOhmI
7 8
3 4
1 2
3 4
NOTE:
Reserve for Intel 8 Series Chipset Family SKUs
5
4
CL_CLK[28]
CL_DATA[28]
CL_RST#[28]
APR2010KOhmNI 1%
12
GND
GPU_PWR_DET#
S_GPI_CHASSIS_ID2
RN3A8.2KOhmI
RN2D8.2KOhmI
RN3C8.2KOhmI
RN2C8.2KOhmI
7 8
5 6
5 6
1 2
NOBOM
NOBOM
NOBOM
NOBOM
4
3
U1B
CLINK
U36
CL_CLK
U35
CL_DATA
U34
CL_RST#
AA32
NI
AL31
AM31
AP31
AV30
AP28
AT31
AM28
AV34
AT30
AV35
AJ31
L38
H41
R31
L40
AP2
AT2
AP1
AA31
M40
AU29
AU27
AW28
AV27
AR30
AV29
AV28
AT27
AM22
AA37
A2
A3
B2
B1
C3
APWROK
FAN
PWM0
PWM1
PWM2
PWM3
TACH0/GPIO17
TACH1/GPIO1
TACH2/GPIO6
TACH3/GPIO7
TACH4/GPIO68
TACH5/GPIO69
SST
GPIO
SCLOCK/GPIO22
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
EDP
eDP_BKLTCTL
eDP_BKLTEN
eDP_VDDEN
PCI
PME#
GPIO35/NMI#
PIRQA#
PIRQB#
PIRQC#
PIRQD#
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
CLKIN_33MHZLOOPBACK
PLTRST#
TP1
TP2
TP4
TP3
TD_IREF
LYNX_POINT
I
12
SC5
10PF/50V
NPO/+/-5%
GND
IPU 20K
IPU 20K
IPU 20K
IPU 20K
IPU 20K
IPU 20K
+3P3VSB
12
GND
GPI Core
GPI Core
GPI Core
GPI Core
GPI Core
GPI Core
SSTCTL
IPD 10K
12
NI
SC6
10PF/50V
NPO/+/-5%
GND
GPI Core
GPI Core
GPI Core
GPI Core
NI
SR39
10K
PME#
GPO Core
GPI Core
GPI Core
GPI Core
GPI Core
1
TP_PCH_A2
ST4
1
TP_PCH_A3
ST5
1
TP_PCH_B2
ST6
1
TP_PCH_B1
ST7
PCH_TD_IREF PCH_GPIO55
12
SR48
I
8.2KOHM
1%
SATA_RXN0
SATA_RXP0
SATA_TXN0
SATA_TXP0
SATA_RXN1
SATA_RXP1
SATA_TXN1
SATA_TXP1
SATA_RXN2
SATA_RXP2
SATA_TXN2
SATA_TXP2
SATA_RXN3
SATA_RXP3
SATA_TXN3
SATA_TXP3
SATA_RXN4/PERn1
SATA_RXP4/PERp1
SATA_TXN4/PETn1
SATA_TXP4/PETp1
SATA_RXN5/PERn2
SATA_RXP5/PERp2
SATA_TXN5/PETn2
SATA_TXP5/PETp2
SATA
SATA0GP/GPIO21
SATA1GP/GPIO19
SATA2GP/GPIO36
SATA3GP/GPIO37
SATA4GP/GPIO16
SATA5GP/GPIO49
SATA_RCOMP
SATALED#
CLKIN_SATA_N
CLKIN_SATA_P
HOST
PLTRST_PROC#
SERIRQ
THRMTRIP#
PMSYNCH
GPIO50
GPIO51
GPIO52
GPIO53
GPIO54
GPIO55
Rev 1.1
3
TP14
RCIN#
PECI
B28
A28
F31
H31
D30
C30
B34
C34
A31
B31
B35
D35
B32
C32
G33
F33
A26
B26
L28
K28
C27
B27
G28
F28
M37
GPI Core
J40
H40
N41
M39
N40
GPI Core
GPI Core
GPI Core
GPI Core
GPI Core
IPU 20K
IPD 20K
IPD 20K
NOTE:
SATA_RCOMP trace
length < 500mil
D33
SATA_RCOMP
J39
H35
CLKIN_SATA_N
H36
CLKIN_SATA_P
+1P05V_PCH
I
HR64
1K 1%
mx_r0402_small
F41
N30
K36
G39
C40
G40
IPD 0.35K
F40
AH26
AU31
AJ26
AV31
AW33
R30
GPI Core
IPU 20K
IPU 20K
GPI Core
12
12
GND
SATA_Strap_0
SATA_Strap_1
12
GND
12
GND GND
NI
SC7
47PF/50V
NPO/+/-5%
GPO CoreIPU 20K
GPI Core
GPO Core
GPO CoreIPU 20K
SATA_RXN0 [39]
SATA_RXP0 [39]
SATA_TXN0 [39]
SATA_TXP0 [39]
SATA_RXN1 [39]
SATA_RXP1 [39]
SATA_TXN1 [39]
SATA_TXP1 [39]
SATA_RXN4 [29]
SATA_RXP4 [29]
SATA_TXN4 [29]
SATA_TXP4 [29]
SATA_RXN5 [29]
+3P3V +3P3V +3P3V
SATA_RXP5 [29]
SATA_TXN5 [29]
SATA_TXP5 [29]
12
NI
SR614
10KOhm
1%
+1P5V_PCH
12
I
SR35
7.5KOHM
1%
12
I
I
SR36
SR37
10KOhm
10KOhm
1%
1%
12
+3P3V +3P3V
NI
SC8
47PF/50V
NPO/+/-5%
GND
12
12
NI
SR49
1K
GNDGND
I
SR23
10KOhm
1%
12
I
SR45
8.2KOHM
1%
NI
SR50
1K
2
NOTE:
GPIO51 Description
H81 Support SATA600Port0~1:
0
1
1
Boot select straps
GPIO19
0
1
LPC
SPI
NOTE:
GPIO37 is for TLS confidentiality
1: Enable TLS
0: Disable TLS
NOTE:
Check front panel spec to decide install
those parts or not.
+3P3V +3P3V +3P3V
12
I
SR24
10KOhm
1%
12
NI
SR25
1K 1%
mx_r0402_small
5%PROTO
3 4
0 Ohm
12
I
SR46
8.2KOHM
1%
12
I
SR26
1K 1%
mx_r0402_small
SR616 10KOhm I1%
SR617 10KOhm NI1%
5%PROTO
1 2
0 Ohm
RN28B
12
I
SR40
10KOhm
1%
+3P3V
12
I
SR47
8.2KOHM
1%
12
I
SR27
10KOhm
1%
5%PROTO
3 4
0 Ohm
RN28A
OBSDATA_C1 [50,77]
12
I
SR41
10KOhm
1%
12
NI
SC9
47PF/50V
NPO/+/-5%
GND
12
I
SR28
10KOhm
1%
1 2
1 2
SR611 0 OhmPROTO
RN27B
OBSDATA_C2 [77]
+3P3V+3P3V+3P3V
12
1 2
APR270 Ohm
1 2
APR280 Ohm
1 2
1 2
I
SR42
10KOhm
1%
BRD_ID0 [77]
GND
GND
I
SATA_Strap [20,29]
I
SATA_Strap [20,29]
5%PROTO
RN27A
0 Ohm
OBSDATA_C3 [77]
OBSDATA_D0 [77]
HD_LED_IN# [55]
PLTRST_CPU# [11]
A20GATE [44]
RST_KB# [44]
SERIRQ [44,62]
H_THMTRIP# [11,80]
PM_SYNC [11]
ODD_2ndHDD_CBL_DET# [39]
K_GNT#1 [50]
converter_CBL_DET# [53]
PCH_GPIO53 [41]
SCL_FW_DATA [51,52]
OBSDATA_D1 [77]
PEGATRON DT-MB RESTRICTED SECRET
PCIE/USB/DMI 2-9
PCIE/USB/DMI 2-9
PCIE/USB/DMI 2-9
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
IPPLP-TH
IPPLP-TH
IPPLP-TH
Engineer:
1
Shrek_Tseng
Shrek_Tseng
Shrek_Tseng
20 97Friday, January 17, 2014
20 97Friday, January 17, 2014
20 97Friday, January 17, 2014
Rev
Rev
Rev
A00
A00
A00
Vinafix.com
5
+3P3V
4
3
2
1
NI
MR41
2.2KOHM
DDPB_AUXN_DP_IN[60]
DDPB_AUXP_DP_IN[60]
DDPC_HPD_HDMI[51]
GND
DDC_CLK_DP_IN[60]
DDC_DATA_DP_IN[60]
DDPB_HPD_DP_OUT[60]
DDPC_CTRL_CLK[51,52]
DDPC_CTRL_DATA[51,52]
NPO/+/-5%
12
I
SC12
10PF/50V
GND GNDGND
12
C94129510PF/50V I
HDMI_CTRL_CLK[57]
HDMI_CTRL_DATA[57]
HDMI_DDPD_HPD[57]
GND
1 2
SR68 1MImx_r0603_h24
1 3
2
5
D D
C C
B B
A A
1 2
NPO/+/-5%
+1P5V_PCH
12
I
Y10
25MHZ
4
GND
I
SR65
10KOhm
1%
NI
MR40
2.2KOHM
1 2
S1C47
NI
12
0.1UF/16V
X7R 10%
12
C654610PF/50V NI
I
SR64
7.5K
1%
1 2
PCH_CLKIN_BCLK_GND0#
PCH_CLKIN_BCLK_GND0
12
I
SR66
10KOhm
1%
GNDGND GND
XTAL_25M_PCH_IN
XTAL_25M_PCH_OUT
12
I
SC13
10PF/50V
IPD 20K
DIFFCLK_BIASREF
REFCLK14IN
12
I
SR67
10KOhm
1%
AK6
AK8
AM1
AJ5
AJ2
AG7
AG6
AN3
AM2
AH5
AG11
AG10
AN4
AN2
AJ4
R11
G16
F16
AR7
N7
N6
4
U1C
DDPB_AUXN
DDPB_AUXP
DDPB_CTRLCLK
DDPB_CTRLDATA
DDPB_HPD
DDPC_AUXN
DDPC_AUXP
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_HPD
DDPD_AUXN
DDPD_AUXP
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPD_HPD
DIFFCLK_BIASREF
CLKIN_GND_N
CLKIN_GND_P
REFCLK14IN
XTAL25_IN
XTAL25_OUT
LYNX_POINT
I
DP
VGA_VSYNC
VGA_HSYNC
VGA_DDC_CLK
VGA_DDC_DATA
VGA_GREEN
VGA_BLUE
CLOCK
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKOUT_DP_N
CLKOUT_DP_P
CLKOUT_DPNS_N
CLKOUT_DPNS_P
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
CLKOUT_PCIE_N6
CLKOUT_PCIE_P6
CLKOUT_PCIE_N7
CLKOUT_PCIE_P7
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
CLKOUT_33MHZ0
CLKOUT_33MHZ1
CLKOUT_33MHZ2
CLKOUT_33MHZ3
CLKOUT_33MHZ4
CLKOUTFLEX0/GPIO64
CLKOUTFLEX1/GPIO65
CLKOUTFLEX2/GPIO66
CLKOUTFLEX3/GPIO67
VGA_RED
DAC_IREF
VGA_IRTN
Rev 1.1
AH2
AH3
AL2
AL3
AC2
AE2
AC3
AF5
AG4
GNDGND
NOTE:
DAC_IREF should be as short as
possible to prevent noise coupling and IR drop
VGA_IRTN provides the return current path to the VGA DAC signals.
This should be routed out and tied directly to the MB ground plane
R2
T2
T3
T5
W2
U2
U6
U7
AE10
AE11
AC6
AC7
AC11
AC10
W11
W10
Y4
Y2
W7
W6
AA7
AA6
R6
R7
AA3
AA2
AE6
AE7
AV5
AV7
AU2
AN9
AU5
AV8
AT9
AV9
AU8
PCH_CLKOUT_PCI0
IPD 20K
PCH_CLKOUT_PCI1
IPD 20K
IPD 20K
PCH_CLKOUT_PCI3
IPD 20K
PCH_CLKOUT_PCI4
IPD 20K
IPD 20K
TP_CLKOUTFLEX1_GPIO65
IPD 20K
IPD 20K
TP_CLKOUTFLEX3_GPIO67
IPD 20K
SR619 10KOhm I1%
3
1 2
SR615
10KOhmI1%
1 2
+3P3V
+3P3V
DATA2 [51]
SCL_FW_CLK [51,52]
CK_100M_DMI# [11]
CK_100M_DMI [11]
CK_135M_DP# [10]
CK_135M_DP [10]
CK_135M_DPNS# [11]
CK_135M_DPNS [11]
CK_100M_CPUXDP# [76]
CK_100M_CPUXDP [76]
CK_100M_PE1# [28]
CK_100M_PE1 [28]
CK_100M_LAN# [31]
CK_100M_LAN [31]
CK_100M_CR# [30]
CK_100M_CR [30]
CK_100M_MSATA# [29]
CK_100M_MSATA [29]
CK_100M_PE2# [28]
CK_100M_PE2 [28]
GPU_CLKOUT_PEG_A# [79]
GPU_CLKOUT_PEG_A [79]
1 2
SR70 22 OHM 1%I
1 2
SR69 22 OHM 1%I
1 2
SR71 22 OHM 1%I
1 2
SR72 22 OHM 1%I
1 2
SR73 22 OHM 1%I
1 2
SR74 22 OHMNI
NOTE:
CLKOUT_DPNS_P/N
135 MHz differential clock with No SSC for
embedded DisplayPort* (eDP*)
WIFI
LAN
CraReader
MSATA
12
SCB3
10PF/50V
2
CK_33M_SIO [44]
CK_33M_TPM [62]
CK_33M_LPC [50]
CK_33M_PCIFB [20]
CK_14M_SIO [44]
NI
SCB6
10PF/50V
IPPLP-TH
IPPLP-TH
IPPLP-TH
GND GNDGNDGND GNDGND
12
NI
SCB7
10PF/50V
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
12
NI
12
NI
SCB4
10PF/50V
<CORE DESIGN>
<CORE DESIGN>
<CORE DESIGN>
PEGATRON DT-MB RESTRICTED SECRET
Date: Sheet of
Date: Sheet of
Date: Sheet of
12
I
SCB5
10PF/50V
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
12
NI
SCB8
10PF/50V
SATA/HOST/FAN 3-9
SATA/HOST/FAN 3-9
SATA/HOST/FAN 3-9
1
CK_14M_TPM [62]
Shrek_Tseng
Shrek_Tseng
Shrek_Tseng
21 97Friday, January 17, 2014
21 97Friday, January 17, 2014
21 97Friday, January 17, 2014
Rev
Rev
Rev
A00
A00
A00
Vinafix.com
5
+3P3V
12
SR75
10KOhm
NI
5%
D D
P217
HEADER_1X2P
I
+3P3VSB
AZ_SDATA_OUT[40]
AZ_SYNC[40]
AZ_BITCLK[40]
AZ_RST#[40,42]
C C
9,60,76,77]
9,60,76,77]
B B
A A
SMB_CLK_RESUME
SMB_DATA_RESUME
SML0_LANNFC_CLK[31]
SML0_LANNFC_DATA[31]
GPIO_WIRELESS_DISABLE#[28]
SIO_SMLINK_CLK[44]
SIO_SMLINK_DATA[44]
CPUPWRGD[11]
DRAM_PWROK[11]
PWROK[13,20,44]
VRM_PWRGD[44,64,76]
RSMRST#[44,77]
PCH_DPWROK[44,77]
P216
HEADER_1X2P
+BATT
1 2
R13 20K 1%Imx_r0402_small
1 2
R14 20K 1%Imx_r0402_small
+3P3VA
I
12
C19
1UF/6.3V
X5R 10%
mx_c0603
12
GND
GND
12
GND GND GND GND
BT_DISABLE#[28]
TMIN_SHIFT[44]
SYS_RESET#[11,50,76,77]
1
2
SW50_R
1 2
BAT R303_D8
XBT1
BATT_HOLDER
NI
SC14
10PF/50V
NPO/+/-5%
SPI_CS1#[26]
SPI_CS0#[26]
SPI_MOSI[26]
SPI_MISO[26]
SPI_CLK[26]
SPI_IO2[26]
SPI_IO3[26]
R12 4.7KOHMI
C17 1UF/6.3V MLCC/+/-10%mx_c0603I
C15 1UF/6.3V MLCC/+/-10%mx_c0603I
I
R15
1KOhm
1%
mx_r0402
5
12
NI
SC15
10PF/50V
NPO/+/-5%
+3P3VSB
12
12
150PF/50V
NPO/+/-5%
1 2
1 2
1 2
Critical
BATT1
3V/220mAh
KTS
LITHIUM BATT
CR2032
DATA3[51]
NOTE:
HDA_SDO
Disable ME in Manufacturing Mode
--> connect to High.
E50_1
2
1
SR89 1K 1%
I
mx_r0402_small
SR90 33 OHM
I
SR91 33 OHM
I
SR93 33 OHM
I
SR94 33 OHM
I
12
12
+3P3VSB +3P3VSB +3P3VSB +3P3VSB +3P3VSB
12
I
SR111
2.2KOHM
12
NI
SC18
150PF/50V
NPO/+/-5%
+3P3V
RTCRST# [50]
I
D1
1
2
BAT54CW
NI
NI
SC17
SC16
10PF/50V
10PF/50V
NPO/+/-5%
NPO/+/-5%
I
I
SR112
SR113
499 Ohm
4.7KOHM
1 2
1 2
12
12
NI
NI
SC20
SC19
150PF/50V
150PF/50V
NPO/+/-5%
NPO/+/-5%
12
12
GND
AZ2025-01H
+BATT
NI
12
AD7
3
AZ2025-01H
12
I
SC27
18PF/50V
NPO 5%
GND
AZ_SDATA_IN[40]
1 2
1 2
1 2
1 2
1 2
12
I
I
SR115
SR114
499 Ohm
2.2KOHM
12
NI
NI
SC22
SC21
150PF/50V
NPO/+/-5%
PR11KOhm1%
I
R112.2KOHM I
AD8
GND GND
1 2
SR131 10M MX_R0603
I
1 4
XTAL:0708-0006000,0708-000L000
4
NI
SR76
5%
10KOhm
LAD0[44,50,62]
LAD1[44,50,62]
LAD2[44,50,62]
LAD3[44,50,62]
LFRAME#[44,50,62]
HDA_SDO_R [27]
HDA_SYNC_R
HDA_BITCLK_24MHZ_R
HDA_AZRST#_R
12
I
SR116
2.2KOHM
12
NI
SC23
150PF/50V
NPO/+/-5%
GNDGNDGNDGNDGNDGND
1 2
C12 100KOHM 1%I
1 2
C13 150PF/50VNI
1 2
C14 15PF/50VNI
1 2
C18 39PF/50VNI
1 2
C16 180PF/50V
I
12
SRTCRST#
NI
RTCRST#
Y5 32.768Khz
2
3
I
GNDGND GND
4
+3P3V
12
IPU 20K
IPU 20K
IPU 20K
IPU 20K
IPU 20K
IPU 20K
IPD 20K
IPD 20K
IPD 20K
IPD 20K
IPD 20K
IPD 20K
IPU 20K
IPU 20K
IPU 20K
IPD 20K
IPU 20K
IPU 20K
IPU 20K
Native Sus
Native Sus
Native Sus
Native Sus
Native Sus
+BATT+BATT
12
SR124
390KOHM
I
I
PCH_INTVRMEN
NPO 5%
PCH_RTCX1
PCH_RTCX2
12
I
SC28
18PF/50V
NPO 5%
U1D
AK26
LDRQ1#/GPIO23
AN24
LAD0
AP26
LAD1
AJ24
LAD2
AN26
LAD3
AK22
LDRQ0#
AP24
LFRAME#
AT26
HDA_SDI0
AV22
HDA_SDI1
AT22
HDA_SDI2
AW23
HDA_SDI3
AU22
HDA_SDO
AV24
HDA_SYNC
AV23
HDA_BCLK
AU24
HDA_RST#
R40
SPI_CS2#
R35
SPI_CS1#
R38
SPI_CS0#
P40
SPI_MOSI
R36
SPI_MISO
U39
SPI_CLK
U40
SPI_IO2
U37
SPI_IO3
AG36
SMBCLK
AG32
SMBDATA
AG31
SMBALERT#/GPIO11
AE32
SML0CLK
AE35
SML0DATA
AG35
SML0ALERT#/GPIO60
AK36
SML1CLK/GPIO58
AK33
SML1DATA/GPIO75
AJ39
SML1ALERT#/PCHHOT#/GPIO74
12
SR125
390KOHM
AM41
DSWVEN
DSWVRMEN
AV36
INTVRMEN
D40
PROCPWRGD
AE38
DRAMPWROK
AT40
PWROK
W31
SYS_PWROK
N36
SYS_RESET#
AM40
RSMRST#
AV38
DPWROK
AR39
SRTCRST#
AR38
RTCRST#
AN40
RTCX1
AN39
RTCX2
LYNX_POINT
I
LPC
AUDIO
SPI
3
BMBUSY#/GPIO0
GPIO32
DOCKEN#/GPIO33
GPIO34
LAN_PHY_PWR_CTRL/GPIO12
HDA_DOCK_RST#/GPIO13
SLP_WLAN#/GPIO29
ACPRESENT/GPIO31
PCIECLKRQ0#/GPIO73
PCIECLKRQ1#/GPIO18
PCIECLKRQ2#/GPIO20/SMI#
PCIECLKRQ3#/GPIO25
PCIECLKRQ4#/GPIO26
PCIECLKRQ5#/GPIO44
PCIECLKRQ6#/GPIO45
PCIECLKRQ7#/GPIO46
SUSWARN#/SUSPWRNACK/GPIO30
GPIO8
GPIO15
GPIO24
GPIO28
GPIO27
JTAG_TMS
JTAG_TDO
JTAG_TDI
JTAG_TCK
TP20
GPIO57
GPIO72
SUSACK#
SUSCLK/GPIO62
SUS_STAT#/GPIO61
WAKE#
INTRUDER#
SPKR
PWRBTN#
TP21
SLP_S3#
SLP_S4#
SLP_S5#/GPIO63
SLP_A#
SLP_LAN#
SLP_SUS#
Rev 1.1
3
2
+3P3V +3P3V +3P3V +3P3VSB+3P3VSB +3P3VSB +3P3VA +3P3VA
12
I
SR77
10KOhm
1%
G38
GPI Core
N32
GPO Core
AV26
GPO Core
N34
GPI Core
AC40
GPO Sus
AL40
Native Sus
AN22
GPI Sus
AC32
GPO Sus
AE34
GPO Sus
V41
GPO Sus
AL39
GPI DSW
AU34
AM36
W34
Native Sus
P39
Native Core
P37
Native Core
AA39
Native Sus
W35
Native Sus
AA36
Native Sus
W32
Native Sus
AA40
Native Sus
W40
IPU 20K
Y38
W39
IPU 20K
Y40
IPD 20K
W37
AC36
GPI Sus
AJ40
AG41
Native Sus
AJ37
IPU 20K
W36
Native Sus
AD37
Native Sus
AE36
RI#
AK34
AR41
R32
IPD 20K
AK41
IPU 20K
AC35
AK40
AT35
AA35
Native Sus
AN37
AU36
AK38
NI
SR79
10KOhm
1%
IPU 20K
IPU 20KGPI DSW
IPD 20KGPI DSW
+3P3VSB +3P3V
12
I
SR95
10KOhm
1%
IPU 20K
IPU 20K
12
NI
SR119
10KOhm
1%
GND
IPU 20KNative Sus
PCH_SUSWARN#
+3P3VSB
12
I
SR127
10KOhm
1%
12
NI
SC25
10PF/50V
NPO/+/-5%
GND
TP_SLP_S0#
12
12
I
SR80
SR81
10KOhm
10KOhm
1%
12
NI
SR92
10KOhm
1%
12
I
SR96
GND
10KOhm
1%
PCH_JTAG_TMS [77]
PCH_JTAG_TDO [77]
PCH_JTAG_TDI [77]
PCH_JTAG_TCK [77]
PCH_JTAG_RST [77]
12
NI
SC26
0.1UF/16V
GND
1
ST16
NOBOM
I
1%
12
12
I
SR82
10KOhm
1%
MFG_MODE#
12
RN35A10KOHM
I
GND
SR207 0 Ohm PROTO
+3P3VSB
12
I
SR120
10KOhm
1%
PWRBTN# [44,50,55,76,77]
SLP_S3# [44,50,67,72,74]
SLP_S4# [44,50,68,72]
KEY_A_PWR [74]
SLP_A# [44,50,68,91]
SLP_LAN# [67]
SLP_SUS# [44,70,71]
2
+3P3VSB
34
RN35B10KOHM
I
BRD_ID1
1 2
12
I
SR84
10KOhm
1%
CLR_PWD#
56
78
RN35C10KOHM
RN35D10KOHM
I
I
OBSDATA_D3 [77]
+3P3VA
12
I
SR122
10KOhm
1%
12
+3P3VA
NI
SC24
10PF/50V
12
NPO/+/-5%
GND
12
GND
<CORE DESIGN>
<CORE DESIGN>
<CORE DESIGN>
PEGATRON DT-MB RESTRICTED SECRET
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
12
I
SR87
10KOhm
1%
SR103 0 Ohm PROTO
1%
12
SR61810KOhm1% I
+3P3VSB
12
SR613
10KOhm
+BATT
12
I
SR128
I
SR129
10KOhm
1M
1%
NI
SC139
10PF/50V
NPO/+/-5%
IPPLP-TH
IPPLP-TH
IPPLP-TH
I
SR88
10KOhm
1%
1 2
I
1%
1
12
I_GPU
0 Ohm
1 2
APR12
SR10210KOhm
12
+3P3VSB
NI
GPURST_GPIO8 [79]
S_PECI_REQ# [44]
GPUPW_EN [71,91,93]
BRIGHTNESS_DISABLE# [51]
1
ST135
P215:12
MINI_JUMPER
I
NOBOM
HSW_STRAP [11,77]
LAN_DISABLE# [31]
LVDS_CBL_DET_PIN24# [53]
PRE_OS_BIST# [51]
SKTOCC# [11]
DEVSLP [29]
SLP_WLAN# [74]
LAN_WAKE# [31]
HEADER_1X2P
SPKR_CBL_DET# [41]
MSATA_CLKREQ# [29]
OBSDATA_D2 [77]
Mode_button# [51,55]
CAMERA_CBL_DET# [37]
ME_Disable# [27]
INTRUD_CBL_DET# [53,55]
WLAN_CLKREQ# [28]
P215
I
NOTE:
SUSCLK/GPIO62
PLL On-Die Voltage
Regulator Enable should
be NC for internal
VccVRM
WWAN_DISABLE# [29]
VOLUME_DISABLE# [51]
SUS_CLK [28,29,44]
CONFIG_1 [29]
O_IO_PME# [44]
WAKE# [28,29]
Alarm_open# [53,55]
SPKR [41]
AUDIO/LPC/MISC 4-9
AUDIO/LPC/MISC 4-9
AUDIO/LPC/MISC 4-9
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
1
Shrek_Tseng
Shrek_Tseng
Shrek_Tseng
22 97Friday, January 17, 2014
22 97Friday, January 17, 2014
22 97Friday, January 17, 2014
GND
1
2
Rev
Rev
Rev
A00
A00
A00
Vinafix.com
5
4
3
2
1
U1E
+1P05V_PCH
12
I
GND
SC30
0.1UF/6.3V
MLCC/+/-10%
D D
NOTE:
Pin AF19, AF20, AF22, AF23 are connected
to on bottom layer only. Not connected on
VCC layer to avoid noise coupling.
I
I
SCB14
1UF/6.3V
SL1
10UH/125mA
mx_l0805
12
I
SCB15
1UF/6.3V
X5R/+/-10%
21
VCCCLK 0.306 A
NI
SCB16
1UF/6.3V
X5R/+/-10%
12
GND GND GNDGND GND GND
SCB17
1UF/6.3V
X5R/+/-10%
12
I
+1P05V_PCH
+1P05V_PCH
C C
12
X5R/+/-10%
VCCIO 3.629 A
12
GND GNDGND GND GND GND
B B
A A
I
SCB25
10UF/6.3V
X5R 10%
mx_c0805
12
12
GND GNDGND
12
I
SCB26
10UF/6.3V
X5R 10%
mx_c0805
DCPSUSBYP_RC DCPSUSBYP
12
I
SCB48
1UF/16V
X7R 10%
mx_c0603
12
NI
SCB27
1UF/6.3V
X5R/+/-10%
SR133 5.1 OHM
I1%
12
I
SCB49
0.1UF/6.3V
MLCC/+/-10%
5
12
X5R/+/-10%
+1V_CPU2PCH
12
I
SCB29
1UF/6.3V
I
SCB28
1UF/6.3V
X5R/+/-10%
PCH_INTERNAL_VRM_DCPRTC
PCH_INTERNAL_VRM_DCPSST
I
SCB50
0.1UF/6.3V
MLCC/+/-10%
VCCCORE 1.29 A
12
12
SCB18
1UF/6.3V
X5R/+/-10%
12
SCB30
1UF/6.3V
X5R/+/-10%
I
SC29
0.1UF/6.3V
MLCC/+/-10%
GND GND
I
I
GND GND
+1P05V_ME
GND
12
GNDGND GND
12
12
12
12
12
NI
SC31
0.1UF/6.3V
MLCC/+/-10%
12
I
SCB9
10UF/6.3V
X5R 10%
mx_c0805
NI
SCB19
1UF/6.3V
X5R/+/-10%
I
SCB31
1UF/6.3V
X5R/+/-10%
12
GND
12
I
SCB10
1UF/16V
X7R 10%
mx_c0603
I
SCB20
1UF/6.3V
X5R/+/-10%
NI
SCB32
1UF/6.3V
X5R/+/-10%
VCCASW 0.67 A
12
GND
I
SCB39
1UF/6.3V
X5R/+/-10%
I
SCB38
10UF/6.3V
X5R 10%
mx_c0805
NI
SC32
0.1UF/6.3V
MLCC/+/-10%
V_PROC_IO 0.004 A
12
I
SCB44
1UF/16V
X7R 10%
mx_c0603
NOBOM
NOBOM
NOBOM
12
0.1UF/6.3V
MLCC/+/-10%
GNDGND
SCB45
ST18
ST19
ST20
I
12
SCB46
0.1UF/6.3V
MLCC/+/-10%
GND
1
TP_PCH_VCCSUS
1
TP_DCPSUS1
1
TP_DCPSUS2
I
NOTE:
Caps can be removed on DcpSus
(pin AE30, P19 and AJ22)
if Internal VRM is used.
4
AA19
AA20
AB16
AB17
AB19
AB20
AD16
W17
W19
W23
W25
AC12
AB1
W14
AB2
AA16
W16
AF19
AF20
AF22
AF23
AP22
M14
AA23
AA25
AA26
AB22
AB23
AB25
AB26
AD17
AD19
AD20
AD22
AD23
W26
AD25
AF25
AU40
AU41
AJ22
AW35
AH28
AE30
V17
V19
V20
V22
V23
V25
U12
V14
T16
V16
P14
P16
P17
P22
P23
P25
P26
P28
T19
T20
C39
P19
VCC11
VCC12
VCC14
VCC15
VCC16
VCC17
VCC18
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCCIO12
VCC13
VCCCLK2
VCCCLK3
VCCCLK5
VCCCLK8
VCCCLK7
VCCCLK6
VCCCLK1
VCCCLK4
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCUSBPLL
VCCIO1
VCCASW2
VCCASW3
VCCASW4
VCCASW5
VCCASW6
VCCASW7
VCCASW8
VCCASW9
VCCASW10
VCCASW11
VCCASW12
VCCASW13
VCCASW1
VCCASW14
VCCASW15
V_PROC_IO
DCPSUSBYP1
DCPSUSBYP2
DCPSUS2
DCPRTC
DCPSST
DCPSUS1
DCPSUS3
LYNX_POINT
I
DMI_IREF
FDI_IREF
ICLK_IREF
PCIE_IREF
SATA_IREF
VCCVRM6
VCCVRM2
VCCVRM10
VCCVRM7
VCCVRM3
VCCVRM4
VCCVRM11
VCCVRM9
VCCVRM8
VCCVRM5
VCCVRM1
VCCADAC1_5
VCCADACBG3_3
VCC3_3_1
VCC3_3_6
VCCCLK3_3_3
VCCCLK3_3_4
VCCCLK3_3_5
VCCCLK3_3_6
VCCCLK3_3_7
VCCCLK3_3_8
VCCCLK3_3_10
VCCCLK3_3_12
VCCCLK3_3_13
VCCCLK3_3_1
VCCCLK3_3_2
VCCCLK3_3_9
VCCCLK3_3_11
VCC3_3_2
VCC3_3_3
VCC3_3_4
VCC3_3_5
VCCSPI
VCCSUSHDA
VCCSUS3_3_7
VCCSUS3_3_8
VCCSUS3_3_2
VCCSUS3_3_3
VCCSUS3_3_4
VCCSUS3_3_5
VCCSUS3_3_6
VCCSUS3_3_1
VCCSUS3_3_9
VCCDSW3_3_1
VCCDSW3_3_2
VCCDSW3_3_3
VCCRTC
Rev 1.1
+1P5V_PCH
A19
N11
N10
B13
A33
B37
A38
K1
B39
A39
A40
T14
C2
C1
B4
A4
AF2
AE1
B6
AW21
AM7
AM9
AP5
AP7
AR4
AT5
AV4
AW4
AW9
AG12
AK11
AV3
AW3
U30
W30
AF26
AG1
VCCSPI 0.022 A
R41
AW26
AM33
AN33
AH18
AH20
AH22
AJ20
AK20
P20
AP35
AV39
AW38
AW39
AP33
GND
+3P3V_ME
See Page 67
12
SCB36
1UF/6.3V
X5R/+/-10%
I
GND
+3P3VA
VCCDSW3_3 0.015 A
12
0.1UF/6.3V
MLCC/+/-10%
GND
12
SCB51
0.1UF/6.3V
MLCC/+/-10%
GND GND
3
NOTE:
Backup 09X241023060 1UH/300mA(0805)
and install 10uF for External VRM
NOTE:
Backup 09X241031260 10UH/125mA(0805)
and install 10uF/1Ω for External VRM
VCCVRM 0.183 A
VCCADAC3_3 0.0133 A/ VCCADAC1_5 0.07A
+3P3V_BG
VCC3_3 0.0133 A
See Page 66
12
GND
I
SCB47
I
I
SCB11
0.1UF/6.3V
+BATT
12
X5R/+/-10%
12
I
SCB12
1UF/6.3V
X5R/+/-10%
GND
VCCCLK3_3 0.055 A
12
12
12
I
SCB21
1UF/6.3V
X5R/+/-10%
SCB33
0.1UF/6.3V
MLCC/+/-10%
I
SCB22
1UF/6.3V
X5R/+/-10%
GNDGND GND GND
12
I
SCB34
0.1UF/6.3V
MLCC/+/-10%
GND
VCCSUS 0.261 A
I
SCB40
0.1UF/6.3V
MLCC/+/-10%
I
12
SCB41
0.1UF/6.3V
MLCC/+/-10%
12
SCB52
1UF/6.3V
12
X5R/+/-10%
+3P3V
12
I
X5R/+/-10%
GNDGND
12
I
X5R/+/-10%
GNDGNDGND GND
I
SCB23
1UF/6.3V
I
SCB35
1UF/6.3V
I
SCB42
1UF/6.3V
+3P3V
12
+3P3VSB
12
I
SCB24
1UF/6.3V
X5R/+/-10%
I
SCB43
1UF/6.3V
X5R/+/-10%
12
I
SCB13
0.1UF/6.3V
MLCC/+/-10%
GND
GND
NOTE:
PCH power plane isolation
<CORE DESIGN>
<CORE DESIGN>
<CORE DESIGN>
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
PEGATRON DT-MB RESTRICTED SECRET
VGA/DP/HDMI 5-9
VGA/DP/HDMI 5-9
VGA/DP/HDMI 5-9
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
IPPLP-TH
IPPLP-TH
IPPLP-TH
Engineer:
1
+1P5V_PCH
Shrek_Tseng
Shrek_Tseng
Shrek_Tseng
23 97Friday, January 17, 2014
23 97Friday, January 17, 2014
23 97Friday, January 17, 2014
A00
A00
A00
Rev
Rev
Rev
Vinafix.com
5
4
3
2
1
U1F
D9
VSS21
E12
VSS44
E3
VSS40
E31
VSS45
E35
VSS46
E38
VSS47
E4
VSS41
D D
C C
B B
A A
5
E5
VSS42
E7
VSS43
F18
VSS48
F24
VSS49
F35
VSS50
F37
VSS51
F38
VSS52
G2
VSS53
H14
VSS58
H16
VSS59
H20
VSS60
H22
VSS61
H26
VSS62
H28
VSS63
H33
VSS64
H34
VSS65
H38
VSS66
H4
VSS54
H6
VSS55
H8
VSS56
H9
VSS57
J31
VSS68
J37
VSS69
J5
VSS67
K31
VSS72
K4
VSS70
K9
VSS71
L37
VSS73
L41
VSS74
M16
VSS75
M18
VSS76
M20
VSS77
M22
VSS78
M24
VSS79
M26
VSS80
M28
VSS81
N31
VSS84
N35
VSS85
N38
VSS86
N4
VSS82
N8
VSS83
R1
VSS87
R10
VSS89
R34
VSS90
R8
VSS88
T17
VSS91
T22
VSS92
T23
VSS93
T25
VSS94
T26
VSS95
T28
VSS96
U1
VSS97
U31
VSS100
U32
VSS101
U4
VSS98
U8
VSS99
V26
VSS102
V28
VSS103
V38
VSS104
V40
VSS105
W12
VSS109
W20
VSS110
W22
VSS111
W28
VSS112
W3
VSS106
W5
VSS107
W8
VSS108
Y1
VSS113
Y41
VSS114
D12
VSS22
D13
VSS23
D14
VSS24
D16
VSS25
D18
VSS26
D19
VSS27
D20
VSS28
D22
VSS29
D24
VSS30
D25
VSS31
D26
VSS32
D27
VSS33
D28
VSS34
D31
VSS35
D32
VSS36
D8
VSS20
D7
VSS19
D6
VSS18
D4
VSS17
D37
VSS38
D34
VSS37
C6
VSS12
C37
VSS14
C25
VSS13
GND GND
LYNX_POINT
I
VSS1
VSS2
VSS3
VSS4
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS115
VSS116
VSS127
VSS128
VSS126
VSS131
VSS133
VSS134
VSS129
VSS130
VSS135
VSS136
VSS137
VSS140
VSS141
VSS138
VSS142
VSS139
VSS144
VSS145
VSS146
VSS147
VSS148
VSS150
VSS151
VSS152
VSS149
VSS153
VSS154
VSS155
VSS156
VSS158
VSS159
VSS157
VSS161
VSS162
VSS160
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS163
VSS164
VSS165
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS184
VSS183
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS181
VSS182
VSS200
VSS201
VSS204
VSS205
VSS207
VSS212
VSS211
VSS6
VSS5
VSS7
VSS8
VSS9
Rev 1.1
A12
A16
A21
A35
AA10
AA11
AA12
AA14
AA17
AA22
AA28
AA30
AA34
AA5
AA8
AB14
AB28
AB4
AC30
AC34
AC38
AC5
AC8
AD14
AD26
AD28
AE12
AE31
AE4
AE41
AE8
AF14
AF16
AF17
AF28
AG2
AG30
AG34
AG38
AG8
AH14
AH16
AJ1
AJ28
AK24
AK37
AK9
AL11
AL37
AL5
AM14
AM16
AM18
AM20
AM24
AM26
AM35
AM38
AM4
AM6
AM8
AN28
AP4
AP9
AR11
AR35
AR37
AT11
AT10
AT14
AT15
AT16
AT18
AT20
AT21
AT23
AT24
AT28
AT29
AT33
AT36
AT38
AT7
AT8
AU3
AU39
AV12
AV17
AV33
AW30
AW7
B25
B3
B30
B33
B38
GND
4
AT41
AU1
AV40
AV41
AW2
AW40
AT1
AV1
AV2
B40
B41
C41
D41
D1
U1G
VSS180
VSS198
VSS199
VSS202
VSS203
VSS208
VSS209
VSS210
VSS213
VSS10
VSS11
VSS15
VSS16
VSS39
LYNX_POINT
I
TP19
TP18
TP23
TP24
TP9
TP8
TP22
TP11
TP6
TP25
TP17
TP13
TP12
TP7
TP16
TP5
TP15
TP10
VSS132
VSS143
VSS206
Rev 1.1
3
U11
U10
AJ14
AK14
K34
K33
AH24
L16
K16
AM34
R12
N12
L22
K22
R4
K5
P5
L5
AC31
AF3
AV21
TP_PCH_TP19
TP_PCH_TP18
TP_PCH_TP23
TP_PCH_TP9
TP_PCH_TP8
TP_PCH_TP22
TP_PCH_TP11
TP_PCH_TP6
TP_PCH_TP25
TP_PCH_TP17
TP_PCH_TP13
TP_PCH_TP12
TP_PCH_TP7
TP_PCH_TP16
TP_PCH_TP5
TP_PCH_TP15
TP_PCH_TP10
GND
GND
1
ST21
NOBOM
1
ST22
NOBOM
1
ST23
NOBOM
1
ST24
NOBOM
1
ST25
NOBOM
1
ST26
NOBOM
1
ST27
NOBOM
1
ST28
NOBOM
1
ST29
NOBOM
1
ST30
NOBOM
1
ST31
NOBOM
1
ST32
NOBOM
1
ST33
NOBOM
1
ST34
NOBOM
1
ST35
NOBOM
1
ST36
NOBOM
1
ST37
NOBOM
1
ST38
NOBOM
Remove Heatsink
Solder Pad Recommendation
NOTE:
PEGATRON DT-MB RESTRICTED SECRET
CLK/NVRAM/FDI 6-9
CLK/NVRAM/FDI 6-9
CLK/NVRAM/FDI 6-9
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
IPPLP-TH
IPPLP-TH
IPPLP-TH
Engineer:
1
Shrek_Tseng
Shrek_Tseng
Shrek_Tseng
24 97Friday, January 17, 2014
24 97Friday, January 17, 2014
24 97Friday, January 17, 2014
A00
A00
A00
Rev
Rev
Rev
Vinafix.com
5
4
3
2
1
12
SC119
0.1UF/6.3V
+1P5V_DUAL
12
NI
GND
SC118
0.1UF/6.3V
+VDDC
NI
GND
12
SC121
0.1UF/6.3V
+VDDC
NI
GND
12
SC120
0.1UF/6.3V
+12V_CPU
12
NI
GND
SC141
0.1UF/6.3V
+12VSA
12
NI
GND
SC142
0.1UF/6.3V
1 2
SC110 0.1UF/6.3V
NI
1 2
SC111 0.1UF/6.3V
NI
1 2
SC112 0.1UF/6.3V
NI
1 2
SC140 0.1UF/6.3V
I
1 2
SC143 0.1UF/6.3V
D D
C C
NI
AGNDGND
+5V_DUAL +5V_DUAL +5V_DUAL +5V_DUAL
SC114
0.1UF/6.3V
12
NI
GNDGNDGNDGND
NI
12
SC116
0.1UF/6.3V
NI
12
SC115
0.1UF/6.3V
12
NI
SC113
0.1UF/6.3V
+12VBDC_VIN
12
SC144
22UF/16V
X5R/+/-20%
NI
GND
+1P5V_DUAL
NI
GND
B B
A A
PEGATRON DT-MB RESTRICTED SECRET
PCH_DPWROK & SLP_SUS
PCH_DPWROK & SLP_SUS
PCH_DPWROK & SLP_SUS
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Engineer:
IPPLP-TH
IPPLP-TH
IPPLP-TH
1
Shrek_Tseng
Shrek_Tseng
Shrek_Tseng
25 97Friday, January 17, 2014
25 97Friday, January 17, 2014
25 97Friday, January 17, 2014
A00
A00
A00
Rev
Rev
Rev
Vinafix.com
5
I
P13:12
D D
C C
MINI_JUMPER
SPI_CS1#[22]
SPI_CS0#[22]
SPI_MISO[22]
SPI_IO2[22]
SPI_MOSI[22]
SPI_CLK[22]
SPI_IO3[22]
I
P13:34
MINI_JUMPER
NI
NI
1
3
5
7
9
11
1 2
1 2
P13
2
4
8
10
12
HEADER_2X6P_K6
I
F3R50
F3R60
+3P3V_ME
GND
4
+3P3V_ME
12
I
F3R3
1K
1%
mx_r0402_small
1 2
F3R7 33 OHMI1%
1 2
F3R8 33 OHMI1%
1 2
F3R9 33 OHMI1%
1 2
F3R10 33 OHMI1%
1 2
F3R11 33 OHMI1%
1 2
F3R12 33 OHMI1%
1 2
F3R13 33 OHMI1%
1 2
F3R14 33 OHMI1%
1 2
F3R15 33 OHMI1%
1 2
F3R16 33 OHMI1%
+3P3V_ME
12
3
I
F3R2
1K
1%
mx_r0402_small
Dual_SPI_CS1#_E19
Dual_SPI_DO
Dual_FWH_WP#
SPI_CS0#_E19
SPI_DO
FWH_WP#
GND
GND
J132
1
CS#
2
DO(IO1)
3
WP#(IO2)
4
GND
W25Q32FVSSIQ
I
J131
1
CS#
2
DO(IO1)
3
WP#(IO2)
4
GND
W25Q64FVSSIQ
I
VCC
HOLD#(IO3)
CLK
DI(IO0)
VCC
CLK
DI(IO0)
HOLD#/RESET#(IO3)
8
7
6
5
8
7
6
5
SPI_HOLD#
SPI_CK
SPI_DI
2
+3P3V_ME
Dual_SPI_HOLD#
Dual_SPI_CK
Dual_DI
+3P3V_ME
12
12
I
F3R1
1K
1%
mx_r0402_small
I
F3R4
1K
1%
mx_r0402_small
GND
12
GND
12
I
F3CB1
0.1UF/6.3V
I
F3CB3
0.1UF/6.3V
+3P3V_ME
12
GND
+3P3V_ME
12
GND
I
F3CB2
1UF/6.3V
X5R/+/-10%
I
F3CB4
1UF/6.3V
X5R/+/-10%
1
B B
A A
PEGATRON DT-MB RESTRICTED SECRET
SM BUS & SPI ROM
SM BUS & SPI ROM
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Engineer:
IPPLP-TH
IPPLP-TH
IPPLP-TH
SM BUS & SPI ROM
1
Shrek_Tseng
Shrek_Tseng
Shrek_Tseng
26 93Friday, January 17, 2014
26 93Friday, January 17, 2014
26 93Friday, January 17, 2014
A00
A00
A00
Rev
Rev
Rev
Vinafix.com
5
A
4
3
2
1
ME Disable
D D
C C
ME_Disable#[22]
SR135
1 2
10KOhmI1%
PCH_GPIO26_R
I
PMBS3906
1
Q1
B
+3P3V
12
PCH_GPIO26_R_C
2
E
C
3
SR134
1KOhm
I
1%
HDA_SDO_R [22]
B B
<CORE DESIGN>
<CORE DESIGN>
<CORE DESIGN>
PEGATRON DT-MB RESTRICTED SECRET
Title :
Title :
Title :
ME DISABLE
ME DISABLE
ME DISABLE
Shrek_Tseng
Shrek_Tseng
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
IPPLP-TH
IPPLP-TH
IPPLP-TH
Engineer:
Shrek_Tseng
27 97Friday, January 17, 2014
27 97Friday, January 17, 2014
27 97Friday, January 17, 2014
Rev
Rev
Rev
A00
A00
A00
A
Vinafix.com
5
4
3
2
1
D D
NPO/+/-5% NI
12
12
GND
GND
NI
R60372
49.9 OHM
1%
C941289
10PF/50V
NPO/+/-5%
NI
+3V_WLAN
C C
B B
C31510PF/50V
CARD_DET#[44]
LED6
+
1 2
WHITE
GPIO_WIRELESS_DISABLE#[22]
GPIO_WIRELESS_ALERT#[20]
+3P3VSB
+3P3VSB
+3V_WLAN
12
12
LED#_WLAN_9MA
NI
SMB_DATA_RESUME[15,16,22,29,44,59,60,76,77]
SMB_CLK_RESUME[15,16,22,29,44,59,60,76,77]
1 2
SR117 10KOhmI1%
1 2
SR118 10KOhmI1%
NI
R60258
49.9 OHM
1%
LED#_BTLED#_BT_9MA
CL_RST#[20]
CL_DATA[20]
CL_CLK[20]
SUS_CLK[22,29,44]
PCIE_RST#[29,30,44]
BT_DISABLE#[22]
LED5
+
1 2
NI
WHITE
NI
1 2
APR26
0 Ohm
C941265 180PF/50V
GND
1 2
LED#_WLAN
CARD_DET#_R
I
APR25
0 Ohm
1 2
1 2
1 2
I
12
NPO 5%
12
I
C316
10PF/50V
NPO/+/-5%
GND
Mini-PCIE Slot (Half Card) for Wifi
GND
+3V_WLAN
I
S1C60
0.1UF/6.3V
MLCC/+/-10%
C941282 0.1UF/6.3V X5R/+/-10%NI
12
GND
GND
APR310 Ohm
NI
APR300 Ohm
NI
APR290 Ohm
NI
GPIO_WIRELESS_ALERT#_R
APR150 Ohm
NI
12
S1C58
0.1UF/6.3V
MLCC/+/-10%
12
I
S1C61
0.1UF/6.3V
MLCC/+/-10%
GND GND
12
CL_RST#_R
CL_DATA_R
CL_CLK_R
12
I
GNDGND
S1C59
0.1UF/6.3V
MLCC/+/-10%
12
I
78
J218
2
2
4
4
6
6
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
54
56
56
58
58
60
60
62
62
64
64
66
66
68
68
70
70
72
72
74
74
MINI_PCIE_67P
79
I
NP_NC1
NP_NC2
GND
76
1
3
SIDE1
5
7
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
SIDE2
77
1
3
5
7
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
WLAN_PE1_TXP6_C
61
WLAN_PE1_TXN6_C
63
65
67
69
71
73
75
GND
D+
D-
GND
GND
WLAN_PE1_TXP5_C
WLAN_PE1_TXN5_C
GND
GND
GND
GND
GND
GND
GND
12
12
12
12
TC260.1UF/6.3VMLCC/+/-10% I
TC250.1UF/6.3VMLCC/+/-10% I
TC280.1UF/6.3VMLCC/+/-10% I
TC270.1UF/6.3VMLCC/+/-10% I
WLAN_PE1_TXP5 [19]
WLAN_PE1_TXN5 [19]
WLAN_PE1_RXP5 [19]
WLAN_PE1_RXN5 [19]
CK_100M_PE1 [21]
CK_100M_PE1# [21]
WLAN_CLKREQ# [22]
WAKE# [22,29]
WLAN_PE1_TXP6 [19]
WLAN_PE1_TXN6 [19]
WLAN_PE1_RXP6 [19]
WLAN_PE1_RXN6 [19]
CK_100M_PE2 [21]
CK_100M_PE2# [21]
USBP11 [19]
USBN11 [19]
H=4mm
A A
5
4
I
H2
CT217B160D130
GND
PEGATRON DT-MB RESTRICTED SECRET
NGFF KEY A(WLAN)
NGFF KEY A(WLAN)
NGFF KEY A(WLAN)
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
Engineer:
IPPLP-TH
IPPLP-TH
IPPLP-TH
1
Shrek_Tseng
Shrek_Tseng
Shrek_Tseng
28 97Friday, January 17, 2014
28 97Friday, January 17, 2014
28 97Friday, January 17, 2014
A00
A00
A00
Rev
Rev
Rev
Vinafix.com
5
D D
+3P3V_MSATA
12
NI
R60257
49.9 OHM
1%
LED4
+
SR605
10KOhm
SMB_DATA_RESUME[15,16,22,28,44,59,60,76,77]
SMB_CLK_RESUME[15,16,22,28,44,59,60,76,77]
1 2
WHITE
DEVSLP_SSD_SLEEP_MODE
NI
1%
PCIE_RST#[28,30,44]
MSATA_CLKREQ#[22]
WAKE#[22,28]
SUS_CLK[22,28,44]
LED#_WWAN_9MA
C C
DEVSLP
]
B B
0 Ohm
NI
1 2
APR13
12
GND
WWAN_DISABLE#[22]
NI
GPS_DISABLE#[20]
GND
APR43 0 Ohm
NI
APR44 0 Ohm
NI
+3P3V_MSATA
12
C941263
0.1UF/6.3V
X5R/+/-10%
GND GND
12
NI
NI
C941264
180PF/50V
NPO 5%
1 2
1 2
1 2
+3P3V_MSATA
LED#_WWAN_9MA_OD
X5R/+/-10%
4
APR140 Ohm
12
NI
NI
C941262
0.1UF/6.3V
WAKE#_R
MFG_DATA
MFG_CLK
12
X5R/+/-10%
GND
NI
C941261
0.1UF/6.3V
J220
78
NP_NC1
2
2
4
4
6
6
8
8
10
10
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
54
56
56
58
58
60
60
62
62
64
64
66
66
68
68
70
70
72
72
74
74
79
NP_NC2
MINI_PCI_67P
NI
SIDE1
SIDE2
3
76
1
1
3
3
5
5
7
7
9
9
11
11
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
59
61
61
63
63
65
65
67
67
69
69
71
71
73
73
75
75
77
GND
CONFIG_3 [19,77]
CONFIG_0 [20,77]
SATA_RXN5_C
SATA_RXP5_C
SATA_TXN5_C
SATA_TXP5_C
SATA_RXP4_C
SATA_RXN4_C
SATA_TXN4_C
SATA_TXP4_C
CONFIG_1 [22]
CONFIG_2 [19,77]
SATA_Strap [20]
2
USBP12 [19]
USBN12 [19]
12
TC240 Ohm
NI
12
12
12
12
12
12
12
TC230 Ohm
TC210.1UF/6.3VMLCC/+/-10% NI
TC220.1UF/6.3VMLCC/+/-10% NI
TC170 Ohm
TC180 Ohm
TC190.1UF/6.3VMLCC/+/-10% NI
TC200.1UF/6.3VMLCC/+/-10% NI
SATA_RXN5 [20]
NI
SATA_RXP5 [20]
SATA_TXN5 [20]
SATA_TXP5 [20]
NI
SATA_RXP4 [20]
NI
SATA_RXN4 [20]
SATA_TXN4 [20]
SATA_TXP4 [20]
CK_100M_MSATA# [21]
CK_100M_MSATA [21]
1
D17
2N7002
32
3
D
1
1
G
S
2
NI
PEGATRON DT-MB RESTRICTED SECRET
NGFF KEY B(MSATA)
NGFF KEY B(MSATA)
NGFF KEY B(MSATA)
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
Engineer:
IPPLP-TH
IPPLP-TH
IPPLP-TH
1
Shrek_Tseng
Shrek_Tseng
Shrek_Tseng
29 97Friday, January 17, 2014
29 97Friday, January 17, 2014
29 97Friday, January 17, 2014
A00
A00
A00
Rev
Rev
Rev
32
3
D
D18
1
CONFIG_1 CONFIG_0
A A
5
4
H=4mm
NI
H1
CT217B160D130
GND
1
2N7002
G
S
2
NI
GND GND
Vinafix.com
5
12
I
C20
4.7UF/6.3V
X5R/+/-10%
GND GND
+3P3V
D D
12
I
C21
4.7UF/6.3V
X5R/+/-10%
GND GND GND GND GND
GND
C C
B B
A A
12
SCB53
0.1UF/6.3V
MLCC/+/-10%
12
I
SCB56
0.1UF/6.3V
MLCC/+/-10%
5
I
+3P3V+3P3V
12
GND
C304.7UF/6.3VX5R/+/-10% I
SCB600.1UF/6.3VMLCC/+/-10% I
SCB620.1UF/6.3VMLCC/+/-10% I
SCB630.1UF/6.3VMLCC/+/-10% I
GND
GND
12
12
12
12
L1
600Ohm/100Mhz/0.5A I
I
C22
4.7UF/6.3V
X5R/+/-10%
CR_PE1_TXP7[19]
CR_PE1_TXN7[19]
CR_PE1_RXP7[19]
CR_PE1_RXN7[19]
CK_100M_CR#[21]
CK_100M_CR[21]
PCIE_RST#[28,29,44]
12
21
GND GND
12
12
GND
SD_WP[30]
SD_CD#[30]
SCB54
0.1UF/6.3V
MLCC/+/-10%
C23
4.7UF/6.3V
X5R/+/-10%
C234
5pF/50V
NPO/+/-0.25PF
+3P3V
4
12
I
I
SC41 0.1UF/6.3V MLCC/+/-10%I
SC42 0.1UF/6.3V MLCC/+/-10%I
SC43 0.1UF/6.3V MLCC/+/-10%I
SC44 0.1UF/6.3V MLCC/+/-10%I
NI
0.1UF/6.3V
MLCC/+/-10%
12
0.1UF/6.3V
MLCC/+/-10%
L2 0Ohm 5%NOBOM
12
C284.7UF/6.3VX5R/+/-10% I
12
12
GND
+3P3V
1 2
I
SCB55
9
27
1
GND
42
23
13
11
10
41
36
31
28
1
4
6
5
7
8
2
3
15
14
16
17
18
X5R/+/-10%
5pF/50VNPO/+/-0.25PF NI
12
SCB57
1 2
C290.1UF/6.3VMLCC/+/-10% I
C310.1UF/6.3VMLCC/+/-10% I
12
12
12
12
NI
R232
10KOhm
1%
4
I
I
+3P3V
SCB58
+3P3V
0.1UF/6.3V
MLCC/+/-10%
12
R18191Ohm1% I
CR_PE1_TXP7_C
CR_PE1_TXN7_C
CR_PE1_RXP7_C
CR_PE1_RXN7_C
1 2
SR137 10KOhmI1%
NOBOM
SD_D1[30]
SD_CLK[30]
SD_D1#[30]
SD_CMD[30]
SD_D0#[30]
SD_D3[30]
SD_D0[30]
SD_D2[30]
T27
+3P3V
12
R24
100KOHM
I
1%
SD_D1_RCLK#[30]
SD_D0_RCLK[30]
U3A
PE_33VCCAIN
UHSII_33VCCAIN
SD_33VCCD
SD_SKT_33VIN
AUX_33VIN
MAIN_LDO_VIN
MAIN_LDO_12VOUT
CORE_12VCCD
UHSII_12VCCAIN_1
UHSII_12VCCAIN_2
UHSII_12VCCAIN_3
PE_12VCCAIN
PE_REXT
PE_RXP
PE_RXM
PE_TXP
PE_TXM
PE_REFCLKM
PE_REFCLKP
PE_RST#_GATE#
MAIN_LDO_EN
DEV_WAKE#
CLKREQ#
IO0_LDOSEL
OZ777FJ2LN
I
C33
4.7UF/6.3V
3
SD_WPI
SD_CD#
SD_CLK
SD_CMD
MMC_D7
MMC_D6
MMC_D5
MMC_D4
SD_D3
SD_D2
SD_D1
SD_D0
SD_D1P
SD_D1M
SD_D0M
SD_D0P
SD_REXT
LED#
GND1
CR_3V3CR_1V8
12
25
22
24
20
21
43
45
39
40
44
46
47
48
37
38
29
30
32
33
34
35
26
19
49
I
C34
4.7UF/6.3V
X5R/+/-10%
12
SD_CLK_B
R17 22 OHM 1%I
SD_D3_R
SD_D2_R
SD_D1_RCLK#_R
SD_D0_RCLK_R
GND
12
SCB65
0.1UF/6.3V
MLCC/+/-10%
GND
I
C24
4.7UF/6.3V
X5R/+/-10%
1 2
1%
I
GND
I
R19 22 OHM 1%I
R20 22 OHM 1%I
R21 22 OHM 1%I
R22 22 OHM 1%I
1 2
12
AUX_LDO_CAP
SD_IO_LDO_CAP
SD_SKT_33VOUT
SD_SKT_18VOUT
SD_RCLK_M
SD_RCLK_P
I
12
I
0.1UF/6.3V
MLCC/+/-10%
C370
12
12
SCB64
GNDGND GND GND
3
CR_3V3CR_1V8
12
C25
1UF/6.3V
X5R/+/-10%
GNDGND
1 2
1 2
1 2
1 2
R23
4.7KOHM
J56
1
WP_WP_
2
DAT1_RCLK-_
3
DAT0_RCLK+_DAT
4
_VSS5_
5
VSS2_VSS2_VSS
6
_D1+_
7
CLK_CLK
8
_D1-_
9
VDD_VDD1_VDD
10
_VDD2_
11
VSS1_VSS1_VSS
12
CD_CD_
13
_VSS4_
14
CMD_CMD
15
_D0-_
16
CD/DAT3_RSV
17
_D0+_
18
DAT2-__
19
_VSS3_
20
GND_GND_GND
CR_SOCKET_20P
I
I
2
C26
4.7UF/6.3V
X5R/+/-10%
CR8
WHITE
NI
2
I
+
SD_CLK_B
12
GND GND GND
12
I
SCB59
0.1UF/6.3V
MLCC/+/-10%
21
23
P_GND3
P_GND4
22
24
P_GND1
P_GND2
12
R178
300 Ohm
NI
mx_r0603
PEGATRON DT-MB RESTRICTED SECRET
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
GND
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
12
C27
1UF/6.3V
X5R/+/-10%
12
1
L84
I
300Mhz
112
I
+3P3V
2
GND
3
SD_WP [30]
SD_CMD [30]
SCB61
0.1UF/6.3V
MLCC/+/-10%
SD_D3 [30]
SD_D2 [30]
SD_D1_RCLK# [30]
SD_D0_RCLK [30]
SD_D1 [30]
SD_D1# [30]
SD_D0# [30]
SD_D0 [30]
GND
GND
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
IPPLP-TH
IPPLP-TH
IPPLP-TH
I
GND
1
SD_CLK [30]
12
NI
C32
5pF/50V
NPO/+/-0.25PF
GNDGND
SD_CD# [30]
12
I
12
SR136
1MOhm
5%
U3B
50
GND2
51
GND3
52
GND4
53
GND5
54
GND6
55
GND7
56
GND8
57
GND9
OZ777FJ2LN
I
CARD READER
CARD READER
CARD READER
Shrek_Tseng
Shrek_Tseng
Shrek_Tseng
30 97Friday, January 17, 2014
30 97Friday, January 17, 2014
30 97Friday, January 17, 2014
A00
A00
A00
Rev
Rev
Rev
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