PEGATRON IPM61-BE Schematic
5
IPM61-BE
Revision: 1.00
vinafix
PAGE
01
02
D D
04
05
06
07
08
09~14
15
16~18
19~27 INTEL_PCH(1~9)
28
29
30
31
32
C C
33
34
35
36
37
38
39
40
41~4203RJ45+USB 3.0 CONTROLLER
43~46
47
48~49
BLOCK DIAGRAM
CHANGE HISTORY - 1
CHANGE HISTORY - 2
CLOCKS DISTRIBUTION
SIGNAL & RESET MAP
POWER FLOW
POWER DISTRIBUTION
POWER SEQUENCE
INTEL CPU_SOCKET1155(1~6)
PLTRST_CPU# & RSMRST#
DDR3 & TERMINATION
PCH_DPWROK & SUS_ACK#
*********
VGA CONNECTOR
DVI-D CONNECTOR
PCI EXPRESS X16 SLOT
PCI SLOT
PCI EXPRESS X1 SLOT x2
INTEL 82579 LAN CONTROLLER
RJ45+USB2.0 CONNECTOR
PRINT PORT
SERIAL PORT
USB 3.0 CONTROLLER
USB 3.0 POWER
REALTEK ALC892 AUDIO CIRCUIT
PCI-E to PCI Bridge
USB HEADER
TITLE
4
PCI-E X16 SLOT
High-Speed USB
10 PORTS
Intel 82579
10/100/1000
PCI-E X1 SLOT
PCI-E X1 SLOT
PCI-E to PCI Bridge
XDP
3
100MHz
PCI-E BUS
480Mb/s
PCIE BUS
100MHz
PCIE BUS
PCIE BUS
PCIE BUS
Intel Processor
Sandy Bridge
LGA-1155 H2 Socket
FDI LINK
DMI
INTEL
Cougar Point
PCH
942 Pin
27mm X 27mm
2
TMDS
RGB
PCI-e x1
PCI-e x1
SATA BUS
SPI
Azalia
Channel A
Channel B
Dual-Channel Memory x 2 Slots
DDR3 1066/1333
DDR3 1066/1333
8GB MAX
DVI-D
VGA
SATA 3.0
USB 3.0
SATA 2.0SATA 2.0
SATA 2.0SATA 2.0
SPI FLASH
AUDIO CODEC
ALC892
32Mb
1
50 SATA CONN
51
B B
52~53
54
55
56~57
58
59
60
61
62
63
64
65
66
67
68
A A
69
70
71~72
73~75
76
77 PS2 + USB CONN
SATA 3.0 CONTROLLER
SUPER I/O -WINBOND W83677
SMBUS CONTROL
TPM
FAN circuit
FRONT PANEL CIRCUIT
SPI ROM
ATX POWER_24P CONNECTOR
+3VA & +3VSB & +5VSB
+1P5V_DUAL
+VTT_DDR & +1P5V_DUAL_EN
+1P8V FOR SATA3.0 CONTROLLER
VSA_OV_Function
+0P925V_SA & +1P05V_PCH
5V DUAL POWER
+1P8V_SFR
+1V_USB3 & VRM_EN
+3P3V_LAN & +3P3V_ME
+1P05V_CPUIO
VCORE CONTROLLER + DRIVER
+V_AXG DRIVER
5
LPC BUS
33MHz
PCI SLOT
LPT
SIO
WINBOND W83677
78
79
80
81
82
83
4
EMI CAP
RTC/LED/SPKR/SCREW
BIOS and LPC header
Heceta Fan Control
CPU XDP DEBUG CONNECTOR
PCH XDP DEBUG CONNECTOR
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3
2
FAN
COM
PEGATRON DT-MB RESTRICTED SECRET
BLOCK DIAGRAM
BLOCK DIAGRAM
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Engineer:
IPMSB-BE/CR
IPMSB-BE/CR
IPMSB-BE/CR
BLOCK DIAGRAM
1
Livy_Zhu
Livy_Zhu
Livy_Zhu
183Friday, September 24, 2010
183Friday, September 24, 2010
183Friday, September 24, 2010
Rev
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5
Schematics Change History
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Version
D D
C C
Date
4
3
2
1
Comments
B B
A A
CAD Note:
Default component footprint is SMD 0402, Y5V, 5% type. Difference footprint show on schematics.
Property: BOM
I = Installed Part.
NI = Not Installed Part.
5
PROTO = PROTO Phase Only.
VP = Virtual Part.
4
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3
2
<Variant Name>
<Variant Name>
<Variant Name>
PEGATRON DT-MB RESTRICTED SECRET
CHANGE HISTORY-1
CHANGE HISTORY-1
CHANGE HISTORY-1
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet of
IPMSB-BE/CR
IPMSB-BE/CR
IPMSB-BE/CR
Engineer:
Livy_Zhu
Livy_Zhu
Livy_Zhu
283Friday, September 24, 2010
283Friday, September 24, 2010
283Friday, September 24, 2010
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Schematics Change History
vinafix
Version
D D
C C
Date
Comments
B B
A A
CAD Note:
Default component footprint is SMD 0402, Y5V, 5% type. Difference footprint show on schematics.
Property: BOM
I = Installed Part.
NI = Not Installed Part.
5
PROTO = PROTO Phase Only.
VP = Virtual Part.
4
http://vinafix.vn
3
2
<Variant Name>
<Variant Name>
<Variant Name>
PEGATRON DT-MB RESTRICTED SECRET
CHANGE HISTORY-2
CHANGE HISTORY-2
CHANGE HISTORY-2
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet of
IPMSB-BE/CR
IPMSB-BE/CR
IPMSB-BE/CR
Engineer:
Livy_Zhu
Livy_Zhu
Livy_Zhu
383Friday, September 24, 2010
383Friday, September 24, 2010
383Friday, September 24, 2010
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M_CHA_CLK[0..3]/#
D D
XMM3 / XMM4
C C
CK_100M_DMI2/#_CK505
CK_133M_BCLK_CK505/#
CK505
CK_100M_DMI_CK505/#
M_CHB_CLK[0..3]/#
XMM1 / XMM2
Intel Processor
Sandy Bridge
LGA-1155 Pin Socket
RSVD_001/002
BCLK/#_0
Intel
Platform Controller Hub
Cougar Point
942 Pin
CLKIN_GND1_P/N
CLKIN_GND0_P/N
CLKIN_DMI_P/N
CPU XDP
CK_100M_DMI/#
CK_100M_CPUXDP/#
100 MHz
CK_100M_PCHXDP/#
100 MHz
CK_100M_PE16/#
100 MHz
CK_100M_PE1/#
100 MHz
CK_100M_LAN/#
100 MHz
CK_100M_CPU_XDP/#_CK505
PCH XDP
PCIEx1 Slot
Intel 82579
PCIEx16 Slot
25 MHz
PCH Buffer Through Mode for Pre-Silicon
CK_100M_SATA_CK505/#
SLG8SP424VTR
ICS9LRS4180A/B
B B
CK_96M_DOT_CK505/#
CK_14M_REF_CK505
NOTE:
Reserved PD resistors for FCIM
CLKIN_SATA_P/N
CLKIN_DOT_96_P/N
REFCLK14IN
32 Pin
CK_33M_TPM
33 MHz
CK_48M_SIO
48 MHz
CK_33M_SIO
33 MHz
CK_33M_SL1
33 MHz
CK_33M_PCIFB
TPM Header
W83677
PCI Slot
CK_48M_SIO_CK505
48 MHz
CKKIN_PCILOOPBACK
HDA_BCLK
AZ_BITCLK
24 MHz
14.318MHz
A A
XTAL25_IN RTCX
SPI_CLK
SPI_CLK
33 MHz
32.768KHz25MHz
5
4
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3
AUDIO CODEC
ALC892
SPI ROM
2
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PEGATRON DT-MB RESTRICTED SECRET
CLCOK DISTRIBUTION
CLCOK DISTRIBUTION
CLCOK DISTRIBUTION
Title :
Title :
Title :
Engineer:
Engineer:
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Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet of
IPMSB-BE/CR
IPMSB-BE/CR
IPMSB-BE/CR
Engineer:
Livy_Zhu
Livy_Zhu
Livy_Zhu
483Friday, September 24, 2010
483Friday, September 24, 2010
483Friday, September 24, 2010
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PCI_Express x 16
PCI_Express x 4
PCI_Express x 1
<28>PCIE_RST#
PWRGD
<28>PCIE_RST#
PWRGD
<28>PCIE_RST#
4
<29>PCH_PCIRST#
<27>PLTRST#
3
RST#
PCI SLOT #1
PE_RSTN
LAN 82579
2
1
Intel AMT 7.0 and non-DSW supported
RESET_SWITCH
PWRGD
D D
USB3.0
PERSTB
<27.1>PLTRST_CPU#
PCH PROCESSOR
POWER_SWITCH
<4>PWRBTN#
C C
2X12 ATX PSU
<15>PSON#
PSON#
PWROK
B B
<21>ATX_PWRGD
W83677
PWSIN#
PS_ON#
ATXPG_IN
PCIRST3#
PCIRST2#
PCIRST1#
LRESET#
KBRST# RCIN#
RSMRST#
PWSOUT# PWRBTN#
S3# SLP_S3#
S4#
<27>PLTRST#
RST_KB#
<9>RSMRST#
<4>SB_PWRBTN#
<13>SLP_S3#
<12>SLP_S4#
<11>SLP_A#
<10>SLP_LAN#
PWROK
<7>SLP_SUS#
<5>SUS_WARN#
<6>SUS_ACK#
<3>PCH_DPWROK
PCIRST#
PLTRST#
RSMRST#
SLP_S4#
SLP_A#
SLP_LAN#
SLP_SUS#
SUS_WARN#
SUS_ACK#
DPWROK
PWROK
ME & LAN POWER
<22>PWROK
HDA_RST#
DRAMPWROK
RTCRST#
PROCPWRGD
SYS_PWROK
APWROK
+1P05V_ME
ONBOARD POWER
+3P3V_LAN
<14>APWROK
+3P3V_ME
STANDBY POWER
<8>
+5VSB
CHIP
A A
+3P3VSB
MB Logic
<2>+5VA
MB Logic
CK505
CKPWRGD/PD#
<22>CK505_PWRGD
AZ_RST#
<1>RTCRST#
RESET#
CPU SVID buffers are Hi-Z once +1P05V_CPUIO is
stable and UNCOREPWRGOOD = 0
<26>VRM_PWRGD
Vcore Controller
VR_RDY
MB Logic
SOCKET or SLOT
2X12 ATX PSU
5
<2>+5VA
4
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3
AUDIO
ALC8889
SYS_RESET#
<23>DRAM_PWROK
BATTERY
<24>CPUPWRGD
VDIO/VCLK
VCORE
EN
RT8859AGQW
<20~24>SVIDs
<25>VCORE
<16>+1P05V_CPUIO
<19>+1P05V_CPUIO
2
DBR#SYS_RESET#
RESET#
SM_DRAMPWROK
UNCOREPWRGOOD
VIDSOUT/VIDSCLK
VCORE
<16>
+1P05V_CPUIO
<17>1P05V_CPUIO_PWRGD
PWRGD
NCP5380MNTXG
<18>
+0P925V_SA
EN
LM358
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PEGATRON DT-MB RESTRICTED SECRET
SIGNAL&RESET MAP
SIGNAL&RESET MAP
SIGNAL&RESET MAP
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet of
IPMSB-BE/CR
IPMSB-BE/CR
IPMSB-BE/CR
Engineer:
Livy_Zhu
Livy_Zhu
Livy_Zhu
583Friday, September 24, 2010
583Friday, September 24, 2010
583Friday, September 24, 2010
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+12V_CPU
+
L/S * 6
H/S * 1
+
H/S * 3
D D
L/S * 2
H/S * 2
+
L/S * 2
HIGH SIDE: NTMFS4839NHT1G
LOW SIDE: IPS06N03LAG
HIGH SIDE: NTMFS4839NHT1G
LOW SIDE: IPS06N03LAG
HIGH SIDE: FDU8780_F071
LOW SIDE: IPS06N03LAG
Imax = 17A
eff = TBD%
Imax = ?A
eff = TBD%
TDP = 95W
Imax = 35A
eff = TBD%
LM358 Linear Regulator
0.925V / 0.85V
APM9932CKC
+5V
C C
+5VA
AOD472 (S0,S1)
FDN340P_NL (S3)
RT8204AGQW
HIGH SIDE: AOD452
LOW SIDE: IPDH6N03LAG
Iocp = TBD A
Imax = TBD A
eff = TBD %
RT9045GSP
+VCORE
Idc(TDC) = 85A
+V_AXG
Idc(TDC) = 25A
+1P05V_CPUIO
Imax = 17A
+0P925V_SA
Imax = 8.8A
+5V_DUAL_USB_B/F
Idc = 7A
(S0, S1, S3)
+5V_DUAL
Idc = TBD A
(S0, S1, S3)
+1P5V_DUAL
Imax = 28.5A
(S0, S1, S3)
VTT_DDR
Idc = 1A
(S0, S1)
+1P05V_PCH
LM358
B B
+3P3V
LM358
LIN REG, 1085
RT8015APQW
Imax = 6.2A
+1P8V_SFR
Imax = 1.6A
+3P3VSB
Idc = TBD A
+1P05V_ME
Imax = 1.8A
+12V
+3P3V_ME
FDN340P_NL
A A
Switch ON/OFF
5
LinearSwitching
4
Note: Ixx/Ioo
means
Itdc/Imax
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AOD452
FDN340P_NL
2
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Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet of
IPMSB-BE/CR
IPMSB-BE/CR
IPMSB-BE/CR
Idc = 0.016A
+3P3V_LAN
Idc = 0.218A
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
1
POWER FLOW
POWER FLOW
POWER FLOW
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Livy_Zhu
Livy_Zhu
683Friday, September 24, 2010
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4
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D D
+VCORE
+1P05V_CPUIO
+0P925V_SA
+V_AXG
-> 95A(TDC) - 95W
-> 17A(Imax) - W
-> 8.8A(Imax) - W
-> 25A(TDC) - W
+12V
+3P3V
+3P3VSB
CPU Sandy Bridge
PCI Express x 1
-> 5A - 60W
-> 3.0A - 9.9W
WAKE -> 0.375A - 1.24W
No WAKE-> 20mA - 66mW
+3P3V
+1P05V_USB
+5V_DUAL_B/F
FL1009 USB3.0
-> mA - W
-> mA - W
USB 14 PORTS
(S0, S1) -> 7A - 35W
+3P3V
CLOCK GEN
-> 125mA - W
+12V
+3P3V
+3P3VSB
PCH
+1P05V_PCH
C C
+1P05V_CPUIO
+1P8V_SFR
+3P3V
+3P3VSB
-> 5.831A - W
-> 0.043A - W
-> 0.16A - W
-> 0.267A - W
-> 0.107A - W
+12V
-12V
+5V
+3P3V
+3P3VSB
+1P05V_ME
-> 1.01A - W
PCI Express x 16
-> 5.5A - 66W
-> 3.0A - 9.9W
WAKE -> 0.375A - 1.24W
No WAKE-> 20mA - 66mW
PCI SLOTS
-> 0.5A - 6W
-> 0.1A - 1.2W
-> 5.0A - 25W
-> 7.6A - 25.08W
WAKE -> 0.375A - 1.24W
No WAKE-> 20mA - 66mW
+5V
+12V
+5V_DUAL
+3P3V_ME
DVI
-> mA - mW
-> mA - mW
FANS
-> 1.2A - 14.4W
PS2 KB/MS
(S0, S1) -> 0.345A - 1.73W
(S3) -> 2mA - 10mW
SPI
-> 30mA - 99mW
+3P3V_ME
-> 0.02A - W
+3P3VA
B B
+BATT
-> 0.002A - W
RTC(G3) -> 6uA - 0.0198mW
+3P3V_LAN
+3P3V
-> mA - 720mW
-> 35mA - mW
INTEL 82579
83677
DDR2 DIMM (4) & Termination
+1P5V_DAUL
+3P3V
VDD (S0, S1,S3) ->7.5 A - 11.25W
+VTT_DDR(0.75V)
A A
5
SM VTT (S0, S1) -> 1A - 0.75W
4
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-> mA - mW
ALC892
<Variant Name>
<Variant Name>
<Variant Name>
PEGATRON DT-MB RESTRICTED SECRET
POWER DISTRIBUTION
POWER DISTRIBUTION
POWER DISTRIBUTION
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet
Date: Sheet
3
2
Date: Sheet of
IPMSB-BE/CR
IPMSB-BE/CR
IPMSB-BE/CR
Engineer:
Livy_Zhu
Livy_Zhu
Livy_Zhu
783Friday, September 24, 2010
783Friday, September 24, 2010
1
783Friday, September 24, 2010
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S5 to S0 Power Sequence
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SLP_SUS#
DSW exit
+5VSB / +3P3VSB
D D
RSMRST#
SUSWARN#
SUSACK#
SLP_LAN#
SLP_A#
+1P05V_ME
SLP_S5#
30uS
SLP_S4#
SLP_S3#
30uS
APWROK
C C
PSU: <=20mS
+12V / +5V
+3P3V
+1P5V_DUAL
=500mS
+1P05V_CPUIO
+1P8V_SFR
=50mS
VCCSA_VID
UNCOREPWRGOOD must be stable (low) at this time
+0P925V_SA
VCORE EN
B B
VIDSCLK / VIDSOUT
VIDALERT#
CPU SVID buffers are Hi-Z once VCCIO is
stable and Uncorepowergood = 0
CPU SVID buffers are Hi-Z once VCCIO is
stable and Uncorepowergood = 0
UNCOREPWRGOOD assertion
VCCSA_VID[0] FINAL
Recommended that +0P925V_SA ramp after +1P05V_CPUIO has ramped to ensure VCCSA_VID[0] is stable
<5mS
Typ 60uS
MISC ACK0/1...
Set VID
slow packet status packet
ACK0/1...
Get Reg
ACK0/1...
<600uS
<1uS
Pay
load
+0P925V_SA FINAL
>400uS
PSU: 100ms~500ms
ATX_PWRGD
BCLK / PCIE CLOCKS
DRAM_PWROK
>1mS
CPUPWRGD
+VCORE
VRM_PWRGD
A A
PLTRST#
5
4
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1mS
Min 10 PCIe BCLKs
<5uS
<2mS
5mS
<5mS
1~100mS
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POWER SEQUENCE
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Title :
Engineer:
Engineer:
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Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet
Date: Sheet
3
2
Date: Sheet of
IPMSB-BE/CR
IPMSB-BE/CR
IPMSB-BE/CR
Engineer:
Livy_Zhu
Livy_Zhu
Livy_Zhu
883Friday, September 24, 2010
883Friday, September 24, 2010
1
883Friday, September 24, 2010
Rev
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M_CHA_DQ[0..63]16
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D D
C C
B B
A A
5
M_CHA_DQS016
M_CHA_DQS0#16
M_CHA_DQS116
M_CHA_DQS1#16
M_CHA_DQS216
M_CHA_DQS2#16
M_CHA_DQS316
M_CHA_DQS3#16
M_CHA_DQS416
M_CHA_DQS4#16
M_CHA_DQS516
M_CHA_DQS5#16
M_CHA_DQS616
M_CHA_DQS6#16
M_CHA_DQS716
M_CHA_DQS7#16
4
I
I
HU1A
HU1A
M_CHA_DQS0
M_CHA_DQS0#
M_CHA_DQ0
M_CHA_DQ1
M_CHA_DQ2
M_CHA_DQ3
M_CHA_DQ4
M_CHA_DQ5
M_CHA_DQ6
M_CHA_DQ7
M_CHA_DQS1
M_CHA_DQS1#
M_CHA_DQ8
M_CHA_DQ9
M_CHA_DQ10
M_CHA_DQ11
M_CHA_DQ12
M_CHA_DQ13
M_CHA_DQ14
M_CHA_DQ15
M_CHA_DQS2
M_CHA_DQS2#
M_CHA_DQ16
M_CHA_DQ17
M_CHA_DQ18
M_CHA_DQ19
M_CHA_DQ20
M_CHA_DQ21
M_CHA_DQ22
M_CHA_DQ23
M_CHA_DQS3
M_CHA_DQS3#
M_CHA_DQ24
M_CHA_DQ25
M_CHA_DQ26
M_CHA_DQ27
M_CHA_DQ28
M_CHA_DQ29
M_CHA_DQ30
M_CHA_DQ31
M_CHA_DQS4
M_CHA_DQS4#
M_CHA_DQ32
M_CHA_DQ33
M_CHA_DQ34
M_CHA_DQ35
M_CHA_DQ36
M_CHA_DQ37
M_CHA_DQ38
M_CHA_DQ39
M_CHA_DQS5
M_CHA_DQS5#
M_CHA_DQ40
M_CHA_DQ41
M_CHA_DQ42
M_CHA_DQ43
M_CHA_DQ44
M_CHA_DQ45
M_CHA_DQ46
M_CHA_DQ47
M_CHA_DQS6
M_CHA_DQS6#
M_CHA_DQ48
M_CHA_DQ49
M_CHA_DQ50
M_CHA_DQ51
M_CHA_DQ52
M_CHA_DQ53
M_CHA_DQ54
M_CHA_DQ55
M_CHA_DQS7
M_CHA_DQS7#
M_CHA_DQ56
M_CHA_DQ57
M_CHA_DQ58
M_CHA_DQ59
M_CHA_DQ60
M_CHA_DQ61
M_CHA_DQ62
M_CHA_DQ63
4
http://vinafix.vn
AK3
AK2
AP3
AP2
AN1
AN4
AR3
AR4
AN2
AN3
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AR1
AW4
AV4
AV2
AW3
AV5
AW5
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AU3
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AY5
AV8
AW8
AY7
AU7
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AU9
AV7
AW7
AW9
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AV37
AV36
AU35
AW37
AU39
AU36
AW35
AY36
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AU37
AP38
AP39
AR40
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AR38
AN39
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AK39
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AJ37
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AL38
AJ39
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AE38
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AG38
AE39
AE40
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AJ4
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AJ2
AJ1
AL2
AL1
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SA_DQS#_0
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SA_DQ_7
SA_DQS_1
SA_DQS#_1
SA_DQ_8
SA_DQ_9
SA_DQ_10
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SA_DQ_56
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SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
SOCKET_1155P
SOCKET_1155P
3
SM_DRAMRST#
SA_ECC_CB_0
SA_ECC_CB_1
SA_ECC_CB_2
SA_ECC_CB_3
SA_ECC_CB_4
SA_ECC_CB_5
SA_ECC_CB_6
SA_ECC_CB_7
DDR3_A
DDR3_A
3
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
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SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
SA_MA_15
SA_WE#
SA_CAS#
SA_RAS#
SA_BS_0
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SA_CS#_0
SA_CS#_1
SA_CS#_2
SA_CS#_3
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SA_CK_1
SA_CK#_1
SA_CK_2
SA_CK#_2
SA_CK_3
SA_CK#_3
SA_DQS_8
SA_DQS#_8
AV27
AY24
AW24
AW23
AV23
AT24
AT23
AU22
AV22
AT22
AV28
AU21
AT21
AW32
AU20
AT20
AW29
AV30
AU28
AY29
AW28
AV20
AU29
AV32
AW30
AU33
AV19
AT19
AU18
AV18
AV31
AU32
AU30
AW33
AY25
AW25
AU24
AU25
AW27
AY27
AV26
AW26
AW18
AV13
AV12
AU12
AU14
AW13
AY13
AU13
AU11
AY12
AW12
M_CHA_MAA0
M_CHA_MAA1
M_CHA_MAA2
M_CHA_MAA3
M_CHA_MAA4
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M_CHA_MAA6
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M_CHA_MAA8
M_CHA_MAA9
M_CHA_MAA10
M_CHA_MAA11
M_CHA_MAA12
M_CHA_MAA13
M_CHA_MAA14
M_CHA_MAA15
TP_HU1_AW30
TP_HU1_AU33
TP_HU1_AU18
TP_HU1_AV18
TP_HU1_AU30
TP_HU1_AW33
R_DDR3_DRAMRST#
MA_ECC_CB0
MA_ECC_CB1
MA_ECC_CB2
MA_ECC_CB3
MA_ECC_CB4
MA_ECC_CB5
MA_ECC_CB6
MA_ECC_CB7
TP_HU1_AW27
TP_HU1_AY27
TP_HU1_AV26
TP_HU1_AW26
I
I
SR283
SR283
1 2
0
0
2
M_CHA_MAA[0..15] 16
M_CHA_WE# 16
M_CHA_CAS# 16
M_CHA_RAS# 16
M_CHA_BA0 16
M_CHA_BA1 16
M_CHA_BA2 16
M_CHA_CS#0 16
M_CHA_CS#1 16
M_CHA_CKE0 16
M_CHA_CKE1 16
M_CHA_ODT0 16
M_CHA_ODT1 16
M_CHA_CLK0 16
M_CHA_CLK0# 16
M_CHA_CLK1 16
M_CHA_CLK1# 16
DDR3_DRAMRST# 16,17
M_CHA_DQS8 16
M_CHA_DQS8# 16
MA_ECC_CB[0..7] 16
NOTE:
For ECC DIMM
2
1
PEGATRON DT-MB RESTRICTED SECRET
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Engineer:
IPMSB-BE/CR
IPMSB-BE/CR
IPMSB-BE/CR
1
DDR3_A 1-6
DDR3_A 1-6
DDR3_A 1-6
Livy_Zhu
Livy_Zhu
Livy_Zhu
983Friday, September 24, 2010
983Friday, September 24, 2010
983Friday, September 24, 2010
Rev
Rev
Rev
1.00
1.00
1.00
5
vinafix
D D
C C
B B
A A
5
M_CHB_DQ[0..63]17
M_CHB_DQS017
M_CHB_DQS0#17
M_CHB_DQS117
M_CHB_DQS1#17
M_CHB_DQS217
M_CHB_DQS2#17
M_CHB_DQS317
M_CHB_DQS3#17
M_CHB_DQS417
M_CHB_DQS4#17
M_CHB_DQS517
M_CHB_DQS5#17
M_CHB_DQS617
M_CHB_DQS6#17
M_CHB_DQS717
M_CHB_DQS7#17
4
I
I
HU1B
HU1B
M_CHB_DQS0
M_CHB_DQS0#
M_CHB_DQ0
M_CHB_DQ1
M_CHB_DQ2
M_CHB_DQ3
M_CHB_DQ4
M_CHB_DQ5
M_CHB_DQ6
M_CHB_DQ7
M_CHB_DQS1
M_CHB_DQS1#
M_CHB_DQ8
M_CHB_DQ9
M_CHB_DQ10
M_CHB_DQ11
M_CHB_DQ12
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M_CHB_DQ14
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M_CHB_DQS2#
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M_CHB_DQS3#
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M_CHB_DQS4#
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M_CHB_DQS5#
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M_CHB_DQS6
M_CHB_DQS6#
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M_CHB_DQ53
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M_CHB_DQS7
M_CHB_DQS7#
M_CHB_DQ56
M_CHB_DQ57
M_CHB_DQ58
M_CHB_DQ59
M_CHB_DQ60
M_CHB_DQ61
M_CHB_DQ62
M_CHB_DQ63
4
http://vinafix.vn
AH7
AH6
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AR29
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SB_DQ_60
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DDR3_B
DDR3_B
SOCKET_1155P
SOCKET_1155P
3
SB_MA_0
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SB_MA_3
SB_MA_4
SB_MA_5
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SB_MA_8
SB_MA_9
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SB_MA_11
SB_MA_12
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SB_CKE_0
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3
AK24
AM20
AM19
AK18
AP19
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AL18
AN18
AY17
AN23
AU17
AT18
AR26
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AV16
AR25
AK25
AP24
AP23
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AW17
AN25
AN26
AL25
AT26
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AY15
AW15
AV15
AL26
AP26
AM26
AK26
AL21
AL22
AL20
AK20
AL23
AM22
AP21
AN21
AN16
AN15
AL16
AM16
AP16
AR16
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AM15
AR15
AP15
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M_CHB_MAA7
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M_CHB_MAA13
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TP_HU1_AL25
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TP_HU1_AM26
TP_HU1_AK26
TP_HU1_AL23
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TP_HU1_AP21
TP_HU1_AN21
2
M_CHB_MAA[0..15] 17
M_CHB_WE# 17
M_CHB_CAS# 17
M_CHB_RAS# 17
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M_CHB_BA1 17
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M_CHB_CS#1 17
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M_CHB_ODT0 17
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M_CHB_CLK0 17
M_CHB_CLK0# 17
M_CHB_CLK1 17
M_CHB_CLK1# 17
M_CHB_DQS8 17
M_CHB_DQS8# 17
MB_ECC_CB[0..7] 17
NOTE:
For ECC DIMM
2
1
PEGATRON DT-MB RESTRICTED SECRET
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Engineer:
IPMSB-BE/CR
IPMSB-BE/CR
IPMSB-BE/CR
1
DDR3_B 2-6
DDR3_B 2-6
DDR3_B 2-6
Livy_Zhu
Livy_Zhu
Livy_Zhu
10 83Friday, September 24, 2010
10 83Friday, September 24, 2010
10 83Friday, September 24, 2010
Rev
Rev
Rev
1.00
1.00
1.00
5
4
3
2
1
vinafix
EXP_RXP032
EXP_RXN032
D D
C C
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EXP_RXP132
EXP_RXN132
EXP_RXP232
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EXP_RXP332
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EXP_RXP432
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EXP_RXP732
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EXP_RXP832
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EXP_RXP932
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EXP_RXP1032
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EXP_RXP1232
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D11
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AA5
C9
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C6
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A6
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E1
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G1
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I
HU1C
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PEG_RX#_12
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DMI_RX_0
DMI_RX#_0
DMI_RX_1
DMI_RX#_1
DMI_RX_2
DMI_RX#_2
DMI_RX_3
DMI_RX#_3
PEG
PEG
PEG_TX_0
PEG_TX#_0
PEG_TX_1
PEG_TX#_1
PEG_TX_2
PEG_TX#_2
PEG_TX_3
PEG_TX#_3
PEG_TX_4
PEG_TX#_4
PEG_TX_5
PEG_TX#_5
PEG_TX_6
PEG_TX#_6
PEG_TX_7
PEG_TX#_7
PEG_TX_8
PEG_TX#_8
PEG_TX_9
PEG_TX#_9
PEG_TX_10
PEG_TX#_10
PEG_TX_11
PEG_TX#_11
PEG_TX_12
PEG_TX#_12
PEG_TX_13
PEG_TX#_13
PEG_TX_14
PEG_TX#_14
PEG_TX_15
PEG_TX#_15
DMI_TX_0
DMI_TX#_0
DMI_TX_1
DMI_TX#_1
DMI_TX_2
DMI_TX#_2
DMI_TX_3
DMI_TX#_3
C13
C14
E14
E13
G14
G13
F12
F11
J14
J13
D8
D7
D3
C3
E6
E5
F8
F7
G10
G9
G5
G6
K7
K8
J5
J6
M8
M7
L6
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N5
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V7
V6
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AA8
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EXP_TXP10 32
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EXP_TXP12 32
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EXP_TXP13 32
EXP_TXN13 32
EXP_TXP14 32
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EXP_TXP15 32
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I
I
HU1D
HU1D
+1P05V_CPUIO
12
I
I
HR2
HR2
24.9
24.9
1%
1%
mx_r0402
mx_r0402
FDI_COMP
AE2
FDI_COMPIO
AE1
FDI_ICOMPO
FDI
FDI
FDI_FSYNC_024
FDI_LSYNC_024
FDI_FSYNC_124
FDI_LSYNC_124
FDI_INT24
AC5
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AG3
SOCKET_1155P
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FDI_TX_1
FDI_TX#_1
FDI_TX_2
FDI_TX#_2
FDI_TX_3
FDI_TX#_3
FDI_TX_4
FDI_TX#_4
FDI_TX_5
FDI_TX#_5
FDI_TX_6
FDI_TX#_6
FDI_TX_7
FDI_TX#_7
AC8
AC7
AC2
AC3
AD2
AD1
AD4
AD3
AD7
AD6
AE7
AE8
AF3
AF2
AG2
AG1
FDI_TXP0 24
FDI_TXN0 24
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FDI_TXP5 24
FDI_TXN5 24
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FDI_TXP7 24
FDI_TXN7 24
PEG_COMP
+1P05V_CPUIO
12
I
I
HR3
HR3
24.9
24.9
1%
1%
mx_r0402
mx_r0402
DMI
DMI
PE_TX_0
PE_TX#_0
PE_TX_1
PE_TX#_1
PE_TX_2
PE_TX#_2
PE_TX_3
PE_TX#_3
B5
C4
B4
P8
P7
T7
T8
R6
R5
U5
U6
PEG_ICOMPO
PEG_RCOMPO
PEG_COMPI
P3
PE_RX_0
P4
PE_RX#_0
R2
PE_RX_1
R1
PE_RX#_1
T4
PE_RX_2
T3
PE_RX#_2
U2
PE_RX_3
U1
PE_RX#_3
A A
SOCKET_1155P
SOCKET_1155P
GEN
GEN
PEGATRON DT-MB RESTRICTED SECRET
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet
Date: Sheet of
5
4
http://vinafix.vn
3
2
Date: Sheet of
Engineer:
IPMSB-BE/CR
IPMSB-BE/CR
IPMSB-BE/CR
1
PCIE/DMI/FDI 3-6
PCIE/DMI/FDI 3-6
PCIE/DMI/FDI 3-6
Livy_Zhu
Livy_Zhu
Livy_Zhu
11 83Friday, September 24, 2010
11 83Friday, September 24, 2010
11 83Friday, September 24, 2010
Rev
Rev
Rev
1.00
1.00
1.00
of
vinafix
5
4
I
I
HU1E
HU1E
3
2
1
NOTE:
H_CFG0
H_CFG1
H_CFG2
H_CFG3
H_CFG4
H_CFG5
H_CFG6
H_CFG7
H_CFG8
H_CFG9
H_CFG10
H_CFG11
H_CFG12
H_CFG13
H_CFG14
H_CFG15
W2
BCLK_0
W1
BCLK#_0
C40
RSVD_001
D40
RSVD_002
C37
VIDSCLK
B37
VIDSOUT
A37
VIDALERT#
F36
RESET#
J40
UNCOREPWRGOOD
AJ19
SM_DRAMPWROK
J35
PECI
E37
CATERR#
H34
PROCHOT#
G35
THERMTRIP#
E38
PM_SYNC
AJ22
SM_VREF
AJ33
SKTOCC#
K32
PROC_SEL
H36
CFG_0
J36
CFG_1
J37
CFG_2
K36
CFG_3
L36
CFG_4
N35
CFG_5
L37
CFG_6
M36
CFG_7
J38
CFG_8
L35
CFG_9
M38
CFG_10
N36
CFG_11
N38
CFG_12
N39
CFG_13
N37
CFG_14
N40
CFG_15
G37
CFG_16
G36
CFG_17
AT14
RSVD_016
AY3
RSVD_023
H7
RSVD_028
H8
RSVD_029
SOCKET_1155P
SOCKET_1155P
3
MISC
MISC
VCCSA_VID
VCCSA_SENSE
VCC_SENSE
VSS_SENSE
VCCIO_SENSE
VSSIO_SENSE
VCCAXG_SENSE
VSSAXG_SENSE
VCCP_SELECT
CK_100M_DMI24
CK_100M_DMI#24
D D
HR55 0Imx_r0402HR55 0Imx_r0402
VIDSCLK73
VIDSOUT73
VIDALERT#73
PLTRST_CPU#15
CPUPWRGD22,69,82
DRAM_PWROK22
C C
PECI_HECETA81
PECI_SIO52
PECI_PCH21
CATERR#21,79
PROCHOT#73
H_THMTRIP#21
PM_SYNC21
SKTOCC#52
NVR_CLE24
B B
+1P5V_DUAL
12
I
I
D3R39
D3R39
100
100
1%
1%
mx_r0402
mx_r0402
A A
12
I
I
D3R40
D3R40
100
100
1%
1%
mx_r0402
mx_r0402
12
GNDGND
1 2
HR56 0Imx_r0402HR56 0Imx_r0402
1 2
HR57 0Imx_r0402HR57 0Imx_r0402
1 2
NI
NI
12
HC7
HC7
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0402
mx_c0402
HR51 0NImx_r0402HR51 0NImx_r0402
1 2
HR20 0Imx_r0402HR20 0Imx_r0402
1 2
HR21 0NImx_r0402HR21 0NImx_r0402
1 2
HR23 4.7KImx_r0402HR23 4.7KImx_r0402
12
Place HR23 close to NVRAM connector
and minimize this stub to <100 mils
with PCH and NVRAM
connector
CFG[0~15] is IPU
NOTE:
I
I
D3CB17
D3CB17
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0402
mx_c0402
CFG6 CFG5
11
10
01
00
5
Description
X16(Default)
2X8
Reserved
X8, X4/X4
CK_100M_CPU_XDP82
CK_100M_CPU_XDP#82
+1P05V_CPUIO
12
GND
12
I
I
12
NI
NI
NI
NI
HR5
HR5
HR4
HR4
90.9
90.9
51
51
1%
1%
mx_r0402
mx_r0402
mx_r0402
mx_r0402
VIDALERT#_R H_VIDALERT#
R1458 120 Ohm 1%
R1458 120 Ohm 1%
1 2
I
I
HR58
HR58
1K
1K
mx_r0402
mx_r0402
12
12
GND
NOTE:
Place near CPU
12
I
I
HR6
HR6
110
110
1%
1%
mx_r0402
mx_r0402
NI
NI
12
HC6
HC6
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0402
mx_c0402
GNDGND
I
I
HR14
HR14
2.2K
2.2K
mx_r0402
mx_r0402
NI
NI
HCB2
HCB2
0.1UF/16V
0.1UF/16V
Y5V +80-20%
Y5V +80-20%
mx_c0402
mx_c0402
GND
GND
8/17
NI
NI
+1P05V_CPUIO+1P8V_NANDIO
12
HC11
HC11
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0402
mx_c0402
GND
1 2
R_DRAM_PWROK
NI
NI
12
HC5
HC5
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0402
mx_c0402
GND
12
NI
NI
HR17
HR17
1K
1K
mx_r0402
mx_r0402
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
http://vinafix.vn
12
I
I
HR7
HR7
75
75
1%
1%
mx_r0402
mx_r0402
HR11 44.2 1%Imx_r0402HR11 44.2 1%Imx_r0402
12
NI
NI
HR16
HR16
1K
1K
mx_r0402
mx_r0402
CPU_CFG082
HR24 1KNImx_r0402HR24 1KNImx_r0402
HR25 1KNImx_r0402HR25 1KNImx_r0402
HR27 1KNImx_r0402HR27 1KNImx_r0402
HR26 1KNImx_r0402HR26 1KNImx_r0402
HR28 1KNImx_r0402HR28 1KNImx_r0402
HR29 1KNImx_r0402HR29 1KNImx_r0402
HR30 1KNImx_r0402HR30 1KNImx_r0402
HR32 1KNImx_r0402HR32 1KNImx_r0402
HR31 1KNImx_r0402HR31 1KNImx_r0402
HR33 1KNImx_r0402HR33 1KNImx_r0402
HR34 1KNImx_r0402HR34 1KNImx_r0402
HR35 1KNImx_r0402HR35 1KNImx_r0402
HR37 1KNImx_r0402HR37 1KNImx_r0402
HR36 1KNImx_r0402HR36 1KNImx_r0402
HR39 1KNImx_r0402HR39 1KNImx_r0402
HR38 1KNImx_r0402HR38 1KNImx_r0402
HR41 1KNImx_r0402HR41 1KNImx_r0402
HR40 1KNImx_r0402HR40 1KNImx_r0402
4
H_VIDSCLK
H_VIDSOUT
12
NI
NI
HR59
HR59
100
100
mx_r0402
mx_r0402
For VR Debug
GND
I
I
HR18
HR18
51
51
mx_r0402
mx_r0402
H_PECI_R
CATERR_R#
H_DDR_VREF
PROC_SEL
H_CFG16_SNB_PCUSTB0
H_CFG17_SNB_PCUSTB1
TDO
TCK
TMS
TRST#
PRDY#
PREQ#
DBR#
BPM#_0
BPM#_1
BPM#_2
BPM#_3
BPM#_4
BPM#_5
BPM#_6
BPM#_7
RSVD_024
RSVD_030
RSVD_037
RSVD_036
RSVD_033
RSVD_040
RSVD_039
RSVD_018
RSVD_020
RSVD_038
RSVD_032
RSVD_034
RSVD_035
RSVD_050
RSVD_053
RSVD_051
RSVD_052
P34
T2
A36
B36
AB4
AB3
L32
M32
+5V
12
I
I
HR52
HR52
10K
10K
mx_r0402
mx_r0402
P33
L39
L40
TDI
M40
L38
J39
12
I
I
HR53
HR53
4.7K
4.7K
mx_r0402
mx_r0402
GND
K38
K40
E39
H40
H38
G38
G40
G39
F38
E40
F40
B39
J33
L34
L33
K34
N33
M34
AV1
AW2
L9
J9
K9
L31
J31
K31
AD34
AD35
VCCSA_SENSE 66
VCC_SENSE 73
VSS_SENSE 73
VCCIO_SENSE 71
VSSIO_SENSE 71
VCCAXG_SENSE 73
VSSAXG_SENSE 73
12
I
I
HR8
HR8
51
51
mx_r0402
mx_r0402
+3P3VSB
12
NI
NI
HR15
HR15
220
220
mx_r0402
mx_r0402
NOTE:
Place near CPU
12
I
I
HR9
HR9
51
51
mx_r0402
mx_r0402
12
I
I
HR12
HR12
51
51
mx_r0402
mx_r0402
GND
+1P05V_CPUIO +1P05V_CPUIO
BPM0# 82
BPM1# 82
BPM2# 82
BPM3# 82
BPM4# 82
BPM5# 82
BPM6# 82
BPM7# 82
12
GND
H_PRDY# 82
H_PREQ# 82
SYS_RESET_DBR# 22,82,83
PEGATRON DT-MB RESTRICTED SECRET
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet
Date: Sheet of
2
Date: Sheet of
NI
NI
HR60
HR60
1K
1K
mx_r0402
mx_r0402
VCCSA_VID 66
NOTE:
Place near XDP connector
12
I
I
HR10
HR10
51
51
mx_r0402
mx_r0402
12
I
I
HR13
HR13
51
51
mx_r0402
mx_r0402
GND
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
IPMSB-BE/CR
IPMSB-BE/CR
IPMSB-BE/CR
1
VCCIO_SEL 71
TDO 82
TDI 82
TCK 82
TMS 82
TRST# 82
MISC 4-6
MISC 4-6
MISC 4-6
Livy_Zhu
Livy_Zhu
Livy_Zhu
12 83Friday, September 24, 2010
12 83Friday, September 24, 2010
12 83Friday, September 24, 2010
of
Rev
Rev
Rev
1.00
1.00
1.00
5
4
3
2
1
vinafix
I
AG33
AJ16
AJ17
AJ26
AJ28
AJ32
AK15
AK17
AK19
AK21
AK23
AK27
AK29
AK30
AK11
AK12
M13
A11
AA3
AB8
AF8
D10
H10
H11
H12
K10
K11
M10
M11
M12
A7
B9
D6
E3
E4
G3
G4
J3
J4
J7
J8
L3
L4
L7
N3
N4
N7
R3
R4
R7
U3
U4
U7
V8
W3
J10
L11
L12
I
HU1H
HU1H
VCCIO_34
VCCIO_01
VCCIO_02
VCCIO_03
VCCIO_04
VCCIO_05
VCCIO_06
VCCIO_07
VCCIO_08
VCCIO_09
VCCIO_10
VCCIO_11
VCCIO_12
VCCIO_13
VCCIO_14
VCCIO_15
VCCIO_16
VCCIO_17
VCCIO_18
VCCIO_19
VCCIO_20
VCCIO_21
VCCIO_22
VCCIO_23
VCCIO_24
VCCIO_25
VCCIO_26
VCCIO_27
VCCIO_28
VCCIO_29
VCCIO_30
VCCIO_31
VCCIO_32
VCCIO_33
VCCIO_35
VCCIO_36
VCCIO_37
VCCIO_38
VCCIO_39
VCCIO_40
VCCIO_41
VCCIO_42
VCCIO_43
VCCIO_44
VCCIO_45
VCCSA_01
VCCSA_02
VCCSA_03
VCCSA_04
VCCSA_05
VCCSA_06
VCCSA_07
VCCSA_08
VCCSA_09
VCCSA_10
VCCSA_11
VCCPLL_01
VCCPLL_02
SOCKET_1155P
SOCKET_1155P
VDDQ_01
VDDQ_02
VDDQ_04
VDDQ_05
VDDQ_06
VDDQ_07
VDDQ_08
VDDQ_09
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VDDQ_14
VDDQ_15
VDDQ_16
VDDQ_17
VDDQ_18
VDDQ_19
VDDQ_20
VDDQ_21
VDDQ_22
VDDQ_23
VDDQ_03
AJ13
AJ14
AJ23
AJ24
AR20
AR21
AR22
AR23
AR24
AU19
AU23
AU27
AU31
AV21
AV24
AV25
AV29
AV33
AW31
AY23
AY26
AY28
AJ20
+1P5V_DUAL+1P05V_CPUIO
I
I
12
HCB1
HCB1
22UF/6.3V
22UF/6.3V
X5R 20%
X5R 20%
mx_c0805_small
mx_c0805_small
GND GND GND
I
I
12
HCB6
HCB6
22UF/6.3V
22UF/6.3V
X5R 20%
X5R 20%
mx_c0805_small
mx_c0805_small
Inside processor socket cavity
8/17: change to 22UF 11X234226160
I
I
12
HCB3
HCB3
22UF/6.3V
22UF/6.3V
X5R 20%
X5R 20%
mx_c0805_small
mx_c0805_small
+V_AXG
AB33
AB34
AB35
AB36
AB37
AB38
AB39
AB40
AC33
AC34
AC35
AC36
AC37
AC38
AC39
AC40
W33
W34
W35
W36
W37
W38
T33
T34
T35
T36
T37
T38
T39
T40
U33
U34
U35
U36
U37
U38
U39
U40
Y33
Y34
Y35
Y36
Y37
Y38
I
I
HU1G
HU1G
VCCAXG_01
VCCAXG_02
VCCAXG_03
VCCAXG_04
VCCAXG_05
VCCAXG_06
VCCAXG_07
VCCAXG_08
VCCAXG_09
VCCAXG_10
VCCAXG_11
VCCAXG_12
VCCAXG_13
VCCAXG_14
VCCAXG_15
VCCAXG_16
VCCAXG_17
VCCAXG_18
VCCAXG_19
VCCAXG_20
VCCAXG_21
VCCAXG_22
VCCAXG_23
VCCAXG_24
VCCAXG_25
VCCAXG_26
VCCAXG_27
VCCAXG_28
VCCAXG_29
VCCAXG_30
VCCAXG_31
VCCAXG_32
VCCAXG_33
VCCAXG_34
VCCAXG_35
VCCAXG_36
VCCAXG_37
VCCAXG_38
VCCAXG_39
VCCAXG_40
VCCAXG_41
VCCAXG_42
VCCAXG_43
VCCAXG_44
SOCKET_1155P
SOCKET_1155P
I
A12
A13
A14
A15
A16
A18
A24
A25
A27
A28
B15
B16
B18
B24
B25
B27
B28
B30
B31
B33
B34
C15
C16
C18
C19
C21
C22
C24
C25
C27
C28
C30
C31
C33
C34
C36
D13
D14
D15
D16
D18
D19
D21
D22
D24
D25
D27
D28
D30
D31
D33
D34
D35
D36
E15
E16
E18
E19
E21
E22
E24
E25
E27
E28
E30
E31
E33
E34
E35
F15
F16
F18
F19
F21
F22
F24
F25
F27
F28
F30
F31
I
HU1F
HU1F
VCC_001
VCC_002
VCC_003
VCC_004
VCC_005
VCC_006
VCC_007
VCC_008
VCC_009
VCC_010
VCC_011
VCC_012
VCC_013
VCC_014
VCC_015
VCC_016
VCC_017
VCC_018
VCC_019
VCC_020
VCC_021
VCC_022
VCC_023
VCC_024
VCC_025
VCC_026
VCC_027
VCC_028
VCC_029
VCC_030
VCC_031
VCC_032
VCC_033
VCC_034
VCC_035
VCC_036
VCC_037
VCC_038
VCC_039
VCC_040
VCC_041
VCC_042
VCC_043
VCC_044
VCC_045
VCC_046
VCC_047
VCC_048
VCC_049
VCC_050
VCC_051
VCC_052
VCC_053
VCC_054
VCC_055
VCC_056
VCC_057
VCC_058
VCC_059
VCC_060
VCC_061
VCC_062
VCC_063
VCC_064
VCC_065
VCC_066
VCC_067
VCC_068
VCC_069
VCC_070
VCC_071
VCC_072
VCC_073
VCC_074
VCC_075
VCC_076
VCC_077
VCC_078
VCC_079
VCC_080
VCC_081
VCC_082
VCC_083
VCC_084
VCC_085
VCC_086
VCC_087
VCC_088
VCC_089
VCC_090
VCC_091
VCC_092
VCC_093
VCC_094
VCC_095
VCC_096
VCC_097
VCC_098
VCC_099
VCC_100
VCC_101
VCC_102
VCC_103
VCC_104
VCC_105
VCC_106
VCC_107
VCC_108
VCC_109
VCC_110
VCC_111
VCC_112
VCC_113
VCC_114
VCC_115
VCC_116
VCC_117
VCC_118
VCC_119
VCC_120
VCC_121
VCC_122
VCC_123
VCC_124
VCC_125
VCC_126
VCC_127
VCC_128
VCC_129
VCC_130
VCC_131
VCC_132
VCC_133
VCC_134
VCC_135
VCC_136
VCC_137
VCC_138
VCC_139
VCC_140
VCC_141
VCC_142
VCC_143
VCC_144
VCC_145
VCC_146
VCC_147
VCC_148
VCC_149
VCC_150
VCC_151
VCC_152
VCC_153
VCC_154
VCC_155
VCC_156
VCC_157
VCC_158
VCC_159
VCC_160
VCC_161
F32
F33
F34
G15
G16
G18
G19
G21
G22
G24
G25
G27
G28
G30
G31
G32
G33
H13
H14
H15
H16
H18
H19
H21
H22
H24
H25
H27
H28
H30
H31
H32
J12
J15
J16
J18
J19
J21
J22
J24
J25
J27
J28
J30
K15
K16
K18
K19
K21
K22
K24
K25
K27
K28
K30
L13
L14
L15
L16
L18
L19
L21
L22
L24
L25
L27
L28
L30
M14
M15
M16
M18
M19
M21
M22
M24
M25
M27
M28
M30
+VCORE+VCORE
+0P925V_SA
+1P8V_SFR
09/07
I
I
12
HCB5
HCB5
0.1UF/16V
0.1UF/16V
Y5V +80-20%
Y5V +80-20%
mx_c0402
mx_c0402
I
I
12
HCB4
HCB4
0.1UF/16V
0.1UF/16V
Y5V +80-20%
Y5V +80-20%
mx_c0402
mx_c0402
GNDGND
D D
C C
B B
A A
5
SOCKET_1155P
SOCKET_1155P
PEGATRON DT-MB RESTRICTED SECRET
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
4
http://vinafix.vn
3
2
Date: Sheet
Engineer:
IPMSB-BE/CR
IPMSB-BE/CR
IPMSB-BE/CR
1
VCC 5 - 6
VCC 5 - 6
VCC 5 - 6
Livy_Zhu
Livy_Zhu
Livy_Zhu
13 83Friday, September 24, 2010
13 83Friday, September 24, 2010
13 83Friday, September 24, 2010
of
Rev
Rev
Rev
1.00
1.00
1.00
5
4
3
2
1
vinafix
D D
C C
B B
A A
GND GND GND GND
A17
A23
A26
A29
A35
AA33
AA34
AA35
AA36
AA37
AA38
AA6
AB5
AC1
AC6
AD33
AD36
AD38
AD39
AD40
AD5
AD8
AE3
AE33
AE36
AF1
AF34
AF36
AF37
AF40
AF5
AF6
AF7
AG36
AH2
AH3
AH33
AH36
AH37
AH38
AH39
AH40
AH5
AH8
AJ12
AJ15
AJ18
AJ21
AJ25
AJ27
AJ36
AJ5
AK1
AK10
AK13
AK14
AK16
AK22
AK28
AK31
AK32
AK33
AK34
AK35
AK36
AK37
AK4
AK40
AK5
AK6
AK7
AK8
AK9
AL11
AL14
AL17
AL19
AL24
AL27
AL30
AL36
AL5
AM1
AM11
AM14
AM17
AM2
AM21
AM23
AM25
AV39
A4
I
I
HU1I
HU1I
VSS_001
VSS_002
VSS_003
VSS_004
VSS_005
VSS_006
VSS_007
VSS_008
VSS_009
VSS_010
VSS_011
VSS_012
VSS_013
VSS_014
VSS_015
VSS_016
VSS_017
VSS_018
VSS_019
VSS_020
VSS_021
VSS_022
VSS_023
VSS_024
VSS_025
VSS_026
VSS_027
VSS_028
VSS_029
VSS_030
VSS_031
VSS_032
VSS_033
VSS_034
VSS_035
VSS_036
VSS_037
VSS_038
VSS_039
VSS_040
VSS_041
VSS_042
VSS_043
VSS_044
VSS_045
VSS_046
VSS_047
VSS_048
VSS_049
VSS_050
VSS_051
VSS_052
VSS_053
VSS_054
VSS_055
VSS_056
VSS_057
VSS_058
VSS_059
VSS_060
VSS_061
VSS_062
VSS_063
VSS_064
VSS_065
VSS_066
VSS_067
VSS_068
VSS_069
VSS_070
VSS_071
VSS_072
VSS_073
VSS_074
VSS_075
VSS_076
VSS_077
VSS_078
VSS_079
VSS_080
VSS_081
VSS_082
VSS_083
VSS_084
VSS_085
VSS_086
VSS_087
VSS_088
VSS_089
VSS_090
VSS_NCTF_01
VSS_NCTF_02
SOCKET_1155P
SOCKET_1155P
5
GND
GND
VSS_091
VSS_092
VSS_093
VSS_094
VSS_095
VSS_096
VSS_097
VSS_098
VSS_099
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
AM27
AM3
AM30
AM36
AM37
AM38
AM39
AM4
AM40
AM5
AN10
AN11
AN14
AN17
AN19
AN22
AN24
AN27
AN30
AN31
AN32
AN33
AN34
AN35
AN36
AN5
AN6
AN7
AN8
AN9
AP1
AP11
AP14
AP17
AP22
AP25
AP27
AP30
AP36
AP37
AP4
AP40
AP5
AR11
AR14
AR17
AR18
AR19
AR27
AR30
AR36
AR5
AT1
AT10
AT12
AT13
AT15
AT16
AT17
AT2
AT25
AT27
AT28
AT29
AT3
AT30
AT31
AT32
AT33
AT34
AT35
AT36
AT37
AT38
AT39
AT4
AT40
AT5
AT6
AT7
AT8
AT9
AU1
AU15
AU26
AU34
AU4
AU6
AU8
AV10
AV11
AV14
AV17
AV35
AV38
AW10
AW11
AW14
AW16
AW36
AW6
AY11
AY14
AY18
AY35
AY37
4
AV3
AV6
AY4
AY6
AY8
B10
B13
B14
B17
B23
B26
B29
B32
B35
B38
C11
C12
C17
C20
C23
C26
C29
C32
C35
D17
D20
D23
D26
D29
D32
D37
D39
E11
E12
E17
E20
E23
E26
E29
E32
E36
F10
F13
F14
F17
F20
F23
F26
F29
F35
F37
F39
G11
G12
G17
G20
G23
G26
G29
G34
B6
C7
C8
D2
D4
D5
D9
E7
E8
F1
F2
F5
F6
F9
G7
B3
I
I
HU1J
HU1J
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_NCTF_03
VSS_NCTF_04
GND
GND
SOCKET_1155P
SOCKET_1155P
G8
VSS_271
H1
VSS_272
H17
VSS_273
H2
VSS_274
H20
VSS_275
H23
VSS_276
H26
VSS_277
H29
VSS_278
H33
VSS_279
H35
VSS_280
H37
VSS_281
H39
VSS_282
H5
VSS_283
H6
VSS_284
H9
VSS_285
J11
VSS_286
J17
VSS_287
J20
VSS_288
J23
VSS_289
J26
VSS_290
J29
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360
J32
K1
K12
K13
K14
K17
K2
K20
K23
K26
K29
K33
K35
K37
K39
K5
K6
L10
L17
L20
L23
L26
L29
L8
M1
M17
M2
M20
M23
M26
M29
M33
M35
M37
M39
M5
M6
M9
N8
P1
P2
P36
P38
P40
P5
P6
R33
R35
R37
R39
R8
T1
T5
T6
U8
V1
V2
V33
V34
V35
V36
V37
V38
V39
V40
V5
W6
Y5
Y8
NOBOM
NOBOM
HT38
HT38
http://vinafix.vn
TP_H_NCTF_A38
1
I
I
BACKPLATE1
BACKPLATE1
INTEL LGA 1156P BACK PLATE,3 SCREW
INTEL LGA 1156P BACK PLATE,3 SCREW
PT44P11-6401
PT44P11-6401
3
AB7
AD37
AG4
AJ29
AJ30
AJ31
AV34
AW34
P35
P37
P39
R34
R36
R38
R40
A38
AU40
AW38
C2
D1
I
I
HU1K
HU1K
RSVD_04
RSVD_05
RSVD_08
RSVD_10
RSVD_11
RSVD_12
RSVD_19
RSVD_21
RSVD_43
RSVD_44
RSVD_45
RSVD_46
RSVD_47
RSVD_48
RSVD_49
NCTF_01
NCTF_02
NCTF_03
NCTF_04
NCTF_05
SOCKET_1155P
SOCKET_1155P
FC_AH1
FC_AH4
RSVD_15
RSVD_14
RSVD_13
RSVD_17
RSVD_22
RSVD_07
RSVD_03
RSVD_06
RSVD_09
RSVD_27
RSVD_26
RSVD_25
RSVD_31
RSVD_41
NP_NC1
NP_NC2
NP_NC3
NP_NC4
NP_NC5
NP_NC6
NP_NC7
AH1
AH4
AT11
AP20
AN20
AU10
AY10
AF4
AB6
AE6
AJ11
D38
C39
C38
J34
N34
1
2
3
4
5
6
7
SA_DIMM_VR
SB_DIMM_VR
I
I
ILM1
ILM1
SOCKET1156_ILM
SOCKET1156_ILM
2
HR42 0Imx_r0402HR42 0Imx_r0402
1 2
HR43 0Imx_r0402HR43 0Imx_r0402
1 2
I
I
I
12
HC2
HC2
0.1UF/16V
0.1UF/16V
Y5V +80-20%
Y5V +80-20%
mx_c0402
mx_c0402
GND GND
INTEL LGA1156 SOCKET ILM
INTEL LGA1156 SOCKET ILM
I
12
HC3
HC3
0.1UF/16V
0.1UF/16V
Y5V +80-20%
Y5V +80-20%
mx_c0402
mx_c0402
PEGATRON DT-MB RESTRICTED SECRET
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet
Date: Sheet of
Date: Sheet of
DIMM_DQ_VREF_A 16
DIMM_DQ_VREF_B 17
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
IPMSB-BE/CR
IPMSB-BE/CR
IPMSB-BE/CR
1
VSS 6 - 6
VSS 6 - 6
VSS 6 - 6
Livy_Zhu
Livy_Zhu
Livy_Zhu
14 83Friday, September 24, 2010
14 83Friday, September 24, 2010
14 83Friday, September 24, 2010
Rev
Rev
Rev
1.00
1.00
1.00
of
5
4
3
2
1
vinafix
D D
+3P3VA
I
I
12
HC9
HC9
0.1UF/16V
0.1UF/16V
X7R 10%
+3P3VA
12
I
I
HR44
HR44
1K
1K
mx_r0402
C C
PLTRST#22,35,53,55,80,82,83
I
I
HR47
HR47
10K
10K
mx_r0402
mx_r0402
1 2
TBD
HQ1_B
12
NI
NI
HR50
HR50
5.1K
5.1K
mx_r0402
mx_r0402
mx_r0402
PLTRST
3
3
C
C
I
I
B
1
B
1
HQ1
HQ1
12
PMBS3904
PMBS3904
E
E
2
2
GND
GNDGND
8/24
5 6
NI
NI
SC84
SC84
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
147
VCC
VCC
GND
GND
I
I
SU2C
SU2C
74LVC14AD
74LVC14AD
X7R 10%
mx_c0402
mx_c0402
GND
PLTRST_CPU#_SHT
178 ohm in CRB and PDG
I
I
HR46
HR46
180
180
1%
1%
MX_R0402
MX_R0402
1 2
GND
12
I
I
HR49
HR49
75
75
1%
1%
mx_r0402
mx_r0402
I
I
HR48
HR48
1K
1K
mx_r0402
mx_r0402
1 2
PLTRST_CPU# 12
CPURST_XDP# 82,83
PLTRST_CPU#
B B
+3P3VA
+3P3VSB
12
I
I
SR276
SR276
47K
47K
I
I
SR278
SQ11_B_R SQ11_B
12
SC80
SC80
2.2UF/6.3V
2.2UF/6.3V
X5R 10%
X5R 10%
I
I
mx_c0603
mx_c0603
A A
5
GND
SR278
1 2
0
0
12
1
1
NI
NI
SC81
SC81
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
4
12
I
I
SR279
SR279
10K
10K
I
I
SR282
SR282
SQ12_BSQ12_B_R RSMRST#_R
1 2
0
I
I
SQ11
SQ11
PMBS3904
PMBS3904
0
12
3
3
C
C
B
B
E
E
2
2
GND GNDGNDGND
http://vinafix.vn
NI
NI
SC82
SC82
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
+3P3VA
I
I
SU2D
SU2D
147
74LVC14AD
74LVC14AD
VCC
VCC
9 8
GND
GND
I
I
SR12
SR12
4.7K
4.7K
12
RSMRST# 22,52,83
PEGATRON DT-MB RESTRICTED SECRET
PLTRST_CPU#
PLTRST_CPU#
1
PLTRST_CPU#
Livy_Zhu
Livy_Zhu
Livy_Zhu
15 83Friday, September 24, 2010
15 83Friday, September 24, 2010
15 83Friday, September 24, 2010
Rev
Rev
Rev
1.00
1.00
1.00
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
Engineer:
IPMSB-BE/CR
IPMSB-BE/CR
IPMSB-BE/CR
5
vinafix
XMM1 COLOR: BLUE
D D
M_CHA_MAA0
M_CHA_MAA1
M_CHA_MAA2
M_CHA_MAA3
M_CHA_MAA4
M_CHA_MAA5
M_CHA_MAA6
M_CHA_MAA7
M_CHA_MAA8
M_CHA_MAA9
M_CHA_MAA11
M_CHA_MAA12
M_CHA_MAA13
M_CHA_MAA14
M_CHA_MAA15
M_CHA_CLK19
M_CHA_CLK1#9
M_CHA_CLK09
M_CHA_CLK0#9
C C
B B
A A
M_CHA_CS#19
M_CHA_CS#09
M_CHA_CKE19
M_CHA_CKE09
M_CHA_BA29
M_CHA_BA19
M_CHA_BA09
SMB_DATA_MAIN17,54,81,82,83
MA_ECC_CB[0..7]9
SMB_CLK_MAIN17,54,81,82,83
MA_ECC_CB7
MA_ECC_CB6
MA_ECC_CB5
MA_ECC_CB4
MA_ECC_CB3
MA_ECC_CB2
MA_ECC_CB1
MA_ECC_CB0
GND
M_CHA_WE#9
M_CHA_RAS#9
M_CHA_CAS#9
M_CHA_ODT19
M_CHA_ODT09
DDR3_DRAMRST#9,17
12
NI
NI
HC1
HC1
150PF/50V
150PF/50V
NPO 5%
NPO 5%
mx_c0402
mx_c0402
GND
M_CHA_DQS89
M_CHA_DQS8#9
GND
5
IDIMMA0A
IDIMMA0A
188
A0
181
A1
61
A2
180
A3
59
A4
58
A5
178
A6
56
A7
177
A8
175
A9
70
A10/AP
55
A11
174
A12
196
A13
172
A14
171
A15
63
CK1P/NU
64
CK1N/NU
184
CK0P
185
CK0N
76
CS1#
193
CS0#
169
CKE1
50
CKE0
52
BA2
190
BA1
71
BA0
238
SDA
118
SCL
165
CB7
164
CB6
159
CB5
158
CB4
46
CB3
45
CB2
40
CB1
39
CB0
237
SA1
117
SA0
73
WE#
192
RAS#
74
CAS#
77
ODT1
195
ODT0
168
RESET#
161
DM8/DQS17P
162
NC/DQS17N
230
DM7/DQS16P
231
NC/DQS16N
221
DM6/DQS15P
222
NC/DQS15N
212
DM5/DQS14P
213
NC/DQS14N
203
DM4/DQS13P
204
NC/DQS13N
152
DM3/DQS12P
153
NC/DQS12N
143
DM2/DQS11P
144
NC/DQS11N
134
DM1/DQS10P
135
NC/DQS10N
125
DM0/DQS9P
126
NC/DQS9N
43
NC/DQS8P
42
NC/DQS8N
198
FREE1
187
FREE2
49
FREE3
48
FREE4
DDR3_DIMM_240P
DDR3_DIMM_240P
I
I
DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
DQS7P
DQS7N
DQS6P
DQS6N
DQS5P
DQS5N
DQS4P
DQS4N
DQS3P
DQS3N
DQS2P
DQS2N
DQS1P
DQS1N
DQS0P
DQS0N
RESERVED
NC/PAR_IN
NC/ERR_OUT
NC/TEST4
234
233
228
227
115
114
109
108
225
224
219
218
106
105
100
99
216
215
210
209
97
96
91
90
207
206
201
200
88
87
82
81
156
155
150
149
37
36
31
30
147
146
141
140
28
27
22
21
138
137
132
131
19
18
13
12
129
128
123
122
10
9
4
3
112
111
103
102
94
93
85
84
34
33
25
24
16
15
7
6
79
68
53
167
M_CHA_DQ63
M_CHA_DQ62
M_CHA_DQ61
M_CHA_DQ60
M_CHA_DQ59
M_CHA_DQ58
M_CHA_DQ57
M_CHA_DQ56
M_CHA_DQ55
M_CHA_DQ54
M_CHA_DQ53M_CHA_MAA10
M_CHA_DQ52
M_CHA_DQ51
M_CHA_DQ50
M_CHA_DQ49
M_CHA_DQ48
M_CHA_DQ47
M_CHA_DQ46
M_CHA_DQ45
M_CHA_DQ44
M_CHA_DQ43
M_CHA_DQ42
M_CHA_DQ41
M_CHA_DQ40
M_CHA_DQ39
M_CHA_DQ38
M_CHA_DQ37
M_CHA_DQ36
M_CHA_DQ35
M_CHA_DQ34
M_CHA_DQ33
M_CHA_DQ32
M_CHA_DQ31
M_CHA_DQ30
M_CHA_DQ29
M_CHA_DQ28
M_CHA_DQ27
M_CHA_DQ26
M_CHA_DQ25
M_CHA_DQ24
M_CHA_DQ23
M_CHA_DQ22
M_CHA_DQ21
M_CHA_DQ20
M_CHA_DQ19
M_CHA_DQ18
M_CHA_DQ17
M_CHA_DQ16
M_CHA_DQ15
M_CHA_DQ14
M_CHA_DQ13
M_CHA_DQ12
M_CHA_DQ11
M_CHA_DQ10
M_CHA_DQ9
M_CHA_DQ8
M_CHA_DQ7
M_CHA_DQ6
M_CHA_DQ5
M_CHA_DQ4
M_CHA_DQ3
M_CHA_DQ2
M_CHA_DQ1
M_CHA_DQ0
4
M_CHA_DQS7 9
M_CHA_DQS7# 9
M_CHA_DQS6 9
M_CHA_DQS6# 9
M_CHA_DQS5 9
M_CHA_DQS5# 9
M_CHA_DQS4 9
M_CHA_DQS4# 9
M_CHA_DQS3 9
M_CHA_DQS3# 9
M_CHA_DQS2 9
M_CHA_DQS2# 9
M_CHA_DQS1 9
M_CHA_DQS1# 9
M_CHA_DQS0 9
M_CHA_DQS0# 9
4
3
+1P5V_DUAL
SMB_DATA_MAIN
SMB_CLK_MAIN
GND
12
NI
NI
SC7
SC7
150PF/50V
150PF/50V
NPO 5%
NPO 5%
mx_c0402
mx_c0402
GND
12
NI
NI
SC10
SC10
150PF/50V
150PF/50V
NPO 5%
NPO 5%
mx_c0402
mx_c0402
http://vinafix.vn
DIMM_DQ_VREF_A14
3
2
M_CHA_DQ[0..63] 9
M_CHA_MAA[0..15] 9
+VTT_DDR
12
I
I
D3CB1
D3CB1
4.7UF/6.3V
4.7UF/6.3V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
+1P5V_DUAL
12
I
I
D3R1
D3R1
1K
1K
1%
1%
mx_r0402
mx_r0402
12
I
I
D3R3
D3R3
1K
1K
1%
1%
mx_r0402
mx_r0402
GND GND
12
I
I
D3R2
D3R2
1K
1K
1%
1%
mx_r0402
mx_r0402
12
I
I
D3R4
D3R4
1K
1K
1%
1%
mx_r0402
mx_r0402
GND GND
2
12
I
I
D3CB3
D3CB3
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0402
mx_c0402
12
GNDGND
1
I
I
D3CB2
D3CB2
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0402
mx_c0402
GND
DIMM_CA_VREF_A
DIMM_DQ_VREF_A
12
I
I
D3CB4
D3CB4
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0402
mx_c0402
78
VDD10
75
VDD9
72
VDD8
69
VDD7
66
VDD6
65
VDD5
62
VDD4
60
VDD3
57
VDD2
54
VDD1
51
VDD0
240
VTT2
120
VTT1
113
GND27
110
GND26
107
GND25
104
GND24
101
GND23
98
GND22
95
GND21
92
GND20
89
GND19
86
GND18
83
GND17
80
GND16
47
GND15
44
GND14
41
GND13
38
GND12
35
GND11
32
GND10
29
GND9
26
GND8
23
GND7
20
GND6
17
GND5
14
GND4
11
GND3
8
GND2
5
GND1
2
GND0
67
VREFCA
1
VREFDQ
DDR3_DIMM_240P
DDR3_DIMM_240P
I
I
VDD21
VDD20
VDD19
VDD18
VDD17
VDD16
VDD15
VDD14
VDD13
VDD12
VDD11
GND59
GND58
GND57
GND56
GND55
GND54
GND53
GND52
GND51
GND50
GND49
GND48
GND47
GND46
GND45
GND44
GND43
GND42
GND41
GND40
GND39
GND38
GND37
GND36
GND35
GND34
GND33
GND32
GND31
GND30
GND29
GND28
NP_NC1
NP_NC2
NP_NC3
VDDSPD
197
194
191
189
186
183
182
179
176
173
170
239
235
232
229
226
223
220
217
214
211
208
205
202
199
166
163
160
157
154
151
148
145
142
139
136
133
130
127
124
121
119
116
241
242
243
236
PEGATRON DT-MB RESTRICTED SECRET
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Engineer:
IPMSB-BE/CR
IPMSB-BE/CR
IPMSB-BE/CR
1
+1P5V_DUAL+1P5V_DUAL
IDIMMA0B
IDIMMA0B
+3P3V
GND
GND
DDR3 CHANNEL A
DDR3 CHANNEL A
DDR3 CHANNEL A
Livy_Zhu
Livy_Zhu
Livy_Zhu
16 83Friday, September 24, 2010
16 83Friday, September 24, 2010
16 83Friday, September 24, 2010
12
I
I
D3CB48
D3CB48
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0402
mx_c0402
Rev
Rev
Rev
1.00
1.00
1.00
5
vinafix
XMM3 COLOR: BLUE
D D
M_CHB_MAA0
M_CHB_MAA1
M_CHB_MAA2
M_CHB_MAA3
M_CHB_MAA4
M_CHB_MAA5
M_CHB_MAA6
M_CHB_MAA7
M_CHB_MAA8
M_CHB_MAA9
M_CHB_MAA10
M_CHB_MAA11
M_CHB_MAA12
M_CHB_MAA13
M_CHB_MAA14
M_CHB_MAA15
M_CHB_CLK110
M_CHB_CLK1#10
M_CHB_CLK010
M_CHB_CLK0#10
C C
B B
A A
M_CHB_CS#110
M_CHB_CS#010
M_CHB_CKE110
M_CHB_CKE010
M_CHB_BA210
M_CHB_BA110
M_CHB_BA010
SMB_DATA_MAIN16,54,81,82,83
M_CHB_WE#10
M_CHB_RAS#10
M_CHB_CAS#10
M_CHB_ODT110
M_CHB_ODT010
GND
M_CHB_DQS810
M_CHB_DQS8#10
12
SMB_CLK_MAIN16,54,81,82,83
NI
NI
HC4
HC4
150PF/50V
150PF/50V
NPO 5%
NPO 5%
mx_c0402
mx_c0402
MB_ECC_CB7
MB_ECC_CB6
MB_ECC_CB5
MB_ECC_CB4
MB_ECC_CB3
MB_ECC_CB2
MB_ECC_CB1
MB_ECC_CB0
+3P3V
GND
GND
5
MB_ECC_CB[0..7]10
DDR3_DRAMRST#9,16
IDIMMB0A
IDIMMB0A
188
A0
181
A1
61
A2
180
A3
59
A4
58
A5
178
A6
56
A7
177
A8
175
A9
70
A10/AP
55
A11
174
A12
196
A13
172
A14
171
A15
63
CK1P/NU
64
CK1N/NU
184
CK0P
185
CK0N
76
CS1#
193
CS0#
169
CKE1
50
CKE0
52
BA2
190
BA1
71
BA0
238
SDA
118
SCL
165
CB7
164
CB6
159
CB5
158
CB4
46
CB3
45
CB2
40
CB1
39
CB0
237
SA1
117
SA0
73
WE#
192
RAS#
74
CAS#
77
ODT1
195
ODT0
168
RESET#
161
DM8/DQS17P
162
NC/DQS17N
230
DM7/DQS16P
231
NC/DQS16N
221
DM6/DQS15P
222
NC/DQS15N
212
DM5/DQS14P
213
NC/DQS14N
203
DM4/DQS13P
204
NC/DQS13N
152
DM3/DQS12P
153
NC/DQS12N
143
DM2/DQS11P
144
NC/DQS11N
134
DM1/DQS10P
135
NC/DQS10N
125
DM0/DQS9P
126
NC/DQS9N
43
NC/DQS8P
42
NC/DQS8N
198
FREE1
187
FREE2
49
FREE3
48
FREE4
DDR3_DIMM_240P
DDR3_DIMM_240P
I
I
DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
DQS7P
DQS7N
DQS6P
DQS6N
DQS5P
DQS5N
DQS4P
DQS4N
DQS3P
DQS3N
DQS2P
DQS2N
DQS1P
DQS1N
DQS0P
DQS0N
RESERVED
NC/PAR_IN
NC/ERR_OUT
NC/TEST4
234
233
228
227
115
114
109
108
225
224
219
218
106
105
100
99
216
215
210
209
97
96
91
90
207
206
201
200
88
87
82
81
156
155
150
149
37
36
31
30
147
146
141
140
28
27
22
21
138
137
132
131
19
18
13
12
129
128
123
122
10
9
4
3
112
111
103
102
94
93
85
84
34
33
25
24
16
15
7
6
79
68
53
167
M_CHB_DQ63
M_CHB_DQ62
M_CHB_DQ61
M_CHB_DQ60
M_CHB_DQ59
M_CHB_DQ58
M_CHB_DQ57
M_CHB_DQ56
M_CHB_DQ50
M_CHB_DQ52
M_CHB_DQ54
M_CHB_DQ49
M_CHB_DQ51
M_CHB_DQ55
M_CHB_DQ53
M_CHB_DQ48
M_CHB_DQ47
M_CHB_DQ46
M_CHB_DQ45
M_CHB_DQ44
M_CHB_DQ43
M_CHB_DQ42
M_CHB_DQ41
M_CHB_DQ40
M_CHB_DQ39
M_CHB_DQ38
M_CHB_DQ37
M_CHB_DQ36
M_CHB_DQ35
M_CHB_DQ34
M_CHB_DQ33
M_CHB_DQ32
M_CHB_DQ31
M_CHB_DQ30
M_CHB_DQ29
M_CHB_DQ28
M_CHB_DQ27
M_CHB_DQ26
M_CHB_DQ25
M_CHB_DQ24
M_CHB_DQ23
M_CHB_DQ22
M_CHB_DQ21
M_CHB_DQ20
M_CHB_DQ19
M_CHB_DQ18
M_CHB_DQ17
M_CHB_DQ16
M_CHB_DQ11
M_CHB_DQ14
M_CHB_DQ8
M_CHB_DQ12
M_CHB_DQ10
M_CHB_DQ15
M_CHB_DQ9
M_CHB_DQ13
M_CHB_DQ7
M_CHB_DQ6
M_CHB_DQ5
M_CHB_DQ4
M_CHB_DQ3
M_CHB_DQ2
M_CHB_DQ1
M_CHB_DQ0
4
M_CHB_DQS7 10
M_CHB_DQS7# 10
M_CHB_DQS6 10
M_CHB_DQS6# 10
M_CHB_DQS5 10
M_CHB_DQS5# 10
M_CHB_DQS4 10
M_CHB_DQS4# 10
M_CHB_DQS3 10
M_CHB_DQS3# 10
M_CHB_DQS2 10
M_CHB_DQS2# 10
M_CHB_DQS1 10
M_CHB_DQS1# 10
M_CHB_DQS0 10
M_CHB_DQS0# 10
4
3
+1P5V_DUAL
DIMM_DQ_VREF_B14
http://vinafix.vn
3
M_CHB_DQ[0..63] 10
M_CHB_MAA[0..15] 10
I
I
12
D3R5
D3R5
1K
1K
1%
1%
mx_r0402
mx_r0402
12
I
I
D3R7
D3R7
1K
1K
1%
1%
mx_r0402
mx_r0402
GND
I
I
12
D3CB16
D3CB16
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0402
mx_c0402
2
+VTT_DDR
12
GND
+1P5V_DUAL
12
12
GNDGND
2
I
I
D3CB9
D3CB9
4.7UF/6.3V
4.7UF/6.3V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
I
I
D3R6
D3R6
1K
1K
1%
1%
mx_r0402
mx_r0402
I
I
D3R8
D3R8
1K
1K
1%
1%
mx_r0402
mx_r0402
12
I
I
D3CB10
D3CB10
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0402
mx_c0402
GND
GND
DIMM_CA_VREF_B
DIMM_DQ_VREF_B
12
I
I
D3CB15
D3CB15
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0402
mx_c0402
GND
1
+1P5V_DUAL+1P5V_DUAL
78
VDD10
75
VDD9
72
VDD8
69
VDD7
66
VDD6
65
VDD5
62
VDD4
60
VDD3
57
VDD2
54
VDD1
51
VDD0
240
VTT2
120
VTT1
113
GND27
110
GND26
107
GND25
104
GND24
101
GND23
98
GND22
95
GND21
92
GND20
89
GND19
86
GND18
83
GND17
80
GND16
47
GND15
44
GND14
41
GND13
38
GND12
35
GND11
32
GND10
29
GND9
26
GND8
23
GND7
20
GND6
17
GND5
14
GND4
11
GND3
8
GND2
5
GND1
2
GND0
67
VREFCA
1
VREFDQ
DDR3_DIMM_240P
DDR3_DIMM_240P
I
I
VDD21
VDD20
VDD19
VDD18
VDD17
VDD16
VDD15
VDD14
VDD13
VDD12
VDD11
GND59
GND58
GND57
GND56
GND55
GND54
GND53
GND52
GND51
GND50
GND49
GND48
GND47
GND46
GND45
GND44
GND43
GND42
GND41
GND40
GND39
GND38
GND37
GND36
GND35
GND34
GND33
GND32
GND31
GND30
GND29
GND28
NP_NC1
NP_NC2
NP_NC3
VDDSPD
197
194
191
189
186
183
182
179
176
173
170
239
235
232
229
226
223
220
217
214
211
208
205
202
199
166
163
160
157
154
151
148
145
142
139
136
133
130
127
124
121
119
116
241
242
243
236
IDIMMB0B
IDIMMB0B
GND
+3P3V
12
GND
I
I
D3CB49
D3CB49
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0402
mx_c0402
PEGATRON DT-MB RESTRICTED SECRET
DDR3 CHANNEL B
DDR3 CHANNEL B
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Engineer:
IPMSB-BE/CR
IPMSB-BE/CR
IPMSB-BE/CR
DDR3 CHANNEL B
Livy_Zhu
Livy_Zhu
Livy_Zhu
1
17 83Friday, September 24, 2010
17 83Friday, September 24, 2010
17 83Friday, September 24, 2010
Rev
Rev
Rev
1.00
1.00
1.00
5
4
3
2
1
vinafix
D D
C C
+1P5V_DUAL
GND
12
I
I
D3CB18
D3CB18
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0402
mx_c0402
12
I
I
D3CB23
D3CB23
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0402
mx_c0402
12
I
I
D3CB66
D3CB66
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0402
mx_c0402
12
I
I
D3CB19
D3CB19
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0402
mx_c0402
GND GND GND GND
12
I
I
D3CB24
D3CB24
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0402
mx_c0402
12
I
I
D3CB67
D3CB67
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0402
mx_c0402
12
I
I
D3CB20
D3CB20
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0402
mx_c0402
12
I
I
D3CB25
D3CB25
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0402
mx_c0402
12
I
I
D3CB68
D3CB68
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0402
mx_c0402
12
I
I
D3CB21
D3CB21
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0402
mx_c0402
12
I
I
D3CB26
D3CB26
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0402
mx_c0402
12
I
I
D3CB69
D3CB69
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0402
mx_c0402
12
I
I
D3CB22
D3CB22
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0402
mx_c0402
12
I
I
D3CB27
D3CB27
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0402
mx_c0402
12
I
I
D3CB70
D3CB70
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0402
mx_c0402
12
I
I
D3CB28
D3CB28
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0402
mx_c0402
8/30:
12
I
I
D3CB71
D3CB71
1UF/16V
1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
NOTE:
Place those cap close to CH A DIMM0
12
I
I
D3CB29
D3CB29
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0402
mx_c0402
12
I
I
D3CB30
D3CB30
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0402
mx_c0402
12
I
I
D3CB31
D3CB31
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0402
mx_c0402
GNDGND GND GND GNDGND GNDGND GND GNDGND GNDGND
12
I
I
D3CB32
D3CB32
1UF/16V
1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
12
I
I
D3CB33
D3CB33
1UF/16V
1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
8/30:
12
I
I
D3CB34
D3CB34
1UF/16V
1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
12
I
I
D3CB35
D3CB35
1UF/16V
1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
NOTE:
Place those cap between CH B DIMM 0 to DIMM1
GND GND GND GND GNDGND
Place those cap between CH A DIMM1 to CH B DIMM0
B B
12
I
I
D3CB72
D3CB72
22UF/6.3V
22UF/6.3V
X5R 20%
X5R 20%
mx_c0805
mx_c0805
GND GNDGND GNDGND
12
I
I
D3CB73
D3CB73
22UF/6.3V
22UF/6.3V
X5R 20%
X5R 20%
mx_c0805
mx_c0805
12
I
I
D3CB74
D3CB74
22UF/6.3V
22UF/6.3V
X5R 20%
X5R 20%
mx_c0805
mx_c0805
12
I
I
D3CB75
D3CB75
22UF/6.3V
22UF/6.3V
X5R 20%
X5R 20%
mx_c0805
mx_c0805
12
I
I
D3CB77
D3CB77
22UF/6.3V
22UF/6.3V
X5R 20%
X5R 20%
mx_c0805
mx_c0805
12
I
I
+
+
D3CE3
D3CE3
560UF/6.3V
560UF/6.3V
Irms = 5.7A
Irms = 5.7A
GND GND GND
12
8/26:delete D3CE5
NI
NI
+
+
D3CE4
D3CE4
680UF/4V
680UF/4V
12
NI
NI
+
+
D3CE6
D3CE6
680UF/4V
680UF/4V
TBD
Place D3CB77 near CH B DIMM1
A A
PEGATRON DT-MB RESTRICTED SECRET
DDR3 TERMINATION A&B
DDR3 TERMINATION A&B
DDR3 TERMINATION A&B
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet
Date: Sheet of
5
4
http://vinafix.vn
3
2
Date: Sheet of
Engineer:
IPMSB-BE/CR
IPMSB-BE/CR
IPMSB-BE/CR
Livy_Zhu
Livy_Zhu
Livy_Zhu
18 83Friday, September 24, 2010
18 83Friday, September 24, 2010
1
18 83Friday, September 24, 2010
Rev
Rev
Rev
1.00
1.00
1.00
of
5
vinafix
D D
C C
PME#33
Strapping Options Flash
NOTE:
SATA1GP
/GPIO19
00
10
11
12
GND
NI
NI
SC21
SC21
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0402
mx_c0402
Boot DeviceGNT1#
LPC
PCI
SPI
+3P3V
CK_33M_PCIFB
12
GND
SRN5A
SRN5A
I
I
SRN5B
SRN5B
I
I
SRN10A
SRN10A
I
I
SRN5C
SRN5C
I
I
SRN6B
SRN6B
I
I
SRN8A
SRN8A
I
I
SRN8D
SRN8D
I
I
SRN6A
SRN6A
I
I
NI
NI
SC24
SC24
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0402
mx_c0402
1 2
3 4
1 2
5 6
3 4
1 2
7 8
1 2
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
+3P3V
+3P3V
+3P3VSB
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
1 2
ST26
ST26
ST27
ST27
ST28
ST28
ST29
ST29
SRN6D
SRN6D
SRN4A
SRN4A
SRN4B
SRN4B
SRN8B
SRN8B
SRN5D
SRN5D
SRN8C
SRN8C
SRN10C
SRN10C
SRN4D
SRN4D
SRN10B
SRN10B
SRN6C
SRN6C
SRN10D
SRN10D
SRN4C
SRN4C
NI
NI
SR11
SR11
4.7K
4.7K
4
NOBOM
NOBOM
NOBOM
NOBOM
CK_33M_PCIFB24
PCH_GNT3
1
PCH_GNT2
1
PCH_GNT1
1
PCH_GNT0
1
7 8
8.2K
8.2K
1 2
8.2K
8.2K
3 4
8.2K
8.2K
3 4
8.2K
8.2K
7 8
8.2K
8.2K
5 6
8.2K
8.2K
5 6
8.2K
8.2K
7 8
8.2K
8.2K
3 4
8.2K
8.2K
5 6
8.2K
8.2K
7 8
8.2K
8.2K
5 6
8.2K
8.2K
ST30
ST30
ST31
ST31
1
1
TP_SU1_AV14
TP_SU1_BH8
SU1_DEVSEL#
IPU 20K
IPU 20K
IPU
IPU 20K
Native CoreIPU 20K
Native Core
Native Core
Native Core
Native Core
Native Core
GPI Core
GPI Core
GPI Core
GPI Core
I
I
SU1A
SU1A
AV14
PCIRST#
AV15
PME#
BH8
PAR
BH9
DEVSEL#
BD15
CLKIN_PCILOOPBACK
BF11
IRDY#
BR6
SERR#
BC12
STOP#
BA17
PLOCK#
BC8
TRDY#
BM3
PERR#
BC11
FRAME#
BE2
GNT3#/GPIO55
BU12
GNT2#/GPIO53
AV8
GNT1#/GPIO51
BA15
GNT0#
AV11
REQ3#/GPIO54
BK8
REQ2#/GPIO52
BT5
REQ1#/GPIO50
BG5
REQ0#
BK10
PIRQA#
BJ5
PIRQB#
BM15
PIRQC#
BP5
PIRQD#
BN9
PIRQE#/GPIO2
AV9
PIRQF#/GPIO3
BT15
PIRQG#/GPIO4
BR4
PIRQH#/GPIO5
3
BN4
C/BE0#
BP7
C/BE1#
BG2
C/BE2#
BP13
C/BE3#
BF15
AD0
BF17
AD1
BT7
AD2
BT13
AD3
BG12
AD4
BN11
AD5
BJ12
AD6
BU9
AD7
BR12
AD8
PCI
PCI
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
BJ3
BR9
BJ10
BM8
BF3
BN2
BE4
BE6
BG15
BC6
BT11
BA14
BL2
BC4
BL4
BC2
BM13
BA9
BF9
BA8
BF8
AV17
BK12
2
1
12
I
I
SR6
SR6
2.7K
2.7K
mx_r0402
mx_r0402
12
NI
NI
SC2
SC2
150PF/50V
150PF/50V
NPO 5%
NPO 5%
mx_c0402
mx_c0402
12
I
I
SC8
SC8
12PF/50V
12PF/50V
NPO 5%
NPO 5%
mx_c0402
mx_c0402
+3P3VSB +3P3VSB+3P3VSB
I
I
Y5
Y5
32.768Khz
32.768Khz
1
1
GND GND
GND GND
324
324
3
4
GNDGND
1 2
4
GND GNDGND
12
I
I
SR8
SR8
2.7K
2.7K
mx_r0402
mx_r0402
12
NI
NI
SC44
SC44
150PF/50V
150PF/50V
NPO 5%
NPO 5%
mx_c0402
mx_c0402
I
I
SR15
SR15
10M
10M
MX_R0603
MX_R0603
Y5_RTC
2
I
I
SR9
SR9
2.7K
2.7K
mx_r0402
mx_r0402
NI
NI
SC5
SC5
150PF/50V
150PF/50V
NPO 5%
NPO 5%
mx_c0402
mx_c0402
12
12
GNDGND
I
I
SR10
SR10
2.7K
2.7K
mx_r0402
mx_r0402
Native Sus
Native Sus
NI
NI
SC6
SC6
150PF/50V
150PF/50V
NPO 5%
NPO 5%
mx_c0402
mx_c0402
PCH_RTCX1
PCH_RTCX2
12
I
I
SC9
SC9
12PF/50V
12PF/50V
NPO 5%
NPO 5%
mx_c0402
mx_c0402
SMBUS
SMBUS
Native Sus
SPI_CS1#
SPI_CS0#
SPI_MOSI
SPI_MISO
SPI_CLK
BN49
BU49
BR46
AR56
AT57
AU53
AT55
AR54
Native Sus
Native Sus
IPD 20K
IPU 20K
BT47
BR49
BT51
BM50
BJ46
BK46
BT41
BN37
BR39
BN39
SMBCLK
SMBDATA
SML0CLK
SML0DATA
SML1CLK/GPIO58
SML1DATA/GPIO75
RTCRST#
SRTCRST#
RTCX1
RTCX2
COUGARPOINT
COUGARPOINT
SMBALERT#/GPIO11
SML0ALERT#/GPIO60
SML1ALERT#/PCHHOT#/GPIO74
RTC
RTC
Rev=1.0
Rev=1.0
SPI
SPI
0901: Change PCH P/N directly to 0200-00J80IN
(ES2 C.S 908095 B0 QMZP BGA942 )
3
12
12
I
I
SR14
SR14
0
0
mx_r0402
mx_r0402
1 2
http://vinafix.vn
SMBALERT#_GPIO11
SML0ALERT#
SM1ALERT#_PCHHOT#_GPIO74
TP_SPI_CS1
PCH_SPI_CS0#
PCH_SPI_MOSI
PCH_SPI_CLK
12
I
I
SR7
SR7
2.7K
2.7K
mx_r0402
mx_r0402
12
NI
NI
SC3
SC3
150PF/50V
150PF/50V
NPO 5%
NPO 5%
mx_c0402
mx_c0402
1
+3P3VSB +3P3VSB+3P3VSB
12
I
I
SR16
SR16
10K
10K
mx_r0402
mx_r0402
12
I
I
SR17
SR17
2.2K
2.2K
mx_r0402
mx_r0402
8/25
+3P3V
12
NI
NI
SR19
SR19
1K
1K
mx_r0402
mx_r0402
ST24
ST24
1
SR23 0Imx_r0402SR23 0Imx_r0402
1 2
2
12
I
I
SR18
SR18
10K
10K
mx_r0402
mx_r0402
NOBOM
NOBOM
SR21 0Imx_r0402SR21 0Imx_r0402
1 2
SR22 0Imx_r0402SR22 0Imx_r0402
1 2
12
NI
NI
SC46
SC46
150PF/50V
150PF/50V
NPO 5%
NPO 5%
mx_c0402
mx_c0402
GND
<Variant Name>
<Variant Name>
<Variant Name>
PEGATRON DT-MB RESTRICTED SECRET
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
IPMSB-BE/CR
IPMSB-BE/CR
IPMSB-BE/CR
SPI_CS# 59
SPI_MOSI 59
SPI_MISO 59
SPI_CLK 59
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
1
PCI/SM/SPI/RTC 1-9
PCI/SM/SPI/RTC 1-9
PCI/SM/SPI/RTC 1-9
Livy_Zhu
Livy_Zhu
Livy_Zhu
19 83Friday, September 24, 2010
19 83Friday, September 24, 2010
19 83Friday, September 24, 2010
Rev
Rev
Rev
1.00
1.00
1.00
of
of
of
+3P3VSB +3P3VSB +3P3VSB
12
I
I
SR5
SR5
2.7K
2.7K
mx_r0402
mx_r0402
SMB_CLK_RESUME32,33,34,54
SMB_DATA_RESUME32,33,34,54
SML0_LAN_CLK35
B B
A A
SML0_LAN_DATA35
SML1_SIO_CLK59
SML1_SIO_DATA59
I
I
XY5
XY5
Crystal Holder
Crystal Holder
12
NI
NI
SC1
SC1
150PF/50V
150PF/50V
NPO 5%
NPO 5%
mx_c0402
mx_c0402
GNDGND
RTCRST#79
SRTCRST#79
8/17:change 18pF to 12pF
5
5
vinafix
D D
NOTE:
Used for for DMI, PCIe(PCIe 2.0 jitter spec compliant).
12
I
I
SR36
SR36
10K
10K
mx_r0402
mx_r0402
C C
PCI_PE1_RXN147
PCI bridge
9/6
B B
PCI-E x1 SLOT
9/6
USB 3.0
PCI-E x1 SLOT
LAN
A A
PCI_PE1_RXP147
PCI_PE1_TXN147
PCI_PE1_TXP147
IOH_PE2_RXN0_SATA351
IOH_PE2_RXP0_SATA351
IOH_PE2_TXN0_SATA351
IOH_PE2_TXP0_SATA351
PE1_RXN334
PE1_RXP334
PE1_TXN334
PE1_TXP334
USB3_PE1_RXN439
USB3_PE1_RXP439
USB3_PE1_TXN439
USB3_PE1_TXP439
PE1_RXN234
PE1_RXP234
PE1_TXN234
PE1_TXP234
LAN_PE1_RXN635
LAN_PE1_RXP635
LAN_PE1_TXN635
LAN_PE1_TXP635
5
GND GND
4
DMI_TXN011
DMI_TXP011
DMI_RXN011
DMI_RXP011
DMI_TXN111
DMI_TXP111
DMI_RXN111
DMI_RXP111
DMI_TXN211
DMI_TXP211
DMI_RXP211
DMI_TXN311
DMI_TXP311
DMI_RXN311
DMI_RXP311
12
I
I
SR37
SR37
10K
10K
mx_r0402
mx_r0402
NOTE:
trace length < 450 mils
4
3
I
I
SU1B
SU1B
D33
DMI0RXN
B33
DMI0RXP
J36
DMI0TXN
H36
DMI0TXP
A36
DMI1RXN
B35
DMI1RXP
P38
DMI1TXN
R38
DMI1TXP
B37
DMI2RXN
C36
DMI2RXP
H38
DMI2TXN
J38
DMI2TXP
E37
DMI3RXN
F38
DMI3RXP
M41
DMI3TXN
P41
DMI3TXP
+1P05V_PCH
12
I
I
SR30
SR30
49.9
49.9
1%
1%
mx_r0402
mx_r0402
DMICOMP
DMI2RBIAS
12
I
I
SR31
SR31
750
750
1%
1%
mx_r0402
mx_r0402
GND
CLKIN_DMI_N
CLKIN_DMI_P
P33
R33
B31
E31
A32
J20
L20
F25
F23
P20
R20
C22
A22
H17
J17
E21
B21
P17
M17
F18
E17
N15
M15
B17
C16
J15
L15
A16
B15
J12
H12
F15
F13
H10
J10
B13
D13
COUGARPOINT
COUGARPOINT
CLKIN_DMI_N
CLKIN_DMI_P
DMI
DMI
DMI_IRCOMP
DMI_ZCOMP
DMI2RBIAS
PCIE
PCIE
PERn1
PERp1
PETn1
PETp1
PERn2
PERp2
PETn2
PETp2
PERn3
PERp3
PETn3
PETp3
PERn4
PERp4
PETn4
PETp4
PERn5
PERp5
PETn5
PETp5
PERn6
PERp6
PETn6
PETp6
PERn7
PERp7
PETn7
PETp7
PERn8
PERp8
PETn8
PETp8
http://vinafix.vn
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
USB
USB
OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14
CLKIN_DOT_96N
CLKIN_DOT_96P
USBRBIAS#
USBRBIAS
3
BF36
BD36
BC33
BA33
BM33
BM35
BT33
BU32
BR32
BT31
BN29
BM30
BK33
BJ33
BF31
BD31
BN27
BR29
BR26
BT27
BK25
BJ25
BJ31
BK31
BF27
BD27
BJ27
BK27
BM43
BD41
BG41
BK43
BP43
BJ41
BT45
BM45
BD38
BF38
BP25
BM25
IPD 20K
IPD 20K
IPD 20K
IPD 20K
IPD 20K
IPD 20K
IPD 20K
IPD 20K
IPD 20K
IPD 20K
IPD 20K
IPD 20K
IPD 20K
IPD 20K
IPD 20K
IPD 20K
IPD 20K
IPD 20K
IPD 20K
IPD 20K
IPD 20K
IPD 20K
IPD 20K
IPD 20K
IPD 20K
IPD 20K
IPD 20K
IPD 20K
Native Sus
Native Sus
Native Sus
Native Sus
Native Sus
Native Sus
Native Sus
Native Sus
CLKIN_DOT_96N
CLKIN_DOT_96P
USBRBIAS
GND
12
USBN0 49
USBP0 49
USBN1 49
USBP1 49
USBN2 48
USBP2 48
USBN3 48
USBP3 48
USBN4 49DMI_RXN211
USBP4 49
USBN5 49
USBP5 49
TP_BK33
TP_BJ33
TP_BF31
TP_BD31
USBN8 77
USBP8 77
USBN9 77
USBN10_R
USBP10_R
USBN11_RUSBN11_R
USBP11_R
USBP9 77
TP_BF27
1
TP_BD27
1
TP_BJ27
1
TP_BK27
1
For BE: Front USB Header
For CR: LAN+USB
OC01# 49
OC23# 48
OC45# 49
OC89# 77
OC7#/GPIO14
OC1011# 40,48
NOTE:
Used for integrated graphics, generate USB backbone,
24MHz HDA bit, and 48MHz clock.
I
I
SR35
SR35
22.6
22.6
1%
1%
mx_r0402
mx_r0402
NOTE:
trace length < 200 mils
2
1
1
1
1
PS2+USB
ST167
ST167
NOBOM
NOBOM
ST168
ST168
NOBOM
NOBOM
ST165
ST165
NOBOM
NOBOM
ST166
ST166
NOBOM
NOBOM
12
I
I
SR34
SR34
10K
10K
mx_r0402
mx_r0402
GND GND
2
1
USB ports 6,7,12,13 are disabled for H61
Front USB Header
ST33
ST33
NOBOM
NOBOM
ST34
ST34
NOBOM
NOBOM
ST49
ST49
NOBOM
NOBOM
ST87
ST87
NOBOM
NOBOM
RN21A
5% IRN21A
5% I
RN21B
5% IRN21B
5% I
RN23B
5% NIRN23B
5% NI
RN23A
5% NIRN23A
5% NI
RN22A
5% IRN22A
5% I
RN22B
5% IRN22B
5% I
RN24B
5% NIRN24B
5% NI
RN24A
5% NIRN24A
5% NI
+3P3VSB+3P3VSB+3P3VSB
12
I
I
SR32
SR32
10K
10K
mx_r0402
mx_r0402
Engineer:
Engineer:
Engineer:
IPMSB-BE/CR
IPMSB-BE/CR
IPMSB-BE/CR
USBN10_F 48
USBP10_F 48
USBN10_B 41
USBP10_B 41
USBN11_F 48
USBP11_F 48
USBN11_B 41
USBP11_B 41
Title :
Title :
Title :
1
PCIE/USB/DMI 2-9
PCIE/USB/DMI 2-9
PCIE/USB/DMI 2-9
12
I
I
SR33
SR33
10K
10K
mx_r0402
mx_r0402
1 2
0Ohm
0Ohm
3 4
0Ohm
0Ohm
3 4
0Ohm
0Ohm
1 2
0Ohm
0Ohm
1 2
0Ohm
0Ohm
3 4
0Ohm
0Ohm
3 4
0Ohm
0Ohm
1 2
0Ohm
0Ohm
12
I
I
SR42
SR42
10K
10K
mx_r0402
mx_r0402
12
I
I
SR40
SR40
10K
10K
mx_r0402
mx_r0402
<Variant Name>
<Variant Name>
<Variant Name>
PEGATRON DT-MB RESTRICTED SECRET
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
Livy_Zhu
Livy_Zhu
Livy_Zhu
20 83Friday, September 24, 2010
20 83Friday, September 24, 2010
20 83Friday, September 24, 2010
of
of
of
Rev
Rev
Rev
1.00
1.00
1.00
5
4
3
2
1
B
1
B
1
NI
NI
SR45
SR45
10K
10K
mx_r0402
mx_r0402
I
I
SR88
SR88
10K
10K
mx_r0402
mx_r0402
HD_LED# 58
A20GATE 53
RST_KB# 53
SERIRQ 53
H_THMTRIP# 12
PECI_PCH 12
PM_SYNC 12
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
1
+3P3V
12
I
I
SR46
SR46
10K
10K
mx_r0402
mx_r0402
CATERR#_GPI
3
3
C
C
I
I
PQ28
PQ28
PMBS3904
PMBS3904
E
E
2
2
12
NI
NI
SR48
SR48
10K
10K
mx_r0402
mx_r0402
12
I
I
SR85
SR85
10K
10K
mx_r0402
mx_r0402
GPIO49
GPIO16
01.00
01.01
TPM_SERIRQ 55
SATA/HOST/FAN 3-9
SATA/HOST/FAN 3-9
SATA/HOST/FAN 3-9
Livy_Zhu
Livy_Zhu
Livy_Zhu
21 83Friday, September 24, 2010
21 83Friday, September 24, 2010
21 83Friday, September 24, 2010
of
of
of
0
1
Rev
Rev
Rev
1.00
1.00
1.00
vinafix
D D
PWROK22,52
C C
USB3_SMI#39
SIO_SMI#52
BIOS_CONF180
B B
Board ID
GPIO21BEGPIO48 GPIO39 GPIO38
NOTE:
+3P3V
12
SR40 SR41
INI
NI I
SR41 0Imx_r0402SR41 0Imx_r0402
12
I
I
I
I
SR49
SR49
SR50
SR50
10K
10K
10K
10K
mx_r0402
mx_r0402
mx_r0402
mx_r0402
R_FAN_INITIAL57
F_FAN_INITIAL56
1 2
12
SR52
SR52
10K
10K
mx_r0402
mx_r0402
+3P3V +3P3V +3P3V
GND GND GND
I
I
12
12
+3P3V+3P3V
12
NI
NI
SR55
SR55
10K
10K
mx_r0402
mx_r0402
I
I
SR56
SR56
10K
10K
mx_r0402
mx_r0402
Description
iAMT
non iAMT
I
I
SR47
SR47
10K
10K
mx_r0402
mx_r0402
12
NI
NI
SR64
SR64
10K
10K
mx_r0402
mx_r0402
12
I
I
SR57
SR57
10K
10K
mx_r0402
mx_r0402
0000
12
NI
NI
SR65
SR65
10K
10K
mx_r0402
mx_r0402
12
I
I
SR58
SR58
10K
10K
mx_r0402
mx_r0402
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
GND
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
GND GND
ST21
ST21
ST22
ST22
ST23
ST23
NI
NI
12
SC30
SC30
100PF/50V
100PF/50V
NPO 5%
NPO 5%
mx_c0402
mx_c0402
ST38
ST38
ST39
ST39
ST25
ST25
ST44
ST44
CATERR#_GPI
12
I
I
SR38
SR38
10K
10K
mx_r0402
mx_r0402
TP_CL_CLK1
1
TP_CL_DATA1
1
TP_CL_RST1#
1
TP_SU1_PWM0
1
TP_SU1_PWM1
1
TP_SU1_PWM2
1
TP_SU1_PWM3
1
GND
Board_ID_0
Board_ID_1
Board_ID_2
12
I
I
SR39
SR39
10K
10K
mx_r0402
mx_r0402
+3P3V+3P3V
12
Native Core
Native Core
12
NI
NI
SC31
SC31
220PF/50V
220PF/50V
X7R 10%
X7R 10%
mx_c0402
mx_c0402
IPU 32/ IPD 100
IPU 32/ IPD 100
PCH_MEPWROK
I
I
SR51
SR51
10K
10K
mx_r0402
mx_r0402
GPI Core
GPI Core
GPI Core
GPI Core
GPI Core
GPI Core
SST
CLKIN_SATA_N
CLKIN_SATA_P
IPU 20K
IPU 20K
IPU 20K
IPU 20K
IPU 20K
IPU 20K
IPU 20K
IPU 20K
IPD 10K
GPI Core
GPI Core
GPI Core
GPI Core
CR0001
A A
5
4
http://vinafix.vn
BA50
BF50
BF49
BC46
BN21
BT21
BM20
BN19
BT17
BR19
BA22
BR16
BU16
BM18
BN17
BP15
BC43
BA53
BE54
BF55
AW53
AF55
AG56
AY20
I
I
SU1C
SU1C
COUGARPOINT
COUGARPOINT
CLINK
CLINK
CL_CLK1
CL_DATA1
CL_RST1#
APWROK
FAN
FAN
PWM0
PWM1
PWM2
PWM3
TACH0/GPIO17
TACH1/GPIO1
TACH2/GPIO6
TACH3/GPIO7
TACH4/GPIO68
TACH5/GPIO69
TACH6/GPIO70
TACH7/GPIO71
SST
GPIO
GPIO
SCLOCK/GPIO22
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
CLKIN_SATA_N
CLKIN_SATA_P
NC_1
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATA0GP/GPIO21
SATA1GP/GPIO19
SATA2GP/GPIO36
SATA3GP/GPIO37
SATA4GP/GPIO16
SATA5GP/GPIO49
SATAICOMPI
SATAICOMPO
SATA3COMPI
SATA3RCOMPO
SATALED#
TP16
SATA3RBIAS
HOST
HOST
A20GATE
INIT3_3V#
RCIN#
SERIRQ
THRMTRIP#
PECI
PMSYNCH
3
AC56
AB55
AE46
AE44
AA53
AA56
AG49
AG47
AL50
AL49
AL56
AL53
AN46
AN44
AN56
AM55
AN49
AN50
AT50
AT49
AT46
AT44
AV50
AV49
BC54
AY52
BB55
BG53
AU56
BA56
AJ55
AJ53
AE54
AE52
BF57
AE50
AC52
BB57
BN56
BG56
AV52
E56
H48
F55
GPI Core
GPI Core
GPI Core
GPI Core
GPI Core
GPI Core
NOTE:
trace length
< 500 mils
SATAICOMP
SATA3COMP
SATA3RBIAS
IPU 20K
IPD 0.35K
Board_ID_3
SATA1GP_GPIO19
IPU 20K
SATA2GP_GPIO36
IPD 20K
SATA3GP_GPIO37
IPD 20K
FAB_ID_0
FAB_ID_1
+1P05V_PCH
NOTE:
trace length < 450 mils
12
I
I
SR70
SR70
750
750
1%
1%
mx_r0402
mx_r0402
+1P05V_CPUIO
GND
INIT3_3V#
12
NI
NI
SR74
SR74
1K
1K
mx_r0402
mx_r0402
GND
12
I
I
SR66
SR66
37.4
37.4
1%
1%
mx_r0402
mx_r0402
GND
SATA_RXN0 50
SATA_RXP0 50
SATA_TXN0 50
SATA_TXP0 50
SATA_RXN1 50
SATA_RXP1 50
SATA_TXN1 50
SATA_TXP1 50
SATA_RXN4 50
SATA_RXP4 50
SATA_TXN4 50
SATA_TXP4 50
SATA_RXN5 50
SATA_RXP5 50
SATA_TXN5 50
SATA_TXP5 50
EDS 1.0 SATA2GP/SATA3GP should not
be pulled high when strap is sampled.
SR61 10KImx_r0402SR61 10KImx_r0402
SR62 10KImx_r0402SR62 10KImx_r0402
SR63 10KImx_r0402SR63 10KImx_r0402
+1P05V_PCH
12
I
I
SR67
SR67
49.9
49.9
1%
1%
mx_r0402
mx_r0402
12
12
12
NOTE:
trace length < 500 mils
+3P3V
+3P3V
12
NI
NI
HR19
HR19
51
51
mx_r0402
mx_r0402
NI
NI
12
HC8
HC8
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0402
mx_c0402
12
12
NI
NI
SR113
SR113
I
I
SR73
SR73
10K
10K
10K
10K
mx_r0402
mx_r0402
mx_r0402
mx_r0402
12
NI
NI
O2C23
O2C23
0.1UF/16V
0.1UF/16V
mx_c0402
mx_c0402
GND
2
+1P05V_CPUIO
12
SR83
SR83
51
51
I
I
mx_r0402
mx_r0402
CATERR#_BASE
NI
NI
12
HC10
HC10
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
mx_c0402
GND
mx_c0402
+3P3V
12
I
I
SR68
SR68
10K
10K
mx_r0402
mx_r0402
+3P3V
GND
CATERR#12,79
+3P3V
GND GNDGND
12
SR60
SR60
10K
10K
mx_r0402
mx_r0402
12
I
I
SR82
SR82
10K
10K
mx_r0402
mx_r0402
NI
NI
+3P3V +3P3V
12
12
Fab.ID
SIOD5
+3P3V
12
SIOD5
NI
NI
SR114
SR114
10K
10K
mx_r0402
mx_r0402
<Variant Name>
<Variant Name>
<Variant Name>
PEGATRON DT-MB RESTRICTED SECRET
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
2
3
1
BAT54AW
BAT54AW
NI
NI
mx_r0402
mx_r0402
0
1 2
1 2
0
SR43
SR43
mx_r0402
mx_r0402
0
0
SR44
SR44
IPMSB-BE/CR
IPMSB-BE/CR
IPMSB-BE/CR
NI
NI
I
I
5
vinafix
NI
NI
+3P3V
SR80
+3P3V
12
NI
D D
LDREQ#53
LFRAME#53,55,80
HDA_SYNC
NOTE:
NI
SR81
SR81
10K
10K
mx_r0402
mx_r0402
On-die PLL VR voltage selector.
Hi: supplied by 1.5V.
Low: supplied by 1.8V.
HDA_SDO
NOTE:
8/28:deletet JE50
AZ_SDATA_IN043
Disable ME in Manufacturing Mode
--> connect to GND.
C C
AZ_SDATA_OUT_143
AZ_SYNC_143
AZ_BITCLK_143
AZ_RST#_143
12
NI
NI
SC33
SC33
10PF/50V
10PF/50V
NPO 5%
NPO 5%
mx_c0402
mx_c0402
BIOS_CONF280
12
NI
NI
SC22
SC22
12PF/50V
12PF/50V
NPO 5%
NPO 5%
mx_c0402
mx_c0402
8/17:NI
NOTE:
For platform not supporting deep
B B
sleep connect directly to RSMRST#.
The DSW rails must be stable for at least 10 ms
before DPWROK is asserted to PCH.
CPUPWRGD12,69,82
DRAM_PWROK12
PWROK21,52
VRM_PWRGD69,73,82
SYS_RESET_DBR#12,82,83
RSMRST#15,52,83
PCH_DPWROK28,83
A A
12
GND
PLTRST#15,35,53,55,80,82,83
SLP_SUS28,67
I
I
SR104
SR104
100K
100K
mx_r0402
mx_r0402
5
12
1 2
12
I
NI
NI
SC40
SC40
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
I
I
SR169
SR169
10K
10K
mx_r0402
mx_r0402
I
SR97
SR97
100K
100K
mx_r0402
mx_r0402
GND GNDGND
SR98 0Imx_r0402SR98 0Imx_r0402
1 2
SR99 0Imx_r0402SR99 0Imx_r0402
1 2
SR137 0Imx_r0402SR137 0Imx_r0402
1 2
RSMRST_CUTOFF
SR80
10K
10K
mx_r0402
mx_r0402
1 2
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
1 2
I
I
R_SDATAOUT
mx_r0402 SR53 22 OHM
mx_r0402
mx_r0402 SR54 33
mx_r0402
mx_r0402 SR59 33
mx_r0402
12
NI
NI
SC23
SC23
12PF/50V
12PF/50V
NPO 5%
NPO 5%
mx_c0402
mx_c0402
GNDGND
+1P5V_DUAL
I
I
SR90
SR90
200 Ohm
200 Ohm
5%
5%
1 2
LDRQ1#_GPIO23
LAD053,55,80
LAD153,55,80
LAD253,55,80
LAD353,55,80
ST36
ST36
ST37
ST37
ST32
ST32
+3P3VSB
NI
NI
BR81K
SR53 22 OHM
I
I
SR54 33
I
I
SR59 33
I
I
12
GNDGND
1
1
1
1 2
I
I
1 2
1 2
1 2
NI
NI
SC32
SC32
10PF/50V
10PF/50V
NPO 5%
NPO 5%
mx_c0402
mx_c0402
TBD: Both are 390Kohm in CRB 0.7
+3P3V
NI
NI
12
SC41
SC41
100PF/50V
100PF/50V
NPO 5%
NPO 5%
mx_c0402
mx_c0402
12
GND
I
I
SQ8
SQ8
PMBS3904
PMBS3904
NI
NI
SC29
SC29
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
1
1
12
NI
NI
SR144
SR144
10K
10K
mx_r0402
mx_r0402
12
NI
NI
SC83
SC83
0.01UF/25V
0.01UF/25V
3
3
X7R 10%
X7R 10%
C
C
B
B
E
E
2
2
GND
GND
mx_r0402BR81K
mx_r0402
SR69 22 OHM
SR69 22 OHM
4
TP_PCH_SDIN1
TP_PCH_SDIN2
TP_PCH_SDIN3
SR1771K
mx_r0402
mx_r0402
1 2
PCH_JTAG_TMS83
PCH_JTAG_TDO83
PCH_JTAG_TDI83
PCH_JTAG_TCK83
PCH_JTAG_RST83
+BATT +BATT
I
I
SR92
SR92
390K
390K
1 2
PCH_SYS_RESET#
PCH_DPOWEROK
12
NI
NI
SR93
SR93
1K
1K
GND
mx_r0402
mx_r0402
GND
4
Native CoreIPU 20K
IPU 20K
IPU 20K
IPU 20K
IPU 20K
IPU 20K
IPD 20K
IPD 20K
IPD 20K
IPD 20K
mx_r0402SR1771K
mx_r0402
HDA_SYNC_R
HDA_BITCLK_R
HDA_AZRST#_R
IPU 20K
IPU 20K
IPD 20K
12
GND
I
I
SR94
SR94
390K
390K
1 2
DSWVRMEN
PCH_INTVRMEN
12
NI
NI
SC42
SC42
100PF/50V
100PF/50V
NPO 5%
NPO 5%
mx_c0402
mx_c0402
GND
3
I
I
SU1D
SU1D
LPC
BA20
BK15
BG20
BK17
BG17
BD22
BK22
IPD 20K
BT23
IPD 20K
BP23
BU22
BC22
BC50
BC52
BA43
BC49
NI
NI
SR106
SR106
10K
10K
mx_r0402
mx_r0402
BG46
BR42
BN41
BK48
BE52
BK38
BT37
12
NI
NI
SC39
SC39
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
12
I
I
SR95
SR95
GND
100K
100K
mx_r0402
mx_r0402
LPC
LDRQ1#/GPIO23
FWH0/LAD0
BJ17
FWH1/LAD1
BJ20
FWH2/LAD2
FWH3/LAD3
LDRQ0#
FWH4/LFRAME#
AUDIO
AUDIO
HDA_SDIN0
BF22
HDA_SDIN1
HDA_SDIN2
BJ22
HDA_SDIN3
HDA_SDO
HDA_SYNC
HDA_BCLK
HDA_RST#
SUSWARN#/SUSPWRDNACK/GPIO30
JTAG_TMS
BF47
JTAG_TDO
JTAG_TDI
JTAG_TCK
TP12
D53
PROCPWRGD
DRAMPWROK
BJ38
PWROK
BJ53
SYS_PWROK
DSWVRMEN
INTVRMEN
PLTRST#
SYS_RESET#
RSMRST#
DPWROK
COUGARPOINT
COUGARPOINT
http://vinafix.vn
BMBUSY#/GPIO0
CLKRUN#/GPIO32
HDA_DOCK_EN#/GPIO33
STP_PCI#/GPIO34
GPIO35
LAN_PHY_PWR_CTRL/GPIO12
HDA_DOCK_RST#/GPIO13
PCIECLKRQ2#/GPIO20
PCIECLKRQ5#/GPIO44
PCIECLKRQ6#/GPIO45
PCIECLKRQ7#/GPIO46
GPIO8
GPIO15
GPIO24/MEM_LED
GPIO28
SLP_LAN#/GPIO29
GPIO27
GPIO31
GPIO57
BATLOW#/GPIO72
SUSACK#
SUSCLK/GPIO62
SUS_STAT#/GPIO61
WAKE#
INTRUDER#
SPKR
PWRBTN#
SLP_S3#
SLP_S4#
SLP_S5#/GPIO63
SLP_A#
SLP_SUS#
3
RI#
AW55
BC56
BC25
BL56
BJ57
BP51
BK50
BA25
BM55
BP53
BJ55
BH49
BJ43
BG43
AV43
BL54
AV44
BP55
BT53
IPU 20K
AV46
BU46
BP45
BA47
BN54
BJ48
BC44
BM38
BE56
BT43
BM53
BN52
BH50
BC41
BD43
GPI Core
GPO Core
GPO Core
GPI Core
GPO Core
GPO Sus
Native Sus
GPI Sus
GPO Sus
GPO Sus
GPO Sus
GPI Sus
GPI DSW
GPI DSW
Native Core
Native Sus
Native Sus
Native Sus
GPI Sus
Native Sus
GPI DSW
IPU TBD
Native Sus
Native Sus
+3P3VSB
12
I
I
SR75
SR75
10K
10K
mx_r0402
mx_r0402
RI
INTRUDER#
IPD 20K
IPU 20K
Native Sus
IPU 20K
IPD 20K
IPU 20K
IPU 20K
IPD TBD
IPU TBD
IPU 20K
IPU 20K
GND
12
GND
+3P3V +3P3VSB +3P3VA
STP_PCI#_GPIO34
GPIO27
GPIO31
PCIECLKRQ5#_GPIO44
PCIECLKRQ6#_GPIO45
PCIECLKRQ7#_GPIO46
+3P3VSB
BATLOW#_GPIO72
PCH_SUSWARN#
SR158 0Imx_r0402SR158 0Imx_r0402
PCH_SUSACK#
SUSCLK_GPIO62
SUS_STAT#
12
NI
NI
SR183
SR183
1K
1K
mx_r0402
mx_r0402
GND
12
NI
NI
SC28
SC28
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
PCH_PWRBTN#
PCH_PWRBTN#
NI
NI
SC25
SC25
0.1UF/16V
0.1UF/16V
TP_PCH_SLP_S5#
TP_PCH_SLP_A#
X7R 10%
X7R 10%
12
I
I
SR100
SR100
10K
10K
mx_r0402
mx_r0402
12
12
NI
NI
SR124
SR124
10K
10K
mx_r0402
mx_r0402
1 2
NI
NI
12
SC47
SC47
10PF/50V
10PF/50V
NPO 5%
NPO 5%
mx_c0402
mx_c0402
08/11
+3P3VSB
12
NI
NI
SR116
SR116
10K
10K
+3P3VA
12
LPCPD# 55
GND
ST35
ST35
1
ST50
ST50
1
2
+3P3V
12
12
I
I
SR115
SR115
1K
1K
mx_r0402
mx_r0402
NI
NI
SR142
SR142
10K
10K
SR141 1KImx_r0402SR141 1KImx_r0402
SR256 1KImx_r0402SR256 1KImx_r0402
SR180 1KImx_r0402SR180 1KImx_r0402
12
NI
NI
SR143
SR143
10K
10K
1 2
1 2
1 2
I
I
SR105
SR105
10K
10K
mx_r0402
mx_r0402
GND
12
NI
NI
SR195
SR195
1K
1K
mx_r0402
mx_r0402
12
I
I
SR103
SR103
10K
10K
mx_r0402
mx_r0402
12
GND
TBD
+3P3V+BATT +3P3VSB
12
NI
NI
SR78
SR78
1K
1K
mx_r0402
mx_r0402
GND
NI
NI
SR159
SR159
10K
10K
mx_r0402
mx_r0402
NI
NI
12
SC45
SC45
10PF/50V
10PF/50V
NPO 5%
NPO 5%
mx_c0402
mx_c0402
12
I
I
SR76
SR76
1M
1M
mx_r0402
mx_r0402
8/24
12
GND
12
P_LED2 58
NOTE:
NI
NI
SC72
SC72
0.1UF/16V
0.1UF/16V
PIN HIGH LOW DESCRIPTION
X7R 10%
X7R 10%
mx_c0402
mx_c0402
GPIO8
GPIO15
GPIO28
I
I
SR77
SR77
1K
1K
mx_r0402
mx_r0402
8/17:delete reserved PWRBTN#
SLP_S3# 52,63,66
SLP_S4# 52,63,69
NOBOM
NOBOM
NOBOM
NOBOM
SLP_SUS# 28,61
2
PEGATRON DT-MB RESTRICTED SECRET
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
12
I
I
SR109
SR109
10K
10K
mx_r0402
mx_r0402
12
I
I
SR110
SR110
10K
10K
mx_r0402
mx_r0402
8/28：deltet OV
F_AUDIO_DET# 45
AUDIO_DISABLE 43
ST172
ST172
1
1
NOBOM
NOBOM
ST173
ST173
NOBOM
NOBOM
MUTE# 44
LAN_DISABLE# 35
LPC_PME# 52
FRONTFAN_34PIN 56
SLP_LAN# 70
NOTE:
I
I
SR101
SR101
100K
100K
mx_r0402
mx_r0402
GPIO27 can be configured as wake input
to allow wakes from Deep Sleep.
NOTE:
External PU resistor required
if used for CLKREQ# functionality.
SERIAL_POST 80
REARFAN_34PIN 57
NOTE:
SUSACK# and SUSWARN#
can be tied together if EC/SIO
does not want to involve in
SUS_WARN# 28
SUS_ACK# 28
the handshake mechanism
for the Deep Sleep state
entry and exit.
BTM FCIM Clock validation
Enable Disable TLS confidentiality
Enable Disable On-Die PLL VR
PCH_RI# 38
WAKE# 32,34,39,47
12
I
I
SC13
SPKR 43,44,79,80
SB_PWRBTN# 52SYS_RESET#52,58
IPMSB-BE/CR
IPMSB-BE/CR
IPMSB-BE/CR
SC13
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
1
AUDIO/LPC/MISC 4-9
AUDIO/LPC/MISC 4-9
AUDIO/LPC/MISC 4-9
Livy_Zhu
Livy_Zhu
Livy_Zhu
22 83Friday, September 24, 2010
22 83Friday, September 24, 2010
22 83Friday, September 24, 2010
Rev
Rev
Rev
1.00
1.00
1.00
5
vinafix
D D
NOTE:
DDP[B..D]_HPD are 3.3V tolerant.
C C
DDPB_HPD_DVI31
CRB 0.7 do not implement.
+3P3V
12
VGA_DDCA_CLK30
VGA_DDCA_DATA30
I
I
SR79
SR79
1M
1M
mx_r0402
mx_r0402
ST72
ST72
NOBOM
NOBOM
ST73
ST73
NOBOM
NOBOM
SDVO_CTRL_CLK31
SDVO_CTRL_DATA31
4
TP_PCH_DDPBAUXP
1
TP_PCH_DDPBAUXN
1
12
GND
IPD 20K
NI
NI
SR120
SR120
1K
1K
mx_r0402
mx_r0402
AB18
AB17
AW3
AW1
AL15
AL17
Y18
Y17
R8
R9
T1
I
I
SU1E
SU1E
TP6
TP7
TP8
TP9
CRT_DDC_CLK
CRT_DDC_DATA
DDPB_AUXP
DDPB_AUXN
SDVO_CTRLCLK
SDVO_CTRLDATA
DDPB_HPD
CRT_HSYNC
CRT_VSYNC
CRT_RED
CRT_GREEN
CRT_BLUE
DAC_IREF
CRT_IRTN
DDPB_0P
DDPB_0N
DDPB_1P
DDPB_1N
DDPB_2P
DDPB_2N
DDPB_3P
DDPB_3N
SDVO_INTP
SDVO_INTN
SDVO_STALLP
SDVO_STALLN
SDVO_TVCLKINP
SDVO_TVCLKINN
AR4
AR2
AN6
AN2
AM1
AT3
AM6
R14
R12
M11
M12
H8
K8
L5
M3
U2
T3
W3
U5
U8
U9
3
VGA_HSYNC_3P3V
VGA_VSYNC_3P3V
VGA_RED_S
VGA_GREEN_S
VGA_BLUE_S
DACREFSET
IPD 50
IPD 50
IPD 50
IPD 50
IPD 50
IPD 50
GND
SDVO_INTP
SDVO_INTN
SR245 33Imx_r0402SR245 33Imx_r0402
1 2
SR246 33Imx_r0402SR246 33Imx_r0402
1 2
12
I
I
SR247
SR247
150
150
1%
1%
mx_r0402
mx_r0402
GND GND GND
12
I
I
SR248
SR248
150
150
1%
1%
mx_r0402
mx_r0402
12
I
I
Replace DACREFSET resistor
SR131
SR131
1K
1K
close to PCH within 500mils
1%
1%
mx_r0402
mx_r0402
GND
ST78
ST78
1
1
ST79
ST79
NOBOM
NOBOM
NOBOM
NOBOM
12
I
I
SR249
SR249
150
150
1%
1%
mx_r0402
mx_r0402
2
JP20 SHORT_PIN
JP20 SHORT_PIN
1 2
JP21 SHORT_PIN
JP21 SHORT_PIN
1 2
JP22 SHORT_PIN
JP22 SHORT_PIN
1 2
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOTE:
Place RGB resistors close to PCH within 250mils
DVI_TMDSB_DATA0 31
DVI_TMDSB_DATA0# 31
DVI_TMDSB_DATA1 31
DVI_TMDSB_DATA1# 31
DVI_TMDSB_DATA2 31
DVI_TMDSB_DATA2# 31
DVI_TMDSB_CLK 31
DVI_TMDSB_CLK# 31
DVI
1
VGA_HSYNC 30
VGA_VSYNC 30
VGA_RED 30
VGA_GREEN 30
VGA_BLUE 30
TP_PCH_DDPCAUXP
ST84
ST84
ST83
ST83
ST86
ST86
ST85
ST85
ST76
ST76
ST77
ST77
ST89
ST89
ST88
ST88
1
1
1
1
1
1
1
1
TP_PCH_DDPCAUXN
TP_PCH_DDPC_CTRLCLK
TP_PCH_DDPC_CTRLDATA
TP_PCH_DDPDAUXP
TP_PCH_DDPDAUXN
TP_PCH_DDPD_CTRLCLK
TP_PCH_DDPD_CTRLDATA
GND
GND
12
I
I
SR121
SR121
1K
1K
mx_r0402
mx_r0402
12
I
I
SR122
SR122
1K
1K
mx_r0402
mx_r0402
4
IPD 20K
IPD 20K
U14
DDPC_AUXP
U12
DDPC_AUXN
AL12
DDPC_CTRLCLK
AL14
DDPC_CTRLDATA
N2
DDPC_HPD
N6
DDPD_AUXP
R6
DDPD_AUXN
AL9
DDPD_CTRLCLK
AL8
DDPD_CTRLDATA
M1
DDPD_HPD
COUGARPOINT
COUGARPOINT
DDPC_0P
DDPC_0N
DDPC_1P
DDPC_1N
DDPC_2P
DDPC_2N
DDPC_3P
DDPC_3N
DDPD_0P
DDPD_0N
DDPD_1P
DDPD_1N
DDPD_2P
DDPD_2N
DDPD_3P
DDPD_3N
L2
J3
G2
G4
F3
F5
E4
E2
D5
B5
C6
D7
B7
C9
E11
B11
http://vinafix.vn
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
B B
A A
5
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
3
TP_PCH_L2
TP_PCH_J3
TP_PCH_G2
TP_PCH_G4
TP_PCH_F3
TP_PCH_F5
TP_PCH_E4
TP_PCH_E2
TP_PCH_D5
TP_PCH_B5
TP_PCH_C6
TP_PCH_D7
TP_PCH_B7
TP_PCH_C9
TP_PCH_E11
TP_PCH_B11
ST90
ST90
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ST93
ST93
ST94
ST94
ST102
ST102
ST103
ST103
ST104
ST104
ST130
ST130
ST139
ST139
ST146
ST146
ST147
ST147
ST141
ST141
ST140
ST140
ST143
ST143
ST142
ST142
ST145
ST145
ST144
ST144
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
<Variant Name>
<Variant Name>
<Variant Name>
PEGATRON DT-MB RESTRICTED SECRET
VGA/DP/HDMI 5-9
VGA/DP/HDMI 5-9
VGA/DP/HDMI 5-9
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet
Date: Sheet
2
Date: Sheet
IPMSB-BE/CR
IPMSB-BE/CR
IPMSB-BE/CR
Engineer:
Livy_Zhu
Livy_Zhu
Livy_Zhu
23 83Friday, September 24, 2010
23 83Friday, September 24, 2010
1
23 83Friday, September 24, 2010
Rev
Rev
Rev
1.00
1.00
1.00
of
of
of
5
vinafix
D D
NVR_CLE12
C C
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
FDI_TXN011
FDI_TXP011
FDI_TXN111
FDI_TXP111
FDI_TXN211
FDI_TXP211
FDI_TXN311
FDI_TXP311
FDI_TXN411
FDI_TXP411
FDI_TXN511
FDI_TXP511
FDI_TXN611
FDI_TXP611
FDI_TXN711
FDI_TXP711
ST91
ST91
ST92
ST92
ST95
ST95
ST96
ST96
ST97
ST97
ST98
ST98
ST99
ST99
ST100
ST100
ST101
ST101
NOTE:
CLKIN_BCLK(CLKIN_GND0): Optional(BTM usage)
CLKIN_DMI2(CLKIN_GND1): Optional(BTM usage)
I
I
SR125
SR125
10K
10K
mx_r0402
mx_r0402
Y12_R
12
I
I
SR126
SR126
10K
10K
mx_r0402
mx_r0402
I
I
SR140
SR140
1M
1M
mx_r0603_h24
mx_r0603_h24
1 2
I
I
Y12
Y12
25Mhz
25Mhz
12
12
12
I
I
SR127
SR127
10K
10K
mx_r0402
mx_r0402
GND
GND
3
3
12
I
I
SC56
SC56
27PF/50V
27PF/50V
NPO 5%
NPO 5%
mx_c0402
mx_c0402
B B
12
I
I
SR157
SR157
10K
10K
mx_r0402
mx_r0402
GND
A A
5
12
GND GND GND GND
I
I
SR149
SR149
0
0
1 2
mx_r0402
mx_r0402
12
I
I
SC55
SC55
27PF/50V
27PF/50V
NPO 5%
NPO 5%
mx_c0402
mx_c0402
GND GND GND
4
TP_NVR_RB#_Y41
1
TP_NVR_RE#_WRB0_M50
1
TP_NVR_WE#_CK1_J57
1
TP_NVR_CE#3_G56
1
TP_NVR_CE#2_AB46
1
TP_NVR_CE#1_K49
1
TP_NVR_CE#0_K50
1
1
1
12
TP_NVR_DQS0_Y44
TP_NVR_DQS1_L53
+1P05V_PCH
12
PCH_CLKIN_BCLK_GND0#
PCH_CLKIN_BCLK_GND0
PCH_CLKIN_DMI2_GND1#
PCH_CLKIN_DMI2_GND1
I
I
SR128
SR128
10K
10K
mx_r0402
mx_r0402
REFCLK14IN
XTAL_25M_PCH_IN
XTAL_25M_PCH_OUT
4
IPD 20K
IPD 20K
IPU 600
I
I
SR136
SR136
90.9
90.9
1%
1%
mx_r0402
mx_r0402
XCLK_RCOMP
3
I
I
SU1F
SU1F
C42
M43
M48
M50
M49
G56
AB46
W53
AN8
B43
F45
F43
H41
C46
D47
B45
A46
B47
C49
H43
P43
R47
Y41
U43
K49
K50
Y44
L53
AL2
V52
R27
P27
AJ3
AJ5
H31
C29
E29
L27
F28
E27
L25
C26
B27
L22
B25
D25
J41
J43
J57
J31
J27
J25
J22
FDI_RXN0
FDI_RXP0
FDI_RXN1
FDI_RXP1
FDI_RXN2
FDI_RXP2
FDI_RXN3
FDI_RXP3
FDI_RXN4
FDI_RXP4
FDI_RXN5
FDI_RXP5
FDI_RXN6
FDI_RXP6
FDI_RXN7
FDI_RXP7
Reserved_001
DF_TVS
Reserved_002
Reserved_003
Reserved_004
Reserved_005
Reserved_006
Reserved_007
Reserved_008
Reserved_009
Reserved_010
Reserved_011
Reserved_012
XCLK_RCOMP
CLKIN_GND0_N
CLKIN_GND0_P
CLKIN_GND1_N
CLKIN_GND1_P
REFCLK14IN
XTAL25_IN
XTAL25_OUT
TP21
TP25
TP29
TP33
TP22
TP26
TP30
TP34
TP23
TP27
TP31
TP35
TP24
TP28
TP32
TP36
COUGARPOINT
COUGARPOINT
CLOCK
CLOCK
FDI_FSYNC0
FDI_LSYNC0
FDI_FSYNC1
FDI_LSYNC1
FDI
FDI
RSD
RSD
Reserved_013
Reserved_014
Reserved_015
Reserved_016
Reserved_017
Reserved_018
Reserved_019
Reserved_020
Reserved_021
Reserved_022
Reserved_023
Reserved_024
Reserved_025
Reserved_026
Reserved_027
Reserved_028
Reserved_029
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKOUT_DP_N
CLKOUT_DP_P
CLKOUT_PCIE7N
CLKOUT_PCIE7P
CLKOUT_PCIE6N
CLKOUT_PCIE6P
CLKOUT_PCIE5N
CLKOUT_PCIE5P
CLKOUT_PCIE4N
CLKOUT_PCIE4P
CLKOUT_PCIE3N
CLKOUT_PCIE3P
CLKOUT_PCIE2N
CLKOUT_PCIE2P
CLKOUT_PCIE1N
CLKOUT_PCIE1P
CLKOUT_PCIE0N
CLKOUT_PCIE0P
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
CLKOUTFLEX0/GPIO64
CLKOUTFLEX1/GPIO65
CLKOUTFLEX2/GPIO66
CLKOUTFLEX3/GPIO67
http://vinafix.vn
FDI_INT
B51
E49
C52
D51
H46
TP_NVR_DATA0
AB50
TP_NVR_DATA1
Y50
TP_NVR_DATA2
AB49
TP_NVR_DATA3
AB44
TP_NVR_DATA4
U49
TP_NVR_DATA5
R44
TP_NVR_DATA6
U50
TP_NVR_DATA7
U46
TP_NVR_DATA8
U44
TP_NVR_DATA9
H50
TP_NVR_DATA10
K46
TP_NVR_DATA11
L56
TP_NVR_DATA12
J55
TP_NVR_DATA13
F53
TP_NVR_DATA14
H52
TP_NVR_DATA15
E52
TP_SU1_029
R50
R52
N52
P31
R31
TP_CLKOUT_DP#_CLKOUT_BCLK1#
N56
TP_CLKOUT_DP_CLKOUT_BCLK1
M55
AE2
AF1
AB3
AA2
AF3
AG2
Y9
Y8
AB9
AB8
AB12
AB14
AA5
W5
TP_CPU_AE6
AE6
TP_CPU_AC6
AC6
AG8
AG9
TP_CLKOUT_PEG_B#
AE12
TP_CLKOUT_PEG_B
AE11
AT11
AN14
AT12
AT17
AT14
AT9
BA5
AW5
BA2
PCH_CLKOUT_PCI0
IPD 20K
PCH_CLKOUT_PCI1
IPD 20K
PCH_CLKOUT_PCI2
IPD 20K
PCH_CLKOUT_PCI3
IPD 20K
PCH_CLKOUT_PCI4
IPD 20K
CLKOUTFLEX0_GPIO64
IPD 20K
PCH_CLKOUTFLEX1_48M_SIO
IPD 20K
CLKOUTFLEX0_GPIO66
IPD 20K
CLKOUTFLEX0_GPIO67
IPD 20K
ST105
ST105
1
ST106
ST106
1
ST107
ST107
1
ST108
ST108
1
ST109
ST109
1
ST110
ST110
1
ST111
ST111
1
ST112
ST112
1
ST113
ST113
1
ST114
ST114
1
ST115
ST115
1
ST116
ST116
1
ST117
ST117
1
ST118
ST118
1
ST119
ST119
1
ST120
ST120
1
ST129
ST129
1
SR251 22 OHM
SR251 22 OHM
I
I
SR275 22 OHM
SR275 22 OHM
I
I
SR277 22 OHM
SR277 22 OHM
NI
NI
1
SR253 22 OHM
SR253 22 OHM
I
I
1
I
I
1
1
NOTE:
1.Prioritize 27/14/24/48/25-MHz FLEX on FLEX1/3.
2.Do not configure 27/14/24/48/25-MHz FLEX clock on FLEX0/2
if more than 2 PCI clocks + PCI loopback are routed.
3.With 2 PCI clocks routed (or less), prioritize the FLEX clocks to FLEX1/3
a. 27MHz(SSC/non-SSC) b.14.31818MHz c.24/48 d.25MHz
3
FDI_FSYNC_0 11
FDI_LSYNC_0 11
FDI_FSYNC_1 11
FDI_LSYNC_1 11
FDI_INT 11
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
NOBOM
ST40
ST40
1
1
1
1
1
1
NOBOM
NOBOM
ST41
ST41
NOBOM
NOBOM
ST42
ST42
NOBOM
NOBOM
ST43
ST43
NOBOM
NOBOM
ST54
ST54
NOBOM
NOBOM
ST55
ST55
NOBOM
NOBOM
1 2
1 2
1 2
ST164
ST164
NOBOM
NOBOM
1 2
ST57
ST57
NOBOM
NOBOM
SR152 22
SR152 22
1 2
ST162
ST162
NOBOM
NOBOM
ST163
ST163
mx_r0402
mx_r0402
NOBOM
NOBOM
2
2
CK_48M_SIO 53
1
CK_100M_CPUXDP# 82
CK_100M_CPUXDP 82
CK_100M_DMI# 12
CK_100M_DMI 12
CK_100M_USB3# 39
CK_100M_USB3 39
CK_100M_PCHXDP# 83
CK_100M_PCHXDP 83
CK_100M_BRIDGE# 47
CK_100M_BRIDGE 47
CK_100M_PE2# 34
CK_100M_PE2 34
CK_100M_PE3# 34
CK_100M_PE3 34
CK_100M_LAN# 35
CK_100M_LAN 35
CK_100M_SATA3# 51
CK_100M_SATA3 51
CK_100M_PE16# 32
CK_100M_PE16 32
12
GND
PEGATRON DT-MB RESTRICTED SECRET
12
NI
NI
SC35
SC35
150PF/50V
150PF/50V
NPO 5%
NPO 5%
GND GND GND
mx_c0402
mx_c0402
<Variant Name>
<Variant Name>
<Variant Name>
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
12
NI
NI
SC34
SC34
150PF/50V
150PF/50V
NPO 5%
NPO 5%
mx_c0402
mx_c0402
NI
NI
SC37
SC37
150PF/50V
150PF/50V
NPO 5%
NPO 5%
mx_c0402
mx_c0402
IPMSB-BE/CR
IPMSB-BE/CR
IPMSB-BE/CR
12
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
1
NI
NI
SC38
SC38
150PF/50V
150PF/50V
NPO 5%
NPO 5%
mx_c0402
mx_c0402
CLK/NVRAM/FDI 6-9
CLK/NVRAM/FDI 6-9
CLK/NVRAM/FDI 6-9
Livy_Zhu
Livy_Zhu
Livy_Zhu
CK_33M_SIO 53
CK_33M_DEBUG 80
CK_33M_TPM 55
CK_33M_PCIFB 19
24 83Friday, September 24, 2010
24 83Friday, September 24, 2010
24 83Friday, September 24, 2010
of
of
of
Rev
Rev
Rev
1.00
1.00
1.00
5
+1P05V_PCH
vinafix
D D
NOTE:
Splitting 2 power trace/shape
on pin Y20/Y22/V22 to other pins.
C C
NOTE:
Splitting 2 power trace/shape
+1P05V_PCH
B B
NOTE:
Install SCB12 during initial power-on.
A A
NOTE:
Install those cap during initial power-on.
12
I
I
SCB1
SCB1
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
GND GND GND GND
12
I
I
SCB2
SCB2
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
12
I
I
SCB5
SCB5
0.1UF/16V
0.1UF/16V
Y5V +80-20%
Y5V +80-20%
mx_c0402
mx_c0402
GND GND
12
I
I
SCB3
SCB3
0.1UF/16V
0.1UF/16V
Y5V +80-20%
Y5V +80-20%
mx_c0402
mx_c0402
12
I
I
SCB6
SCB6
0.1UF/16V
0.1UF/16V
Y5V +80-20%
Y5V +80-20%
mx_c0402
mx_c0402
+1P05V_CPUIO
NOTE:
Trace needs
to be at least
20 mils width
with full VSS/
12
GND
I
I
SCB12
SCB12
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
VCC reference
plane
12
I
I
SCB10
SCB10
1UF/16V
1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
GND GND
5
12
I
I
SCB11
SCB11
1UF/16V
1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
GND
+1P05V_PCH
GND
+1P05V_PCH
GND
GND
+1P05V_PCH
GND
12
I
I
SCB4
SCB4
0.1UF/16V
0.1UF/16V
Y5V +80-20%
Y5V +80-20%
mx_c0402
mx_c0402
12
I
I
SCB7
SCB7
1UF/16V
1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
12
I
I
SCB8
SCB8
1UF/16V
1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
12
I
I
SCB9
SCB9
1UF/16V
1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
12
NI
NI
SCB16
SCB16
1UF/16V
1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
12
NI
NI
SCB13
SCB13
0.1UF/16V
0.1UF/16V
Y5V +80-20%
Y5V +80-20%
mx_c0402
mx_c0402
AA34
AA36
AL40
AN40
AN41
BA38
AG38
AG40
AG41
AJ38
AG24
AG26
AG28
AJ24
AJ26
AJ28
AL24
AL28
AN22
AN24
AN26
AN28
AR24
AR26
AR28
AR30
AR36
AR38
AU30
AU36
AU34
AV36
AU32
F20
F30
V25
V27
V31
V33
Y24
Y26
Y30
Y32
Y34
V22
Y20
Y22
B41
E41
4
I
I
SU1G
SU1G
VccIO_024
VccIO_025
VccIO_026
VccIO_027
VccIO_028
VccIO_029
VccIO_030
VccIO_031
VccIO_032
VccIO_033
VccIO_034
VccIO_035
VccIO_022
VccIO_023
VccIO_036
VccIO_037
VccDMI_02
VccDMI_01
VccIO_008
VccIO_009
VccIO_010
VccIO_019
VccIO_020
VccIO_021
VccIO_007
VccIO_011
VccASW_004
VccASW_005
VccASW_006
VccASW_007
VccASW_008
VccASW_009
VccASW_010
VccASW_011
VccASW_012
VccASW_013
VccASW_014
VccASW_015
VccASW_016
VccASW_017
VccASW_018
VccASW_019
VccASW_020
VccASW_021
VccASW_022
VccASW_023
VccASW_003
VccASW_002
VccASW_001
COUGARPOINT
COUGARPOINT
4
VccCore_001
VccCore_002
VccCore_003
VccCore_004
VccCore_005
VccCore_006
VccCore_007
VccCore_008
VccCore_009
VccCore_010
VccCore_011
VccCore_012
VccCore_013
VccCore_014
VccCore_015
VccCore_016
VccCore_017
VccCore_018
VccCore_019
VccCore_020
VccCore_021
VccCore_022
VccIO_018
VccSSC_01
VccSSC_02
VccIO_001
VccIO_002
VccIO_003
VccIO_004
VccIO_013
VccIO_012
VccIO_014
VccDIFFCLKN_01
VccDIFFCLKN_02
VccDIFFCLKN_03
VccAFDIPLL
VccAClk
VccAPLLEXP
VccAPLLSATA
VccAPLLDMI2
VccClkDMI
VccADAC
VccADPLLA
VccADPLLB
3
AC24
AC26
AC28
AC30
AC32
AE24
AE28
AE30
AE32
AE34
AE36
AG32
AG34
AJ32
AJ34
AJ36
AL32
AL34
AN32
AN34
AR32
AR34
GND
12
I
I
SCB14
SCB14
1UF/10V
1UF/10V
mx_c0603
mx_c0603
+1P05V_PCH
12
I
I
SCB15
SCB15
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
GND
NOTE:
VccAPLLEXP, VccAPLLSATA, and VccAPLLDMI2 can be NC
in On-Die VR mode.
NI
NI
SR168
SR168
0
0
mx_r0402
mx_r0402
NOTE:
Splitting 2 power trace/shape
+1P05V_PCH
AE40
AC20
AE20
AV24
AV26
AY25
AY27
V36
Y36
Y28
+1P05V_PCH
AE15
AE17
AG15
C54
AL5
B53
U56
A19
AJ20
AT1
AB1
AC2
http://vinafix.vn
on pins AV24/AV26 to AY25/AY27,
and AE40 to AG38/AG40.
I
I
SCB32
SCB32
1UF/16V
1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
12
12
NI
NI
SR161
SR161
0
0
mx_r0402
mx_r0402
3
I
I
SCB33
SCB33
1UF/16V
1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
+1P05V_PCH+1P05V_PCH
12
NOTE:
If filter is unstuffed, 0 ohm resistor(SR163)
must be stuffed in R and L site.
12
GND GND
NOTE:
Splitting 2 power traces
on pins AC20 to AE20.
12
I
I
SCB65
SCB65
NOTE:
1UF/16V
1UF/16V
VccAFDIPLL and VccAClk
X7R 10%
X7R 10%
mx_c0603
mx_c0603
GND
VCCFDIPLL
VCCACLKPLL
VCCAPLLEXP
VCCAPLLSATA
VCCAPLLDMI2
VCCCLKDMI
VCCADAC
VCCA_DPLLA
VCCA_DPLLB VCCA_DPLLB_R
can be NC in on-die VR mode.
NI
NI
SR160
SR160
0
0
mx_r0402
mx_r0402
12
2
12
NI
NI
SCB20
SCB20
1UF/16V
1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
GND
12
GND GND
12
GND
12
GND
12
GND
12
GND GND
12
GND GND
NI
NI
SCB22
SCB22
1UF/10V
1UF/10V
mx_c0603
mx_c0603
NI
NI
SCB24
SCB24
1UF/16V
1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
I
I
SCB26
SCB26
1UF/16V
1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
NI
NI
SCB28
SCB28
1UF/16V
1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
I
I
SCB29
SCB29
1UF/16V
1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
I
I
SCB30
SCB30
1UF/16V
1UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
2
GND
12
12
12
GND
GND
GND
+
+
+
+
+
+
12
NI
NI
SCB21
SCB21
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
12
NI
NI
SCB23
SCB23
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
12
NI
NI
SCB25
SCB25
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
12
I
I
SCB27
SCB27
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
I
I
SCE1
SCE1
220UF/16V
220UF/16V
I
I
SCE2
SCE2
220UF/16V
220UF/16V
I
I
SCE3
SCE3
220UF/16V
220UF/16V
1
NI
NI
SL1
VCCAPLLEXP_R
NI
NI
SR162
SR162
0
0
mx_r0402
mx_r0402
12
VCCAPLLDMI2_R
NOTE:
SL1
2 1
1UH/300mA
1UH/300mA
mx_l0805
mx_l0805
NI
NI
SL2
SL2
2 1
10UH/125mA
10UH/125mA
mx_l0805
mx_l0805
NI
NI
SL3
SL3
2 1
1UH/300mA
1UH/300mA
mx_l0805
mx_l0805
Backup to 0 ohm 1/8W(0805)JUMP
if power noise is pass on SL3 and SL4.
I
I
SR163
SR163
1
1
mx_r0402
mx_r0402
VCCIOPLL_R
12
NOTE:
CRB 0.7:
I
I
SL4
SL4
2 1
10UH/125mA
10UH/125mA
mx_l0805
mx_l0805
SCB27 is NI and
SR163 is 0 ohm.
I
I
SL5
SL5
2 1
600Ohm/100Mhz/0.5A
600Ohm/100Mhz/0.5A
mx_l0603
mx_l0603
+3P3V
NOTE:
Backup SL5 to 10X2121R0040(1 ohm/0402)
if have no power noise issue.
I
I
SR165
SR165
0
0
mx_r0402
mx_r0402
VCCA_DPLLA_R
12
I
I
SL6
SL6
2 1
10UH/125mA
10UH/125mA
mx_l0805
mx_l0805
NOTE:
Backup to 0 ohm 1/8W(0805)JUMP
I
I
SR167
SR167
0
0
mx_r0402
mx_r0402
if power noise is pass on SL6 and SL7.
I
I
SL7
SL7
12
<Variant Name>
<Variant Name>
<Variant Name>
PEGATRON DT-MB RESTRICTED SECRET
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
2 1
10UH/125mA
10UH/125mA
mx_l0805
mx_l0805
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
IPMSB-BE/CR
IPMSB-BE/CR
IPMSB-BE/CR
1
+1P05V_PCH
VCC/PLL 7-9
VCC/PLL 7-9
VCC/PLL 7-9
Livy_Zhu
Livy_Zhu
Livy_Zhu
25 83Friday, September 24, 2010
25 83Friday, September 24, 2010
25 83Friday, September 24, 2010
of
of
of
Rev
Rev
Rev
1.00
1.00
1.00
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