Pegatron IPM41-D3 Schematic

5
A
IPM41-D3
D D
Intel Pentium processor
Conroe-L/Conroe/Wolfdate
On board VGA
C C
PCI Express X16 SLOT
PCI-E X16
4
Revision:1.00
LGA775
HOST BUS
INTEL
GMCH
EagleLake
DMI Link
Channel A
Channel B
3
53
+1P1V_CORE
54
SPI 4Mb
55
RTC / CMOS / SPKR/SCREW HOLE
DDR3 DIMM A1
DDR3 DIMM B1
2
01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Block Diagram Power Sequence Power Flow Clock Distribution Clock PROCESSOR LGA775 1 - 3 PROCESSOR LGA775 2 - 3 PROCESSOR LGA775 3 - 3 ITP_31P DEBUG CONNECTOR INTEL EAGLELAKE 1 - 7 INTEL EAGLELAKE 2 - 7 INTEL EAGLELAKE 3 - 7 INTEL EAGLELAKE 4 - 7 INTEL EAGLELAKE 5 - 7 INTEL EAGLELAKE 6 - 7 INTEL EAGLELAKE 7 - 7 DDR2 CHANNEL A DDR2 CHANNEL B DDR2 TERMINATION A&B ICH7-1 ICH7-2 ICH7-3 ICH7-4 PCI EXPRESS X16 SLOT PCI EXPRESS X1 SLOT INTEGRATED VGA PORT SATA CONNECTORS PCI SLOT INTERFACE - PCI1 PCI SLOT INTERFACE - PCI2
1
3032DOUBLE STACK PORT CONNECTOR
PCI Express X1 SLOT
PCI-E X1
SATA
INTEL
B B
ALC662/ALC888S
Audio
Azalia Link
24MHz
ICH7
SATA1
SATA2
SATA3
SATA4
33 34 35 36 37 38 39 40
31
USB2.0
8 ports
480Mb/s
LPC
SUPER I/O
Winbond83627DHG-A
41 42 43 44 45
PCI Slot1
PCI Slot2
PCI Bus
SPI
Parallel Port
SPI
LAN
RealTek
PCI-E X
RTL8111D(L)
TPM
Serial Port PS2 KB/MS FAN Control H/W Monitor
46 47 48 49 50 51 52
USB HEADER CONNECTOR REALTEK RTL8111C CONTROLLER RJ-45+USB CONNECTOR ALC662/883 AUDIO Connector FRONT AUDIO CONNECTOR TPM HEADER INTERFACE SUPER I/O W83627DHG - 1 OF 2 SUPER I/O W83627DHG - 2 OF 2 PARALLEL PORT - CPC SERIAL PORT CONNECTOR- SI PS2 KB &MS CONNECTOR FOR CPC FAN CIRCUIT FOR 4 - PIN FRONT PANEL CIRCUIT FOR CPC ATX POWER_24P CONNECTOR VCORE CONTROLLER - RT8857 VCORE DRIVER - RT9619_1 VCORE DRIVER - RT9619_2 +0P9V_VTT_DDR_LDO +1P1V_FSB_VTT&+5V_DUAL PSI CIRCUIT +1P8V_DUAL
<Variant Name>
<Variant Name>
<Variant Name>
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
IPM41-D3
IPM41-D3
IPM41-D3
Engineer:
Block Diagram
Block Diagram
Block Diagram
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
1 55Thursday, July 09, 2009
1 55Thursday, July 09, 2009
1 55Thursday, July 09, 2009
1.00G
1.00G
1.00G
Rev
Rev
Rev
A
5
A
4
3
2
1
8
PLTRST#
GMCH
7
PWROK
PSON#
Power Supply
6
PLTRST#_PCIEX16
PLTRST#_PCIEX1
5V
PWROK_PS
RST#_IDE
/X
5V Level
9
IDE
PCI Express X16
9
3.3V
PCI Express X1
9
3.3V
D D
User press Ctrl+Alt+Del
User press Power button
PWRBTN#
Default
3
C C
Super IO
3.3V
RST_KB
8
3.3V
RSMRST#
2
PWROK
7
Buffer Out
4
5
5
SLP_S3#
SLP_S4#
IO_PWRBTN#
PCI slots
3.3V
3.3V
3.3V
3.3V
PLTRST#
8
8
3.3V
PCIRST#
User press Reset button
RSTCON#
Default
User Clear CMOS
RTCRST#
3.3V
3.3V
3.3V
1
3.3V
3.3V
3.3V
ICH7
B B
10
CPURST#
CPU
CPUPWRGD
HINIT#
Vcore
Vcore
FWHHINIT#
RTL8111C
3.3V
FWH
3.3V
3.3V
3.3V
3.3V
8
8
8
<Variant Name>
<Variant Name>
<Variant Name>
8
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
IPM41-D3
IPM41-D3
IPM41-D3
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
Power Sequence
Power Sequence
Power Sequence
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
1.00G
1.00G
2 55Thursday, July 09, 2009
2 55Thursday, July 09, 2009
2 55Thursday, July 09, 2009
1.00G
Rev
Rev
Rev
A
5
A
4
3
2
1
ATX12V
ISL6312
3.5Phases
I max.=125A. TDC: 100A.
D D
S0
VCORE_EN
TDP:65W.(05A)
VCORE
ATXPWR
+5VSB
L1085DG
S0/S3/S5
L1117LG
S0/S3/S5
+3VSB
LAN_2.5V
Io: 2A
Io: 260mA
L1117LG
S0/S3/S5
LAN_1.5V
+3VDUAL
Io: 380mA
Io S0: 500mA S3: 12mA
AME1117ACGTZ
C C
+5V
APM9932CKC
+
AP2306GN
S3/S5:+5VSB
S0:+5V
+5V_DUAL
S0/S3/S5
Switch
APW7120KE_TRL
S0/S1/S3
+1.8V_DUAL
Io S0/S1: 14A
LM324DR+ AP60T03H*2
S0
Io: >10.4A
+1.5V
S3: 425mA
LM324DR +P3055LDG
S0
+3.3V
LM324DR+7002
S0
+2.5V_DAC
Io: 70mA
LM324DR +P3055LDG
B B
LM324DR+7002
S0
VR_ProtHot
S0
Io: 6A
+VTT_CPU
Io: 1.31A
+1.05V
CM8562PGISTR VTT_DDR
S0/S3
Io S0: 1.2A S3: 420mA
NOTE:
Linear REG
1.00G
1.00G
1.00G
Rev
Rev
Rev
A
<Variant Name>
<Variant Name>
Switch REG
<Variant Name>
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
IPM41-D3
IPM41-D3
IPM41-D3
Engineer:
Power Flow
Power Flow
Power Flow
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
3 55Thursday, July 09, 2009
3 55Thursday, July 09, 2009
3 55Thursday, July 09, 2009
5
A
4
3
2
1
133/200/266 MHz
CK_FSB_CPU/#
CPU
ICS
D D
9LPRS552AGLF_T
133/200/266 MHz
100 MHz
96 MHz
CK_FSB_NB/#
CK_100M_MCH/#
CK_96M_DREF/#
MCH
Lakeport
CK_100M_PCIEX16/#100 MHz
PCIEX16
14.318 MHz
XTAL
100 MHz
100 MHz
C C
33 MHz
14.318 MHz
48 MHz CK_48M_SIO
CK_100M_ICH/#
CK_100M_SATA/#
CK_48M_USB48 MHz
CK_33M_ICH
CK_14M_ICH
CK_33M_SIO33 MHz
ICH7
Super I/O
33 MHz
B B
33 MHz
CK_PCI_TPM
TCM
CK_33M_SL133 MHz
PCI SLOT 1
33 MHz
CK_33M_SL2
PCI SLOT 2
CK_PCIE_SLOT1/#100 MHz
PCIEX1_1
100 MHz
CK_100M_LAN/#
LAN
<Variant Name>
<Variant Name>
<Variant Name>
Clock Distribution
Clock Distribution
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
IPM41-D3
IPM41-D3
IPM41-D3
Engineer:
Clock Distribution
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
4 55Thursday, July 09, 2009
4 55Thursday, July 09, 2009
4 55Thursday, July 09, 2009
1.00G
1.00G
1.00G
Rev
Rev
Rev
A
5
I
+3P3VSB
+3P3V
D D
I
CKL1
CKL1 600Ohm/100Mhz/0.5A
600Ohm/100Mhz/0.5A
mx_l0603
mx_l0603
21
NI
NI
CKL2
CKL2 600Ohm/100Mhz/0.5A
600Ohm/100Mhz/0.5A
mx_l0603
mx_l0603
21
+CLKVCC3
12
I
I
CKCB2
CKCB2
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
NOTE:
CKR2 CKR10
4
I
I
CKCB3
CKCB3
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
12
12
GND
PIN17 PIN18
25MHzI NI
24.576MHz
I
I
CKCB4
CKCB4
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
12
I
I
CKCB5
CKCB5
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
VDDPCI
VDD_PLL3 VDD_SRC
VDDCPU
VDDREF
+CLKVCC3
12
I
I
CKR2
CKR2 10K
10K
12
I
I
CKCB6
CKCB6
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GNDGND
GND
VOUT_VDDIO
I
I CRITICAL
CRITICAL
CKU2
CKU2
2
VDD_PCI
16
VDD_PLL3
31
VDD_SRC
47
VDD_CPU
53
VDD_REF
8
VSS_PCI
23
VSS_SRC1
34
VSS_SRC2
44
VSS_CPU
50
VSS_REF
40
SEL_24.576MHz
3
CPU_0
CPU_0#
CPU_1_AMT
CPU_1_AMT#
SRC_8/CPU_ITP
SRC_8#/CPU_ITP#
SRC_7
SRC_7#
SRC_6
SRC_6#
PCI_STOP#/SRC_5
CPU_STOP#SRC_5#
SRC_4
SRC_4#
SRC_3
SRC_3#
SRC_2
SRC_2#
25MHz_0_F
25MHz_1/24.576MHz
SRC_0/DOT_96
SRC_0#/DOT_96#
2
46 45
43 42
39 38
36 35
33 32
30 29
27 28
24 25
21 22
17 18
13 14
1 2
CKR1
CKR1
I
I
33
33
8/19 modify
CPUHCLK [6] CPUHCLK# [6]
CK_FSB_NB [10] CK_FSB_NB# [10]
CK_ITP [9] CK_ITP# [9]
CK_100M_ICH [20] CK_100M_ICH# [20]
CK_100M_PCIEX16 [24] CK_100M_PCIEX16# [24]
CK_100M_PCIEX1 [25] CK_100M_PCIEX1# [25]
CK_100M_MCH [10] CK_100M_MCH# [10]
CK_100M_LAN [32] CK_100M_LAN# [32]
CK_100M_SATA [20] CK_100M_SATA# [20]
CK_25M_LAN [32]
CK_96M_DREF [13] CK_96M_DREF# [13]
1
NOTE:
SRC[3 4 6 and 7] are designated for PCIe GEN2, must be used for GMCH and PCIe Gen2 slot
NOTE:
PIN [29 30] tie to ICH through 1K ohm if iAMT support (PCI_STOP#, CPU_STOP#), Strap SRC5 disable
C C
12
I
I
CKCB9
CKCB9
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
I
I
CKCB12
CKCB12 10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10% mx_c0805
mx_c0805
12
12
I
I
CKCB13
CKCB13
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
12
I
I
CKC8
CKC8 33PF/50V
33PF/50V
NPO 5%
NPO 5%
GND GND GND
12
NI
NI
CKC10
CKC10 33PF/50V
33PF/50V
NPO 5%
NPO 5%
GND
4
12
PCB40
PCB40
PCB
PCB
PCB_BOARD
PCB_BOARD
I
I
B B
VRMPWRGD_ICH[21,51]
A A
SMB_CLK_R[9,17,18,21,24,25,28,29]
SMB_DATA_R[9,17,18,21,24,25,28,29]
5
GND
+CLKVCC3
VRMPWRGD_ICH
12
NI
NI
CKCB11
CKCB11 10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10% mx_c0805
mx_c0805
GND GND
I
I
CKCB14
CKCB14
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
12
I
I
CKCB18
CKCB18
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
I
I
Y1
Y1
14.318Mhz
14.318Mhz
1 2
1 2
GND
GND
3
3
GND
12
GNDGND
12
NI
NI
CKC11
CKC11 33PF/50V
33PF/50V
NPO 5%
NPO 5%
I
I
CKCB15
CKCB15
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
12
VDD_IO_96
+VDD_IO
12
I
I
CKCB16
CKCB16
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
VDD48_BW
GND
OSC_CK14M_XTALIN OSC_CK14M_XTALOUT
I
I
CKC9
CKC9 33PF/50V
33PF/50V
NPO 5%
NPO 5%
GND
12
VDD_I/O_3.3
20
VDD_PLL3_I/O
26
VDD_SRC_I/O1
37
VDD_SRC_I/O2
41
VDD_CPU_I/O
19
VSS_PLL3
15
VSS_I/O
9
VDD_48
11
VSS_48
48
CKPWRGD/PD#
52
XTAL_IN
51
XTAL_OUT
56
SCL
55
SDA
SLG8XP548T
SLG8XP548T
ITP_EN/PCI_5
PCI_4/SRC_5_EN
FS_A/48MHz_0
FS_B/TEST_MODE
REF/FS_C/TEST_SEL
3
PCIF5/ITP_EN(Pin7): 1: CPU_ITP
PCI4/SRC5_EN(Pin6): 1: SRC5 Output
7 6 5
PCI_3
4
PCI_2
3
PCI_1
1
PCI_0
PCI3/CFG0(Pin5): Strap for SATA PLL 1: PLL2, SS OFF
PCI2/TME(Pin4): 1: SR enable
10
49
54
RCK_33M_ICH CK_33M_PCI4 RCK_33M_TPM RCK_33M_SL2 RCK_33M_SL1 RCK_33M_SIO
RCK_48M_USB
FSLB
RCK_14M_ICH
1 2
+CLKVCC3
I
I
CKRN1A
CKRN1A
4.7KOHM
4.7KOHM
5%
5%
CKRN1B
CKRN1B
4.7KOHM
4.7KOHM
3 4
CKRN2A
CKRN2B CKRN2C CKRN2D
I
I
I
I
CKRN1C
CKRN1C
CKRN1D
CKRN1D
4.7KOHM
4.7KOHM
4.7KOHM
5%
5%
5 6
4.7KOHM
5%
5%
5%
5%
7 8
CKR42 22
CKR42 22
I
I
CKR40 22
CKR40 22
I
I
CKR39 33
CKR39 33
I
I
NOTE:
Single End damping resistor Single Load => 33 OHM Double Load => 22 OHM
2
1 2
33 Ohm
33 Ohm
3 4
33 Ohm
33 Ohm
5 6
33 Ohm
33 Ohm
7 8
33 Ohm
33 Ohm
I
I
1 2 1 2
1 2
NOTE:
PCIF_5 is dedicated for ICH
5%I CKRN2A
5%I
5%I CKRN2B
5%I 5%I CKRN2C
5%I 5%I CKRN2D
5%I
1 2
CKR34
CKR34
I
I
CKRN3A
I CKRN3A
I
CKRN3C
I CKRN3C
I
CKRN3B
I CKRN3B
I
33
33
12
12
NI
NI
CKC3
CKC3 10PF/50V
10PF/50V
NPO 5%
NPO 5%
GND GND GND GND GND
1 2
1KOHM
1KOHM
5 6
1KOHM
1KOHM
3 4
1KOHM
1KOHM
PCI4 is for the shortest route PCI0 is for the longest route
8/27 modify
12
12
NI
NI
NI
NI
CKC5
CKC5
CKC4
CKC4
10PF/50V
10PF/50V
10PF/50V
10PF/50V
NPO 5%
NPO 5%
NPO 5%
NPO 5%
5%
5%
5%
5%
5%
5%
I
I
CKC6
CKC6 10PF/50V
10PF/50V
NPO 5%
NPO 5%
PEGATRON DT-MB RESTRICTED SECRET
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Engineer:
IPM41-D3
IPM41-D3
IPM41-D3
1
CK_33M_ICH [20]
CK_33M_TPM [37] CK_33M_SL2 [29] CK_33M_SL1 [28] CK_33M_SIO [39]
12
NI
NI
CKC7
CKC7 10PF/50V
10PF/50V
NPO 5%
NPO 5%
M_HBSEL0 [7,13]
CK_48M_SIO [39]
CK_48M_USB [20]
M_HBSEL1 [7,13]
CK_14M_ICH [21]
M_HBSEL2 [7,13]
CLOCK CK505
CLOCK CK505
CLOCK CK505
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
5 55Thursday, July 09, 2009
5 55Thursday, July 09, 2009
5 55Thursday, July 09, 2009
Rev
Rev
Rev
1.00G
1.00G
1.00G
5
I
I
XU1A
XU1A
SOCKET775/ATX
HA#[3..35][10]
HA#3 HA#4 HA#5 HA#6
HRS#2 HRS#1 HRS#0
HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16
HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4
HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31
HA#32 HA#33 HA#34 HA#35
D D
HREQ#[0..4][10]
HADSTB0#[10]
C C
B B
HA#[3..35][10]
HADSTB1#[10]
HRS#[0..2][10]
SOCKET775/ATX
L5
A03#
P6
A04#
M5
A05#
L4
A06#
M4
A07#
R4
A08#
T5
A09#
U6
A10#
T4
A11#
U5
A12#
U4
A13#
V5
A14#
V4
A15#
W5
A16#
K4
REQ0#
J5
REQ1#
M6
REQ2#
K6
REQ3#
J6
REQ4#
R6
ADSTB0#
N4
RSVD1
P5
RSVD2
AB6
A17#
W6
A18#
Y6
A19#
Y4
A20#
AA4
A21#
AD6
A22#
AA5
A23#
AB5
A24#
AC5
A25#
AB4
A26#
AF5
A27#
AF4
A28#
AG6
A29#
AG4
A30#
AG5
A31#
AH4
A32#
AH5
A33#
AJ5
A34#
AJ6
A35#
AD5
ADSTB1#
AC4
RSVD3
AE4
RSVD4
A3
RS2#
F5
RS1#
B3
RS0#
ADS# BNR#
HIT# RSP# BPRI#
DBSY# DRDY#
HITM# IERR#
INIT# LOCK# TRDY# BINIT#
DEFER#
MCERR#
AP0#
AP1#
DP0#
DP1#
DP2#
DP3#
BR0#
GTLREF1
GTLREF0
GTLREF2
GTLREF3
4
+1P1V_FSB_VTT
12
I
I
HR1
HR1 62
62
D2 C2 D4 H4 G8 B2 C1 E4
HIERR#
AB2 P3 C3 E3 AD3 G7
AB3
U2 U3
J16 H15 H16 J17
F3
H2
CPU_GTLREF0
H1
NJP4
NJP4 SHORTPIN_RECT
SHORTPIN_RECT
NOBOM
NOBOM
1 2
F2
G10
RMA1
RMA1
NOBOM
NOBOM
SMD4X25_NP
SMD4X25_NP
RMA1 is soldermask on trace for RMA
1
purpose. Place on suitable location where
1
can be easily reached by Probe
HADS# [10] HBNR# [10] HIT# [10]
HBPRI# [10] HDBSY# [10] HDRDY# [10] HITM# [10]
HINIT# [20] HLOCK# [10] HTRDY# [10]
HDEFER# [10]
+VTT_OUT_L
12
I
I
HR2
HR2 62
62
I
I
HR5
HR5 10
12
NI
NI
HCB2
HCB2 220PF/50V
220PF/50V
X7R 10%
X7R 10%
10
I
I
HR6
HR6 10
10
12
12
12
CPU_GTLREF0_R
I
I
HCB3
HCB3 1UF/10V
1UF/10V
mx_c0603
mx_c0603
CPU_GTLREF1 CPU_GTLREF1_R
12
NI
NI
HCB1
HCB1 220PF/50V
220PF/50V
X7R 10%
X7R 10%
GND GND GNDGND
NOTE:
Place near CPU
NJP5
NJP5 SHORTPIN_RECT
SHORTPIN_RECT
NOBOM
NOBOM
1 2
12
I
I
HCB4
HCB4 1UF/10V
1UF/10V
mx_c0603
mx_c0603
3
HBREQ0# [10]
+VTT_OUT_L
12
12
I
I
HR4
HR4
57.6
57.6
1%
1%
I
I
HR8
HR8 100
100
1%
1%
+VTT_OUT_L
12
I
I
HR3
HR3
57.6
57.6
1%
1%
12
I
I
HR7
HR7 100
100
1%
1%
GNDGND
2
I
I
XU1B
XU1B
SOCKET775/ATX
SOCKET775/ATX
HD#[0..63][10]
HDBI0#[10]
HDSTBN0#[10] HDSTBP0#[10]
HD#[0..63][10] HD#[0..63] [10]
HDBI1#[10]
HDSTBN1#[10] HDSTBP1#[10]
HD#0
B4
A10 A11 B10 C11
B12 C12 D11
E10 D10 F11 F12 D13 E13 G13 F14 G14 F15 G15
G11
G12 E12
D00#
C5
D01#
A4
D02#
C6
D03#
A5
D04#
B6
D05#
B7
D06#
A7
D07# D08# D09# D10# D11#
D8
D12# D13# D14# D15#
A8
DBI0#
C8
DSTBN0#
B9
DSTBP0#
G9
D16#
F8
D17#
F9
D18#
E9
D19#
D7
D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31#
DBI1#
DSTBN1# DSTBP1#
HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#39 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15
HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31
D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47#
DBI2#
DSTBN2# DSTBP2#
D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63#
DBI3#
DSTBN3# DSTBP3#
G16 E15 E16 G18 G17 F17 F18 E18 E19 F20 E21 F21 G21 E22 D22 G22
D19
G20 G19
D20 D17 A14 C15 C14 B15 C18 B16 A17 B18 C21 B21 B19 A19 A22 B22
C20
A16 C17
HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38
HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47
HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63
1
HD#[0..63] [10]
HDBI2# [10]
HDSTBN2# [10] HDSTBP2# [10]
HDBI3# [10]
HDSTBN3# [10] HDSTBP3# [10]
I
I
HR13
HR13 62
62
NI
NI
HC1
HC1 22PF/50V
22PF/50V
NPO 5%
NPO 5%
G28
G23
F28
BCLK0 BCLK1
RESET#
FC10
FC15
E24
H29
REV=1.3
REV=1.3
NOTE:
ICH_GPIOA
Default is 0.63*VTT
ICH_GPIOB
0
10
01
11
GTLREF
0.615*VTT0
0.65*VTT
0.63*VTT
0.67*VTT
COMMENTS
HQ1 off, HQ2 on HQ3 off, HQ4 on HQ1 off, HQ2 on HQ3 on, HQ4 off HQ1 on, HQ2 off HQ3 off, HQ4 on HQ1 on, HQ2 off HQ3 on, HQ4 off
ASUS OEM-DT MB RESTRICTED SECRET
REV=1.3
REV=1.3
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
4
3
2
Engineer:
IPM41-D3
IPM41-D3
IPM41-D3
INTEL LGA-775 1 - 3
INTEL LGA-775 1 - 3
INTEL LGA-775 1 - 3
Title :
Title :
Title :
1
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
6 55Thursday, July 09, 2009
6 55Thursday, July 09, 2009
6 55Thursday, July 09, 2009
Rev
Rev
Rev
1.00G
1.00G
1.00G
CPUHCLK[5] CPUHCLK#[5]
+VTT_OUT_R
12
A A
CPURESET#[9,10,51]
12
GND
5
5
4
3
2
1
PLACE NEAR SB
+1P1V_FSB_VTT
12
I
I
HR17
HR17 62
62
D D
C C
+VTT_OUT_R
RCVID[0..7][46]
B B
VID_SELECT[46]
+VCORE
A A
SMI#[20] A20M#[20]
HFERR#[20] INTR[20] NMI[20] IGNNE#[20] STPCLK#[20]
NOTE:
The VCCIO PLL Filter Circuit is no longer needed since Conroe CPU
HRN1D
HRN1D
680
680
HRN1C
HRN1C
680
680
HRN1B
HRN1B
680
680
HRN1A
HRN1A
680
680
HRN2D
HRN2D
680
680
HRN2C
HRN2C
680
680
HRN2B
HRN2B
680
680
HRN2A
HRN2A
680
680
I
I
HR65
HR65 680
680
VCC_SENSE[46]
VSS_SENSE[46]
5
GND
I
I
7 8
I
I
5 6
I
I
3 4
I
I
1 2
I
I
7 8
I
I
5 6
I
I
3 4
I
I
1 2
+VTT_OUT_R
TRD_CPU_P[38] TRD_CPU_N[38]
12
RCVID0 RCVID1 RCVID2 RCVID3 RCVID4 RCVID5 RCVID6 RCVID7
VID_SELECT
GND
GND
I
I
XU1C
XU1C
SOCKET775/ATX
SOCKET775/ATX
P2
SMI#
K3
A20M#
R3
FERR#/PBE#
K1
LINT0
L1
LINT1
N2
IGNNE#
M3
STPCLK#
A23
VCCA
B23
VSSA
C23
VCCIOPLL
AM2
VID0
AL5
VID1
AM3
VID2
AL6
VID3
AK4
VID4
AL4
VID5
AM5
VID6
AM7
VID7
AN7
VID_SECECT
AE8
SKTOCC#
AL1
THERMDA
AK1
THERMDC
AJ7
VSS_AJ7
AH7
VSS_AH7
AN5
VCC_MB_REGULATION
AN6
VSS_MB_REGULATION
AN3
VCC_SENSE
AN4
VSS_SENSE
AL8
VCC_D_SENSE
AL7
VSS_D_SENSE
REV=1.3
REV=1.3
TESTHI00 TESTHI01 TESTHI10 TESTHI11
TESTHI13 TESTHI02 TESTHI03 TESTHI04 TESTHI05 TESTHI06 TESTHI07 TESTHI08 TESTHI09
TESTHI12
BOOTSELECT
FORCEPR#
PWRGOOD
PROCHOT#
THERMTRIP#
4
COMP0 COMP1 COMP2 COMP3 COMP4 COMP5 COMP6 COMP7 COMP8
RSVD33 RSVD34 RSVD35 RSVD36 RSVD12 RSVD21
RSVD9
MSID0
MSID1
LL_ID1
LL_ID0
PECI
IMPSEL
TESTHI0
F26
TESTHI1
W3
TESTHI10
H5
TESTHI11
P1
TESTHI13
L2
TESTHI2_7
F25 G25 G27 G26 G24 F24
TESTHI8
G3
TESTHI9
G4
HCOMP0
A13
HCOMP1
T1
HCOMP2
G2
HCOMP3
R1
HCOMP4
J2
DPRSTP#
T2
CPU_PSI
Y3
HCOMP7
AE3
HCOMP8
B13
TESTHI12
W2
HR48
HR48
NI
NI
G1 U1 A24 E29 AH2 G6 F29
MSID0
W1
MSID1
V1
CPU_LL_ID1
AA2
V2
CPU_BOOT
Y1
AL3
NC
PECI_CPU
G5
IMPSEL_F6
F6
HFORCEPH#
AK6
CPUPWRGD
N1
PROCHOT#
AL2
H_THMTRIP#
M2
THERMALTRIP# NEED A PULL UP RESISTOR NEAR SB
0.05 IHRN3A
0.05 I
1 2
0.05 IHRN3B
0.05 I
3 4
0.05 IHRN3C
0.05 I
5 6
0.05 IHRN3D
0.05 I
7 8
HR24 51
HR24 51
I
I
HR23 51
HR23 51
I
I
HR49 49.9 1%
HR49 49.9 1%
I
I
HR46 49.9 1%
HR46 49.9 1%
I
I
HR28 49.9 1%
HR28 49.9 1%
I
I
HR33 49.9 1%
HR33 49.9 1%
I
I
HR32 49.9 1%
HR32 49.9 1%
NI
NI
HR37 49.9 1%
HR37 49.9 1%
I
I
HR36 49.9 1%
HR36 49.9 1%
I
I
HR47 49.9 1%
HR47 49.9 1%
NI
NI
HR39 24.9 1%
HR39 24.9 1%
I
I
HR21 51
HR21 51
I
I
0
0
12
0.05 IHRN6C
0.05 I
+VTT_OUT_L
12
NI
NI
HR53
HR53 62
62
12
I
I
HR56
HR56 51
51
GND
51OHM
51OHM 51OHM
51OHM 51OHM
51OHM 51OHM
51OHM
0.05 IHRN6A
0.05 I
0.05 IHRN6B
0.05 I
1 2 1 2 1 2 1 2
1 2
5 6
+VTT_OUT_R +VTT_OUT_L +VTT_OUT_R
+1P1V_FSB_VTT
HRN3A HRN3B HRN3C HRN3D
12 12
PM_SLP# [13,20 ] DPSLP# [21]
1 2
51OHM
51OHM
3 4
51OHM
51OHM
H_BPM2_2 [9] H_BPM3_2 [9] CPU_PSI [51] DPRSTP# [13]
12 12 12 12
12
HRN6C
51OHM
51OHM
12
NI
NI
HR50
HR50 51
51
GND
GND
PECI_CPU [38]
12
I
I
HR61
HR61 130
130
1%
1%
HRN6A HRN6B
12
12
NI
NI
HR51
HR51 51
51
NI
NI
HR62
HR62 100
100
+VTT_OUT_L
GND
H_BPM0_2 [9]
12
GND
12
3
+VTT_OUT_L
+VTT_OUT_L
+VTT_OUT_R
TRST#[9]
+VTT_OUT_R
+VTT_OUT_R
0.05 IHRN6D
0.05 I
7 8
51OHM
51OHM
H_BPM1_2[9]
TCK[9] TDI[9] TDO[9] TMS[9]
I
I I
I
BPM0#[9 ] BPM1#[9 ] BPM2#[9 ] BPM3#[9 ] BPM4#[9 ] BPM5#[9 ]
SYS_RESET#[9,21,38,44]
HRN6D
Check PWM controller
VRMPWRGD[46,51]
BOOTSELECT:
I
I
Install PD resistor to
HR55
HR55 51
51
prevent PSC SMF CDM PSL CPU from booting
+1P1V_FSB_VTT
I
I
HR63
HR63 130
130
1%
1%
M_HBSEL0[5,13] M_HBSEL1[5,13] M_HBSEL2[5,13]
CPUPWRGD [9,21]
H_THMTRIP# [20]
9/8 modify
0.05 IHRN4A
0.05 I
1 2
0.05 IHRN4B
0.05 I
3 4
0.05 IHRN4C
0.05 I
5 6
0.05 IHRN4D
0.05 I
7 8
0.05 IHRN5A
0.05 I
1 2
0.05 IHRN5B
0.05 I
3 4
0.05 IHRN5C
0.05 I
5 6
0.05 IHRN5D
0.05 I
7 8
HR35 51
HR35 51
1 2
HR38 51
HR38 51
1 2
HRN4A
51OHM
51OHM
HRN4B
51OHM
51OHM
HRN4C
51OHM
51OHM
HRN4D
51OHM
51OHM
12
I
I
HR26
HR26
49.9
49.9
1%
1%
GND
HRN5A
51OHM
51OHM
HRN5B
51OHM
51OHM
HRN5C
51OHM
51OHM
HRN5D
51OHM
51OHM
5%I HRN7A
5%I
HR500 470 OHM 5% IHR500 470 OHM 5% I
1 2
470 OHM
470 OHM
5%I
5%I
1 2
5 6
470 OHM
470 OHM
06/20 modify
5%I HRN7D
5%I 5%I HRN7B
5%I
I
I
XU1D
XU1D
SOCKET775/ATX
SOCKET775/ATX
AE1
TCK
AD1
TDI
AF1
TDO
AC1
TMS
AG1
HRN7D HRN7B
AJ2
AJ1 AD2 AG2
AF2 AG3
AC2
AK3
AJ3
AE6
D16
A20
E23
AM6
G29
H30 G30
N5 C9 E7
TRST#
BPM0# BPM1# BPM2# BPM3# BPM4# BPM5#
DBR#
ITPCLK<0> ITPCLK<1>
RSVD17 RSVD18 RSVD19 RSVD20 RSVD22 RSVD23 RSVD31
VTTPWRGD
BSEL0 BSEL1 BSEL2
REV=1.3
REV=1.3
VTT10 VTT11 VTT12 VTT13 VTT14 VTT15 VTT16 VTT17 VTT18 VTT19 VTT20 VTT21 VTT22 VTT23 VTT24
VTT_OUT1
VTT_OUT2
VCC_PLL
VTT_SEL
12
I
I
HR27
HR27
49.9
49.9
1%
1%
GND
+VTT_OUT_R +CPU_VCCPLL
12
I
I
HR52
HR52 680
680
12
NI
NI
HC2
HC2 100PF/50V
100PF/50V
NPO 5%
NPO 5%
GND
HRN7A
HRN7C
HRN7C
7 8
470 OHM
470 OHM
3 4
470 OHM
470 OHM
ASUS OEM-DT MB RESTRICTED SECRET
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
2
NOTE:
FSB_VTT Net Name changed
+1P1V_FSB_VTT
A29
VTT1
B25
VTT2
B29
VTT3
B30
VTT4
C29
VTT5
A26
VTT6
B27
VTT7
C28
VTT8
A25
VTT9
A28 A27 C30 A30 C25 C26 C27 B26 D27 D28 D25 D26 B28 D29 D30
+VTT_OUT_R
AA1
J1
12
GND GND
D23
12
F27
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
IPM41-D3
IPM41-D3
IPM41-D3
1
+VTT_OUT_L
12
NI
NI
NI
HCB13
HCB13
0.1UF/16V
0.1UF/16V
I
I
HCB14
HCB14
0.01UF/25V
0.01UF/25V
X7R 10%
X7R 10%
INTEL LGA-775 2 - 3
INTEL LGA-775 2 - 3
INTEL LGA-775 2 - 3
NI
HCB12
HCB12
0.1UF/16V
0.1UF/16V
12
NI
NI
HCB15
HCB15 10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10% mx_c0805
mx_c0805
GNDGND
VTT_SELECT [50]
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
7 55Thursday, July 09, 2009
7 55Thursday, July 09, 2009
7 55Thursday, July 09, 2009
Rev
Rev
Rev
1.00G
1.00G
1.00G
5
4
3
2
1
+VCORE
D D
I
AM15 AM18 AM19 AM21 AM22 AM25 AM26 AM29 AM30
AM8
AM9 AN11 AN12 AN14 AN15 AN18 AN19 AN21 AN22 AN25 AN26 AN29 AN30
AN8
AN9
K30 K29 K28 K27 K26 K25 K24 K23
J10 J11 J12 J13 J14 J15 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30
J8 J9
K8 Y8
I
XU1F
XU1F
SOCKET775/ATX
SOCKET775/ATX
VCC113 VCC114 VCC115 VCC116 VCC117 VCC118 VCC119 VCC120 VCC121 VCC122 VCC123 VCC124 VCC125 VCC126 VCC127 VCC128 VCC129 VCC130 VCC131 VCC132 VCC133 VCC134 VCC135 VCC136 VCC137 VCC138 VCC139 VCC140 VCC141 VCC142 VCC143 VCC144 VCC145 VCC146 VCC147 VCC148 VCC149 VCC150 VCC151 VCC152 VCC153 VCC154 VCC155 VCC156 VCC157 VCC158 VCC159 VCC160 VCC161 VCC162 VCC163 VCC164 VCC165 VCC166 VCC167 VCC168
REV=1.3
REV=1.3
VCC225 VCC224 VCC223 VCC222 VCC221 VCC220 VCC219 VCC218 VCC217 VCC216 VCC215 VCC214 VCC213 VCC212 VCC211 VCC210 VCC209 VCC208 VCC207 VCC206 VCC205 VCC204 VCC203 VCC202 VCC201 VCC200 VCC199 VCC198 VCC197 VCC196 VCC195 VCC194 VCC193 VCC192 VCC191 VCC190 VCC189 VCC188 VCC187 VCC186 VCC185 VCC184 VCC183 VCC182 VCC181 VCC180 VCC179 VCC178 VCC177 VCC176 VCC175 VCC174 VCC173 VCC172 VCC171 VCC170 VCC169
L8 M23 M24 M25 M26 M27 M28 M29 M30 M8 N23 N24 N25 N26 N27 N28 N29 N30 N8 P8 R8 T23 T24 T25 T26 T27 T28 T29 T30 T8 U23 U24 U25 U26 U27 U28 U29 U30 U8 V8 W23 W24 W25 W26 W27 W28 W29 W30 W8 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30
4
GND
12
NI
NI
HR66
HR66 1K
1K
GND GND
I
I
XU1E
XU1E
SOCKET775/ATX
SOCKET775/ATX
AA8
VCC1
AB8
VCC2
AC23
VCC3
AC24
VCC4
AC25
VCC5
AC26
VCC6
AC27
VCC7
AC28
VCC8
AC29
VCC9
AC30
VCC10
AC8
VCC11
AD23
VCC12
AD24
VCC13
AD25
VCC14
AD26
VCC15
AD27
VCC16
AD28
VCC17
AD29
VCC18
AD30
VCC19
AD8
C C
B B
A A
AE11 AE12 AE14 AE15 AE18 AE19 AE21 AE22 AE23
AE9 AF11 AF12 AF14 AF15 AF18 AF19 AF21 AF22
AF8
AF9 AG11 AG12 AG14 AG15 AG18 AG19 AG21 AG22 AG25 AG26 AG27 AG28 AG29 AG30
AG8
AG9
VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56
REV=1.3
REV=1.3
5
VCC112 VCC111 VCC110 VCC109 VCC108 VCC107 VCC106 VCC105 VCC104 VCC103 VCC102 VCC101 VCC100
VCC99 VCC98 VCC97 VCC96 VCC95 VCC94 VCC93 VCC92 VCC91 VCC90 VCC89 VCC88 VCC87 VCC86 VCC85 VCC84 VCC83 VCC82 VCC81 VCC80 VCC79 VCC78 VCC77 VCC76 VCC75 VCC74 VCC73 VCC72 VCC71 VCC70 VCC69 VCC68 VCC67 VCC66 VCC65 VCC64 VCC63 VCC62 VCC61 VCC60 VCC59 VCC58 VCC57
AM14 AM12 AM11 AL9 AL30 AL29 AL26 AL25 AL22 AL21 AL19 AL18 AL15 AL14 AL12 AL11 AK9 AK8 AK26 AK25 AK22 AK21 AK19 AK18 AK15 AK14 AK12 AK11 AJ9 AJ8 AJ26 AJ25 AJ22 AJ21 AJ19 AJ18 AJ15 AJ14 AJ12 AJ11 AH9 AH8 AH30 AH29 AH28 AH27 AH26 AH25 AH22 AH21 AH19 AH18 AH15 AH14 AH12 AH11
I
I
XU1G
XU1G
SOCKET775/ATX
SOCKET775/ATX
AF28
VSS1
AF27
VSS2
AF26
VSS3
AF25
VSS4
AF24
VSS5
AF23
VSS6
AF20
VSS7
AF17
VSS8
AF16
VSS9
AF13
VSS10
AF10
VSS11
AE7
VSS12
AE5
VSS13
AE30
VSS14
AE29
VSS15
AE28
VSS16
AE27
VSS17
AE26
VSS18
AE25
VSS19
AE24
VSS20
AE20
VSS21
AE2
VSS22
AE17
VSS23
AE16
VSS24
AE13
VSS25
AE10
VSS26
AD7
VSS27
AD4
VSS28
AC7
VSS29
AC3
VSS30
AC6
VSS31
AB7
VSS32
AB30
VSS33
AB29
VSS34
AB28
VSS35
AB27
VSS36
AB26
VSS37
AB25
VSS38
AB24
VSS39
AB23
VSS40
AB1
VSS41
AA7
VSS42
AA6
VSS43
AA30
VSS44
AA3
VSS45
AA29
VSS46
AA28
VSS47
AA27
VSS48
AA26
VSS49
AA25
VSS50
A12
VSS51
A15
VSS52
A18
VSS53
A2
VSS54
A21
VSS55
A6
VSS56
A9
VSS57
AA23
VSS58
AA24
VSS59
AF29
VSS60
D1
RSVD27
D14
RSVD28
E5
RSVD29
E6
RSVD30
F23
RSVD37
J3
RSVD32
12
NI
NI
HR67
HR67 1K
1K
NOTE:
Intel ENG Feature
REV=1.3
REV=1.3
VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98
VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140
3
AF3 AF30 AF6 AF7 AG10 AG13 AG16 AG17 AG20 AG23 AG24 AG7 AH1 AH10 AH13 AH16 AH17 AH20 AH23 AH24 AH3 AH6 AJ10 AJ13 AJ16 AJ17 AJ20 AJ23 AJ24 AJ27 AJ28 AJ29 AJ30 AJ4 AK10 AK13 AK16 AK17 AK2 AK20 AK23 AK24 AK27 AK28 AK29 AK30 AK5 AK7 AL10 AL13 AL16 AL17 AL20 AL23 AL24 AL27 AL28 AM1 AM10 AM13 AM16 AM17 AM20 AM23 AM24 AM27 AM28 AM4 AN1 AN10 AN13 AN16 AN17 AN2 AN20 AN23 AN24 AN27 AN28 B1
GND
GND
I
I
XU1H
XU1H
SOCKET775/ATX
SOCKET775/ATX
B11
VSS141
B14
VSS142
B17
VSS143
B20
VSS144
B24
VSS145
B5
VSS146
B8
VSS147
C10
VSS148
C13
VSS149
C16
VSS150
C19
VSS151
C22
VSS152
C24
VSS153
C4
VSS154
C7
VSS155
D12
VSS156
D15
VSS157
D18
VSS158
D21
VSS159
D24
VSS160
D3
VSS161
D5
VSS162
D6
VSS163
D9
VSS164
E11
VSS165
E14
VSS166
E17
VSS167
E2
VSS168
E20
VSS169
E25
VSS170
E26
VSS171
E27
VSS172
E28
VSS173
E8
VSS174
F10
VSS175
F13
VSS176
F16
VSS177
F19
VSS178
F22
VSS179
F4
VSS180
F7
VSS181
H10
VSS182
H11
VSS183
H12
VSS184
H13
VSS185
H14
VSS186
H17
VSS187
H18
VSS188
H19
VSS189
H20
VSS190
H21
VSS191
H22
VSS192
H23
VSS193
H24
VSS194
H25
VSS195
H26
VSS196
H27
VSS197
H28
VSS198
H3
VSS199
H6
VSS200
REV=1.3
REV=1.3
VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265
2
Y7 Y5 Y2 W7 W4 V7 V6 V30 V3 V29 V28 V27 V26 V25 V24 V23 U7 T7 T6 T3 R7 R5 R30 R29 R28 R27 R26 R25 R24 R23 R2 P7 P4 P30 P29 P28 P27 P26 P25 P24 P23 N7 N6 N3 M7 M1 L7 L6 L30 L3 L29 L28 L27 L26 L25 L24 L23 K7 K5 K2 J7 J4 H9 H8 H7
I
I
XU1I
XU1I
SOCKET775/ATX
SOCKET775/ATX
1
RM_POST_NC1
2
RM_POST_NC2
3
RM_POST_NC3
4
RM_POST_NC4
REV=1.3
REV=1.3
GND
ASUS OEM-DT MB RESTRICTED SECRET
INTEL LGA-775 3 - 3
INTEL LGA-775 3 - 3
INTEL LGA-775 3 - 3
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Engineer:
IPM41-D3
IPM41-D3
IPM41-D3
1
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
8 55Thursday, July 09, 2009
8 55Thursday, July 09, 2009
8 55Thursday, July 09, 2009
Rev
Rev
Rev
1.00G
1.00G
1.00G
5
4
3
2
1
INTEL LGA-775 PROCESSOR ITP DEBUG PORT
BPM0#[7] BPM1#[7]
0 Ohm
0 Ohm 0 Ohm
0 Ohm 0 Ohm
0 Ohm 0 Ohm
0 Ohm
BPM2#[7] BPM3#[7]
GRN1A GRN1B GRN1C GRN1D
ITP_SMBDATA
XDP
XDP
9
BPM0#
7
BPM1#
6
BPM2#
4
BPM3#
3
BPM4#
1
BPM5#
13
BCLK0
15
BCKL1
16
GCLKp
18
GCLKn
22
SCL
24
SDA
PWRGOOD
TDO
TMS TCK
TRST#
RESET#
DBR#
23 29
TDI
31 30 25
CPUPWRGD
10
CPURST_ITP#
19
MR_R#ITP_SMBCLK
21
TDO [7] TDI [7] TMS [7] TCK [7] TRST# [7]
CPUPWRGD [7,21]
CPURESET# [6,10,51]
SYS_RESET# [7,21,38,44]
D D
5%NI GRN1A
5%NI
H_BPM0_2[7] H_BPM1_2[7] H_BPM2_2[7] H_BPM3_2[7] BPM4#[7] BPM5#[7]
CK_ITP[5] CK_ITP#[5]
C C
SMB_CLK_R[5,17,18,21,24,25,28,29] SMB_DATA_R[5,17,18,21,24,25,28,29]
1 2
5%NI GRN1B
5%NI
3 4
5%NI GRN1C
5%NI
5 6
5%NI GRN1D
5%NI
7 8
GND1 GND5 GND2 GND6 GND7 GND3 GND4 GND8
12
2 5 8 11 17 20 26 27
GND
28
NC
+VTT_OUT_R
14
VTT
12
NI/PROTO/ITP
NI/PROTO/ITP
GCB1
GND
GCB1
0.1UF/16V
0.1UF/16V
BtoB_CON_31P
BtoB_CON_31P
NI/PROTO
NI/PROTO
B B
RESERVED
PEGATRON P/N: 12X64A531W00
A A
ASUS OEM-DT MB RESTRICTED SECRET
ITP_31P CONN.
ITP_31P CONN.
ITP_31P CONN.
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
5
4
3
2
Engineer:
IPM41-D3
IPM41-D3
IPM41-D3
1
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
9 55Thursday, April 29, 2010
9 55Thursday, April 29, 2010
9 55Thursday, April 29, 2010
Rev
Rev
Rev
1.00G
1.00G
1.00G
5
I
I
NU1A
H39
N39 N35 N37
N40 M45 R35
R36 R34 R37 R39 U38
U34 U40
Y36 U35
AA35
U37 Y37 Y34
Y38 AA37 AA36
G38
K35
C43
G39
C39
B39
B40
K31
K25
C32
D32
D30
G44
K44
H45
H40
H37
H42
G43
G42
D27
P30
P29
N25
L36 L37 J38 F40
L38 L43
J41
T36
T37
T34
J39
J40 T39
J31 F33
J25
F26
J42 L40 J43
L42 J44
L44
NU1A
HA3# HA4# HA5# HA6# HA7# HA8# HA9# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31# HA32# HA33# HA34# HA35#
HREQ0# HREQ1# HREQ2# HREQ3# HREQ4#
HADSTB0# HADSTB1#
HDSTBP0# HDSTBN0# HDINV#0
HDSTBP1# HDSTBN1# HDINV#1
HDSTBP2# HDSTBN2# HDINV#2
HDSTBP3# HDSTBN3# HDINV#3
HADS# HTRDY# HDRDY# HDEFER# HITM# HIT# HLOCK# HBREQ0# HBNR# HBPRI# HDBSY#
HRS0# HRS1# HRS2#
HCPURST#
HCLKN HCLKP
RESERVED
EAGLELAKE
EAGLELAKE
FSB
FSB
REV=1.4
REV=1.4
HSWING
HRCOMP
HDVREF
HACCVREF
HA#[3..35][6] HD#[0..63] [6]
D D
C C
HREQ#[0..4][6]
HADSTB0#[6] HADSTB1#[6]
HDSTBP0#[6] HDSTBN0#[6] HDBI0#[6]
HDSTBP1#[6] HDSTBN1#[6] HDBI1#[6]
HDSTBP2#[6] HDSTBN2#[6] HDBI2#[6]
HDSTBP3#[6] HDSTBN3#[6] HDBI3#[6]
B B
A A
HADS#[6] HTRDY#[6] HDRDY#[6] HDEFER#[6] HITM#[6] HIT#[6] HLOCK#[6] HBREQ0#[6] HBNR#[6] HBPRI#[6] HDBSY#[6]
HRS#[0..2][6]
CPURESET#[6,9,51]
CK_FSB_NB#[5] CK_FSB_NB[5]
HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31 HA#32 HA#33 HA#34 HA#35
HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4
HRS#0 HRS#1 HRS#2
5
HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8
HD9 HD10 HD11 HD12 HD13 HD14 HD15 HD16 HD17 HD18 HD19 HD20 HD21 HD22 HD23 HD24 HD25 HD26 HD27 HD28 HD29 HD30 HD31 HD32 HD33 HD34 HD35 HD36 HD37 HD38 HD39 HD40 HD41 HD42 HD43 HD44 HD45 HD46 HD47 HD48 HD49 HD50 HD51 HD52 HD53 HD54 HD55 HD56 HD57 HD58 HD59 HD60 HD61 HD62 HD63
F44 C44 D44 C41 E43 B43 D40 B42 B38 F38 A38 B37 D38 C37 D37 B36 E37 J35 H35 F37 G37 J33 L33 G33 L31 M31 M30 J30 G31 K30 M29 G30 J29 F29 H29 L25 K26 L29 J26 M26 H26 F25 F24 G25 H24 L24 J24 N24 C28 B31 F35 C35 B35 D35 D31 A34 B32 F31 D28 A29 C30 B30 E27 B28
B24
A23
C22 B23
4
4
3
HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63
HXSWING
HXRCOMP
12
GND
MCH_GTLREF0
12
GND GND GND
MCH_GTLREF0 W/S=10/7
MCH_GTLREF0 W/S=10/7
MCH_GTLREF0 W/S=10/7MCH_GTLREF0 W/S=10/7
HXSWING W/S=10/10
HXSWING W/S=10/10
HXSWING W/S=10/10HXSWING W/S=10/10
HXRCOMP W/S=10/7
HXRCOMP W/S=10/7
HXRCOMP W/S=10/7HXRCOMP W/S=10/7
10/07 modify
I
I
NR5
NR5
16.5
16.5
1%
1%
10/07 modify
NI
NI
NCB2
NCB2 220PF/50V
220PF/50V
X7R 10%
X7R 10%
SDVO_CTRL_DATA
1
SDVO CARD PRESENT, PEG DISABLE
SDVO DISABLE(DEFAULT)
0
02G010024100 C.S EAGLELAKE 82G41 A-3 G41
+1P1V_FSB_VTT
12
I
I
NR4
NR4
49.9 1%
49.9 1%
I
I
NR8
NR8
49.9 1%
49.9 1%
12
12
HXSWING_R
12
I
I
NCB1
NCB1
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
R_MCH_GTLREF0
12
I
I
NCB3
NCB3 1UF/16V
1UF/16V
X7R 10%
X7R 10% mx_c0603
mx_c0603
12
GND
3
I
I
NR3
NR3 301
301
1%
1%
I
I
NR6
NR6 100
100
1%
1%
+1P1V_FSB_VTT
12
I
I
NR7
NR7
49.9
49.9
1%
1%
12
I
I
NR9
NR9 100
100
1%
1%
CK_100M_MCH[5] CK_100M_MCH#[5]
SDVO_CTRL_DATA[24] SDVO_CTRL_CLK[24]
9/9 modify
2
I
I
NU1B
NU1B
SDVO
D9
EXP_CLKINP
E9
EXP_CLKINN
J13
SDVO_CTRLDATA
G13
SDVO_CTRLCLK
AB13
RESERVED3
AD13
RESERVED4
N10
R10 U10
AA9
AA10
AA7 AA6
AB10
AB9 AB3
AA2 AD10 AD11
AD7
AD8
AE9 AE10
AE6
AE7
AF9
AF8
F6
G7
H6
G4
J6 J7 L6 L7
N9
N7 N6 R7 R6 R9
U9 U6 U7
R4 P4
PEG_RXP_0 PEG_RXN_0 PEG_RXP_1 PEG_RXN_1 PEG_RXP_2 PEG_RXN_2 PEG_RXP_3 PEG_RXN_3 PEG_RXP_4 PEG_RXN_4 PEG_RXP_5 PEG_RXN_5 PEG_RXP_6 PEG_RXN_6 PEG_RXP_7 PEG_RXN_7 PEG_RXP_8 PEG_RXN_8 PEG_RXP_9 PEG_RXN_9 PEG_RXP_10 PEG_RXN_10 PEG_RXP_11 PEG_RXN_11 PEG_RXP_12 PEG_RXN_12 PEG_RXP_13 PEG_RXN_13 PEG_RXP_14 PEG_RXN_14 PEG_RXP_15 PEG_RXN_15
DMI_RXP0 DMI_RXN0 DMI_RXP1 DMI_RXN1 DMI_RXP2 DMI_RXN2 DMI_RXP3 DMI_RXN3
EAGLELAKE
EAGLELAKE
EXP_RXP0[24] EXP_RXN0[24] EXP_RXP1[24] EXP_RXN1[24] EXP_RXP2[24] EXP_RXN2[24] EXP_RXP3[24] EXP_RXN3[24] EXP_RXP4[24] EXP_RXN4[24] EXP_RXP5[24] EXP_RXN5[24] EXP_RXP6[24] EXP_RXN6[24] EXP_RXP7[24] EXP_RXN7[24] EXP_RXP8[24] EXP_RXN8[24] EXP_RXP9[24] EXP_RXN9[24] EXP_RXP10[24] EXP_RXN10[24] EXP_RXP11[24] EXP_RXN11[24] EXP_RXP12[24] EXP_RXN12[24] EXP_RXP13[24] EXP_RXN13[24] EXP_RXP14[24] EXP_RXN14[24] EXP_RXP15[24] EXP_RXN15[24]
DMI_RXP0[20] DMI_RXN0[20] DMI_RXP1[20] DMI_RXN1[20] DMI_RXP2[20] DMI_RXN2[20] DMI_RXP3[20] DMI_RXN3[20]
SDVO
PCIE
PCIE
DMI
DMI
REV=1.4
REV=1.4
EXP_RCOMPO
EXP_COMPI
EXP_ICOMPO
EXP_RBIAS
PEG_TXP0 PEG_TXN0 PEG_TXP1 PEG_TXN1 PEG_TXP2 PEG_TXN2 PEG_TXP3 PEG_TXN3 PEG_TXP4 PEG_TXN4 PEG_TXP5 PEG_TXN5 PEG_TXP6 PEG_TXN6 PEG_TXP7 PEG_TXN7 PEG_TXP8 PEG_TXN8 PEG_TXP9
PEG_TXN9 PEG_TXP10 PEG_TXN10 PEG_TXP11 PEG_TXN11 PEG_TXP12 PEG_TXN12 PEG_TXP13 PEG_TXN13 PEG_TXP14 PEG_TXN14 PEG_TXP15 PEG_TXN15
DMI_TXP0 DMI_TXN0 DMI_TXP1 DMI_TXN1 DMI_TXP2 DMI_TXN2 DMI_TXP3 DMI_TXN3
Y7 Y8 Y6
AG1
C11 B11 A10 B9 C9 D8 B8 C7 B7 B6 B3 B4 D2 C2 H2 G2 J2 K2 K1 L2 P2 M2 T2 R1 U2 V2 W4 V3 AA4 Y4 AC1 AB2
NOTE:
Check Eaglelake PDG for detai if wanna support Integrated HDMI/DVI/DP
AC2
1 2
AD2 AD4
1 2
AE4 AE2 AF2
1 2 AF4 AG4
1 2
+1P1V_CORE
EXP_RCOMP
EXP_RBIAS
12
GND
NCB66
NCB66
NCB68
NCB68
NCB78
NCB78
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
NCB80
NCB80
0.1UF/16V
0.1UF/16V
I
I
X7R 10%
X7R 10%
0.1UF/16V
0.1UF/16V
I
I
X7R 10%
X7R 10%
0.1UF/16V
0.1UF/16V
I
I
X7R 10%
X7R 10%
I
I
1
12
I
I
NR1
NR1
49.9
49.9
1%
1%
NOTE:
Breakout W/S:10/6 W/S:10/10
I
I
NR2
NR2 750
750
1%
1%
EXP_TXP0 [24] EXP_TXN0 [24] EXP_TXP1 [24] EXP_TXN1 [24] EXP_TXP2 [24] EXP_TXN2 [24] EXP_TXP3 [24] EXP_TXN3 [24] EXP_TXP4 [24] EXP_TXN4 [24] EXP_TXP5 [24] EXP_TXN5 [24] EXP_TXP6 [24] EXP_TXN6 [24] EXP_TXP7 [24] EXP_TXN7 [24] EXP_TXP8 [24] EXP_TXN8 [24] EXP_TXP9 [24] EXP_TXN9 [24] EXP_TXP10 [24] EXP_TXN10 [24] EXP_TXP11 [24] EXP_TXN11 [24] EXP_TXP12 [24] EXP_TXN12 [24] EXP_TXP13 [24] EXP_TXN13 [24] EXP_TXP14 [24] EXP_TXN14 [24] EXP_TXP15 [24] EXP_TXN15 [24]
NCB26
NCB26
1 2
1 2
1 2
1 2
NCB67
NCB67
NCB77
NCB77
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
NCB79
NCB79
0.1UF/16V
0.1UF/16V
I
I
X7R 10%
X7R 10%
0.1UF/16V
0.1UF/16V
I
I
X7R 10%
X7R 10%
0.1UF/16V
0.1UF/16V
I
I
X7R 10%
X7R 10%
I
I
DMI_TXP0 [2 0] DMI_TXN0 [20] DMI_TXP1 [2 0] DMI_TXN1 [20] DMI_TXP2 [2 0] DMI_TXN2 [20] DMI_TXP3 [2 0] DMI_TXN3 [20]
ASUS OEM-DT MB RESTRICTED SECRET
EAGLELAKE 1- 7
EAGLELAKE 1- 7
EAGLELAKE 1- 7
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
2
Engineer:
IPM41-D3
IPM41-D3
IPM41-D3
1
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
10 55Thursday, July 09, 2009
10 55Thursday, July 09, 2009
10 55Thursday, July 09, 2009
Rev
Rev
Rev
1.00G
1.00G
1.00G
5
M_CHA_MAA[1..14][17]
D D
M_CHA_CAS#[17] M_CHA_RAS#[17]
M_CHA_BA0[17] M_CHA_BA1[17] M_CHA_BA2[17]
M_CHA_CS#0[17]
NOBOM
NOBOM
1
M_CHA_CKE0[17] M_CHA_CKE1[17]
M_CHA_ODT0[17]
C C
B B
A A
5
M_CHA_ODT1[17]
M_CHA_CLK0[17] M_CHA_CLK0#[17]
M_CHA_CLK2[17] M_CHA_CLK2#[17]
NOBOM
NOBOM
NOBOM
NOBOM NOBOM
NOBOM
NOBOM
NOBOM NOBOM
NOBOM NOBOM
NOBOM
1
1 1
1 1 1
HT8
HT8
HT11
HT11
HT15
HT15 HT16
HT16
HT18
HT18 HT19
HT19 HT20
HT20
4
M_CHA_MAA1 M_CHA_MAA2 M_CHA_MAA3 M_CHA_MAA4 M_CHA_MAA5 M_CHA_MAA6 M_CHA_MAA7 M_CHA_MAA8 M_CHA_MAA9 M_CHA_MAA10 M_CHA_MAA11 M_CHA_MAA12 M_CHA_MAA13 M_CHA_MAA14
N27146510
N27146424
N27146426 N27146514
N27146515 N27146428 N27146516
4
BC41 BC35 BB32 BC32 BD32 BB31 AY31 BA31 BD31 BD30
AW43
BC30 BB30 AM42 BD28
AW42
AU42 AV42
AV45 AY44 BC28
AU43 AR40 AU44 AM43
BB27 BD27 BA27 AY26
AR42 AM44 AR44
AL40
AY37 BA37
AW29
AY29 AU37 AV37 AU33 AT33 AT30 AR30
AW38
AY38
I
I
NU1C
NU1C
SMA_A0 SMA_A1 SMA_A2 SMA_A3 SMA_A4 SMA_A5 SMA_A6 SMA_A7 SMA_A8 SMA_A9 SMA_A10 SMA_A11 SMA_A12 SMA_A13 SMA_A14
SWE_A# SCAS_A# SRAS_A#
SBS_A0 SBS_A1 SBS_A2
SCS_A0# SCS_A1# SCS_A2# SCS_A3#
SCKE_A0 SCKE_A1 SCKE_A2 SCKE_A3
SODT_A0 SODT_A1 SODT_A2 SODT_A3
SCLK_A0 SCLK_A0# SCLK_A1 SCLK_A1# SCLK_A2 SCLK_A2# SCLK_A3 SCLK_A3# SCLK_A4 SCLK_A4# SCLK_A5 SCLK_A5#
DDR_A
DDR_A
EAGLELAKE
EAGLELAKE
REV=1.4
REV=1.4
SDQS_A0
SDQS_A0#
SDM_A0
SDQ_A0 SDQ_A1 SDQ_A2 SDQ_A3 SDQ_A4 SDQ_A5 SDQ_A6 SDQ_A7
SDQS_A1
SDQS_A1#
SDM_A1
SDQ_A8
SDQ_A9 SDQ_A10 SDQ_A11 SDQ_A12 SDQ_A13 SDQ_A14 SDQ_A15
SDQS_A2
SDQS_A2#
SDM_A2
SDQ_A16 SDQ_A17 SDQ_A18 SDQ_A19 SDQ_A20 SDQ_A21 SDQ_A22 SDQ_A23
SDQS_A3
SDQS_A3#
SDM_A3
SDQ_A24 SDQ_A25 SDQ_A26 SDQ_A27 SDQ_A28 SDQ_A29 SDQ_A30 SDQ_A31
SDQS_A4
SDQS_A4#
SDM_A4
SDQ_A32 SDQ_A33 SDQ_A34 SDQ_A35 SDQ_A36 SDQ_A37 SDQ_A38 SDQ_A39
SDQS_A5
SDQS_A5#
SDM_A5
SDQ_A40 SDQ_A41 SDQ_A42 SDQ_A43 SDQ_A44 SDQ_A45 SDQ_A46 SDQ_A47
SDQS_A6
SDQS_A6#
SDM_A6
SDQ_A48 SDQ_A49 SDQ_A50 SDQ_A51 SDQ_A52 SDQ_A53 SDQ_A54 SDQ_A55
SDQS_A7
SDQS_A7#
SDM_A7
SDQ_A56 SDQ_A57 SDQ_A58 SDQ_A59 SDQ_A60 SDQ_A61 SDQ_A62 SDQ_A63
BC5 BD4 BC3
BC2 BD3 BD7 BB7 BB2 BA3 BE6 BD6
BB9 BC9 BD9
BB8 AY8 BD11 BB11 BC7 BE8 BD10 AY11
BD15 BB15 BD14
BB14 BC14 BC16 BB16 BC11 BE12 BA15 BD16
AR22 AT22 AV22
AW21 AY22 AV24 AY24 AU21 AT21 AR24 AU24
AH43 AH42 AK42
AL41 AK43 AG42 AG44 AL42 AK44 AH44 AG41
AD43 AE42 AE45
AF43 AF42 AC44 AC42 AF40 AF44 AD44 AC41
Y43 Y42 AA45
AB43 AA42 W42 W41 AB42 AB44 Y44 Y40
T44 T43 T42
V42 U45 R40 P44 V44 V43 R41 R44
3
M_CHA_DQ0 M_CHA_DQ1 M_CHA_DQ2 M_CHA_DQ3 M_CHA_DQ4 M_CHA_DQ5 M_CHA_DQ6 M_CHA_DQ7
M_CHA_DQ8 M_CHA_DQ9 M_CHA_DQ10 M_CHA_DQ11 M_CHA_DQ12 M_CHA_DQ13 M_CHA_DQ14 M_CHA_DQ15
M_CHA_DQ16 M_CHA_DQ17 M_CHA_DQ18 M_CHA_DQ19 M_CHA_DQ20 M_CHA_DQ21 M_CHA_DQ22 M_CHA_DQ23
M_CHA_DQ24 M_CHA_DQ25 M_CHA_DQ26 M_CHA_DQ27 M_CHA_DQ28 M_CHA_DQ29 M_CHA_DQ30 M_CHA_DQ31
M_CHA_DQ32 M_CHA_DQ33 M_CHA_DQ34 M_CHA_DQ35 M_CHA_DQ36 M_CHA_DQ37 M_CHA_DQ38 M_CHA_DQ39
M_CHA_DQ40 M_CHA_DQ41 M_CHA_DQ42 M_CHA_DQ43 M_CHA_DQ44 M_CHA_DQ45 M_CHA_DQ46 M_CHA_DQ47
M_CHA_DQ48 M_CHA_DQ49 M_CHA_DQ50 M_CHA_DQ51 M_CHA_DQ52 M_CHA_DQ53 M_CHA_DQ54 M_CHA_DQ55
M_CHA_DQ56 M_CHA_DQ57 M_CHA_DQ58 M_CHA_DQ59 M_CHA_DQ60 M_CHA_DQ61 M_CHA_DQ62 M_CHA_DQ63
3
M_CHA_DQS0 [17] M_CHA_DQS0# [17] M_CHA_DM0 [17]
M_CHA_DQS1 [17] M_CHA_DQS1# [17] M_CHA_DM1 [17]
M_CHA_DQS2 [17] M_CHA_DQS2# [17] M_CHA_DM2 [17]
M_CHA_DQS3 [17] M_CHA_DQS3# [17] M_CHA_DM3 [17]
M_CHA_DQS4 [17] M_CHA_DQS4# [17] M_CHA_DM4 [17]
M_CHA_DQS5 [17] M_CHA_DQS5# [17] M_CHA_DM5 [17]
M_CHA_DQS6 [17] M_CHA_DQS6# [17] M_CHA_DM6 [17]
M_CHA_DQS7 [17] M_CHA_DQS7# [17] M_CHA_DM7 [17]
2
M_CHA_DQ[0..63] [17]
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
2
1
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
IPM41-D3
IPM41-D3
IPM41-D3
1
EAGELLAKE 2 - 7
EAGELLAKE 2 - 7
EAGELLAKE 2 - 7
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
11 55Thursday, July 09, 2009
11 55Thursday, July 09, 2009
11 55Thursday, July 09, 2009
Rev
Rev
Rev
1.00
1.00
1.00
5
M_CHB_MAA[0..14][18]
D D
C C
DDR_REF NEED ROUTING Width/Spacing: 12/12 mils
+1P5V_DUAL
12
NI
NI
NCB4
NCB4
0.1UF/16V
B B
0.1UF/16V
GND
12
I
I
NR11
NR11 1K
1K
1%
1%
12
I
I
NR12
NR12 1K
1K
1%
1%
GND GND GND
12
I
I
NCB115
NCB115 1UF/10V
1UF/10V
mx_c0603
mx_c0603
090420 add by TSL
12
I
I
NCB5
NCB5
0.1UF/16V
0.1UF/16V
MCH_DDR_RPU, MCH_DDR_RPD, MCH_DDR_SPU, MCH_DDR_SPD
NEED ROUTING LESS THEN 1000MIL LENGTH.
WIDTH/SPACING = 10/10 MIL
A A
5
4
M_CHB_WE#[18] M_CHB_CAS#[18] M_CHB_RAS#[18]
M_CHB_BA0[18] M_CHB_BA1[18] M_CHB_BA2[18]
M_CHB_CS#0[18] M_CHB_CS#1[18]
NOBOM
NOBOM
M_CHB_CKE0[18] M_CHB_CKE1[18]
NOBOM
NOBOM NOBOM
NOBOM
M_CHB_ODT0[18] M_CHB_ODT1[18]
NOBOM
NOBOM
M_CHB_CLK0[18] M_CHB_CLK0#[18]
NOBOM
NOBOM NOBOM
NOBOM
M_CHB_CLK2[18] M_CHB_CLK2#[18]
NOBOM
NOBOM NOBOM
NOBOM NOBOM
NOBOM NOBOM
NOBOM
NOBOM
NOBOM
M_CHA_CS#1[17] M_CHA_MAA0[17] M_CHA_WE#[17]
DDR3_DRAM_PWROK[19]
DDR3_DRAMRST#[17,18]
NOBOM
NOBOM NOBOM
NOBOM
+1P5V_DUAL
1 2
12
I
I
NCB6
NCB6
0.1UF/16V
0.1UF/16V
GND GND
+1P5V_DUAL
1 2
12
I
I
NCB7
NCB7
0.1UF/16V
0.1UF/16V
GND GND
4
I
I
NR13
NR13
80.6
80.6
1%
1%
I
I
NR15
NR15
80.6
80.6
1%
1%
HT25
HT25
1
HT26
HT26
1
HT27
HT27
1
HT29
HT29
1
HT30
HT30
1
HT31
HT31
1
HT32
HT32
1
HT33
HT33
1
HT34
HT34
1
HT35
HT35
1
HT37
HT37
1
HT39
HT39
1
HT40
HT40
1
M_CHB_MAA0 M_CHB_MAA1 M_CHB_MAA2 M_CHB_MAA3 M_CHB_MAA4 M_CHB_MAA5 M_CHB_MAA6 M_CHB_MAA7 M_CHB_MAA8 M_CHB_MAA9 M_CHB_MAA10 M_CHB_MAA11 M_CHB_MAA12 M_CHB_MAA13 M_CHB_MAA14
N27146430
N27146431 N27146432
N27146434
N27146435 N27146436
N27146437 N27146438 N27146439 N27146440
N27146442
N27146445 N27146446
MCH_DDR_RPD
12
I
I
NR14
NR14
80.6
80.6
1%
1%
MCH_DDR_SPD
12
I
I
NR16
NR16 249
249
1%
1%
DDR_VREF
MCH_DDR_RPU
MCH_DDR_SPU
I
I
NU1D
NU1D
False
BD24
SMA_B0
BB23
SMA_B1
BB24
SMA_B2
BD23
SMA_B3
BB22
SMA_B4
BD22
SMA_B5
BC22
SMA_B6
BC20
SMA_B7
BB20
SMA_B8
BD20
SMA_B9
BC26
SMA_B10
BD19
SMA_B11
BB19
SMA_B12
BE38
SMA_B13
BA19
SMA_B14
BD36
SWE_B#
BC37
SCAS_B#
BD35
SRAS_B#
BD26
SBS_B0
BB26
SBS_B1
BD18
SBS_B2
BB35
SCS_B0#
BD39
SCS_B1#
BB37
SCS_B2#
BD40
SCS_B3#
BC18
SCKE_B0
AY20
SCKE_B1
BE17
SCKE_B2
BB18
SCKE_B3
BD37
SODT_B0
BC39
SODT_B1
BB38
SODT_B2
BD42
SODT_B3
AY33
SCLK_B0
AW33
SCLK_B0#
AV31
SCLK_B1
AW31
SCLK_B1#
AW35
SCLK_B2
AY35
SCLK_B2#
AT31
SCLK_B3
AU31
SCLK_B3#
AP31
SCLK_B4
AP30
SCLK_B4#
AW37
SCLK_B5
AV35
SCLK_B5#
AR43
DDR3_A_CSB1
BB40
DDR3_A_MA0
AT44
DDR3_A_WEB
AV40
DDR3_B_ODT3
AR6
DDR3_DRAM_PWROK
BC24
DDR3_DRAMRSTB
AN29
RESERVED5
AN30
RESERVED6
AJ33
RESERVED7
AK33
RESERVED8
BB44
DDR_VREF
BA43
DDR_RPU
AY42
DDR_RPD
BC44
DDR_SPU
BC43
DDR_SPD
EAGLELAKE
EAGLELAKE
DDR_B
DDR_B
3
REV=1.4
REV=1.4
3
SDQS_B0
SDQS_B0#
SDM_B0
SDQ_B0 SDQ_B1 SDQ_B2 SDQ_B3 SDQ_B4 SDQ_B5 SDQ_B6 SDQ_B7
SDQS_B1
SDQS_B1#
SDM_B1
SDQ_B8
SDQ_B9 SDQ_B10 SDQ_B11 SDQ_B12 SDQ_B13 SDQ_B14 SDQ_B15
SDQS_B2
SDQS_B2#
SDM_B2
SDQ_B16 SDQ_B17 SDQ_B18 SDQ_B19 SDQ_B20 SDQ_B21 SDQ_B22 SDQ_B23
SDQS_B3
SDQS_B3#
SDM_B3
SDQ_B24 SDQ_B25 SDQ_B26 SDQ_B27 SDQ_B28 SDQ_B29 SDQ_B30 SDQ_B31
SDQS_B4
SDQS_B4#
SDM_B4
SDQ_B32 SDQ_B33 SDQ_B34 SDQ_B35 SDQ_B36 SDQ_B37 SDQ_B38 SDQ_B39
SDQS_B5
SDQS_B5#
SDM_B5
SDQ_B40 SDQ_B41 SDQ_B42 SDQ_B43 SDQ_B44 SDQ_B45 SDQ_B46 SDQ_B47
SDQS_B6
SDQS_B6#
SDM_B6
SDQ_B48 SDQ_B49 SDQ_B50 SDQ_B51 SDQ_B52 SDQ_B53 SDQ_B54 SDQ_B55
SDQS_B7
SDQS_B7#
SDM_B7
SDQ_B56 SDQ_B57 SDQ_B58 SDQ_B59 SDQ_B60 SDQ_B61 SDQ_B62 SDQ_B63
AW8 AW9 AY6
AV7 AW4 BA9 AU11 AU7 AU8 AW7 AY9
AT15 AU15 AR15
AY13 AP15 AW15 AT16 AU13 AW13 AP16 AU16
AR20 AR17 AU17
AY17 AV17 AR21 AV20 AP17 AW16 AT20 AN20
AU26 AT26 AV25
AT25 AV26 AU29 AV29 AW25 AR25 AP26 AR29
AR38 AR37 AU39
AR36 AU38 AN35 AN37 AV39 AW39 AU40 AU41
AK34 AL34 AL37
AL35 AL36 AK36 AJ34 AN39 AN40 AK37 AL39
AF37 AF36 AJ35
AJ38 AJ37 AF38 AE37 AK40 AJ40 AF34 AE35
AB35 AD35 AD37
AD40 AD38 AB40 AA39 AE36 AE39 AB37 AB38
M_CHB_DQ0 M_CHB_DQ1 M_CHB_DQ2 M_CHB_DQ3 M_CHB_DQ4 M_CHB_DQ5 M_CHB_DQ6 M_CHB_DQ7
M_CHB_DQ8 M_CHB_DQ9 M_CHB_DQ10 M_CHB_DQ11 M_CHB_DQ12 M_CHB_DQ13 M_CHB_DQ14 M_CHB_DQ15
M_CHB_DQ16 M_CHB_DQ17 M_CHB_DQ18 M_CHB_DQ19 M_CHB_DQ20 M_CHB_DQ21 M_CHB_DQ22 M_CHB_DQ23
M_CHB_DQ24 M_CHB_DQ25 M_CHB_DQ26 M_CHB_DQ27 M_CHB_DQ28 M_CHB_DQ29 M_CHB_DQ30 M_CHB_DQ31
M_CHB_DQ32 M_CHB_DQ33 M_CHB_DQ34 M_CHB_DQ35 M_CHB_DQ36 M_CHB_DQ37 M_CHB_DQ38 M_CHB_DQ39
M_CHB_DQ40 M_CHB_DQ41 M_CHB_DQ42 M_CHB_DQ43 M_CHB_DQ44 M_CHB_DQ45 M_CHB_DQ46 M_CHB_DQ47
M_CHB_DQ48 M_CHB_DQ49 M_CHB_DQ50 M_CHB_DQ51 M_CHB_DQ52 M_CHB_DQ53 M_CHB_DQ54 M_CHB_DQ55
M_CHB_DQ56 M_CHB_DQ57 M_CHB_DQ58 M_CHB_DQ59 M_CHB_DQ60 M_CHB_DQ61 M_CHB_DQ62 M_CHB_DQ63
2
M_CHB_DQS0 [18] M_CHB_DQS0# [18] M_CHB_DM0 [18]
M_CHB_DQS1 [18] M_CHB_DQS1# [18] M_CHB_DM1 [18]
M_CHB_DQS2 [18] M_CHB_DQS2# [18] M_CHB_DM2 [18]
M_CHB_DQS3 [18] M_CHB_DQS3# [18] M_CHB_DM3 [18]
M_CHB_DQS4 [18] M_CHB_DQS4# [18] M_CHB_DM4 [18]
M_CHB_DQS5 [18] M_CHB_DQS5# [18] M_CHB_DM5 [18]
M_CHB_DQS6 [18] M_CHB_DQS6# [18] M_CHB_DM6 [18]
M_CHB_DQS7 [18] M_CHB_DQS7# [18] M_CHB_DM7 [18]
2
1
M_CHB_DQ[0..63] [18]
EAGLELAKE 3 - 7
EAGLELAKE 3 - 7
EAGLELAKE 3 - 7
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Engineer:
IPM41-D3
IPM41-D3
IPM41-D3
1
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
12 55Thursday, July 09, 2009
12 55Thursday, July 09, 2009
12 55Thursday, July 09, 2009
Rev
Rev
Rev
1.00
1.00
1.00
5
5%I NRN1A
5%I
M_HBSEL0[5 ,7] M_HBSEL1[5 ,7] M_HBSEL2[5 ,7]
1 2
5%I NRN1B
5%I
3 4
5%I NRN1C
5%I
5 6
1KOHM
1KOHM 1KOHM
1KOHM 1KOHM
1KOHM
4
NRN1A NRN1B NRN1C
G16 P15
F17
I
I
NU1E
NU1E
BSEL0 BSEL1 BSEL2
3
CRT_HSYNC CRT_VSYNC
VGA_HSYNC_3P3V
D14
VGA_VSYNC_3P3V
C14
2
NOTE:
Install NR67 NR68 and NOT Install NR18 NR21 for non-Graphics SKU
NR18 33
NR18 33
I
I
1 2
NR21 33
NR21 33
I
I
1 2
VGA_HSYNC [26] VGA_VSYNC [26]
1
EXP_EN
D D
NR661K
NR661K
NI
NI
PCIE_B7[24]
EXP_EN_HDR[24]
1 2
NOBOM
NOBOM
12
NR760
NR760
12
12
NI
NI
NI
NI
NR30
NR30
NR75
NR75
1K
1K
1K
1K
GNDGND
12
12
NI
NI
NR32
NR32 1K
1K
NI
NI
NR22
NR22 1K
1K
12
12
NI
NI
NI
NI
NR23
NR23
NR24
NR24
1K
1K
1K
1K
DUALX8_EN
X16_OCC EXP_SM EXP_SLR ITPM_EN# TCEN
12
NI
NI
NR28
NR28 1K
1K
GNDGNDGND GND GND
NOTE:
HIGH DESCRIPTIONLOWPIN
C C
DUALX8 1x16 PCIe 2x8 PCIe DUALX8 ENABLE
X16_OCC NOT
EXP_SLR
ITPM_EN#
B B
PWROK[21,38]
CONCURRENT
PRESENCE NORMAL ATX
ENABLE
+1P1V_CORE
GND GND
CONCURRENT
PRESENCE PCIe CARD IN
BTX
DISABLETCEN TLS CONFIDENTALITY
12
I
I
NR35
NR35 1K
1K
CLINK VREF TARGET=0.349V
1%
1%
I
I
NR38
NR38 464OHM
464OHM
1%
1%
1 2
12
I
I
NCB8
NCB8
0.1UF/16V
0.1UF/16V
PCI-E/SDVOEXP_SM NOT
PRIMARY SLOT PCI-E LANE RESERVALRESERVE
iTPM EnableENABLEDISABLE
LRESET#[21,37,39]
I
1 2
CL_VREF
NR803KINR803K
12
I
I
NR81
NR81
1.5K
1.5K
GND
NOTE:
Install NR45 for non-iAMT support
G15
M20 N17 K16 H17
AN17
A44 BD1
BD45
BE2
BE44
B14
B45 AK15 AD42 AN16
W30
AW44
R42
U32
M17
G20
M16
AR7 AN10 AN11
AN9
R31
R32
U30
U31
R15
R14
AB15
AN13
AY4
AY2
AW2
AN8
F20
F15 L17 J17
J16
J15 J20
T15 T14
L13 L11
RESERVED9 DUALX8_ENABLE ALLZTEST XORTEST RSVD EXP_SM EXP_SLR ITPM_EN# CEN
NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15
RESERVED10 BSCANTEST RESERVED12 RESERVED13 RESERVED14 RESERVED16 JTAG_TDI JTAG_TDO JTAG_TCK JTAG_TMS RESERVED22 RESERVED23 RESERVED24 RESERVED25 RESERVED26 RESERVED27 RESERVED28 RESERVED29 RESERVED30 RESERVED32 RESERVED33
CL_VREF CL_DATA CL_CLK CL_RST# CL_PWROK
CRT_DDC_DATA
DPL_REFSSCLKP
DPL_REFSSCLKN
MISC
MISC
DDPC_CTRLCLK
DDPC_CTRLDATA
CRT_RED
CRT_GREEN
CRT_BLUE
CRT_IRTN
VGA
VGA
CRT_DDC_CLK
DAC_IREF
DREFCLKINP DREFCLKINN
RSTIN#
PWROK
ICH_SYNC#
HDA_BCLK HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC
B18 D18 C18 F13
12
NI
NI
NC1
NC1 22PF/50V
22PF/50V
PLACED CAPACITOR CLOSE TO GMCH FOR EMI
L15 M15
DACREFSET
B15
PLACED RESISTOR CLOSE TO THE GMCH WITHIN 500 MIL LENGTH
E15 D15
G8 G9
AN6
AR4
K15
AU4 AV4 AU2 AV1 AU3
GND
NOTE:
HDMI PORTC DDC Control CLK HDMI PORTC DDC Control DATA
J11 F11
GND
12
NI
NI
NC2
NC2 22PF/50V
22PF/50V
12
I
I
NR33
NR33 1K
1K
1%
1%
12
NI
NI
NC3
NC3 22PF/50V
22PF/50V
GNDGND GNDGND
DDCA_DATA [26] DDCA_CLK [26]
NOTE:
Change NR33 and NR25~NR27 to 0 OHM for non-Graphics SKU, KEEP PU resistor VR14~15 for DDCDATA/CLK
LRESET# [21,37,39]
PWROK [21,38]
ICH_SYNC# [21]
I
I
NR26
NR26 150
150
1%
1%
GND
12
I
I
NR27
NR27 150
150
1%
1%
I
I
NR25
NR25 150
150
1%
1%
12
12
GND GND
PLACED RESISTOR CLOSE TO GMCH WITHIN 250 MIL LENGTH
VGA_RED [26] VGA_GREEN [26] VGA_BLUE [26]
CK_96M_DREF [5] CK_96M_DREF# [5]
A45
TEST0
B2
TEST1
A A
5
4
BE1 BE45
TEST2 TEST3
EAGLELAKE
EAGLELAKE
REV=1.4
REV=1.4
DPRSTP#
SLP#
3
R_RESERVED_F1#
P43
R_PM_SLP#
P42
NOTE:
NR69 NR46 place near CPU side
2
DPRSTP# [7] PM_SLP# [7,20]
ASUS OEM-DT MB RESTRICTED SECRET
EAGLELAKE 4 - 7
EAGLELAKE 4 - 7
EAGLELAKE 4 - 7
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Engineer:
IPM41-D3
IPM41-D3
IPM41-D3
1
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
13 55Thursday, July 09, 2009
13 55Thursday, July 09, 2009
13 55Thursday, July 09, 2009
Rev
Rev
Rev
1.00G
1.00G
1.00G
5
I
+1P1V_CORE
D D
+1P1V_CORE
+1P1V_CORE
I
NL1
NL1 1UH/300mA
1UH/300mA
mx_l0805
mx_l0805
I
I
NL2
NL2 1UH/300mA
1UH/300mA
mx_l0805
mx_l0805
I
I
NL7
NL7
2.2UH/250mA
2.2UH/250mA
mx_l0805
mx_l0805
0
0
NR47
+1P1V_GPLLD_R +1P1V_GPLLD
21
+1P1V_GPLL_R +1P1V_GPLL
21
21
NR47
1 2
NOBOM
NOBOM
NR48
NR48
1 2
NOBOM
NOBOM
NR49
NR49
1 2
NOBOM
NOBOM
NR50
NR50
1 2
NOBOM
NOBOM
NR51
NR51
1 2
NOBOM
NOBOM
NR52
NR52
1 2
NOBOM
NOBOM
0
0
0
0
0
0
0
0
0
0
NOTE:
C C
+1P1V_CORE
+1P1V_CORE
+1P1V_CORE
B B
A A
NL5
NL5
0.27UH/170mAImx_l0603
0.27UH/170mAImx_l0603
21
I
I
NL6
NL6 10UH/125mA
10UH/125mA
mx_l0805
mx_l0805
I
I
NL8
NL8 10UH/125mA
10UH/125mA
mx_l0805
mx_l0805
5
21
21
Install NL3 NL4 for iAMT support Install NL5 NL7 for non-iAMT support
4
+1P1V_MPLL_R
4
12
NI
NI
NCB9
NCB9 10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10% mx_c0805
mx_c0805
GND
12
GND
12
GND
12
GND GND
12
GND
GND
NI
NI
NCB13
NCB13 10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10% mx_c0805
mx_c0805
GND
NOTE:
I
I
NCB18
NCB18
Install NCB18 for EA issue
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10% mx_c0805
mx_c0805
GND
I
I
NCE1
NCE1 10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10% mx_c0805
mx_c0805
I
I
NCE2
NCE2 10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10% mx_c0805
mx_c0805
GND
12
NI
NI
NCB10
NCB10
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
12
NI
NI
NCB14
NCB14
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
12
NI
NI
NCB23
NCB23
2.2UF/6.3V
2.2UF/6.3V
X5R 10%
X5R 10% mx_c0603
mx_c0603
12
NI
NI
NCB27
NCB27
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
12
NI
NI
NCB30
NCB30
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
+1P1V_MPLL
+1P1V_HPLL
+1P1V_DPLLB
+1P1V_DPLLA
+3P3V
12
NI
NI
NCB38
NCB38
4.7UF/6.3V
4.7UF/6.3V
X5R 10%
X5R 10% mx_c0805
mx_c0805
GND GND
+1P1V_CORE
12
12
I
I
NCB39
NCB39
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
NR53
NR53 0
0
NOBOM
NOBOM
3
3
+1P1V_CORE
+1P1V_HPLL_D
GND
AA19 AA21 AA23 AA25 AA27 AA29 AA30 AB20 AB22 AB24 AB26 AB29 AB30 AC16 AC17 AC19 AC21 AC23 AC25 AC27 AC29 AD16 AD17 AD20 AD22 AD24 AD26 AD29 AE16 AE17 AE19 AE21 AE23 AE25 AE27 AE29
AF16 AF17 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27
AF29 AG16 AG17 AG20 AG22 AG24 AG26 AG29
AJ16
AJ17
AJ19
AJ21
AJ23
AJ25
R25
B12
B16
A21
B22
U33
C20
D20
E19
AR2
I
I
NU1F
NU1F
VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_12 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35 VCC_36 VCC_37 VCC_38 VCC_39 VCC_40 VCC_41 VCC_42 VCC_43 VCC_44 VCC_45 VCC_46 VCC_47 VCC_48 VCC_49 VCC_50 VCC_51 VCC_52 VCC_53 VCC_54 VCC_55 VCC_56 VCC_57 VCC_58 VCC_59 VCC_60 VCC_61 VCC_62 VCC_63 VCC_64 VCC_65 VCC_72
VCCD_PLL_EXP
VCCA_PLL_EXP
VCCA_MPLL
VCCA_HPLL
VCCD_HPLL
VCCA_DPLLB
VCCA_DPLLA
VCC_3P3
VCC_HDA
EAGLELAKE
EAGLELAKE
REV=1.4
REV=1.4
VCC_73 VCC_74 VCC_75 VCC_81 VCC_82 VCC_83 VCC_84 VCC_85 VCC_86 VCC_92 VCC_93 VCC_94 VCC_95 VCC_96 VCC_97 VCC_98
VCC_99 VCC_102 VCC_103 VCC_104 VCC_105 VCC_106 VCC_107 VCC_110 VCC_111 VCC_112 VCC_113 VCC_114 VCC_115 VCC_116 VCC_117 VCC_118 VCC_119 VCC_120 VCC_121 VCC_122
POWER
POWER
VCC_EXP_1 VCC_EXP_2 VCC_EXP_3 VCC_EXP_4 VCC_EXP_6 VCC_EXP_7 VCC_EXP_8
VCC_EXP_9 VCC_EXP_10 VCC_EXP_11 VCC_EXP_13 VCC_EXP_14 VCC_EXP_15 VCC_EXP_16 VCC_EXP_17 VCC_EXP_18 VCC_EXP_19 VCC_EXP_20 VCC_EXP_21 VCC_EXP_22 VCC_EXP_23 VCC_EXP_24 VCC_EXP_25 VCC_EXP_26 VCC_EXP_27 VCC_EXP_28 VCC_EXP_29 VCC_EXP_30 VCC_EXP_35 VCC_EXP_36 VCC_EXP_38 VCC_EXP_39 VCC_EXP_40 VCC_EXP_41 VCC_EXP_42 VCC_EXP_43 VCC_EXP_44 VCC_EXP_45
VCCAVRM_EXP
2
+1P1V_CORE
R26 R27 R29 T21 T24 T25 T26 T27 T29 U21 U22 U23 U24 U25 U26 U27 U29 W19 W21 W23 W25 W27 W29 Y20 Y22 Y24 Y26 T22 T23 AC4 AF3 F9 H4 L3 P3 V4
AA14 AA15 AB14 AC15 AD14 AD15 AE14 AE15 AF14 AF15 AG15 AJ10 AJ11 AJ12 AJ13 AJ14 AJ6 AJ7 AJ8 AJ9 AK10 AK11 AK12 AK13 AK6 AK7 AK8 AK9 U14 U15 W15 Y14 Y15 AJ1 AJ2 AK2 AK3 AK4
AG2
12
GND
2
12
GND
12
GND
12
GND
Core edge CAP decoupling, Place in PCI-E breakout
12
I
I
NCB65
NCB65
2.2UF/6.3V
2.2UF/6.3V
X5R 10%
X5R 10% mx_c0805
mx_c0805
GND
VCCAVRM_EXP_R
NI
NI
NCB76
NCB76
4.7UF/6.3V
4.7UF/6.3V
X5R 10%
X5R 10%
mx_c0805
mx_c0805
12
I
I
NCB24
NCB24 22UF/6.3V
22UF/6.3V
X5R 20%
X5R 20% mx_c1206
mx_c1206
Y
Y
I
I
NCB25
NCB25 10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10% mx_c0805
mx_c0805
I
I
NCB19
NCB19 1UF/16V
1UF/16V
X7R 10%
X7R 10% mx_c0603
mx_c0603
1 2
GND
GND
10/2 modify
GND
NOBOM
NOBOM
NR79
NR79 0
0
NI
NI
NR78
NR78
0
0
I
I
NCB11
NCB11 22UF/6.3V
22UF/6.3V
X5R 20%
X5R 20% mx_c1206
mx_c1206
Y
Y
12
NI
NI
NCB15
NCB15 10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10% mx_c0805
mx_c0805
GND
12
I
I
NCB20
NCB20 1UF/16V
1UF/16V
X7R 10%
X7R 10% mx_c0603
mx_c0603
10/2 modify
+1P1V_PCIEXPRESS
12
I
I
NCB28
NCB28
2.2UF/6.3V
2.2UF/6.3V
X5R 10%
X5R 10% mx_c0805
mx_c0805
+1P1V_CORE
+1P5V_ICH
12
12
GND
12
12
GND
GNDGND
I
I
NCB12
NCB12 22UF/6.3V
22UF/6.3V
X5R 20%
X5R 20% mx_c1206
mx_c1206
Y
Y
I
I
NCB16
NCB16 10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10% mx_c0805
mx_c0805
NI
NI
NCB21
NCB21 1UF/16V
1UF/16V
X7R 10%
X7R 10% mx_c0603
mx_c0603
12
I
I
NCB29
NCB29
2.2UF/6.3V
2.2UF/6.3V
X5R 10%
X5R 10% mx_c0805
mx_c0805
ASUS OEM-DT MB RESTRICTED SECRET
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
1
12
NI
NI
NCB17
NCB17 10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10% mx_c0805
mx_c0805
GND
12
NI
NI
NCB22
NCB22 1UF/16V
1UF/16V
X7R 10%
X7R 10% mx_c0603
mx_c0603
GND
NOBOM
NOBOM
NJP1
NJP1 SHORTPIN_RECT
SHORTPIN_RECT
NOBOM
NOBOM
NJP2
NJP2 SHORTPIN_RECT
SHORTPIN_RECT
NOBOM
NOBOM
NJP3
NJP3 SHORTPIN_RECT
SHORTPIN_RECT
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
IPM41-D3
IPM41-D3
IPM41-D3
1
+1P1V_CORE
12
12
12
EAGLELAKE 5 - 7
EAGLELAKE 5 - 7
EAGLELAKE 5 - 7
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
14 55Thursday, July 09, 2009
14 55Thursday, July 09, 2009
14 55Thursday, July 09, 2009
Rev
Rev
Rev
1.00G
1.00G
1.00G
5
4
3
2
1
I
I
NCB46
NCB46
2.2UF/6.3V
2.2UF/6.3V
X5R 10%
X5R 10% mx_c0603
mx_c0603
I
I
NCB42
NCB42
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
I
I
NCB57
NCB57
2.2UF/6.3V
2.2UF/6.3V
X5R 10%
X5R 10% mx_c0603
mx_c0603
NI
NI
NCB75
NCB75 1UF/16V
1UF/16V
X7R 10%
X7R 10% mx_c0603
mx_c0603
+1P1V_FSB_VTT
+3P3V_DAC_VCCA
NR61
NR61
1 2
NOBOM
NOBOM
VCCCML_DDR
0
0
VCCABG_EXP
VCCDQ_CRT
GND
Place near GMCH
12
I
I
NCB40
D D
C C
+1P5V_DUAL
12
NI
NI
NCB43
NCB43
2.2UF/6.3V
2.2UF/6.3V
X5R 10%
X5R 10% mx_c0603
mx_c0603
+3P3V
B B
A A
Place a via in between cap and GMCH on GND trace.It means that the GND for cap has to be independent
12
I
I
NCB53
NCB53
2.2UF/6.3V
2.2UF/6.3V
X5R 10%
X5R 10% mx_c0603
mx_c0603
NL10
NL10
1 2
NOBOM
NOBOM
mx_r0603_short
mx_r0603_short
+1P5V_ICH
+1P1V_CORE
+3P3V_DAC_FB
0
0
5
12
I
I
NCB54
NCB54
2.2UF/6.3V
2.2UF/6.3V
X5R 10%
X5R 10% mx_c0603
mx_c0603
12
NI
NI
+
+
NCE3
NCE3 220UF/16V
220UF/16V
NJP7
NJP7
12
SHORTPIN_RECT
SHORTPIN_RECT
NOBOM
NOBOM
12
I
I
NCB44
NCB44
2.2UF/6.3V
2.2UF/6.3V
X5R 10%
X5R 10% mx_c0603
mx_c0603
GNDGNDGND GND
12
I
I
NCB62
NCB62 1UF/16V
1UF/16V
X7R 10%
X7R 10% mx_c0603
mx_c0603
GNDGND
+CPU_VCCPLL
NCB40
2.2UF/6.3V
2.2UF/6.3V
X5R 10%
X5R 10% mx_c0603
mx_c0603
12
NI
NI
NCB49
NCB49
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
12
I
I
NCB55
NCB55
2.2UF/6.3V
2.2UF/6.3V
X5R 10%
X5R 10% mx_c0603
mx_c0603
I
I
NR60
NR60
40.2 OHM
40.2 OHM
1%
1%
1 2
I
I
NR62
NR62
39.2 OHM
39.2 OHM
1%
1%
1 2
GND
I
I
NL12
NL12
0.1UH/300mA
0.1UH/300mA
mx_l0603
mx_l0603
12
I
I
NCB45
NCB45
2.2UF/6.3V
2.2UF/6.3V
X5R 10%
X5R 10% mx_c0603
mx_c0603
12
NI
NI
NCB41
NCB41
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
12
I
I
NCB56
NCB56
2.2UF/6.3V
2.2UF/6.3V
X5R 10%
X5R 10% mx_c0603
mx_c0603
GND GNDGND
+1P5V_EXP_FB+1P5V_EXP_FB
0
0
NL11
NL11
1 2
NOBOM
NOBOM
mx_r0603_short
mx_r0603_short
21
12
GNDGNDGND
12
GNDGNDGND
12
VCCDQ_CRT_R
VCCDQ_CRT_R
12
GND
4
M21 M22 N20 N21 N22
R20 R21 R22 R23 R24
AP44 AT45 AV44 AY40 BA41
BB39 BD21 BD25 BD29 BD34 BD38
BE23
BE27
BE31
BE36
D19
AM30
A25 B25 B26 C24 C26 D22 D23 D24 E23 F21 F22 G21 G22 H21 H22
K21 K22 L21 L22
P20 P21 P22 P24
B19
A17
B20
B17
J21 J22
I
I
NU1G
NU1G
VTT1 VTT2 VTT3 VTT4 VTT5 VTT6 VTT7 VTT8 VTT9 VTT10 VTT11 VTT12 VTT13 VTT14 VTT15 VTT16 VTT17 VTT18 VTT19 VTT20 VTT21 VTT22 VTT23 VTT24 VTT25 VTT26 VTT27 VTT28 VTT29 VTT30 VTT31 VTT32 VTT33 VTT34 VTT35
VCCSM1 VCCSM2 VCCSM3 VCCSM4 VCCSM5 VCCSM6 VCCSM7 VCCSM8 VCCSM9 VCCSM10 VCCSM11 VCCSM12 VCCSM13 VCCSM14 VCCSM15
VCCA_DAC1 VCCA_DAC2
VCCA_EXP
VCCDQ_CRT
VSS0
VCCCML_DDR
EAGLELAKE
EAGLELAKE
REV=1.4
REV=1.4
3
VCC_SMCLK1 VCC_SMCLK2 VCC_SMCLK3 VCC_SMCLK4
VCC_CL1 VCC_CL2 VCC_CL3 VCC_CL4 VCC_CL5 VCC_CL6 VCC_CL7 VCC_CL8
VCC_CL9 VCC_CL10 VCC_CL11 VCC_CL12 VCC_CL13 VCC_CL14 VCC_CL15 VCC_CL16 VCC_CL17 VCC_CL18 VCC_CL19 VCC_CL20 VCC_CL21 VCC_CL22 VCC_CL23 VCC_CL24 VCC_CL25 VCC_CL26 VCC_CL27 VCC_CL28 VCC_CL29 VCC_CL30 VCC_CL31 VCC_CL32 VCC_CL33 VCC_CL34 VCC_CL35 VCC_CL36 VCC_CL37 VCC_CL38 VCC_CL39 VCC_CL40 VCC_CL41 VCC_CL42 VCC_CL43 VCC_CL44 VCC_CL45 VCC_CL46 VCC_CL47 VCC_CL48 VCC_CL49 VCC_CL50 VCC_CL51 VCC_CL52 VCC_CL53 VCC_CL55 VCC_CL56 VCC_CL57 VCC_CL58 VCC_CL59 VCC_CL60 VCC_CL61 VCC_CL62 VCC_CL63 VCC_CL64 VCC_CL65 VCC_CL66 VCC_CL67 VCC_CL68 VCC_CL69 VCC_CL70 VCC_CL71 VCC_CL72 VCC_CL73 VCC_CL74 VCC_CL75 VCC_CL76 VCC_CL77 VCC_CL78 VCC_CL79 VCC_CL80 VCC_CL81 VCC_CL82 VCC_CL83 VCC_CL84 VCC_CL85 VCC_CL86
AK32 AL31 AL32 AM31
AA32 AA33 AB32 AB33 AD32 AD33 AE32 AE33 AF32 AJ32 AK31 AL30 AM15 AM16 AM17 AM20 AM21 AM22 AM24 AM25 AM26 AM29 Y32 Y33 AP1 AP2 Y31 AA31 AB31 AC31 AD31 AE31 AF31 AG30 AG31 AJ30 AJ31 AK16 AK17 AK19 AK20 AK21 AK22 AK23 AK24 AK25 AK26 AK27 AK29 AK30 AL1 AL10 AL11 AL26 AL12 AL15 AL17 AL19 AL2 AL20 AL21 AL22 AL23 AL16 AL24 AL25 AL27 AL29 AL4 AL5 AL6 AL7 AL8 AL9 AM2 AM3 AM4 AL14 AJ15 AK14 AJ27 AJ29 W31 Y30 Y29
VCCCK_DDR
BOTTOM
BOTTOM
NL90
NL90
12
NOBOM
12
NI
NI
NCB47
NCB47
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
BOTTOM
BOTTOM
GND
10/2 modify
12
GND
NI
NI
NCB50
NCB50
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
+1P1V_CL +1P1V_CORE
12
I
I
NCB51
NCB51 10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10% mx_c0805
mx_c0805
GND GND
NOBOM
mx_r1206_short
mx_r1206_short
NR57 1
NR57 1
NI
NI
1 2
BOTTOM
BOTTOM
NR56 1
NR56 1
NI
NI
1 2
BOTTOM
BOTTOM
NOBOM
NOBOM
NJP10
NJP10 SHORTPIN_RECT
SHORTPIN_RECT
NOBOM
NOBOM
NJP9
NJP9 SHORTPIN_RECT
SHORTPIN_RECT
NOBOM
NOBOM
NJP8
NJP8 SHORTPIN_RECT
SHORTPIN_RECT
12
I
I
NCB52
NCB52 10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10% mx_c0805
mx_c0805
12
12
12
BACKSIDE CAPS FOR SPECIFIC +1P1V_CORE GMCH
12
NI
NI
NCB58
NCB58 10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10% mx_c0805
mx_c0805
BOTTOM
BOTTOM
12
NI
NI
NCB63
NCB63 1UF/16V
1UF/16V
X7R 10%
X7R 10% mx_c0603
mx_c0603
BOTTOM
BOTTOM
GND
12
NI
NI
NCB71
NCB71 1UF/16V
1UF/16V
X7R 10%
X7R 10% mx_c0603
mx_c0603
BOTTOM
BOTTOM
GND GND GND GND
GND
GND
12
NI
NI
NCB59
NCB59 10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10% mx_c0805
mx_c0805
BOTTOM
BOTTOM
12
NI
NI
NCB64
NCB64 1UF/16V
1UF/16V
X7R 10%
X7R 10% mx_c0603
mx_c0603
BOTTOM
BOTTOM
12
NI
NI
NCB72
NCB72 1UF/16V
1UF/16V
X7R 10%
X7R 10% mx_c0603
mx_c0603
BOTTOM
BOTTOM
GNDGND
GND
12
NI
NI
NCB60
NCB60 10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10% mx_c0805
mx_c0805
BOTTOM
BOTTOM
12
NI
NI
NCB69
NCB69 1UF/16V
1UF/16V
X7R 10%
X7R 10% mx_c0603
mx_c0603
BOTTOM
BOTTOM
12
NI
NI
NCB73
NCB73 1UF/16V
1UF/16V
X7R 10%
X7R 10% mx_c0603
mx_c0603
BOTTOM
BOTTOM
ASUS OEM-DT MB RESTRICTED SECRET
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
2
V_CKDDR_R
12
NI
NI
NCB61
NCB61 10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10% mx_c0805
mx_c0805
BOTTOM
BOTTOM
GND
12
NI
NI
NCB70
NCB70 1UF/16V
1UF/16V
X7R 10%
X7R 10% mx_c0603
mx_c0603
BOTTOM
BOTTOM
GND
12
NI
NI
NCB74
NCB74 1UF/16V
1UF/16V
X7R 10%
X7R 10% mx_c0603
mx_c0603
BOTTOM
BOTTOM
Engineer:
Engineer:
Engineer:
IPM41-D3
IPM41-D3
IPM41-D3
+1P5V_DUAL
12
GND
+1P1V_CORE
Title :
Title :
Title :
1
NI
NI
NCB48
NCB48 10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10% mx_c0805
mx_c0805
BOTTOM
BOTTOM
EAGLELAKE 6 - 7
EAGLELAKE 6 - 7
EAGLELAKE 6 - 7
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
15 55Thursday, July 09, 2009
15 55Thursday, July 09, 2009
15 55Thursday, July 09, 2009
Rev
Rev
Rev
1.00G
1.00G
1.00G
5
I
I
NU1H
NU1H
A12
VSS1
A15
VSS2
A19
VSS3
A27
VSS4
A31
VSS5
A36
VSS6
A40
VSS7
D D
C C
B B
A A
AA1 AA11 AA12 AA13 AA20 AA22 AA24 AA26 AA34 AA38 AA40 AA44
AA8 AB11 AB12 AB19 AB21 AB23 AB25 AB27 AB34 AB36 AB39
AB4
AB6
AB7
AB8 AC20 AC22 AC24 AC26 AC45
AC5 AD12 AD19 AD21 AD23 AD25 AD27
AD3 AD34 AD36 AD39
AD6
AD9
AE1 AE11 AE20 AE22 AE24 AE26 AE34 AE38 AE40 AE44
AE8
AF10 AF11 AF12 AF13 AF33 AF35 AF39
AF6
AF7 AG19 AG21 AG23 AG25 AG27 AG45
AG5 AH2 AH3
AH4 AJ20 AJ22 AJ24
AU20 AA16 AA17 AB16 AB17
N16 P16 P17 R16 R17 R19 R30
VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85
VSS346 VSS347 VSS348 VSS349 VSS350 VSS351 VSS352 VSS353 VSS354 VSS355 VSS356 VSS357
EAGLELAKE
EAGLELAKE
5
GND
GND
REV=1.4
REV=1.4
VSS170 VSS169 VSS168 VSS167 VSS166 VSS165 VSS164 VSS163 VSS162 VSS161 VSS160 VSS159 VSS158 VSS157 VSS156 VSS155 VSS154 VSS153 VSS152 VSS151 VSS150 VSS149 VSS148 VSS147 VSS146 VSS145 VSS144 VSS143 VSS142 VSS141 VSS140 VSS139 VSS138 VSS137 VSS136 VSS135 VSS134 VSS133 VSS132 VSS131 VSS130 VSS129 VSS128 VSS127 VSS126 VSS125 VSS124 VSS123 VSS122 VSS121 VSS120 VSS119 VSS118 VSS117 VSS116 VSS115 VSS114 VSS113 VSS112 VSS111 VSS110 VSS109 VSS108 VSS107 VSS106 VSS105 VSS104 VSS103 VSS102 VSS101 VSS100
VSS99 VSS98 VSS97 VSS96 VSS95 VSS94 VSS93 VSS92 VSS91 VSS90 VSS89 VSS88 VSS87 VSS86
VSS370 VSS369 VSS368 VSS367 VSS366 VSS365 VSS364 VSS363 VSS362 VSS361 VSS360 VSS359 VSS358
AP20 AP22 AP24 AP29 AP45 AR10 AR11 AR13 AR16 AR26 AR3 AR31 AR33 AR35 AR39 AR8 AR9 AT1 AT11 AT13 AT17 AT2 AT24 AT29 AY15 AT35 AU22 AU25 AU30 AU9 AV11 AV13 AV15 AV16 AV2 AV21 AV30 AV38 AV8 AV9 AW11 AW17 AW20 AW22 AW24 AW26 AW3 AW30 AY1 AY16 AY21 AY25 AY30 AY45 B21 B27 B29 B34 BA23 BA5 BB21 BB25 BB28 BB6 BD12 BD17 BD43 BD8 BE10 BE15 BE19 BE21 BE25 BE29 BE34 BE40 AV33 C3 C5 H38 AJ45 AJ44 AJ39 AJ36 AJ26
Y17 Y16 W17 W16 U20 U19 U17 U16 T30 T20 T19 T17 T16
GNDGND
4
I
I
NU1I
NU1I
AK35
VSS171
AK38
VSS172
AK39
VSS173
AL38
VSS174
AL44
VSS175
AL45
VSS176
AN33
VSS177
AN36
VSS178
AN38
VSS179
AN7
VSS180
A8
VSS181
D11
VSS182
D16
VSS183
D21
VSS184
D25
VSS185
D26
VSS186
D39
VSS187
D6
VSS188
D7
VSS189
B10
VSS190
E3
VSS191
E31
VSS192
E41
VSS193
E5
VSS194
F16
VSS195
F2
VSS196
F30
VSS197
F4
VSS198
F42
VSS199
F45
VSS200
F8
VSS201
G11
VSS202
G17
VSS203
G24
VSS204
G26
VSS205
G29
VSS206
G3
VSS207
G35
H1 H11 H13 H15 H16 H20 H25 H30 H31 H33 H44
H7
H8
H9
J3
J37
J4 J5 J8
J9 K11 K13 K17 K20 K24 K29 K33 K45 L10 L16 L20 L26 L30 L35 L39
L4 L8 L9
M1 M24 M25 M44 N11 N13 N26 N29 N30 N33 N36
F1
C45
C1
4
VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260
EAGLELAKE
EAGLELAKE
GND
GND
REV=1.4
REV=1.4
VSS345 VSS344 VSS343 VSS342 VSS341 VSS340 VSS339 VSS338 VSS337 VSS336 VSS335 VSS334 VSS333 VSS332 VSS331 VSS330 VSS329 VSS328 VSS327 VSS326 VSS325 VSS324 VSS323 VSS322 VSS321 VSS320 VSS319 VSS318 VSS317 VSS316 VSS315 VSS314 VSS313 VSS312 VSS311 VSS310 VSS309 VSS308 VSS307 VSS306 VSS305 VSS304 VSS303 VSS302 VSS301 VSS300 VSS299 VSS298 VSS297 VSS296 VSS295 VSS294 VSS293 VSS292 VSS291 VSS290 VSS289 VSS288 VSS287 VSS286 VSS285 VSS284 VSS283 VSS282 VSS281 VSS280 VSS279 VSS277 VSS276 VSS275 VSS274 VSS273 VSS271 VSS270 VSS269 VSS268 VSS267 VSS266 VSS265 VSS264 VSS263 VSS262 VSS261
VSS371 VSS372 VSS373 VSS374
AV6 AU6 AU5 AP25 AP21 AN26 C16 N38 N8 P25 P26 P31 R11 R12 R2 R38 R45 R5 R8 T10 T11 T12 T13 T3 T31 T32 T33 T35 T38 T4 T40 T6 T7 T8 T9 U1 U11 U12 U13 U36 U39 U44 U8 W1 W2 W20 W22 W24 W26 W44 W45 W5 Y10 Y11 Y12 Y13 Y19 Y2 Y21 Y23 Y25 Y27 Y3 Y35 Y39 Y9 AN22 AE13 AN24 AU35 AN25 AE12 AN21 A3 A43 A6 B44 BC1 BC45 BD2 BD44 BE3 BE43
AD30 AC30 AF30 AE30
3
2
1
EAGLELAKE-P/Q/G (25.2W/23.4W/25.5W)
13G070432001 HEATSINK 55.2*37.6*30MM SILVER
13G070432000 HEATSINK 55.2*37.6*30MM SILVER
13G070432002 HEATSINK 55.2*37.6*30MM SILVER
I
I
HEATSINK1
I
I
CLIP1
CLIP1
ANCHOR_CLIP
ANCHOR_CLIP
ANGLE_45
ANGLE_45
HEATSINK1
8 7
6 5
8/11 change to 13X070401000
1 2
3 4
HEATSINK_4ANCHOR
HEATSINK_4ANCHOR
T725
T725
I
I
CLIP2
CLIP2
ANCHOR_CLIP
ANCHOR_CLIP
ANGLE_45
ANGLE_45
GNDGND
I
I
CLIP3
CLIP3
ANCHOR_CLIP
ANCHOR_CLIP
ANGLE_45
ANGLE_45
I
I
CLIP4
CLIP4
ANCHOR_CLIP
ANCHOR_CLIP
ANGLE_45
ANGLE_45
ASUS OEM-DT MB RESTRICTED SECRET
EAGLELAKE 7 - 7
EAGLELAKE 7 - 7
GNDGND
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
IPM41-D3
IPM41-D3
IPM41-D3
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
1
EAGLELAKE 7 - 7
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
16 55Thursday, July 09, 2009
16 55Thursday, July 09, 2009
16 55Thursday, July 09, 2009
Rev
Rev
Rev
1.00G
1.00G
1.00G
5
NOTE:
Below 4 signals are different connection in Eaglelake platform Channel A : CS1/WE/MA0 Channel B : ODT3 (G41 No ODT3)
XMM1 COLOR: BLUE
D D
M_CHA_MAA0 M_CHA_MAA1 M_CHA_MAA2 M_CHA_MAA3 M_CHA_MAA4 M_CHA_MAA5 M_CHA_MAA6 M_CHA_MAA7 M_CHA_MAA8 M_CHA_MAA9 M_CHA_MAA10 M_CHA_DQ53 M_CHA_MAA11 M_CHA_MAA12 M_CHA_MAA13
NOTE:
Check clock source if Eaglelake implemented
M_CHA_CLK0[11] M_CHA_CLK0#[11] M_CHA_CLK2[11] M_CHA_CLK2#[11]
06/03 Important! follow Intel MRC code,
C C
B B
A A
only DIMMA need.
M_CHA_CS#1[12] M_CHA_CS#0[11]
M_CHA_CKE1[11] M_CHA_CKE0[11]
M_CHA_BA2[11] M_CHA_BA1[11] M_CHA_BA0[11]
SMB_DATA_R[5,9,18,21,24,25,28,29] SMB_CLK_R[5,9,18,21,24,25,28,29]
M_CHA_WE#[12] M_CHA_RAS#[11] M_CHA_CAS#[11]
M_CHA_ODT1[11] M_CHA_ODT0[11]
DDR3_DRAMRST#[12,18]
M_CHA_DM7[11]
M_CHA_DM5[11] M_CHA_DQS4 [11]
M_CHA_DM4[11]
M_CHA_DM3[11]
M_CHA_DM2[11]
M_CHA_DM1[11]
M_CHA_DM0[11]
M_CHA_MAA14
GND
GND
5
DIMMA0A
DIMMA0A
188
A0
181
A1
61
A2
180
A3
59
A4
58
A5
178
A6
56
A7
177
A8
175
A9
70
A10/AP
55
A11
174
A12
196
A13
172
A14
171
A15
63
CK1P/NU
64
CK1N/NU
184
CK0P
185
CK0N
76
CS1#
193
CS0#
169
CKE1
50
CKE0
52
BA2
190
BA1
71
BA0
238
SDA
118
SCL
165
CB7
164
CB6
159
CB5
158
CB4
46
CB3
45
CB2
40
CB1
39
CB0
237
SA1
117
SA0
73
WE#
192
RAS#
74
CAS#
77
ODT1
195
ODT0
168
RESET#
161
DM8/DQS17P
162
NC/DQS17N
230
DM7/DQS16P
231
NC/DQS16N
221
DM6/DQS15P
222
NC/DQS15N
212
DM5/DQS14P
213
NC/DQS14N
203
DM4/DQS13P
204
NC/DQS13N
152
DM3/DQS12P
153
NC/DQS12N
143
DM2/DQS11P
144
NC/DQS11N
134
DM1/DQS10P
135
NC/DQS10N
125
DM0/DQS9P
126
NC/DQS9N
43
NC/DQS8P
42
NC/DQS8N
198
FREE1
187
FREE2
49
FREE3
48
FREE4
DDR3_DIMM_240P
DDR3_DIMM_240P
I
I
DQ63 DQ62 DQ61 DQ60 DQ59 DQ58 DQ57 DQ56 DQ55 DQ54 DQ53 DQ52 DQ51 DQ50 DQ49 DQ48 DQ47 DQ46 DQ45 DQ44 DQ43 DQ42 DQ41 DQ40 DQ39 DQ38 DQ37 DQ36 DQ35 DQ34 DQ33 DQ32 DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10
DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
DQS7P DQS7N DQS6P DQS6N DQS5P DQS5N DQS4P DQS4N DQS3P DQS3N DQS2P DQS2N DQS1P DQS1N DQS0P DQS0N
RESERVED
NC/PAR_IN
NC/ERR_OUT
NC/TEST4
234 233 228 227 115 114 109 108 225 224 219 218 106 105 100 99 216 215 210 209 97 96 91 90 207 206 201 200 88 87 82 81 156 155 150 149 37 36 31 30 147 146 141 140 28 27 22 21 138 137 132 131 19 18 13 12 129 128 123 122 10 9 4 3
112 111 103 102 94 93 85 84 34 33 25 24 16 15 7 6
79
68 53 167
4
M_CHA_DQ63 M_CHA_DQ62 M_CHA_DQ61 M_CHA_DQ60 M_CHA_DQ59 M_CHA_DQ58 M_CHA_DQ57 M_CHA_DQ56 M_CHA_DQ55 M_CHA_DQ54
M_CHA_DQ52 M_CHA_DQ51 M_CHA_DQ50 M_CHA_DQ49 M_CHA_DQ48 M_CHA_DQ47 M_CHA_DQ46 M_CHA_DQ45 M_CHA_DQ44 M_CHA_DQ43 M_CHA_DQ42 M_CHA_DQ41 M_CHA_DQ40 M_CHA_DQ39 M_CHA_DQ38 M_CHA_DQ37 M_CHA_DQ36 M_CHA_DQ35 M_CHA_DQ34 M_CHA_DQ33 M_CHA_DQ32 M_CHA_DQ31 M_CHA_DQ30 M_CHA_DQ29 M_CHA_DQ28 M_CHA_DQ27 M_CHA_DQ26 M_CHA_DQ25 M_CHA_DQ24 M_CHA_DQ23 M_CHA_DQ22 M_CHA_DQ21 M_CHA_DQ20 M_CHA_DQ19 M_CHA_DQ18 M_CHA_DQ17 M_CHA_DQ16 M_CHA_DQ15 M_CHA_DQ14 M_CHA_DQ13 M_CHA_DQ12 M_CHA_DQ11 M_CHA_DQ10 M_CHA_DQ9 M_CHA_DQ8 M_CHA_DQ7 M_CHA_DQ6 M_CHA_DQ5 M_CHA_DQ4 M_CHA_DQ3 M_CHA_DQ2 M_CHA_DQ1 M_CHA_DQ0
M_CHA_DQS7 [11] M_CHA_DQS7# [11] M_CHA_DQS6 [11] M_CHA_DQS6# [11] M_CHA_DQS5 [11]M_CHA_DM6[11] M_CHA_DQS5# [11]
M_CHA_DQS4# [11] M_CHA_DQS3 [11] M_CHA_DQS3# [11] M_CHA_DQS2 [11] M_CHA_DQS2# [11] M_CHA_DQS1 [11] M_CHA_DQS1# [11] M_CHA_DQS0 [11] M_CHA_DQS0# [11]
4
3
3
2
M_CHA_DQ[0..63] [11]
M_CHA_MAA[1..14] [11]
M_CHA_MAA0 [12]
+0P75V_VTT_DDR
12
GND GND
+1P5V_DUAL +1P5V_DUAL
12
I
I
D3R17
D3R17 1K
1K
1%
1%
12
I
I
D3R18
D3R18 1K
1K
1%
1%
GND GND GND GND
2
I
I
D3CB17
D3CB17
4.7UF/6.3V
4.7UF/6.3V
X5R 10%
X5R 10% mx_c0805
mx_c0805
12
I
I
D3R15
D3R15 1K
1K
1%
1%
12
I
I
D3R16
D3R16 1K
1K
1%
1%
12
I
I
D3CB18
D3CB18
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
12
I
I
D3CB6
D3CB6
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
1
+1P5V_DUAL +1P5V_DUAL
GND
DIMM_CA_VREF_A
DIMM_VREF_A
12
I
I
D3CB5
D3CB5
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
DIMMA0B
DIMMA0B
78
VDD10
75
VDD9
72
VDD8
69
VDD7
66
VDD6
65
VDD5
62
VDD4
60
VDD3
57
VDD2
54
VDD1
51
VDD0
240
VTT2
120
VTT1
113
GND27
110
GND26
107
GND25
104
GND24
101
GND23
98
GND22
95
GND21
92
GND20
89
GND19
86
GND18
83
GND17
80
GND16
47
GND15
44
GND14
41
GND13
38
GND12
35
GND11
32
GND10
29
GND9
26
GND8
23
GND7
20
GND6
17
GND5
14
GND4
11
GND3
8
GND2
5
GND1
2
GND0
67
VREFCA
1
VREFDQ
DDR3_DIMM_240P
DDR3_DIMM_240P
I
I
197
VDD21
194
VDD20
191
VDD19
189
VDD18
186
VDD17
183
VDD16
182
VDD15
179
VDD14
176
VDD13
173
VDD12
170
VDD11
239
GND59
235
GND58
232
GND57
229
GND56
226
GND55
223
GND54
220
GND53
217
GND52
214
GND51
211
GND50
208
GND49
205
GND48
202
GND47
199
GND46
166
GND45
163
GND44
160
GND43
157
GND42
154
GND41
151
GND40
148
GND39
145
GND38
142
GND37
139
GND36
136
GND35
133
GND34
130
GND33
127
GND32
124
GND31
121
GND30
119
GND29
116
GND28
241
NP_NC1
242
NP_NC2
243
NP_NC3
236
VDDSPD
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
IPM41-D3
IPM41-D3
IPM41-D3
1
GND
DDR3 CHANNEL A
DDR3 CHANNEL A
DDR3 CHANNEL A
York Chang
York Chang
York Chang
17 55Thursday, July 09, 2009
17 55Thursday, July 09, 2009
17 55Thursday, July 09, 2009
+3P3V
Rev
Rev
Rev
1.00
1.00
1.00
5
XMM3 COLOR: BLUE
D D
M_CHB_MAA0 M_CHB_MAA1 M_CHB_MAA2 M_CHB_MAA3 M_CHB_MAA4 M_CHB_MAA5 M_CHB_MAA6 M_CHB_MAA7 M_CHB_MAA8 M_CHB_MAA9 M_CHB_MAA10 M_CHB_MAA11 M_CHB_MAA12 M_CHB_MAA13
5
M_CHB_MAA14
+3P3V
GND
12
I
I
D3C02
D3C02
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
GND
NOTE:
Check clock source if Eaglelake implemented
M_CHB_CLK2[12] M_CHB_CLK2#[12] M_CHB_CLK0[12] M_CHB_CLK0#[12]
C C
B B
A A
M_CHB_CS#1[12] M_CHB_CS#0[12]
M_CHB_CKE1[12] M_CHB_CKE0[12]
M_CHB_BA2[12] M_CHB_BA1[12] M_CHB_BA0[12]
SMB_DATA_R[5,9,17,21,24,25,28,29] SMB_CLK_R[5,9,17,21,24,25,28,29]
M_CHB_WE#[12] M_CHB_RAS#[12] M_CHB_CAS#[12]
M_CHB_ODT1[12] M_CHB_ODT0[12]
DDR3_DRAMRST#[12,17]
M_CHB_DM7[12]
M_CHB_DM6[12]
M_CHB_DM5[12]
M_CHB_DM4[12]
M_CHB_DM3[12]
M_CHB_DM2[12]
M_CHB_DM1[12]
M_CHB_DM0[12]
DIMMB0A
DIMMB0A
188
A0
181
A1
61
A2
180
A3
59
A4
58
A5
178
A6
56
A7
177
A8
175
A9
70
A10/AP
55
A11
174
A12
196
A13
172
A14
171
A15
63
CK1P/NU
64
CK1N/NU
184
CK0P
185
CK0N
76
CS1#
193
CS0#
169
CKE1
50
CKE0
52
BA2
190
BA1
71
BA0
238
SDA
118
SCL
165
CB7
164
CB6
159
CB5
158
CB4
46
CB3
45
CB2
40
CB1
39
CB0
237
SA1
117
SA0
73
WE#
192
RAS#
74
CAS#
77
ODT1
195
ODT0
168
RESET#
161
DM8/DQS17P
162
NC/DQS17N
230
DM7/DQS16P
231
NC/DQS16N
221
DM6/DQS15P
222
NC/DQS15N
212
DM5/DQS14P
213
NC/DQS14N
203
DM4/DQS13P
204
NC/DQS13N
152
DM3/DQS12P
153
NC/DQS12N
143
DM2/DQS11P
144
NC/DQS11N
134
DM1/DQS10P
135
NC/DQS10N
125
DM0/DQS9P
126
NC/DQS9N
43
NC/DQS8P
42
NC/DQS8N
198
FREE1
187
FREE2
49
FREE3
48
FREE4
DDR3_DIMM_240P
DDR3_DIMM_240P
I
I
DQ63 DQ62 DQ61 DQ60 DQ59 DQ58 DQ57 DQ56 DQ55 DQ54 DQ53 DQ52 DQ51 DQ50 DQ49 DQ48 DQ47 DQ46 DQ45 DQ44 DQ43 DQ42 DQ41 DQ40 DQ39 DQ38 DQ37 DQ36 DQ35 DQ34 DQ33 DQ32 DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10
DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
DQS7P DQS7N DQS6P DQS6N DQS5P DQS5N DQS4P DQS4N DQS3P DQS3N DQS2P DQS2N DQS1P DQS1N DQS0P DQS0N
RESERVED
NC/PAR_IN
NC/ERR_OUT
NC/TEST4
234 233 228 227 115 114 109 108 225 224 219 218 106 105 100 99 216 215 210 209 97 96 91 90 207 206 201 200 88 87 82 81 156 155 150 149 37 36 31 30 147 146 141 140 28 27 22 21 138 137 132 131 19 18 13 12 129 128 123 122 10 9 4 3
112 111 103 102 94 93 85 84 34 33 25 24 16 15 7 6
79
68 53 167
4
M_CHB_DQ63 M_CHB_DQ62 M_CHB_DQ61 M_CHB_DQ60 M_CHB_DQ59 M_CHB_DQ58 M_CHB_DQ57 M_CHB_DQ56 M_CHB_DQ55 M_CHB_DQ54 M_CHB_DQ53 M_CHB_DQ52 M_CHB_DQ51 M_CHB_DQ50 M_CHB_DQ49 M_CHB_DQ48 M_CHB_DQ47 M_CHB_DQ46 M_CHB_DQ45 M_CHB_DQ44 M_CHB_DQ43 M_CHB_DQ42 M_CHB_DQ41 M_CHB_DQ40 M_CHB_DQ39 M_CHB_DQ38 M_CHB_DQ37 M_CHB_DQ36 M_CHB_DQ35 M_CHB_DQ34 M_CHB_DQ33 M_CHB_DQ32 M_CHB_DQ31 M_CHB_DQ30 M_CHB_DQ29 M_CHB_DQ28 M_CHB_DQ27 M_CHB_DQ26 M_CHB_DQ25 M_CHB_DQ24 M_CHB_DQ23 M_CHB_DQ22 M_CHB_DQ21 M_CHB_DQ20 M_CHB_DQ19 M_CHB_DQ18 M_CHB_DQ17 M_CHB_DQ16 M_CHB_DQ15 M_CHB_DQ14 M_CHB_DQ13 M_CHB_DQ12 M_CHB_DQ11 M_CHB_DQ10 M_CHB_DQ9 M_CHB_DQ8 M_CHB_DQ7 M_CHB_DQ6 M_CHB_DQ5 M_CHB_DQ4 M_CHB_DQ3 M_CHB_DQ2 M_CHB_DQ1 M_CHB_DQ0
M_CHB_DQS7 [12] M_CHB_DQS7# [12] M_CHB_DQS6 [12] M_CHB_DQS6# [12] M_CHB_DQS5 [12] M_CHB_DQS5# [12] M_CHB_DQS4 [12] M_CHB_DQS4# [12] M_CHB_DQS3 [12] M_CHB_DQS3# [12] M_CHB_DQS2 [12] M_CHB_DQS2# [12] M_CHB_DQS1 [12] M_CHB_DQS1# [12] M_CHB_DQS0 [12] M_CHB_DQS0# [12]
4
3
+1P5V_DUAL
2
M_CHB_DQ[0..63] [12]
M_CHB_MAA[0..14] [12]
+0P75V_VTT_DDR
12
I
I
D3CB25
D3CB25
4.7UF/6.3V
4.7UF/6.3V
X5R 10%
X5R 10% mx_c0805
mx_c0805
GND GND
+1P5V_DUAL
12
12
I
I
I
I
D3R28
D3R28
D3R25
D3R25
1K
1K
1K
1K
1%
1%
1%
1%
12
12
I
I
D3R26
D3R26
I
I
1K
1K
D3R27
D3R27
1%
1%
1K
1K
1%
1%
GND GND GND
12
I
I
D3CB12
D3CB12
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
12
I
I
D3CB26
D3CB26
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
DIMM_CA_VREF_B
DIMM_VREF_B
12
I
I
D3CB11
D3CB11
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
DIMMB0B
DIMMB0B
78
VDD10
75
VDD9
72
VDD8
69
VDD7
66
VDD6
65
VDD5
62
VDD4
60
VDD3
57
VDD2
54
VDD1
51
VDD0
240
VTT2
120
VTT1
113
GND27
110
GND26
107
GND25
104
GND24
101
GND23
98
GND22
95
GND21
92
GND20
89
GND19
86
GND18
83
GND17
80
GND16
47
GND15
44
GND14
41
GND13
38
GND12
35
GND11
32
GND10
29
GND9
26
GND8
23
GND7
20
GND6
17
GND5
14
GND4
11
GND3
8
GND2
5
GND1
2
GND0
67
VREFCA
1
VREFDQ
DDR3_DIMM_240P
DDR3_DIMM_240P
I
I
VDD21 VDD20 VDD19 VDD18 VDD17 VDD16 VDD15 VDD14 VDD13 VDD12 VDD11 GND59 GND58 GND57 GND56 GND55 GND54 GND53 GND52 GND51 GND50 GND49 GND48 GND47 GND46 GND45 GND44 GND43 GND42 GND41 GND40 GND39 GND38 GND37 GND36 GND35 GND34 GND33 GND32 GND31 GND30 GND29
GND28 NP_NC1 NP_NC2 NP_NC3
VDDSPD
1
197 194 191 189 186 183 182 179 176 173 170 239 235 232 229 226 223 220 217 214 211 208 205 202 199 166 163 160 157 154 151 148 145 142 139 136 133 130 127 124 121 119 116 241 242 243 236
+1P5V_DUAL+1P5 V_DUAL
+3P3V
GND
PEGATRON DT-MB RESTRICTED SECRET
DDR3 CHANNEL B
DDR3 CHANNEL B
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
3
2
Engineer:
IPM41-D3
IPM41-D3
IPM41-D3
DDR3 CHANNEL B
York Chang
York Chang
York Chang
1
Rev
Rev
Rev
1.00
1.00
18 55Thursday, July 09, 2009
18 55Thursday, July 09, 2009
18 55Thursday, July 09, 2009
1.00
5
D D
C C
+1P5V_DUAL
4
3
2
+1P5V_DUAL +1 P5V_DUAL
D3R01
D3R01 10K
10K
I
I
1 2
B
B
C
C
E12
3
E12
D3Q1
D3Q1
3
I
I
SLP_S5#[21,38] DDR3_DRAM_PWROK [12]
PMBS3904
PMBS3904
D3R02
D3R02 10K
10K
I
I
1 2
D3R03
D3R03 100KOHM
100KOHM
5%
5%
1 2
NI
NI
GND GND
12
I
I
D3C01
D3C01
0.1UF/16V
0.1UF/16V
1
12
I
I
D3CB33
D3CB33 1UF/10V
1UF/10V
mx_c0603
mx_c0603
GND GND GND GND GND GND GND GND
B B
A A
12
I
I
D3CB41
D3CB41
4.7UF/6.3V
4.7UF/6.3V
X5R 10%
X5R 10% mx_c0805
mx_c0805
GND GND GND GND
12
+
+
I
I
D3CE1
D3CE1 470uF/6.3V
470uF/6.3V
GND GND
12
I
I
D3CB34
D3CB34 1UF/10V
1UF/10V
mx_c0603
mx_c0603
12
I
I
D3CB42
D3CB42
4.7UF/6.3V
4.7UF/6.3V
X5R 10%
X5R 10% mx_c0805
mx_c0805
12
+
+
I
I
D3CE2
D3CE2 470uF/6.3V
470uF/6.3V
12
I
I
D3CB35
D3CB35 1UF/10V
1UF/10V
mx_c0603
mx_c0603
12
I
I
D3CB43
D3CB43
4.7UF/6.3V
4.7UF/6.3V
X5R 10%
X5R 10% mx_c0805
mx_c0805
12
I
I
D3CB36
D3CB36 1UF/10V
1UF/10V
mx_c0603
mx_c0603
12
I
I
D3CB44
D3CB44
4.7UF/6.3V
4.7UF/6.3V
X5R 10%
X5R 10% mx_c0805
mx_c0805
12
I
I
D3CB37
D3CB37 1UF/10V
1UF/10V
mx_c0603
mx_c0603
09511 modify by TSL
12
I
I
D3CB38
D3CB38 1UF/10V
1UF/10V
mx_c0603
mx_c0603
12
I
I
D3CB39
D3CB39 1UF/10V
1UF/10V
mx_c0603
mx_c0603
12
I
I
D3CB40
D3CB40 1UF/10V
1UF/10V
mx_c0603
mx_c0603
+0P75V_VTT_DDR
GND GND
12
GND GND
GND GND
12
I
I
DCB5
DCB5
0.1UF/16V
0.1UF/16V
I
I
DCB20
DCB20 1UF/10V
1UF/10V
mx_c0603
mx_c0603
12
I
I
DCB25
DCB25 10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10% mx_c0805
mx_c0805
12
12
I
I
DCB21
DCB21 1UF/10V
1UF/10V
mx_c0603
mx_c0603
I
I
DCB6
DCB6
0.1UF/16V
0.1UF/16V
12
I
I
DCB26
DCB26 10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10% mx_c0805
mx_c0805
09511 modify by TSL
PEGATRON DT-MB RESTRICTED SECRET
DECOUPLING
DECOUPLING
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
5
4
3
2
Engineer:
IPM41-D3
IPM41-D3
IPM41-D3
DECOUPLING
1
York Chang
York Chang
York Chang
19 55Thursday, July 09, 2009
19 55Thursday, July 09, 2009
19 55Thursday, July 09, 2009
Rev
Rev
Rev
1.00
1.00
1.00
5
A
ICH7 will not driver PME# high,but it will be pull up to +3VSB by an internal pull-up resistor
SU1A
SU1A
PGNT#3 PGNT#4 PGNT#5
PREQ#4 PREQ#5
SU1C
SU1C
DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15
DDACK# DDREQ DIOR# DIOW# IORDY
DA0 DA1 DA2
DCS1# DCS3#
IDEIRQ
ICH7
ICH7
E10 A12
B18
B19 B10 F15 E11 F14
F16
D16 D17 F13 A14
C16 C17 E13 A13
A9
A7
C9
E7
D8
D7
C8
A3 B4 C5 B5
G8
F7 F8
G7
IDE
IDE
I
I
PAR DEVSEL# PCICLK PCIRST# IRDY# PME# SERR# STOP# PLOCK# TRDY# PERR# FRAME#
GNT0# GNT1# GNT2# GNT3# GNT4#/GPIO48 GNT5#/GPIO17
REQ0# REQ1# REQ2# REQ3# REQ4#/GPIO22 GPIO1/REQ5#
PIRQA# PIRQB# PIRQC# PIRQD# GPIO2/PIRQE# GPIO3/PIRQF# GPIO4/PIRQG# GPIO5/PIRQH#
ICH7
ICH7
SATA_CLKN
SATA
SATA
SATA_CLKP
SATARBIASN SATARBIASP
GPIO21/SATA0GP GPIO19/SATA1GP GPIO36/SATA2GP GPIO37/SATA3GP
HOST
HOST
THERMTRIP#
PPAR[28,29]
5%
5% 5%
5% 5%
5% 5%
5%
RN8A RN8C RN8B RN8D
R1036
R1036
4.7K
4.7K
I
I
R1037
R1037
4.7K
4.7K
I
I
PDEVSEL#[28,29]
ICH_PCIRST#[28,29]
PIRDY#[28,29] PPME#[28,29]
PSERR#[28,29]
PSTOP#[28,29] PPLOCK#[28,29] PTRDY#[28,29] PPERR#[28,29] PFRAME#[28,29]
PGNT#4 PGNT#3 PREQ#4 PREQ#5
GNT0#[28] GNT1#[29]
PREQ#0[28] PREQ#1[28,29] PREQ#2[28] PREQ#3[28]
PINTA#[28] PINTB#[28] PINTC#[28] PINTD#[28] PINTE#[28,29] PINTF#[28,29] PINTG#[28,29] PINTH#[28,29]
AB15 AE14 AG13
AF13 AD14 AC13 AD12 AC12 AE12
AF12 AB13 AC14
AF14 AH13 AH14 AC15
AF16 AE15
AF15 AH15 AG16
AH17 AE17
AF17
AE16 AD16
AH16
CK_33M_ICH[5]
D D
+3P3VSB
SR85
SR85
8.2KOhm
8.2KOhm
/X
/X
1 2
NI
NI
SC74
SC74 5PF/50V
5PF/50V
NI
NI
/X
/X
1 2
GND
PPME#
C C
+3P3V
I RN8A
I
1 2
1KOHM
1KOHM
I RN8C
I
5 6
1KOHM
1KOHM
I RN8B
I
3 4
1KOHM
1KOHM
I RN8D
I
7 8
1KOHM
1KOHM
B B
+3P3V
12
+3P3V
12
PCI
PCI
I
I
SATA0RXN SATA0RXP SATA0TXN
SATA0TXP SATA1RXN SATA1RXP SATA1TXN
SATA1TXP SATA2RXN SATA2RXP SATA2TXN
SATA2TXP SATA3RXN SATA3RXP SATA3TXN
SATA3TXP
SATALED#
A20GATE
A20M#
CPUSLP#
IGNNE#
INIT3_3V#
INIT# INTR
FERR#
NMI
RCIN#
SERIRQ
SMI#
STPCLK#
4
C/BE0# C/BE1# C/BE2# C/BE3#
AF3 AE3 AG2 AH2 AE5 AD5 AG4 AH4 AF7 AE7 AG6 AH6 AD9 AE9 AG8 AH8 AF1 AE1
AH10 AG10 AF18
AF19 AH18 AH19 AE19
AE22 AH28 AG27 AG22 AG21 AF22 AF25 AG26 AH24 AG23 AH21 AF23 AH22 AF26
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8
AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
E18 C18 A16 F18 E16 A18 E17 A17 A15 C14 E14 D14 B12 C13 G15 G13 E12 C11 D11 A11 A10 F11 F10 E9 D9 B9 A8 A6 C7 B6 E6 D6
B15 C12 D12 C15
NI
NI
A_D0 A_D1 A_D2 A_D3 A_D4 A_D5 A_D6 A_D7 A_D8 A_D9 A_D10 A_D11 A_D12 A_D13 A_D14 A_D15 A_D16 A_D17 A_D18 A_D19 A_D20 A_D21 A_D22 A_D23 A_D24 A_D25 A_D26 A_D27 A_D28 A_D29 A_D30 A_D31
C/BE0#
C/BE0# [28,29]
C/BE1#
C/BE1# [28,29]
C/BE2#
C/BE2# [28,29]
C/BE3#
C/BE3# [28,29]
SATA_RXN0 [27] SATA_RXP0 [27] SATA_TXN0 [27] SATA_TXP0 [27] SATA_RXN1 [27] SATA_RXP1 [27] SATA_TXN1 [27] SATA_TXP1 [27] SATA_RXN2 [27] SATA_RXP2 [27] SATA_TXN2 [27] SATA_TXP2 [27] SATA_RXN3 [27] SATA_RXP3 [27] SATA_TXN3 [27] SATA_TXP3 [27] CK_100M_SATA# [5] CK_100M_SATA [5]
SATA_BIAS
SR102 24.9Ohm 1%
SR102 24.9Ohm 1%
1 2
ICH_SATALED# [27]
A20GATE [39] A20M# [7] PM_SLP# [7,13] IGNNE# [7]
HINIT# [6] INTR [7] HFERR# [7] NMI [7] RST_KB [39] SERIRQ [37,39] SMI# [7] STPCLK# [7] H_THMTRIP# [7]
12
SC24
SC24 150PF/50V
150PF/50V
/X
/X
GND
A_D[31..0] [28,29]
I
I
GND
NI
NI
GND
3 4
I
I
7 8
I
I
5 6
I
I
1 2
I
I
12
SC18
SC18 1000PF/50V
1000PF/50V
/X
/X
8.2KOHM
8.2KOHM
8.2KOHM
8.2KOHM
8.2KOHM
8.2KOHM
8.2KOHM
8.2KOHM
3
ICH_PCIRST#
SRN3B
SRN3B SRN3D
SRN3D SRN3C
SRN3C SRN3A
SRN3A
SC7 0.1 UF/16V
SC7 0.1 UF/16V
DMI_RXN0[10] DMI_RXP0[10]
SC9 0.1 UF/16V
SC9 0.1 UF/16V
DMI_RXN1[10] DMI_RXP1[10]
SC11 0.1UF/16V
SC11 0.1UF/16V
I
I
DMI_RXN2[10] DMI_RXP2[10]
SC13 0.1UF/16V
SC13 0.1UF/16V
I
I
DMI_RXN3[10] DMI_RXP3[10]
I
I
LAN_TXN[32] LAN_TXP[ 32]
Close to ICH7
<500mil
SC18 is used for tuning signal integrity.
+3P3V
Close to ICH7
SC8 0.1 UF/16V
SC8 0.1 UF/16V
12
I
I
SC10 0.1UF/16V
SC10 0.1UF/16V
12
I
I
I
I
SC12 0.1UF/16V
SC12 0.1UF/16V
12
I
I
I
I
SC14 0.1UF/16V
SC14 0.1UF/16V
12
I
I
SC5 0.1 UF/16V
SC5 0.1 UF/16V
12
SC6 0.1UF/16V
SC6 0.1UF/16V
ICH7_PCIE_CORE
SR89
SR89
24.9Ohm
24.9Ohm
1%
1%
1 2
I
I
HFERR#
H_THMTRIP#
L<3''
12
12
12
12
I
I
CK_100M_ICH#[5] CK_100M_ICH[5]
SR300 62 Ohm 5%I SR300 62 Ohm 5%I
1 2
SR301 62 Ohm 5%I SR301 62 Ohm 5%I
1 2
DMI_TXN0[10] DMI_TXP0[10]
DMI_TXN1[10] DMI_TXP1[10]
DMI_TXN2[10] DMI_TXP2[10]
DMI_TXN3[10] DMI_TXP3[10]
N_X1_RX#0[25] N_X1_RX0[25] N_X1_TX#0[25] N_X1_TX0[25]
12
LAN_RXN[32] LAN_RXP[32]
NI
NI
modify 6/20
DMI_TXN0 DMI_TXP0
DMI_TXN1 DMI_TXP1
DMI_TXN2 DMI_TXP2
DMI_TXN3 DMI_TXP3
6/30 modify del 2cap
DMI_ZCOMP DMI_IRCOMP
SC71
SC71 5PF/50V
5PF/50V
/X
/X
NI
NI
1 2
GND GND
+1P1V_FSB_VTT
1 2
CK_100M_SATA# CK_100M_SATA
2
V26 V25 U28 U27 Y26
Y25 W28 W27
AB26 AB25 AA28 AA27 AD25 AD24 AC28 AC27
F26
F25 E28 E27 H26 H25 G28 G27 K26 K25
J28
J27 M26 M25
L28
L27 P26 P25 N28 N27
T25
T24 R28 R27
C25 D25
AE28 AE27
SC72
SC72 5PF/50V
5PF/50V
/X
/X
A20GATE
SU1B
SU1B
DMI0RXN DMI0RXP DMI0TXN DMI0TXP DMI1RXN DMI1RXP DMI1TXN DMI1TXP DMI2RXN DMI2RXP DMI2TXN DMI2TXP DMI3RXN DMI3RXP DMI3TXN DMI3TXP
PERN_0 PERP_0 PETN_0 PETP_0 PERN_1 PERP_1 PETN_1 PETP_1 PERN_2 PERP_2 PETN_2 PETP_2 PERN_3 PERP_3 PETN_3 PETP_3 PERN_4 PERP_4 PETN_4 PETP_4 PERN_5 PERP_5 PETN_5 PETP_5
DMI_ZCOMP DMI_IRCOMP
DMI_CLKN DMI_CLKP
ICH7
ICH7
I
I
R_Measure
1 2
DMI
DMI
OC5#/GPIO29 OC6#/GPIO30 OC7#/GPIO31
PCI-E
PCI-E
SC20
SC20 5PF/50V
5PF/50V
/X
/X
1 2
NI
NI
NI
NI
GND GND
SR129
SR129
8.2KOhm
8.2KOhm
/X
/X
NI
NI
1
F1
USBP0N
F2
USBP0P
G4
USBP1N
G3
USBP1P
H1
USBP2N
H2
USBP2P
J4
USBP3N
J3
USBP3P
K1
USBP4N
K2
USBP4P
L4
USBP5N
L5
USBP5P
M1
USBP6N
M2
USBP6P
N4
USBP7N
N3
USBP7P
USB_OC0#
D3
OC0# OC1#
USB
USB
OC2# OC3# OC4#
USBRBIAS
USBRBIAS#
CLK48
USB_OC0#
C4
USB_OC0#
D5
USB_OC0#
D4
USB_OC0#
E5
USB_OC0#
C3
USB_OC0#
A2
USB_OC0#
B3
Place it within 500mils of ICH7,avoid routing next to clock pins
D1 D2
B2
I
I
SR88
SR88
1 2
20 OHM 1%
20 OHM 1%
Boot BIOS Destination Selection
Sampled at Rising edge of PWROK (GNT5# is MSB) 0 : SPI
SC19
SC19 5PF/50V
5PF/50V
/X
/X
1 2
+3P3V
<Variant Name>
<Variant Name>
<Variant Name>
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
1 : LPC (Weak internal pull-up)
PGNT#5
IPM41-D3
IPM41-D3
IPM41-D3
SC21
SC21
12
5PF/50V /X
5PF/50V /X
NI
NI
R_Measure
SR87
SR87 1KOhm
1KOhm
I
I
1 2
GND
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
USBN2 [30] USBP2 [30] USBN3 [30] USBP3 [30] USBN0 [33] USBP0 [33] USBN1 [33] USBP1 [33] USBN4 [31] USBP4 [31] USBN5 [31] USBP5 [31] USBN6 [31] USBP6 [31] USBN7 [31] USBP7 [31]
I
I
SR132
SR132
1 2
8.2KOHM1%
8.2KOHM1%
GND
CK_48M_USB [5]
LF FootPrint
ICH7-1
ICH7-1
ICH7-1
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
20 55Thursday, July 09, 2009
20 55Thursday, July 09, 2009
20 55Thursday, July 09, 2009
+3P3VSB
GND
Rev
Rev
Rev
1.00G
1.00G
1.00G
A
5
A
SU1D
SU1D
AA5
LDRQ1#/GPIO23
LAD0[ 37,39] LAD1[ 37,39] LAD2[ 37,39] LAD3[ 37,39]
LDRQ#[ 39]
LFRAME#[37,39]
D D
AZ_SDATA_IN0[34]
CK_14M_ICH[5]
add SR1818 & SR7878 modify 7/31
NI
NI
SR1818 0
SR1818 0
RSMRST#[38]
C C
SPI_MOSI[54]
SPI_MISO[54] SPI_CS#[54] SPI_CLK[54]
1 2
5%I SRN15C
5%I
5 6
47 OHM
47 OHM
RN14A RN14D RN14B RN14C
7/9 modify to 0603
12
GND
RTCRST#[55]
SMB_CLK_R[5,9,17,18,24,25,28,29] SMB_DATA_R[5,9,17,18,24,25,28,29]
SRN15C
5%I SRN15B
5%I
3 4
47 OHM
47 OHM
5%I SRN15A
5%I
1 2
47 OHM
47 OHM
5%I SRN15D
5%I
7 8
47 OHM
47 OHM
1 2
8.2KOHM
8.2KOHM
7 8
8.2KOHM
8.2KOHM
3 4
8.2KOHM
8.2KOHM
5 6
8.2KOHM
8.2KOHM
NI
NI
I
I
SR7878
SR7878
8.2KOHM
8.2KOHM
5% IRN14A
5% I 5% IRN14D
5% I 5% IRN14B
5% I 5% IRN14C
5% I
SC73
SC73 5PF/50V
5PF/50V
/X
/X
1 2
GND
SRN15B
SRN15A SRN15D
ACZ_BITCLK_R ACZ_RST#_R
ACZ_SDOUT_R ACZ_SYNC_R
ICH_RTCX1
RTCRST#
SMB_CLK_R SMB_DATA_R LINKALERT# SMBLINK0 SMBLINK1
SPI_+3VSB
B B
BATT_DUAL
12
I
I
SR123
SR123 10MOhm
10MOhm
5%
INTRUDER
INTRUDER
1 2
I
I
HEADER_1X2P
HEADER_1X2P
10/2 modify 12X602012B00
5%
mx_r0402
mx_r0402
ICH_INTRUDER#
GND
AA6
LAD0
AB5
LAD1
AC4
LAD2
Y6
LAD3
AC3
LDRQ0#
AB3
LFRAME#
U1
ACZ_BIT_CLK
R5
ACZ_RST#
T2
ACZ_SDIN0
T3
ACZ_SDIN1
T1
ACZ_SDIN2
T4
ACZ_SDOUT
R6
ACZ_SYNC
AC1
CLK14
W1
EE_CS
W3
EE_DIN
Y2
EE_DOUT
Y1
EE_SHCLK
V3
LAN_CLK
U3
LAN_RSTSYNC
C19
LAN_RST#
U5
LAN_RXD0
V4
LAN_RXD1
T5
LAN_RXD2
U7
LAN_TXD0
V6
LAN_TXD1
V7
LAN_TXD2
AB1
RTXC1
AB2
RTCX2
AA3
RTCRST#
B23
SMBALERT#/GPIO11
C22
SMBCLK
B22
SMBDATA
A26
LINKALERT#
B25
SMLINK0
A25
P5 P2 P6 R2 P1
SMLINK1
SPI_MOSI SPI_MISO SPI_CS# SPI_CLK SPI_ARB
ICH7
ICH7
ICH_SPI_MOSI
ICH_SPI_CS# ICH_SPI_CLK
RTC
ICH_RTCX2 ICH_RTCX1
1
1
1
I
I
SR71
SR71
0
0
1 2
1 2
12
I
I
SC27
SC27 12PF/50V
12PF/50V
NPO 5%
NPO 5%
I
I
SX1
SX1
32.768Khz
32.768Khz
GND GND
GND GND
324
324
3
4
I
I
GND
SR124
SR124 10MOhm 5%
10MOhm 5%
I
I
4
GPIO0/BM_BUSY#
LPC AUDIO
LPC AUDIO
GPIO10 GPIO12 GPIO13 GPIO14 GPIO15
GPIO16/DPRSLPVR
GPIO18/STPPCI#
GPIO20/STPCPU#
GPIO24 GPIO25
EPROM
EPROM
GPIO33/AZ_DOCK_EN#
GPIO34/AZ_DOCK_RST#
LAN
LAN
MISC
MISC
RTC SMB SPI
RTC SMB SPI
2
GPIO26 GPIO27 GPIO28
GPIO32/CLKRUN#
GPIO35 GPIO38 GPIO39
GPIO49/CPUPWRGD
THRM# VRMPWRGD MCH_SYNC#
PWRBTN#
SUS_STAT#
SUSCLK
SYS_RST#
PLTRST#
WAKE#
INTRUDER#
PWROK
RSMRST#
INTVRMEN
SLP_S3# SLP_S4# SLP_S5#
TP0/BATLOW#
TP1/DPRSTP#
TP2/DPSLP#
SMD (07X901232760)
12
I
I
SC28
SC28 12PF/50V
12PF/50V
NPO 5%
NPO 5%
GPIO6 GPIO7 GPIO8 GPIO9
SPKR
TP3
F_AUDIO_DET# [36]
1 2
GND
I
I
SR78
SR78
4.7K
4.7K
NOBOM
NOBOM
SP78
SP78
3
GPI1
4
GPI2
6
GND
PEGATRON_MFG
PEGATRON_MFG
3
9/1 modify
1 2
GND
NI
NI
SC67
SC67
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10% mx_c0603
mx_c0603
DPSLP# [7]
NP_NC1 NP_NC2 NP_NC3
PLED_N [44]
I
I
SR109
SR109
5.1KOHM
5.1KOHM
1%
1%
NI
NI
PWROK [13,38]
SC66
SC66
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
1 2
mx_c0603
mx_c0603
9/3 modify
GND
1 2 5
SMBus Switch
NI
NI
RTC Power-well Isolation Control
SMB_CLK_R SMB_DATA_R
IO_PME# WAKE#
12
SC25
SC25 10PF/50V
10PF/50V
/X
/X
GND
SBGPI38: Deafult High for new board, Low for forward compibility(P5LD2-TVM)
SBGPI38
I
I I
I
12
AZ_BITCLK[34]
Add MFG header 7/30
AB18 AC21 AC18 E21 E20 A20 F19 E19 R4 E22 AC22 AC20 AF21 R3 D20 A21 B21 E23 AG18 AC19 U2 AD21 AD20 AE20 AG24
AF20 AD22 AH20 C23 A28
RI#
A27 C20 A22 C26 F20 Y5 AA4 Y4 W4 A19
B24 D23 F22
C21 AF24 AH25 F21
MFG_NET
SB_GPIO9 SB_GPIO10 SB_GPIO12
IO_PME#
CLKRUN#
SBGPI38
ICH_THRM# VRMPWRGD_ICH ICH_SYNC# IO_PWRBTN# RING# LPCPD#
SYS_RESET#ICH_RTCX2
WAKE#
ICH_INTRUDER#SMBALERT#
PWROK
RSMRST#
ICH_INTVRMEN
ICH_TP0
MFG_NET
LPC_PME# [38]
CLKRUN# [37]
CPUPWRGD [7,9]
LPC_SMI# [38] VRMPWRGD_ICH [5,51] ICH_SYNC# [13] SB_PWRBTN# [38] RING# [41]
LPCPD# [37]
SYS_RESET# [7,9,38,44]
LRESET# [13,37,39]
WAKE# [24,25,32]
RSMRST# [38]
SPKR [55]
SLP_S3# [38] SLP_S5# [19,38]
+3P3V
12
GND
5 6
2.7KOHM
2.7KOHM
7 8
2.7KOHM
2.7KOHM
1 2
I
I
2.7KOHM
2.7KOHM
3 4
I
I
2.7KOHM
2.7KOHM
SMB_CLK_R
SMB_DATA_R
SC26
SC26 10PF/50V
10PF/50V
/X
/X
NI
NI
SR5 1K 1%
SR5 1K 1%
I
I
1 2
SR6
SR6
1 2
0Ohm /X
0Ohm /X
NI
NI
SC70
SC70
22PF/50V
22PF/50V
NPO 5%
NPO 5%
2
I
I
SRN2C
SRN2C SRN2D
SRN2D
6/23 modify
1 2
GND
SRN2A
SRN2A SRN2B
SRN2B
1.00 Intel recommend Dual power for different SMBus Devices But only implement Main power here
SMBus connect to two kind of devices, one use Main power, another use Standby power, so use this switch circuit to isolate those two device. SMB_CLK and SMB_DATA for Standby device. SMB_CLK_MAIN and SMB_DATA_MAIN for Main power device.
+3P3VSB
+3P3VSB
+3P3V
GND
AZ_RST#[34]
AZ_SDATA_OUT[34]
AZ_SYNC[34]
SMBALERT# LINKALERT# SMBLINK0 SMBLINK1
ICH_THRM#
IO_PWRBTN# SYS_RESET# ICH_TP0
ICH_INTVRMEN
SB_GPIO9 SB_GPIO10 SB_GPIO12
SMB_CLK_R
SMB_DATA_R
1 2
I
I
2.7KOHM
2.7KOHM
7 8
I
I
2.7KOHM
2.7KOHM
3 4
I
I
2.7KOHM
2.7KOHM
5 6
I
I
2.7KOHM
2.7KOHM
3 4
I
I
8.2KOHM
8.2KOHM
7 8
I
I
8.2KOHM
8.2KOHM
5 6
I
I
8.2KOHM
8.2KOHM
1 2
I
I
8.2KOHM
8.2KOHM
1 2
SR116 390KOHM 5%I SR116 390KOHM 5%I
3 4
I
I
1KOHM
1KOHM
7 8
I
I
1KOHM
1KOHM
5 6
I
I
1KOHM
1KOHM
1 2
I
I
1KOHM
1KOHM
7 8
I
I
33OHM
33OHM
1 2
I
I
33OHM
33OHM
5 6
I
I
33OHM
33OHM
3 4
I
I
33OHM
33OHM
SRN4A
SRN4A SRN4D
SRN4D SRN4B
SRN4B SRN4C
SRN4C
SRN5B
SRN5B SRN5D
SRN5D SRN5C
SRN5C SRN5A
SRN5A
FRN1B
FRN1B FRN1D
FRN1D FRN1C
FRN1C FRN1A
FRN1A
SRN9D
SRN9D
SRN9A
SRN9A
SRN9C
SRN9C
SRN9B
SRN9B
1
SMB_CLK_R [5,9,17,18,24,25,28,29]
SMB_DATA_R [5,9,17,18,24,25,28,29]
+3P3VSB
+3P3VSB
+3P3V
BATT_DUAL
1.00
SR32 Intel recommend 330K
+3P3VSB
6/23 modify
ACZ_BITCLK_R
ACZ_RST#_R
ACZ_SDOUT_R
ACZ_SYNC_R
GND GND
I
I
XSX1
XSX1
Add MFG header 7/30
A
<Variant Name>
<Variant Name>
<Variant Name>
Crystal Holder
Crystal Holder
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
IPM41-D3
IPM41-D3
IPM41-D3
Engineer:
Title :
Title :
Title :
ICH7-2
ICH7-2
ICH7-2
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
21 55Thursday, July 09, 2009
21 55Thursday, July 09, 2009
21 55Thursday, July 09, 2009
Rev
Rev
Rev
1.00G
1.00G
1.00G
5
A
+1P5V_ICH +1P5V_ICH
12
12
SC29
SC29
0.1UF/25V
0.1UF/25V
c0603
c0603 /X
/X
NI
D D
NI
NI
NI
SC30
SC30
0.1UF/25V
0.1UF/25V
c0603
c0603 /X
/X
12
I
I
+1P5V_ICH
C C
NI
NI
B B
HEATSINK2
HEATSINK2
2
HEATSINK
HEATSINK
/X
/X
NI
NI
12
SC31
SC31
0.1UF/25V
0.1UF/25V
c0603
c0603
GND GND
NI
NI
SC32
SC32
0.1UF/25V
0.1UF/25V
c0603
c0603
I
I
12
SC45
SC45 1UF/10V
1UF/10V
c0603
c0603 /X
/X
12
SC56
SC56
0.1UF/25V
0.1UF/25V
c0603
c0603 /X
/X
GND GND GND
1
NI
NI
SL1
SL1
21
70Ohm/100Mhz
70Ohm/100Mhz
I
I
12
SC57
SC57
0.1UF/25V
0.1UF/25V
c0603
c0603
I
I
12
SC63
SC63
0.1UF/25V
0.1UF/25V
c0603
c0603
NI
NI
/X
/X
GND GND
12
SC33
SC33 1UF/10V
1UF/10V
c0603
c0603 /X
/X
ICH7_PCIE_CORE
NI
NI
NI
NI
NI
NI
GND
12
+
+
SCE1
SCE1 100uF/16V
100uF/16V
/X
/X
12
12
12
NI
NI
SC34
SC34 1UF/10V
1UF/10V
mx_c0603
mx_c0603
10/2 modify
SC58
SC58
0.1UF/25V
0.1UF/25V
c0603
c0603 /X
/X
SC64
SC64
0.1UF/25V
0.1UF/25V
c0603
c0603 /X
/X
4
SU1E
SU1E
A1 AB10 AB17
AB7 AB8
AB9 AC10 AC17
AC6
AC7
AC8 AD10
AD6 AE10
AE6
AF10
AF5
AF6
AF9
AG5
AG9
AH5
AH9
G17
D26
D27
D28
E24
E25
E26
G22
G23
H22
H23
K22
K23
M22
M23
N22
N23
P22
P23
R22
R23
R24
R25
R26
U22
U23
V22
V23
W22 W23
Y22
Y23 AA22 AA23 AB22 AB23 AC23 AC24 AC25 AC26 AD26 AD27 AD28
F17
F23 F24
J22 J23
L22 L23
T22 T23 T26 T27 T28
H6 H7
J6 J7
T7
VCC1_5_A_1 VCC1_5_A_2 VCC1_5_A_3 VCC1_5_A_4 VCC1_5_A_5 VCC1_5_A_6 VCC1_5_A_7 VCC1_5_A_8 VCC1_5_A_9 VCC1_5_A_10 VCC1_5_A_11 VCC1_5_A_12 VCC1_5_A_13 VCC1_5_A_14 VCC1_5_A_15 VCC1_5_A_16 VCC1_5_A_17 VCC1_5_A_18 VCC1_5_A_19 VCC1_5_A_20 VCC1_5_A_21 VCC1_5_A_22 VCC1_5_A_23 VCC1_5_A_24 VCC1_5_A_25 VCC1_5_A_26 VCC1_5_A_27 VCC1_5_A_28 VCC1_5_A_29 VCC1_5_A_30
VCC1_5_B_1 VCC1_5_B_2 VCC1_5_B_3 VCC1_5_B_4 VCC1_5_B_5 VCC1_5_B_6 VCC1_5_B_7 VCC1_5_B_8 VCC1_5_B_9 VCC1_5_B_10 VCC1_5_B_11 VCC1_5_B_12 VCC1_5_B_13 VCC1_5_B_14 VCC1_5_B_15 VCC1_5_B_16 VCC1_5_B_17 VCC1_5_B_18 VCC1_5_B_19 VCC1_5_B_20 VCC1_5_B_21 VCC1_5_B_22 VCC1_5_B_23 VCC1_5_B_24 VCC1_5_B_25 VCC1_5_B_26 VCC1_5_B_27 VCC1_5_B_28 VCC1_5_B_29 VCC1_5_B_30 VCC1_5_B_31 VCC1_5_B_32 VCC1_5_B_33 VCC1_5_B_34 VCC1_5_B_35 VCC1_5_B_36 VCC1_5_B_37 VCC1_5_B_38 VCC1_5_B_39 VCC1_5_B_40 VCC1_5_B_41 VCC1_5_B_42 VCC1_5_B_43 VCC1_5_B_44 VCC1_5_B_45 VCC1_5_B_46 VCC1_5_B_47 VCC1_5_B_48 VCC1_5_B_49 VCC1_5_B_50 VCC1_5_B_51 VCC1_5_B_52 VCC1_5_B_53
ICH7
ICH7
I
I
VccSus3_3/VccLAN3_3_0 VccSus3_3/VccLAN3_3_1 VccSus3_3/VccLAN3_3_2 VccSus3_3/VccLAN3_3_3
VccSus1_05/VccLAN1_05_1
VccSus1_05/VccLAN1_05_0
V5REF_1 V5REF_2
V5REF_SUS
VCCRTC
VCCUSBPLL
VCCSATAPLL
VCCDMIPLL
VCC1_05_1 VCC1_05_2 VCC1_05_3 VCC1_05_4 VCC1_05_5 VCC1_05_6 VCC1_05_7 VCC1_05_8
VCC1_05_9 VCC1_05_10 VCC1_05_11 VCC1_05_12 VCC1_05_13 VCC1_05_14 VCC1_05_15 VCC1_05_16 VCC1_05_17 VCC1_05_18 VCC1_05_19 VCC1_05_20
V_CPU_IO_1 V_CPU_IO_2
POWER
POWER
V_CPU_IO_3
VCC3_3_1 VCC3_3_2 VCC3_3_3 VCC3_3_4 VCC3_3_5 VCC3_3_6 VCC3_3_7 VCC3_3_8
VCC3_3_9 VCC3_3_10 VCC3_3_11 VCC3_3_12 VCC3_3_13 VCC3_3_14 VCC3_3_15 VCC3_3_16 VCC3_3_17 VCC3_3_18 VCC3_3_19 VCC3_3_20 VCC3_3_21
Vcc3_3/VccHDA
VCCSUS3_3_1 VCCSUS3_3_2 VCCSUS3_3_3 VCCSUS3_3_4 VCCSUS3_3_5 VCCSUS3_3_6 VCCSUS3_3_7 VCCSUS3_3_8
VCCSUS3_3_9 VCCSUS3_3_10 VCCSUS3_3_11 VCCSUS3_3_12 VCCSUS3_3_13 VCCSUS3_3_14 VCCSUS3_3_15 VCCSUS3_3_16 VCCSUS3_3_17 VCCSUS3_3_18 VCCSUS3_3_19
VccSus3_3/VccSusHDA
VCCSUS1_05_2 VCCSUS1_05_3 VCCSUS1_05_4
AD17 G10
F6
W5
C1
AD2
AG28
L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18
AE23 AE26 AH26
A5 AA7 AB12 AB20 AC16 AD13 AD18 AG12 AG15 AG19 AH11 B13 B16 B27 B7 C10 D15 F9 G11 G12 G16 U6 A24 C24 D19 D22 E3 G19 K3 K4 K5 K6 L1 L2 L3 L6 L7 M6 M7 N7 P7 R7 V1 V5 W2 W7
AA2 C28 G20 K7 Y7
3
V5REF
V5REF_AUA
VCCUSBPLL
VCCSATAPLL
VCCDMPLL
SB_K7
2
r0603_h24
r0603_h24
12
SC51
SC51
0.1UF/25V
0.1UF/25V
c0603
c0603 /X
/X
NI
NI
IPM41-D3
IPM41-D3
IPM41-D3
+5VSB
SR126 1 0Ohm
SR126 1 0Ohm
I
I
1 2
12
SC35
SC35
0.1UF/25V
0.1UF/25V
c0603
c0603 /X
/X
NI
NI
+1P1V_CORE
12
SC44
SC44
0.1UF/25V
0.1UF/25V
c0603
c0603 /X
/X
GND
12
SC54
SC54
0.1UF/25V
0.1UF/25V
c0603
c0603 /X
/X
SC60
SC60
0.1UF/25V
0.1UF/25V
c0603
c0603 /X
/X
12
SC39
SC39
0.1UF/25V
0.1UF/25V
c0603
c0603 /X
/X
NI
NI
GND
+3P3V
SC48
SC48
0.1UF/25V
0.1UF/25V
c0603
c0603
SC61
SC61
0.1UF/25V
0.1UF/25V
c0603
c0603 /X
/X
NI
NI
GND
+3P3VSB
NI
NI
12
SC49
SC49
0.1UF/25V
0.1UF/25V
c0603
c0603 /X
/X
12
GND
SC62
SC62
0.1UF/16V
0.1UF/16V
c0603
c0603 /X
/X
12
I
I
12
NI
NI
12
12
SC37
SC37
0.1UF/16V
0.1UF/16V
c0603
c0603 /X
/X
NI
NI
NI
NI
12
SC46
SC46
0.1UF/25V
0.1UF/25V
c0603
c0603 /X
/X
NI
NI
12
I
I
12
SC59
SC59
0.1UF/25V
0.1UF/25V
c0603
c0603 /X
/X
NI
NI
I
I
NI
NI
12
SC43
SC43
0.1UF/25V
0.1UF/25V
c0603
c0603 /X
/X
NI
NI
SC53
SC53
0.1UF/25V
0.1UF/25V
c0603
c0603
12
SC65
SC65
0.1UF/25V
0.1UF/25V
c0603
c0603
GND
SC38
SC38
0.1UF/25V
0.1UF/25V
c0603
c0603 /X
/X
+1P1V_FSB_VTT
NI
NI
12
SC47
SC47
0.1UF/25V
0.1UF/25V
c0603
c0603 /X
/X
NI
NI
GND
12
NI
NI
GND GND
12
SC50
SC50 10UF/6.3V
10UF/6.3V
c1206_h55
c1206_h55 /X
/X
NI
NI
GND GND
12
SC55
SC55
0.1UF/25V
0.1UF/25V
I
I
GND
<Variant Name>
<Variant Name>
<Variant Name>
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
SR125
SR125
I
I
1KOhm
1KOhm
r0603_h24
r0603_h24
SD2
SD2
3
12
SC36
SC36
0.1UF/25V
0.1UF/25V
c0603
c0603
I
I
I
I
SC40
SC40
0.1UF/16V
0.1UF/16V
c0603
c0603
NI
NI
NOBOM
NOBOM
NJP11
NJP11 SHORTPIN_RECT
SHORTPIN_RECT
NOBOM
NOBOM
NJP12
NJP12 SHORTPIN_RECT
SHORTPIN_RECT
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
1%
1%
12
2
1
BAT54CW
BAT54CW
BATT_DUAL
12
I
I
/X
/X
+1P5V_ICH
12
12
GND
12
SC42
SC42
0.1UF/25V
0.1UF/25V
c0603
c0603
I
I
GND
+1P5V_ICH
I
I
GND
+1P5V_ICH
ICH7-3
ICH7-3
ICH7-3
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
22 55Thursday, July 09, 2009
22 55Thursday, July 09, 2009
22 55Thursday, July 09, 2009
12
SC41
SC41
0.1UF/25V
0.1UF/25V
c0603
c0603
12
SC52
SC52
0.1UF/25V
0.1UF/25V
c0603
c0603
+5V
+3P3V
Rev
Rev
Rev
1.00G
1.00G
1.00G
A
5
D D
C C
B B
A A
5
4
SU1F
SU1F
E4
VSS1
AG11
VSS2
C27
VSS3
R14
VSS4
R15
VSS5
R16
VSS6
R17
VSS7
R18
VSS8
T6
VSS9
T12
VSS10
T13
VSS11
T14
VSS12
T15
VSS13
T16
VSS14
T17
VSS15
U4
VSS16
U12
VSS17
U13
VSS18
U14
VSS19
U15
VSS20
U16
VSS21
U17
VSS22
U24
VSS23
U25
VSS24
U26
VSS25
V2
VSS26
V13
VSS27
V15
VSS28
V24
VSS29
V27
VSS30
V28
VSS31
W6
VSS32
W24
VSS33
W25
VSS34
W26
VSS35
Y3
VSS36
Y24
VSS37
Y27
VSS38
Y28
VSS39
AA1
VSS40
AA24
VSS41
AA25
VSS42
AA26
VSS43
AB4
VSS44
AB6
VSS45
AB11
VSS46
AB14
VSS47
AB16
VSS48
AB19
VSS49
AB21
VSS50
AB24
VSS51
AB27
VSS52
AB28
VSS53
AC2
VSS54
AC5
VSS55
AC9
VSS56
AC11
VSS57
AD1
VSS58
AD3
VSS59
AD4
VSS60
AD7
VSS61
AD8
VSS62
AD11
VSS63
AD15
VSS64
AD19
VSS65
AD23
VSS66
AE2
VSS67
AE4
VSS68
AE8
VSS69
AE11
VSS70
AE13
VSS71
AE18
VSS72
AE21
VSS73
AE24
VSS74
AE25
VSS75
AF2
VSS76
AF4
VSS77
AF8
VSS78
AF11
VSS79
AF27
VSS80
AF28
VSS81
AG1
VSS82
AG3
VSS83
AG7
VSS84
AG14
VSS85
AG17
VSS86
AG20
VSS87
AG25
VSS88
AH1
VSS89
AH3
VSS90
AH7
VSS91
AH23
VSS92
AH27
VSS93
AH12
VSS94
ICH7
GND GND
4
ICH7
I
I
3
VSS95 VSS96 VSS97 VSS98
VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194
3
A4 A23 B1 B8 B11 B14 B17 B20 B26 B28 C2 C6 D10 D13 D18 D21 D24 E1 E2 E8 E15 F3 F4 F5 F12 F27 F28 G1 G2 G5 G6 G9 G14 G18 G21 G24 G25 G26 H3 H4 H5 H24 H27 H28 J1 J2 J5 J24 J25 J26 K24 K27 K28 L13 L15 L24 L25 L26 M3 M4 M5 M12 M13 M14 M15 M16 M17 M24 M27 M28 N1 N2 N5 N6 N11 N12 N13 N14 N15 N16 N17 N18 N24 N25 N26 P3 P4 P12 P13 P14 P15 P16 P17 P24 P27 P28 R1 R11 R12 R13
2
<Variant Name>
<Variant Name>
<Variant Name>
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
IPM41-D3
IPM41-D3
IPM41-D3
1
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
1
ICH7-4
ICH7-4
ICH7-4
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
23 55Thursday, July 09, 2009
23 55Thursday, July 09, 2009
23 55Thursday, July 09, 2009
Rev
Rev
Rev
1.00G
1.00G
1.00G
5
4
3
2
1
PCI EXPRESS X16 Graphics Card Slot
GND
+12V
CK_100M_PCIEX16 [5] CK_100M_PCIEX16# [5]
EXP_RXP0 [10] EXP_RXN0 [10]
EXP_RXP1 [10] EXP_RXN1 [10]
EXP_RXP2 [10] EXP_RXN2 [10]
EXP_RXP3 [10] EXP_RXN3 [10]
EXP_RXP4 [10] EXP_RXN4 [10]
EXP_RXP5 [10] EXP_RXN5 [10]
EXP_RXP6 [10] EXP_RXN6 [10]
EXP_RXP7 [10] EXP_RXN7 [10]
EXP_RXP8 [10] EXP_RXN8 [10]
EXP_RXP9 [10] EXP_RXN9 [10]
EXP_RXP10 [1 0] EXP_RXN10 [10]
EXP_RXP11 [1 0] EXP_RXN11 [10]
EXP_RXP12 [10] EXP_RXN12 [10]
EXP_RXP13 [1 0] EXP_RXN13 [10]
EXP_RXP14 [1 0] EXP_RXN14 [10]
EXP_RXP15 [1 0] EXP_RXN15 [10]
+3P3V
PCIES_RST# [25,32,38]
GND
12
I
I
XCB3
XCB3
0.1UF/16V
0.1UF/16V
12
GND
NI
NI
XC1
XC1 1000PF/50V
1000PF/50V
X7R 10%
X7R 10%
ASUS OEM-DT MB RESTRICTED SECRET
Title :
Title :
Title :
PCI EXPRESS X16
PCI EXPRESS X16
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Engineer:
IPM41-D3
IPM41-D3
IPM41-D3
PCI EXPRESS X16
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
24 55Thursday, July 09, 2009
24 55Thursday, July 09, 2009
24 55Thursday, July 09, 2009
1
Rev
Rev
Rev
1.00G
1.00G
1.00G
I
+3P3V
+3P3VSB
D D
C C
B B
A A
12
+
+
I
I
XCE1
XCE1 470uF/16V
470uF/16V
GND GND
EXP_TXP0[10] EXP_TXN0[10]
SDVO_CTRL_CLK[10]
EXP_TXP1[10] EXP_TXN1[10]
EXP_TXP2[10] EXP_TXN2[10]
EXP_TXP3[10] EXP_TXN3[10]
SDVO_CTRL_DATA[10]
EXP_TXP4[10] EXP_TXN4[10]
EXP_TXP5[10] EXP_TXN5[10]
EXP_TXP6[10] EXP_TXN6[10]
EXP_TXP7[10] EXP_TXN7[10]
EXP_EN_HDR[13]
EXP_TXP8[10] EXP_TXN8[10]
EXP_TXP9[10] EXP_TXN9[10]
EXP_TXP10[10] EXP_TXN10[10]
EXP_TXP11[10] EXP_TXN11[10]
EXP_TXP12[10] EXP_TXN12[10]
EXP_TXP13[10] EXP_TXN13[10]
EXP_TXP14[10] EXP_TXN14[10]
EXP_TXP15[10] EXP_TXN15[10]
12
I
I
XCB1
XCB1
0.1UF/16V
0.1UF/16V
12
I
I
XCB2
XCB2
0.1UF/16V
0.1UF/16V
GND
XC2 0.1UF/16 V X7R 10%
XC2 0.1UF/16 V X7R 10%
I
I
XC3 0.1UF/16 V X7R 10%
XC3 0.1UF/16 V X7R 10%
I
I
XC4 0.1UF/16 V X7R 10%
XC4 0.1UF/16 V X7R 10%
I
I
XC5 0.1UF/16 V X7R 10%
XC5 0.1UF/16 V X7R 10%
I
I
XC6 0.1UF/16 V X7R 10%
XC6 0.1UF/16 V X7R 10%
I
I
XC7 0.1UF/16 V X7R 10%
XC7 0.1UF/16 V X7R 10%
I
I
XC8 0.1UF/16 V X7R 10%
XC8 0.1UF/16 V X7R 10%
I
I
XC9 0.1UF/16 V X7R 10%
XC9 0.1UF/16 V X7R 10%
I
I
XC10 0.1UF/16V X7R 10%
XC10 0.1UF/16V X7R 10%
I
I
XC11 0.1UF/16V X7R 10%
XC11 0.1UF/16V X7R 10%
I
I
XC12 0.1UF/16V X7R 10%
XC12 0.1UF/16V X7R 10%
I
I
XC13 0.1UF/16V X7R 10%
XC13 0.1UF/16V X7R 10%
I
I
XC14 0.1UF/16V X7R 10%
XC14 0.1UF/16V X7R 10%
I
I
XC15 0.1UF/16V X7R 10%
XC15 0.1UF/16V X7R 10%
I
I
XC16 0.1UF/16V X7R 10%
XC16 0.1UF/16V X7R 10%
I
I
XC17 0.1UF/16V X7R 10%
XC17 0.1UF/16V X7R 10%
I
I
XC18 0.1UF/16V X7R 10%
XC18 0.1UF/16V X7R 10%
I
I
XC19 0.1UF/16V X7R 10%
XC19 0.1UF/16V X7R 10%
I
I
XC20 0.1UF/16V X7R 10%
XC20 0.1UF/16V X7R 10%
I
I
XC21 0.1UF/16V X7R 10%
XC21 0.1UF/16V X7R 10%
I
I
XC22 0.1UF/16V X7R 10%
XC22 0.1UF/16V X7R 10%
I
I
XC23 0.1UF/16V X7R 10%
XC23 0.1UF/16V X7R 10%
I
I
XC24 0.1UF/16V X7R 10%
XC24 0.1UF/16V X7R 10%
I
I
XC25 0.1UF/16V X7R 10%
XC25 0.1UF/16V X7R 10%
I
I
XC26 0.1UF/16V X7R 10%
XC26 0.1UF/16V X7R 10%
I
I
XC27 0.1UF/16V X7R 10%
XC27 0.1UF/16V X7R 10%
I
I
XC28 0.1UF/16V X7R 10%
XC28 0.1UF/16V X7R 10%
I
I
XC29 0.1UF/16V X7R 10%
XC29 0.1UF/16V X7R 10%
I
I
XC30 0.1UF/16V X7R 10%
XC30 0.1UF/16V X7R 10%
I
I
XC31 0.1UF/16V X7R 10%
XC31 0.1UF/16V X7R 10%
I
I
XC32 0.1UF/16V X7R 10%
XC32 0.1UF/16V X7R 10%
I
I
XC33 0.1UF/16V X7R 10%
XC33 0.1UF/16V X7R 10%
I
I
5
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
SMB_CLK_R[5,9,17,18,21,25,28,29] SMB_DATA_R[5,9,17,18,21,25,28,29] PCIE_B7[13]
WAKE#[21,25,32]
EXP_TXP0_C EXP_TXN0_C
EXP_TXP1_C EXP_TXN1_C
EXP_TXP2_C EXP_TXN2_C
EXP_TXP3_C EXP_TXN3_C
EXP_TXP4_C EXP_TXN4_C
EXP_TXP5_C EXP_TXN5_C
EXP_TXP6_C EXP_TXN6_C
EXP_TXP7_C EXP_TXN7_C
EXP_TXP8_C
EXP_TXN8_C
EXP_TXP9_C EXP_TXN9_C
EXP_TXP10_C EXP_TXN10_C
EXP_TXP11_C EXP_TXN11_C
EXP_TXP12_C EXP_TXN12_C
EXP_TXP13_C EXP_TXN13_C
EXP_TXP14_C EXP_TXN14_C
EXP_TXP15_C EXP_TXN15_C
4
+12V
GND
I
J41
J41
SLOT 164P,PCI-E X16
SLOT 164P,PCI-E X16
B1
+12V_1
B2
+12V_2
B3
RSVD1
B4
GND1
B5
SMCLK
B6
SMDAT
B7
GND2
B8
+3.3V_1
B9
JTAG1
B10
3.3Vaux
B11
WAKE#
B12
RSVD2
B13
GND3
B14
HSOP0
B15
HSON0
B16
GND4
B17
PRSNT2_1#
B18
GND5
B19
HSOP1
B20
HSON1
B21
GND6
B22
GND7
B23
HSOP2
B24
HSON2
B25
GND8
B26
GND9
B27
HSOP3
B28
HSON3
B29
GND10
B30
RSVD3
B31
PRSNT2_2#
B32
GND11
B33
HSOP4
B34
HSON4
B35
GND12
B36
GND13
B37
HSOP5
B38
HSON5
B39
GND14
B40
GND15
B41
HSOP6
B42
HSON6
B43
GND16
B44
GND17
B45
HSOP7
B46
HSON7
B47
GND18
B48
PRSNT2_3#
B49
GND19
B50
HSOP8
B51
HSON8
B52
GND20
B53
GND21
B54
HSOP9
B55
HSON9
B56
GND22
B57
GND23
B58
HSOP10
B59
HSON10
B60
GND24
B61
GND25
B62
HSOP11
B63
HSON11
B64
GND26
B65
GND27
B66
HSOP12
B67
HSON12
B68
GND28
B69
GND29
B70
HSOP13
B71
HSON13
B72
GND30
B73
GND31
B74
HSOP14
B75
HSON14
B76
GND32
B77
GND33
B78
HSOP15
B79
HSON15
B80
GND34
B81
PRSNT2_4#
B82
RSVD4
2
A1
PRSNT1#
A2
+12V_3 +12V_4
GND35 JTAG2 JTAG3 JTAG4
JTAG5 +3.3V_2 +3.3V_3
PWRGD
GND36
REFCLK+
REFCLK-
GND37
HSIP0 HSIN0
GND38
RSVD6
GND39
HSIP1
HSIN1 GND40 GND41
HSIP2
HSIN2 GND42 GND43
HSIP3
HSIN3 GND44 RSVD7
RSVD8 GND45
HSIP4
HSIN4 GND46 GND47
HSIP5
HSIN5 GND48 GND49
HSIP6
HSIN6 GND50 GND51
HSIP7
HSIN7 GND52 RSVD9 GND53
HSIP8
HSIN8 GND54 GND55
HSIP9
HSIN9 GND56 GND57
HSIP10
HSIN10
GND58 GND59 HSIP11
HSIN11
GND60 GND61 HSIP12
HSIN12
GND62 GND63
HSIP13
HSIN13
GND64 GND65 HSIP14
HSIN14
GND66 GND67 HSIP15
HSIN15
GND68
A3 A4 A5 A6 A7 A8 A9 A10 A11
A12 A13 A14 A15 A16 A17 A18
A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32
A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71
A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82
3
NP_NC11NP_NC2
5
D D
+3P3V
SMB_CLK_R[5,9,17,18,21,24,28,29] SMB_DATA_R[5,9,17,18,21,24,28,29]
WAKE#[21,24,32]
C C
12
+
+
I
I
X1CE1
X1CE1 820UF/6.3V
820UF/6.3V
4
12
I
I
X1CB3
X1CB3
0.1UF/16V
0.1UF/16V
+3P3VSB
12
I
I
X1CB4
X1CB4
0.1UF/16V
0.1UF/16V
3
PCI Express x1 SLOT
PCI Express x1 SLOT
PCI Express x1 SLOTPCI Express x1 SLOT
I
I
J36
+12V
GND
J36
SLOT 36P,PCI-E X1
SLOT 36P,PCI-E X1
B1
+12V_1
B2
+12V_2
B3
+12V_5
B4
GND1
B5
SMCLK
B6
SMDAT
B7
GND2
B8
+3.3V_1
B9
JTAG1
B10
3.3Vaux
B11
WAKE#
PRSNT1#
+12V_3 +12V_4
GND6 JTAG2 JTAG3 JTAG4 JTAG5
+3.3V_2 +3.3V_3 PWRGD
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
2
+12V
+3P3V
12
I
I
X1CB5
X1CB5
0.1UF/16V
0.1UF/16V
12
I
I
X1CB6
X1CB6
0.1UF/16V
0.1UF/16V
1
PCIES_RST# [24,32,38]
GND
X1C1 0.1UF/16V X7R 10%
X1C1 0.1UF/16V X7R 10%
I
I
N_X1_TX0[20] N_X1_TX#0[20]
B B
A A
1.Place Near to slot
2.Please check if another side already have installed serial capacitor
1 2
X1C2 0.1UF/16V X7R 10%
X1C2 0.1UF/16V X7R 10%
I
I
1 2
GND
GND
PE1_TXP1_C PE1_TXN1_C
GND
B12 B13 B14 B15 B16 B17 B18
RSVD2 GND3 HSOP0 HSON0 GND4 PRSNT2_1# GND5
GND7
REFCLK+
REFCLK-
GND8
HSIP0
HSIN0
GND9
NP_NC1 NP_NC2
A12 A13 A14 A15 A16 A17 A18
1 2
GND
GNDGND
CK_100M_PCIEX1 [5] CK_100M_PCIEX1# [5]
N_X1_RX0 [20] N_X1_RX#0 [20]
ASUS MBRD2_CET RESTRICTED SECRET
PCI EXPRESS X1
PCI EXPRESS X1
PCI EXPRESS X1
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
5
4
3
2
Engineer:
IPM41-D3
IPM41-D3
IPM41-D3
1
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
25 55Thursday, July 09, 2009
25 55Thursday, July 09, 2009
25 55Thursday, July 09, 2009
Rev
Rev
Rev
1.00G
1.00G
1.00G
5
4
3
2
1
+5V
12
I
I
VCB1
1
2
I
I
VD1
VD1 BAV99W-L
BAV99W-L
D D
VGA_RED[13]
VGA_GREEN[13]
C C
VGA_BLUE[13]
3
1
2
3
NOTE:
Place there VGA filter components
I
I
VD2
VD2 BAV99W-L
BAV99W-L
2
I
I
VD3
VD3 BAV99W-L
BAV99W-L
3
GND
12
I
I
VR1
VR1 150
150
1%
1%
12
I
I
VR2
VR2 150
150
1%
1%
12
I
I
VR4
VR4 150
150
1%
1%
1
VCB1
0.1UF/16V
0.1UF/16V
8/27 modify
GND
12
NI
NI
VC1
VC1
3.3PF/50V
3.3PF/50V
NPO 0.25PF
NPO 0.25PF
12
NI
NI
VC4
VC4
3.3PF/50V
3.3PF/50V
NPO 0.25PF
NPO 0.25PF
GNDGND
12
NI
NI
VC7
VC7
3.3PF/50V
3.3PF/50V
NPO 0.25PF
NPO 0.25PF
NOTE:
Install the VD1/VD2/VD3/VD4/VD5 diode to prevent from ESD issue
VP
VP
VL2
VL2
1 2
0
0
mx_r0603
mx_r0603
VP
VP
VL4
VL4
1 2
0
0
mx_r0603
mx_r0603
VP
VP
VL6
VL6
1 2
0
0
mx_r0603
mx_r0603
within 500 mils of the VGA connector
GND GND
VR60
VR60
NOBOM
1 2
1 2
NI
NI
VU1
VU1
74AHCT1G125
74AHCT1G125
1
OE#
GND
GND
DDCA_CLK_G DDCA_DATA_G
I
I
1
1
VQ1
VQ1
G
G
2N7002
2N7002
3
3
D
D
2
A
3
GND
NI
NI
VU2
VU2
74AHCT1G125
74AHCT1G125
1
OE#
2
A
3
GND
VGA_HSYNC[13]
B B
VGA_VSYNC[13]
A A
2
2
S
DDCA_DATA[13]
2
2
S
DDCA_CLK[13]
5
S
S
I
I
1
1
VQ2
VQ2
G
G
2N7002
2N7002
3
3
D
D
NOBOM
VR70
VR70
NOBOM
NOBOM
+5V
5
Vcc
4
Y
5
Vcc
4
Y
5%I VRN1A
5%I
1 2
5%I VRN1B
5%I
3 4
5%I VRN1C
5%I
5 6
5%I VRN1D
5%I
7 8
modify 6/20
2.2kOhm
2.2kOhm
2.2kOhm
2.2kOhm
2.2kOhm
2.2kOhm
2.2kOhm
2.2kOhm
4
12
I
I
VCB2
VCB2
0.1UF/16V
0.1UF/16V
8/27 modify
GND
VRN1A VRN1B VRN1C VRN1D
VHSYNC_OBVHSYNC_OB
VVSYNC_OB
+5V_DAC_CLAMP
I
I
VL3
RA
GA
VL3
21
0.068UH/300mA
0.068UH/300mA
12
mx_l0603
mx_l0603
I
I
VC2
VC2
5.6PF/50V
5.6PF/50V
NPO 0.25PF
NPO 0.25PF
GNDGNDGND
I
I
VL5
VL5
21
0.068UH/300mA
0.068UH/300mA
12
mx_l0603
mx_l0603
I
I
VC5
VC5
5.6PF/50V
5.6PF/50V
NPO 0.25PF
NPO 0.25PF
GND GND
I
I
VL7
VL7
BA
12
I
I
VC8
VC8
5.6PF/50V
5.6PF/50V
NPO 0.25PF
NPO 0.25PF
GNDGND
+3P3V
RDDCA_DATA
RDDCA_CLK
21
0.068UH/300mA
0.068UH/300mA
mx_l0603
mx_l0603
NI
NI
VR8
VR8 30
30
1 2
NI
NI
VR9
VR9 30
30
1 2
+5V +5V_VGA
I
I
VD6
VD6 SS14
SS14
1 2
12
I
I
VC3
VC3
3.3PF/50V
3.3PF/50V
NPO 0.25PF
NPO 0.25PF
GND
12
I
I
VC6
VC6
3.3PF/50V
3.3PF/50V
NPO 0.25PF
NPO 0.25PF
12
I
I
VC9
VC9
3.3PF/50V
3.3PF/50V
NPO 0.25PF
NPO 0.25PF
1
RED
GREEN
BLUE
VGADATA
VHSYNC
VVSYNC
VGACLK
2
I
I
VD5
VD5 BAV99W-L
BAV99W-L
3
12
NI
NI
VC12
VC12
3.3PF/50V
3.3PF/50V
NPO 0.25PF
NPO 0.25PF
NI
NI
VL8
VL8 80Ohm/100Mhz/2A
80Ohm/100Mhz/2A
mx_l0805
mx_l0805
+5V_VGA_CONN
21
6/21 modify
GND
12
GND
NI
NI
VC13
VC13 470PF/50V
470PF/50V
X7R 10%
X7R 10%
GND
12
NI
NI
VCB3
VCB3
0.1UF/16V
0.1UF/16V
6/21 modify
GND
I
I
J69
J69
DDC_CONN_15P3R
DDC_CONN_15P3R
SIDE_G16
SIDE_G16
GND2
GND2
6
RED
RED
1
NC2
NC2
11
GND3
GND3
7
GREEN
GREEN
2
DATA
DATA
12
GND4
GND4
8
BLUE
BLUE
3
HSYNC
HSYNC
13
VCC
VCC
9
NC1
NC1
4
VSYNC
VSYNC
14
GND5
GND5
10
GND1
GND1
5
DCLK
DCLK
15
SIDE_G17
SIDE_G17
16
17
1
2
I
I
VD4
VD4 BAV99W-L
BAV99W-L
3
I
I
VR3
VR3 100
100
1 2
1 2
I
I
VR5
VR5 100
100
12
12
I
I
I
I
VR19
VR19
VR18
VR18
2.2K
2.2K
2.2K
2.2K
NI
NI
VF1
VF1
1.1A/6V
1.1A/6V
1 2
6/21 modify
12
I
I
VC10
VC10 470PF/50V
470PF/50V
X7R 10%
X7R 10%
12
NI
NI
VC11
VC11
3.3PF/50V
3.3PF/50V
NPO 0.25PF
NPO 0.25PF
GNDGND GND
+5V_VGA_L
PEGATRON DT-MB RESTRICTED SECRET
VGA PORT
VGA PORT
1
VGA PORT
York Chang
York Chang
York Chang
26 55Thursday, July 09, 2009
26 55Thursday, July 09, 2009
26 55Thursday, July 09, 2009
Rev
Rev
Rev
1.00G
1.00G
1.00G
Title :
Title :
Title :
Engineer:
Engineer:
Pegatron Corp.
Pegatron Corp.
Pegatron Corp.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
Engineer:
IPM41-D3
IPM41-D3
IPM41-D3
5
D D
TC1 0.01UF/25V X7R 10%
TC1 0.01UF/25V X7R 10%
I
I
SATA_TXP0[20]
SATA_TXN0[20]
SATA_RXN0[20]
SATA_RXP0[20]
C C
SATA_TXP2[20]
SATA_TXN2[20]
SATA_RXN2[20] SATA_RXN3[20]
SATA_RXP2[20] SATA_RXP3[20]
1 2
TC2 0.01UF/25V X7R 10%
TC2 0.01UF/25V X7R 10%
I
I
1 2
TC3 0.01UF/25V X7R 10%
TC3 0.01UF/25V X7R 10%
I
I
1 2
TC4 0.01UF/25V X7R 10%
TC4 0.01UF/25V X7R 10%
I
I
1 2
TC9 0.01UF/25V X7R 10%
TC9 0.01UF/25V X7R 10%
I
I
1 2
TC10 0.01UF/2 5V X7R 10%
TC10 0.01UF/2 5V X7R 10%
I
I
1 2
TC11 0.01UF/2 5V X7R 10%
TC11 0.01UF/2 5V X7R 10%
I
I
1 2
TC12 0.01UF/2 5V X7R 10%
TC12 0.01UF/2 5V X7R 10%
I
I
1 2
SATA_TXP0_C SATA_TXN0_C
SATA_RXN0_C SATA_RXP0_C
SATA_TXP4_C SATA_TXN4_C
SATA_RXN4_C SATA_RXP4_C
4
I
I
P60
P60
SATA_CON_7P
SATA_CON_7P
1
1
2
2
3
3
4
4
5
5
6
6
7
7
7/15 modify 12X702200Y00
I
I
P62
P62
SATA_CON_7P
SATA_CON_7P
1
1
2
2
3
3
4
4
5
5
6
6
7
7
P_GND1
P_GND2
P_GND1
P_GND2
8
9
8
9
3
SATA CONNECTOR FOR BPC
SATA CONNECTOR FOR BPC
SATA CONNECTOR FOR BPCSATA CONNECTOR FOR BPC
SATA_TXP1[20]
SATA_TXN1[20]
SATA_RXN1[20]
SATA_RXP1[20]
SATA_TXP3[20]
SATA_TXN3[20]
COLOR = ORANGE
TC5 0.01UF/25V X7R 10%
TC5 0.01UF/25V X7R 10%
I
I
1 2
TC6 0.01UF/25V X7R 10%
TC6 0.01UF/25V X7R 10%
I
I
1 2
TC7 0.01UF/25V X7R 10%
TC7 0.01UF/25V X7R 10%
I
I
1 2
TC8 0.01UF/25V X7R 10%
TC8 0.01UF/25V X7R 10%
I
I
1 2
TC13 0.01UF/2 5V X7R 10%
TC13 0.01UF/2 5V X7R 10%
I
I
1 2
TC14 0.01UF/2 5V X7R 10%
TC14 0.01UF/2 5V X7R 10%
I
I
1 2
TC15 0.01UF/2 5V X7R 10%
TC15 0.01UF/2 5V X7R 10%
I
I
1 2
TC16 0.01UF/2 5V X7R 10%
TC16 0.01UF/2 5V X7R 10%
I
I
1 2
2
I
I
P61
P61
SATA_CON_7P
SATA_CON_7P
SATA_TXP1_C SATA_TXN1_C
SATA_RXN1_C SATA_RXP1_C
SATA_TXP5_C SATA_TXN5_C
SATA_RXN5_C SATA_RXP5_C
1
1
2
2
3
3
4
4
5
5
6
6
7
7
GNDGND
7/15 modify 12X702200Y00
I
I
P63
P63
SATA_CON_7P
SATA_CON_7P
1
1
2
2
3
3
4
4
5
5
6
6
7
7
P_GND1
P_GND2
P_GND1
P_GND2
8
9
8
9
1
COLOR = ORANGECOLOR = ORANGE
COLOR = ORANGE
GND
7/15 modify 12X702200Y00
+3P3V
B B
ICH_SATALED#[20]
A A
12
I
I
F3R1
F3R1
8.2K
8.2K
1
2
I
I
TD1
TD1 BAT54AW
BAT54AW
3
HD_LED# [44]
GND
7/15 modify 12X702200Y00
ASUS OEM-DT MB RESTRICTED SECRET
SATA2 FOR BPC
SATA2 FOR BPC
SATA2 FOR BPC
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Engineer:
IPM41-D3
IPM41-D3
IPM41-D3
1
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
27 55Thursday, July 09, 2009
27 55Thursday, July 09, 2009
27 55Thursday, July 09, 2009
Rev
Rev
Rev
1.00G
1.00G
1.00G
5
4
3
2
1
-12V
+3P3V +5V
+5V
A_D[31..0] [20,29]
D D
C C
B B
12
+
+
I
I
KCE1
KCE1 820UF/6.3V
820UF/6.3V
CK_33M_SL1[5]
PREQ#0[20]
C/BE3#[20,29]
C/BE2#[20,29]
PIRDY#[20,29]
PDEVSEL#[20,29]
PPLOCK#[20,29] PPERR#[20,29]
PSERR#[20,29]
C/BE1#[20,29]
12
I
I
KCB2
KCB2
0.1UF/16V
0.1UF/16V
I
I
J20
GNDGND
PINTF#[20,29] PINTH#[20,29]
A_D31 A_D29
A_D27 A_D25
A_D23
A_D21 A_D19
A_D17
A_D14
A_D12 A_D10
A_D8 A_D7
A_D5 A_D4 A_D3
A_D1
ACK64#_1
J20
SLOT 120P, PCI
SLOT 120P, PCI
B1
-12V
B2
TCK
B3
GND11
B4
TDO
B5
+5V22
B6
+5V23
B7
INTB
B8
INTD
B9
PRSNT1
B10
RESERVED5
B11
PRSNT2
B12
GND12
B13
GND13
B14
RESERVED6
B15
GND14
B16
CLK
B17
GND15
B18
REQ
B19
+5V8
B20
AD31
B21
AD29
B22
GND16
B23
AD27
B24
AD25
B25
+3.3V7
B26
C/BE3
B27
AD23
B28
GND17
B29
AD21
B30
AD19
B31
+3.3V8
B32
AD17
B33
C/BE2
B34
GND18
B35
IRDY
B36
+3.3V9
B37
DEVSEL
B38
GND19
B39
LOCK
B40
PERR
B41
+3.3V10
B42
SERR
B43
+3.3V11
B44
C/BE1
B45
AD14
B46
GND20
B47
AD12
B48
AD10
B49
GND21
B52
AD8
B53
AD7
B54
+3.3V12
B55
AD5
B56
AD3
B57
GND22
B58
AD1
B59
+5V9
B60
ACK64
B61
+5V10
B62
+5V11
RESERVED1
RESERVED2
RESERVED3
RESERVED4
hold_NC11hold_NC2
2
TRST
+12V
TMS
+5V1 INTA INTC +5V2
+5V3
GND1 GND2
RST
+5V4
GNT
GND3
AD30
+3.3V1
AD28 AD26
GND4
AD24
IDSEL
+3.3V2
AD22 AD20
GND5
AD18 AD16
+3.3V3
FRAME
GND6 TRDY GND7 STOP
+3.3V4
SDONE
SBO
GND8
PAR
AD15
+3.3V5
AD13 AD11
GND9
AD9
C/BE0
+3.3V6
AD6 AD4
GND10
AD2 AD0
+5V5
REQ64
+5V6 +5V7
A1 A2 A3 A4
TDI
A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49
A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62
+3P3V
REQ64#_1
A_D30
A_D28 A_D26
A_D24
A_D22 A_D20
A_D18 A_D16
A_D15
A_D13 A_D11
A_D9
A_D6
A_D2 A_D0
12
I
I
KCB1
KCB1
0.1UF/16V
0.1UF/16V
GND
PCI1_TMS PCI1_TDI
7/8 modify net name 7/8 modify net name
GND
PINTE# [20,29] PINTG# [20,29]
ICH_PCIRST# [20,29]
GNT0# [20]
PPME# [20,29]
PFRAME# [20,29]
PTRDY# [20,29]
PSTOP# [20,29]
SMB_CLK_R [5,9,17,18,21,24,25,29] SMB_DATA_R [5,9,17,18,21,24,25,29]
PPAR [20,29]
C/BE0# [20,29]
12
+
+
I
I
KCE2
KCE2 820UF/6.3V
820UF/6.3V
I
I I
I
KRN1D
KRN1D KRN1C
KRN1C
+5V
A_D19
7 8 5 6
2.7K
2.7K
2.7K
2.7K
+5V
+3P3VSB
12
GND
I
I
KCB5
KCB5
0.1UF/16V
0.1UF/16V
+12V
+5V
GND
A A
+3P3V
KRN3A
KRN3A
I
I
1 2
8.2K
PREQ#0[20] PREQ#1[20,29] PREQ#3[20] PREQ#2[20]
5
I
I I
I I
I
KRN3C
KRN3C KRN3B
KRN3B KRN3D
KRN3D
8.2K
5 6
8.2K
8.2K
3 4
8.2K
8.2K
7 8
8.2K
8.2K
PINTA#[20] PINTC#[20] PINTF#[ 20,29] PINTG#[ 20,29]
PINTB#[20] PINTD#[20] PINTE#[20,29]
4
I
I I
I I
I I
I
I
I I
I I
I I
I
KRN4A
KRN4A KRN4C
KRN4C KRN2A
KRN2A KRN2D
KRN2D
KRN4B
KRN4B KRN4D
KRN4D KRN2C
KRN2C KRN2B
KRN2B
1 2 5 6 1 2 7 8
3 4 7 8 5 6 3 4
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
GND
+3P3V +5V
KRN6A
KRN6A
I
I
1 2
2.7K
PPERR#[20,29] PSERR#[20,29] PPLOCK#[20,29]
PDEVSEL#[20,29]
PIRDY#[20,29] PSTOP#[20,29] PFRAME#[20,29] PTRDY#[20,29]PINTH#[20,29]
3
KRN6B
KRN6B
I
I
KRN6C
KRN6C
I
I
KRN6D
KRN6D
I
I
KRN7A
KRN7A
I
I
KRN7B
KRN7B
I
I
KRN7C
KRN7C
I
I
KRN7D
KRN7D
I
I
2.7K
3 4
2.7K
2.7K
5 6
2.7K
2.7K
7 8
2.7K
2.7K
1 2
2.7K
2.7K
3 4
2.7K
2.7K
5 6
2.7K
2.7K
7 8
2.7K
2.7K
ASUS OEM-DT MB RESTRICTED SECRET
PCI1 SLOT
PCI1 SLOT
PCI1 SLOT
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Engineer:
IPM41-D3
IPM41-D3
IPM41-D3
1
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
28 55Thursday, July 09, 2009
28 55Thursday, July 09, 2009
28 55Thursday, July 09, 2009
Rev
Rev
Rev
1.00G
1.00G
1.00G
5
4
3
2
1
D D
A_D[31..0] [20,28]
12
PINTG#[20,28] PINTE#[20,28]
7/8 modify net name
C C
CK_33M_SL2[5]
PREQ#1[20,28]
C/BE3#[20,28]
C/BE2#[20,28]
PIRDY#[20,28]
PDEVSEL#[20,28]
PPLOCK#[20,28]
B B
PPERR#[20,28]
PSERR#[20,28]
C/BE1#[20,28]
NI
NI
KCB6
KCB6
0.1UF/16V
0.1UF/16V
A_D31 A_D29
A_D27 A_D25
A_D23
A_D21 A_D19
A_D17
A_D14
A_D12 A_D10
A_D8 A_D7
A_D5 A_D3
A_D1
+5V
+3P3V
-12V
I
I
J21
J21
SLOT 120P, PCI
SLOT 120P, PCI
B1 B2 B3 B4 B5 B6 B7 B8
B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49
B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62
-12V TCK GND11 TDO +5V22 +5V23 INTB INTD PRSNT1 RESERVED5 PRSNT2 GND12 GND13 RESERVED6 GND14 CLK GND15 REQ +5V8 AD31 AD29 GND16 AD27 AD25 +3.3V7 C/BE3 AD23 GND17 AD21 AD19 +3.3V8 AD17 C/BE2 GND18 IRDY +3.3V9 DEVSEL GND19 LOCK PERR +3.3V10 SERR +3.3V11 C/BE1 AD14 GND20 AD12 AD10 GND21
AD8 AD7 +3.3V12 AD5 AD3 GND22 AD1 +5V9 ACK64 +5V10 +5V11
RESERVED1
RESERVED2
RESERVED3
RESERVED4
hold_NC11hold_NC2
2
TRST
+12V
TMS
+5V1 INTA INTC +5V2
+5V3
GND1 GND2
RST
+5V4
GNT
GND3
AD30
+3.3V1
AD28 AD26
GND4
AD24
IDSEL
+3.3V2
AD22 AD20
GND5
AD18 AD16
+3.3V3
FRAME
GND6 TRDY GND7 STOP
+3.3V4
SDONE
SBO
GND8
PAR
AD15
+3.3V5
AD13 AD11
GND9
AD9
C/BE0
+3.3V6
AD6 AD4
GND10
AD2 AD0
+5V5
REQ64
+5V6 +5V7
TDI
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49
A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62
+5V
+3P3V
GNDGND
PCI2_TMS PCI2_TDI
7/8 modify net name
A_D30
A_D28 A_D26
A_D24 A_D20
A_D22 A_D20
A_D18 A_D16
A_D15
A_D13 A_D11
A_D9
A_D6 A_D4
A_D2 A_D0
REQ64#_2ACK64#_2
+12V
12
NI
NI
KCB7
KCB7
0.1UF/16V
0.1UF/16V
PINTF# [20,28] PINTH# [20,28]
ICH_PCIRST# [20,28]
GNT1# [20]
PPME# [20,28]
PFRAME# [20,28]
PTRDY# [20,28]
PSTOP# [20,28]
SMB_CLK_R [5,9,17,18,21,24,25,28] SMB_DATA_R [5,9,17,18,21,24,25,28]
PPAR [20,28]
C/BE0# [20,28]
KRN1A
KRN1A
I
I
KRN1B
KRN1B
I
I
+5V
1 2
2.7K
2.7K
3 4
2.7K
2.7K
+5V
+3P3VSB
12
NI
NI
KCB10
KCB10
0.1UF/16V
0.1UF/16V
GND
+5V
GND
A A
GND
ASUS OEM-DT MB RESTRICTED SECRET
PCI2 SLOT
PCI2 SLOT
PCI2 SLOT
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Engineer:
IPM41-D3
IPM41-D3
IPM41-D3
1
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
29 55Thursday, July 09, 2009
29 55Thursday, July 09, 2009
29 55Thursday, July 09, 2009
Rev
Rev
Rev
1.00G
1.00G
1.00G
5
4
3
2
1
D D
DOUBLE STACK PORT CONNECTOR FOR CPC
IIII
IIII
IIII
URN5B
URN5B
3 4
0
0
14
1 2
0
0
IIII
IIII
URN5A
URN5A
IIII
IIII
URN6B
URN6B
3 4
0
0
14
1 2
0
0
IIII
IIII
URN6A
URN6A
23
NI
NI
NI
NI
NINI
NINI
UL5
UL5 90OHM/100MHz/300mA
90OHM/100MHz/300mA
23
NI
NI
NI
NI
NINI
NINI
UL6
UL6 90OHM/100MHz/300mA
90OHM/100MHz/300mA
CH1
CH1
CH2 CH3
CH2 CH3
GND
NI
NI
NI
NI
NINI
NINI
UU3
UU3
CM1213_04SO
CM1213_04SO
1
VN
VN
2
3 4
CH4
CH4
6
VP
VP
5
+5VSB
USBN2[20]
USBP2[2 0]
C C
USBN3[20]
USBP3[2 0]
B B
LP4-
LP4+
LP5-
LP5+
GND GND
IIII
J16
J16
USB_CON_2X4P
USB_CON_2X4P
1P-
VCC1
1P-
VCC1
GND1
GND1
1P+
1P+
3 4
2P-
2P-
VCC2
VCC2
2P+
GND2
2P+
SIDE_G9
SIDE_G9
SIDE_G10
SIDE_G10
GND2
SIDE_G11
SIDE_G11
SIDE_G12
SIDE_G12
7 8
9 11
12
IIII
IIII
UF4
UF4
1.6A/6V
1.6A/6V
+5V_DUAL_USB
12
12
GND
56
12
GND
1210
GND
+SBV45
12
IIII
IIII
UC3
UC3
0.1UF/16V
0.1UF/16V
+
+
I
I
UCE3
UCE3 330UF/6.3V
330UF/6.3V
GND
modify 8/1 470uF/6.3V=11X040477140 change to 330uF/6.3V=11X040337140
IIII
IIII
UF3
UF3
1.6A/6V
1.6A/6V
A A
ASUS OEM-DT MB RESTRICTED SECRET
DOUBLE USB CON.
DOUBLE USB CON.
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
5
4
3
2
Engineer:
IPM41-D3
IPM41-D3
IPM41-D3
DOUBLE USB CON.
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
1
Rev
Rev
Rev
1.00G
1.00G
30 55Thursday, July 09, 2009
30 55Thursday, July 09, 2009
30 55Thursday, July 09, 2009
1.00G
5
4
3
2
1
12
I
I
UCB3
UCB3
0.1UF/16V
0.1UF/16V
12
I
I
UCB4
UCB4
0.1UF/16V
0.1UF/16V
NOTE:
Check USB cable internal whether had capacity NI:BPC I: CPC
12
+
+
I
I
UCE5
UCE5 330UF/6.3V
330UF/6.3V
modify 8/1 470uF/6.3V=11X040477140 change to 330uF/6.3V=11X040337140
GNDGND
NOTE:
Check USB cable internal whether had capacity NI: BPC I: CPC
I
I
UF5
UF5
1.6A/6V
1.6A/6V
12
I
I
UF6
UF6
1.6A/6V
1.6A/6V
12
+5V_DUAL
USBPW
USBPW
1 2
I
I
3
HEADER_1X3P
HEADER_1X3P
Default as short pin 1-2
+5VSB
USBPW5-8: 1-2: +5V_DUAL 2-3: +5VSB
USBPW:12
USBPW:12
MINI_JUMPER
MINI_JUMPER
I
I
USB_F
+SBV89 USB_F
D D
I
I
URN9B
URN9B
3 4
0
0
USBN4[20]
USBP4[2 0]
C C
USBN5[20]
USBP5[2 0]
USBN6[20]
B B
USBP6[2 0]
USBN7[20]
USBP7[2 0]
A A
14
1 2
0
0
I
I
URN9A
URN9A
I
I
URN10B
URN10B
3 4
0
0
14
1 2
0
0
I
I
URN10A
URN10A
IIII
IIII
URN11B
URN11B
3 4
0
0
14
1 2
0
0
IIII
IIII
URN11A
URN11A
IIII
IIII
URN12B
URN12B
3 4
0
0
14
1 2
0
0
IIII
IIII
URN12A
URN12A
23
NI
NI
UL9
UL9 90OHM/100MHz/300mA
90OHM/100MHz/300mA
23
NI
NI
UL10
UL10 90OHM/100MHz/300mA
90OHM/100MHz/300mA
23
NI
NI
NI
NI
NINI
NINI
UL11
UL11 90OHM/100MHz/300mA
90OHM/100MHz/300mA
23
NI
NI
NI
NI
NINI
NINI
UL12
UL12 90OHM/100MHz/300mA
90OHM/100MHz/300mA
GND
GND
NI
NI
NI
NI
NINI
NINI
UU5
UU5
CM1213_04SO
CM1213_04SO
CH1
CH1
1
VN
VN
2
CH2 CH3
CH2 CH3
3 4
CH1
CH1
1
VN
VN
2
CH2 CH3
CH2 CH3
3 4
NI
NI
NI
NI
NINI
NINI
UU6
UU6
CM1213_04SO
CM1213_04SO
CH4
CH4
6
5
CH4
CH4
6
5
+5VSB
VP
VP
+5VSB
VP
VP
LP8­LP8+
LP10-
I
I
P154
P154
HEADER_2X5P_K9
HEADER_2X5P_K9
1
2 3 4 5 6 7 8
10
GND GND
12X602025Y92 (15U)
I
I
P153
P153
HEADER_2X5P_K9
HEADER_2X5P_K9
1
2 3 4 5 6 7 8
10
GNDGND
12X602025Y92 (15U)
LP9­LP9+
LP11­LP11+LP10+
+SBV89
GND
ASUS OEM-DT MB RESTRICTED SECRET
USB HEADER CON.
USB HEADER CON.
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
5
4
3
2
Engineer:
IPM41-D3
IPM41-D3
IPM41-D3
USB HEADER CON.
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
1
Rev
Rev
Rev
1.00G
1.00G
31 55Thursday, July 09, 2009
31 55Thursday, July 09, 2009
31 55Thursday, July 09, 2009
1.00G
5
+3P3VSB+1P2V_VDD
RTL8111DL Switching regulator
PIN
PIN NAME
48
REG_OUT
4
FB12
43
44,45
ENSWREG
VDDREG
8103EL Pin
DVDD3.3V
AVDD3.3V
DVDD1.2V
+1.2V_OUT
D D
C C
B B
A A
I/O
O
I
I
P
29,37
1
10,13,30,36
19,45,48
Function
Regulator output
Feedback pin
3.3V : Enable ; 0V : disable
3.3V power pin
Layout Guide: +1P2V_OUT & +1P2OUT wider than 60mil LL1&LR18 place near 200mil to LAN LCB6&LCB7 place near 300mil to LAN
8111DL Pin
DVDD3.3V
AVDD3.3V
DVDD1.2V
AVDD1.2V
5
29,37
1,40
13,36
10,30,39
19EVDD1.2V
48+1.0V_OUT
+1P2V_OUT
CK_25M_LAN[5]
Layout Guide: +3P3VSB wider than 40mil LC2~LC5 place near 200mil to LAN
0
0
I
I
1 2
LR4
LR4
/8103_NI
/8103_NI
0
0
I
I
1 2
LR6
LR6
/8103_NI
/8103_NI
LJP1
1 2
SHORTPIN
SHORTPIN
+3P3V
12
I
I
LR8
LR8 1K
1K
12
I
I
LR10
LR10 15K
15K
GND GND GND
4
LR1 0
I /8103_NI
I /8103_NI
1 2
LR2 0
NI /8103_I
NI /8103_I
1 2
+3P3VSB
+1P2V_VDD
I
I
12
LCB8
LCB8
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND GND GND GND GND
NOBOMLJP1
NOBOM
LAN_RXN[20] LAN_RXP[20]
LAN_TXN[20] LAN_TXP[ 20]
CK_100M_LAN[5] CK_100M_LAN#[5]
WAKE#[21,24,25]
PCIES_RST#[24,25,38]
VP
VP
LR13
LR13 0
0
1 2
4
mx_r0603LR1 0
mx_r0603 mx_r0603LR2 0
mx_r0603
12
I
I
LCB2
LCB2
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND GND GND GND
I
I
12
LCB6
LCB6 22UF/6.3V
22UF/6.3V
X5R 10%
X5R 10% mx_c1206
mx_c1206
/8103_NI
/8103_NI
GND GND
I
I
12
LCB9
LCB9
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
12
GND GND GND
12
I
I
LCB3
LCB3
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
I
I
12
LCB7
LCB7
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
I
I
12
LCB10
LCB10
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
LC2 0.1UF/16V X7R 10%
LC2 0.1UF/16V X7R 10%
I
I
1 2
LC1 0.1UF/16V X7R 10%
LC1 0.1UF/16V X7R 10%
I
I
1 2
12
NI
NI
LC3
LC3 10PF/50V
10PF/50V
NPO 5%
NPO 5%
NOBOM
NOBOM
1 2
LR14 0 Ohm
LR14 0 Ohm
NI
NI
LC4
LC4 30PF/50V
30PF/50V
NPO 5%
NPO 5%
12
GND GND
12
12
12
GND GND
12
NI
NI
Y10
Y10
1 2
1 2
Y10 LAN__XOUT
GND
GND
3
3
+SWREG/+1P2VOUT
I
I
LCB17
LCB17 22UF/6.3V
22UF/6.3V
X5R 10%
X5R 10% mx_c1206
mx_c1206
/8103_NI
/8103_NI
I
I
LCB4
LCB4
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
LL1
LL1
/8103NI
/8103NI
4.7UH/1.7A
4.7UH/1.7A
I
I
0
0
1 2
LR18
LR18
NI
NI
/8103_I
/8103_I
I
I
LCB11
LCB11
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
I
I
LCB18
LCB18 1UF/16V
1UF/16V
X7R 10%
X7R 10% mx_c0603
mx_c0603
I
I
LR12
LR12
2.49K
2.49K
1%
1%
25Mhz
25Mhz
12
I
I
LCB1
LCB1
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
12
I
I
LCB5
LCB5
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
+1P2OUT
21
I
I
12
LCB12
LCB12
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
+1P2V_EVDD
I
I
12
LCB13
LCB13 1UF/16V
1UF/16V
X7R 10%
X7R 10% mx_c0603
mx_c0603
FB12
LAN_RXN_C LAN_RXP_C
LAN_ISOLATEB
LANRSET
LAN_XIN
NI
NI
12
LC5
LC5
33PF/50V
33PF/50V
NPO 5%
NPO 5%
3
3
I
I
LU2
LU2
44
VDDSR2
45
VDDSR1
29
VDD33_1
37
VDD33_2
1
AVDD33_1
40
AVDD33_2
48
SROUT12
13
DVDD12_1
36
DVDD12_2
30
DVDD12_3
10
AVDD12_1
39
AVDD12_2
19
EVDD12
4
FB12
21
HSON
20
HSOP
16
HSIN
15
HSIP
17
REFCLK_P
18
REFCLK_N
28
ISOLATEB
26
LANWAKEB
27
PERSTB
46
RSET
41
CKTAL1
42
CKTAL2
RTL8111DL_GR
RTL8111DL_GR
MDIN0 MDIP0
MDIN1 MDIP1
MDIN2 MDIP2
MDIN3 MDIP3
EECS
LED0
LED1/EESK
LED2/EEDI/AUX
LED3/EEDO
CLKREQB
ENSR
NC1 NC2
EGND
GND2 GND1 GND3 GND4
3 2
6 5
9 8
12 11
32 38 35 34 33
25
43
23 24
22
7 14 31 47
LAN_EECS
LAN_EEDI LAN_EEDO
O/D
ENSWREG
GND
2
1 2
GND
+3P3VSB
12
12
GND
2
+3P3VSB
NI
NI
LR7
LR7 10KOhm
10KOhm
/8103_I
/8103_I
I
I
LR9
LR9 0
0
/8103_NI
/8103_NI
NI
NI
LR11
LR11 0
0
+3P3VSB
12
NI
NI
LR24
LR24
4.7K
4.7K
REALTEK_ACTLED# [33] REALTEK_LINK100# [33]
REALTEK_LINK1G# [33]
12
I
I
LR5
LR5
3.6K
3.6K
NI
NI
LU5
LU5
EEPROM 1Kb 93C46
EEPROM 1Kb 93C46
1
CS
VCC
2
SK
NC
3
DI
ORG
DO4GND
NOTE:
If using eFuse funtion, NI LU2 directly
NOTE: LED MODE
(LEDS1, LEDS0) = (1, 1) DEFAULT (LEDS1, LEDS0) = (0, 1) ==> For this schematic
NOTE: 8111DL[PIN43]
3.3V enable internal regulator 0V disable internal regulator
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
8 7 6 5
LAN_MDI0_N [33] LAN_MDI0_P [33]
LAN_MDI1_N [33] LAN_MDI1_P [33]
LAN_MDI2_N [33] LAN_MDI2_P [33]
LAN_MDI3_N [33] LAN_MDI3_P [33]
+3P3VSB
12
NI
NI
LCB14
LCB14
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND GND
IPM41-D3
IPM41-D3
IPM41-D3
1
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
1
8111DL co-lay 8102EL
8111DL co-lay 8102EL
8111DL co-lay 8102EL
York Chang
York Chang
York Chang
32 55Thursday, July 09, 2009
32 55Thursday, July 09, 2009
32 55Thursday, July 09, 2009
1.00
1.00
1.00
Rev
Rev
Rev
5
IIII
IIII
UU7
UU7
CM1213_04SO
CM1213_04SO
CH1
LAN_MDI1_P
LAN_MDI0_P
GND
D D
LAN_MDI3_P
LAN_MDI2_P
GND
10/2 modify 10/3 modify
C C
B B
A A
LAN_MDI0_P[32]
LAN_MDI0_N[32]
LAN_MDI1_P[32]
LAN_MDI1_N[32]
LAN_MDI2_P[32]
LAN_MDI2_N[32]
LAN_MDI3_P[32]
LAN_MDI3_N[32]
USBN0[20]
USBP0[2 0]
USBN1[20]
USBP1[2 0]
CH1
1
VN
VN
2
CH2 CH3
CH2 CH3
3 4
CH1
CH1
1
VN
VN
2
CH2 CH3
CH2 CH3
3 4
IIII
IIII
UU8
UU8
CM1213_04SO
CM1213_04SO
IIII
IIII
URN16A
URN16A
1 2
0
0
1 4
3 4
0
0
IIII
IIII
URN16B
URN16B
IIII
IIII
URN17A
URN17A
1 2
0
0
1 4
3 4
0
0
IIII
IIII
URN17B
URN17B
CH4
CH4
LAN_MDI1_N
6
VP
VP
5
LAN_MDI0_NLAN_MDI0_N
CH4
CH4
LAN_MDI3_N
6
VP
VP
5
LAN_MDI2_N
90OHM/100MHz/300mA
90OHM/100MHz/300mA UL7
UL7
NI
NI
NI
NI
NINI
NINI
2 3
NI
NI
NI
NI
NINI
NINI
90OHM/100MHz/300mA
90OHM/100MHz/300mA UL8
UL8
2 3
+5VSB
12
GND
+5VSB
12
GND
I
I
LCB25
LCB25
0.1UF/16V
0.1UF/16V
I
I
LCB26
LCB26
0.1UF/16V
0.1UF/16V
GND
4
09/11 modify
+3P3VSB
12
I
I
LR20
LR20 200
200
mx_r0603
mx_r0603
ICH_ACT_CTRL
REALTEK_ACTLED#[32] REALTEK_LINK100# [32]
NI
NI
NI
NI
NINI
NINI
UU4
UU4
CM1213_04SO
CM1213_04SO
CH1
CH1
1
VN
VN
2
CH2 CH3
CH2 CH3
3 4
CH4
CH4
6
5
VP
VP
+5VSB
LAN + Dual USB CONNECTOR
12
I
I
LC15
LC15 1000PF/50V
1000PF/50V
X7R 10%
X7R 10%
GND
12
I
I
LC12
LC12 1000PF/50V
1000PF/50V
X7R 10%
X7R 10%
GND
8/19 modify
LP0-
LP0+
LP1-
LP1+
19
20
10
11
12
13
14
15
16
17
3
12G14203322X giga LAN connector
/Change to 12XA070YG040 for 10/100
/Change to 12XA070YG040 for 10/100 I
I
J9
J9
JACK_USB/LAN_GIGA
JACK_USB/LAN_GIGA
LILEDP
G
G
LILEDN
VCC_CTR
GND_CTR
VCC1
GND1
VCC2
GND2
21
22
9
18
30 29 26 25
5
8
1
4
28 27 24 23
6
7
2
3
ACTLEDP
Y
Y
ACTLEDN
TD1+
TD1-
TD2+
TD2-
TD3+
TD3-
TD4+
TD4-
1P-
1P+
2P-
2P+
LANGND30 LANGND29 LANGND26 LANGND25
USBGND28 USBGND27 USBGND24 USBGND23
LINKLED#_Q
8/19 modify
VCC_CTR
GND_CTR
GND
GND
12
I
I
LC11
LC11 1000PF/50V
1000PF/50V
X7R 10%
X7R 10%
GND
12
I
I
LC16
LC16 1000PF/50V
1000PF/50V
X7R 10%
X7R 10%
GND
12
I
I
LR22
LR22 0
0
/8102E_NI
/8102E_NI
GND GND
+SBV45
GND
+SBV45
GND
2
REALTEK_LINK1G# [32]
8/19 modify8/19 modify
12
NI
NI
LCB22
LCB22
0.01UF/25V
GND
0.01UF/25V
X7R 10%
X7R 10%
/8102E_I
/8102E_I
I
I
12
LCB23
LCB23
0.1UF/16V
0.1UF/16V
/8102E_I
/8102E_I
8/29 modify
1
ASUS OEM-DT MB RESTRICTED SECRET
RJ45+USB CONN.
RJ45+USB CONN.
RJ45+USB CONN.
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Engineer:
IPM41-D3
IPM41-D3
IPM41-D3
1
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
33 55Thursday, July 09, 2009
33 55Thursday, July 09, 2009
33 55Thursday, July 09, 2009
Rev
Rev
Rev
1.00G
1.00G
1.00G
5
ALC888S-VC2ALC888S-B1
DVSSPin 4 GPIO1/DMIC-DATA
D D
Please noite: AZ_BITCLK need add a serial res(22 ohm) near SB side
S
S
D
D
3
3
2
2
12
+
+
I
I
AQ3
AQ3 AP2306GN
AP2306GN
1
1
G
G
NI
NI
ACE11
ACE11 100uF/16V
100uF/16V
1 2
AZ_SDATA_IN0[21]
AZ_SDATA_OUT[21]
AZ_SYNC[21] AZ_RST#[21] AZ_BITCLK[21]
C C
+5VSB
I
I
+12V
1 2
B B
Digital Region
Digital Region
Digital RegionDigital Region
A A
AR7
AR7 100K
100K
5%
5%
+12V
GND
I
I
12
ACB7
ACB7 10UF/16V
10UF/16V
X5R 10%
X5R 10% mx_c0805
mx_c0805
NTR4502PT1G
NTR4502PT1G
AZ_AVDD_GATEAZ_AVDD_GATE
AC26
AC26
0.22UF/16V
0.22UF/16V
X7R 10%
X7R 10%
mx_c0603
mx_c0603
Provision AR23 for ALC888S-VC codec
NI
1 2
I
I
AQ1
AQ1
S
S
2
2
1
1
12
I
I
AU2
AU2
Vin
GND4
GND3
NC2
78L05
78L05
1M
1M
1 2
AR10
AR10
I
I
12
Vout
GND1
GND2
NC1
I
I
8
7
6
5
G
G
I
I
AR8
AR8 100K
100K
5%
5%
D
D
3
3
AR370NIAR370
12
AGNDGNDGND
+5VA_AZ
1
2
3
4
NI
NI
AC47
AC47 100PF/50V
100PF/50V
1 2
I
I
AR69
AR69 0
0
1 2
The Gate Pin of AQ3 should be placed in degital area for better Audio Quality
NI
NI
ACB3
ACB3 10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10% mx_c0805
mx_c0805
GNDAGND
PLACE NEAR front audio CODEC FOR EMI
5
+3P3VSB +3P3V
AR26
AR26 0 Ohm
0 Ohm
NI/VIA I
NI/VIA I
I
I
AR1
AR1 33
33
12
AQ3_G
12
GNDAGNDAGNDAGND
4
12
12
AR25
AR25 0 Ohm
0 Ohm
I/VIA NI
I/VIA NI
12
NI/VIA I
NI/VIA I
ACB1
ACB1 10UF/10V
10UF/10V
Y5V +80-20%
Y5V +80-20%
GND GND
12
NI
NI
AC3
AC3 10PF/50V
10PF/50V
NPO 5%
NPO 5%
GND GND
12
I
I
+
+
ACE10
ACE10 100uF/16V
100uF/16V
I
I
AC2
AC2
0.1UF/16V
0.1UF/16V
Change ACE864/ACE865/AC6 to 4.7uF/X5R/0805/10V because CD-IN are dedicated Input port , and for better noise immunity
4
C.S ALC662-GR LQFP-4802G611003200 C.S ALC888S-GR(B1) LQFP-4802G611003510 C.S ALC888S-VC2-GR LQFP-4802G611003521
12
I
I
ACB2
ACB2
0.1UF/16V
0.1UF/16V
Y5V +80-20%
Y5V +80-20%
RSDATA_IN0
12
NI
NI
AC4
AC4 22PF/50V
22PF/50V
NPO 5%
NPO 5%
12
I
I
I
ACB4
ACB4
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
I
ACB5
ACB5
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
SPDIF_OUT[36]
12
+5VA
AGNDAGNDAGNDAGND
AR24
AR24 0 Ohm
0 Ohm
I
I
GNDGND
I
I
1 9
4 7
8
5 10 11
6
12
2
3
25 38
26 42
20
18
19
47
48
ALC888S_GR
ALC888S_GR
3
AU22
AU22
DVDD1 DVDD2
DVSS1 DVSS2
SDATA_IN SDATA_OUT SYNC RESET# BIT_CLK
PCBEEP
ALC888S Rev. A
GPIO0/DMIC-CLK/SPDIFO2 GPIO1/DMIC-DATA
AVDD1 AVDD2
AVSS1 AVSS2
CD_R
CD_L
CD_GND
SIDESURR_OUT_R
SIDESURR_OUT_L
SPDIFI/EAPD
SPDIFO
3
LINE1_R
LINE1_L
FRONT_OUT_R
FRONT_OUT_L
MIC1_R
MIC1_L
SENSE_A
LINE2_R
LINE2_L
MIC2_R
MIC2_L
SENSE_B
AGPIO
MIC1_VREFO_R
MIC1_VREFO_L
PIN37_VREFO
LINE1_VREFO
MIC2_VREFO
LINE2_VREFO
VREF
LFE_OUT
CEN_OUT
SURR_OUT_R
SURR_OUT_L
JDREF
2
If pin 23/24 and pin 21/22 support retasking function, please changed AR34/AR35/AR30/AR31 to 75 ohm
1 2
I_SURB_R_C
I_SURB_L_C
I_LEF_C
I_CEN_C
I_SUR_R_C
I_SUR_L_C
I_F_LIN1_RC
I_F_LIN1_LC
I_FRONT_R_C
I_FRONT_L_C
I_MIC1_R_C
I_MIC1_L_C
R_LIN2_RC
R_LIN2_LC
I_MIC2_R_C
I_MIC2_L_C
AR7039.2K 1%
AR7039.2K 1%
888S(B1) 0 ohm
888S(B1) 0 ohm
PEGATRON DT-MB RESTRICTED SECRET
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
F_LIN1_RC
24
F_LIN1_LC
23
FRONT_RC
36
FRONT_LC
35
MIC1_RC
22
MIC1_LC
21
13
LIN2_RC
15
LIN2_LC
14
MIC2_RC
17
MIC2_LC
16
34
NI/VIA I
NI/VIA I
NI/VIA I
NI/VIA I
R_CD_IN_JD
33
32
28
If front Microphone is not support retasking function,
37
1.ACE8/ACE9 can be changed to SMD 4.7uF(11X234475150)
29
2.please change AR4/AR6 to 1K for better ESD immunity
30
31
ALC_VREF
27
SURB_RC
46
SURB_LC
45
LEFC
44
CENC
43
SUR_RC
41
SUR_LC
39
AUD_JD_REF
40
12
AGND
AC17 4.7UF/6.3 V X5R 10%
AC17 4.7UF/6.3 V X5R 10%
I
I
1 2
AC16 4.7UF/6.3 V X5R 10%
AC16 4.7UF/6.3 V X5R 10%
I
I
1 2
ACE4 10UF/25V
ACE4 10UF/25V
I
I
1 2
+
+
ACE5 10UF/25V
ACE5 10UF/25V
I
I
1 2
+
+
AC19 4.7UF/6.3 V X5R 10%
AC19 4.7UF/6.3 V X5R 10%
I
I
1 2
AC18 4.7UF/6.3 V X5R 10%
AC18 4.7UF/6.3 V X5R 10%
I
I
1 2
ACE6 100uF/16V
ACE6 100uF/16V
I
I
1 2
ACE7 100uF/16V
ACE7 100uF/16V
I
I
1 2
ACE8 100uF/16V
ACE8 100uF/16V
I
I
1 2
ACE9 100uF/16V
ACE9 100uF/16V
I
I
1 2
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
NI/ VIA I
NI/ VIA I
AC36
AC36 220PF/50V
220PF/50V
X7R 10%
X7R 10%
1 2
1 2
12
I
I
ACB6
ACB6 10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10%
AGND
ACE868 10UF/25V
ACE868 10UF/25V
I
I
1 2
ACE869 10UF/25V
ACE869 10UF/25V
I
I
1 2
ACE870 10UF/25V
ACE870 10UF/25V
I
I
1 2
ACE871 10UF/25V
ACE871 10UF/25V
I
I
1 2
ACE872 10UF/25V
ACE872 10UF/25V
I
I
1 2
ACE873 10UF/25V
ACE873 10UF/25V
I
I
1 2
12
I /VIA 5.1K I
I /VIA 5.1K I
AR11
AR11 20KOhm
20KOhm
1%
1%
AGND
mx_c0805
mx_c0805
mx_c0805
mx_c0805
mx_c0805
mx_c0805
mx_c0805
mx_c0805
+
+
+
+
+
+
+
+
ACB9
ACB9
AGND
ACB8
ACB8
AGND
I
I
Pin33 : rear side detected function as line-in used AR70 : for ALC888S-B1use 0 ohm for ALC888S-VC2use 39.2K ohm
+
+
+
+
+
+
+
+
+
+
+
+
2
AR34 1K
AR34 1K
I
I
1 2
AR35 1K
AR35 1K
I
I
1 2
AR15 75
AR15 75
I
I
1 2
AR32 75
AR32 75
I
I
1 2
AR30 1K
AR30 1K
I
I
1 2
1 2
AR31 1K
AR31 1K
I
I
AR2 75
AR2 75
I
I
1 2
1 2
AR5 75
AR5 75
I
I
AR4 75
AR4 75
I
I
1 2
1 2
AR6 75
AR6 75
I
I
ALC662 NI ALC888 I
ALC662 NI ALC888 I
AR27 75
AR27 75
I
I
1 2
AR38 75
AR38 75
I
I
1 2
AR36 75
AR36 75
I
I
1 2
AR28 75
AR28 75
I
I
1 2
AR33 75
AR33 75
I
I
1 2
AR29 75
AR29 75
I
I
1 2
IPM41-D3
IPM41-D3
IPM41-D3
1
LIN1_R_C [35]
LIN1_L_C [35]
FRONT_R_C [35]
FRONT_L_C [35]
MIC1_R_C [35]
MIC1_L_C [35]
SENSE_A [35]
LIN2_R_C [36]
LIN2_L_C [36]
MIC2_R_C [36]
MIC2_L_C [36]
SENSE_B [35,36 ]
LIN1_JD [35]
MIC1_VREF_R [35]
MIC1_VREF_L [35]
MIC2_VREF [36]
LIN2_VREF [36]
SURB_R_C [35]
SURB_L_C [35]
LEF_C [35]
CEN_C [35]
SUR_R_C [35]
SUR_L_C [35]
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
1
ALC888S AUDIO CODEC
ALC888S AUDIO CODEC
ALC888S AUDIO CODEC
XXXXX_XX
XXXXX_XX
XXXXX_XX
34 55Thursday, July 09, 2009
34 55Thursday, July 09, 2009
34 55Thursday, July 09, 2009
1.00
1.00
1.00
Rev
Rev
Rev
5
MIC1_VREF_R[34]
MIC1_VREF_L[34]
I
I
AR13
AR13
4.7K
4.7K
AL87/AL89/AL91/AL93/AL95/AL97;Please use 09X131216000 instead of 0 ohm if you found have
12
12
I
I
AR12
AR12
4.7K
4.7K
EMI issue
Note: AR61&AR63 Place near to codec
AL87 0
AL87 0
VP
VP
D D
C C
LIN1_L_C[34] LIN1_JD[34]
LIN1_R_C[34]
FRONT_L_C[34] SENSE_A[34]
FRONT_R_C[34]
MIC1_L_C[34]
MIC1_R_C[34]
1 2
AL89 0
AL89 0
VP
VP
1 2
AL91 0
AL91 0
VP
VP
1 2
AL93 0
AL93 0
VP
VP
1 2
AL95 0
AL95 0
VP
VP
1 2
AL97 0
AL97 0
VP
VP
1 2
ALC888S_NI
ALC888S_NI
I
I
1 2
for avoid JD malfunction
AR615.1K 1%
I
I
1 2
I
I
1 2
AR6610KOh m 1%
AR6610KOh m 1%
AR615.1K 1%
AR6320K 1%
AR6320K 1%
I
I
I
I
AC21
AC21
AC28
12
AGND AGND AGND AGND AGND AGND
AC28
12
100PF/50V
NPO 5%
100PF/50V
NPO 5%
100PF/50V
NPO 5%
100PF/50V
NPO 5%
LIN1_JD
4
3
2
1
AL88/AL90/AL92/AL94/AL96/AL98;Please use
Azalia Rear Audio Connector
I
I
J86
J86
AUDIO_6IN1_AZA_26P
AUDIO_6IN1_AZA_26P
L
LIN1_L
LIN1_R LEF
FRONT_JD
FRONT_R
MIC1_L
MIC1_JD
MIC1_R
I
I
I
I
I
I
AC22
AC22
AC20
AC20
12
100PF/50V
NPO 5%
100PF/50V
NPO 5%
12
12
100PF/50V
NPO 5%
100PF/50V
NPO 5%
AC24
AC24
I
I
AC25
AC25
12
100PF/50V
NPO 5%
100PF/50V
NPO 5%
AUD_GND
100PF/50V
NPO 5%
100PF/50V
NPO 5%
JP19
JP19 SHORTPIN
SHORTPIN
NOBOM
NOBOM
1 2
AGND AGND
L
10 11
PORT3
PORT3
12
R
R
13
L
L
6 7 8
PORT2
PORT2
R
R
9
L
L
2 3 4
PORT1
PORT1
5
R
R
1
31
NC1
NC1
32
NC2
NC2
33
GND1
GND1
34
GND2
GND2
B O
B O
L
L
P
P
L
L
CEN
23
CEN_JD
24
PORT6
PORT6
25
R
R
26
L
L
SUR_LFRONT_L
19
SUR_JD
PORT5
PORT5
PORT4
PORT4
GND3
GND3 GND4
GND4 GND5
GND5 GND6
GND6
20 21
R
R
SUR_R
22
L
L
SURB_L
15
SURB_JD
16 17
SURB_R
18
R
R
14
27 28 29 30
I
I
AC27
AC27
12
AGND AGND AGND AGND AGND AGND AGND
I
I
AC29
AC29
12
100PF/50V
NPO 5%
100PF/50V
100PF/50V
NPO 5%
100PF/50V
NPO 5%
NPO 5%
B
B
G
G
09X131216000 instead of 0 ohm if you found have EMI issue
AL88 0
AL88 0
I
I
AL90 0
AL90 0
I
I
AL92 0
AL92 0
I
I
AL94 0
AL94 0
I
I
AL96 0
AL96 0
I
I
AL98 0
AL98 0
I
I
1 2
1 2
1 2
1 2
1 2
1 2
I
I
1 2
I
I
1 2
I
I
1 2
Note:
I
I
I
AC32
AC32
12
I
AC30
AC30
12
100PF/50V
NPO 5%
100PF/50V
NPO 5%
I
I
I
I
AC31
AC31
AC33
12
100PF/50V
NPO 5%
100PF/50V
NPO 5%
AC33
12
100PF/50V
NPO 5%
100PF/50V
NPO 5%
100PF/50V
100PF/50V
AR60&AR62&AR64 Place near to codec for avoid JD malfunction
NPO 5%
NPO 5%
ALC662 NI ALC888 I
AR6010K 1%
AR6010K 1%
AR6239.2 K 1%
AR6239.2 K 1%
AR645.1K 1%
AR645.1K 1%
CEN_C [34]
LEF_C [34]
SUR_L_C [34] SENSE_A [34]
SUR_R_C [34]
SURB_L_C [34] SENSE_B [34,36]
SURB_R_C [34]
Azalia Rear Audio Connector
Note: Rear Side Audio Header Just Only Function Dedicated
ALC888S_NI
ALC888S_NI
NI
NI
J83
J83
AUDIO_3IN1_AZA_13P
AUDIO_3IN1_AZA_13P
L
LIN1_L LIN1_JD
B B
LIN1_R
FRONT_L FRONT_JD
FRONT_R
MIC1_L MIC1_JD
MIC1_R
AR24&AR25&AR26 Place near to codec
NI
NI
AC34
AC34 100PF/50V
100PF/50V
NPO 5%
NPO 5%
1 2
I
I
AR65
A A
AR65 0
0
1 2
AGND GND
PLACE NEAR AUDIO Connector FOR EMI
5
4
3
AGND
AUD_GND
32 33 34 35
22 23 24 25
2 3 4 5 1
G1
P_GND1
P_GND1
G2
P_GND2
P_GND2
G3
P_GND3
P_GND3
G4
P_GND4
P_GND4
1 2
NOBOM
NOBOM
JP1
JP1 SHORTPIN
SHORTPIN
L
PORT3
PORT3
B
B
R
R
L
L
PORT2
PORT2
L
L
R
R
L
L
PORT1
PORT1
P
P
R
R
P1
NP_NC1
NP_NC1
AGND
PEGATRON DT-MB RESTRICTED SECRET
Title :
Title :
Title :
HP AUDIO CONNECTOR
HP AUDIO CONNECTOR
HP AUDIO CONNECTOR
XXXXX_XX
XXXXX_XX
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
2
IPM41-D3
IPM41-D3
IPM41-D3
Engineer:
XXXXX_XX
Rev
Rev
Rev
1.00
1.00
35 55Thursday, July 09, 2009
35 55Thursday, July 09, 2009
1
35 55Thursday, July 09, 2009
1.00
5
4
3
2
1
Note:
D D
I
I
AD2
AD2 BAW56WPT
BAW56WPT
MIC2_VREF[34]
LIN2_VREF[34]
MIC2_L_C[34]
C C
MIC2_R_C[34] LIN2_R_C[34]
LIN2_L_C[34]
3
I
I
AD3
AD3 BAW56WPT
BAW56WPT
3
Front Side Support MIC&Headphone&Re-tasking Function
mx_4r8p0603
12
I
I
AR18
AR18 22K
22K
mx_4r8p0603
I
I
1 2
I
I
3 4
mx_4r8p0603
mx_4r8p0603
mx_4r8p0603
mx_4r8p0603
I
I
5 6
I
I
7 8
mx_4r8p0603
mx_4r8p0603
12
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
I
I
AR19
AR19 22K
22K
ARN1A
ARN1A
ARN1B
ARN1B
ARN1C
ARN1C
ARN1D
ARN1D
12
AGNDAGNDAGNDAGND
I
I
AR20
AR20 22K
22K
AL1 1 20Ohm/100Mhz/0.6A
AL1 1 20Ohm/100Mhz/0.6A
I
I
AL2 1 20Ohm/100Mhz/0.6A
AL2 1 20Ohm/100Mhz/0.6A
I
I
AL3 1 20Ohm/100Mhz/0.6A
AL3 1 20Ohm/100Mhz/0.6A
I
I
AL4 1 20Ohm/100Mhz/0.6A
AL4 1 20Ohm/100Mhz/0.6A
I
I
21 21 21
21
2
1
2
1
MIC2_VREF_R
MIC2_VREF_L
LIN2_VREF_R
LIN2_VREF_L
12
I
I
AR17
AR17 22K
22K
12
I
I
AC5
AC5 100PF/50V
100PF/50V
NPO 5%
NPO 5%
12
I
I
AC6
AC6 100PF/50V
100PF/50V
NPO 5%
NPO 5%
12
I
I
AC7
AC7 100PF/50V
100PF/50V
NPO 5%
NPO 5%
12
I
I
AC8
AC8 100PF/50V
100PF/50V
NPO 5%
NPO 5%
MIC2_L MIC2_R LIN2_R
LIN2_L
Azalia Front Audio Header
Note: Follow Intel Front Audio Pin Definition
This connection type of SENSE_B
Color = GREEN
I
I
P23
P23
1
2 3 4 5 6 7 9 10
MIC_JD
LIN_JD
HEADER_2X5P_K8
HEADER_2X5P_K8
+3P3V
just only for HDA front panel,
12
not suit for AC97 Type
I
I
AR16
AR16
4.7K
4.7K
AR2220K 1%
I
I
1 2
I
I
1 2
12
AR21&AR22 Place near to codec
NI
NI
AC23
AC23
0.1UF/16V
0.1UF/16V
Y5V +80-20%
Y5V +80-20%
GNDAGNDAGNDAGNDAGNDAGNDAGND
AR2220K 1%
AR2139.2 K 1%
AR2139.2 K 1%
F_AUDIO_DET# [21]
SENSE_B [34,35]
B B
NI
NI
AC9
AC9 100PF/50V
100PF/50V
NPO 5%
NPO 5%
1 2
NI
NI
AR23
AR23 0 Ohm
0 Ohm
1 2
8/27 modify
AGND GND
+5V
SPDIF_OUT
SPDIF_OUT
1
SPDIFO
3
I
I
4
12
NI
GND
NI
AC35
AC35
0.1UF/16V
0.1UF/16V
Y5V +80-20%
Y5V +80-20%
HEADER_1X4P_K2
HEADER_1X4P_K2
NI
NI
12
AC41
AC41 150PF/50V
150PF/50V
/X/EMI
/X/EMI
SPDIF_OUT [34]
PLACE NEAR FRONT AUDIO HEADER FOR EMI
A A
PEGATRON DT-MB RESTRICTED SECRET
AUDIO CONNECTOR
AUDIO CONNECTOR
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
5
4
3
2
IPM41-D3
IPM41-D3
IPM41-D3
Engineer:
AUDIO CONNECTOR
1
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
36 55Thursday, July 09, 2009
36 55Thursday, July 09, 2009
36 55Thursday, July 09, 2009
Rev
Rev
Rev
1.00G
1.00G
1.00G
5
D D
+3P3V
CK_33M_TPM[5]
LFRAME#[21,39]
LRESET#[13 ,21,39]
LAD3[2 1,39]
+3P3VSB
C C
LAD0[2 1,39]
LPCPD#[21]
4
CK_33M_TPM
12
GND
NI
NI
VC14
VC14
5.6PF/50V
5.6PF/50V
NPO 0.25PF
NPO 0.25PF
CK_33M_TPM LFRAMEn PLTRST# LAD3
LAD0
3
NI
NI
JLPC
JLPC
HEADER_2X10P_K4
HEADER_2X10P_K4
1 3 5 7
9 11 13 15 17 19
2
2
6 8 10 12 14 16 18 20
GND
TPM_CLKRUN#
LAD2 [21,39] LAD1 [21,39]
SERIRQ [20,39] CLKRUN# [21]
1
B B
A A
ASUS OEM-DT MB RESTRICTED SECRET
TPM HEADER
TPM HEADER
1
TPM HEADER
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
37 55Thursday, July 09, 2009
37 55Thursday, July 09, 2009
37 55Thursday, July 09, 2009
Rev
Rev
Rev
1.00G
1.00G
1.00G
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
5
4
3
2
Engineer:
IPM41-D3
IPM41-D3
IPM41-D3
5
4
3
2
1
12
I
I
O2C8
O2C8
0.1UF/16V
0.1UF/16V
+3P3VSB
ORN2D
ORN2D
4.7KOHM
4.7KOHM
5%
5% NI
NI
12
I
I
O2R25
O2R25 1M
1M
+1P1V_FSB_VTT
12
NI
NI
O2R34
O2R34 680
680
5%
5%
GND
GND
4
+VCORE
12
12
GND
ORN1C
ORN1C
4.7KOHM
4.7KOHM
5%
5% I
I
5 6
CPU_OPEN#
PECI_CPU
SIO_SST
12
I
I
O2R35
O2R35
4.7K
4.7K
I
I
O2R24
O2R24
4.7K
4.7K
+5VIN
+12VIN
I
I
O2C4
O2C4
0.1UF/16V
0.1UF/16V
I
I
O2U1A
O2U1A
100
CPUVCORE
99
VIN0
98
VIN1
97
VIN2
96
VIN3
75
RSMRST#/GP51
94
RSTOUT0#
93
RSTOUT1#
90
GP32/RSTOUT2#/SCL
89
GP33/RSTOUT3#/SDA
88
GP34/RSTOUT4#
76
CASEOPEN#
109
NC1
110
NC2
107
VTT
108
PECI
106
PECI_SB
114
SST
117
FAN_STE/PLED
19
GP22/SCE
2
GP23/SCK
W83627DHG-A
W83627DHG-A
83627DHG(C) 02X230362760
02G230362761 C.S W83627DHG-A(C) PQFP128 WINBOND (SORT)
CPUFANOUT0
GP20/CPUFANOUT1
SYSFANOUT
AUXFANOUT0
GP21/CPUFANIN1
SI/AUXFANIN1
PSOUT#/GP57
GP37/SUSC#
SUSB#/GP52
PSON#/GP53
GP35/ATXPGD
PWROK/GP54 GP30/PWRGD
GP31/3VSBSW#
HM_SMI#/OVT#
GP55/SUSLED(EN_AS)
GP36/RESETCON#
CPUFANIN0
SYSFANIN
AUXFANIN0
VREF
CPUTIN
CPUD-
SYSTIN
AUXTIN
PSIN#/GP56
PME#
BEEP/SO
3
115 120 116 7
112 119 113 111 58
GND GND GNDGND GND
IO_VREF
101
C5: Please close to pin101
103
105
104
102
GND
Please note: pin68 need have pull-up res on power connector side.
68 67 64 73 72 87 71 92
10/1 modify
91
86
5
70
69
118
Please note: Pin118 is OD pin, please add a pull-up res when you have used it.
02G230362761 C.S W83627DHG-A(C) PQFP128 WINBOND (SORT)
12
I
I
O2C10
O2C10 2200PF/50V
2200PF/50V
X7R 10%
X7R 10%
+3P3VSB +3P3VSB
12
NI
NI
O2R33
O2R33
4.7K
4.7K
SIO_SUSLED
SIO_BEEP
12
GND
I
I
O2Q21
O2Q21
PMBS3904
PMBS3904
1
1
CPUFAN_PWM [43] CHAFAN_PWM [43]
CPUFAN_TACH [43] CHAFAN_TACH [43]
I
I
O2C5
O2C5
0.1UF/16V
0.1UF/16V
C6: Please close to SIO
12
2
2 E
E
B
B
C
C 3
3
12
I
I
O2R30
O2R30 1K
1K
SR72 0
SR72 0
I
I
NOBOM
NOBOM
JP2
JP2 SHORTPIN
SHORTPIN
GND
06/29 NI for Linear, I for Switching power with +3P3VSB by TSL
+3P3VSB+3P3VSB +3P3V
12
I
I
O2R31
O2R31
4.7K
4.7K
9/5 modify
SIO_BEEP [55]
Please note: Pin71/Pin92 have the same timing sequence
+3P3VSB +3P3V+5VSB
ORN2A
ORN2A
4.7KOHM
4.7KOHM
5%
5% NI
NI
1 2
12
I
I
O2R32
O2R32
4.7K
4.7K
12
2
NI
NI
O2R8
O2R8
1K
1K
Please note: pin69 need have pull-up res on power connector side.
12
I
I
O2C6
O2C6 2200PF/50V
2200PF/50V
X7R 10%
X7R 10%
+3P3VSB
ORN1B
ORN1B
4.7KOHM
4.7KOHM
5%
5% I
I
3 4
12
LPC_PME# [21]
LPC_SMI# [21]
SYS_RESET# [7,9,21,44]
TRD_CPU_P [7]
TRD_CPU_N [7]
+3P3VSB
ORN2C
ORN2C
ORN1D
4.7KOHM
4.7KOHM
5%
5% NI
NI
5 6
1
1
ORN1D
4.7KOHM
4.7KOHM
5%
5% I
I
7 8
B
B
+3P3VSB
12
I
I
O2R168
O2R168
4.7K
4.7K
3
3
C
C
E
E 2
2
GND
I
I
O2Q4
O2Q4
PMBS3904
PMBS3904
ORN2B
ORN2B
4.7KOHM
4.7KOHM
5%
5% NI
NI
3 4
PWRBTN# [44] SB_PWRBTN# [21] SLP_S5# [19,21] SLP_S3# [21] PSON# [45] ATX_PWRGD [45] PWROK [13,21]
Add inverter circuit for +3VSBSW function
+3VSBSW [50]
12
NI
NI
O2C11
O2C11 1UF/10V
1UF/10V
mx_c0603
mx_c0603
GND
Only S3
S0/S1
high
1
S3
S4/S5
ORN1A
ORN1A
4.7KOHM
4.7KOHM
5%
5% I
I
1 2
I
I
O2R169
O2R169
4.7K
4.7K
1 2
0
ASUS OEM-DT MB RESTRICTED SECRET
SIO W83627DHG 1 - 2
SIO W83627DHG 1 - 2
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
IPM41-D3
IPM41-D3
IPM41-D3
Engineer:
SIO W83627DHG 1 - 2
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
1
38 55Thursday, July 09, 2009
38 55Thursday, July 09, 2009
38 55Thursday, July 09, 2009
Rev
Rev
Rev
1.00G
1.00G
1.00G
12
12
I
I
O2R13
O2R13 22K
22K
1%
1%
I
I
O2R16
O2R16 10K
10K
1%
1%
+12V
12
Voltage over 2.048V or less than 0V
I
I
O2R14
O2R14
Please add those divider res if you need to
56K
56K
monitor the voltage with +5V or +12V
1%
1%
12
I
I
O2R15
O2R15 10K
10K
1%
1%
GND
Please note: pin94 need have pull-up res on IDE connector side.
RSMRST#[21]
PCIES_RST#[24,25,32]
Please note PIN76: You also used this pin as inducder function.
Pin 117 : During power-on reset, this pin is pulled down internally and is defined as fan rotation rate is 50%. Only CPUFANOUT0 supports.
12
I
I
O2C7
O2C7
0.1UF/16V
0.1UF/16V
GNDGND
+5V
7 8
+BATT
+5V
D D
GND
C C
B B
Pin108 : from CPU
+3P3V +3P3V
12
12
NI
NI
NI
NI
O2R5
O2R5
O2R6
O2R6
1K
1K
1K
1K
A A
10/1 modify
5
Pin106 : To SB
PECI_CPU[7]
PLED_P[44]
5
I
I
P10
P10
BOX_HEAD_2X17P_K5
BOX_HEAD_2X17P_K5
1 3
7
D D
GND
C C
9 11 13 15 17 19 21 23 25 27 29 31 33
+3P3V +3P3V+3P3V
12
NI
NI
O2R2
O2R2
4.7K
4.7K
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34
12
NI
NI
O2R3
O2R3
4.7K
4.7K
4
+5V
+5V
O2RN1B
O2RN1B
I
I
3 4
1K
1 2 7 8 5 6
DENSEL# INDEX# MTRA# DRVA# DIR# STEP# WDATA# WGATE# TRK0# WPT# RDATA# HDSEL# DSKCHG#
XINIT#[40] XSLIN#[40] SLCT[40] PE[ 40] BUSY[40]
ACK#[40] ERROR#[40] XAFD#[40] XSTB#[40]
XPD7[4 0] XPD6[4 0] XPD5[4 0] XPD4[4 0] XPD3[4 0] XPD2[4 0] XPD1[4 0] XPD0[4 0]
1K 1K
1K 1K
1K 1K
1K
O2RN1A
O2RN1A
I
I
O2RN1D
O2RN1D
I
I
O2RN1C
O2RN1C
I
I
12
I
I
O2R4
O2R4
4.7K
4.7K
12
I
I
O2R1
O2R1 1K
1K
I
I
O2U1B
O2U1B
1 3 4 6 8
9 10 11 13 14 15 16 17
44 43 31 32 33 34 45 46 47
35 36 37 38 39 40 41 42
3
DRVDEN0 INDEX# MOA# DSA# DIR# STEP# WD# WE# TRAK0# WP# RDATA# HEAD# DSKCHG#
INIT# SLIN# SLCT PE BUSY ACK# ERR# AFD# STB#
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
3VSB
VBAT
3VCC_1 3VCC_2 3VCC_3
AVCC
2
+3P3VSB
61
12
I
I
O2CB1
O2CB1
0.1UF/16V
0.1UF/16V
GND
+BATT
74
12
I
I
O2CB2
O2CB2 1UF/10V
1UF/10V
mx_c0603
mx_c0603
GND
12 28 48 95
12
I
I
O2CB3
O2CB3
0.1UF/16V
0.1UF/16V
GND GND GND GND
12
I
I
O2CB4
O2CB4
0.1UF/16V
0.1UF/16V
12
I
I
O2CB5
O2CB5
0.1UF/16V
0.1UF/16V
+3P3V
12
NI
NI
O2CB6
O2CB6
0.1UF/16V
0.1UF/16V
1
LAD0[21,37] LAD1[21,37] LAD2[21,37] LAD3[21,37]
LFRAME#[21,37]
LDRQ#[21] LRESET#[13,21,37] CK_33M_SIO[5]
SERIRQ[20,37 ]
KBDATA[42] KBCLK[42] MSDATA[42] MSCLK[42]
RST_KB[20]
0x002E
0x004E
5
A20GATE[20]
TXD1[41]
RTS1#[41]
DTR1#[41]
ORN3B
ORN3B 1KOHM
1KOHM
5%
5% I
I
3 4
ROM TRAPING -> DTR1# : During power on reset, it is internal PD
0
+5V
ORN3A
ORN3A 1KOHM
1KOHM
5%
5% I
I
1 2
ORN3C
ORN3C 1KOHM
1KOHM
5%
5% I
I
5 6
GNDGND
12
NI
NI
O2C1
O2C1
0.1UF/16V
0.1UF/16V
RXD1[41]
DSR1#[41]
CTS1#[41]
RI1#[41] DCD1#[4 1]
KEYBOARD TRAPING -> PENKBC : During power on reset, it is internal PD
PENROMDTR1#
DISABLE
ENABLE
4
TXD1
GNDGND
12
NI
NI
O2C2
O2C2 12PF/50V
12PF/50V
NPO 5%
NPO 5%
GND
12
NI
NI
O2C3
O2C3
0.1UF/16V
0.1UF/16V
KEYBOARD
DISABLE
0
ENABLE
1
B B
A A
PORT ADDRESS TRAPING -> HEFRAS : During power on reset, it is internal PD
CONFIG PORT ADDRRTS1#
0
1 1
27
LAD0
26
LAD1
25
LAD2
24
LAD3
29
LFRAME#
22
LDRQ#
30
LRESET#
21
PCICLK
23
SERIRQ
63
KDAT/GP26
62
KCLK/GP27
66
MDAT/GP24
65
MCLK/GP25
60
KBRST
59
GA20M
53
SINA/GP63
54
SOUTA/GP62(PENKBC)
50
DSRA#/GP66
51
RTSA#/GP65(HEFRAS)
49
CTSA#/GP67
52
DTRA#/GP64(PENROM)
57
RIA#/GP60
56
DCDA#/GP61
W83627DHG-A
W83627DHG-A
83627DHG(C) 02X230362760
02G230362761 C.S W83627DHG-A(C) PQFP128 WINBOND (SORT)
3
GP50/WDTO#(EN_GTL)
GP43/SINB/IRRX
GP42/SOUTB/IRTX
GP46/DSRB#
GP45/RTSB# GP47/CTSB# GP44/DTRB#
GP41/DCDB#
IOCLK
VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7
GP40/RIB#
VSS1 VSS2
18
128 127 126 125 124 123 122 121 77
VID TRAPING -> VID_GTL
VID_GTL VID VOLTAGE
0
1
82 83 79 80 78 81 85 84
20 55
GND
TTL
VRD10
12
GND
2
NI
NI
O2R17
O2R17 680
680
5%
5%
CK_48M_SIO [5]
GND
IR_CON
RXD2 [41] TXD2 [41] DSR2# [41] RTS2# [41] CTS2# [41] DTR2# [41] RI2# [41] DCD2# [41]
X1_0907
X1_0907
X1_0907
ASUS OEM-DT MB RESTRICTED SECRET
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
IPM41-D3
IPM41-D3
IPM41-D3
IR_CON
1
3 4
I
I
5
HEADER_1X5P_K2
HEADER_1X5P_K2
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
1
+5V
RXD2
TXD2
modify 7/30
GND
SIO W83627DHG 2 - 2
SIO W83627DHG 2 - 2
SIO W83627DHG 2 - 2
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
39 55Thursday, July 09, 2009
39 55Thursday, July 09, 2009
39 55Thursday, July 09, 2009
NI
NI
12
C512
C512
0.1UF/16V
0.1UF/16V
Y5V +80-20%
Y5V +80-20%
Rev
Rev
Rev
1.00G
1.00G
1.00G
5
4
3
2
1
D D
<< FOR CPC >>
+5V
C C
XPD7[39] XPD6[39] XPD5[39] XPD4[39]
XPD3[39] XPD2[39] XPD1[39] XPD0[39]
XAFD#[39]
XSTB#[39] XINIT#[39] XSLIN#[3 9]
ERROR#[39]
B B
12
GND
1 2
NI
NI
CB3
CB3
0.1UF/16V
0.1UF/16V
I
I
D2
D2
1SS355PT
1SS355PT
GND
12
CB4
CB4
0.01UF/25V
0.01UF/25V
X7R 10%
X7R 10%
I
+5V_PRT
RN2C
5 6
2.2k
2.2k
1 2
2.2k
2.2k
5 6
2.2k
2.2k
1 2
2.2k
2.2k
3 4
2.2k
2.2k
5 6
2.2k
2.2k
7 8
2.2k
2.2k
1 2
2.2k
2.2k
12 12 12 12
RN2C
RN3A
RN3A
RN3C
RN3C
RN1A
RN1A
RN1B
RN1B
RN1C
RN1C
RN1D
RN1D
RN4A
RN4A
SPD0
SPD1
SPD2SPD2
SPD3SPD3
SPD4SPD4
SPD5SPD5
SPD6SPD6
SPD7SPD7
C43 150PF/50V
C43 150PF/50V
I
I
1 2
C5 150PF/50V
C5 150PF/50V
I
I
1 2
C10 150PF/50V
C10 150PF/50V
I
I
1 2
C14 150PF/50V
C14 150PF/50V
I
I
1 2
GND
GND
I
I
I
I
I
RN5D
RN5D
I
I
RN5A
RN5A
I
I
RN5B
RN5B
I
I
RN5C
RN5C
I
I
RN6D
RN6D
I
I
RN6B
RN6B
I
I
RN7D
RN7D
I
I
RN7A
RN7A
I
I
RN7B
RN7B
I
I
RN7C
RN7C
I
I
RN6C
RN6C
I
I
RN6A
RN6A
I
I
GND
I
I
I
I
I
I
I
I
I
I
I
I
I
7 8
22
22
1 2
22
22
3 4
22
22
5 6
22
22
7 8
22
22
3 4
22
22
7 8
22
22
1 2
22
22
3 4
22
22
5 6
22
22
5 6
22
22
1 2
22
22
C42 150PF/50V
C42 150PF/50V
I
I
C45 150PF/50V
C45 150PF/50V
I
I
C8 150PF/50V
C8 150PF/50V
I
I
C9 150PF/50V
C9 150PF/50V
I
I
I
R1
R1
2.2K
2.2K
1 2
RN4B
3 4
2.2k
2.2k
5 6
2.2k
2.2k
7 8
2.2k
2.2k
7 8
2.2k
2.2k
7 8
2.2k
2.2k
3 4
2.2k
2.2k
1 2
2.2k
2.2k
3 4
2.2k
2.2k
12 12 12 12
RN4B
RN4C
RN4C
RN4D
RN4D
RN2D
RN2D
RN3D
RN3D
RN3B
RN3B
RN2A
RN2A
RN2B
RN2B
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
C46 150PF/50V
C46 150PF/50V
I
I
C47 150PF/50V
C47 150PF/50V
I
I
C12 150PF/50V
C12 150PF/50V
I
I
C15 150PF/50V
C15 150PF/50V
I
I
C3 150PF/50V
C3 150PF/50V
I
I
C7 150PF/50V
C7 150PF/50V
I
I
C13 150PF/50V
C13 150PF/50V
I
I
C17 150PF/50V
C17 150PF/50V
I
I
C16 150PF/50V
C16 150PF/50V
I
I
GND
PARALLEL PORT
I
I
J50
J50
D-SUB_25P
D-SUB_25P
26
SIDE_G26
SLCT[39 ]
PE[39]
BUSY[39]
ACK#[39]
12 12 12 12 12
SLCT
PE
BUSY
ACK#
SPD7
SPD6
SPD5
SPD4
SPD3 SLIN# SPD2 PINIT# SPD1 ERROR# SPD0 AFD# STB#
GND
SIDE_G26
13
SLCT
SLCT
25
GND8
GND8
12
PE
PE
24
GND7
GND7
11
BUSY
BUSY
23
GND6
GND6
10
ACK#
ACK#
22
GND5
GND5
9
SPD7
SPD7
21
GND4
GND4
8
SPD6
SPD6
20
GND3
GND3
7
SPD5
SPD5
19
GND2
GND2
6
SPD4
SPD4
18
GND1
GND1
5
SPD3
SPD3
17
SLIN#
SLIN#
4
SPD2
SPD2
16
PINIT#
PINIT#
3
SPD1
SPD1
15
ERROR#
ERROR#
2
SPD0
SPD0
14
AFD#
AFD#
1
STB#
STB#
27
SIDE_G27
SIDE_G27
SIDE_G28
SIDE_G28
28
GND
A A
ASUS OEM-DT MB RESTRICTED SECRET
PARALLEL PORT - 2
PARALLEL PORT - 2
PARALLEL PORT - 2
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Engineer:
IPM41-D3
IPM41-D3
IPM41-D3
1
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
40 55Thursday, July 09, 2009
40 55Thursday, July 09, 2009
40 55Thursday, July 09, 2009
Rev
Rev
Rev
1.00G
1.00G
1.00G
5
A
4
3
2
1
+12V
3
I
I
D7
D7
12
NI
BAT54AW
BAT54AW
D D
I
+5V
DCD1#[39]
RRI1_B
I
I
C30
C30 1000PF/50V
1000PF/50V
X7R 10%
X7R 10%
DSR1#[ 39]
12
I
I
CB11
CB11
0.1UF/16V
0.1UF/16V
GND
+3P3VSB
12
I
I
R1154
R1154
8.2K
8.2K
I
C C
RING#[21]
I
Q2
Q2
3
3
PMBS3904
PMBS3904
C
C
B
1
B
1
E
E 2
2
GND GND GND
12
DCD1# DSR1# RXD1
RXD1[39]
RTS1#
RTS1#[39]
TXD1
TXD1[39]
CTS1#
CTS1#[39]
DTR1#
DTR1#[39] RI1#[39]
12
I
I
R8
R8
2.2K
2.2K
RI1#
I
I
R9
R9
4.7K
4.7K
GND
12
I
U3
U3
INTERFACE RS-232
INTERFACE RS-232
20
VCC
19
RY1
18
RY2
17
RY3
16
DA1
15
DA2
14
RY4
13
DA3
12
RY5
11
GND
RRI1_D
VCC+
I
I
3
BAT54CW
BAT54CW
RA1 RA2 RA3 DY1 DY2 RA4 DY3 RA5
VCC-
D10
D10
+12V_COM
1 2 3 4 5 6 7 8 9 10
1
2
DDCD1# DDSR1# RRXD1 RRTS1# TTXD1 CCTS1# DDTR1# RRI1
-12V_COM
RRI1
RRI2#
1
2
NI
GND
CB10
CB10
0.01UF/25V
0.01UF/25V
X7R 10%
X7R 10%
-12V
1
2
I
I
3
D8
D8 BAT54AW
BAT54AW
GND
12
NI
NI
CB9
CB9
0.01UF/25V
0.01UF/25V
X7R 10%
X7R 10%
RRI1 DDTR1# CCTS1# TTXD1
RRTS1# RRXD1 DDSR1# DDCD1#
C27 150PF/50VINPO 5%C2 7 150PF/50VINPO 5%
1 2
C28 150PF/50VINPO 5%C2 8 150PF/50VINPO 5%
1 2
C29 150PF/50VINPO 5%C2 9 150PF/50VINPO 5%
1 2
C31 150PF/50VINPO 5%C3 1 150PF/50VINPO 5%
1 2
C32 150PF/50VINPO 5%C3 2 150PF/50VINPO 5%
1 2
C33 150PF/50VINPO 5%C3 3 150PF/50VINPO 5%
1 2
C34 150PF/50VINPO 5%C3 4 150PF/50VINPO 5%
1 2
C35 150PF/50VINPO 5%C3 5 150PF/50VINPO 5%
1 2
SERIAL PORT A
DDCD1# DDSR1# RRXD1 RRTS1# TTXD1 CCTS1# DDTR1# RRI1
GND
GND
10
1 6 2 7 3 8 4 9 5
11
I
I
J53
J53
D-SUB_9P
D-SUB_9P
SIDE_G10
SIDE_G10
DDCD#
DDCD#
DDSR#
DDSR#
RRXD
RRXD
RRTS#
RRTS#
TTXD
TTXD
CCTS#
CCTS#
DDTR#
DDTR#
RRI#
RRI#
GND1
GND1
SIDE_G11
SIDE_G11
SERIAL PORT B
090507 modify P53 to P52 for text
I
I
P52
B B
+5V
GND
DDCD2# TTXD2
RRTS2# RRI2#
12
I
I
CB12
CB12
0.1UF/16V
0.1UF/16V
P52
1
2
1
3
3
4
5
6
5
7
8
7
9
9
BOX_HEAD_2X5P_K10
BOX_HEAD_2X5P_K10
GND
C70 150PF/50VINPO 5%C7 0 150PF/50VINPO 5%
1 2
C71 150PF/50VINPO 5%C7 1 150PF/50VINPO 5%
1 2
C72 150PF/50VINPO 5%C7 2 150PF/50VINPO 5%
1 2
C73 150PF/50VINPO 5%C7 3 150PF/50VINPO 5%
1 2
C74 150PF/50VINPO 5%C7 4 150PF/50VINPO 5%
1 2
C75 150PF/50VINPO 5%C7 5 150PF/50VINPO 5% C76 150PF/50VINPO 5%C7 6 150PF/50VINPO 5% C77 150PF/50VINPO 5%C7 7 150PF/50VINPO 5%
DCD2#[39]
DSR2#[39]
RTS2#[39]
TXD2[39] CTS2#[39] DTR2#[39] RI2#[39]
GND
1 2 1 2 1 2
GND
RXD2[39]
GND
2 4 6 8
DCD2# DSR2# RXD2 RTS2# TXD2 CTS2# DTR2#
RI2#
RRXD2 DDTR2# DDSR2# CCTS2#
I
I
U4
U4
INTERFACE RS-232
INTERFACE RS-232
20
VCC
19
RY1
18
RY2
17
RY3
16
DA1
15
DA2
14
RY4
13
DA3
12
RY5
11
GND
VCC+
RA1 RA2 RA3 DY1 DY2 RA4 DY3 RA5
VCC-
+12V
1
DDCD2#
2
DDSR2#
3
RRXD2
4
RRTS2#
5
TTXD2
6
CCTS2#
7
DDTR2#
8
RRI2#
9
-12V_COM
10
12
GND
NI
NI
CB13
CB13
0.01UF/25V
0.01UF/25V
X7R 10%
X7R 10%
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
IPM41-D3
IPM41-D3
IPM41-D3
Engineer:
COM Port
COM Port
COM Port
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
41 55Thursday, July 09, 2009
41 55Thursday, July 09, 2009
41 55Thursday, July 09, 2009
Rev
Rev
Rev
1.00G
1.00G
1.00G
A
5
D D
4
3
2
1
PS/2 KEYBOARD & MOUSE FOR CPC
I
FF+5V
Note:
The +5V_DUAL_USB_B power trace width must have 40 mils or more
C C
I
YF2
YF2
1.1A/6V
1.1A/6V
1 2
KBPWR
KBPWR
1 2
I
I
3
HEADER_1X3P
HEADER_1X3P
Default as short pin 2-3
KBPWR: 1-2: +5V 2-3: +5VSB
KBPWR:23
KBPWR:23
I
I
MINI_JUMPER
MINI_JUMPER
+5V_KBMS_F
+5V
+5VSB
FF+5V
+5V_KBMS
12
I
I
YCB2
YCB2
0.1UF/16V
0.1UF/16V
GND
GND
I
I
J68
J68
MINI_DIN_6PX2
MINI_DIN_6PX2
10
VCC2
9
GND2
13
SIDE_G13
14
SIDE_G14
4
VCC1
3
GND1
15
SIDE_G15
16
SIDE_G16
17
SIDE_G17
PS2_MOUSE
PS2_MOUSE
MDATA
MCLK
NC3 NC4
PS2_KB
PS2_KB
KDATA
KCLK
NC1 NC2
FF+5V
YRN4A
YRN4A
I
I
YRN4B
YRN4B
I
I
YRN4C
YRN4C
I
I
YRN4D
YRN4D
I
I
7
11
8 12
1
5
2 6
CMSDATA
CMSCLK
CKBDATA
CKBCLK
YL6 1 20Ohm/100Mhz/0.6A
YL6 1 20Ohm/100Mhz/0.6A
I
I
2 1
YL7 1 20Ohm/100Mhz/0.6A
YL7 1 20Ohm/100Mhz/0.6A
I
I
2 1
YL8 1 20Ohm/100Mhz/0.6A
YL8 1 20Ohm/100Mhz/0.6A
I
I
2 1
YL9 1 20Ohm/100Mhz/0.6A
YL9 1 20Ohm/100Mhz/0.6A
I
I
2 1
YC5 150PF/50 V NPO 5%
YC5 150PF/50 V NPO 5%
I
I
1 2
YC6 150PF/50 V NPO 5%
YC6 150PF/50 V NPO 5%
I
I
1 2
YC7 150PF/50 V NPO 5%
YC7 150PF/50 V NPO 5%
I
I
1 2
YC8 150PF/50 V NPO 5%
YC8 150PF/50 V NPO 5%
I
I
1 2
MDAT
MCLK
KDAT
KCLK
I
I
I
I
I
I
I
I
YRN3C
YRN3C
YRN3A
YRN3A
YRN3D
YRN3D
YRN3B
YRN3B
5 6
33
33
1 2
33
33
7 8
33
33
3 4
33
33
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
12 34 56 78
MSDATA [3 9]
MSCLK [3 9]
KBDATA [39]
KBCLK [39]
GND
B B
A A
ASUS MBRD2_CEC RESTRICTED SECRET
KB & MS FOR CPC
KB & MS FOR CPC
KB & MS FOR CPC
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
5
4
3
2
Engineer:
IPM41-D3
IPM41-D3
IPM41-D3
1
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
42 55Thursday, July 09, 2009
42 55Thursday, July 09, 2009
42 55Thursday, July 09, 2009
Rev
Rev
Rev
1.00G
1.00G
1.00G
5
4
3
2
1
CPU FAN
COLOR: WHITE
W/POST
I
I
P70
12
I
I
C2
C2 100PF/50V
100PF/50V
NPO 5%
NPO 5%
P70
WAFER_HD_4P
WAFER_HD_4P
1
1
2
2
3
3
4
4
5
NC
CFAN_D
12
I
I
R1150
R1150
4.7K
4.7K
I
I
R3
R3 150
150
mx_r0805
mx_r0805
1 2
I
I
R1151
R1151
1.5K
1.5K
+12V
D D
12
+
+
I
I
CE1
CE1 100uF/16V
100uF/16V
GND GND
12
NI
NI
CB1
CB1
0.01UF/25V
0.01UF/25V
X7R 10%
X7R 10%
GND
12
I
I
C40
C40 100PF/50V
100PF/50V
NPO 5%
NPO 5%
+5V
3
I
I
D1
D1 BAT54CW
BAT54CW
1
2
12
+5V+3P3V
12
I
I
R2
R2 1K
1K
CPUFAN_PWMCPUFAN_PWM_C
CPUFAN_TACH
CPUFAN_PWM [38]
CPUFAN_TACH [38]
GND
GND
CHASIS FAN
COLOR: WHITE
12
GND
1 2 3 4 5
I
I
C4
C4 100PF/50V
100PF/50V
NPO 5%
NPO 5%
W/POST
I
I
P8
P8
WAFER_HD_4P
WAFER_HD_4P
1 2 3 4 NC
F_SFAN_D
+3P3V
12
I
I
R6
R6
4.7K
4.7K
I
I
R1152
R1152 150
150
mx_r0805
mx_r0805
1 2
I
I
R1153
R1153
1.5K
1.5K
+5V
3
I
I
D9
D9 BAT54CW
BAT54CW
1
2
12
+5V
12
I
I
R5
R5 1K
1K
F_CHAFAN_PWMF_CHAFAN_PWM_C
F_CHAFAN_TACH
CHAFAN_PWM [38]
CHAFAN_TACH [38]
C C
+12V
12
+
+
I
I
CE2
CE2 100uF/16V
100uF/16V
GND
B B
12
GND
NI
NI
CB2
CB2
0.01UF/25V
0.01UF/25V
X7R 10%
X7R 10%
7/15 modify part reference
GND
12
I
I
C41
C41 100PF/50V
100PF/50V
NPO 5%
NPO 5%
GND
A A
ASUS OEM-DT MB RESTRICTED SECRET
4-PIN FAN CONN
4-PIN FAN CONN
4-PIN FAN CONN
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
5
4
3
2
Engineer:
IPM41-D3
IPM41-D3
IPM41-D3
1
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
43 55Thursday, July 09, 2009
43 55Thursday, July 09, 2009
43 55Thursday, July 09, 2009
Rev
Rev
Rev
1.00G
1.00G
1.00G
5
4
3
2
1
12
NI
NI
R1148
R1148 0
0
mx_r0805
mx_r0805
+5V_DUAL
12
3
3
C
C
E
E 2
2
GND
+5V_DUAL
12
3
3
C
C
E
E 2
2
GNDGNDGND
I
I
R1141
R1141 220
220
mx_r0805
mx_r0805
NI
NI
Q1
Q1 PMBS3904
PMBS3904
B
1
B
1
I
I
R1147
R1147 220
220
mx_r0805
mx_r0805
I
I
Q3
Q3 PMBS3904
PMBS3904
B
1
B
1
SIO_LED1_G
SIO_LED2_G
NI
NI
R1143
R1143 1K
1K
I
I
R1149
R1149 1K
1K
+3P3VSB
12
NI
NI
R1142
R1142 1K
1K
12
12
PLED_P [38]
PLED_N [21]
INTEL CONTROL PANEL / LED CIRCUITRY
D D
R1156
R1156
1 2
100 Ohm
100 Ohm
5%
5% I
I
GND
+3P3VSB
12
I
I
R1146
R1146
4.7K
4.7K
PWRBTN# [38]
12
C37
C37 1000PF/50V
1000PF/50V
X7R 10%
X7R 10%
GND GND
I
I
12
NI
NI
C38
C38
0.1UF/16V
0.1UF/16V
GND GND
12
NI
NI
C39
C39
0.1UF/16V
0.1UF/16V
+3P3VSB +5V
C C
HD_LED#[27]
SYS_RESET#[7,9,21,38]
12
NI
NI
R1144
R1144
4.7K
4.7K
10/1 modify
12
I
I
R1145
R1145 220
220
mx_r0805
mx_r0805
12
I
I
C36
C36
0.1UF/16V
0.1UF/16V
HDLED+
R1155
R1155
1 2
100 Ohm
100 Ohm
5%
5% I
I
I
I
P5
P5 HEADER_2X5P_K10
HEADER_2X5P_K10
1
2 3 4 5 6 7 8 9
FP_LED+ FP_LED-
B B
R10FRONT POWER LED COLOR SUPPORT
SINGLE COLOR
DUAL COLOR
A A
Q2 R6 R11
I
NI NI NI
I I INI
ASUS OEM-DT MB RESTRICTED SECRET
FRONT_PANEL
FRONT_PANEL
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Engineer:
IPM41-D3
IPM41-D3
IPM41-D3
FRONT_PANEL
1
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
44 55Thursday, July 09, 2009
44 55Thursday, July 09, 2009
44 55Thursday, July 09, 2009
Rev
Rev
Rev
1.00G
1.00G
1.00G
5
4
3
2
1
ATX POWER_24P SUPPLY CONNECTOR
NOTE:
ATX_PWRGD internal pull high in PSU
I
I
P1CB2
P1CB2
0.1UF/16V
0.1UF/16V
+5V
GND
12
I
I
P1CB4
P1CB4
0.1UF/16V
0.1UF/16V
+3P3V
12
I
I
P1CB5
P1CB5
0.1UF/16V
0.1UF/16V
+5V
D D
ATX_PWRGD[38]
12
NI
NI
P1R2
P1R2
8.2K
8.2K
I
I
P1R4
P1R4 100
100
1 2
ATX_PWRGD_C
12
I
I
P1C1
P1C1 1000PF/50V
1000PF/50V
X7R 10%
X7R 10%
GND GND
12
GND
+5VSB+12V
I
I
P1CB1
P1CB1
0.1UF/16V
0.1UF/16V
12
GND GNDGND
GNDGND
I
I
P1
P1
POWER_CON_2X12P
POWER_CON_2X12P
1
+3V1
2
+3V2
3
GND1
4
+5V1
5
GND2
6
+5V2
7
GND3
8
PWR0K
9
5VSB
10
+12V1
11
+12V2
12
+3V3
25
26
hold1
hold2
+3V4
-12V
GND4
PSON#
GND5 GND6 GND7
+5V3 +5V4 +5V5
GND8
+5V +3P3V
13 14 15 16 17 18 19 20
-5V
21 22 23 24
GND
12
NI
NI
P1CB6
P1CB6
0.1UF/16V
0.1UF/16V
1 2
GND
I
I
P1CB7
P1CB7
0.1UF/16V
0.1UF/16V
-12V
12
NI
NI
P1CE1
P1CE1
0.1UF/16V
0.1UF/16V
12
NI
NI
P1CB8
P1CB8
0.1UF/16V
0.1UF/16V
12
GND
P1_PSON#
I
I
P1C2
P1C2 1000PF/50V
1000PF/50V
X7R 10%
X7R 10%
-5V
12
GND
NI
NI
P1CB3
P1CB3
0.1UF/16V
0.1UF/16V
I
I
P1R3
P1R3 47
47
12
PSON# [38]
All of the Caps Around the ATX Power Connector
C C
B B
A A
VRM POWER_4P SUPPLY CONNECTOR
I
I
P3
GND
P3
POWER_CON_2X2P
POWER_CON_2X2P
2
2
4
1
1
3
NP_NC
4 3 5
12
GND
NI
NI
P1CB9
P1CB9
0.1UF/16V
0.1UF/16V
+12V_CPU
12
NI
NI
P1CB10
P1CB10
0.1UF/16V
0.1UF/16V
GND
ASUS OEM-DT MB RESTRICTED SECRET
ATX POWER
ATX POWER
1
ATX POWER
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
45 55Thursday, July 09, 2009
45 55Thursday, July 09, 2009
45 55Thursday, July 09, 2009
Rev
Rev
Rev
1.00G
1.00G
1.00G
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
5
4
3
2
IPM41-D3
IPM41-D3
IPM41-D3
Engineer:
5
D D
+VTT_OUT_L +VTT_OUT_R
I
I
PR20
PR20 0
0
1 2
NI
NI
PC12
PC12 120PF/50V
120PF/50V
NPO 5%
NPO 5%
12
12
NI
NI
PC14
PC14 120PF/50V
120PF/50V
NPO 5%
NPO 5%
12
I
I
PC59
PC59
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
2009/04/30 PR7 change to NI
NI
NI
PR7
PR7 0 Ohm
0 Ohm
mx_r0603
mx_r0603
1 2
I
I
PR18
PR18 0 Ohm
0 Ohm
mx_r0603
mx_r0603
1 2
VRM_VCC5_A
12
I
I
PC23
PC23 1UF/16V
1UF/16V
mx_c0603
mx_c0603 X7R 10%
X7R 10%
GND
+VTT_OUT_L
12
I
I
PR37
PR37 180K
180K
1%
1%
12
I
I
PR41
PR41 820
820
1%
1%
12
I
I
PR5
PR5 1K
1K
12
NI
NI
PR10
PR10 100K
100K
1%
1%
12
VRM_ADJ2_A
12
I
I
PR4
PR4 1K
1K
VCORE_PSI[51]
5
3%
3%
VRMPWRGD[7,51]
I
I
PR19
PR19 100
100
1%
1%
A1
1 2
I
I
PR107
PR107 0
0
1 2
I
I
PR108
PR108 0
0
1 2
I
I
PR25
PR25 100
100
1%
1%
A2
1 2
3KOHM1%
3KOHM1%
I
I
1 2
NI
NI
PC18
PC18
0.1UF/16V
0.1UF/16V
1 2
X7R 10%
X7R 10%
1 2
12
I
I
PR40
PR40 180K
180K
1%
1%
PR22
PR22
I
I
PR36
PR36
6.8K
6.8K
1%
1%
NI
NI
PC19
PC19
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
12
NI
NI
PC3
PC3
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
C C
+VCORE
NOBOM
NOBOM
PJP11
PJP11 SHORTPIN
SHORTPIN
1 2
VCC_SENSE[7]
VSS_SENSE[7]
NOBOM
NOBOM
PJP12
PJP12 SHORTPIN
B B
CPU : AN6
A A
SHORTPIN
1 2
GND GND
I
I
PR29
PR29 10K
10K
mx_r0603
mx_r0603
1 2
GND
I
I
PC22
PC22
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
1 2
GND GND GND GND GND GND GND GND GND GND
4
+12V_CPU
12
NI
NI
PCB1
PCB1
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND GND GND
+VTT_OUT_R
12
I
I
HR57
HR57 1K
1K
I
I
PC4
PC4 1000PF/50V
1000PF/50V
VRM_COMP1_A
12
X7R 10%
X7R 10%
VRM_FB1_A
I
I
PC9
PC9 820PF/50V
820PF/50V
VRM_COMP2_A
12
X7R 10%
X7R 10%
VRM_VOUT1_A
VRM_ADJ1_A
12
I
I
PC60
PC60 680PF/50V
680PF/50V
X7R 10%
X7R 10%
GND GND
06/12 modify by Power team
PR33 10KI1%PR33 10KI1%
1 2
PR35 110KOHMNI1%PR35 110KOHMNI1%
1 2
4
I
I
PR1
PR1
4.7
4.7
mx_r0603
mx_r0603
1 2
RCVID[0..7][7]
2009/04/30 HR57 from 51ohm change to 1Kohm
VID_SELECT[7]
I
I
PR11
PR11 20KOhm
20KOhm
1 2
1%
NI
NI
PC6
PC6
0.1UF/16V
0.1UF/16V
1 2
X7R 10%
X7R 10%
I
I
PC13
PC13
0.1UF/16V
0.1UF/16V
1 2
X7R 10%
X7R 10%
I
I
PC15
PC15
0.01UF/25V
0.01UF/25V
1 2
X7R 10%
X7R 10%
PR16
PR16
1 2
510 OHM
510 OHM
1%
1%
I
I
06/12 modify by Power team
12
I
I
PC24
PC24 1000PF/50V
1000PF/50V
X7R 10%
X7R 10%
1%
I
I
PR13
PR13 0
0
1 2
I
I
PR14
PR14 1K
1K
1 2
1%
1%
I
I
PR8
PR8
1.8KOHM
1.8KOHM
1 2
1%
1%
I
I
PC16
PC16 120PF/50V
120PF/50V
12
NPO 5%
NPO 5%
I
I
PR31
PR31 200 Ohm
200 Ohm
1%
1%
1 2
12
I
I
PR42
PR42 240K
240K
1%
1%
06/12 modify by Power team
12
I
I
PCB2
PCB2
0.47UF/16V
0.47UF/16V
mx_c0603
mx_c0603 X7R 10%
X7R 10%
3
I
I
PU1
PU1 RT8857GQW
RT8857GQW
VRM_VCC_C
VRM_PSI#_A VRM_EN_A VRMPWRGD
VRM_FB_A
VRM_COMP_A
VRM_VOUT_A
VRM_QR2_A
VRM_FBRTN_A
VRM_SS_A
VRM_QR1_A
VRM_ADJ_A
12
NI
NI
PC20
PC20 2200PF/50V
2200PF/50V
X7R 10%
X7R 10%
VRM_IMAXPSI_A VRM_RT_A
VRM_IMAX_A
VRM_OFS_A
VRM_VCC5_A
VRM_IMONFB_A
VRM_IMON_A
12
I
I
PR30
PR30 140OHM
140OHM
1%
1%
RCVID0 RCVID1 RCVID2 RCVID3 RCVID4 RCVID5 RCVID6 RCVID7
12
I
I
PC25
PC25 1000PF/50V
1000PF/50V
X7R 10%
X7R 10%
31
VCC12
49
GND
45
VID0
44
VID1
43
VID2
42
VID3
41
VID4
40
VID5
39
VID6
38
VID7
46
VIDSEL
47
PSI#
37
EN/VTT
36
PWRGD
6
FB
5
COMP
48
VOUT
3
QR2
1
FBRTN
4
SS/EN
2
QR1
9
ADJ
11
IMAXPSI
10
IMAX
7
OFS
24
VCC5
12
IMONFB
13
IMON
3
BOOT1
UGATE1
PHASE1
LGATE1
ISP1
ISN1
BOOT2
UGATE2
PHASE2
LGATE2
ISP2
ISN2
PWM3
ISP3
ISN3
PWM4
ISP4
ISN4
VRHOT
TSEN
GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8
35
34
33
32
21
20
27
28
29
30
18
19
26
17
16
25
14
15
22
23
8
RT
50 51 52 53 54 55 56 57
R_ISEN1+_A
R_ISEN1-_A
R_ISEN2+_A
R_ISEN2-_A
R_ISEN3+_A
R_ISEN3-_A
I
I
PR12
PR12 1KOhm
1KOhm
mx_r0603
mx_r0603 1%
1%
1 2
I
I
PR17
PR17 1KOhm
1KOhm
mx_r0603
mx_r0603 1%
1%
1 2
I
I
PR21
PR21 1KOhm
1KOhm
mx_r0603
mx_r0603 1%
1%
1 2
2
VRM_VCC5_A
12
I
I
PR38
PR38 33K
33K
1%
1%
GND
2
1
12
I
I
PC1
PC1
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
12
I
I
PC5
PC5
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
12
I
I
PC10
PC10
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
12
I
I
PR3
PR3
5.6K
5.6K
1%
1%
I
I
PC2
PC2
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
1 2
12
I
I
PR9
PR9
5.6K
5.6K
1%
1%
I
I
PC8
PC8
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
1 2
12
I
I
PR15
PR15
5.6K
5.6K
1%
1%
I
I
PC11
PC11
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
1 2
PEGATRON DT-MB RESTRICTED SECRET
IPM41-D3
IPM41-D3
IPM41-D3
GND
GND
GND
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
1
VRM_BOOT1_C [47]
VRM_UGATE1_D [47]
VRM_PHASE1_C [47]
VRM_LGATE1_D [47]
ISEN1+_A [47]
ISEN1-_A [47]
VRM_BOOT2_C [47]
VRM_UGATE2_D [47]
VRM_PHASE2_C [47]
VRM_LGATE2_D [47]
ISEN2+_A [47]
ISEN2-_A [47]
VRM_PWM3_A [48]
ISEN3+_A [48]
ISEN3-_A [48]
VCORE CONTROLLER
VCORE CONTROLLER
VCORE CONTROLLER
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
46 55Thursday, July 09, 2009
46 55Thursday, July 09, 2009
46 55Thursday, July 09, 2009
Rev
Rev
Rev
1.00
1.00
1.00
5
4
3
2
1
+12V_CPU
I
I
PL1
PL1
0.4UH/25A
0.4UH/25A
21
12
I
I
PCB3
D D
I
I
PC26
I
I
I
PD1
PD1 BAV70WPT
BAV70WPT
1
3
2
VRM_BOOT1_C[46]
VRM_UGATE1_D[ 46] VRM_PHASE1_C[46]
VRM_LGATE1_D[46]
C C
I
I
PD2
PD2 BAV70WPT
BAV70WPT
1
3
2
B B
VRM_BOOT2_C[46]
VRM_UGATE2_D[ 46] VRM_PHASE2_C[46]
VRM_LGATE2_D[46]
I
PR44
PR44 1
1
mx_r0603
mx_r0603
1 2
I
I
PR48
PR48 1
1
mx_r0603
mx_r0603
1 2
VRM_BOOT1_RC_C
VRM_BOOT2_RC_C
PC26
0.1UF/16V
0.1UF/16V
mx_c0603
mx_c0603 X7R 10%
X7R 10%
1 2
I
I
PC29
PC29
0.1UF/16V
0.1UF/16V
mx_c0603
mx_c0603 X7R 10%
X7R 10%
1 2
NOBOM
NOBOM
PR45
PR45 0
0
mx_r0603_short
mx_r0603_short
1 2
NOBOM
NOBOM
PR49
PR49 0
0
mx_r0603_short
mx_r0603_short
1 2
2
2
I
I
D
D
PQ27
PQ27 AOD452
AOD452
1
VRM_UGR1_D
12
I
I
PR46
PR46
8.2K
8.2K
2
2
I
I
D
D
PQ2
PQ2 AOD472
AOD472
1
1
G
G
S
S
3
3
GND GND GND
VRM_UGR2_D
12
I
I
PR50
PR50
8.2K
8.2K
2
2
I
I
D
D
PQ5
PQ5 AOD472
AOD472
1
1
G
G
S
S
3
3
1
G
G
S
S
3
3
2
2
I
I
D
D
PQ3
PQ3 AOD472
AOD472
1
1
G
G
S
S
3
3
2
2
I
I
D
D
PQ28
PQ28 AOD452
AOD452
1
1
G
G
S
S
3
3
2
2
I
I
D
D
PQ6
PQ6 AOD472
AOD472
1
1
G
G
S
S
3
3
PCB3
4.7UF/16V
4.7UF/16V
mx_c1206
mx_c1206 X7R 20%
X7R 20%
GND GND GND GND
12
I
I
PC27
PC27 4700PF/50V
4700PF/50V
mx_c0603
mx_c0603 X7R 10%
X7R 10%
VRM_SN1_C
I
I
PR47
PR47 1 Ohm
1 Ohm
mx_r1206
mx_r1206
1 2
+12V_VCORE_VIN
12
I
I
PCB4
PCB4
4.7UF/16V
4.7UF/16V
mx_c1206
mx_c1206 X7R 20%
X7R 20%
GND
12
I
I
PC30
PC30 4700PF/50V
4700PF/50V
mx_c0603
mx_c0603 X7R 10%
X7R 10%
VRM_SN2_C
I
I
PR51
PR51 1 Ohm
1 Ohm
mx_r1206
mx_r1206
1 2
GNDGNDGND
2009/04/30 delete PCE2
GND
GND
12
NI
NI
PC28
PC28 680PF/50V
680PF/50V
X7R 10%
X7R 10%
ISEN1+_A[46]
ISEN1-_A[46]
12
NI
NI
PC31
PC31 680PF/50V
680PF/50V
X7R 10%
X7R 10%
ISEN2+_A[46]
ISEN2-_A[46]
12
I
I
+
+
PCE3
PCE3 270UF/16V
270UF/16V
12
+
+
NOBOM
NOBOM
PJP1
PJP1 SHORTPIN
SHORTPIN
1 2
NOBOM
NOBOM
PJP4
PJP4 SHORTPIN
SHORTPIN
1 2
+12V_VCORE_VIN
I
I
PCE4
PCE4 270UF/16V
270UF/16V
I
I
PL2
PL2
0.3UH/48A
0.3UH/48A
I
I
PL3
PL3
0.3UH/48A
0.3UH/48A
12
I
I
+
+
PCE5
PCE5 270UF/16V
270UF/16V
21
21
NOBOM
NOBOM
PJP2
PJP2 SHORTPIN
SHORTPIN
1 2
NOBOM
NOBOM
PJP3
PJP3 SHORTPIN
SHORTPIN
1 2
+VCORE
A A
PEGATRON DT-MB RESTRICTED SECRET
VCORE DRIVER-1
VCORE DRIVER-1
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
5
4
3
2
IPM41-D3
IPM41-D3
IPM41-D3
Engineer:
VCORE DRIVER-1
1
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
47 55Thursday, July 09, 2009
47 55Thursday, July 09, 2009
47 55Thursday, July 09, 2009
1.00
1.00
1.00
Rev
Rev
Rev
5
I
I
PD3
PD3 BAV70WPT
BAV70WPT
1
2
D D
1 2
C C
I
I
PR58
PR58
4.7
4.7
mx_r0603
mx_r0603
3
I
I
PR52
PR52 1
1
mx_r0603
mx_r0603
1 2
VRM_PWM3_A[46]
VRM_BOOT3_RC_C
VRM_VCC5_A
VRM_BOOT3_C
DRI_VCC3_B
12
I
I
PC34
PC34
0.47UF/16V
0.47UF/16V
mx_c0603
mx_c0603 X7R 10%
X7R 10%
GND GND
I
I
PU2
PU2 RT9618PS
RT9618PS
1
BOOT
2
PWM
3
OD# VCC4LGATE
4
UGATE PHASE
PGND
I
I
PC32
PC32
0.1UF/16V
0.1UF/16V
mx_c0603
mx_c0603 X7R 10%
X7R 10%
1 2
3
+12V_VCORE_VIN+12V_CPU
NOBOM
NOBOM
PR53
PR53 0
0
mx_r0603_short
mx_r0603_short
1 2
VRM_UG3_D
8
VRM_PHASE3_C
7 6
VRM_LG3_D
5
VRM_UGR3_D
12
I
I
PR60
PR60
8.2K
8.2K
2
2
I
I
D
D
PQ8
PQ8 AOD472
AOD472
1
1
G
G
S
S
3
3
GND GND GND
2
2
I
I
D
D
PQ30
PQ30 AOD452
AOD452
1
1
G
G
S
S
3
3
12
I
I
PC33
PC33 4700PF/50V
4700PF/50V
mx_c0603
mx_c0603 X7R 10%
X7R 10%
2
2
I
I
D
D
PQ9
PQ9 AOD472
AOD472
1
1
G
G
S
S
3
3
VRM_SN3_C
I
I
PR59
PR59 1 Ohm
1 Ohm
mx_r1206
mx_r1206
1 2
GND
12
I
I
PCB5
PCB5
4.7UF/16V
4.7UF/16V
mx_c1206
mx_c1206 X7R 20%
X7R 20%
2
I
I
PL4
PL4
0.3UH/48A
0.3UH/48A
12
NI
NI
PC35
PC35 680PF/50V
680PF/50V
X7R 10%
X7R 10%
GND
ISEN3+_A[46]
ISEN3-_A[46]
NOBOM
NOBOM
PJP5
PJP5 SHORTPIN
SHORTPIN
1 2
+VCORE
21
1
NOBOM
NOBOM
PJP6
PJP6 SHORTPIN
SHORTPIN
1 2
+VCORE
12
NI
NI
+
+
PCE6
PCE6 220UF/2V
220UF/2V
BOTTOM
GND
+VCORE
12
BOTTOM
I
I
+
+
PCE7
PCE7
B B
A A
12
NI
NI
+
+
PCE9
PCE9 220UF/2V
220UF/2V
BOTTOM
BOTTOM
090515 move from 2009/5/11_D PCE31
12
12
12
I
I
+
+
PCE8
PCE8
820UF/2.5V
820UF/2.5V
820UF/2.5V
820UF/2.5V
5
+
+
I
I
PCE10
PCE10
820UF/2.5V
820UF/2.5V
I
I
+
+
PCE11
PCE11
820UF/2.5V
820UF/2.5V
12
+
+
I
I
PCE12
PCE12
820UF/2.5V
820UF/2.5V
12
+
+
NI
NI
PCE31
PCE31
820UF/2.5V
820UF/2.5V
+VCORE
I
I
PCB8
PCB8 22UF/6.3V
22UF/6.3V
mx_c1206
mx_c1206 X5R 10%
X5R 10%
12
I
I
PCB9
PCB9 22UF/6.3V
22UF/6.3V
mx_c1206
mx_c1206 X5R 10%
X5R 10%
GNDGND
12
I
I
PCB6
PCB6 22UF/6.3V
22UF/6.3V
mx_c1206
mx_c1206 X5R 10%
X5R 10%
12
I
I
PCB7
PCB7 22UF/6.3V
22UF/6.3V
mx_c1206
mx_c1206 X5R 10%
X5R 10%
12
12
+CPU VCORE OUTPUT CAPs
4
I
I
PCB10
PCB10 22UF/6.3V
22UF/6.3V
mx_c1206
mx_c1206 X5R 10%
X5R 10%
3
12
I
I
PCB11
PCB11 22UF/6.3V
22UF/6.3V
mx_c1206
mx_c1206 X5R 10%
X5R 10%
12
I
I
PCB12
PCB12 22UF/6.3V
22UF/6.3V
mx_c1206
mx_c1206 X5R 10%
X5R 10%
12
I
I
PCB13
PCB13 22UF/6.3V
22UF/6.3V
mx_c1206
mx_c1206 X5R 10%
X5R 10%
12
I
I
PCB14
PCB14 22UF/6.3V
22UF/6.3V
mx_c1206
mx_c1206 X5R 10%
X5R 10%
12
I
I
PCB15
PCB15 22UF/6.3V
22UF/6.3V
mx_c1206
mx_c1206 X5R 10%
X5R 10%
12
I
I
PCB16
PCB16 22UF/6.3V
22UF/6.3V
mx_c1206
mx_c1206 X5R 10%
X5R 10%
2
12
I
I
PCB17
PCB17 22UF/6.3V
22UF/6.3V
mx_c1206
mx_c1206 X5R 10%
X5R 10%
12
I
I
PCB18
PCB18 22UF/6.3V
22UF/6.3V
mx_c1206
mx_c1206 X5R 10%
X5R 10%
12
I
I
PCB19
PCB19 22UF/6.3V
22UF/6.3V
mx_c1206
mx_c1206 X5R 10%
X5R 10%
12
I
I
PCB20
PCB20 22UF/6.3V
22UF/6.3V
mx_c1206
mx_c1206 X5R 10%
X5R 10%
12
I
I
PCB21
PCB21 22UF/6.3V
22UF/6.3V
mx_c1206
mx_c1206 X5R 10%
X5R 10%
12
I
I
PCB22
PCB22 22UF/6.3V
22UF/6.3V
mx_c1206
mx_c1206 X5R 10%
X5R 10%
PEGATRON DT-MB RESTRICTED SECRET
VCORE DRIVER-2
VCORE DRIVER-2
1
VCORE DRIVER-2
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
48 55Thursday, July 09, 2009
48 55Thursday, July 09, 2009
48 55Thursday, July 09, 2009
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
IPM41-D3
IPM41-D3
IPM41-D3
Engineer:
12
I
I
PCB23
PCB23 22UF/6.3V
22UF/6.3V
mx_c1206
mx_c1206 X5R 10%
X5R 10%
1.00
1.00
1.00
Rev
Rev
Rev
5
4
3
2
1
+1P5V_ICH (2A)
+1P5V_DUAL+12V
For G41 DDR3 Platform
+1P5V_DUAL → +0P75V_VTT_DDR (1A)
D D
C C
I
I
PR907
PR907
8.2KOHM
8.2KOHM
+1P5V_ICH_GATE_A
1 2
1
1
G
G
12
NI
NI
PCB901
PCB901
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND GND GND
12
I
I
PC903
PC903 10UF/6.3V
10UF/6.3V
mx_c0805
mx_c0805 X5R 10%
X5R 10%
GND
2
2
I
I
D
D
PQ29
PQ29 AOD472
AOD472
S
S
3
3
12
NI
NI
+
+
PCE714
PCE714 680UF/4V
680UF/4V
+1P5V_ICH
12
I
I
PC902
PC902 10UF/6.3V
10UF/6.3V
mx_c0805
mx_c0805 X5R 10%
X5R 10%
I
I
PD902
PD902 BAT54CW
BAT54CW
3
2
1
+5VSB → +3P3VSB (1.5A)
+5VSB → +3P3VSB (1.5A)
+5VSB → +3P3VSB (1.5A)+5VSB → +3P3VSB (1.5A) Eup 1W
Eup 1W
Eup 1WEup 1W
+1P1V_FSB_VTT
12
NI
NI
+
+
PCE15
PCE15 330UF/6.3V
330UF/6.3V
GND GND GND GND GND GND GND GND
2009/04/30 PCE16 from 820uF change to 330uF
12
I
I
PC81
PC81 10UF/6.3V
10UF/6.3V
mx_c0805
mx_c0805 X5R 10%
X5R 10%
12
I
I
PC80
PC80 10UF/6.3V
10UF/6.3V
mx_c0805
mx_c0805 X5R 10%
X5R 10%
12
I
I
PCB29
PCB29
0.1UF/16V
0.1UF/16V
mx_c0603
mx_c0603 X7R 10%
X7R 10%
I
I
PU4
PU4 RT9045GSP
RT9045GSP
1
VIN
2
GND1
3
REFEN VOUT4NC1
GND2
NC3 NC2
VCNTL
+5V+1P5V_DUAL +1P5V_DUAL+0P75V_VTT_DDR
12
I
I
PR762
PR762 0
0
mx_r0603
9 8 7 6 5
mx_r0603
12
I
I
PCB28
PCB28 1UF/16V
1UF/16V
mx_c0603
mx_c0603 X7R 10%
X7R 10%
I
I
PR57
PR57 100KOHM
100KOHM
1%
1%
+0P75V_REF_A
I
I
PR105
PR105 100KOHM
100KOHM
1%
1%
12
I
I
PC37
PC37 1000PF/50V
1000PF/50V
X7R 10%
X7R 10%
+5VSB ==> +3P3VSB (1.5A)
NO BOM
NO BOM
PU302
PU302 3MM_OPEN_5MIL
3MM_OPEN_5MIL
+5VSB
B B
A A
112
2
12
NI
NI
PR65
PR65 100KOHM
100KOHM
1%
NI
NI
PC305
PC305
0.01UF/25V
0.01UF/25V
X7R 10%
X7R 10%
+3P3VSB_BST_C +3P3VSB_SS_A
12
+3P3VSB_VCC_C +3P3VSB_SW_C
NI
NI
PR56
PR56
1.8KOHM
NI
NI
PC79
PC79 10UF/6.3V
10UF/6.3V
mx_c1206
mx_c1206 X5R 10%
X5R 10%
12
NI
NI
PC72
PC72 10UF/6.3V
10UF/6.3V
mx_c1206
mx_c1206 X5R 10%
X5R 10%
GND GNDGND GND GND GND GND
5
12
1.8KOHM
1%
1%
NI
NI
PU303
PU303 MP1482-C165DS-LF-Z
MP1482-C165DS-LF-Z
1
BS
2
IN
3
SW
4
GND1
+3P3VSB_COMP1_A
12
COMP
SS EN
FB
4
8
+3P3VSB_EN_A
7
+3P3VSB_COMP_A
6
+3P3VSB_FB_A
5
NI
NI
PC76
PC76
0.018UF/16V
0.018UF/16V
X7R 10%
X7R 10%
NI
NI
PC77
PC77 100PF/50V
100PF/50V
NPO 5%
NPO 5%
12
12
1%
12
NI
NI
PR64
PR64 100KOHM
100KOHM
1%
1%
12
NI
NI
PC78
PC78
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
1 2
GND
NI
NI
PD21
PD21 SSM24LPT
SSM24LPT
12
NI
NI
PC75
PC75
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
NI
NI
PL9
PL9 10UH
10UH
Irat=4A
Irat=4A
21
12
NI
NI
PR55
PR55
26.1KOHM
26.1KOHM
1%
1%
1 2
NI
NI
PC74
PC74 1000PF/50V
1000PF/50V
X7R 10%
X7R 10%
NI
NI
PR54
PR54 10KOhm
10KOhm
1%
1%
1 2
3
12
GND GND
+3P3VSB_FB1_A +3P3VSB_FB2_A
NI
NI
PC73
PC73 10UF/6.3V
10UF/6.3V
mx_c1206
mx_c1206 X5R 10%
X5R 10%
+3P3VSB
12
NI
NI
PC47
PC47 10UF/6.3V
10UF/6.3V
mx_c1206
mx_c1206 X5R 10%
X5R 10%
1 2
NI
NI
PR62
PR62 0 Ohm
0 Ohm
mx_r0603
mx_r0603
NOBOM
NOBOM
PJP15
PJP15 SHORTPIN
SHORTPIN
2
+5VSB
12
12
GND
I
I
PCB30
PCB30
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
I
I
PQ10
PQ10 LIN REG, 1085
LIN REG, 1085
3
VIN
GND
VOUT
ADJ
1
12
NI
NI
PC38
PC38
0.1UF/16V
0.1UF/16V
2
3P3VSB_ADJ
GND
12
12
I
I
PR61
PR61 120
120
1%
1%
I
I
PR63
PR63 200
200
1%
1%
I
I
PCE16
PCE16
820UF/6.3V
820UF/6.3V
GND
+3P3VSB
12
I
I
+
+
PCB31
PCB31
10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10% mx_c0805
mx_c0805
12
GND
PEGATRON DT-MB RESTRICTED SECRET
+0P9V_VTT_DDR_LDO
+0P9V_VTT_DDR_LDO
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
IPM41-D3
IPM41-D3
IPM41-D3
Engineer:
+0P9V_VTT_DDR_LDO
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
1
Rev
Rev
Rev
1.00G
1.00G
49 55Thursday, July 09, 2009
49 55Thursday, July 09, 2009
49 55Thursday, July 09, 2009
1.00G
5
4
3
2
1
+1P5V_DUAL ==> +1P1V_FSB_VTT (1.5A) Fixed in 1.2V
change to NI in 9/9
D D
+3P3VSB
1
1
G
G
NI
NI
PC42
PC42 2200PF/50V
2200PF/50V
X7R 10%
X7R 10%
NI
NI
PC43
PC43 2200PF/50V
2200PF/50V
X7R 10%
X7R 10%
+1P1V_EN_A
3
3
D
D
S
S
2
2
GND
+12V
+5VSB
B
1
B
1
GND
+5V_DUAL_MAIN
+5V_DUAL_AUX
12
NI
NI
PR70
PR70 1K
1K
VTT_SELECT#
3
3
C
C
NI
NI
PQ14
PQ14 PMBS3904
PMBS3904
E
E 2
2
12
GND
12
GND
+1P1V_FSB_VTT
12
NI
NI
PR72
PR72 62
62
NI
NI
PR75
PR75 1K
1K
VTT_SELECT[7]
C C
B B
H--->1.206 L--->1.101
1 2
R_VTT_SEL
I
I
PR78
PR78 1K
1K
1 2
1
S0/S1
S3
S0/S5
0
I
I
PR80
PR80 1K
1K
+3VSBSW[38]
A A
5
1 2
NI
NI
PQ13
PQ13 2N7002
2N7002
1 2
1 2
4
1 2
I
I
PR77
PR77
8.2K
8.2K
I
I
PR79
PR79
8.2K
8.2K
NI
NI
PR71
PR71
68.1K
68.1K
1%
1%
B
1
B
1
GND
B
1
B
1
GND
+3P3VSB
12
I
I
PR68
PR68
17.4K
17.4K
1%
1%
12
I
I
PR73
PR73 10K
10K
1%
1%
+5V_DUAL_MAIN_GATE
3
3
C
C
I
I
PQ16
PQ16
E
E
PMBS3904
PMBS3904
2
2
+5V_DUAL_AUX_GATE
3
3
C
C
I
I
PQ19
PQ19 PMBS3904
PMBS3904
E
E 2
2
GNDGND
12
I
I
PCB36
PCB36
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
+5VSB
+1P1V_FSB_VTT_REF_A
+5V
G
G
1
1
G
G
1
1
+5V_DUAL.....A +5V_DUAL_USB_B......3A
3
3
S
S
I
I
PQ15
PQ15
AOD452
AOD452
D
D
2
2
3
3
D
D
I
I
PQ18
PQ18 NTR4502PT1G
NTR4502PT1G
S
S
2
2
I
I
PU6
PU6 LM358
LM358
A+
A+
3
8
VCC
VCC
+
+
1
A-
A-
AO
AO
2
-
-
B+
B+
5
+
+
BO
BO
7
B-
B-
4
6
-
-
GND
GND
+1P1V_FSB_VTT_FB_A
+5V_DUAL
12
+
+
NI
NI
PCE19
PCE19 820UF/6.3V
820UF/6.3V
GND
3
GND
+12V
12
I
I
PCB37
PCB37
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
+5V_DUAL_MAIN_GATE
+5V_DUAL_AUX_GATE
+1P1V_FSB_VTT_CON_A
12
12
NI
I
I
PC41
PC41 470PF/50V
470PF/50V
X7R 10%
X7R 10%
NI
PR74
PR74 10K
10K
1%
1%
+5VSB
+5V_DUAL_MAIN_GATE
6/18 modify
2
+1P5V_DUAL
2
2
D
D
AOD452
AOD452
1
1
PQ12
PQ12
I
I
G
G
S
S
3
3
N
N
S2G2D2
S2G2D2
P
P
+5V
8
7
D1
D1
6
54
D2
D2
+1P1V_FSB_VTT
12
+
+
I
I
PCE17
PCE17 1800UF/6.3V
1800UF/6.3V
GND
+5V_DUAL_USB+5V
9/9 DEL
I
I
PR76
PR76 1K
1K
1%
1%
+5V_DUAL
1
1
G
G
12
3
3
D
D
S
S
2
2
I
I
PQ17
PQ17 APM9932CKC
APM9932CKC
1
S1 D1
S1 D1
2
G1
G1
3
I
I
Q10
Q10 AP2306GN
AP2306GN
PEGATRON DT-MB RESTRICTED SECRET
+1P1V_FSB_VTT_LDO
+1P1V_FSB_VTT_LDO
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
IPM41-D3
IPM41-D3
IPM41-D3
Engineer:
+1P1V_FSB_VTT_LDO
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
1
Rev
Rev
Rev
1.00G
1.00G
50 55Thursday, July 09, 2009
50 55Thursday, July 09, 2009
50 55Thursday, July 09, 2009
1.00G
5
4
3
2
1
PSI CIRCUIT
D D
NI
NI
PR81
PR81
CPURESET#[6,9,10]
NI
NI
PR84
C C
CPURESET#[6,9,10]
PR84
1 2
1K
1K
1 2
5.1K
5.1K
CPURST_PSI_PQ902
PMBS3904
PMBS3904
8/20 modify to NI
+VTT_OUT_L
NI
NI
PQ22
PQ22
B
1
B
1
CPURST_PSI_PQ901
12
NI
NI
PR83
PR83 1K
1K
CPURST_PSI_PQ903
3
3
C
C
E
E 2
2
GND
GND
12
NI
NI
PC44
PC44 10UF/6.3V
10UF/6.3V
X5R 10%
X5R 10% mx_c0805
mx_c0805
1
1
PMBS3904
PMBS3904
NI
NI
PQ21
PQ21
B
B
GND
C
C
3
3
E
E 2
2
1
1
PMBS3904
PMBS3904
NI
NI
PQ20
PQ20
B
B
3
3 C
C
E
E 2
2
07/15 modify
12
NI
NI
PR82
PR82
0
0
VCORE_PSI [46]
CPU_PSI [7]
VRMPWRGD CIRCUIT
+3P3V
B B
SRN12A
8.2KOHM
8.2KOHM
I
I
SRN12B
SRN12B
SRN12A
12
GND
VRMPWRGD[7,46]
A A
5
1 2
3 4
8.2KOHM
8.2KOHM
I
I
4
PMBS3904
PMBS3904
NI
NI
C44
C44
0.1UF/16V
0.1UF/16V
+5VSB
SRN12C
SRN12C
8.2KOHM
8.2KOHM
I
I
5 6
3
3
PQ31
PQ31
C
C
B
1
B
1
I
I
E
E 2
2
GND GND
SRN12D
SRN12D
8.2KOHM
8.2KOHM
I
I
7 8
VRMPWRGD_ICH [5,21]
3
3
D
D
VQ3
VQ3 2N7002
2N7002
1
1
I
I
G
G
S
S
2
2
PEGATRON DT-MB RESTRICTED SECRET
Title :
Title :
Title :
PSI CIRCUIT
PSI CIRCUIT
PSI CIRCUIT
Wayne Hsieh
Wayne Hsieh
1
Wayne Hsieh
51 55Thursday, July 09, 2009
51 55Thursday, July 09, 2009
51 55Thursday, July 09, 2009
Rev
Rev
Rev
1.00G
1.00G
1.00G
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
3
2
IPM41-D3
IPM41-D3
IPM41-D3
Engineer:
5
D D
+5V_DUAL
C C
1P5V_DUAL_BST_C
B B
1P5V_DUAL_HG_D
1P5V_DUAL_LG_D
GND GND GND
1 2 3 4
+12V
I
I
PD7
PD7 BAT54CW
BAT54CW
3
I
I
PC49
PC49
0.1UF/16V
0.1UF/16V
mx_c0603
mx_c0603 X7R 10%
X7R 10%
1 2
I
I
PU7
PU7 APW7120
APW7120
BOOT UGATE GND LGATE
PHASE OCSET
VCC
FB
2
1
1
2
I
I
PD6
PD6 BAT54CW
BAT54CW
8 7 6 5
1P5V_DUAL_PWM_C
3
1P5V_DUAL_PHASE_C 1P5V_DUAL_OCSET_A 1P5V_DUAL_FB_A 1P5V_DUAL_VCC_C
12
I
I
PR87
PR87
4.7
4.7
mx_r0603
mx_r0603
12
I
I
PC50
PC50
0.47UF/16V
0.47UF/16V
mx_c0603
mx_c0603 X7R 10%
X7R 10%
4
+5V_DUAL
12
NI
NI
PCB38
PCB38
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND GND GND
1 2
I
I
PL5
PL5 1UH
1UH
Irat=14A
Irat=14A
21
VP
VP
PR28
PR28 0 Ohm
0 Ohm
mx_r0603
mx_r0603
1 2
1P5V_DUAL_OCSET1_A
OCP=26A
PR90
PR90 13KOHM
13KOHM
1%
1%
2009/04/30 PR24 from 22Kohm change to 18.2Kohm
I
I
12
PR92
PR92
2.1KOHM
2.1KOHM
1%
1%
I
I
+1P5V_DUAL_VIN
1P5V_DUAL_HGR_D
12
I
I
PR86
PR86
8.2K
8.2K
NOBOM
NOBOM
PJP13
PJP13 SHORTPIN
SHORTPIN
12
NI
NI
PR101
PR101
8.2K
8.2K
12
PR91
PR91 2KOhm
2KOhm
1%
1%
I
I
1 2
NI
NI
PC51
PC51
0.47UF/16V
0.47UF/16V
mx_c0603
mx_c0603 X7R 10%
X7R 10%
12
3
2
2
1
1
G
G
3
3
2
2
1
1
G
G
3
3
I
I
D
D
PQ23
PQ23 AOD452
AOD452
S
S
I
I
D
D
PQ24
PQ24 AOD452
AOD452
Rds(on)=14m ohm
Rds(on)=14m ohm
S
S
1P5V_DUAL_FB1_A
Irms=5.86A
12
I
I
PC45
PC45 10UF/6.3V
10UF/6.3V
mx_c0805
mx_c0805 X5R 10%
X5R 10%
12
I
I
PC46
PC46 4700PF/50V
4700PF/50V
mx_c0603
mx_c0603 X7R 10%
X7R 10%
+1P5V_DUAL_SN_C
12
I
I
PR89
PR89 1
1
mx_r1206
mx_r1206
GNDGNDGND
2
12
I
I
+
+
PCE20
PCE20 560UF/6.3V
560UF/6.3V
12
NI
NI
PC66
PC66 680PF/50V
680PF/50V
X7R 10%
X7R 10%
GND GND GND GND
+5V_DUAL → +1P5V_DUAL (12A)
I
I
PL6
PL6
1.2UH
1.2UH
Irat=29A
Irat=29A
I
I
PR6
PR6 0 Ohm
0 Ohm
mx_r0603
mx_r0603
1 2
21
12
I
I
PC67
PC67 10UF/6.3V
10UF/6.3V
mx_c0805
mx_c0805 X5R 10%
X5R 10%
I=3.2A / V=18.9mV
12
I
I
+
+
PCE33
PCE33 820UF/2.5V
820UF/2.5V
ESR=7m
ESR=7m
1
+1P5V_DUAL_FB2_A
12
I
I
+
+
PCE29
PCE29 820UF/6.3V
820UF/6.3V
ESR=36m
ESR=36m
+1P5V_DUAL
12
NOBOM
NOBOM
PJP14
PJP14 SHORTPIN
SHORTPIN
A A
PEGATRON DT-MB RESTRICTED SECRET
+1P8V_DUAL_SW
+1P8V_DUAL_SW
1
+1P8V_DUAL_SW
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
52 55Thursday, July 09, 2009
52 55Thursday, July 09, 2009
52 55Thursday, July 09, 2009
Rev
Rev
Rev
1.00
1.00
1.00
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
5
4
3
2
IPM41-D3
IPM41-D3
IPM41-D3
Engineer:
5
4
3
2
1
+3P3V
D D
C C
+12V
12
I
I
PR95
PR95
4.7
I
I
PD8
PD8 BAT54CW
BAT54CW
1
3
2
I
I
PC56
PC56
0.1UF/16V
0.1UF/16V
mx_c0603
mx_c0603 X7R 10%
B B
1P1V_BST_C 1P1V_HG_D
GND
A A
X7R 10%
1 2
I
I
PU8
PU8 APW7120
APW7120
1
BOOT
PHASE
2
UGATE
OCSET
3
GND
4
LGATE
+3P3V +5VSB
12
NI
NI
PR39
PR39 1KOhm
1KOhm
SW1_PR39_A
5
1P1V_PHASE_C
8
1P1V_OCSET_A
7
1P1V_FB_A
6
FB
1P1V_VCC_C1P1V_LG_D
5
VCC
12
PR34
PR34 845OHM
845OHM
1%
1%
NI
NI
SW1_PR34_A
3
3
NI
NI
D
D
PQ1
PQ1 2N7002
2N7002
1
1
G
G
S
S
2
2
GND GND
4.7
mx_r0603
mx_r0603
12
I
I
PC57
PC57
0.47UF/16V
0.47UF/16V
mx_c0603
mx_c0603 X7R 10%
X7R 10%
B
1
B
1
3
3
NI
NI
C
C
PQ4
PQ4 PMBS3904
PMBS3904
E
E 2
2
12
NI
NI
PCB39
PCB39
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND GND GND
GNDGND
090511 Modified by Power team.
2009/05/04 Avoid 3P3V leakage issue.
4
I
I
PL7
PL7 1UH
1UH
Irat=14A
Irat=14A
VP
VP
PR26
PR26 0 Ohm
0 Ohm
mx_r0603
mx_r0603
1 2
1P1V_OCSET1_A
OCP=26A
I
I
PR93
PR93 13KOHM
13KOHM
1%
1%
1 2
12
I
I
PR100
PR100
1.96K
1.96K
1%
1%
12
I
I
PC69
PC69 10UF/6.3V
10UF/6.3V
mx_c0805
mx_c0805 X5R 10%
X5R 10%
12
I
I
PC53
PC53 4700PF/50V
4700PF/50V
mx_c0603
mx_c0603 X7R 10%
X7R 10%
+1P1V_SN_C
12
I
I
PR97
PR97 1
1
mx_r1206
mx_r1206
GNDGNDGND
Irms=5.74A
12
I
I
+
+
PCE25
PCE25 560UF/6.3V
560UF/6.3V
Irms=5700mA
Irms=5700mA
12
NI
NI
PC70
PC70 680PF/50V
680PF/50V
X7R 10%
X7R 10%
I
I
PL8
PL8
1.2UH
1.2UH
Irat=29A
Irat=29A
I
I
PR2
PR2 0 Ohm
0 Ohm
mx_r0603
mx_r0603
1 2
+3P3V → +1P1V_CORE (12A)
21
12
I
I
PC71
PC71 10UF/6.3V
10UF/6.3V
mx_c0805
mx_c0805 X5R 10%
X5R 10%
I=2A / V=12mV
12
I
I
+
+
PCE27
PCE27 820UF/2.5V
820UF/2.5V
ESR=7m
ESR=7m
12
+
+
GNDGNDGNDGND
I
I
PCE28
PCE28 820UF/6.3V
820UF/6.3V
ESR=36m
ESR=36m
1P1V_FB2_A
+1P1V_CORE
12
NOBOM
NOBOM
PJP10
PJP10 SHORTPIN
SHORTPIN
+1P1V_VIN
21
2
2
I
I
D
D
PQ25
PQ25 AOD452
AOD452
1
12
I
I
PR99
PR99 806
806
1%
1%
NI
NI
PC58
PC58
0.47UF/16V
0.47UF/16V
mx_c0603
mx_c0603 X7R 10%
X7R 10%
12
12
1
1
1
G
G
3
3
2
2
G
G
3
3
S
S
I
I
D
D
PQ26
PQ26 AOD452
AOD452
S
S
1P1V_FB1_A
1P1V_HG1_D
12
I
I
PR94
PR94
8.2K
8.2K
NOBOM
NOBOM
PJP9
PJP9 SHORTPIN
SHORTPIN
12
I
I
PR96
PR96
8.2K
8.2K
PEGATRON DT-MB RESTRICTED SECRET
+1P1V_CORE
+1P1V_CORE
1
+1P1V_CORE
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
53 55Thursday, July 09, 2009
53 55Thursday, July 09, 2009
53 55Thursday, July 09, 2009
Rev
Rev
Rev
1.00G
1.00G
1.00G
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Date: Sheet of
3
2
IPM41-D3
IPM41-D3
IPM41-D3
Engineer:
5
A
4
3
2
1
NI
NI
C62
C62
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
+1P1V_CORE
12
NI
NI
C57
C57
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
+1P5V_DUAL
12
NI
NI
C67
C67
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
7/8 EMI modify
12
GND
NI
NI
C58
C58
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
+1P5V_DUAL
12
I
I
C59
C59
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
8/27 modify
GND
+5VSB
12
GNDGND GND
NI
NI
C60
C60
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
+3P3V
12
12
C49
C49
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10% NI
NI
6/19 modify(near SB)
C50
C50
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10% NI
NI
12
C51
C51
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10% NI
NI
GND
12
C52
C52
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10% NI
NI
+5V
12
NI
NI
C53
C53
0.1UF/16V
AGND
0.1UF/16V
X7R 10%
X7R 10%
D D
12
NI
NI
C63
C63
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
12
NI
NI
C61
C61
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
12
NI
NI
C64
C64
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
+3P3V
12
NI
NI
C54
C54
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
12
NI
NI
C65
C65
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
8/27 modify
12
I
I
C55
C55
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
12
NI
NI
C66
C66
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
GND
12
I
I
C56
C56
0.1UF/16V
0.1UF/16V
X7R 10%
X7R 10%
12
C C
SPI Flash
SPI_+3VSB +3P3VSB
SPI BIOS ROM - 8Mbit
10/2 modify
B B
SPI_CS#[21] SPI_MISO[21]
SPI_MOSI[21]
SPI_CLK[21]
SPI_CS#_E16
1 2
I
I
F3R8
F3R8 15
15
SPI ROM Part Number: 05G001217000
SPI_+3VSB
12
I
I
F3R5
F3R5
8.2K
8.2K
R_SPI_MISO FWH_WP#
GND
I
I
FU2
FU2
1
CS#
2
SO
HOLD#
3
WP# GND4SI
IC_SCK_8P
IC_SCK_8P
10/06 modify
FU2_flash rom
FU2_flash rom
1
1
2
2
BIOS
BIOS
I
I
3
3
4 5
4 5
PM25LV040-100PCE
PM25LV040-100PCE
05G001217000
05G001217000
VCC
SCLK
SPI_+3VSB
8 7 6 5
8
8
7
7
6
6
12
GND
I
I
F3CB1
F3CB1
0.1UF/16V
0.1UF/16V
SPI_HOLD#
SPI_+3VSB
12
I
I
F3R6
F3R6
8.2K
8.2K
PEGATRON DT-MB RESTRICTED SECRET
Title :
Title :
Title :
Engineer:
Engineer:
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
IPM41-D3
IPM41-D3
IPM41-D3
Engineer:
SPI 4Mb
SPI 4Mb
SPI 4Mb
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
54 55Thursday, July 09, 2009
54 55Thursday, July 09, 2009
54 55Thursday, July 09, 2009
Rev
Rev
Rev
1.00G
1.00G
1.00G
A
5
4
3
2
1
External RTC Circuitry CLEAR CMOS
+3P3VSB
D D
I
I
BATT1
BATT1
3V/220mAh
3V/220mAh
KTS
KTS
LITHIUM BATT
LITHIUM BATT
CR2032
CR2032
BAT R303_D8
1 2
I
I
R33
R33 1K
1K
1%
XBT2
XBT2
BATT_HOLDER
BATT_HOLDER
I
I
1%
12
GND
1
2
BAT54CW
BAT54CW
Battery Socket
I
I
D20
D20
BATT_DUAL
3
SW50
SW50
1 2 3
HEADER_1X3P
HEADER_1X3P
I
I
8/27 modify
1 2
GND GND GND
R35
R35 1KOhm
1KOhm
5%
5% I
I
+BATT
1 2
12
I
I
C18
C18
4.7UF/6.3V
4.7UF/6.3V
X5R 10%
X5R 10% mx_c0805
mx_c0805
I
I
R34
R34
20K
20K
CMOS DATA
1-2
Default
1%
1%
12
I
I
C19
C19 1UF/10V
1UF/10V
mx_c0603
mx_c0603
6/21 modify
RTCRST# [21]
2-3 CLEAR
I
I
SW50:12
SW50:12
MINI_JUMPER
MINI_JUMPER
8/21 modify to 12
SPEAKER
C C
SIO_BEEP[38]
SPKR[21]
B B
+3P3V
+5V
I=5/(100+40)=35.7mA
I
SPKR_B
I
R36
R36
1 2
100
100
mx_r0805
mx_r0805
Q9
Q9
PMBS3904
PMBS3904
1
1
P7
BUZZ SPKR_O
I
I
3
3
C
C
B
B
E
E 2
2
GND
P7
1 2
AC_1205G
AC_1205G
I
I
12
GND
NI
NI
CB99
CB99
0.1UF/16V
0.1UF/16V
Max 40mA 40Ohm
R39
R39 1KOhm
1KOhm
I
5%
5%
R38
5%IR38
1 2
5%
I
I
1KOhm
1KOhm
12
I
R37
5%IR37
5%
1KOhm
1KOhm
12
SB_PWR
+5VSB
GND
I
I
R18
R18 300 OHM
300 OHM
5%
5%
1 2
12
+
+
SB_PWR
SB_PWR
GREEN
GREEN
I
I
NOBOM
NOBOM
NOBOM
NOBOM
H1
H1 SCREWHOLE_160_HP
SCREWHOLE_160_HP
1
GND1
2
GND2
3
GND3
4
GND4
GND GND GND GND GND GND GND GND AGND AGND
A A
GND8 GND7 GND6 GND5
9
NC
8 7 6 5
NOBOM
NOBOM
H3
H3 SCREWHOLE_160_HP
SCREWHOLE_160_HP
1
GND1 GND2 GND3 GND4
GND8 GND7 GND6 GND5
NC
2 3 4
9 8 7 6 5
AGND AGND
NOBOM
H4
H4 SCREWHOLE_160_HP
SCREWHOLE_160_HP
1
GND1 GND2 GND3 GND4
GND8 GND7 GND6 GND5
NC
2 3 4
9 8 7 6 5
NOBOM
H5
H5 SCREWHOLE_160_HP
SCREWHOLE_160_HP
1
GND1 GND2 GND3 GND4
GND8 GND7 GND6 GND5
NC
2 3 4
9 8 7 6 5
NOBOM
NOBOM
H7
H7 SCREWHOLE_160_HP
SCREWHOLE_160_HP
1
GND1 GND2 GND3 GND4
GND8 GND7 GND6 GND5
NC
2 3 4
NOBOM
NOBOM
H6
H6 SCREWHOLE_160_HP
SCREWHOLE_160_HP
9 8 7 6 5
AGND
1
GND1
2
GND2
3
GND3
4
GND4
GND8 GND7 GND6 GND5
9
NC
8 7 6 5
PEGATRON DT-MB RESTRICTED SECRET
Title :
Title :
Title :
RTC / CMOS / SPKR
RTC / CMOS / SPKR
ONLY FOR SCREW HOLE
5
4
3
2
PEGATRON CORP.
PEGATRON CORP.
PEGATRON CORP.
Size Project Name
Size Project Name
Size Project Name
A3
A3
A3
Engineer:
Engineer:
Engineer:
IPM41-D3
IPM41-D3
IPM41-D3
RTC / CMOS / SPKR
Wayne Hsieh
Wayne Hsieh
Wayne Hsieh
55 55Thursday, July 09, 2009
55 55Thursday, July 09, 2009
1
55 55Thursday, July 09, 2009
Rev
Rev
Rev
1.00G
1.00G
1.00G
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