PEGATRON IPISB-SB Schematics

5

IPISB-SB

Revision: 1.00

PAGE

01
02
03

D D

04
05
06
07
08
09
10~15
16
17 DDR3 CHANNEL A
18
19
20
21~29
30

C C

31
32
33
34
35
36
37
38
39
40
41
42
43 CODEC ALC269Q
44

B B

45
46
47
48
49
50
51
52
53
54
55
56
57
58
59

A A

60
61
62
63
64~66
67

BLOCK DIAGRAM
CHANGE HISTORY - 1
CHANGE HISTORY - 2
CHANGE HISTORY - 3
CLCOK DISTRIBUTION
SIGNAL&RESET MAP
POWER FLOW
POWER DISTRIBUTION
POWER SEQUENCE
Sandy Bridge LGA-1155
PLTRST_CPU#

DDR3 CHANNEL B
DDR3 TERMINATION A&B
XXXXX
Cougar Point Q67
AMT POWER OK
PCH_DPWROK & SUS_ACK#
DEBUG VGA PORT
PANEL CONTROL
eDP TO LVDS
LVDS TO PANEL
WLAN
LEWISVILLE 82579LM
RJ45
FRONT PANEL
SCREW HOLE
WEBCAM & MIC
CARD READER

COM HEADER
AUDIO JACK
TPM
SIDE USB
REAR USB
SATA CONN
SYSTEM FAN
SM BUS & SPI ROM
19V IN
+3VA,+5VA,+393V_MINI
+1P5V_DUAL,+1P5V
+VTT_DDR&+1P5V_DUAL_EN +3P3VSB,+5VSB
+19V,+5V,+3P3V
CURRENT METER & DEBUG LED
+5V_DUAL,+3P3V_DUAL
+12V,+1P8V_SFR
+1P05V_PCH
+3P3V_LAN +3P3V_ME,+1P5VSB,+1P05V_ME
+1P05V_CPUIO,+0P925V_SA
+1P05V_CPUIO CAP
VCORE CONTROLLER
VCORE CAP

TITLE

5

4

USB x 4

USB x 2

Card Reader

68
69
70
71
72
73
74
75

4

XDP

Webcam

<Rear>

<Side>

AU6433-GBL

Intel 82579LM

10/100/1000

TRANSFORMER

RJ 45

WLAN
(MINICARD)

XDP

+V_AXG DRIVER
VCORE CAP
RTC/CMOS/SPKR
BIOS and LPC header
CPU XDP DEBUG CONNECTOR
PCH XDP DEBUG CONNECTOR
SIO11-1
SIO11-2

3

USB

480Mb/s

PCIE BUS

100MHz

PCIE BUS

3

Intel Processor

Sandy Bridge

LGA-1155 H2 Socket

65W

FDI LINK

DMI

INTEL

Cougar Point

PCH
Q67

942 Pin

27mm X 27mm

LPC BUS

33MHz

SIO11

SLB 9635 TT 1.2

2

LPC BUS

33MHz

TPM

2

Channel A

Channel B

TMDS(Port D)

SATA BUS

SPI

Azalia

1

Dual Channel DDR3 MEMORY x 2 Slots

DDR3 SO-DIMM 1333

DDR3 SO-DIMM 1333

Parade
PS8615

SATA 2.0
SATA 2.0

SPI FLASH

ALAZIA AUDIO
ALC269Q

Mic Headphone

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

LVDS

64Mb

IPISB-SB

IPISB-SB

IPISB-SB

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

1

23" LCD

SPK.
2W per Channel

Rear

Line Out

BLOCK DIAGRAM

BLOCK DIAGRAM

BLOCK DIAGRAM

Scott Chen

Scott Chen

Scott Chen

173Thursday, April 14, 2011

173Thursday, April 14, 2011

173Thursday, April 14, 2011

Rev

Rev

Rev

1.00

1.00

1.00

5

Schematics Change History

Observation Id: 720315 - VTT_DDR enable level too low
Change PR119 to 1Kohm,delete PQ44,PR164,PC248,PR379,add PC249/PQ78(NI)/PR419(NI).

4

3

2

1

Observation Id: 718229 - to meet the enterprise requirement (Common Reference Designators)
Observation Id: 717253 - Kona EVT2 system boards FDO jumper is labeled as IE80.
Observation Id: 717255 - Kona EVT2 system boards do not have silkscreen labels for
Bootblock and Bootblock Recovery.
Add mini jumper E15:12 E14:12

Observation Id: 715089 - remove the EDID_WP# feature and releated circuit.
Delete R37438, R37439; install R85

D D

R27, R28, R37401, R37402 change to RN4407 save layout space
Observation Id: 715087 - remove the FAB_ID[0:2] releated circuit and feature

Remove SR88, SR85, SR57; install SR64
Observation Id: 718216 - to meet Kona enterprise requirement (Connector Contact Plating)

Change DIMMA P/N to 12X2BBB2E011
Observation Id: 720317 - WLAN_DISABLE# pull-up is required

Delete Net:WLAN_DIS_SUS# (GPIO8) add SR112 for BRD_ID2
Delete Net:WLAN_DIS#,R37420;Add SR116 for GPIO33

Observation Id: 715248 - Need HP to define which GPIO of SIO11 will be for Brightness up/down and ODD
eject buttons.
Bright_up# change from PCH (GPIO31) to SIO11 (pin92) delete R37412
Bright_down# change from PCH(GPIO34) to SIO(pin95);delete R37411(internal debunce)
Install R7170, DELETE R37413

C C

Observation Id: 720320 - Audio BEEP support
AUDIO_DISABLE change from PCH(GPIO32) to using SIO11 control (pin69) add SR115
Uninstall R7247,PR418; Install PQ77,R7221,PQ76,PQ74,R7234
Uninstall R37562,R37561; Install PQ79,PR90,PR91,PQ80,PR88,PR89,PQ81,PR116
delete D3601; C3623 change to 2.2uF;
delete Q56,R3620,ER103,R3619;R1219 change to reserved 0.1uF cap.Add Q9346,R37563

Observation Id: 720321 - Support BEEP from codec in S5 state
Audio codec pin39 pin46 change from core power to
standby power(+5VSB);

Delete E69 E69:46 E69:35
Delete NET:Boot_BLK_WRITE_EN, R8826, R8824
P1 change to P5 Layout PB
P52 chnge to P54 Layout COMA
SU1 change to U4
U9382 Change to U5
LU1 Change to U10
AU3 Change to U13
IU1 Chnge to U19
U86 Change to U29
U8 Change to U31
U1 change to U40
HU1 change to XU1
Y3 (1.00) change to Y10 (1.01)
Y10 (1.00) change to Y3 (1.01)
LED2>CR1 Layout should use AUX
IE80>E1 Layout should use FDO BR8 move to pin 2 and change connecter to 2 pin ,
remove R37445,
delete mini jumpter IE80:23
E19>E14 Layout should use BB change to 2pin connector 12X602012B00 SR21
change to 8.2K
E18>E15 Layout should use BBR
JE16 >E16 Layout should use ROM RCVRY mini jumper change to E16:12
J90>E17 Layout should use LPC
CON3813>J9 Layout should use RJ45
P69>J69 Layout should use VGA
J11>J70 ; J12 >J71 ; CON3807>J90 ; CON3806>J91 ;CON3804>J81 ; CON3805>J82
Layout should use USB
J87>J72 Layout should use MIC

Observation Id: 716637 - Kona EVT2 system boards do not have a silkscreen for the four rear USB ports.
USB port 8 change to port12 and rename to USBN12,USBP12
Delete R7177,R7178(double PU)

B B

Observation Id: 720464 - HD LED didn't meet PCA spec.
Delete ODD_LED#,R37448,D8823,TD1
R82 change to Pull-high standby power, and change to 75ohm

Observation Id: 720468 - DDR reset measurement fail
Add R37564,SQ9,R37565,R37566,R37567,SQ10,SQ11,R37569,R37568
Reserved SR284,SR285; delete SR283
R37565 change to pull-high +3vsb

Observation Id: 720322 - Clock should follow PCA spec
Change CK_33M_TPM to PCH ball AN14
Change CK_33M_PCIFB to PCH ball AT12
Change CK_33M_DEBUG to PCH ball AT14

J89>J74 Layout should use OUT
J76>J75 Layout should use HDPH
J9>J103 Layout should use PWR
J61>J105 Layout should use X1PCIEXP11
PWR_CON1>P1 Layout should use PWR
CON3814>P6 AND CON3815 Layout should use SPKR
P30>P8 Layout should use CPUFAN
P29>P9 Layout should use CHFAN
P116>P160 Layout should use SATA PWR0
P114>P161 Layout should use SATA PWR1
DIMMA0>XMM1 Layout should use DIMM1
DIMMB0>XMM3 Layout should use DIMM3
XBT2>XBT1 Layout should use BATTERY
Install R4707 720317
SW51 change to 2pin connector 12X400120B20 change ref to E49 Layout should use PSWD
SW50 change to button type

Change CK_100M_PCHXDP to Port 7
Change CLK_PCIE_WLAN to port 6

A A

Observation Id: 720324 - SM-Link didn't connect to SIO11
Add smbus link from PCH to SIO
Reserved SR117
Install SR85, uninstall SR64
Reserved SR48 add SR96

5

4

3

2

<Variant Name>

<Variant Name>

<Variant Name>

PEGATRON DT-MB RESTRICTED SECRET

CHANGE HISTORY-1

CHANGE HISTORY-1

CHANGE HISTORY-1

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

IPISB-SB

IPISB-SB

IPISB-SB

Engineer:

Scott Chen

Scott Chen

Scott Chen

273Thursday, April 14, 2011

273Thursday, April 14, 2011

1

273Thursday, April 14, 2011

Rev

Rev

Rev

1.00

1.00

1.00

5

4

3

2

1

Schematics Change History

Observation Id: 720471 - Board ID should follow PCA spec
Delete SR108 change BRD_REV1 to use stand by power uninstall SR87 install SR91

Reduce power consumption in DSW mode

1).R364 change to 2K

2).PR22 change to 2K

3).Remove SR196, SR199, SR188, SR189, SR190

Observation Id: 720326 - Debug LED and Serial port didn't meet PCA spec
Change serial port solution

D D

delete Q8,R37407,R37408,Q15,R16
R8831,Q9348,CR7,R4819,R8830,CR6,Q9347,R4818,CR8,R8832,R4822,

Delete PR327,PR330 ,U9378 ,C9352 ,SR133 ,SR134 ,U9379,R37418, R37450, PC329, PQ506,R37449, PC328
delete ECA5

Q9349,R8833,CR10,Q9350,R4823 net SLP_A#,SLP_S5#,SLP_SUS#,SLP_LAN#
Add U7204 for Serial port function

Power modify

1).Add PR196,PC178

Observation Id: 720475 - GPIO should follow PCA spec
Reserved SR113 for USB detec control
Add SR114
Add COMM_B_DET# CONNECT TO GPIO69
Install SR50,

Observation Id: 720452 - Power noise fail with VccClkDMI and +5VSB
SR163 change to 0 ohm, follow CRB
change PR339 to 97.6 K and PR321 to 24 K can fix +5V noise issue.
Uninstall SR261 install SR259

C C

Thermal issue

3).delete PPQ56 and relate circuit, add PU3/PC20/PC23.
delete PR381/PR384/PR406/PR410,PR382/PR386/PR407/PR411 change to NI.
add PC25(NI)/PC32(NI).
PQ64 change to 07X50S211059.
PQ24/PQ28/PQ67/PQ58 to NI.PQ25/PQ29/PQ69/PQ60 to Critical

Observation Id: 720456 - Power Status LED didn't meet PCA spec
Change Power LED design for PCA spec.

Observation Id: 721236 - O2R122 chould chane to un-install
Observation Id: 714716 - please implenentation the DC INRUSH CIRCUIT

Add at page 55
Observation Id: 718222 - to meet enterprise PCa requirement (Smart ID )

Add at page 76
Observation Id: 719021 - Kona EVT2 system can't detect mini PCIe ETD device.

Observation Id: 719694 - Kona EVT2 systems do not have R4706 installed for the mini-PCIe slot 1.5V
Add at page 36

B B

A A

<Variant Name>

<Variant Name>

<Variant Name>

PEGATRON DT-MB RESTRICTED SECRET

CHANGE HISTORY-2

CHANGE HISTORY-2

CHANGE HISTORY-2

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

IPISB-SB

IPISB-SB

IPISB-SB

Engineer:

Scott Chen

Scott Chen

Scott Chen

373Thursday, April 14, 2011

373Thursday, April 14, 2011

1

373Thursday, April 14, 2011

Rev

Rev

Rev

1.00

1.00

1.00

5

A

4

3

2

1

D D

C C

B B

Title :

Title :

Title :

CHANGE HISTORY-3

CHANGE HISTORY-3

CHANGE HISTORY-3

Scott Chen

Scott Chen

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet

Date: Sheet

Date: Sheet

IPISB-SB

IPISB-SB

IPISB-SB

Engineer:

Scott Chen

473Thursday, April 14, 2011

473Thursday, April 14, 2011

473Thursday, April 14, 2011

of

of

of

Rev

Rev

Rev

1.00

1.00

1.00

A

5

www.schematic-x.blogspot.com

4

3

2

1

Intel Processor

PCH Buffer Through Mode for Pre-Silicon

Sandy Bridge

M_CHA_CLK[0..3]/#

D D

XMM3 / XMM4

C C

M_CHB_CLK[0..3]/#

XMM1 / XMM2

CK_100M_DMI2/#_CK505

CK_133M_BCLK_CK505/#

CK505

CK_100M_DMI_CK505/#

LGA-1155 Pin Socket

RSVD_001/002

BCLK/#_0

Intel

Platform Controller Hub

Cougar Point

942 Pin

CLKIN_GND1_P/N

CLKIN_GND0_P/N

CLKIN_DMI_P/N

CPU XDP

CK_100M_DMI/#

CK_100M_CPUXDP/#

100 MHz

CK_100M_PCHXDP/#

100 MHz

CK_100M_PE16/#

100 MHz

CK_100M_PE1/#

100 MHz

CK_100M_LAN/#

100 MHz

CK_100M_1394/#

100 MHz

CK_100M_CPU_XDP/#_CK505

PCH XDP

PCIEx16 Slot

PCIEx1 Slot

Intel 82579

VT6315N 1394

25 MHz

24.576 MHz

CK_100M_SATA_CK505/#

SLG8SP424VTR
ICS9LRS4180A/B

B B

CK_96M_DOT_CK505/#

CK_14M_REF_CK505

NOTE:

Reserved PD resistors for FCIM

CLKIN_SATA_P/N

CLKIN_DOT_96_P/N

REFCLK14IN

32 Pin

CK_33M_TPM

33 MHz

CK_48M_SIO

48 MHz

CK_33M_SIO

33 MHz

CK_33M_SL1

33 MHz

CK_33M_PCIFB

TPM Header

Fintek F71869E

PCI Slot

CK_48M_SIO_CK505

48 MHz

CKKIN_PCILOOPBACK

HDA_BCLK

AZ_BITCLK

24 MHz

14.318MHz

A A

XTAL25_IN RTCX

SPI_CLK

SPI_CLK
33 MHz

32.768KHz25MHz

5

4

3

AUDIO CODEC
ALC888S-VD

SPI ROM

2

<Variant Name>

<Variant Name>

<Variant Name>

PEGATRON DT-MB RESTRICTED SECRET

CLCOK DISTRIBUTION

CLCOK DISTRIBUTION

CLCOK DISTRIBUTION

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

IPISB-SB

IPISB-SB

IPISB-SB

Engineer:

Scott Chen

Scott Chen

Scott Chen

573Thursday, April 14, 2011

573Thursday, April 14, 2011

1

573Thursday, April 14, 2011

Rev

Rev

Rev

1.00

1.00

1.00

5

PCI_Express x 16

PCI_Express x 4

PCI_Express x 1

<28>PCIE_RST#

PWRGD

<28>PCIE_RST#

PWRGD

<28>PCIE_RST#

4

<29>PCH_PCIRST#

<27>PLTRST#

3

RST#

PCI SLOT #1

PE_RSTN

LAN 82579

2

1

Intel AMT 7.0 and non-DSW supported

RESET_SWITCH

PWRGD

D D

eSATA

1394

PERST#

PERST#

<28>PCIE16_RST#

<28>1394_RST#

NEC uPD720200 USB3.0

PERSTB

<27.1>PLTRST_CPU#

PCH PROCESSOR

POWER_SWITCH

<4>PWRBTN#

C C

2X12 ATX PSU

<15>PSON#

PSON#

PWROK

B B

<21>ATX_PWRGD

SIO FINTEK F71869E

PWSIN#

PS_ON#

ATXPG_IN

PCIRST3#
PCIRST2#
PCIRST1#

LRESET#

KBRST# RCIN#

RSMRST#

PWSOUT# PWRBTN#

S3# SLP_S3#

S4#

PWROK

<27>PLTRST#

RST_KB#

<9>RSMRST#

<4>SB_PWRBTN#

<13>SLP_S3#

<12>SLP_S4#

<11>SLP_A#

<10>SLP_LAN#

<7>SLP_SUS#

<5>SUS_WARN#

<6>SUS_ACK#

<3>PCH_DPWROK

PCIRST#

PLTRST#

RSMRST#

SLP_S4#

SLP_A#

SLP_LAN#

SLP_SUS#

SUS_WARN#

SUS_ACK#

DPWROK

PWROK

ME & LAN POWER

<22>PWROK

HDA_RST#

DRAMPWROK

RTCRST#

PROCPWRGD

SYS_PWROK

APWROK

+1P05V_ME

ONBOARD POWER

+3P3V_LAN

<14>APWROK

+3P3V_ME

STANDBY POWER

<8>

+5VSB

CHIP

A A

+3P3VSB

MB Logic

<2>+5VA

MB Logic

CK505

CKPWRGD/PD#

<22>CK505_PWRGD

AZ_RST#

<1>RTCRST#

RESET#

CPU SVID buffers are Hi-Z once +1P05V_CPUIO is
stable and UNCOREPWRGOOD = 0

<26>VRM_PWRGD

Vcore Controller

VR_RDY

MB Logic

SOCKET or SLOT

2X12 ATX PSU

5

<2>+5VA

4

3

AUDIO

ALC8889

SYS_RESET#

<23>DRAM_PWROK

BATTERY

<24>CPUPWRGD

VDIO/VCLK

VCORE

EN

RT8859AGQW

<20~24>SVIDs

<25>VCORE

<16>+1P05V_CPUIO
<19>+1P05V_CPUIO

2

DBR#SYS_RESET#

RESET#

SM_DRAMPWROK

UNCOREPWRGOOD

VIDSOUT/VIDSCLK

VCORE

<16>

+1P05V_CPUIO

<17>1P05V_CPUIO_PWRGD

PWRGD

NCP5380MNTXG

<18>

+0P925V_SA

EN

LM358

<Variant Name>

<Variant Name>

<Variant Name>

PEGATRON DT-MB RESTRICTED SECRET

SIGNAL&RESET MAP

SIGNAL&RESET MAP

SIGNAL&RESET MAP

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

IPISB-SB

IPISB-SB

IPISB-SB

Engineer:

Scott Chen

Scott Chen

Scott Chen

673Thursday, April 14, 2011

673Thursday, April 14, 2011

1

673Thursday, April 14, 2011

Rev

Rev

Rev

1.00

1.00

1.00

5

Adapter

4

3.8A

PS_ON#

0.11A

3

P-MOS

TPS51220RHBR

2

S0/S1

1

+19V

3.8A

S0/S1/S3/S4/S5

+5VA

100mA

S0/S1/S3/S4/S5

+3P3VA

10mA

D D

+19VA_VIN

+19VA

Hot-Plug

19.35A

180W

OVP
UVP

+19VSB

+1P05V_CPUIO

4.27A

1.19A

PWRGD_30MS

0.6A

SLP_A#

C C

1.46A

SLP_S4#

1.36A

19V

3.5A

SLP_S5#
5V_USB_MAIN#

NCP6121S52MNR2G 3Phase
H/N-MOSFET 11.7mOhm/30V PQFN*1
L/N-MOSFET 2.6mOhm/30V PQFN*2

NCP6151S52MNR2G
H/N-MOSFET 11.7mOhm/30V PQFN*2
L/N-MOSFET 2.6mOhm/30V PQFN*2

TPS51211DSCR
H/N-MOSFET 11.7mOhm/30V PQFN*1
L/N-MOSFET 3.3mOhm/30V PQFN*2

TPS51211DSCR
H/N-MOSFET 11.7mOhm/30V PQFN*1
L/N-MOSFET 3.3mOhm/30V PQFN*1

TPS51216RUKR
H/N-MOSFET 11.7mOhm/30V PQFN*1
L/N-MOSFET 3.3mOhm/30V PQFN*2

TPS54331DR

TPS51220RHBR
5VSB
H/N-MOSFET 11.7mOhm/30V PQFN*1
L/N-MOSFET 3.3mOhm/30V PQFN*1

S0/S1

+VCORE

Imax=75A.TDC=55A

S0/S1

+GFX_VCORE

Imax=35A.TDC=25A

S0/S1

17.3A

1P05V_CPUIO_PWRGD 8.8A

APL5611CI+N-MOS

8.7A

14.8A

PWRGD_30MS
SLP_S3#

N-MOS

S0/S1/S3

+1P05V_CPUIO

S0/S1

VCCSA(0P95V)

S0/S1

S0/S1

8.5A

+1P05V_ME

2.5A

+1P05V_PCH

6.2A

+1P5V_DUAL

13.3A

1.72A

TPS51216RUKR

N-MOS

S0/S1

S0/S1

S0/S1

+VTT_DDR

+1P5V

0.5A+12V

+12V

1.72A

10.62A

14.1A

S0/S1/S3/S4/S5

S3_GATE# 5A

N-MOS

N-MOS

S0/S1/S3

S0/S1

S0/S1/S3/S4/S5

+5VSB

2A

+5V_DUAL

+5V

3.62A+12V

+3P3V_ATX

1A

1A

B B

TPS51220RHBR
3P3V_ATX
H/N-MOSFET 11.7mOhm/30V, PQFN*1
L/N-MOSFET 3.3mOhm/30V, PQFN*1

LPS_ON#

+5V_DUAL

N-MOSFET

P-MOS

N-MOS

3.06A

+3P3V

APL5611CI+N-MOS

P-MOS

P-MOS

+3P3VSB

A A

RT9025_25PSP

P-MOSFET

SLP_A#

Switch ON/OFF

Switching

5

Linear

4

Note: Ixx/Ioo
means
Itdc/Imax

3

2

S0/S1/S3/S4

+3P3VSB

2A

S0/S1/S3

+3P3V_DUAL

305mA

S0/S1

+3P3V

5.48A+12V

S0/S1

+1P8V_SFR

1.6A

S0/S1

+3P3V_ME

1.6ASLP_LAN#

S0/S1

+3P3V_LAN

0.1ASLP_LAN#

S0/S1

1.5VSB

0.5A

S0/S1

+3P3V_MINI_PCIE

1.5AWLAN_EN &

<Variant Name>

<Variant Name>

<Variant Name>

PEGATRON DT-MB RESTRICTED SECRET

POWER FLOW

POWER FLOW

POWER FLOW

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

IPISB-SB

IPISB-SB

IPISB-SB

Engineer:

Scott Chen

Scott Chen

Scott Chen

773Thursday, April 14, 2011

773Thursday, April 14, 2011

1

773Thursday, April 14, 2011

Rev

Rev

Rev

1.00

1.00

1.00

5

4

3

2

1

D D

+VCORE

+1P05V_CPUIO

+0P925V_SA

+V_AXG

!$7'&:

!$,PD[:

!$,PD[:

!$7'&:

+12V

+3P3V

+3P3VSB

CPU Sandy Bridge

ࣿࣜࣜ࣭ࣜ

!$:

!$:

:$.(!$:
1R:$.(!P$P:

+3P3V

+1P05V_USB

+5V_DUAL_B/F

ࣿࣜ࣮࣮ࣳ࣬࣬࣬ࣜ࣯ࣾ࣪࣬

!P$:

!P$:

ࣰ࣭ࣾࣜࣜ

66!$:

+3P3V

CLOCK GEN

!P$:

+12V

+3P3V

+3P3VSB

ࣿ

+1P05V_PCH

C C

+1P05V_CPUIO

+1P8V_SFR

+3P3V

+3P3VSB

!$:

!$:

!$:

!$:

!$:

+12V

-12V

+5V

+3P3V

+3P3VSB

+1P05V_ME

!$:

+3P3V_ME

!$:

+3P3VA

B B

+BATT

!$:

57&*!X$P:

+3P3V_LAN

+3P3V

࣮ࣜࣰࣜࣤࣥࣜ࣢ࣜ

+1P5V_DAUL

+3P3V

9''666!$:

+VTT_DDR(0.75V)

6097766!$:

ࣿࣜࣜࣲ࣭ࣜ

!$:

!$:

:$.(!$:
1R:$.(!P$P:

ࣿࣜ

!$:

!$:

!$:

!$:

:$.(!$:
1R:$.(!P$P:

ࣱ࣮ࣜࣴࣳࣵ

!P$P:

ࣜࣜࣲ࣭ࣳࣴࣵ

!P$P:

ࣽࣿࣴࣴࣴࣩࣜࣿ

!P$P:

+3P3V

+5V

+5V

+3P3V

+12V

+5V_DUAL

+3P3V_ME

ࣰ࣭࣯ࣵࣽࣜࣱࣲ࣯࣭

!P$:



!P$P:
!P$P:



!P$P:

!P$P:



!P$P:

!P$P:

ࣽ

!$:

࣮ࣜࣾ࣫

66!$:
6!P$P:



!P$P:

A A

<Variant Name>

<Variant Name>

<Variant Name>

PEGATRON DT-MB RESTRICTED SECRET

POWER DISTRIBUTION

POWER DISTRIBUTION

POWER DISTRIBUTION

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

IPISB-SB

IPISB-SB

IPISB-SB

Engineer:

Scott Chen

Scott Chen

Scott Chen

873Thursday, April 14, 2011

873Thursday, April 14, 2011

1

873Thursday, April 14, 2011

Rev

Rev

Rev

1.00

1.00

1.00

5

4

3

2

1

DSW exit

S5 to S0 Power Sequence

SLP_SUS#

+5VSB / +3P3VSB

D D

RSMRST#
SUSWARN#
SUSACK#
SLP_LAN#
SLP_A#
+1P05V_ME
SLP_S5#

30uS

SLP_S4#
SLP_S3#

30uS

APWROK

C C

PSU: <=20mS

+12V / +5V
+3P3V
+1P5V_DUAL

=500mS

+1P05V_CPUIO

+1P8V_SFR

=50mS

VCCSA_VID

UNCOREPWRGOOD must be stable (low) at this time

+0P925V_SA

VCORE EN

B B

VIDSCLK / VIDSOUT

VIDALERT#

CPU SVID buffers are Hi-Z once VCCIO is
stable and Uncorepowergood = 0

CPU SVID buffers are Hi-Z once VCCIO is
stable and Uncorepowergood = 0

UNCOREPWRGOOD assertion

VCCSA_VID[0] FINAL

Recommended that +0P925V_SA ramp after +1P05V_CPUIO has ramped to ensure VCCSA_VID[0] is stable

<5mS

Typ 60uS

MISC ACK0/1...

Set VID
slow packet status packet

ACK0/1...

Get Reg

ACK0/1...

<600uS

<1uS

Pay
load

+0P925V_SA FINAL

>400uS

PSU: 100ms~500ms

ATX_PWRGD

BCLK / PCIE CLOCKS

DRAM_PWROK

>1mS

CPUPWRGD

+VCORE

VRM_PWRGD

A A

PLTRST#

5

4

1mS

Min 10 PCIe BCLKs

<5uS

<2mS

5mS

<5mS

1~100mS

<Variant Name>

<Variant Name>

<Variant Name>

PEGATRON DT-MB RESTRICTED SECRET

POWER SEQUENCE

POWER SEQUENCE

POWER SEQUENCE

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

3

2

Date: Sheet of

IPISB-SB

IPISB-SB

IPISB-SB

Engineer:

Scott Chen

Scott Chen

Scott Chen

973Thursday, April 14, 2011

973Thursday, April 14, 2011

1

973Thursday, April 14, 2011

Rev

Rev

Rev

1.00

1.00

1.00

5

M_CHA_DQ[0..63]{17}

M_CHA_DQS0{17}
M_CHA_DQS0#{17}

D D

M_CHA_DQS1{17}
M_CHA_DQS1#{17}

M_CHA_DQS2{17}
M_CHA_DQS2#{17}

C C

B B

A A

5

M_CHA_DQS3{17}
M_CHA_DQS3#{17}

M_CHA_DQS4{17}
M_CHA_DQS4#{17}

M_CHA_DQS5{17}
M_CHA_DQS5#{17}

M_CHA_DQS6{17}
M_CHA_DQS6#{17}

M_CHA_DQS7{17}
M_CHA_DQS7#{17}

4

Critical

Critical

XU1A

XU1A

M_CHA_DQS0
M_CHA_DQS0#

M_CHA_DQ0
M_CHA_DQ1
M_CHA_DQ2
M_CHA_DQ3
M_CHA_DQ4
M_CHA_DQ5
M_CHA_DQ6
M_CHA_DQ7

M_CHA_DQS1
M_CHA_DQS1#

M_CHA_DQ8
M_CHA_DQ9
M_CHA_DQ10
M_CHA_DQ11
M_CHA_DQ12
M_CHA_DQ13
M_CHA_DQ14
M_CHA_DQ15

M_CHA_DQS2
M_CHA_DQS2#

M_CHA_DQ16
M_CHA_DQ17
M_CHA_DQ18
M_CHA_DQ19
M_CHA_DQ20
M_CHA_DQ21
M_CHA_DQ22
M_CHA_DQ23

M_CHA_DQS3
M_CHA_DQS3#

M_CHA_DQ24
M_CHA_DQ25
M_CHA_DQ26
M_CHA_DQ27
M_CHA_DQ28
M_CHA_DQ29
M_CHA_DQ30
M_CHA_DQ31

M_CHA_DQS4
M_CHA_DQS4#

M_CHA_DQ32
M_CHA_DQ33
M_CHA_DQ34
M_CHA_DQ35
M_CHA_DQ36
M_CHA_DQ37
M_CHA_DQ38
M_CHA_DQ39

M_CHA_DQS5
M_CHA_DQS5#

M_CHA_DQ40
M_CHA_DQ41
M_CHA_DQ42
M_CHA_DQ43
M_CHA_DQ44
M_CHA_DQ45
M_CHA_DQ46
M_CHA_DQ47

M_CHA_DQS6
M_CHA_DQS6#

M_CHA_DQ48
M_CHA_DQ49
M_CHA_DQ50
M_CHA_DQ51
M_CHA_DQ52
M_CHA_DQ53
M_CHA_DQ54
M_CHA_DQ55

M_CHA_DQS7
M_CHA_DQS7#

M_CHA_DQ56
M_CHA_DQ57
M_CHA_DQ58
M_CHA_DQ59
M_CHA_DQ60
M_CHA_DQ61
M_CHA_DQ62
M_CHA_DQ63

4

AK3
AK2

AP3
AP2

AN1
AN4
AR3
AR4
AN2
AN3
AR2
AR1

AW4

AV4
AV2

AW3

AV5

AW5

AU2
AU3
AU5
AY5

AV8

AW8

AY7
AU7
AV9
AU9

AV7
AW7
AW9

AY9

AV37
AV36

AU35

AW37

AU39
AU36

AW35

AY36
AU38
AU37

AP38
AP39

AR40
AR37
AN38
AN37
AR39
AR38
AN39
AN40

AK38
AK39

AL40
AL37
AJ38
AJ37
AL39
AL38
AJ39
AJ40

AF38
AF39

AG40
AG37
AE38
AE37
AG39
AG38
AE39
AE40

AJ3
AJ4
AL3
AL4
AJ2
AJ1
AL2
AL1

SA_DQS_0
SA_DQS#_0

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7

SA_DQS_1
SA_DQS#_1

SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15

SA_DQS_2
SA_DQS#_2

SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23

SA_DQS_3
SA_DQS#_3

SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31

SA_DQS_4
SA_DQS#_4

SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39

SA_DQS_5
SA_DQS#_5

SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47

SA_DQS_6
SA_DQS#_6

SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55

SA_DQS_7
SA_DQS#_7

SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

SOCKET_1155P

SOCKET_1155P

3

SM_DRAMRST#

SA_ECC_CB_0
SA_ECC_CB_1
SA_ECC_CB_2
SA_ECC_CB_3
SA_ECC_CB_4
SA_ECC_CB_5
SA_ECC_CB_6
SA_ECC_CB_7

DDR3_A

DDR3_A

3

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
SA_MA_15

SA_WE#
SA_CAS#
SA_RAS#

SA_BS_0
SA_BS_1
SA_BS_2

SA_CS#_0
SA_CS#_1
SA_CS#_2
SA_CS#_3

SA_CKE_0
SA_CKE_1
SA_CKE_2
SA_CKE_3

SA_ODT_0
SA_ODT_1
SA_ODT_2
SA_ODT_3

SA_CK_0

SA_CK#_0

SA_CK_1

SA_CK#_1

SA_CK_2

SA_CK#_2

SA_CK_3

SA_CK#_3

SA_DQS_8

SA_DQS#_8

AV27
AY24
AW24
AW23
AV23
AT24
AT23
AU22
AV22
AT22
AV28
AU21
AT21
AW32
AU20
AT20

AW29
AV30
AU28

AY29
AW28
AV20

AU29
AV32
AW30
AU33

AV19
AT19
AU18
AV18

AV31
AU32
AU30
AW33

AY25
AW25
AU24
AU25
AW27
AY27
AV26
AW26

AW18

AV13
AV12

AU12
AU14
AW13
AY13
AU13
AU11
AY12
AW12

M_CHA_MAA0
M_CHA_MAA1
M_CHA_MAA2
M_CHA_MAA3
M_CHA_MAA4
M_CHA_MAA5
M_CHA_MAA6
M_CHA_MAA7
M_CHA_MAA8
M_CHA_MAA9
M_CHA_MAA10
M_CHA_MAA11
M_CHA_MAA12
M_CHA_MAA13
M_CHA_MAA14
M_CHA_MAA15

2

M_CHA_MAA[0..15] {17}

M_CHA_WE# {17}
M_CHA_CAS# {17}
M_CHA_RAS# {17}

M_CHA_BA0 {17}
M_CHA_BA1 {17}
M_CHA_BA2 {17}

M_CHA_CS#0 {17}
M_CHA_CS#1 {17}

M_CHA_CKE0 {17}
M_CHA_CKE1 {17}

M_CHA_ODT0 {17}
M_CHA_ODT1 {17}

M_CHA_CLK0 {17}
M_CHA_CLK0# {17}
M_CHA_CLK1 {17}
M_CHA_CLK1# {17}

DDR3_DRAMRST# {20}

NOTE:

For ECC DIMM

2

1

PEGATRON DT-MB RESTRICTED SECRET

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

Engineer:

IPISB-SB

IPISB-SB

IPISB-SB

1

DDR3_A 1-6

DDR3_A 1-6

DDR3_A 1-6

Scott Chen

Scott Chen

Scott Chen

10 73Thursday, April 14, 2011

10 73Thursday, April 14, 2011

10 73Thursday, April 14, 2011

Rev

Rev

Rev

1.00

1.00

1.00

5

M_CHB_DQ[0..63]{18}

M_CHB_DQS0{18}
M_CHB_DQS0#{18}

D D

M_CHB_DQS1{18}
M_CHB_DQS1#{18}

M_CHB_DQS2{18}
M_CHB_DQS2#{18}

C C

M_CHB_DQS3{18}
M_CHB_DQS3#{18}

M_CHB_DQS4{18}
M_CHB_DQS4#{18}

B B

A A

5

M_CHB_DQS5{18}
M_CHB_DQS5#{18}

M_CHB_DQS6{18}
M_CHB_DQS6#{18}

M_CHB_DQS7{18}
M_CHB_DQS7#{18}

4

Critical

Critical

XU1B

XU1B

M_CHB_DQS0
M_CHB_DQS0#

M_CHB_DQ0
M_CHB_DQ1
M_CHB_DQ2
M_CHB_DQ3
M_CHB_DQ4
M_CHB_DQ5
M_CHB_DQ6
M_CHB_DQ7

M_CHB_DQS1
M_CHB_DQS1#

M_CHB_DQ8
M_CHB_DQ9
M_CHB_DQ10
M_CHB_DQ11
M_CHB_DQ12
M_CHB_DQ13
M_CHB_DQ14
M_CHB_DQ15

M_CHB_DQS2
M_CHB_DQS2#

M_CHB_DQ16
M_CHB_DQ17
M_CHB_DQ18
M_CHB_DQ19
M_CHB_DQ20
M_CHB_DQ21
M_CHB_DQ22
M_CHB_DQ23

M_CHB_DQS3
M_CHB_DQS3#

M_CHB_DQ24
M_CHB_DQ25
M_CHB_DQ26
M_CHB_DQ27
M_CHB_DQ28
M_CHB_DQ29
M_CHB_DQ30
M_CHB_DQ31

M_CHB_DQS4
M_CHB_DQS4#

M_CHB_DQ32
M_CHB_DQ33
M_CHB_DQ34
M_CHB_DQ35
M_CHB_DQ36
M_CHB_DQ37
M_CHB_DQ38
M_CHB_DQ39

M_CHB_DQS5
M_CHB_DQS5#

M_CHB_DQ40
M_CHB_DQ41
M_CHB_DQ42
M_CHB_DQ43
M_CHB_DQ44
M_CHB_DQ45
M_CHB_DQ46
M_CHB_DQ47

M_CHB_DQS6
M_CHB_DQS6#

M_CHB_DQ48
M_CHB_DQ49
M_CHB_DQ50
M_CHB_DQ51
M_CHB_DQ52
M_CHB_DQ53
M_CHB_DQ54
M_CHB_DQ55

M_CHB_DQS7
M_CHB_DQS7#

M_CHB_DQ56
M_CHB_DQ57
M_CHB_DQ58
M_CHB_DQ59
M_CHB_DQ60
M_CHB_DQ61
M_CHB_DQ62
M_CHB_DQ63

4

AH7
AH6

AG7
AG8

AJ9

AJ8
AG5
AG6

AJ6

AJ7

AM8

AL8

AL7
AM7

AM10

AL10

AL6
AM6

AL9
AM9

AR8
AP8

AP7
AR7

AP10
AR10

AP6
AR6
AP9
AR9

AN13
AN12

AM12
AM13
AR13
AP13

AL12

AL13
AR12
AP12

AN29
AN28

AR28
AR29

AL28

AL29
AP28
AP29
AM28
AM29

AP33
AR33

AP32
AP31
AP35
AP34
AR32
AR31
AR35
AR34

AL33
AM33

AM32
AM31

AL35

AL32
AM34

AL31
AM35

AL34

AG35
AG34

AH35
AH34
AE34
AE35

AJ35

AJ34

AF33

AF35

SB_DQS_0
SB_DQS#_0

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7

SB_DQS_1
SB_DQS#_1

SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15

SB_DQS_2
SB_DQS#_2

SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23

SB_DQS_3
SB_DQS#_3

SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31

SB_DQS_4
SB_DQS#_4

SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39

SB_DQS_5
SB_DQS#_5

SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47

SB_DQS_6
SB_DQS#_6

SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55

SB_DQS_7
SB_DQS#_7

SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

DDR3_B

DDR3_B

SOCKET_1155P

SOCKET_1155P

3

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
SB_MA_15

SA_CK[2]

SA_CK[1]
SA_ODT[2]

SB_BS_0
SB_BS_1
SB_BS_2

SB_CS#_0
SB_CS#_1
SB_CS#_2
SB_CS#_3

SB_CKE_0
SB_CKE_1
SB_CKE_2
SB_CKE_3

SB_ODT_0
SB_ODT_1
SB_ODT_2
SB_ODT_3

SB_CK_0
SB_CK#_0

SB_CK_1
SB_CK#_1

SB_CK_2
SB_CK#_2

SB_CK_3
SB_CK#_3

SB_DQS_8

SB_DQS#_8

SB_ECC_CB_0
SB_ECC_CB_1
SB_ECC_CB_2
SB_ECC_CB_3
SB_ECC_CB_4
SB_ECC_CB_5
SB_ECC_CB_6
SB_ECC_CB_7

3

AK24
AM20
AM19
AK18
AP19
AP18
AM18
AL18
AN18
AY17
AN23
AU17
AT18
AR26
AY16
AV16

AR25
AK25
AP24

AP23
AM24
AW17

AN25
AN26
AL25
AT26

AU16
AY15
AW15
AV15

AL26
AP26
AM26
AK26

AL21
AL22
AL20
AK20
AL23
AM22
AP21
AN21

AN16
AN15

AL16
AM16
AP16
AR16
AL15
AM15
AR15
AP15

M_CHB_MAA0
M_CHB_MAA1
M_CHB_MAA2
M_CHB_MAA3
M_CHB_MAA4
M_CHB_MAA5
M_CHB_MAA6
M_CHB_MAA7
M_CHB_MAA8
M_CHB_MAA9
M_CHB_MAA10
M_CHB_MAA11
M_CHB_MAA12
M_CHB_MAA13
M_CHB_MAA14
M_CHB_MAA15

2

M_CHB_MAA[0..15] {18}

M_CHB_WE# {18}
M_CHB_CAS# {18}
M_CHB_RAS# {18}

M_CHB_BA0 {18}
M_CHB_BA1 {18}
M_CHB_BA2 {18}

M_CHB_CS#0 {18}
M_CHB_CS#1 {18}

M_CHB_CKE0 {18}
M_CHB_CKE1 {18}

M_CHB_ODT0 {18}
M_CHB_ODT1 {18}

M_CHB_CLK0 {18}
M_CHB_CLK0# {18}
M_CHB_CLK1 {18}
M_CHB_CLK1# {18}

2

1

PEGATRON DT-MB RESTRICTED SECRET

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

Engineer:

IPISB-SB

IPISB-SB

IPISB-SB

1

DDR3_B 2-6

DDR3_B 2-6

DDR3_B 2-6

Scott Chen

Scott Chen

Scott Chen

11 73Thursday, April 14, 2011

11 73Thursday, April 14, 2011

11 73Thursday, April 14, 2011

Rev

Rev

Rev

1.00

1.00

1.00

5

Critical

Critical

XU1C

XU1C

B11

PEG_RX_0

B12

PEG_RX#_0

D12

PEG_RX_1

D D

C C

DMI_RXP0{22}
DMI_RXN0{22}

DMI_RXP1{22}
DMI_RXN1{22}

DMI_RXP2{22}
DMI_RXN2{22}

B B

DMI_RXP3{22}
DMI_RXN3{22}

D11
C10

E10

AA4
AA5

C9

E9
B8

B7
C6

C5
A5

A6
E2

E1
F4

F3

G2
G1

H3
H4

J1
J2

K3
K4

L1
L2

M3
M4

N1
N2

W5
W4

V3
V4

Y3
Y4

PEG_RX#_1
PEG_RX_2

PEG_RX#_2
PEG_RX_3

PEG_RX#_3
PEG_RX_4

PEG_RX#_4
PEG_RX_5

PEG_RX#_5
PEG_RX_6

PEG_RX#_6
PEG_RX_7

PEG_RX#_7
PEG_RX_8

PEG_RX#_8
PEG_RX_9

PEG_RX#_9
PEG_RX_10

PEG_RX#_10
PEG_RX_11

PEG_RX#_11
PEG_RX_12

PEG_RX#_12
PEG_RX_13

PEG_RX#_13
PEG_RX_14

PEG_RX#_14
PEG_RX_15

PEG_RX#_15

DMI_RX_0
DMI_RX#_0

DMI_RX_1
DMI_RX#_1

DMI_RX_2
DMI_RX#_2

DMI_RX_3
DMI_RX#_3

PEG

PEG

PEG_TX#_10

PEG_TX#_11

PEG_TX#_12

PEG_TX#_13

PEG_TX#_14

PEG_TX#_15

PEG_TX_0

PEG_TX#_0

PEG_TX_1

PEG_TX#_1

PEG_TX_2

PEG_TX#_2

PEG_TX_3

PEG_TX#_3

PEG_TX_4

PEG_TX#_4

PEG_TX_5

PEG_TX#_5

PEG_TX_6

PEG_TX#_6

PEG_TX_7

PEG_TX#_7

PEG_TX_8

PEG_TX#_8

PEG_TX_9

PEG_TX#_9
PEG_TX_10

PEG_TX_11

PEG_TX_12

PEG_TX_13

PEG_TX_14

PEG_TX_15

DMI_TX_0

DMI_TX#_0

DMI_TX_1

DMI_TX#_1

DMI_TX_2

DMI_TX#_2

DMI_TX_3

DMI_TX#_3

4

C13
C14

E14
E13

G14
G13

F12
F11

J14
J13

D8
D7

D3
C3

E6
E5

F8
F7

G10
G9

G5
G6

K7
K8

J5
J6

M8
M7

L6
L5

N5
N6

V7
V6

W7
W8

Y6
Y7

AA7
AA8

DMI_TXP0 {22}
DMI_TXN0 {22}

DMI_TXP1 {22}
DMI_TXN1 {22}

DMI_TXP2 {22}
DMI_TXN2 {22}

DMI_TXP3 {22}
DMI_TXN3 {22}

3

+1P05V_CPUIO

12

I

I

HR2

HR2

24.9

24.9

1%

1%
mx_r0402_small

mx_r0402_small

FDI_COMP

AE2
AE1

FDI_FSYNC_0{26}
FDI_LSYNC_0{26}

FDI_FSYNC_1{26}
FDI_LSYNC_1{26}

FDI_INT{26}

AC5
AC4

AE5
AE4

AG3

2

Critical

Critical

XU1D

XU1D

FDI_COMPIO
FDI_ICOMPO

FDI_FSYNC_0
FDI_LSYNC_0

FDI_FSYNC_1
FDI_LSYNC_1

FDI_INT

SOCKET_1155P

SOCKET_1155P

FDI

FDI

FDI_TX_0

FDI_TX#_0

FDI_TX_1

FDI_TX#_1

FDI_TX_2

FDI_TX#_2

FDI_TX_3

FDI_TX#_3

FDI_TX_4

FDI_TX#_4

FDI_TX_5

FDI_TX#_5

FDI_TX_6

FDI_TX#_6

FDI_TX_7

FDI_TX#_7

AC8
AC7

AC2
AC3

AD2
AD1

AD4
AD3

AD7
AD6

AE7
AE8

AF3
AF2

AG2
AG1

1

FDI_TXP0 {26}
FDI_TXN0 {26}

FDI_TXP1 {26}
FDI_TXN1 {26}

FDI_TXP2 {26}
FDI_TXN2 {26}

FDI_TXP3 {26}
FDI_TXN3 {26}

FDI_TXP4 {26}
FDI_TXN4 {26}

FDI_TXP5 {26}
FDI_TXN5 {26}

FDI_TXP6 {26}
FDI_TXN6 {26}

FDI_TXP7 {26}
FDI_TXN7 {26}

PEG_COMP

+1P05V_CPUIO

12

I

I

HR3

HR3

24.9

24.9

1%

1%
mx_r0402_small

mx_r0402_small

DMI

DMI

PE_TX_0

PE_TX#_0

PE_TX_1

PE_TX#_1

PE_TX_2

PE_TX#_2

PE_TX_3

PE_TX#_3

B5
C4
B4

P8
P7

T7
T8

R6
R5

U5
U6

PEG_ICOMPO

PEG_RCOMPO

PEG_COMPI

P3

PE_RX_0

P4

PE_RX#_0

R2

PE_RX_1

R1

PE_RX#_1

T4

PE_RX_2

T3

PE_RX#_2

U2

PE_RX_3

U1

PE_RX#_3

A A

SOCKET_1155P

SOCKET_1155P

GEN

GEN

PEGATRON DT-MB RESTRICTED SECRET

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

IPISB-SB

IPISB-SB

IPISB-SB

1

PCIE/DMI/FDI 3-6

PCIE/DMI/FDI 3-6

PCIE/DMI/FDI 3-6

Scott Chen

Scott Chen

Scott Chen

12 73Thursday, April 14, 2011

12 73Thursday, April 14, 2011

12 73Thursday, April 14, 2011

Rev

Rev

Rev

1.00

1.00

1.00

of

5

4

Critical

Critical

XU1E

XU1E

3

2

1

NOTE:

H_CFG0
H_CFG1
H_CFG2
H_CFG3
H_CFG4
H_CFG5
H_CFG6
H_CFG7
H_CFG8
H_CFG9
H_CFG10
H_CFG11
H_CFG12
H_CFG13
H_CFG14
H_CFG15

W2

BCLK_0

W1

BCLK#_0

C40

RSVD_001

D40

RSVD_002

C37

VIDSCLK

B37

VIDSOUT

A37

VIDALERT#

F36

RESET#

J40

UNCOREPWRGOOD

AJ19

SM_DRAMPWROK

J35

PECI

E37

CATERR#

H34

PROCHOT#

G35

THERMTRIP#

E38

PM_SYNC

AJ22

SM_VREF

AJ33

SKTOCC#

K32

PROC_SEL

H36

CFG_0

J36

CFG_1

J37

CFG_2

K36

CFG_3

L36

CFG_4

N35

CFG_5

L37

CFG_6

M36

CFG_7

J38

CFG_8

L35

CFG_9

M38

CFG_10

N36

CFG_11

N38

CFG_12

N39

CFG_13

N37

CFG_14

N40

CFG_15

G37

CFG_16

G36

CFG_17

AT14

RSVD_016

AY3

RSVD_023

H7

RSVD_028

H8

RSVD_029

SOCKET_1155P

SOCKET_1155P

3

MISC

MISC

VCCSA_VID

VCCSA_SENSE

VCC_SENSE
VSS_SENSE

VCCIO_SENSE

VSSIO_SENSE

VCCAXG_SENSE
VSSAXG_SENSE

VCCP_SELECT

CK_100M_DMI{26}
CK_100M_DMI#{26}

D D

+1P5V_DUAL

I

I

SR90

SR90
200 Ohm

200 Ohm

5%

5%

1 2

VIDSCLK{64}
VIDSOUT{64}
VIDALERT#{64}

PLTRST_CPU#{16}

CPUPWRGD{24,72}

DRAM_PWROK{24}

NI

NI

12

HC7

HC7

0.1UF/16V

C C

PECI_SIO{23,74}
CATERR#{57}

PROCHOT#{64,74,76}

H_THMTRIP#{74}
PM_SYNC{23}

SKCOTT#{74}
NVR_CLE{26}

B B

HR23 4.7KImx_r0402_smallHR23 4.7KImx_r0402_small

Place HR23 close to NVRAM connector
and minimize this stub to <100 mils
with PCH and NVRAM

connector

NOTE:

CFG6 CFG5

11

+1P5V_DUAL

12

I

I

D3R39

D3R39
100

100

1%

1%
mx_r0402_small

mx_r0402_small

A A

12

I

I

D3R40

D3R40
100

100

1%

1%
mx_r0402_small

mx_r0402_small

I

I

12

D3CB17

D3CB17

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

GNDGND

10
01
00

5

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

12

CFG[0~15] is IPU

Description
X16(Default)
2X8
Reserved
X8, X4/X4

CK_100M_CPU_XDP{72}
CK_100M_CPU_XDP#{72}

+1P05V_CPUIO

12

12

NI

NI

NI

NI

HR4

HR4

HR5

HR5

51

51

90.9

90.9

mx_r0402_small

mx_r0402_small

1%

1%
mx_r0402_small

mx_r0402_small

R1458 120 Ohm 1%

R1458 120 Ohm 1%

1 2

I

I

12

I

I

HR58

HR58
1K

1K

mx_r0402_small

mx_r0402_small

GND

12

12

GND

NOTE:

Place near CPU

12

I

I

HR6

HR6
110

110

1%

1%
mx_r0402_small

mx_r0402_small

NI

NI

12

HC6

HC6

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

GNDGND

I

I

HR14

HR14

2.2K

2.2K

mx_r0402_small

mx_r0402_small

NI

NI

HCB2

HCB2

0.1UF/16V

0.1UF/16V

Y5V +80-20%

Y5V +80-20%

mx_c0402_small

mx_c0402_small

GND

GND

+1P05V_CPUIO+1P8V_SFR

12

C134

C134

0.01UF/25V

0.01UF/25V

X7R 10%

X7R 10%
NI

NI

GND

1 2

R_DRAM_PWROK

NI

NI

12

HC5

HC5

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

GND

12

NI

NI

HR17

HR17
1K

1K

mx_r0402_small

mx_r0402_small

12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12

12
12

12

I

I

HR18

HR18
51

51

mx_r0402_small

mx_r0402_small

H_DDR_VREF

NI

NI

12

HCB4

HCB4

0.1UF/16V

0.1UF/16V

Y5V +80-20%

Y5V +80-20%

mx_c0402_small

mx_c0402_small

GND

12

I

I

HR7

HR7
75

75

1%

1%
mx_r0402_small

mx_r0402_small

HR11 44.2 1%Imx_r0402_smallHR11 44.2 1%Imx_r0402_small

12

NI

NI

HR16

HR16
1K

1K

mx_r0402_small

mx_r0402_small

CPU_CFG0{72}

HR24 1KNImx_r0402_smallHR24 1KNImx_r0402_small
HR25 1KNImx_r0402_smallHR25 1KNImx_r0402_small
HR27 1KNImx_r0402_smallHR27 1KNImx_r0402_small
HR26 1KNImx_r0402_smallHR26 1KNImx_r0402_small
HR28 1KNImx_r0402_smallHR28 1KNImx_r0402_small
HR29 1KNImx_r0402_smallHR29 1KNImx_r0402_small
HR30 1KNImx_r0402_smallHR30 1KNImx_r0402_small
HR32 1KNImx_r0402_smallHR32 1KNImx_r0402_small
HR31 1KNImx_r0402_smallHR31 1KNImx_r0402_small
HR33 1KNImx_r0402_smallHR33 1KNImx_r0402_small
HR34 1KNImx_r0402_smallHR34 1KNImx_r0402_small
HR35 1KNImx_r0402_smallHR35 1KNImx_r0402_small
HR37 1KNImx_r0402_smallHR37 1KNImx_r0402_small
HR36 1KNImx_r0402_smallHR36 1KNImx_r0402_small
HR39 1KNImx_r0402_smallHR39 1KNImx_r0402_small
HR38 1KNImx_r0402_smallHR38 1KNImx_r0402_small

HR41 1KNImx_r0402_smallHR41 1KNImx_r0402_small
HR40 1KNImx_r0402_smallHR40 1KNImx_r0402_small

4

H_VIDALERT#

12

NI

NI

HR59

HR59
100

100

mx_r0402_small

mx_r0402_small

For VR Debug

GND

12

NI

NI

HR20

HR20
51

51

mx_r0402_small

mx_r0402_small

H_PECI_R
CATERR_R#

PROC_SEL

H_CFG16_SNB_PCUSTB0
H_CFG17_SNB_PCUSTB1

TDO
TCK

TMS

TRST#

PRDY#

PREQ#

DBR#

BPM#_0
BPM#_1
BPM#_2
BPM#_3
BPM#_4
BPM#_5
BPM#_6
BPM#_7

RSVD_024
RSVD_030
RSVD_037
RSVD_036
RSVD_033

RSVD_040
RSVD_039

RSVD_018
RSVD_020

RSVD_038
RSVD_032
RSVD_034

RSVD_035
RSVD_050

RSVD_053
RSVD_051

RSVD_052

P34
T2

A36
B36

AB4
AB3

L32
M32

+5V

12

I

I

HR52

HR52
10K

10K

mx_r0402_small

mx_r0402_small

P33
L39

L40

TDI

M40
L38
J39

12

I

I

HR53

HR53

4.7K

4.7K

mx_r0402_small

mx_r0402_small

GND

K38
K40
E39

H40
H38
G38
G40
G39
F38
E40
F40

B39
J33
L34
L33
K34

N33
M34

AV1
AW2

L9
J9
K9

L31
J31

K31
AD34

AD35

VCCSA_SENSE {59}
VCC_SENSE {64}

VSS_SENSE {64}
VCCIO_SENSE {62}

VSSIO_SENSE {62}
VCCAXG_SENSE {64}

VSSAXG_SENSE {64}

12

PROTO

PROTO

HR8

HR8
51

51

mx_r0402_small

mx_r0402_small

+3P3VSB

12

NI

NI

HR15

HR15
220

220

mx_r0402_small

mx_r0402_small

NOTE:

Place near CPU

12

PROTO

PROTO

HR9

HR9
51

51

mx_r0402_small

mx_r0402_small

12

PROTO

PROTO

HR12

HR12
51

51

mx_r0402_small

mx_r0402_small

GND

+1P05V_CPUIO +1P05V_CPUIO

BPM0# {72}
BPM1# {72}
BPM2# {72}
BPM3# {72}
BPM4# {72}
BPM5# {72}
BPM6# {72}
BPM7# {72}

12

GND

H_PRDY# {72}
H_PREQ# {72}
SYS_RESET_DBR# {24,72,73}

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet

Date: Sheet of

2

Date: Sheet of

NI

NI

HR60

HR60
1K

1K

mx_r0402_small

mx_r0402_small

VCCSA_VID {59}

NOTE:

Place near XDP connector

12

PROTO

PROTO

HR10

HR10
51

51

mx_r0402_small

mx_r0402_small

12

PROTO

PROTO

HR13

HR13
51

51

mx_r0402_small

mx_r0402_small

GND

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

IPISB-SB

IPISB-SB

IPISB-SB

1

VCCIO_SEL {62}
TDO {72}

TDI {72}
TCK {72}
TMS {72}
TRST# {72}

MISC 4-6

MISC 4-6

MISC 4-6

Scott Chen

Scott Chen

Scott Chen

13 73Thursday, April 14, 2011

13 73Thursday, April 14, 2011

13 73Thursday, April 14, 2011

of

Rev

Rev

Rev

1.00

1.00

1.00

5

Critical

A12
A13
A14
A15
A16
A18
A24
A25
A27
A28
B15
B16
B18
B24
B25
B27
B28
B30
B31
B33
B34
C15
C16
C18
C19
C21
C22
C24
C25
C27
C28
C30
C31
C33
C34
C36
D13
D14
D15
D16
D18
D19
D21
D22
D24
D25
D27
D28
D30
D31
D33
D34
D35
D36
E15
E16
E18
E19
E21
E22
E24
E25
E27
E28
E30
E31
E33
E34
E35
F15
F16
F18
F19
F21
F22
F24
F25
F27
F28
F30
F31

Critical

XU1F

XU1F

VCC_001
VCC_002
VCC_003
VCC_004
VCC_005
VCC_006
VCC_007
VCC_008
VCC_009
VCC_010
VCC_011
VCC_012
VCC_013
VCC_014
VCC_015
VCC_016
VCC_017
VCC_018
VCC_019
VCC_020
VCC_021
VCC_022
VCC_023
VCC_024
VCC_025
VCC_026
VCC_027
VCC_028
VCC_029
VCC_030
VCC_031
VCC_032
VCC_033
VCC_034
VCC_035
VCC_036
VCC_037
VCC_038
VCC_039
VCC_040
VCC_041
VCC_042
VCC_043
VCC_044
VCC_045
VCC_046
VCC_047
VCC_048
VCC_049
VCC_050
VCC_051
VCC_052
VCC_053
VCC_054
VCC_055
VCC_056
VCC_057
VCC_058
VCC_059
VCC_060
VCC_061
VCC_062
VCC_063
VCC_064
VCC_065
VCC_066
VCC_067
VCC_068
VCC_069
VCC_070
VCC_071
VCC_072
VCC_073
VCC_074
VCC_075
VCC_076
VCC_077
VCC_078
VCC_079
VCC_080
VCC_081

VCC_082
VCC_083
VCC_084
VCC_085
VCC_086
VCC_087
VCC_088
VCC_089
VCC_090
VCC_091
VCC_092
VCC_093
VCC_094
VCC_095
VCC_096
VCC_097
VCC_098
VCC_099
VCC_100
VCC_101
VCC_102
VCC_103
VCC_104
VCC_105
VCC_106
VCC_107
VCC_108
VCC_109
VCC_110
VCC_111
VCC_112
VCC_113
VCC_114
VCC_115
VCC_116
VCC_117
VCC_118
VCC_119
VCC_120
VCC_121
VCC_122
VCC_123
VCC_124
VCC_125
VCC_126
VCC_127
VCC_128
VCC_129
VCC_130
VCC_131
VCC_132
VCC_133
VCC_134
VCC_135
VCC_136
VCC_137
VCC_138
VCC_139
VCC_140
VCC_141
VCC_142
VCC_143
VCC_144
VCC_145
VCC_146
VCC_147
VCC_148
VCC_149
VCC_150
VCC_151
VCC_152
VCC_153
VCC_154
VCC_155
VCC_156
VCC_157
VCC_158
VCC_159
VCC_160
VCC_161

F32
F33
F34
G15
G16
G18
G19
G21
G22
G24
G25
G27
G28
G30
G31
G32
G33
H13
H14
H15
H16
H18
H19
H21
H22
H24
H25
H27
H28
H30
H31
H32
J12
J15
J16
J18
J19
J21
J22
J24
J25
J27
J28
J30
K15
K16
K18
K19
K21
K22
K24
K25
K27
K28
K30
L13
L14
L15
L16
L18
L19
L21
L22
L24
L25
L27
L28
L30
M14
M15
M16
M18
M19
M21
M22
M24
M25
M27
M28
M30

+VCORE+VCORE

D D

C C

B B

A A

4

M13
A11

A7
AA3
AB8
AF8

AG33

AJ16
AJ17
AJ26
AJ28

AJ32
AK15
AK17
AK19
AK21
AK23
AK27
AK29
AK30

B9

D10

D6
E3

E4
G3
G4

J3
J4
J7

J8
L3
L4
L7
N3
N4
N7
R3
R4
R7
U3
U4
U7
V8

W3

+0P925V_SA

H10
H11
H12

J10
K10
K11

L11

L12
M10
M11
M12

+1P8V_SFR

AK11
AK12

3

Critical

Critical

XU1H

XU1H

VCCIO_34
VCCIO_01

VCCIO_02
VCCIO_03
VCCIO_04
VCCIO_05
VCCIO_06
VCCIO_07
VCCIO_08
VCCIO_09
VCCIO_10
VCCIO_11
VCCIO_12
VCCIO_13
VCCIO_14
VCCIO_15
VCCIO_16
VCCIO_17
VCCIO_18
VCCIO_19
VCCIO_20
VCCIO_21
VCCIO_22
VCCIO_23
VCCIO_24
VCCIO_25
VCCIO_26
VCCIO_27
VCCIO_28
VCCIO_29
VCCIO_30
VCCIO_31
VCCIO_32
VCCIO_33
VCCIO_35
VCCIO_36
VCCIO_37
VCCIO_38
VCCIO_39
VCCIO_40
VCCIO_41
VCCIO_42
VCCIO_43
VCCIO_44
VCCIO_45

VCCSA_01
VCCSA_02
VCCSA_03
VCCSA_04
VCCSA_05
VCCSA_06
VCCSA_07
VCCSA_08
VCCSA_09
VCCSA_10
VCCSA_11

VCCPLL_01
VCCPLL_02

SOCKET_1155P

SOCKET_1155P

VDDQ_01
VDDQ_02
VDDQ_04
VDDQ_05
VDDQ_06
VDDQ_07
VDDQ_08
VDDQ_09
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VDDQ_14
VDDQ_15
VDDQ_16
VDDQ_17
VDDQ_18
VDDQ_19
VDDQ_20
VDDQ_21
VDDQ_22
VDDQ_23

VDDQ_03

AJ13
AJ14
AJ23
AJ24
AR20
AR21
AR22
AR23
AR24
AU19
AU23
AU27
AU31
AV21
AV24
AV25
AV29
AV33
AW31
AY23
AY26
AY28

AJ20

+1P5V_DUAL+1P05V_CPUIO

Inside processor socket cavity

2

I

I

I

12

HCB1

HCB1
22UF/6.3V

22UF/6.3V

X5R 20%

X5R 20%
mx_c0805

mx_c0805

GND GND GND

I

12

HCB6

HCB6
22UF/6.3V

22UF/6.3V

X5R 20%

X5R 20%
mx_c0805

mx_c0805

I

I

12

HCB3

HCB3
22UF/6.3V

22UF/6.3V

X5R 20%

X5R 20%
mx_c0805

mx_c0805

+V_AXG

AB33
AB34
AB35
AB36
AB37
AB38
AB39
AB40
AC33
AC34
AC35
AC36
AC37
AC38
AC39
AC40

W33
W34
W35
W36
W37
W38

T33
T34
T35
T36
T37
T38
T39
T40
U33
U34
U35
U36
U37
U38
U39
U40

Y33
Y34
Y35
Y36
Y37
Y38

Critical

Critical

XU1G

XU1G

VCCAXG_01
VCCAXG_02
VCCAXG_03
VCCAXG_04
VCCAXG_05
VCCAXG_06
VCCAXG_07
VCCAXG_08
VCCAXG_09
VCCAXG_10
VCCAXG_11
VCCAXG_12
VCCAXG_13
VCCAXG_14
VCCAXG_15
VCCAXG_16
VCCAXG_17
VCCAXG_18
VCCAXG_19
VCCAXG_20
VCCAXG_21
VCCAXG_22
VCCAXG_23
VCCAXG_24
VCCAXG_25
VCCAXG_26
VCCAXG_27
VCCAXG_28
VCCAXG_29
VCCAXG_30
VCCAXG_31
VCCAXG_32
VCCAXG_33
VCCAXG_34
VCCAXG_35
VCCAXG_36
VCCAXG_37
VCCAXG_38
VCCAXG_39
VCCAXG_40
VCCAXG_41
VCCAXG_42
VCCAXG_43
VCCAXG_44

SOCKET_1155P

SOCKET_1155P

1

5

SOCKET_1155P

SOCKET_1155P

PEGATRON DT-MB RESTRICTED SECRET

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet

Date: Sheet of

4

3

2

Date: Sheet of

Engineer:

IPISB-SB

IPISB-SB

IPISB-SB

1

VCC 5 - 6

VCC 5 - 6

VCC 5 - 6

Scott Chen

Scott Chen

Scott Chen

14 73Thursday, April 14, 2011

14 73Thursday, April 14, 2011

14 73Thursday, April 14, 2011

of

Rev

Rev

Rev

1.00

1.00

1.00

5

Critical

Critical

XU1I

XU1I

A17

VSS_001

A23

VSS_002

A26

VSS_003

A29

VSS_004

D D

C C

B B

A A

A35

VSS_005

AA33

VSS_006

AA34

VSS_007

AA35

VSS_008

AA36

VSS_009

AA37

VSS_010

AA38

VSS_011

AA6

VSS_012

AB5

VSS_013

AC1

VSS_014

AC6

VSS_015

AD33

VSS_016

AD36

VSS_017

AD38

VSS_018

AD39

VSS_019

AD40

VSS_020

AD5

VSS_021

AD8

VSS_022

AE3

VSS_023

AE33

VSS_024

AE36

VSS_025

AF1

VSS_026

AF34

VSS_027

AF36

VSS_028

AF37

VSS_029

AF40

VSS_030

AF5

VSS_031

AF6

VSS_032

AF7

VSS_033

AG36

VSS_034

AH2

VSS_035

AH3

VSS_036

AH33

VSS_037

AH36

VSS_038

AH37

VSS_039

AH38

VSS_040

AH39

VSS_041

AH40

VSS_042

AH5

VSS_043

AH8

VSS_044

AJ12

VSS_045

AJ15

VSS_046

AJ18

VSS_047

AJ21

VSS_048

AJ25

VSS_049

AJ27

VSS_050

AJ36

VSS_051

AJ5

VSS_052

AK1

VSS_053

AK10

VSS_054

AK13

VSS_055

AK14

VSS_056

AK16

VSS_057

AK22

VSS_058

AK28

VSS_059

AK31

VSS_060

AK32

VSS_061

AK33

VSS_062

AK34

VSS_063

AK35

VSS_064

AK36

VSS_065

AK37

VSS_066

AK4

VSS_067

AK40

VSS_068

AK5

VSS_069

AK6

VSS_070

AK7

VSS_071

AK8

VSS_072

AK9

VSS_073

AL11

VSS_074

AL14

VSS_075

AL17

VSS_076

AL19

VSS_077

AL24

VSS_078

AL27

VSS_079

AL30

VSS_080

AL36

VSS_081

AL5

VSS_082

AM1

VSS_083

AM11

VSS_084

AM14

VSS_085

AM17

VSS_086

AM2

VSS_087

AM21

VSS_088

AM23

VSS_089

AM25

VSS_090

A4

VSS_NCTF_01

AV39

VSS_NCTF_02

GND GND GND GND

SOCKET_1155P

SOCKET_1155P

5

GND

GND

VSS_091
VSS_092
VSS_093
VSS_094
VSS_095
VSS_096
VSS_097
VSS_098
VSS_099
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180

AM27
AM3
AM30
AM36
AM37
AM38
AM39
AM4
AM40
AM5
AN10
AN11
AN14
AN17
AN19
AN22
AN24
AN27
AN30
AN31
AN32
AN33
AN34
AN35
AN36
AN5
AN6
AN7
AN8
AN9
AP1
AP11
AP14
AP17
AP22
AP25
AP27
AP30
AP36
AP37
AP4
AP40
AP5
AR11
AR14
AR17
AR18
AR19
AR27
AR30
AR36
AR5
AT1
AT10
AT12
AT13
AT15
AT16
AT17
AT2
AT25
AT27
AT28
AT29
AT3
AT30
AT31
AT32
AT33
AT34
AT35
AT36
AT37
AT38
AT39
AT4
AT40
AT5
AT6
AT7
AT8
AT9
AU1
AU15
AU26
AU34
AU4
AU6
AU8
AV10

4

AV11
AV14
AV17

AV35
AV38

AW10
AW11
AW14
AW16
AW36

AW6
AY11
AY14
AY18
AY35

AY37

4

AV3

AV6

AY4
AY6
AY8
B10
B13
B14
B17
B23
B26
B29
B32
B35
B38

C11
C12
C17
C20
C23
C26
C29
C32
C35

D17
D20

D23
D26
D29
D32
D37
D39

E11
E12
E17
E20
E23
E26
E29
E32
E36

F10
F13
F14
F17

F20
F23
F26
F29
F35
F37
F39

G11
G12
G17
G20
G23
G26
G29
G34

B6

C7
C8

D2

D4
D5
D9

E7
E8
F1

F2

F5
F6
F9

G7

B3

Critical

Critical

XU1J

XU1J

VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_NCTF_03
VSS_NCTF_04

GND

GND

SOCKET_1155P

SOCKET_1155P

VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360

G8
H1
H17
H2
H20
H23
H26
H29
H33
H35
H37
H39
H5
H6
H9
J11
J17
J20
J23
J26
J29
J32
K1
K12
K13
K14
K17
K2
K20
K23
K26
K29
K33
K35
K37
K39
K5
K6
L10
L17
L20
L23
L26
L29
L8
M1
M17
M2
M20
M23
M26
M29
M33
M35
M37
M39
M5
M6
M9
N8
P1
P2
P36
P38
P40
P5
P6
R33
R35
R37
R39
R8
T1
T5
T6
U8
V1
V2
V33
V34
V35
V36
V37
V38
V39
V40
V5
W6
Y5
Y8

NOBOM

NOBOM

NOBOM

NOBOM
NOBOM

NOBOM

3

Critical

Critical

XU1K

XU1K

AB7

RSVD_04

AD37

RSVD_05

AG4

RSVD_08

AJ29

RSVD_10

AJ30

RSVD_11

AJ31

RSVD_12

AV34

RSVD_19

AW34

RSVD_21

P35

RSVD_43

P37

RSVD_44

P39

RSVD_45

R34

RSVD_46

R36

RSVD_47

R38

RSVD_48

R40

RSVD_49

HT38

HT38

HT41

HT41
HT42

HT42

TP_H_NCTF_1

1

TP_H_NCTF_4

1

TP_H_NCTF_5

1

Critical

Critical

BACKPLATE1

BACKPLATE1

INTEL LGA 1156P BACK PLATE,3 SCREW

INTEL LGA 1156P BACK PLATE,3 SCREW

PT44P11-6401

PT44P11-6401

3

A38

AU40

AW38

C2
D1

NCTF_01
NCTF_02
NCTF_03
NCTF_04
NCTF_05

SOCKET_1155P

SOCKET_1155P

FC_AH1
FC_AH4

RSVD_15
RSVD_14
RSVD_13
RSVD_17
RSVD_22

RSVD_07
RSVD_03
RSVD_06
RSVD_09

RSVD_27
RSVD_26
RSVD_25
RSVD_31
RSVD_41

NP_NC1
NP_NC2
NP_NC3
NP_NC4
NP_NC5
NP_NC6
NP_NC7

AH1
AH4

AT11
AP20
AN20
AU10
AY10

AF4
AB6
AE6
AJ11

D38
C39
C38
J34
N34

1
2
3
4
5
6
7

2

SA_DIMM_VR
SB_DIMM_VR

Critical

Critical

ILM1

ILM1

SOCKET1156_ILM

SOCKET1156_ILM

2

HR42 0Imx_r0402_smallHR42 0Imx_r0402_small

1 2

HR43 0Imx_r0402_smallHR43 0Imx_r0402_small

1 2

I

I

12

HC2

HC2

0.1UF/10V

0.1UF/10V

0.1

0.1

GND GND

INTEL LGA1156 SOCKET ILM

INTEL LGA1156 SOCKET ILM

I

I

12

HC3

HC3

0.1UF/10V

0.1UF/10V

0.1

0.1

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet

Date: Sheet of

Date: Sheet of

1

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

IPISB-SB

IPISB-SB

IPISB-SB

1

DIMM_DQ_VREF_A {17}
DIMM_DQ_VREF_B {18}

VSS 6 - 6

VSS 6 - 6

VSS 6 - 6

Scott Chen

Scott Chen

Scott Chen

15 73Thursday, April 14, 2011

15 73Thursday, April 14, 2011

15 73Thursday, April 14, 2011

of

Rev

Rev

Rev

1.00

1.00

1.00

5

D D

NI

NI

HR51

HR51
10K

10K

mx_r0402_small

mx_r0402_small

PCIE_PLT_RST#{36,37,75}

PLTRST#{24,46,71,72,73,74}

C C

1 2

I

I

HR47

HR47
10K

10K

mx_r0402_small

mx_r0402_small

1 2

TBD

4

HQ1_B

12

NI

NI

HR50

HR50

5.1K

5.1K

mx_r0402_small

mx_r0402_small

1

1

+3P3V_AMP

+3P3V_AMP

12

I

I

HR44

HR44
1K

1K

mx_r0402_small

mx_r0402_small

PLTRST PLTRST_CPU#_SHT

3

3

C

C

I

I

B

B

HQ1

HQ1
PMBS3904

PMBS3904

E

E
2

2

GNDGND

Critical

Critical

SU2C

SU2C

147

74LVC14AD

74LVC14AD

VCC

VCC

5 6

GND

GND

GND

I

I

12

HC9

HC9

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

GND

3

2

1

178 ohm in CRB and PDG

I

I

HR46

HR46
162 Ohm

162 Ohm

1%

1%

1 2

12

I

I

HR49

HR49
75

75

1%

1%
mx_r0402_small

mx_r0402_small

GND

PROTO

PROTO

HR48

HR48
1K

1K

mx_r0402_small

mx_r0402_small

1 2

PLTRST_CPU# {13}

CPURST_XDP# {72,73}

PLTRST_CPU#

+3P3V_AMP +3P3V_AMP

Critical

Critical

SU2D

SU2D

147

74LVC14AD

74LVC14AD

VCC

VCC

9 8

GND

GND

GND GND

B B

A A

Critical

Critical

SU2E

SU2E

147

74LVC14AD

74LVC14AD

VCC

VCC

11 10

GND

GND

+3P3V_AMP

Critical

Critical

SU2F

SU2F

147

74LVC14AD

74LVC14AD

VCC

VCC

13 12

GND

GND

GND

PEGATRON DT-MB RESTRICTED SECRET

PLTRST_CPU#

PLTRST_CPU#

1

PLTRST_CPU#

Scott Chen

Scott Chen

Scott Chen

16 73Thursday, April 14, 2011

16 73Thursday, April 14, 2011

16 73Thursday, April 14, 2011

of

Rev

Rev

Rev

1.00

1.00

1.00

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

IPISB-SB

IPISB-SB

IPISB-SB

5

M_CHA_MAA[0..15] {10}

12X2S1204B01(5.2H)
BLCAK

XMM1A

XMM1A

M_CHA_MAA0
M_CHA_MAA1
M_CHA_MAA2

12

NI

NI

SC7

SC7
150PF/50V

150PF/50V

NPO 5%

NPO 5%
mx_c0402_small

mx_c0402_small

M_CHA_MAA3
M_CHA_MAA4
M_CHA_MAA5
M_CHA_MAA6
M_CHA_MAA7
M_CHA_MAA8
M_CHA_MAA9
M_CHA_MAA10
M_CHA_MAA11
M_CHA_MAA12
M_CHA_MAA13
M_CHA_MAA14
M_CHA_MAA15

GND

12

D D

modify:0811

NOTE:

Check clock source if Eaglelake
implemented

M_CHA_CLK1{10}
M_CHA_CLK1#{10}
M_CHA_CLK0{10}
M_CHA_CLK0#{10}

M_CHA_CS#1{10}
M_CHA_CS#0{10}

M_CHA_ODT1{10}
M_CHA_ODT0{10}

M_CHA_WE#{10}
M_CHA_RAS#{10}

C C

B B

SMB_CLK_MAIN{18,72,73,75}
SMB_DATA_MAIN{18,72,73,75}

M_CHA_CAS#{10}

M_CHA_BA2{10}
M_CHA_BA1{10}
M_CHA_BA0{10}

M_CHA_CKE1{10}
M_CHA_CKE0{10}

M_CHA_DQS7{10}

M_CHA_DQS7#{10}

M_CHA_DQS6{10}

M_CHA_DQS6#{10}

M_CHA_DQS5{10}

M_CHA_DQS5#{10}

M_CHA_DQS4{10}

M_CHA_DQS4#{10}

M_CHA_DQS3{10}

M_CHA_DQS3#{10}

M_CHA_DQS2{10}

M_CHA_DQS2#{10}

M_CHA_DQS1{10}

M_CHA_DQS1#{10}

M_CHA_DQS0{10}

M_CHA_DQS0#{10}

GND GND

107

119

102
104
101
103

121
114

120
116

113
110
115

108
109

201
197

188
186
171
169
154
152
137
135

187
170
153
136

202
200

GND

NI

NI

SC48

SC48
150PF/50V

150PF/50V

NPO 5%

NPO 5%
mx_c0402_small

mx_c0402_small

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9
A10/AP

84

A11

83

A12/BC#
A13

80

A14

78

A15

CK1
CK1#
CK0
CK0#

S1#
S0#

ODT1
ODT0

WE#
RAS#
CAS#

79

BA2
BA1
BA0

74

CKE1

73

CKE0
SA1

SA0

DQS7
DQS#7
DQS6
DQS#6
DQS5
DQS#5
DQS4
DQS#4

64

DQS3

62

DQS#3

47

DQS2

45

DQS#2

29

DQS1

27

DQS#1

12

DQS0

10

DQS#0
DM7

DM6
DM5
DM4

63

DM3

46

DM2

28

DM1

11

DM0
SCL

SDA

DDR3_DIMM_204P

DDR3_DIMM_204P

Critical

Critical

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

RESET#

5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194

30

4

M_CHA_DQ0
M_CHA_DQ4
M_CHA_DQ2
M_CHA_DQ3
M_CHA_DQ5
M_CHA_DQ1
M_CHA_DQ6
M_CHA_DQ7
M_CHA_DQ9
M_CHA_DQ8
M_CHA_DQ15
M_CHA_DQ14
M_CHA_DQ12
M_CHA_DQ13
M_CHA_DQ11
M_CHA_DQ10
M_CHA_DQ16
M_CHA_DQ21
M_CHA_DQ19
M_CHA_DQ22
M_CHA_DQ20
M_CHA_DQ17
M_CHA_DQ18
M_CHA_DQ23
M_CHA_DQ24
M_CHA_DQ25
M_CHA_DQ26
M_CHA_DQ27
M_CHA_DQ28
M_CHA_DQ29
M_CHA_DQ31
M_CHA_DQ30

M_CHA_DQ32
M_CHA_DQ37
M_CHA_DQ34
M_CHA_DQ35
M_CHA_DQ36
M_CHA_DQ33
M_CHA_DQ38
M_CHA_DQ39
M_CHA_DQ40
M_CHA_DQ41
M_CHA_DQ42
M_CHA_DQ43
M_CHA_DQ44
M_CHA_DQ45
M_CHA_DQ46
M_CHA_DQ47
M_CHA_DQ49
M_CHA_DQ48
M_CHA_DQ50
M_CHA_DQ51
M_CHA_DQ53
M_CHA_DQ52
M_CHA_DQ54
M_CHA_DQ55
M_CHA_DQ56
M_CHA_DQ57
M_CHA_DQ59
M_CHA_DQ58
M_CHA_DQ61
M_CHA_DQ60
M_CHA_DQ62
M_CHA_DQ63

12

GND

DDR3_DRAMRST_A# {20}

NI

NI

HC1

HC1
150PF/50V

150PF/50V

NPO 5%

NPO 5%
mx_c0402_small

mx_c0402_small

M_CHA_DQ[0..63] {10}

DIMM_DQ_VREF_A{15}

3

+1P5V_DUAL

12

12

GND

I

I

D3R1

D3R1
1K

1K

1%

1%
mx_r0402_small

mx_r0402_small

I

I

D3R3

D3R3
1K

1K

1%

1%
mx_r0402_small

mx_r0402_small

+1P5V_DUAL

12

I

I

D3CB8

D3CB8

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

12

I

I

D3R2

D3R2
1K

1K

1%

1%
mx_r0402_small

mx_r0402_small

12

I

I

D3R4

D3R4
1K

1K

1%

1%
mx_r0402_small

mx_r0402_small

GNDGND

DIMM_CA_VREF_A

DIMM_DQ_VREF_A

12

I

I

D3CB7

D3CB7

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

GND

GND

+1P5V_DUAL

2

XMM1B

XMM1B

75

VDD1

81

VDD3

87

VDD5

93

VDD7

99

VDD9

105

VDD11

111

VDD13

117

VDD15

123

VDD17

2

VSS1

8

VSS3

13

VSS5

19

VSS7

25

VSS9

31

VSS11

37

VSS13

43

VSS15

48

VSS17

54

VSS19

60

VSS21

65

VSS23

71

VSS25

127

VSS27

133

VSS29

138

VSS31

144

VSS33

150

VSS35

155

VSS37

161

VSS39

167

VSS41

172

VSS43

178

VSS45

184

VSS47

189

VSS49

195

VSS51

198

EVENT#

125

TEST

77

NC1

122

NC2

126

VREFCA

1

VREFDQ

DDR3_DIMM_204P

DDR3_DIMM_204P

Critical

Critical

VDD2
VDD4
VDD6

VDD8
VDD10
VDD12
VDD14
VDD16
VDD18

VSS2
VSS4
VSS6

VSS8
VSS10
VSS12
VSS14
VSS16
VSS18
VSS20
VSS22
VSS24
VSS26
VSS28
VSS30
VSS32
VSS34
VSS36
VSS38
VSS40
VSS42
VSS44
VSS46
VSS48
VSS50
VSS52

GND1
GND2

NP_NC1
NP_NC2

VTT1

VTT2

VDDSPD

1

+1P5V_DUAL

76
82
88
94
100
106
112
118
124

3
9
14
20
26
32
38
44
49
55
61
66
72
128
134
139
145
151
156
162
168
173
179
185
190
196

207
208

205
206

203
204

199

GND

+3P3V

12

I

I

D3CB48

D3CB48

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

GND

D3CB52

D3CB52

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%

12

I

I

4.7UF/6.3V

4.7UF/6.3V

X5R 10%

X5R 10%

mx_c0805_small

mx_c0805_small

D3CB51

D3CB51

+VTT_DDR

12

I

I

GNDGND

A A

DDR3 CHANNEL A

DDR3 CHANNEL A

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

IPISB-SB

IPISB-SB

IPISB-SB

DDR3 CHANNEL A

Scott Chen

Scott Chen

Scott Chen

1

Rev

Rev

Rev

1.00

1.00

17 73Thursday, April 14, 2011

17 73Thursday, April 14, 2011

17 73Thursday, April 14, 2011

1.00

5

M_CHB_MAA[0..15] {11}

XMM3A

XMM3A

M_CHB_MAA0
M_CHB_MAA1
M_CHB_MAA2

12

I

I

SR13

SR13

2.7K

2.7K

mx_r0402_small

mx_r0402_small

12

NI

NI

SC10

SC10
150PF/50V

150PF/50V

NPO 5%

NPO 5%
mx_c0402_small

mx_c0402_small

M_CHB_MAA3
M_CHB_MAA4
M_CHB_MAA5
M_CHB_MAA6
M_CHB_MAA7
M_CHB_MAA8
M_CHB_MAA9
M_CHB_MAA10
M_CHB_MAA11
M_CHB_MAA12
M_CHB_MAA13
M_CHB_MAA14
M_CHB_MAA15

GND

12

GND

D D

modify:0811

NOTE:

Check clock source if Eaglelake
implemented

M_CHB_CLK1{11}
M_CHB_CLK1#{11}
M_CHB_CLK0{11}
M_CHB_CLK0#{11}

M_CHB_CS#1{11}
M_CHB_CS#0{11}

M_CHB_ODT1{11}
M_CHB_ODT0{11}

M_CHB_WE#{11}
M_CHB_RAS#{11}

C C

B B

+3P3V

SMB_CLK_MAIN{17,72,73,75}
SMB_DATA_MAIN{17,72,73,75}

M_CHB_CAS#{11}

M_CHB_BA2{11}
M_CHB_BA1{11}
M_CHB_BA0{11}

M_CHB_CKE1{11}
M_CHB_CKE0{11}

M_CHB_DQS7{11}

M_CHB_DQS7#{11}

M_CHB_DQS6{11}

M_CHB_DQS6#{11}

M_CHB_DQS5{11}

M_CHB_DQS5#{11}

M_CHB_DQS4{11}

M_CHB_DQS4#{11}

M_CHB_DQS3{11}

M_CHB_DQS3#{11}

M_CHB_DQS2{11}

M_CHB_DQS2#{11}

M_CHB_DQS1{11}

M_CHB_DQS1#{11}

M_CHB_DQS0{11}

M_CHB_DQS0#{11}

+3P3V +3P3V

12

I

I

SR14

SR14

2.7K

2.7K

mx_r0402_small

mx_r0402_small

GND

107

119

102
104
101
103

121
114

120
116

113
110
115

108
109

201
197

188
186
171
169
154
152
137
135

187
170
153
136

202
200

GND

NI

NI

SC49

SC49
150PF/50V

150PF/50V

NPO 5%

NPO 5%
mx_c0402_small

mx_c0402_small

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9
A10/AP

84

A11

83

A12/BC#
A13

80

A14

78

A15

CK1
CK1#
CK0
CK0#

S1#
S0#

ODT1
ODT0

WE#
RAS#
CAS#

79

BA2
BA1
BA0

74

CKE1

73

CKE0
SA1

SA0

DQS7
DQS#7
DQS6
DQS#6
DQS5
DQS#5
DQS4
DQS#4

64

DQS3

62

DQS#3

47

DQS2

45

DQS#2

29

DQS1

27

DQS#1

12

DQS0

10

DQS#0
DM7

DM6
DM5
DM4

63

DM3

46

DM2

28

DM1

11

DM0
SCL

SDA

DDR3_DIMM_204P

DDR3_DIMM_204P

Critical

Critical

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

RESET#

5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194

30

4

M_CHB_DQ1
M_CHB_DQ5
M_CHB_DQ7
M_CHB_DQ6
M_CHB_DQ4
M_CHB_DQ0
M_CHB_DQ2
M_CHB_DQ3
M_CHB_DQ12
M_CHB_DQ8
M_CHB_DQ14
M_CHB_DQ11
M_CHB_DQ13
M_CHB_DQ9
M_CHB_DQ15
M_CHB_DQ10
M_CHB_DQ20
M_CHB_DQ21
M_CHB_DQ23
M_CHB_DQ22
M_CHB_DQ16
M_CHB_DQ17
M_CHB_DQ18
M_CHB_DQ19
M_CHB_DQ24
M_CHB_DQ25
M_CHB_DQ27
M_CHB_DQ26

M_CHB_DQ28

M_CHB_DQ29

M_CHB_DQ30
M_CHB_DQ31
M_CHB_DQ33
M_CHB_DQ32
M_CHB_DQ38
M_CHB_DQ39
M_CHB_DQ36
M_CHB_DQ37
M_CHB_DQ35
M_CHB_DQ34
M_CHB_DQ45
M_CHB_DQ44
M_CHB_DQ47
M_CHB_DQ46
M_CHB_DQ40
M_CHB_DQ41
M_CHB_DQ42
M_CHB_DQ43
M_CHB_DQ54
M_CHB_DQ49
M_CHB_DQ50
M_CHB_DQ52
M_CHB_DQ48
M_CHB_DQ53
M_CHB_DQ55
M_CHB_DQ51
M_CHB_DQ61
M_CHB_DQ60
M_CHB_DQ63
M_CHB_DQ62
M_CHB_DQ56
M_CHB_DQ57
M_CHB_DQ59
M_CHB_DQ58

12

GND

DDR3_DRAMRST_B# {20}

NI

NI

HC11

HC11
150PF/50V

150PF/50V

NPO 5%

NPO 5%
mx_c0402_small

mx_c0402_small

M_CHB_DQ[0..63] {11}

DIMM_DQ_VREF_B{15}

3

+1P5V_DUAL

12

12

GND

I

I

D3R13

D3R13
1K

1K

1%

1%
mx_r0402_small

mx_r0402_small

I

I

D3R11

D3R11
1K

1K

1%

1%
mx_r0402_small

mx_r0402_small

+1P5V_DUAL

12

I

I

D3CB56

D3CB56

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

12

I

I

D3R12

D3R12
1K

1K

1%

1%
mx_r0402_small

mx_r0402_small

12

I

I

D3R14

D3R14
1K

1K

1%

1%
mx_r0402_small

mx_r0402_small

GNDGND

GND

DIMM_DQ_VREF_B

12

C941012

C941012

2.2UF/10V

2.2UF/10V

X5R 10%

X5R 10%
NI

NI

GND

2

+1P5V_DUAL

DIMM_CA_VREF_B

12

I

I

D3CB57

D3CB57

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

GND

XMM3B

XMM3B

75

VDD1

81

VDD3

87

VDD5

93

VDD7

99

VDD9

105

VDD11

111

VDD13

117

VDD15

123

VDD17

2

VSS1

8

VSS3

13

VSS5

19

VSS7

25

VSS9

31

VSS11

37

VSS13

43

VSS15

48

VSS17

54

VSS19

60

VSS21

65

VSS23

71

VSS25

127

VSS27

133

VSS29

138

VSS31

144

VSS33

150

VSS35

155

VSS37

161

VSS39

167

VSS41

172

VSS43

178

VSS45

184

VSS47

189

VSS49

195

VSS51

198

EVENT#

125

TEST

77

NC1

122

NC2

126

VREFCA

1

VREFDQ

DDR3_DIMM_204P

DDR3_DIMM_204P

Critical

Critical

VDD2
VDD4
VDD6

VDD8
VDD10
VDD12
VDD14
VDD16
VDD18

VSS2
VSS4
VSS6

VSS8
VSS10
VSS12
VSS14
VSS16
VSS18
VSS20
VSS22
VSS24
VSS26
VSS28
VSS30
VSS32
VSS34
VSS36
VSS38
VSS40
VSS42
VSS44
VSS46
VSS48
VSS50
VSS52

GND1
GND2

NP_NC1
NP_NC2

VTT1

VTT2

VDDSPD

1

+1P5V_DUAL

76
82
88
94
100
106
112
118
124

3
9
14
20
26
32
38
44
49
55
61
66
72
128
134
139
145
151
156
162
168
173
179
185
190
196

207
208

205
206

203
204

199

GND

+3P3V

12

I

I

D3CB59

D3CB59

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

GND

D3CB58

D3CB58

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%

12

I

I

4.7UF/6.3V

4.7UF/6.3V

X5R 10%

X5R 10%

mx_c0805_small

mx_c0805_small

D3CB55

D3CB55

+VTT_DDR

12

I

I

GNDGND

A A

DDR3 CHANNEL B

DDR3 CHANNEL B

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

IPISB-SB

IPISB-SB

IPISB-SB

DDR3 CHANNEL B

Scott Chen

Scott Chen

Scott Chen

1

Rev

Rev

Rev

1.00

1.00

18 73Thursday, April 14, 2011

18 73Thursday, April 14, 2011

18 73Thursday, April 14, 2011

1.00

5

+1P5V_DUAL

4

3

2

1

12

I

I

D3CB18

D D

C C

D3CB18

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

GND

12

NI

NI

D3CB23

D3CB23

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

12

NI

NI

D3CB36

D3CB36

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

12

I

I

D3CB66

D3CB66

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

GND GND GND GND GNDGND +1P5V_DUAL

12

I

I

D3CB19

D3CB19

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

GND GND GND GND

12

NI

NI

D3CB24

D3CB24

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

12

NI

NI

D3CB37

D3CB37

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

12

I

I

D3CB67

D3CB67

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

12

I

I

D3CB20

D3CB20

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

12

NI

NI

D3CB25

D3CB25

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

12

NI

NI

D3CB38

D3CB38

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

12

I

I

D3CB68

D3CB68

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

12

I

I

D3CB21

D3CB21

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

12

I

I

D3CB26

D3CB26

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

12

NI

NI

D3CB39

D3CB39

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

12

I

I

D3CB69

D3CB69

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

12

I

I

D3CB22

D3CB22

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

12

I

I

D3CB27

D3CB27

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

12

NI

NI

D3CB40

D3CB40

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

12

I

I

D3CB70

D3CB70

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

12

I

I

D3CB28

D3CB28

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

12

NI

NI

D3CB41

D3CB41

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

12

I

I

D3CB71

D3CB71
1UF/16V

1UF/16V

mx_c0603

mx_c0603
X7R 10%

X7R 10%

NOTE:

Place those cap close to CH A DIMM0

12

I

I

D3CB29

D3CB29

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

12

NI

NI

D3CB42

D3CB42

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

12

I

I

D3CB30

D3CB30

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

12

NI

NI

D3CB43

D3CB43

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

12

I

I

D3CB31

D3CB31

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

GNDGND GND GND GNDGND GNDGND GND GNDGND GNDGND

12

NI

NI

D3CB44

D3CB44

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

GNDGND GND GND GNDGND GNDGND GND GNDGND GND

NOTE:

Place those cap between CH A DIMM1 to CH B DIMM0

12

I

I

D3CB32

D3CB32
1UF/16V

1UF/16V

mx_c0603

mx_c0603
X7R 10%

X7R 10%

12

NI

NI

D3CB45

D3CB45

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

12

I

I

D3CB33

D3CB33
1UF/16V

1UF/16V

mx_c0603

mx_c0603
X7R 10%

X7R 10%

12

NI

NI

D3CB46

D3CB46

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

12

I

I

D3CB34

D3CB34
1UF/16V

1UF/16V

mx_c0603

mx_c0603
X7R 10%

X7R 10%

12

NI

NI

D3CB47

D3CB47

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

12

I

I

D3CB35

D3CB35
1UF/16V

1UF/16V

mx_c0603

mx_c0603
X7R 10%

X7R 10%

NOTE:

Place those cap between CH B DIMM 0 to DIMM1

Place those cap near CH B DIMM1

Place those cap between CH A DIMM1 to CH B DIMM0

B B

12

I

I

D3CB72

D3CB72
10UF/16V

10UF/16V

X5R 10%

X5R 10%

12

I

I

D3CB73

D3CB73
10UF/16V

10UF/16V

X5R 10%

X5R 10%

12

I

I

D3CB74

D3CB74
10UF/16V

10UF/16V

X5R 10%

X5R 10%

12

I

I

D3CB75

D3CB75
10UF/16V

10UF/16V

X5R 10%

X5R 10%

12

I

I

D3CB76

D3CB76
10UF/16V

10UF/16V

X5R 10%

X5R 10%

12

I

I

D3CB77

D3CB77
10UF/16V

10UF/16V

X5R 10%

X5R 10%

12

+

+

CE4103

CE4103
330UF/2.5V

330UF/2.5V

TAN/Lf_T=2000hrs_105C/+/-20%

TAN/Lf_T=2000hrs_105C/+/-20%

12

C9353

C9353
10UF/16V

10UF/16V

X5R 10%

X5R 10%

GND GND GND GND GND GND

I

I

12

C9354

C9354
10UF/16V

10UF/16V

X5R 10%

X5R 10%
I

I

12

C9355

C9355
10UF/16V

10UF/16V

X5R 10%

X5R 10%
I

I

12

C9356

C9356
10UF/16V

10UF/16V

X5R 10%

X5R 10%
I

I

12

C9357

C9357
10UF/16V

10UF/16V

X5R 10%

X5R 10%
I

I

12

C9358

C9358
10UF/16V

10UF/16V

X5R 10%

X5R 10%
I

I

GND GND GNDGND GNDGND

GND

Place D3CB77 near CH B DIMM1

DIMM

110

0

A A

LGA1155

SNB

PEGATRON DT-MB RESTRICTED SECRET

DDR3 TERMINATION A&B

DDR3 TERMINATION A&B

DDR3 TERMINATION A&B

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

CH A CH B

5

4

3

2

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet

Date: Sheet of

Date: Sheet of

Engineer:

IPISB-SB

IPISB-SB

IPISB-SB

1

Scott Chen

Scott Chen

Scott Chen

19 73Thursday, April 14, 2011

19 73Thursday, April 14, 2011

19 73Thursday, April 14, 2011

of

Rev

Rev

Rev

1.00

1.00

1.00

5

DDR3_DRAMRST#{10}

D D

C C

R37564

R37564

1 2

4.7KOHM

4.7KOHM

5%

5%
I

I

4

NI

NI

SR287

SR287

1 2

0

0

+3P3VSB

R37565

R37565
1KOhm

1KOhm

5%

5%

1 2

I

I

3

3

C

C

B

1

B

1

I

I

SQ9

SQ9
PMBS3904

PMBS3904

GND

E

E
2

2

3

NI

NI

SR285

1 2

1

1

I

I

SQ10

SQ10
PMBS3904

PMBS3904

1

1

I

I

SQ11

SQ11
PMBS3904

PMBS3904

SR285

0

0

+1P5V_DUAL

B

B

+1P5V_DUAL

B

B

GND

12

3

3

C

C

E

E
2

2

12

3

3

C

C

E

E
2

2

R37568

R37568
100 Ohm

100 Ohm

1%

1%
I

I

R37569

R37569
100 Ohm

100 Ohm

1%

1%
I

I

DDR3_DRAMRST_B#DDR3_REST_A&B

2

NI

NI

SR284

SR284

1 2

0

0

DDR3_DRAMRST_B# {18}

1

DDR3_DRAMRST_A# {17}

GND

B B

A A

<Variant Name>

<Variant Name>

<Variant Name>

PEGATRON DT-MB RESTRICTED SECRET

RSMRST#

RSMRST#

RSMRST#

Title :

Title :

Title :

Engineer:

Engineer:

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet

Date: Sheet of

5

4

3

2

Date: Sheet of

IPISB-SB

IPISB-SB

IPISB-SB

Engineer:

1

Scott Chen

Scott Chen

Scott Chen

20 73Thursday, April 14, 2011

20 73Thursday, April 14, 2011

20 73Thursday, April 14, 2011

of

Rev

Rev

Rev

1.00

1.00

1.00

5

+3P3V

CK_33M_PCIFB

D D

Strapping Options Flash

NOTE:

00
10

C C

B B

A A

12

GND

SATA1GP
/GPIO19

11

I

I

XY5

XY5

Crystal Holder

Crystal Holder

NI

NI

SC24

SC24

0.1UF/16V

0.1UF/16V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

SMB_CLK_RESUME{36,75}
SMB_DATA_RESUME{36,75}

SML0_LAN_CLK{37}
SML0_LAN_DATA{37}

SMLINK_CLK{74}
SMLINK_DATA{74}

5

Boot DeviceGNT1#

LPC
PCI
SPI

E14:12

E14:12

MINI_JUMPER_BLUE

MINI_JUMPER_BLUE

PROTO

PROTO

mx_r0402_small

mx_r0402_small

12

12

RTCRST#{70}

SRTCRST#{70}

PME_IN#{75}

SRN6C

SRN6C

I

I
I

I
I

I
I

I
I

I
I

I
I

I
I

I

E14

E14

1
2

HEADER_1X2P

HEADER_1X2P

Critical

Critical

I

I

SR20

SR20

1K

1K

I

I

SR5

SR5

2.7K

2.7K

mx_r0402_small

mx_r0402_small

NI

NI

SC1

SC1
150PF/50V

150PF/50V

NPO 5%

NPO 5%
mx_c0402_small

mx_c0402_small

5 6

SRN6D

SRN6D

7 8

SRN5D

SRN5D

7 8

SRN7A

SRN7A

1 2

SRN8D

SRN8D

7 8

SRN4A

SRN4A

1 2

SRN4D

SRN4D

7 8

SRN7B

SRN7B

3 4

NOBOM

NOBOM
NOBOM

NOBOM
NOBOM

NOBOM
NOBOM

NOBOM

+3P3V

12

+3P3V

GND

+3P3VSB +3P3VSB +3P3VSB

12

I

I

SR6

SR6

2.7K

2.7K

mx_r0402_small

mx_r0402_small

12

NI

NI

SC2

SC2
150PF/50V

150PF/50V

NPO 5%

NPO 5%
mx_c0402_small

mx_c0402_small

GNDGND

12

I

I

SC8

SC8
12PF/50V

12PF/50V

NPO 5%

NPO 5%
mx_c0402_small

mx_c0402_small

+3P3VSB +3P3VSB+3P3VSB

+3P3VSB

8.2K

8.2K

8.2K

8.2K

8.2K

8.2K

8.2K

8.2K

8.2K

8.2K

8.2K

8.2K

8.2K

8.2K

8.2K

8.2K

I

I
I

I
I

I

I

I
I

I
I

I
I

I
I

I
I

I
I

I
I

I

12

12

1 2

ST26

ST26
ST27

ST27

TPC26b

TPC26b
ST28

ST28

TPC26b

TPC26b
ST29

ST29

TPC26b

TPC26b
TPC26b

TPC26b

SRN6B

SRN6B
SRN5C

SRN5C
SRN4B

SRN4B

SRN6A

SRN6A
SRN4C

SRN4C
SRN8B

SRN8B
SRN5B

SRN5B
SRN8C

SRN8C
SRN7D

SRN7D
SRN8A

SRN8A
SRN5A

SRN5A

I

I

SR7

SR7

2.7K

2.7K

mx_r0402_small

mx_r0402_small

NI

NI

SC3

SC3
150PF/50V

150PF/50V

NPO 5%

NPO 5%
mx_c0402_small

mx_c0402_small

4

NI

NI

SR11

SR11

4.7K

4.7K

NOBOM

NOBOM
NOBOM

NOBOM

CK_33M_PCIFB{26}

PCH_GNT3

1

PCH_GNT2

1

PCH_GNT1

1

PCH_GNT0

1

SR21 8.2KOHM5% ISR21 8.2KOHM5% I

1 2
3 4

8.2K

8.2K

5 6

8.2K

8.2K

3 4

8.2K

8.2K

1 2

8.2K

8.2K

5 6

8.2K

8.2K

3 4

8.2K

8.2K

3 4

8.2K

8.2K

5 6

8.2K

8.2K

7 8

8.2K

8.2K

1 2

8.2K

8.2K

1 2

8.2K

8.2K

12

I

I

SR8

SR8

2.7K

2.7K

mx_r0402_small

mx_r0402_small

12

NI

NI

SC44

SC44
150PF/50V

150PF/50V

NPO 5%

NPO 5%
mx_c0402_small

mx_c0402_small

GNDGND

I

I

SR15

SR15
10M

10M

mx_r0603_small

mx_r0603_small

1 2

Critical

Critical

Y5

Y5

32.768Khz

32.768Khz

1

1

1

GND GND

GND GND

324

324

4

3

GND

PCH_RTCX2_R

2

4

ST30

ST30
TPC26b

TPC26b
ST31

ST31
TPC26b

TPC26b

1
1

BOOT_BLK_EN#

12

I

I

SR9

SR9

2.7K

2.7K

mx_r0402_small

mx_r0402_small

12

NI

NI

SC5

SC5
150PF/50V

150PF/50V

NPO 5%

NPO 5%
mx_c0402_small

mx_c0402_small

R37410

R37410

1 2

0 Ohm

0 Ohm

5%

5%
I

I

TP_SU1_AV14
TP_SU1_BH8

SU1_DEVSEL#

IPU 20K
IPU 20K
IPU

GNDGND

IPU 20K

Native CoreIPU 20K
Native Core
Native Core

Native Core
Native Core
Native Core

GPI Core
GPI Core
GPI Core
GPI Core

12

I

I

SR10

SR10

2.7K

2.7K

mx_r0402_small

mx_r0402_small

Native Sus
Native Sus

12

NI

NI

SC6

SC6
150PF/50V

150PF/50V

NPO 5%

NPO 5%
mx_c0402_small

mx_c0402_small

PCH_RTCX1
PCH_RTCX2

12

I

I

SC9

SC9
12PF/50V

12PF/50V

NPO 5%

NPO 5%
mx_c0402_small

mx_c0402_small

GNDGND

Critical

Critical

U4A

U4A

AV14

PCIRST#

AV15

PME#

BH8

PAR

BH9

DEVSEL#

BD15

CLKIN_PCILOOPBACK

BF11

IRDY#

BR6

SERR#

BC12

STOP#

BA17

PLOCK#

BC8

TRDY#

BM3

PERR#

BC11

FRAME#

BE2

GNT3#/GPIO55

BU12

GNT2#/GPIO53

AV8

GNT1#/GPIO51

BA15

GNT0#

AV11

REQ3#/GPIO54

BK8

REQ2#/GPIO52

BT5

REQ1#/GPIO50

BG5

REQ0#

BK10

PIRQA#

BJ5

PIRQB#

BM15

PIRQC#

BP5

PIRQD#

BN9

PIRQE#/GPIO2

AV9

PIRQF#/GPIO3

BT15

PIRQG#/GPIO4

BR4

PIRQH#/GPIO5

BT47

SMBCLK

BR49

SMBDATA

BT51

SML0CLK

BM50

SML0DATA

BJ46

SML1CLK/GPIO58

BK46

SML1DATA/GPIO75

BT41

RTCRST#

BN37

SRTCRST#

BR39

RTCX1

BN39

RTCX2

COUGARPOINT

COUGARPOINT

3

C/BE0#
C/BE1#
C/BE2#
C/BE3#

PCI

PCI

SMBUS

SMBUS

SMBALERT#/GPIO11

SML0ALERT#/GPIO60

SML1ALERT#/PCHHOT#/GPIO74

RTC

RTC

3

Rev=1.0

Rev=1.0

SPI

SPI

SPI_CS1#
SPI_CS0#
SPI_MOSI
SPI_MISO

SPI_CLK

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8

AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

BN4
BP7
BG2
BP13

BF15
BF17
BT7
BT13
BG12
BN11
BJ12
BU9
BR12
BJ3
BR9
BJ10
BM8
BF3
BN2
BE4
BE6
BG15
BC6
BT11
BA14
BL2
BC4
BL4
BC2
BM13
BA9
BF9
BA8
BF8
AV17
BK12

BN49

BU49

BR46

AR56
AT57
AU53
AT55
AR54

Native Sus

Native Sus

Native Sus

IPD 20K
IPU 20K

2

+3P3VSB +3P3VSB+3P3VSB

12

I

I

SR16

SR16
10K

10K

mx_r0402_small

mx_r0402_small

SMBALERT#_GPIO11

SML0ALERT#

SM1ALERT#_PCHHOT#_GPIO74

+3P3V_ME

12

NI

NI

SR19

SR19
1K

1K

mx_r0402_small

mx_r0402_small

TP_SPI_CS1

2

1

1

12

I

I

SR17

SR17
10K

10K

mx_r0402_small

mx_r0402_small

ST24

ST24

12

I

I

SR18

SR18
10K

10K

mx_r0402_small

mx_r0402_small

NOBOM

NOBOM

TPC26b

TPC26b

12

NI

NI

SC46

SC46
150PF/50V

150PF/50V

NPO 5%

NPO 5%
mx_c0402_small

mx_c0402_small

GND

<Variant Name>

<Variant Name>

<Variant Name>

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet

Date: Sheet of

Date: Sheet of

IPISB-SB

IPISB-SB

IPISB-SB

SPI_CS# {51}
SPI_MOSI {51}
SPI_MISO {51}
SPI_CLK {51}

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

1

PCI/SM/SPI/RTC 1-9

PCI/SM/SPI/RTC 1-9

PCI/SM/SPI/RTC 1-9

Scott Chen

Scott Chen

Scott Chen

21 73Thursday, April 14, 2011

21 73Thursday, April 14, 2011

21 73Thursday, April 14, 2011

of

Rev

Rev

Rev

1.00

1.00

1.00

5

D D

NOTE:

Used for for DMI, PCIe(PCIe 2.0 jitter spec compliant).

12

I

I

SR36

SR36
10K

10K

mx_r0402_small

mx_r0402_small

C C

WLAN_PE1_RXN1{36}

WLAN

B B

LAN

A A

WLAN_PE1_RXP1{36}
WLAN_PE1_TXN1{36}
WLAN_PE1_TXP1{36}

LAN_PE1_RXN6{37}
LAN_PE1_RXP6{37}
LAN_PE1_TXN6{37}
LAN_PE1_TXP6{37}

5

GND GND

4

DMI_TXN0{12}
DMI_TXP0{12}
DMI_RXN0{12}
DMI_RXP0{12}

DMI_TXN1{12}
DMI_TXP1{12}
DMI_RXN1{12}
DMI_RXP1{12}

DMI_TXN2{12}
DMI_TXP2{12}
DMI_RXN2{12}
DMI_RXP2{12}

DMI_TXN3{12}
DMI_TXP3{12}
DMI_RXN3{12}
DMI_RXP3{12}

12

I

I

SR37

SR37
10K

10K

mx_r0402_small

mx_r0402_small

NOTE:

trace length < 450 mils

4

+1P05V_PCH

12

I

I

SR30

SR30

49.9

49.9

1%

1%
mx_r0402_small

mx_r0402_small

DMICOMP

DMI2RBIAS

12

I

I

SR31

SR31
750

750

1%

1%
mx_r0402_small

mx_r0402_small

GND

3

Critical

Critical

U4B

U4B

D33

DMI0RXN

B33

DMI0RXP

J36

DMI0TXN

H36

DMI0TXP

A36

DMI1RXN

B35

DMI1RXP

P38

DMI1TXN

R38

DMI1TXP

B37

DMI2RXN

C36

DMI2RXP

H38

DMI2TXN

J38

DMI2TXP

E37

DMI3RXN

F38

DMI3RXP

M41

DMI3TXN

P41

DMI3TXP

CLKIN_DMI_N
CLKIN_DMI_P

P33

CLKIN_DMI_N

R33

CLKIN_DMI_P

DMI

DMI

B31

DMI_IRCOMP

E31

DMI_ZCOMP

A32

DMI2RBIAS

USB

USB

OC0#/GPIO59

PCIE

PCIE

J20

PERn1

L20

PERp1

F25

PETn1

F23

PETp1

P20

PERn2

R20

PERp2

C22

PETn2

A22

PETp2

H17

PERn3

J17

PERp3

E21

PETn3

B21

PETp3

P17

PERn4

M17

PERp4

F18

PETn4

E17

PETp4

N15

PERn5

M15

PERp5

B17

PETn5

C16

PETp5

J15

PERn6

L15

PERp6

A16

PETn6

B15

PETp6

J12

PERn7

H12

PERp7

F15

PETn7

F13

PETp7

H10

PERn8

J10

PERp8

B13

PETn8

D13

PETp8

COUGARPOINT

COUGARPOINT

http://hobi-elektronika.net

OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43

OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14

CLKIN_DOT_96N
CLKIN_DOT_96P

USBRBIAS#

USBRBIAS

3

USBP0N
USBP0P

USBP1N
USBP1P

USBP2N
USBP2P

USBP3N
USBP3P

USBP4N
USBP4P

USBP5N
USBP5P

USBP6N
USBP6P

USBP7N
USBP7P

USBP8N
USBP8P

USBP9N
USBP9P

USBP10N
USBP10P

USBP11N
USBP11P

USBP12N
USBP12P

USBP13N
USBP13P

BF36
BD36

BC33
BA33

BM33
BM35

BT33
BU32

BR32
BT31

BN29
BM30

BK33
BJ33

BF31
BD31

BN27
BR29

BR26
BT27

BK25
BJ25

BJ31
BK31

BF27
BD27

BJ27
BK27

BM43
BD41
BG41
BK43
BP43
BJ41
BT45
BM45

BD38
BF38

BP25
BM25

IPD 20K
IPD 20K

IPD 20K
IPD 20K

IPD 20K
IPD 20K

IPD 20K
IPD 20K

IPD 20K
IPD 20K

IPD 20K
IPD 20K

IPD 20K
IPD 20K

IPD 20K
IPD 20K

IPD 20K
IPD 20K

IPD 20K
IPD 20K

IPD 20K
IPD 20K

IPD 20K
IPD 20K

IPD 20K
IPD 20K

IPD 20K
IPD 20K

Native Sus
Native Sus
Native Sus
Native Sus
Native Sus
Native Sus
Native Sus
Native Sus

CLKIN_DOT_96N
CLKIN_DOT_96P

USBRBIAS

GND

+3P3VSB

5%I RN4393A

5%I

10KOhm

10KOhm

RN4393A

1 2

GPIO42

OC7#/GPIO14

12

I

I

SR35

SR35

22.6

22.6

1%

1%
mx_r0402_small

mx_r0402_small

USBN0 {47}
USBP0 {47}

USBN1 {47}
USBP1 {47}

USBN7 {41}
USBP7 {41}

USBN10 {48}
USBP10 {48}

USBN11 {48}
USBP11 {48}

5%I RN4393C

5%I

5%I RN4393D

10KOhm

10KOhm

RN4393C

3 4

12

I

I

SR40

SR40
10K

10K

mx_r0402_small

mx_r0402_small

GND

5%I

10KOhm

10KOhm

10KOhm

10KOhm

RN4393D

5 6

7 8

12

NI

NI

UC15

UC15

0.1UF/16V

0.1UF/16V

GND

12

I

I

SR34

SR34
10K

10K

mx_r0402_small

mx_r0402_small

GND GND

5%I RN4393B

5%I

RN4393B

NOTE:

trace length < 200 mils

2

SIDE USB
SIDE USB

WEB CAM

USBN8 {42}
USBP8 {42}

USBN9 {36}
USBP9 {36}

CARD READER

REAR USB
REAR USB

USBN12 {48}
USBP12 {48}

USBN13 {48}
USBP13 {48}

NOTE:

REAR USB
REAR USB

12

NI

NI

UC16

UC16

0.1UF/16V

0.1UF/16V

GND GND

12

NI

NI

UC17

UC17

0.1UF/16V

0.1UF/16V

Power On Password Enable

OC01# {47,73}
OC23# {73}
OC45# {73}
OC67# {73}

OC1011# {48,73}
OC1213# {48,73}
OCDEBUG# {73}

OC89# {73}

Used for integrated graphics, generate USB backbone,
24MHz HDA bit, and 48MHz clock.

12

I

I

SR33

SR33
10K

10K

mx_r0402_small

mx_r0402_small

<Variant Name>

<Variant Name>

<Variant Name>

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet

Date: Sheet of

2

Date: Sheet of

IPISB-SB

IPISB-SB

IPISB-SB

+3P3VSB

SR41

SR41
300 OHM

300 OHM

5%

5%

1 2

I

I

PASSWORD_EN

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

1

PCIE/USB/DMI 2-9

PCIE/USB/DMI 2-9

PCIE/USB/DMI 2-9

1

E49

E49

2
1

HEADER_1X2P

HEADER_1X2P

Critical

Critical

E49:12

E49:12

MINI_JUMPER_BLUE

MINI_JUMPER_BLUE

MP(I)

MP(I)

Scott Chen

Scott Chen

Scott Chen

22 73Thursday, April 14, 2011

22 73Thursday, April 14, 2011

22 73Thursday, April 14, 2011

of

Rev

Rev

Rev

1.00

1.00

1.00

5

D D

APWROK{30,60}

GND

NOBOM

NOBOM
NOBOM

NOBOM
NOBOM

NOBOM
NOBOM

+3P3V

12

12

I

I

I

I

SR50

SR50

SR49

SR49

10K

10K

10K

10K

mx_r0402_small

mx_r0402_small

mx_r0402_small

mx_r0402_small

C C

B B

SEL_2{35}

LPC_SMI#{57,74}

SEL_0{35}

Boot_BLK_rec#{57}

SEL_1{35}

+3P3V+3P3V

12

12

I

I

I

I

SR52

SR52

SR47

SR47

10K

10K

10K

10K

mx_r0402_small

mx_r0402_small

mx_r0402_small

mx_r0402_small

+3P3V +3P3V +3P3V

12

12

I

I

SR55

SR55
10K

10K

mx_r0402_small

mx_r0402_small

12

NI

NI

SR56

SR56
10K

10K

mx_r0402_small

mx_r0402_small

GND

NI

NI

SR64

SR64
10K

10K

mx_r0402_small

mx_r0402_small

12

I

I

SR85

SR85
10K

10K

mx_r0402_small

mx_r0402_small

GND

NOTE:

SEL_0 SEL_1 SEL_2

SAMSUNG

LG 1 0

A A

101
1

5

+3P3V+3P3V

12

I

I

SR72

SR72
10K

10K

mx_r0402_small

mx_r0402_small

12

NI

NI

SR65

SR65
10K

10K

mx_r0402_small

mx_r0402_small

12

I

I

SR68

SR68
10K

10K

mx_r0402_small

mx_r0402_small

GND

NOBOM

12

I

I

SR71

SR71
10K

10K

mx_r0402_small

mx_r0402_small

GND GND

NI

NI

12

SC30

SC30
100PF/50V

100PF/50V

NPO 5%

NPO 5%
mx_c0402_small

mx_c0402_small

ST38

ST38
ST39

ST39
ST25

ST25
ST44

ST44

+3P3V

12

I

I

SR38

SR38
10K

10K

mx_r0402_small

mx_r0402_small

4

CLINK_CLK_WLAN{36}
CLINK_DATA_WLAN{36}
CLINK_RST_WLAN_N{36}

TP_SU1_PWM0

1

TP_SU1_PWM1

1

TP_SU1_PWM2

1

TP_SU1_PWM3

1

12

I

I

SR58

SR58
10K

10K

mx_r0402_small

mx_r0402_small

12

GND

CHASSIS_ID0
BRD_ID1
CHASSIS_ID1

12

I

I

SR39

SR39
10K

10K

mx_r0402_small

mx_r0402_small

4

+3P3V+3P3V

12

I

I

SR51

SR51
10K

10K

mx_r0402_small

mx_r0402_small

GPI Core
GPI Core
GPI Core
GPI Core
GPI Core

GPI Core
Native Core
Native Core

SST

NI

NI

SC31

SC31

+3P3V

220PF/50V

220PF/50V

X7R 10%

X7R 10%
mx_c0402_small

mx_c0402_small

CLKIN_SATA_N
CLKIN_SATA_P

IPU 20K
IPU 20K
IPU 20K
IPU 20K
IPU 20K
IPU 20K
IPU 20K
IPU 20K

IPD 10K

12

I

I

SR83

SR83
10K

10K

mx_r0402_small

mx_r0402_small

GPI Core
GPI Core
GPI Core
GPI Core

BA50

BF50
BF49

BC46

BN21
BT21
BM20
BN19

BT17
BR19
BA22
BR16
BU16
BM18
BN17
BP15

BC43

BA53
BE54

BF55

AW53

AF55

AG56

AY20

Critical

Critical

U4C

U4C

COUGARPOINT

COUGARPOINT

CLINK

CLINK

CL_CLK1
CL_DATA1
CL_RST1#

APWROK

FAN

FAN

PWM0
PWM1
PWM2
PWM3

TACH0/GPIO17
TACH1/GPIO1
TACH2/GPIO6
TACH3/GPIO7
TACH4/GPIO68
TACH5/GPIO69
TACH6/GPIO70
TACH7/GPIO71

SST

GPIO

GPIO

SCLOCK/GPIO22
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48

CLKIN_SATA_N
CLKIN_SATA_P

NC_1

3

SATA0RXN
SATA0RXP
SATA0TXN

SATA0TXP

SATA1RXN
SATA1RXP
SATA1TXN

SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN

SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN

SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN

SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN

SATA5TXP

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA2GP/GPIO36
SATA3GP/GPIO37
SATA4GP/GPIO16
SATA5GP/GPIO49

SATAICOMPI

SATAICOMPO

SATA3COMPI

SATA3RCOMPO

SATALED#

TP16

SATA3RBIAS

HOST

HOST

A20GATE

INIT3_3V#

RCIN#

SERIRQ

THRMTRIP#

PECI

PMSYNCH

3

AC56
AB55
AE46
AE44

AA53
AA56
AG49
AG47

AL50
AL49
AL56
AL53

AN46
AN44
AN56
AM55

AN49
AN50
AT50
AT49

AT46
AT44
AV50
AV49

BC54
AY52
BB55
BG53
AU56
BA56

AJ55
AJ53

AE54
AE52

BF57

AE50
AC52

BB57
BN56
BG56
AV52
E56
H48
F55

GPI Core
GPI Core
GPI Core
GPI Core
GPI Core
GPI Core

NOTE:

trace length
< 500 mils

SATAICOMP

SATA3COMP

SATA3RBIAS

IPU 20K
I/OD
IPD 0.35K

BRD_ID2
SATA1GP_GPIO19

IPU 20K

SATA2GP_GPIO36

IPD 20K

SATA3GP_GPIO37

IPD 20K

GPIO16
BRD_ID0

+1P05V_PCH

NOTE:

trace length < 450 mils

12

I

I

SR70

SR70
750

750

1%

1%
mx_r0402_small

mx_r0402_small

+1P05V_CPUIO

GND

INIT3_3V#

PECI_PCH

12

NI

NI

SR74

SR74
1K

1K

mx_r0402_small

mx_r0402_small

GND

12

I

I

SR66

SR66

37.4

37.4

1%

1%
mx_r0402_small

mx_r0402_small

12

I

I

HR19

HR19
340 OHM

340 OHM

I

I

12

HC8

HC8
680PF/50V

680PF/50V

X7R 10%

X7R 10%

GND

2

SATA_RXN0 {49}
SATA_RXP0 {49}

SATA_TXN0 {49}
SATA_TXP0 {49}

SATA_RXN1 {49}
SATA_RXP1 {49}

SATA_TXN1 {49}
SATA_TXP1 {49}

EDS 1.0 SATA2GP/SATA3GP should not
be pulled high when strap is sampled.

SR61 10KImx_r0402_smallSR61 10KImx_r0402_small
SR62 10KImx_r0402_smallSR62 10KImx_r0402_small
SR63 10KImx_r0402_smallSR63 10KImx_r0402_small

+1P05V_PCH

12

+3P3V

12

GND

2

12
12
12

I

I

NOTE:

SR67

SR67

49.9

49.9

trace length < 500 mils

1%

1%
mx_r0402_small

mx_r0402_small

I

I

SR84

SR84
10K

10K

mx_r0402_small

mx_r0402_small

+3P3V

12

12

NI

NI

O2C23

O2C23

0.1UF/16V

0.1UF/16V

mx_c0402_small

mx_c0402_small

+3P3V

I

I

SR79

SR79
10K

10K

mx_r0402_small

mx_r0402_small

R7148 43

R7148 43

1 2

NI

NI

<Variant Name>

<Variant Name>

<Variant Name>

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Pegatron Corp.

Pegatron Corp.

Size Project Name

Size Project Name

Size Project Name

A3

A3

A3

Date: Sheet

Date: Sheet of

Date: Sheet of

+3P3V

GND

12

I

I

SR73

SR73
10K

10K

mx_r0402_small

mx_r0402_small

+3P3V

12

SR60

SR60
10K

10K

mx_r0402_small

mx_r0402_small

12

I

I

SR89

SR89
10K

10K

mx_r0402_small

mx_r0402_small

GND

A20GATE {74}
RST_KB# {74}

SERIRQ {46,57,74}
PCH_THMTRIP# {74}
PECI_SIO {13,74}

PM_SYNC {13}

IPISB-SB

IPISB-SB

IPISB-SB

1

+3P3V +3P3V

12

NI

NI

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

1

12

I

I

SR45

SR45
10K

10K

mx_r0402_small

mx_r0402_small

12

GND

HD_LED_IN# {75}

SATA/HOST/FAN 3-9

SATA/HOST/FAN 3-9

SATA/HOST/FAN 3-9

Scott Chen

Scott Chen

Scott Chen

23 73Thursday, April 14, 2011

23 73Thursday, April 14, 2011

23 73Thursday, April 14, 2011

NI

NI

SR48

SR48
10K

10K

mx_r0402_small

mx_r0402_small

I

I

SR96

SR96
10K

10K

mx_r0402_small

mx_r0402_small

of

Rev

Rev

Rev

1.00

1.00

1.00