Pegatron IMPLP-MS Schematics

5

4

3

2

1

IMPLP-MS

Monster (Shark Bay)

Revision_A00_2013/05/20

PAGE TITLE 01 BLOCK DIAGRAM 02 CLOCK DISTRIBUTION 03 POWER ON CHART 04 CHANGE HISTORY

D D

05 POWER FLOW 06 POWER DISTRIBUTION 07 POWER SEQUENCE 08 CPU DMI,FDI,PEG,DDI 09 CPU CLK,MISC,JTAG,Thermal 10 CPU DDR3 CHANNEL A 11 CPU DDR3 CHANNEL B 12 CPU POWER 13 CPU CFG 14 CPU GND 15 DDR3 SO-DIMM 0 16 DDR3 SO-DIMM 1

17. PCH SATA,IHDA,RTC,JTAG 18 PCH FDI,DMI,SPM 19 PCH CLOCK

HDMI OUT

2GB GDDR5 AMD SUN-XT 64bit

631 Pin

4.0/5.0 Gbps

23mm x 23mm

TDP 25W

TMDS 1.65Gbps

PCIE X8 Gen3 8.0Gbps

Intel Processor

Haswell

rPGA-947 Pin Socket

TDP 47W/37W

FDI 2.0

DMI 2.0

2.7Gbps 5.0Gbps

Channel A

Channel B

HDMI TMDS 1.65Gbps

20 PCH LPC,SPI,SMBus,Thermal 21 PCH CRT,LVDS,PCI,DISP 22 PCH GPIO,MISC,NCTF

C C

23 PCH PCIE,USB 24 PCH_POWER-1 25 PCH_POWER-2 26 27-28 SCALAR_TSUMU88BDC2

PCHVSS

29 LVDS & DUAL I/O CONNECTOR 30 HDMI IN 31 HDMI OUT 32 HALF MINI-PCIE 33 FULL MINI-PCIE 34 CARDREADER RST5209 35 36 SUPER I/O - F71808A

CARDREADER CONNECTOR

37 LAN RTL8151GD-CG 38 RJ45 CONNECTOR

SIDE

REAR

TOUCH PANEL

WEBCAM

WLAN/BT

Half mini-PCIE Slot

4 ports

2 ports

USB 2.0 & PCIE X1 Gen2 5.0Gbps

USB 3.0 5.0Gbps

USB 2.0 480Mbps

INTEL

Lynx Point

AZALIA

Mobile PCH

39 USB & AUDIO CONNECTOR 40 LEFT SIDE USB 3.0 CONNECTOR 41 REAR SIDE USB 2.0 CONNECTOR

B B

42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

A A

60-63 64 65 66 67 68 69 70

SATA CONNECTOR

AUDIO CODEC ALC3661 AUDIO AMP TPA3110D2 REAR HP-OUT CONN & MUTE AUDIO MUTE SM BUS & SPI ROM RTC & LPC DEBUG & FAN INTEGRATED VGA PORT CPU XDP DEBUG CONNECTOR PCH XDP DEBUG CONNECTOR LED & PCB & Label & Screw

MARS-S3 PRO PCIE MARS-S3 PRO IO MARS-S3 PRO VROM & STRAP MARS-S3 PRO MEMORY MARS-S3 PRO POWER MARS-S3 PRO DP_Power

MARS-S3 PRO GND & TMDS GDDR5 256M X16bit XCELL CURRENT LIMIT Power supply Vin

+19V / 3P3V / 5V / 5V_DUAL +1P35V_DUAL & +VTTDDR +1P5V +3P3GPU +1P8VMXM & +0P95V_GPU

5

+1P35V_GPU & +VDDCI

71 72

+VDDC controller

73

+VDDC CAP

74

+1P2V & +1P05V_PCH

75

+3VA / 5VA / 3VSB / 5VSB VCORE CONTROLLER

76 77

VCORE DRIVER 2-1

78

VCORE DRIVER 2-2 & Cout

79

DISCHARGE

80

CARD USB3.0 X2

4

TV TUNER/mSATA

Full mini-PCIE slot

RJ45

CARD READER SOCKET

USB 2.0/SATA Gen3 6.0Gbps/PCIE X1

LAN

RTL8151GD

CARD READER

RTS5209-GR

Default component footprint is SMD 0402, Y5V, 5% type. Difference footprint show on schematics.

Property: BOM I = Installed Part. NI = Not Installed Part. PROTO = PROTO Phase Only. VP = Virtual Part. NOBOM = Symbol only.

3

PCIE X1

HM87

695 Pin

20mm X 20mm

TDP 3W

SPI

SATA Gen3 6.0Gbps

LPC

2

SO-DIMM (Max Memory 16GB)

DDR3L 1600MHz *1

MSTAR

Scalar

TSUMU88BDC2-1

LINE IN

REALTEK

AUDIO

ALC3661-CG

QUAD I/O

SPI Flash

Serial ATA Port

FINTEK

SIO

F71808AU

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

(8MB)

LVDS

TMDS

HDMI-IN

AUDIO AMP TPA3110D2PWPR

FAN

Engineer:

IMPLP-MS

PANEL

DIGITAL MIC From Webcam

GHS(HP/MIC)

AUDIO OUT

SPEAKER (AVG)

Title :

1

R(4W)L(4W)

BLOCK DIAGRAM

Stonko_Chen

1 83Thursday, June 27 , 2013

Rev

A00

5

4

3

2

1

SO-DIMM2

Intel

Platform Controller Hub

D D

SO-DIMM1

32.768KHz

M_CHA[0..1]/#

SA_CK_[0:1]/#

C C

(800MHz)

M_CHB[0..1]/#

SB_CK_[0:1]/#

(800MHz)

25MHz

CLK_DMI/#

BCLK/#

CLK_DP/#

SSC_DPLL_REF_CLK/#

DPLL_REF_CLK/#

CLK_DPNS/#

RTCX

XTAL25_IN

CLKOUT_DMI/# (100MHz)

CLKOUT_DP/# (135MHz)

CLKOUT_DPNS/#

Lynx Point

CLKOUT_PEG_A/# (100MHz)

CLKOUT_PCIE_/#_0 (100MHz)

CLKOUT_PCIE_/#_1 (100MHz)

CLKOUT_PCIE_/#_2 (100MHz)

CLKOUT_PCIE_/#_3 (100MHz)

HDA_BCLK (24MHz)

CK_100M_PE8/#

CK_100M_LAN/#

CK_100M_PE1/#

CK_100M_PE2/#

CK_100M_PE3/#

AZ_BITCLK

AMD GPU SUN XT - S3 64Bit

CLKA0/# (1000~1500MHz)

CLKA1/# (1000~1500MHz)

REALTEK

RTL8151GD

CLKA0/#

CLKA1/#

GDDR5-1

GDDR5-3

25 MHz

Half mini-PCIE WLAN/BT

Full mini-PCIE TV TUNER/mSATA

CARD READER

Realtek RTS5209-GR

AUDIO

Realtek ALC3661-CG

GDDR5-2

GDDR5-4

(135MHz)

B B

Intel Processor

CLKOUTFLEX3 (48MHz)

CLKOUT_33MHZ2

Hasewell

(33MHz)

SPI_CLK (20/33/50MHz)

CPU - XDP

CK_100M_CPUXDP/#

CLKOUT_ITPXDP/# (100MHz)

CLKOUT_33MHZ3 (33MHz)

CK_48M_SIO1

CK_33M_SIO1

SPI_CLK

CK_33M_DEBUG

Super I/O

Fintek F71808AU

SPI ROM

LPC Debug Port

MSTAR

Scalar

TSUMU88BDC2-1

14.318MKHz

PCH - XDP

CLKIN_33MHZILOOPBACK (33MHz)

A A

CLKOUT_33MHZ1 (33MHz)

5

4

3

CLK_PCI_FB

PEGATRON DT-MB RESTRICTED SECRET

CLOCK DISTRIBUTION

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

2

Date: Sheet of

IMPLP-MS

Engineer:

1

Stonko_Chen

2 83Thursday, June 27 , 2013

Rev

A00

5

LAN RTL8151GD-CG

RESET#

4

GPU SUN XT

RESET#

3

2

1

Intel SharkBay and DSW supported

Mini Express x 1 (Half Card)

D D

Mini Express x 1 (Full Card)

PERST#

CARDER READER RTS5209-GR

RESET#

RESET_SWITCH

PERST#

LYNXPOINT PCH

HASWELL PROCESSOR

AUDIO ALC3661-CG

POWER_SWITCH

<5> PWRBTN#

C C

MAIN POWER

+5V +3P3V +1P5V +1P2V +1P05V

B B

<14> PSON#

Fintek SIO F71808AU

PSIN#

PSON#

PCIRST2#

PCIRST1#

LRESET#

KBRST# RCIN#

RSMRST#

PSOUT# PWRBTN#

S3# SLP_S3#

S4#

SUS_WARN#

SUS_ACK#

DPWROK

PWROK

<23> PCIE_RST#

<22> PLTRST#

<8> RSMRST#

<5> SB_PWRBTN#

<13> SLP_S3#<15> +19V

<11> SLP_S4#

<9> SUS_WARN#

<10> SUS_ACK#

<4> PCH_DPWROK

<16> PWROK

RST_KB#

PLTRST#

RSMRST#

SLP_S4#

SLP_A#

SLP_LAN#

SUS_WARN#

SUS_ACK#

DPWROK

PWROK

DRAMPWROK

PROCPWRGD PWRGOOD

PLTRST_PROC#

RTCRST#

APWROK

<6> SLP_SUS#

SLP_SUS#

AZ_RST#

<1> RTCRST#

RESET#HDA_RST#

SYS_RESET#

<17> PM_DRAM_PWRGD

<18> H_CPUPWRGD

<22> PLTRST_CPU#

BATTERY

<16~18> SVIDs

<19> LOAD SVIDs

DBR#SYS_RESET#

SM_DRAMPWROK

PLTRSTIN#

VIDSOUT/VIDSCLK

VCORE

DUAL POWER

<12> +5V_DUAL +1P35V_DUAL

ONBOARD POWER

ALWAYS POWER

<3> +5VA

A A

CHIP

+3VA

<2> +19VA

STANDBY POWER

<7> +5VSB +3VSB

SYS_PWROK

<21> VRM_PWRGD

+19V Adapter PSU

SOCKET or SLOT

5

4

3

Vcore Controller

VDIO/VCLK

VCORE

VR_RDY

TPS51631RSM

EN

<20> +VCORE

<15> +3P3V

2

MAIN POWER

+3P3V

PEGATRON DT-MB RESTRICTED SECRET

POWER ON CHART

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

IMPLP-MS

Engineer:

1

Stonko_Chen

3 83Thursday, June 27 , 2013

Rev

A00

5

Schematics Change History

Schematics Change HistorySchematics Change History

Version

VersionVersion

1.00

D D

C C

Date

DateDate

Description

DescriptionDescription

4

3

2

Comments

CommentsComments

1

B B

A A

PEGATRON DT-MB RESTRICTED SECRET

CHANGE HISTORY

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

5

4

3

2

Date: Sheet of

IMPLP-MS

Engineer:

1

Stonko_Chen

4 83Thursday, June 27 , 2013

Rev

A00

5

4

3

2

1

S0 S1 S3 S4 S5

DS5 G3

+19VSB

MOS - ON/OFF

PAGE. 66

D D

TI-TPS51631 ( 3-PHASE )

MOS - ON/OFF

PAGE. 66

+19V_BL Imax=2. 1A/TDC=1.47A

+19V Imax=0.58A /TDC=0.404A

+VCORE Imax=85A /TDC=27A

PAGE. 76,77,78

4

Imax=14.6A TDC=10.22A

Imax=25.8A TDC=17.6A

Imax=7.47A TDC=5.23A

Imax=10.8A TDC=5.83A

MOS - ON/OFF

PAGE. 71

LM358 + MOS

PAGE. 74

LM358 + MOS

PAGE. 74

LM358 + MOS

PAGE. 71

LM358 + MOS

PAGE. 70

MOS - ON/OFF

PAGE. 66

MOS - ON/OFF

PAGE. 69

MOS - ON/OFF

PAGE. 70

MOS - ON/OFF

PAGE. 66

MOS - ON/OFF

PAGE. 66

3

PAGE. 25

+1P5V Imax=1.25 3A/TDC=0.927A

+1P35V_GPU Imax =6.93A/TDC=4.8A

+1P2V Imax=0.5 A/TDC=0.35A

+1P05V_PCH Imax =5.921A/TDC=4.1 447A

+1P05V_ME

+1P35V_DUAL Ima x=9.32A/TDC=6.5 24A

+VTT_DDR Imax= 1.43A/TDC=1A

+VDDCI Imax=9A /TDC=6A

+0P95V_GPU Ima x=6.03A/TDC=4.0 2A

+5VSB Imax=0.5A /TDC=0.35A

+3P3VSB Imax=5. 8944A/TDC=2.476 A

+5VA Imax=0.00 14A /TDC=0.005A

+3VA Imax=0.015 A/TDC=0.011A

+3P3V Imax=2.8 47A/TDC=2.0005A

+3P3V_ME

+3P3V_GPU Imax= 0.086A/TDC=0.06 A

+1P8V_MXM Imax =1.94A/TDC=1.29 A

+5V Imax=1.57A /TDC=1.1A

+5V_DUAL Imax=5 .4A/TDC=3.78A

+VDDC Imax=37.5 A/TDC=25A

+BATT

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

2

Date: Sheet of

IMPLP-MS

Title :

Engineer:

1

POWER FLOW

Stonko_Chen

5 83Thursday, June 27 , 2013

Rev

A00

TI-TPS51211 ( 1-PHASE )

PAGE. 68

C C

TI-TPS51216

( 1-PHASE )

PAGE. 67

+19VA_VIN

+19VSB

19VIN

OVP/UVP Protection

PAGE. 67

B B

A A

BATTERY

TI-TPS51225

( 1-PHASE )

PAGE. 75

RICHTEK RT8153C

( 1-PHASE )

PAGE. 72, 73

SWITCHING Linear ON / OFF

5

4

3

2

1

Intel Haswell CPU

Wattage(W)TDC (A)I(max)(A)

+VCORE

D D

+1P35V_DUAL

2785

2.944.2 5.67

47

Intel PCH - Lynx Point HM87

I(max)(A) TDC (A) Wattage(W)

+3P3V

+3P3VSB

+3VA

+1P5V

C C

+1P05V_PCH

0.202 0.141 0.67

0.293 0.970.205

0.015 0.050.011

0.253 0.177 0.38

5.921

6.224.1447

+1P35V_DUAL

+VTT_DDR

+3P3V

+1P2V

+3P3VSB

+3P3V

+5VSB

SO - DIMM x 2 (DDR3L)

Wattage(W)TDC (A)I(max)(A)

5.12 3.584 6.912

11.43 0.97

Scalar - MSTAR TSUMU88BDC2-1

Wattage(W)TDC (A)I(max)(A)

0.5

0.35

LOM - Realtek RTL8151GD

Wattage(W)TDC (A)I(max)(A)

0.1 0.07 0.33

Audio - Realtek ALC3661-CG

Wattage(W)TDC (A)I(max)(A)

0.071

0.5

0.05

0.35

1.65

0.6

0.236

2.5

SATA 3.0 (1-Port for 2.5" HDD)

+5V

1.57 1.1 7.86

mini_PCIE (Half card)

+1P5V

+3P3VSB

0.5 0.50.375

2.75 9.0751.1

mini_PCIE (Full card)

I(max)(A) TDC (A) Wattage(W)

+1P5V

+3P3VSB

2.75

0.375 0.50.5

1.1 9.075

USB3.0 ( 6-Ports )

TDC (A) Wattage(W)I(max)(A)

+5V_DUAL

5.4 273.78

FAN

Wattage(W)TDC (A)I(max)(A)

+5V

0.5 2.50.35

TDC (A) Wattage(W)I(max)(A)

SPI

Wattage(W)TDC (A)I(max)(A)

+3P3V

0.03 0.099

TDC (A) Wattage(W)I(max)(A)

0.03

PANEL

Wattage(W)TDC (A)I(max)(A)

+19V_BL

+5V_LCD

2.1 39.91.47

1.1 0.50.8

Webcam

Audio AMP - TPA3110D2PWPR

AMD GPU - SUN-XT (64bit)

I(max)(A) TDC (A) Wattage(W)

+VDDC(1.125V)

+VDDCI(0.95V)

B B

+3P3V_GPU

+1P8V_MXM

0.086 0.06 0.283

0.53 0.35 0.954

+1P35V_GPU

+0P95V_GPU

2537.5 49.19

69 8.55

11.5

2.025

4.026.03 5.73

+19V

+3P3V

+3P3VSB

+5VA

0.58 0.404 11.97

SIO - Fintek F71808AU

0.011

0.0014

0.008

0.001

0.0010.0014 0.005

Wattage(W)TDC (A)I(max)(A)

+3P3V

0.323 1.0650.226

Touch

Wattage(W)TDC (A)I(max)(A)

0.38

0.005

+5V_DUAL

+5V

1.57 7.861.1

HDMI

0.055 0.2750.039

TDC (A) Wattage(W)I(max)(A)

Card Reader - Realtek RTS5209-GR

Wattage(W)TDC (A)I(max)(A)

GDDR5 - 2GB

+3P3V

Wattage(W)TDC (A)I(max)(A)

A A

+1P35V_GPU

5

3.85.43 7.33

4

1.71 1.2 5.66

PEGATRON DT-MB RESTRICTED SECRET

POWER DISTRIBUTION

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

3

2

Date: Sheet of

Engineer:

IMPLP-MS

1

Stonko_Chen

6 83Thursday, June 27 , 2013

Rev

A00

5

VCCRTC

G3

S5

DSW

t200: >9mS

S5/S4/S3

4

S0

3

2

1

G3 to S0 Power Sequence

RTCRST#

D D

+19VA

+5VA / +3VA

DPWROK

PWRBTN#

SLP_SUS#

+5VSB / +3VSB

DSW exit

RSMRST#

t225: >0mS

t200b: >10mS

t200a: >0mS

t202: >95mS

t200c: >0mS

t201: >10mS

t226: >20nS

SUS_WARN#

SUS_ACK#

SLP_S4#

C C

+5V_DUAL / +1P35V_DUAL

t204: >30uS

SLP_S3#

PSON#

+19V / +5V / +3P3V / +1P5V / +1P2V / +1P05V

VCORE_EN

VIDSCLK / VIDSOUT

PWROK

t205a: >5mS

t223: >0uS

Serial VID Load

B B

25MHz CRYSTAL OSC

PCH OUTPUT CLOCKs

DRAMPWROK

PROCPWRGD

25MHz CLK Stable

PCH Output CLK Stable

t208: >1mS

t209: >1mS

+VCORE

VRM_PWRGD

PLTRST_PROC#

PLTRST#

A A

PCIE_RST#

PEGATRON DT-MB RESTRICTED SECRET

POWER SEQUENCE

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

5

4

3

2

Date: Sheet of

IMPLP-MS

Engineer:

1

Stonko_Chen

7 83Thursday, June 27 , 2013

Rev

A00

5

I

XU1A

D D

DMI_TXN019 DMI_TXN119 DMI_TXN219 DMI_TXN319

DMI_TXP019 DMI_TXP119 DMI_TXP219 DMI_TXP319

DMI_RXN019 DMI_RXN119 DMI_RXN219 DMI_RXN319

DMI_RXP019 DMI_RXP119 DMI_RXP219 DMI_RXP319

FDI_CSYNC19

C C

B B

A A

FDI_INT19

Haswell rPGA

D21 C21 B21 A21

D20 C20 B20 A20

D18 C17 B17 A17

D17 C18 B18 A18

H29

J29

SOCKET_ 947P

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

FDI_CSYNC DISP_INT

DMI FDI

PEG_RCOMP

PEG_RXN_0 PEG_RXN_1 PEG_RXN_2 PEG_RXN_3 PEG_RXN_4 PEG_RXN_5 PEG_RXN_6 PEG_RXN_7 PEG_RXN_8

PEG_RXN_9 PEG_RXN_10 PEG_RXN_11 PEG_RXN_12 PEG_RXN_13 PEG_RXN_14 PEG_RXN_15

PEG_RXP_0

PEG_RXP_1

PEG_RXP_2

PEG_RXP_3

PEG_RXP_4

PEG_RXP_5

PEG_RXP_6

PEG_RXP_7

PEG_RXP_8

PEG

PEG_RXP_9

PEG_RXP_10 PEG_RXP_11 PEG_RXP_12 PEG_RXP_13 PEG_RXP_14 PEG_RXP_15

PEG_TXN_0

PEG_TXN_1

PEG_TXN_2

PEG_TXN_3

PEG_TXN_4

PEG_TXN_5

PEG_TXN_6

PEG_TXN_7

PEG_TXN_8

PEG_TXN_9

PEG_TXN_10 PEG_TXN_11 PEG_TXN_12 PEG_TXN_13 PEG_TXN_14 PEG_TXN_15

PEG_TXP_0 PEG_TXP_1 PEG_TXP_2 PEG_TXP_3 PEG_TXP_4 PEG_TXP_5 PEG_TXP_6 PEG_TXP_7 PEG_TXP_8

PEG_TXP_9 PEG_TXP_10 PEG_TXP_11 PEG_TXP_12 PEG_TXP_13 PEG_TXP_14 PEG_TXP_15

4

+VCOMP_ OUT

12

I

HR61

24.9

NOTE:

1%

E23

H_PEG_R COMP

M29

PEG_RXN _7

K28

PEG_RXN _6

M31

PEG_RXN _5

L30

PEG_RXN _4

M33

PEG_RXN _3

L32

PEG_RXN _2

M35

PEG_RXN _1

L34

PEG_RXN _0

E29 D28 E31 D30 E35 D34 E33 E32 L29

PEG_RXP _7

L28

PEG_RXP _6

L31

PEG_RXP _5

K30

PEG_RXP _4

L33

PEG_RXP _3

K32

PEG_RXP _2

L35

PEG_RXP _1

K34

PEG_RXP _0

F29 E28 F31 E30 F35 E34 F33 D32 H35 H34 J33 H32 J31 G30 C33 B32 B31 A30 B29 A28 B27 A26 B25 A24 J35 G34 H33 G32 H31 H30 B33 A32 C31 B30 C29 B28 C27 B26 C25 B24

I_GPU I_GPU I_GPU I_GPU I_GPU I_GPU I_GPU I_GPU

W/S=12/15 mil, length<400mil

1 2

HC89 0.22UF/10 V

1 2

HC90 0.22UF/10 V

1 2

HC91 0.22UF/10 V

1 2

HC92 0.22UF/10 V

1 2

HC93 0.22UF/10 V

1 2

HC94 0.22UF/10 V

1 2

HC95 0.22UF/10 V

1 2

HC96 0.22UF/10 V

NOTE:

PCIE X8 Reversed

1 2

HC98 0.22UF/10 V

1 2

HC97 0.22UF/10 V

1 2

HC99 0.22UF/10 V

1 2

HC100 0.22UF/10V

1 2

HC101 0.22UF/10V

1 2

HC102 0.22UF/10V

1 2

HC103 0.22UF/10V

1 2

HC104 0.22UF/10V

EXP_TXN 7 53 EXP_TXN 6 53 EXP_TXN 5 53 EXP_TXN 4 53 EXP_TXN 3 53 EXP_TXN 2 53 EXP_TXN 1 53 EXP_TXN 0 53

EXP_TXP 7 53 EXP_TXP 6 53 EXP_TXP 5 53 EXP_TXP 4 53 EXP_TXP 3 53 EXP_TXP 2 53 EXP_TXP 1 53 EXP_TXP 0 53

3

X7R 10% X7R 10% X7R 10% X7R 10% X7R 10% X7R 10% X7R 10% X7R 10%

EXP_RXN 7 53 EXP_RXN 6 53 EXP_RXN 5 53 EXP_RXN 4 53 EXP_RXN 3 53 EXP_RXN 2 53 EXP_RXN 1 53 EXP_RXN 0 53

EXP_RXP 7 53 EXP_RXP 6 53 EXP_RXP 5 53 EXP_RXP 4 53 EXP_RXP 3 53 EXP_RXP 2 53 EXP_RXP 1 53 EXP_RXP 0 53

To Scalar

To HDMI-Out Connector

2

1

Configuration-wise Mapping of HDMI signals for Processor on DDI ports

DDI

Port

Differential Pairs

DPB_LANE0_P DPB_LANE0_N DPB_LANE1_P DPB_LANE1_N DPB_LANE2_P

Port B

DPB_LANE2_N DPB_LANE3_P DPB_LANE3_N DDPB_HPD DDPB_CTRLCLK DDPB_CTRLDATA

DPC_LANE0_P DPC_LANE0_N DPC_LANE1_P DPC_LANE1_N DPC_LANE2_P

Port C

Port D

HDMIC_TMD SC_DATA2#28 HDMIC_TMD SC_DATA228 HDMIC_TMD SC_DATA1#28 HDMIC_TMD SC_DATA128 HDMIC_TMD SC_DATA0#28 HDMIC_TMD SC_DATA028 HDMIC_TMD SC_CLK#28 HDMIC_TMD SC_CLK28

HDMID_TMD SD_DATA0#32 HDMID_TMD SD_DATA032 HDMID_TMD SD_DATA1#32 HDMID_TMD SD_DATA132 HDMID_TMD SD_DATA2#32 HDMID_TMD SD_DATA232 HDMID_TMD SD_CLK#32 HDMID_TMD SD_CLK32

DPC_LANE2_N DPC_LANE3_P DPC_LANE3_N DDPC_HPD DDPC_CTRLCLK DDPC_CTRLDATA

DPD_LANE0_P DPD_LANE0_N DPD_LANE1_P DPD_LANE1_N DPD_LANE2_P DPD_LANE2_N DPC_LANE3_P DPC_LANE3_N DDPD_HPD DDPD_CTRLCLK DDPD_CTRLDATA

HDMI Signals

HDMIB_DATA2_P HDMIB_DATA2_N HDMIB_DATA1_P HDMIB_DATA1_N HDMIB_DATA0_P HDMIB_DATA0_N HDMIB_CK_P HDMIB_CK_N DDSP_1_HPD0 DPB_CTRL_CK DPB_CTRL_DATA

I

XU1H

Haswell rPGA

T28

DDIB_TXBN_0

U28

DDIB_TXBP_0

T30

DDIB_TXBN_1

U30

DDIB_TXBP_1

U29

DDIB_TXBN_2

V29

DDIB_TXBP_2

U31

DDIB_TXBN_3

V31

DDIB_TXBP_3

T34

DDIC_TXCN_0

U34

DDIC_TXCP_0

U35

DDIC_TXCN_1

V35

DDIC_TXCP_1

U32

DDIC_TXCN_2

T32

DDIC_TXCP_2

U33

DDIC_TXCN_3

V33

DDIC_TXCP_3

P29

DDID_TXDN_0

R29

DDID_TXDP_0

N28

DDID_TXDN_1

P28

DDID_TXDP_1

P31

DDID_TXDN_2

R31

DDID_TXDP_2

N30

DDID_TXDN_3

P30

DDID_TXDP_3

SOCKET_ 947P

HDMIC_TX2_DP HDMIC_TX2_DN HDMIC_TX1_DP HDMIC_TX1_DN HDMIC_TX0_DP HDMIC_TX0_DN HDMIC_CLK_DP HDMIC_CLK_DN DDSP_2_HPD1 DPC_CTRL_CK DPC_CTRL_DATA

HDMID_TX2_DP HDMID_TX2_DN HDMID_TX1_DP HDMID_TX1_DN HDMID_TX0_DP HDMID_TX0_DN HDMID_CLK_DP HDMID_CLK_DN DDSP_3_HPD2 DPD_CTRL_CK DPD_CTRL_DATA

DDI

Processor DDI Pins

DDIB_TXP0 DDIB_TXN0 DDIB_TXP1 DDIB_TXBN1 DDIB_TXBP2 DDIB_TXBN2 DDIB_TXBP3 DDIB_TXBN3 Hot plug detect used by HDMI Port B HDMI DDC lines for Port B HDMI DDC lines for Port B

DDIC_TXP0 DDIC_TXN0 DDIC_TXP1 DDIC_TXBN1 DDIC_TXBP2 DDIC_TXBN2 DDIC_TXBP3 DDIC_TXBN3 Hot plug detect used by HDMI Port C HDMI DDC lines for Port C HDMI DDC lines for Port C

DDID_TXP0 DDID_TXN0 DDID_TXP1 DDID_TXBN1 DDID_TXBP2 DDID_TXBN2 DDID_TXBP3 DDID_TXBN3 Hot plug detect used by HDMI Port D HDMI DDC lines for Port D HDMI DDC lines for Port D

EDP_AUXP

EDP_HPD

FDI_TXN_0 FDI_TXP_0 FDI_TXN_1 FDI_TXP_1

M27 N27 P27 E24 R27

P35 R35 N34 P34 P33 R33 N32 P32

EDP_DISP_UTIL

eDP

EDP_AUXN

EDP_RCOMP

EDP_TXN_0 EDP_TXP_0 EDP_TXN_1 EDP_TXP_1

FDI_TXN0 19 FDI_TXP0 19 FDI_TXN1 19 FDI_TXP1 19

PEGATRON DT-MB RESTRICTED SECRET

CPU_DMI,FDI,PEG,DDI

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

5

4

3

2

Date: Sheet of

IMPLP-MS

Engineer:

CPU_DMI,FDI,PEG,DDI

1

Stonko_Chen

8 83Thursday, June 27 , 2013

Rev

A00

5

D D

+1P05V_ PCH

NI

HR134 0

PROCHOT _SIO#36

PROCHOT #64,76

H_THRMT RIP#23

C C

B B

PECI_SIO23,36

PM_DRAM _PWRGD19

H_PM_SYNC19

PLTRST_ CPU#23,50

H_CPUPW RGD2 3,50

1 2

+1P35V_ DUAL +1V_CPUIOOU T

12

I

HR3

1.8K

12

I

HR4

3.3K

+1V_CPU IOOUT +1P05V_PCH

12

NI

HR126 0

12

NI

HC105 47PF/50V

NPO 5%

GND

12

NI

HR130

4.7K

12

NI

HR128 47PF/50V

NPO 5%

4

12

I

HR1 62

HR2 56

I

HR127 43

I

Close to SIO Side

1 2

12

NOBOM

12

1 2

I

HR132 0

I

HR6 10K

HT7

HT8

NI

HR125 0

PM_DRAM _PWRGD_R

1

H_PROCH OT#_D

AP32

AN32

AK31

AM30

AM35

AR27

AC10

AT28

AT26

AL34

I

XU1B

Haswell rPGA

SKTOCC#

CATERR#

THERMAL

FC1

PROCHOT#

THERMTRIP#

PECI

SM_DRAMPWROK

PM_SYNC

PLTRSTIN#

PWRGOOD

MISC

PWR

3

AP3

SM_RCOMP_0

SM_RCOMP_1

SM_RCOMP_2

AR3

AP2

SM_RCOM P0

SM_RCOM P1

SM_RCOM P2

DDR3

BPM_N_0

BPM_N_1

BPM_N_2

BPM_N_3

BPM_N_4

BPM_N_5

BPM_N_6

BPM_N_7

PRDY#

PREQ#

TDO

TMS

TRST#

TCK

AN3

AR30

AN31

AN29

H_BPM2

AP31

H_BPM3

AP30

H_BPM4

AN28

H_BPM5

AP29

H_BPM6

AP28

H_BPM7

AR29

AT29

AM31

TDI

AL33

AN33

AM33

AM34

1

12

I

SR133 51

SM_DRAMRST#

JTAG

2

1 2

HR7 100 1%

I

1 2

HR8 75 1 %

I

1 2

HR9 100 1%

I

HT1

NOBOM

HT2

NOBOM

HT3

NOBOM

HT4

NOBOM

HT5

NOBOM

HT6

NOBOM

12

I

SR134 51

SM_DRAM RST# 15,16

+1P05V_ PCH

12

I

SR135 51

1

GND

XDP_BPM 0 50

XDP_BPM 1 50

H_PRDY# 50

H_PREQ# 50

TDI 5 0

TDO 50

TMS 50

TRST# 50

TCK 50

GND GNDGND

CLK_DPN S_N20

CLK_DPN S_P20

CLK_DP_ N20 CLK_DP_ P20

CLK_DMI_N20

CLK_DMI_P20

A A

CRB

G28

DPLL_REF_CLKN

H28

DPLL_REF_CLKP

F27

SSC_DPLL_REF_CLKN

E27

SSC_DPLL_REF_CLKP

D26

BCLKN

E26

BCLKP

SOCKET_ 947P

CLOCK

DBR#

AP33

OD

GND GND

SYS_RESET # 19 ,50,51

PEGATRON DT-MB RESTRICTED SECRET

CPU_CLK,MISC,JTAG

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

IMPLP-MS

CPU_CLK,MISC,JTAG

1

Stonko_Chen

9 83Thursday, June 27 , 2013

Rev

A00

5

M_CHA_D Q[0..63]15 M_CHA_M AA[0..15] 15

M_CHA_D QS015 M_CHA_D QS0#15

D D

M_CHA_D QS115 M_CHA_D QS1#15

M_CHA_D QS215 M_CHA_D QS2#15

C C

M_CHA_D QS315 M_CHA_D QS3#15

M_CHA_D QS415 M_CHA_D QS4#15

B B

A A

5

M_CHA_D QS515 M_CHA_D QS5#15

M_CHA_D QS615 M_CHA_D QS6#15

M_CHA_D QS715 M_CHA_D QS7#15

4

M_CHA_D QS0 M_CHA_D QS0#

M_CHA_D Q0 M_CHA_D Q1 M_CHA_D Q2 M_CHA_D Q3 M_CHA_D Q4 M_CHA_D Q5 M_CHA_D Q6 M_CHA_D Q7

M_CHA_D QS1 M_CHA_D QS1#

M_CHA_D Q8 M_CHA_D Q9 M_CHA_D Q10 M_CHA_D Q11 M_CHA_D Q12 M_CHA_D Q13 M_CHA_D Q14 M_CHA_D Q15

M_CHA_D QS2 M_CHA_D QS2#

M_CHA_D Q16 M_CHA_D Q17 M_CHA_D Q18 M_CHA_D Q19 M_CHA_D Q20 M_CHA_D Q21 M_CHA_D Q22 M_CHA_D Q23

M_CHA_D QS3 M_CHA_D QS3#

M_CHA_D Q24 M_CHA_D Q25 M_CHA_D Q26 M_CHA_D Q27 M_CHA_D Q28 M_CHA_D Q29 M_CHA_D Q30 M_CHA_D Q31

M_CHA_D QS4 M_CHA_D QS4#

M_CHA_D Q32 M_CHA_D Q33 M_CHA_D Q34 M_CHA_D Q35 M_CHA_D Q36 M_CHA_D Q37 M_CHA_D Q38 M_CHA_D Q39

M_CHA_D QS5 M_CHA_D QS5#

M_CHA_D Q40 M_CHA_D Q41 M_CHA_D Q42 M_CHA_D Q43 M_CHA_D Q44 M_CHA_D Q45 M_CHA_D Q46 M_CHA_D Q47

M_CHA_D QS6 M_CHA_D QS6#

M_CHA_D Q48 M_CHA_D Q49 M_CHA_D Q50 M_CHA_D Q51 M_CHA_D Q52 M_CHA_D Q53 M_CHA_D Q54 M_CHA_D Q55

M_CHA_D QS7 M_CHA_D QS7#

M_CHA_D Q56 M_CHA_D Q57 M_CHA_D Q58 M_CHA_D Q59 M_CHA_D Q60 M_CHA_D Q61 M_CHA_D Q62 M_CHA_D Q63

4

AP14 AP15

AR15

AT14 AM14 AN14

AT15 AR14 AN15 AM15

AP9 AP8

AM9 AN9 AM8 AN8 AR9 AT9 AR8 AT8

AK8

AK9

AK6

AJ10 AK10

AK7

AG3 AF3

AF4 AF5 AF1 AF2 AG4 AG5 AG1 AG2

C12 C11

E12 D12 B11 A11 E11 D11 B12 A12

AJ8

AJ9

AJ6

AJ7

H3

J3

J1 J2

J5 H5 H2 H1

J4 H4

E3 E2

F2 F1 D2 D3 D1 F3 C3 B3

C6 C5

B5 E6 A5 D6 D5 E5 B6 A6

I

XU1C

Haswell rPGA

SA_DQS_P_0 SA_DQS_N_0

SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7

SA_DQS_P_1 SA_DQS_N_1

SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15

SA_DQS_P_2 SA_DQS_N_2

SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23

SA_DQS_P_3 SA_DQS_N_3

SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31

SA_DQS_P_4 SA_DQS_N_4

SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39

SA_DQS_P_5 SA_DQS_N_5

SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47

SA_DQS_P_6 SA_DQS_N_6

SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55

SA_DQS_P_7 SA_DQS_N_7

SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63

SOCKET_ 947P

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14 SA_MA_15

SA_WE# SA_CAS# SA_RAS#

SA_BS_0 SA_BS_1 SA_BS_2

SA_CS_N_0 SA_CS_N_1 SA_CS_N_2 SA_CS_N_3

SA_CKE_0 SA_CKE_1 SA_CKE_2 SA_CKE_3

SA_ODT_0 SA_ODT_1 SA_ODT_2 SA_ODT_3

SA_CK_P_0 SA_CK_N_0 SA_CK_P_1 SA_CK_N_1 SA_CK_P_2 SA_CK_N_2 SA_CK_P_3 SA_CK_N_3

SM_VREF SA_DIMM_VREFDQ SB_DIMM_VREFDQ

RSVD_AC7

VSS1

3

V8 AC6 V9 U9 AC5 AC4 AD6 AC3 AD5 AC2 V6 AC1 AD4 V7 AD3 AD2

U7 U8 U6

V5 U5 AD1

M7 L9 M9 M10

AD9 AC9 AD8 AC8

M8 L7 L8 L10

V4 U4 V3 U3 V2 U2 V1 U1

AM3 F16 F13

AC7

V10

3

M_CHA_M AA0 M_CHA_M AA1 M_CHA_M AA2 M_CHA_M AA3 M_CHA_M AA4 M_CHA_M AA5 M_CHA_M AA6 M_CHA_M AA7 M_CHA_M AA8 M_CHA_M AA9 M_CHA_M AA10 M_CHA_M AA11 M_CHA_M AA12 M_CHA_M AA13 M_CHA_M AA14 M_CHA_M AA15

M_CHA_W E# 1 5 M_CHA_C AS# 15 M_CHA_R AS# 15

M_CHA_B A0 15 M_CHA_B A1 15 M_CHA_B A2 15

M_CHA_C S#0 1 5 M_CHA_C S#1 1 5

M_CHA_C KE0 15 M_CHA_C KE1 15

M_CHA_O DT0 15 M_CHA_O DT1 15

M_CHA_C LK0 1 5 M_CHA_C LK0# 15 M_CHA_C LK1 1 5 M_CHA_C LK1# 15

CPU_SM_ VREF CPU_SA_ DIMM_VREFDQ CPU_SB_ DIMM_VREFDQ

RSVD_AC 7

1

GND

HT9

NOBOM

2

I

D3C13

0.1UF/16V

X7R 10%

I

D3R17

24.9

1%

12

SA_VDQ_RC

12

2

I

D3C14

0.1UF/16V

X7R 10%

I

D3R18

24.9

1%

12

SB_VDQ_RC

12

GND GND GND

1 2

D3R14 0Imx_r0603

1 2

D3R15 0Imx_r0603

1 2

D3R16 0Imx_r0603

12

I

D3C15

0.1UF/16V

SM_VREF_RC

X7R 10%

12

I

D3R19

24.9

1%

Close to DIMM Side

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

+1P35V_ DUAL

12

I

D3R4 1K

1%

12

I

D3R11 1K

1%

GND

IMPLP-MS

1

DIMM_CA_V REF_AB 15,16 DIMM_DQ_V REF_A 15 DIMM_DQ_V REF_B 16

Title :

Engineer:

1

CPU_DDR3_A

Stonko_Chen

10 83Thursday, June 27, 2013

Rev

A00

5

M_CHB_D Q[0..63]16

M_CHB_D QS016 M_CHB_D QS0#16

D D

M_CHB_D QS116 M_CHB_D QS1#16

M_CHB_D QS216 M_CHB_D QS2#16

C C

B B

A A

5

M_CHB_D QS316 M_CHB_D QS3#16

M_CHB_D QS416 M_CHB_D QS4#16

M_CHB_D QS516 M_CHB_D QS5#16

M_CHB_D QS616 M_CHB_D QS6#16

M_CHB_D QS716 M_CHB_D QS7#16

4

I

XU1D

Haswell rPGA

M_CHB_D QS0 M_CHB_D QS0#

M_CHB_D Q0 M_CHB_D Q1 M_CHB_D Q2 M_CHB_D Q3 M_CHB_D Q4 M_CHB_D Q5 M_CHB_D Q6 M_CHB_D Q7

M_CHB_D QS1 M_CHB_D QS1#

M_CHB_D Q8 M_CHB_D Q9 M_CHB_D Q10 M_CHB_D Q11 M_CHB_D Q12 M_CHB_D Q13 M_CHB_D Q14 M_CHB_D Q15

M_CHB_D QS2 M_CHB_D QS2#

M_CHB_D Q16 M_CHB_D Q17 M_CHB_D Q18 M_CHB_D Q19 M_CHB_D Q20 M_CHB_D Q21 M_CHB_D Q22 M_CHB_D Q23

M_CHB_D QS3 M_CHB_D QS3#

M_CHB_D Q24 M_CHB_D Q25 M_CHB_D Q26 M_CHB_D Q27 M_CHB_D Q28 M_CHB_D Q29 M_CHB_D Q30 M_CHB_D Q31

M_CHB_D QS4 M_CHB_D QS4#

M_CHB_D Q32 M_CHB_D Q33 M_CHB_D Q34 M_CHB_D Q35 M_CHB_D Q36 M_CHB_D Q37 M_CHB_D Q38 M_CHB_D Q39

M_CHB_D QS5 M_CHB_D QS5#

M_CHB_D Q40 M_CHB_D Q41 M_CHB_D Q42 M_CHB_D Q43 M_CHB_D Q44 M_CHB_D Q45 M_CHB_D Q46 M_CHB_D Q47

M_CHB_D QS6 M_CHB_D QS6#

M_CHB_D Q48 M_CHB_D Q49 M_CHB_D Q50 M_CHB_D Q51 M_CHB_D Q52 M_CHB_D Q53 M_CHB_D Q54 M_CHB_D Q55

M_CHB_D QS7 M_CHB_D QS7#

M_CHB_D Q56 M_CHB_D Q57 M_CHB_D Q58 M_CHB_D Q59 M_CHB_D Q60 M_CHB_D Q61 M_CHB_D Q62 M_CHB_D Q63

4

AP17 AP18

AR18

AT18 AM17 AM18 AR17

AT17 AN17 AN18

AP12 AP11

AT12 AR12 AN12 AM11

AT11 AR11 AM12 AN11

AP6 AP5

AR5 AR6 AM5 AM6 AT5 AT6 AN5 AN6

AK3

AJ3

AJ4

AK4

AJ1

AJ2 AM1 AN1 AK2 AK1

G10

C15 C14

E15

D15

A15

B15

E14

D14

A14

B14

M3

L3

L2

M2

L4

M4

L1

M1

L5

M5

H8 H9

G7

J8 G8 G9

J7

J9

J10

C9 C8

A8 B8 A9 B9 D8 E8 D9 E9

SB_DQS_P_0 SB_DQS_N_0

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7

SB_DQS_P_1 SB_DQS_N_1

SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15

SB_DQS_P_2 SB_DQS_N_2

SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23

SB_DQS_P_3 SB_DQS_N_3

SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31

SB_DQS_P_4 SB_DQS_N_4

SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39

SB_DQS_P_5 SB_DQS_N_5

SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47

SB_DQS_P_6 SB_DQS_N_6

SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55

SB_DQS_P_7 SB_DQS_N_7

SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

SOCKET_ 947P

3

R8 Y5 Y10 AA5 Y7 AA6 Y6 AA7 Y8 AA10 R9 Y9 AF7 P9 AA8 AG7

P6 P7 R6

R7 P8 AA9

P4 R2 P3 P1

AF10 AG10 AG9 AF9

R4 R3 R1 P2

AA4 Y4 AA3 Y3 AA2 Y2 AA1 Y1

AG8

R10

M_CHB_M AA0 M_CHB_M AA1 M_CHB_M AA2 M_CHB_M AA3 M_CHB_M AA4 M_CHB_M AA5 M_CHB_M AA6 M_CHB_M AA7 M_CHB_M AA8 M_CHB_M AA9 M_CHB_M AA10 M_CHB_M AA11 M_CHB_M AA12 M_CHB_M AA13 M_CHB_M AA14 M_CHB_M AA15

RSVD1

GND

M_CHB_W E# 1 6 M_CHB_C AS# 16 M_CHB_R AS# 16

M_CHB_B A0 16 M_CHB_B A1 16 M_CHB_B A2 16

M_CHB_C S#0 1 6 M_CHB_C S#1 1 6

M_CHB_C KE0 16 M_CHB_C KE1 16

M_CHB_O DT0 16 M_CHB_O DT1 16

M_CHB_C LK0 1 6 M_CHB_C LK0# 16 M_CHB_C LK1 1 6 M_CHB_C LK1# 16

1

HT10

NOBOM

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14 SB_MA_15

SB_WE# SB_CAS# SB_RAS#

SB_BS_0 SB_BS_1 SB_BS_2

SB_CS_N_0 SB_CS_N_1 SB_CS_N_2 SB_CS_N_3

SB_CKE_0 SB_CKE_1 SB_CKE_2 SB_CKE_3

SB_ODT_0 SB_ODT_1 SB_ODT_2 SB_ODT_3

SB_CK0

SB_CKN0

SB_CK1

SB_CKN1

SB_CK2

SB_CKN2

SB_CK3

SB_CKN3

RSVD1

VSS2

3

2

M_CHB_M AA[0..15] 16

2

1

PEGATRON DT-MB RESTRICTED SECRET

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

IMPLP-MS

Engineer:

1

CPU_DDR3_B

Stonko_Chen

11 83Thursday, June 27, 2013

Rev

A00

5

+VCORE

D D

VCC_SEN SE76

PIN A23 = FC_A23

+1P05V_ PCH

12

NI

HR131 0

mx_r0805

FC_A23

+1P05V_ PCH

12

I

HR24 150

12

GND

I

HR31 75

1%

12

1%

NI

HR25 10K

+1V_CPU IOOUT

I

HR34 43

1 2

+1P35V_ DUAL

+VCOMP_ OUT

CPU_VIDAL ERT#

C C

B B

A A

XDP_PW R_DEBUG5 0

+1V_CPU IOOUT

VIDALERT#76 VIDSCLK76

VIDSOUT76

12

I

HR30 130

+1V_CPU IOOUT

GND

AB25 AB29 AB26 AA32 AA30 AA34 AA28 AA26 AG32 AG30

AL35

W32 AL16 AL13

AK27

AL27

AB11

AE11

AH11

W11

AN35

AT35

AR35 AR32

AL26

AM28 AM29

AL28

AP35 AP34

AT34 AL22 AT33

AM21 AM25 AM22 AM20 AM24

AL19

AM23

AT32

K26

E17

A23

K27

T27 V27 N26

H27

AB2 AB5 AB8

AE2 AE5 AE8

K11 N11

T11

F22

J27

L27

N8

T2 T5 T8

W2 W5 W8

4

I

XU1E

Haswell rPGA

VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100 VCC101 VCC102 VCC103

VCC_SENSE

RSVD30 RSVD29 RSVD28 RSVD27 RSVD26 RSVD25 RSVD24 RSVD23 RSVD22 RSVD21 RSVD20 RSVD19 RSVD18

PWR_DEBUG

VDDQ13 VDDQ12 VDDQ11 VDDQ10 VDDQ9 VDDQ8 VDDQ7 VDDQ6 VDDQ14 VDDQ15 VDDQ5 VDDQ16 VDDQ4 VDDQ17 VDDQ3 VDDQ18 VDDQ2 VDDQ19 VDDQ1 VDDQ20

VCOMP_OUT

VCCIO_OUT

RSVD_TP4 RSVD_TP3 RSVD_TP2 RSVD_TP1

VIDALERT# VIDSCLK VIDSOUT

VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15

SOCKET_ 947P

VCC92 VCC91 VCC90 VCC89 VCC88 VCC87 VCC86 VCC85 VCC84 VCC83 VCC82 VCC81 VCC80 VCC79 VCC78 VCC77 VCC76 VCC75 VCC74 VCC73 VCC72 VCC71 VCC70 VCC69 VCC68 VCC67 VCC66 VCC65 VCC64 VCC63 VCC62 VCC61 VCC60 VCC59 VCC58 VCC57 VCC56 VCC55 VCC54 VCC53 VCC52 VCC51 VCC50 VCC49 VCC48 VCC47 VCC46 VCC45 VCC44 VCC43 VCC42 VCC41 VCC40 VCC39 VCC38 VCC37 VCC36 VCC35 VCC34 VCC33 VCC32 VCC31 VCC30 VCC29 VCC28 VCC27 VCC26 VCC25 VCC24 VCC23 VCC22 VCC21 VCC20 VCC19 VCC18 VCC17 VCC16 VCC15 VCC14 VCC13 VCC12 VCC11 VCC10

VCC9 VCC8 VCC7 VCC6 VCC5 VCC4 VCC3 VCC2 VCC1

AB27 AB28 AB30 AB31 AB33 AB34 AB32 AC26 AB35 AC28 AD25 AC30 AD28 AC32 AD31 AC34 AD34 AD26 AD27 AD29 AD30 AD32 AD33 AD35 AE26 AE32 AE28 AE30 AG28 AG34 AE34 AF25 AF26 AF27 AF28 AF29 AF30 AF31 AF32 AF33 AF34 AF35 AG26 AH26 AH29 AH32 AH35 AH25 AH27 AH28 AH30 AH31 AH33 AH34 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AJ31 AJ32 AJ33 AJ34 AJ35 G25 H25 J25 K25 L25 M25 N25 P25 R25 T25 U25 U26 V25 V26 W26 W27 Y25 Y26 Y27 Y28 Y29 Y30 Y31 Y32 Y33 Y34 Y35

+VCORE

3

Output CAP

+VCORE

I

12

+VCORE

12

+VCORE

12

+VCORE

12

GND

+

12

PC294 22UF/6.3V

X5R 20% mx_c0805_ small

I

12

PC350 22UF/6.3V

X5R 20% mx_c0805_ small

I

12

PC308 22UF/6.3V

X5R 20% mx_c0805_ small

I

PCE2 330UF/2.5 V

ESR=9mO hm/Ir=3900mA

I

PC299 22UF/6.3V

X5R 20% mx_c0805_ small

I

PC352 22UF/6.3V

X5R 20% mx_c0805_ small

I

PC312 22UF/6.3V

X5R 20% mx_c0805_ small

12

I

+

PCE3 330UF/2.5 V

ESR=9mO hm/Ir=3900mA

GND

I

12

PC303 22UF/6.3V

X5R 20% mx_c0805_ small

I

12

PC284 22UF/6.3V

X5R 20% mx_c0805_ small

I

12

PC314 22UF/6.3V

X5R 20% mx_c0805_ small

I

12

PC304 22UF/6.3V

X5R 20% mx_c0805_ small

I

12

PC285 22UF/6.3V

X5R 20% mx_c0805_ small

I

12

PC342 22UF/6.3V

X5R 20% mx_c0805_ small

2

I

12

PC305 22UF/6.3V

X5R 20% mx_c0805_ small

I

12

PC286 22UF/6.3V

X5R 20% mx_c0805_ small

I

12

PC343 22UF/6.3V

X5R 20% mx_c0805_ small

I

12

PC306 22UF/6.3V

X5R 20% mx_c0805_ small

I

12

PC287 22UF/6.3V

X5R 20% mx_c0805_ small

I

12

PC344 22UF/6.3V

X5R 20% mx_c0805_ small

I

12

PC307 22UF/6.3V

X5R 20% mx_c0805_ small

I

12

PC288 22UF/6.3V

X5R 20% mx_c0805_ small

I

12

PC346 22UF/6.3V

X5R 20% mx_c0805_ small

I

12

PC309 22UF/6.3V

X5R 20% mx_c0805_ small

I

12

PC289 22UF/6.3V

X5R 20% mx_c0805_ small

I

12

PC347 22UF/6.3V

X5R 20% mx_c0805_ small

I

12

PC310 22UF/6.3V

X5R 20% mx_c0805_ small

I

12

PC291 22UF/6.3V

X5R 20% mx_c0805_ small

I

12

PC348 22UF/6.3V

X5R 20% mx_c0805_ small

1

I

12

PC311 22UF/6.3V

X5R 20% mx_c0805_ small

GND

I

12

PC292 22UF/6.3V

X5R 20% mx_c0805_ small

GND

I

12

PC349 22UF/6.3V

X5R 20% mx_c0805_ small

GND

PEGATRON DT-MB RESTRICTED SECRET

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

5

4

3

2

Date: Sheet of

IMPLP-MS

Engineer:

1

CPU_POWER

Stonko_Chen

12 83Thursday, June 27, 2013

Rev

A00

5

4

3

2

1

CFG[19:0] (default value of '1' if not terminated on the board.) [our setting = *]

CFG[2]: PCI Express* Static x16 Lane Numbering Reversal.

— 1 = Normal operation (*)

D D

— 0 = Lane numbers reversed

CFG[3]: MSR Privacy Bit Feature

— 1 = Debug capability is determined by IA32_Debug_Interface_MSR (0xC80) bit[0] setting (*) — 0 = IA32_Debug_Interface_MSR (0xC80) bit[0] default setting overridden

CFG[4]: eDP enable

— 1 = Disabled (*) — 0 = Enabled

CFG[6:5]: PCI Express* Bifurcation:

— 00 = 1 x8, 2 x4 PCI Express* — 01 = reserved — 10 = 2 x8 PCI Express* — 11 = 1 x16 PCI Express*(*)

CFG[1:0] ; CFG[19:7] Reserved configuration lanes. Need test point

I

XU1I

AR1 D23 D24

C23

C35

AT2

AT1 W29 W28

AL25

W30 W31

E20 E21

B23

B35

A35 A34

Haswell rPGA

RSVD_TP5 RSVD_TP6 RSVD_TP7 RSVD_TP8 RSVD_TP9 RSVD_TP10 RSVD_TP11 RSVD_TP12 RSVD_TP13 RSVD_TP14 RSVD_TP15 RSVD_TP16 RSVD_TP17 RSVD_TP18 RSVD_TP19 RSVD_TP20 RSVD_TP21 RSVD_TP22

VCC104

CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8

CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15

CFG_17 CFG_16

CFG_19 CFG_18

C C

B B

NOBOM NOBOM NOBOM NOBOM NOBOM NOBOM NOBOM NOBOM NOBOM NOBOM NOBOM NOBOM NOBOM NOBOM NOBOM NOBOM NOBOM NOBOM

HT81 HT69 HT68 HT65 HT66 HT67 HT64 HT63 HT78 HT73 HT72 HT70 HT71 HT79 HT77 HT76 HT74 HT75

1

CPU_RSV D_TP5

1

CPU_RSV D_TP6

1

CPU_RSV D_TP7

1

CPU_RSV D_TP8

1

CPU_RSV D_TP9

1

CPU_RSV D_TP10

1

CPU_RSV D_TP11

1

CPU_RSV D_TP12

1

CPU_RSV D_TP13

1

CPU_RSV D_TP14

1

CPU_RSV D_TP15

1

CPU_RSV D_TP16

1

CPU_RSV D_TP17

1

CPU_RSV D_TP18

1

CPU_RSV D_TP19

1

CPU_RSV D_TP20

1

CPU_RSV D_TP21

1

CPU_RSV D_TP22

F25

AT20 AR20 AP20 AP22 AT22 AN22 AT25 AN23 AR24 AT23 AN20 AP24 AP26 AN25 AN26 AP25

AP21 AR21

AP23 AR23

+VCORE

CPU_CFG 0 CPU_CFG 1 CPU_CFG 2 CPU_CFG 3 CPU_CFG 4 CPU_CFG 5 CPU_CFG 6 CPU_CFG 7 CPU_CFG 8 CPU_CFG 9 CPU_CFG 10 CPU_CFG 11 CPU_CFG 12 CPU_CFG 13 CPU_CFG 14 CPU_CFG 15

OBSFN_C 0 5 0 OBSFN_C 1 5 0

OBSFN_D 0 5 0 OBSFN_D 1 5 0

1 2

HR38 1K

NI

1 2

HR39 1K

NI

1 2

HR40 1K

NI

1 2

HR41 1K

NI

1 2

HR42 1K

NI

1 2

HR43 1K

NI

CPU_CFG [0..15] 50

GND

W33, AR26, AP27 = GND

AT31

FC2

NC

H_CFG_R COMP

W34

CPU_TES TLOW2

G26

CPU_TES TLOW1

G6

CPU_FC2 _PWROK

B1

AL31 AL32

GND

1

HT80

NOBOM

HT83

NOBOM

HT84

NOBOM

HT85

NOBOM

HT86

NOBOM

HT87

NOBOM

HT88

NOBOM

HT89

NOBOM

HT90

NOBOM

HT91

NOBOM

HT92

NOBOM

HT93

NOBOM

HT94

NOBOM

GND

A A

CPU_RSV D2

1

CPU_RSV D4

1

CPU_RSV D5

1

CPU_RSV D6

1

CPU_RSV D7

1

CPU_RSV D8

1

CPU_RSV D9

1

CPU_RSV D10

1

CPU_RSV D11

1

CPU_RSV D12

1

CPU_RSV D13

1

CPU_RSV D14

1

CPU_RSV D15

AD10

W33 AL30 AL29

AR33 AM27 AM26

AM2

E18 U10 P10

AP27 AR26

F5

K6

A2

RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17

SOCKET_ 947P

CFG_RCOMP

TESTLO2 TESTLO1

VSS258 VSS259

1 2

HR56 49.9 1%

I

1 2

HR57 49.9 1%

I

1 2

HR58 49.9 1%

I

1 2

NI

HR59 2K

1%

GND

12

NI

HR60 1K

1%

GND

PWRO K 19,36

PEGATRON DT-MB RESTRICTED SECRET

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

5

4

3

2

Date: Sheet of

IMPLP-MS

Engineer:

1

CPU_CFG

Stonko_Chen

13 83Thursday, June 27, 2013

Rev

A00

5

D D

C C

B B

A A

A10 A13 A16 A19 A22 A25 A27 A29

A31 A33

AA11 AA25 AA27 AA31 AA29

AB1 AB10 AA33 AA35

AB3 AC25 AC27

AB4

AB6

AB7

AB9 AC11 AD11 AC29 AC31 AC33 AC35

AD7

AE1 AE10 AE25 AE29

AE3 AE27 AE35

AE4

AE6

AE7

AE9

AF11

AF6

AF8 AG11 AG25 AE31 AG31 AE33

AG6

AH1 AH10

AH2 AG27 AG29

AH3 AG33 AG35

AH4

AH5

AH6

AH7

AH8

AH9

AJ11

AJ5 AK11 AK25 AK26 AK28 AK29 AK30 AK32

E19

GND GNDGND GND

I

XU1F

Haswell rPGA

VSS16 VSS127 VSS238 VSS268 VSS279 VSS290 VSS301 VSS312

A3

VSS323 VSS17 VSS28

A4

VSS39

A7

VSS50 VSS61 VSS72 VSS83 VSS94 VSS105 VSS116 VSS128 VSS139 VSS150 VSS161 VSS172 VSS183 VSS194 VSS205 VSS216 VSS227 VSS239 VSS250 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS286 VSS287 VSS288 VSS289 VSS291 VSS292 VSS293 VSS294 VSS295 VSS296 VSS297 VSS298 VSS299 VSS300 VSS302 VSS303 VSS304 VSS305 VSS306 VSS307 VSS308 VSS309 VSS310 VSS311 VSS313

SOCKET_ 947P

4

AK34

VSS314

AK5

VSS315

AL1

VSS316

AL10

VSS317

AL11

VSS318

AL12

VSS319

AL14

VSS320

AL15

VSS321

AL17

VSS322

AL18

VSS324

AL2

VSS325

AL20

VSS326

AL21

VSS327

AL23

VSS328

E22

VSS329

AL3

VSS330

AL4

VSS331

AL5

VSS332

AL6

VSS333

AL7

VSS18

AL8

VSS19

AL9

VSS20

AM10

VSS21

AM13

VSS22

AM16

VSS23

AM19

VSS24

E25

VSS25

AM32

VSS26

AM4

VSS27

AM7

VSS29

AN10

VSS30

AN13

VSS31

AN16

VSS32

AN19

VSS33

AN2

VSS34

AN21

VSS35

AN24

VSS36

AN27

VSS37

AN30

VSS38

AN34

VSS40

AN4

VSS41

AN7

VSS42

AP1

VSS43

AP10

VSS44

AP13

VSS45

AP16

VSS46

AP19

VSS47

AP4

VSS48

AP7

VSS49

W25

VSS51

AR10

VSS52

AR13

VSS53

AR16

VSS54

AR19

VSS55

AR2

VSS56

AR22

VSS57

AR25

VSS58

AR28

VSS59

AR31

VSS60

AR34

VSS62

AR4

VSS63

AR7

VSS64

AT10

VSS65

AT13

VSS66

AT16

VSS67

AT19

VSS68

AT21

VSS69

AT24

VSS70

AT27

VSS71

AT3

VSS73

AT30

VSS74

AT4

VSS75

AT7

VSS76

B10

VSS77

B13

VSS78

B16

VSS79

B19

VSS80

B2

VSS81

B22

VSS82

3

I

XU1G

Haswell rPGA

B34

B4 B7

C1 C10 C13 C16 C19

C2 C22 C24 C26 C28 C30 C32 C34

C4

C7 D10 D13 D16 D19 D22 D25 D27 D29 D31 D33 D35

D4

D7

E1 E10 E13 E16

E4

E7 F10 F11 F12 F14 F15 F17 F18 F20 F21 F23 F24 F26 F28 F30 F32 F34

F4

F6

F7

F8

F9

G1

G11

G2 G27 G29

G3 G31 G33 G35

G4

G5 H10 H26

H6

H7 J11 J26 J28 J30 J32 J34

J6

K1

SOCKET_ 947P

VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS173

VSS_SENSE

VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS234 VSS235 VSS236 VSS237 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257

RSVD31

K10 K2 K29 K3 K31 K33 K35 K4 K5 K7 K8 K9 L11 L26 L6 M11 M26 M28 M30 M32 M34 M6 N1 N10 N2 N29 N3 N31 N33 N35 N4 N5 N6 N7 N9 P11 P26 P5 R11 R26 R28 R30 R32 R34 R5 T1 T10 T29 T3 T31 T33 T35 T4 T6 T7 T9 U11 U27 V11 V28 V30 V32 V34 W1 W10 W3 W35 W4 W6 W7 W9 Y11 H11 AL24 F19 T26 AK35 AK33

2

1

VSS_SEN SE 76

NOBOM

H16 C138D13 8N

NOBOM

H18 C138D13 8N

I

X_BP

CPU

NOBOM

H17 C138D13 8N

NOBOM

H19 C138D13 8N

1

PEGATRON DT-MB RESTRICTED SECRET

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

5

4

3

2

Date: Sheet of

IMPLP-MS

Engineer:

1

CPU_GND

Stonko_Chen

14 83Thursday, June 27, 2013

Rev

A00

5

4

3

2

1

M_CHA_M AA[0..15]10

M_CHA_M AA0 M_CHA_M AA1

D D

C C

SMBus Slave Address: A0H

GND

B B

M_CHA_D QS710 M_CHA_D QS7#10 M_CHA_D QS610 M_CHA_D QS6#10 M_CHA_D QS510 M_CHA_D QS5#10 M_CHA_D QS410 M_CHA_D QS4#10 M_CHA_D QS310 M_CHA_D QS3#10 M_CHA_D QS210 M_CHA_D QS2#10 M_CHA_D QS110 M_CHA_D QS1#10 M_CHA_D QS010 M_CHA_D QS0#10

SMB_CLK _MAIN16,47,50,5 1 SMB_DAT A_MAIN16,47,50,5 1

M_CHA_M AA2 M_CHA_M AA3 M_CHA_M AA4 M_CHA_M AA5 M_CHA_M AA6 M_CHA_M AA7 M_CHA_M AA8 M_CHA_M AA9 M_CHA_M AA10 M_CHA_M AA11 M_CHA_M AA12 M_CHA_M AA13 M_CHA_M AA14 M_CHA_M AA15

M_CHA_C LK110 M_CHA_C LK1#10 M_CHA_C LK010 M_CHA_C LK0#10

M_CHA_C S#110 M_CHA_C S#010

M_CHA_O DT110 M_CHA_O DT010

M_CHA_W E#10 M_CHA_R AS#10 M_CHA_C AS#10

M_CHA_B A210 M_CHA_B A110 M_CHA_B A010

M_CHA_C KE110 M_CHA_C KE010

GND

I

DIMM1A

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12/BC#

119

A13

80

A14

78

A15

102

CK1

104

CK1#

101

CK0

103

CK0#

121

S1#

114

S0#

120

ODT1

116

ODT0

113

WE#

110

RAS#

115

CAS#

79

BA2

108

BA1

109

BA0

74

CKE1

73

CKE0

201

SA1

197

SA0

188

DQS7

186

DQS#7

171

DQS6

169

DQS#6

154

DQS5

152

DQS#5

137

DQS4

135

DQS#4

64

DQS3

62

DQS#3

47

DQS2

45

DQS#2

29

DQS1

27

DQS#1

12

DQS0

10

DQS#0

187

DM7

170

DM6

153

DM5

136

DM4

63

DM3

46

DM2

28

DM1

11

DM0

202

SCL

200

SDA

DDR3_DIMM _204P

0

1

2

3

4

5

6

7

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

RESET#

5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194

30

M_CHA_D Q2 M_CHA_D Q7 M_CHA_D Q3 M_CHA_D Q6 M_CHA_D Q1 M_CHA_D Q5 M_CHA_D Q0 M_CHA_D Q4

M_CHA_D Q11 M_CHA_D Q9 M_CHA_D Q14 M_CHA_D Q15 M_CHA_D Q10 M_CHA_D Q8 M_CHA_D Q13

M_CHA_D Q12 M_CHA_D Q21 M_CHA_D Q20 M_CHA_D Q23 M_CHA_D Q19 M_CHA_D Q16 M_CHA_D Q17 M_CHA_D Q18 M_CHA_D Q22

M_CHA_D Q24

M_CHA_D Q28

M_CHA_D Q30

M_CHA_D Q27

M_CHA_D Q25

M_CHA_D Q29

M_CHA_D Q26

M_CHA_D Q31 M_CHA_D Q38 M_CHA_D Q33 M_CHA_D Q37 M_CHA_D Q34 M_CHA_D Q36 M_CHA_D Q32 M_CHA_D Q35 M_CHA_D Q39

M_CHA_D Q46

M_CHA_D Q44

M_CHA_D Q43

M_CHA_D Q45

M_CHA_D Q40

M_CHA_D Q42

M_CHA_D Q47

M_CHA_D Q41 M_CHA_D Q49 M_CHA_D Q51 M_CHA_D Q50 M_CHA_D Q48 M_CHA_D Q52 M_CHA_D Q53 M_CHA_D Q55 M_CHA_D Q54

M_CHA_D Q60

M_CHA_D Q56

M_CHA_D Q62

M_CHA_D Q63

M_CHA_D Q58

M_CHA_D Q59

M_CHA_D Q61

M_CHA_D Q57

12

I

D3C11

0.1UF/16V

X7R 10%

0~7

8~15

16~23

24~31

32~39

40~47

48~55

56~63

M_CHA_D Q[0..63] 1 0

DIMM_CA_V REF_AB10,16 DIMM_DQ_V REF_A10

SM_DRAM RST# 9,16

+1P35V_ DUAL

12

I

D3R1 1K

1%

12

I

D3R2 1K

1%

GND GND

12

I

D3C1

0.1UF/16V

X7R 10%

+1P35V_ DUAL +1P35V_DUAL

GND

12

I

D3C2

0.1UF/16V

X7R 10%

GND

12

I

D3C16

4.7UF/6.3V

X5R 10% mx_c0603

I

DIMM1B

75

VDD1

81

VDD3

87

VDD5

93

VDD7

99

VDD9

105

VDD11

111

VDD13

117

VDD15

123

VDD17

2

VSS1

8

VSS3

13

VSS5

19

VSS7

25

VSS9

31

VSS11

37

VSS13

43

VSS15

48

VSS17

54

VSS19

60

VSS21

65

VSS23

71

VSS25

127

VSS27

133

VSS29

138

VSS31

144

VSS33

150

VSS35

155

VSS37

161

VSS39

167

VSS41

172

VSS43

178

VSS45

184

VSS47

189

VSS49

195

VSS51

198

EVENT#

125

TEST

77

NC1

122

NC2

126

VREFCA

1

VREFDQ

DDR3_DIMM _204P

VDD2 VDD4 VDD6

VDD8 VDD10 VDD12 VDD14 VDD16 VDD18

VSS2 VSS4 VSS6

VSS8 VSS10 VSS12 VSS14 VSS16 VSS18 VSS20 VSS22 VSS24 VSS26 VSS28 VSS30 VSS32 VSS34 VSS36 VSS38 VSS40 VSS42 VSS44 VSS46 VSS48 VSS50 VSS52

GND1 GND2

NP_NC1 NP_NC2

VTT1

VTT2

VDDSPD

76 82 88 94 100 106 112 118 124

3 9 14 20 26 32 38 44 49 55 61 66 72 128 134 139 145 151 156 162 168 173 179 185 190 196

207 208

205 206

GND

203 204

+3P3V

199

12

NI

D3C3

0.1UF/16V

X7R 10%

GND

+VTT_DD R

12

I

D3C4

0.1UF/16V

X7R 10%

GND GND

12

I

D3C5

4.7UF/6.3V

X5R 10% mx_c0603

H:8.0mm

GND

A A

PEGATRON DT-MB RESTRICTED SECRET

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

5

4

3

2

Date: Sheet of

IMPLP-MS

Engineer:

DDR3(1)_SO-DIMM0

Stonko_Chen

15 83Thursday, June 27, 2013

1

15 83Thursday, June 27, 2013

Rev

A00

5

4

3

2

1

VDD2 VDD4 VDD6

VDD8 VDD10 VDD12 VDD14 VDD16 VDD18

VSS2

VSS4

VSS6

VSS8

VSS10 VSS12 VSS14 VSS16 VSS18 VSS20 VSS22 VSS24 VSS26 VSS28 VSS30 VSS32 VSS34 VSS36 VSS38 VSS40 VSS42 VSS44 VSS46 VSS48 VSS50 VSS52

GND1 GND2

VTT1 VTT2

+1P35V_ DUAL+1P35V_ DUAL

76 82 88 94 100 106 112 118 124

3 9 14 20 26 32 38 44 49 55 61 66 72 128 134 139 145 151 156 162 168 173 179 185 190 196

207 208

205 206

GND

203 204

+3P3V

199

12

NI

D3C8

0.1UF/16V

X7R 10%

GND

+VTT_DD R

12

I

D3C9

0.1UF/16V

X7R 10%

GND GND

12

I

D3C10

4.7UF/6.3V

X5R 10% mx_c0603

+3P3V

GND

M_CHB_M AA[0..15]11

M_CHB_M AA0 M_CHB_M AA1 M_CHB_M AA2 M_CHB_M AA3 M_CHB_M AA4 M_CHB_M AA5 M_CHB_M AA6 M_CHB_M AA7 M_CHB_M AA8 M_CHB_M AA9 M_CHB_M AA10 M_CHB_M AA11 M_CHB_M AA12 M_CHB_M AA13 M_CHB_M AA14 M_CHB_M AA15

M_CHB_C LK111 M_CHB_C LK1#11 M_CHB_C LK011 M_CHB_C LK0#11

M_CHB_C S#111 M_CHB_C S#011

M_CHB_O DT111 M_CHB_O DT011

M_CHB_W E#11 M_CHB_R AS#11 M_CHB_C AS#11

M_CHB_B A211 M_CHB_B A111 M_CHB_B A011

M_CHB_C KE111 M_CHB_C KE011

M_CHB_D QS711 M_CHB_D QS7#11 M_CHB_D QS611 M_CHB_D QS6#11 M_CHB_D QS511 M_CHB_D QS5#11 M_CHB_D QS411 M_CHB_D QS4#11 M_CHB_D QS311 M_CHB_D QS3#11 M_CHB_D QS211 M_CHB_D QS2#11 M_CHB_D QS111 M_CHB_D QS1#11 M_CHB_D QS011 M_CHB_D QS0#11

GND

SMB_CLK _MAIN15,47,50,5 1 SMB_DAT A_MAIN15,47,50,5 1

D D

C C

B B

A A

I

DIMM2A

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90 86 89 85

107

84 83

119

80 78

102 104 101 103

121 114

120 116

113 110 115

79 108 109

74

73

201 197

188 186 171 169 154 152 137 135

64

62

47

45

29

27

12

10

187 170 153 136

63

46

28

11

202 200

0

A6 A7 A8 A9 A10/AP A11 A12/BC# A13

1

A14 A15

CK1 CK1# CK0 CK0#

2

S1# S0#

ODT1 ODT0

WE#

3

RAS# CAS#

BA2 BA1 BA0

CKE1

4

CKE0

SA1 SA0

DQS7

5

DQS#7 DQS6 DQS#6 DQS5 DQS#5 DQS4 DQS#4 DQS3 DQS#3

6

DQS2 DQS#2 DQS1 DQS#1 DQS0 DQS#0

DM7

7

DM6 DM5 DM4 DM3 DM2 DM1 DM0

SCL SDA

DDR3_DIMM _204P

H:4.0mm

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

RESET#

5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194

30

M_CHB_D Q5 M_CHB_D Q0 M_CHB_D Q4 M_CHB_D Q7 M_CHB_D Q3 M_CHB_D Q1 M_CHB_D Q2 M_CHB_D Q6

M_CHB_D Q8 M_CHB_D Q9 M_CHB_D Q15 M_CHB_D Q11 M_CHB_D Q14 M_CHB_D Q10 M_CHB_D Q12

M_CHB_D Q13 M_CHB_D Q17 M_CHB_D Q21 M_CHB_D Q18 M_CHB_D Q19 M_CHB_D Q20 M_CHB_D Q16 M_CHB_D Q23 M_CHB_D Q22

M_CHB_D Q29

M_CHB_D Q30

M_CHB_D Q27

M_CHB_D Q26

M_CHB_D Q31

M_CHB_D Q28

M_CHB_D Q25

M_CHB_D Q24 M_CHB_D Q37 M_CHB_D Q36 M_CHB_D Q38 M_CHB_D Q34 M_CHB_D Q32 M_CHB_D Q33 M_CHB_D Q39 M_CHB_D Q35

M_CHB_D Q41

M_CHB_D Q40

M_CHB_D Q47

M_CHB_D Q46

M_CHB_D Q45

M_CHB_D Q44

M_CHB_D Q43

M_CHB_D Q42 M_CHB_D Q53 M_CHB_D Q52 M_CHB_D Q49 M_CHB_D Q50 M_CHB_D Q48 M_CHB_D Q54 M_CHB_D Q51 M_CHB_D Q55

M_CHB_D Q56

M_CHB_D Q62

M_CHB_D Q63

M_CHB_D Q58

M_CHB_D Q61

M_CHB_D Q60

M_CHB_D Q59

M_CHB_D Q57

12

GND

0~7

8~15

16~23

24~31

32~39

40~47

48~55

56~63

I

D3C12

0.1UF/16V

X7R 10%

M_CHB_D Q[0..63] 1 1

DIMM_CA_V REF_AB10,15 DIMM_DQ_V REF_B10

SM_DRAM RST# 9,15

+1P35V_ DUAL

12

I

D3R6 1K

1%

12

I

D3R7 1K

1%

GND

12

GND

I

DIMM2B

75

VDD1

81

VDD3

87

VDD5

93

VDD7

99

VDD9

105

VDD11

111

VDD13

117

VDD15

123

VDD17

2

VSS1

8

VSS3

13

VSS5

19

VSS7

25

VSS9

31

VSS11

37

VSS13

43

VSS15

48

VSS17

54

VSS19

60

VSS21

65

VSS23

71

VSS25

127

VSS27

133

VSS29

138

VSS31

144

VSS33

150

VSS35

155

VSS37

161

VSS39

167

VSS41

172

VSS43

178

VSS45

184

VSS47

189

VSS49

195

VSS51

198

I

D3C6

0.1UF/16V

X7R 10%

GND

12

I

D3C7

0.1UF/16V

X7R 10%

EVENT#

125

TEST

77

NC1

122

NC2

126

VREFCA

1

VREFDQ

DDR3_DIMM _204P

NP_NC1 NP_NC2

VDDSPD

Layout Note: Place these caps near SO DIMM 1

PEGATRON DT-MB RESTRICTED SECRET

DDR3(2)_SO-DIMM1

1

DDR3(2)_SO-DIMM1

Stonko_Chen

16 83Thursday, June 27, 2013

Rev

A00

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

5

4

3

2

Date: Sheet of

IMPLP-MS

Engineer:

5

SO DIMM CHA DECOUPLING

+1P35V_ DUAL

4

3

2

1

12

I

D3CE6

D D

10UF/6.3V

X5R 10% mx_c0805_ small

GND GND GND GND GND GND GND GND

12

I

D3CE7 10UF/6.3V

X5R 10% mx_c0805_ small

12

NI

D3CE8 10UF/6.3V

X5R 10% mx_c0805_ small

12

NI

D3CE9 10UF/6.3V

X5R 10% mx_c0805_ small

12

I

D3CE13 1UF/6.3V

X5R 10%

12

I

D3CE14 1UF/6.3V

X5R 10%

12

NI

D3CE15 1UF/6.3V

X5R 10%

12

NI

D3CE16 1UF/6.3V

X5R 10%

NOTE:

Place those cap close to CH A DIMM0

SO DIMM CHB DECOUPLING

+1P35V_ DUAL

12

I

D3CE21 10UF/6.3V

X5R 10%

C C

mx_c0805_ small

GND GND

12

I

D3CE22 10UF/6.3V

X5R 10% mx_c0805_ small

12

NI

D3CE23 10UF/6.3V

X5R 10% mx_c0805_ small

GND GND GND GND GND GND

12

NI

D3CE24 10UF/6.3V

X5R 10% mx_c0805_ small

12

I

D3CE20 1UF/6.3V

X5R 10%

12

I

D3CE28 1UF/6.3V

X5R 10%

NI

D3CE29 1UF/6.3V

X5R 10%

12

NI

D3CE30 1UF/6.3V

X5R 10%

NOTE:

Place those cap close to CH B DIMM1

Processor VDDQ DECOUPLING

+1P35V_ DUAL

rPGA Processor VDDQ 1.5-V Rail Decoupling Location

12

I

+

D3CE33 330UF/2V

mx_c7343d _h79

B B

GND

+1P35V_ DUAL

GND

12

+

NI

D3CE34 330UF/2V

mx_c7343d _h79

NOTE:

Place those cap at MB Bottom Socket Edge

Bulk Decoupling Socket Edge Qty x uF (size) ESR MB Bottom Socket Edge 6x MB Bottom Socket Cavity

5x MB Top Socket Cavity

5x MB Bottom Socket Cavity 5x MB Top Socket Cavity

2 x 330 uF 11 x 22 uF

(0805)

10 x 10 uF (0805)

6 m Ohm

3 m Ohm

12

I

D3CE35 22UF/6.3V

X5R 20% mx_c0805_small

+1P35V_ DUAL

12

A A

I

D3CE46 22UF/6.3V

X5R 20% mx_c0805_small

12

I

D3CE36 22UF/6.3V

X5R 20% mx_c0805_small

GND GND GND GND GND GND GND GND G ND GNDGND

12

I

D3CE47 22UF/6.3V

X5R 20% mx_c0805_small

5

12

I

D3CE37 22UF/6.3V

X5R 20% mx_c0805_small

12

I

D3CE48 22UF/6.3V

X5R 20% mx_c0805_small

GND G ND GNDG NDGND G ND GND G ND GNDG ND

12

I

D3CE38 22UF/6.3V

X5R 20% mx_c0805_small

12

I

D3CE49 22UF/6.3V

X5R 20% mx_c0805_small

12

NI

D3CE39 22UF/6.3V

X5R 20% mx_c0805_small

12

NI

D3CE50 22UF/6.3V

X5R 20% mx_c0805_small

12

NI

D3CE40 22UF/6.3V

X5R 20% mx_c0805_small

12

NI

D3CE51 10UF/6.3V

X5R 10% mx_c0805_ small

4

12

NI

D3CE41 10UF/6.3V

X5R 10% mx_c0805_ small

12

NI

D3CE52 10UF/6.3V

X5R 10% mx_c0805_ small

12

NI

D3CE42 10UF/6.3V

X5R 10% mx_c0805_ small

12

NI

D3CE53 10UF/6.3V

X5R 10% mx_c0805_ small

12

NI

D3CE43 10UF/6.3V

X5R 10% mx_c0805_ small

12

NI

D3CE54 10UF/6.3V

X5R 10% mx_c0805_ small

12

NI

D3CE44 10UF/6.3V

X5R 10% mx_c0805_ small

12

NI

D3CE55 10UF/6.3V

X5R 10% mx_c0805_ small

3

12

NI

D3CE45 10UF/6.3V

X5R 10% mx_c0805_ small

NOTE:

Place those cap at MB Bottom Socket Cavity

NOTE:

Place those cap at MB Top Socket Cavity

2

PEGATRON DT-MB RESTRICTED SECRET

DDR3 TERMINATION A&B

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

Engineer:

IPMLP-AR

1

Stonko_Chen

17 83Thursday, June 27, 2013

Rev

A00

5

D D

E50 X00:12X061855000-->1206-01R2000 1206-01R1000 :small footprint hd_2x2p_50_pinrex 1206-01R2000 : Big foorprint hd_2x2p_50_jv

XTAL VIA D>8 mil

NOTE:

HDA_SDO Disable ME in Manufacturing Mode

ME

1-2 EN

Disable

3-4

C C

+3P3VSB

HDA_SDO36

AZ_SDAT A_OUT43 AZ_SYNC43 AZ_BITCLK43 AZ_RST#43,45

12

GND

1 3 4

I

SC143

4.7PF/50V

PROTO

JE50:12 MINI_JUMPER

PROTO

E50 HEADER_ 2x2P

2

12

I

SC5 10PF/50V

NPO 5%

CLPW D#19,48

RTCRST#48

SRTCRST #48

I

SC1 27PF/50V

GND GND

1 2

SR5 1K

I

1 2

SR6 47

I

1 2

SR7 47

I

1 2

SR8 33

I

1 2

SR9 33

I

12

NI

SC6 10PF/50V

NPO 5%

GNDGND

12

I

SR10 10K

4

+BATT+BATT

12

I

SR2 330K

1 2

SR3 1M

I

Y5

32.768Kh z

1 2

R1.04

HDA_SDO _R HDA_SYNC_ R HDA_BITCL K_24MHZ_R HDA_AZR ST#_R

+3P3V

+3P3V+3P3VSB

12

NI

SR11 10K

12

NI

SR12 1K

I

SR1 1M

3

I

SU1A

LYNX POINT

A8

INTRUDER#

I

SC2 27PF/50V

IPD 15K IPD 15K IPD 15K IPD 15K

G10

K22 G22

L22

F22

D9 B9

B5 B4

INTVRMEN

RTCRST# SRTCRST#

RTCX1 RTCX2

HDA_SDI0 HDA_SDI1 HDA_SDI2 HDA_SDI3

RTC

SATA

PCH_INTVR MEN

PCH_RTC X1

PCH_RTC X2

AZ_SDAT A_IN43

AZALIA

A24

IPD 15K IPD 15K

A22 B25 C24

HDA_SDO HDA_SYNC HDA_BCLK HDA_RST#

SATA_RXN_0 SATA_RXP_0 SATA_TXN_0 SATA_TXP_0

SATA_RXN_1 SATA_RXP_1 SATA_TXN_1 SATA_TXP_1

SATA_RXN_2 SATA_RXP_2 SATA_TXN_2 SATA_TXP_2

SATA_RXN_3 SATA_RXP_3 SATA_TXN_3 SATA_TXP_3

SATA_RXN4/PERN1

SATA_RXP4/PERP1 SATA_TXN4/PETN1

SATA_TXP4/PETP1

SATA_RXN5/PERN2

SATA_RXP5/PERP2 SATA_TXN5/PETN2

SATA_TXP5/PETP2

SATA_RCOMP

SATA_IREF

TP9 TP8

BC8 BE8 AW8 AY8

BC10 BE10 AV10 AW10

BB9 BD9 AY13 AW13

BC12 BE12 AR13 AT13

BD13 BB13 AV15 AW15

BC14 BE14 AP15 AR15

AY5 BD4

BA2 BB2

2

SATA_RC OMP

PCH_TP9 PCH_TP8

SATA_RX N0 42 SATA_RX P0 42

SATA_TX N0 4 2 SATA_TX P0 42

SATA_RX N5/PERN2 34 SATA_RX P5/PERP2 3 4

SATA_TX N5/PETN2 34 SATA_TX P5/PETP2 34

I

SR14

7.5K

1%

1 2

1

ST13

NOBOM

1

ST14

NOBOM

To Full Card

+1P5V

NOTE:

SATA_RCOMP trace length < 500mil

12

NI

SC7

0.1UF/16V

X7R 10%

GND

1

IPU 20K

IPU 20K IPD 20K

AL10

SPKR

B17

DOCKEN#/GPIO33

C22

HDA_DOCK_RST#/GPIO13

AD1

JTAG_TMS

AD3

JTAG_TDO

AE2

JTAG_TDI

AB3

JTAG_TCK

AB6

TP20

F8

TP25

C26

TP22

POINT

SATALED# SATA0GP/GPIO21 SATA1GP/GPIO19

AP3 AT1

(GPI) (CORE)

AU2

(GPI) (CORE) IPU 20K

JTAG

Boot select straps

GPIO51

0

1

3

GPIO19 Description

0

1

LPC

SPI

2

B B

A A

5

PCBEEP44

WL_ DISABLE#33

PCH_JTA G_TMS51

PCH_JTA G_TDO51

PCH_JTA G_TDI51 PCH_JTA G_TCK51 PCH_JTA G_RST51

1 2

NOBOM

GND

4

DOCKEN#

I

SR401 0

ST15

IPD 20K (GPO) (CORE) IPD 15K (GPI) (SUS)

PCH_TP2 5

1

PCH_TP2 2

+3P3V +3 P3V

12

GND GND

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

I

SR16 10K

NI

SR21 10K

I

SR17 10K

12

NI

SR20 10K

IMPLP-MS

HD_LED# 30

VOLUME_ UP# 28,51

BL_UP# 28,51

Title :

Engineer:

1

PCH_SATA,IHDA,RTC,JTAG

Stonko_Chen

18 83Thursday, June 27, 2013

Rev

A00

5

D D

+1P5V

12

I

SR22

7.5K

1%

C C

WAKE #33,34,3 7

SYS_RESET #9 ,50,51

VRM_PW RGD50,76

SB_PW RBTN#2 9,36

SCALAR_ PWRBTN#29

PCH_DPW ROK36,51

B B

RSMRST#36,51

PWRO K13 ,36

A A

+3P3VSB + 3P3V

12

I

SR110 100K

GND

12

I

SR33 1K

12

GND

1 2

SR413 0

I

1 2

SR424 0

NI

I

SR109 1K

NI

MC15

0.1UF/16V

X7R 10%

GND

NOBOM NOBOM

SUSACK#

12

NI

SR26 10K

4

DMI_RXN08 DMI_RXN18 DMI_RXN28 DMI_RXN38

DMI_RXP08 DMI_RXP18 DMI_RXP28 DMI_RXP38

DMI_TXN08 DMI_TXN18 DMI_TXN28 DMI_TXN38

DMI_TXP08 DMI_TXP18 DMI_TXP28 DMI_TXP38

1

ST55

1

ST54

R_SB_PW RBTN#

12

NI

SR24 10K

+1P5V

DMI_RCOMP

TP12_PC H TP7_PCH

IPD 20K

OD

IPU 20K

(Native) (SUS)

IPU 20K

I

SU1B

LYNX POINT

AW22

DMI_RXN_0

AR20

DMI_RXN_1

AP17

DMI_RXN_2

AV20

DMI_RXN_3

AY22

DMI_RXP_0

AP20

DMI_RXP_1

AR17

DMI_RXP_2

AW20

DMI_RXP_3

BD21

DMI_TXN_0

BE20

DMI_TXN_1

BD17

DMI_TXN_2

BE18

DMI_TXN_3

BB21

DMI_TXP_0

BC20

DMI_TXP_1

BB17

DMI_TXP_2

BC18

DMI_TXP_3

BE16

DMI_IREF

AY17

DMI_RCOMP

AW17

TP12

AV17

TP7

K3

WAKE#

AM1

SYS_RESET#

AD7

SYS_PWROK

K1

PWRBTN#

L13

DPWROK

J4

SUSWARN#/SUSPWRNACK/GPIO30

R6

SUSACK#

J2

RSMRST#

AB7

APWROK

F10

PWROK

DMI

DMIDMI

3

t

n

e

m

e

g

n

a

M

r

e

w

o

P

m

e

t

s

s y

y

y S

S

FDI_RXN_0 FDI_RXN_1

FDI_RXP_0 FDI_RXP_1

FDI_CSYNC

FDI

FDI_RCOMP

DSWVRMEN

BATLOW#/GPIO72

ACPRESENT/GPIO31

DRAMPWROK

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

SLP_WLAN#/GPIO29

FDI_INT

FDI_IREF

TP5 TP10 TP13 TP15 TP16 TP17

CLKRUN#

SLP_SUS#

SLP_S4#

SLP_S3#

PMSYNCH

SLP_LAN#

SLP_A#

TP21

AJ35 AL35

AJ36 AL36

AL39

AL40

AT45

AR44

AY45 AW44 AU44 AV45 AV43 AU42

C8

AN7

N4

RI#

K7

E6

H3

F1

C6

H1

AY3

U7

Y6

Y7

D2

G5

F3

AB10

FDI_TXN0 8 FDI_TXN1 8

FDI_TXP0 8 FDI_TXP1 8

FDI_CSYNC 8

FDI_INT 8

FDI_RCOMP

PCH_TP5 PCH_TP1 0 PCH_TP1 3 PCH_TP1 5 PCH_TP1 6 PCH_TP1 7

DSWO DVRENDSW ODVREN

CLKRUN#

(Native) (DSW)

(GPI) (DSW) IPD 20K

(Native) (SUS)

(Native) (SUS) IPU 20K

(Native) (SUS)

(Native) (DSW)

1 1 1 1 1 1

2

+1P5V + 1P5V

ST60

NOBOM

ST62

NOBOM

ST59

NOBOM

ST61

NOBOM

ST64

NOBOM

ST66

NOBOM

+3P3V +BATT

PCH_RI#

PCH_BAT LOW#

PCH_ACP RESENT

PM_SUS_ STAT#

PCH_SUS _CLK

SLP_S5#

SLP_W LAN#

SLP_LAN #

SLP_A#

PCH_TP2 1

12

I

SR30

7.5K

1%

12

I

SR32

8.2K

+3VA

12

I

SR27 10K

PM_DRAM _PWRGD 9

SLP_SUS # 36,75

SLP_S4# 36,66,67,79

SLP_S3# 36,67,68

H_PM_SYNC 9

1

ST38

1

ST52

1

ST37

1

ST58

1

ST40

1

ST56

12

I

SR28 10K

NOBOM

+3VA+3P3VSB

12

I

SR29 10K

1 2

+3P3VSB

SR435

12

NI

0

NI

SR119 10K

12

GND

I

SR31 330K

NI

SR125 330K

CLPW D# 18,4 8

Pin. C8 DSWVRMEN

1

On Die DSW VRM Enable

Pull - H

Enabled(DEFAULT)

Pull - l

Disabled

SLP_W LAN# 33

GND

5

4

POINT

PEGATRON DT-MB RESTRICTED SECRET

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

3

2

Date: Sheet of

IMPLP-MS

Engineer:

PCH_FDI,DMI,SPM

Stonko_Chen

1

Rev

A00

19 83Thursday, June 27, 2013

A00

5

D D

LAN

HALF MINI-PCIE

FULL MINI-PCIE

CARD READER

C C

CPU XDP

12

I

SR35 10K

12

NI

SC8 100PF/50 V

12

I

SR36 10K

I

SR34 10K

Mode_butto n#2 8,30

OBSDATA _D251

SCALAR_ MODE#28,43,5 1

Connected to device. Default : Clock free run. (PD 10K). Reserver 10K PU for power saving purpose.

B B

Eric Fang to Alan Chien on 11/15/2010

PCH CLKREQ Setting: Not connected to device.

CK_33M_ SIO136

CK_33M_ DEBUG48

A A

12

I

SR37 10K

12

NI

SC9 100PF/50 V

12

I

SR38 10K

I

12

NI

SC10 100PF/50 V

GNDGNDGND

12

I

SR39 10K

SR42 22

SR43 22

SR44 22

12

NOBOM

1 2

NOBOM

4

I

SU1C

LYNX POINT

+1P5V

12

I

SR57

7.5K

1%

DIFFCLK_B IASREF

RL_CK_1 00M_LAN#37 RL_CK_1 00M_LAN37

CK_100M _PE1#33 CK_100M _PE133

CK_100M _PE2#34 CK_100M _PE234

CK_100M _PE3#35 CK_100M _PE335

CK_100M _CPUXDP#50 CK_100M _CPUXDP50

+3P3VSB+3P3VSB+3P3 VSB+3P3 VSB+3P3 VSB+3P3 VSB +3P3V +3 P3V

12

I

SR40

SR41

10K

(Native) (SUS) (Native) (CORE) (Native) (CORE) IPU 20K

CLK_REQ 3#

(Native) (SUS)

CLK_REQ 4#

(Native) (SUS)

CLK_REQ 5#

(Native) IPU 20K

CLK_REQ 6#

(Native) (SUS)

CLK_REQ 7#

(Native) IPU 20K

CLK_PCI_F B

1

CLKOUT_ PCI0

CLK_PCI_F B_R

CLK_KBC PCI_PCH_R

CLK_DEB UG_R

CLK_DBG _R

ST84

ST83

+1P5V

IPD 20K

AM45

ICLK_IREF

AN44

DIFFCLK_BIASREF

Y43

CLKOUT_PCIE_N_0

Y45

CLKOUT_PCIE_P_0

AA44

CLKOUT_PCIE_N_1

AA42

CLKOUT_PCIE_P_1

AB43

CLKOUT_PCIE_N_2

AB45

CLKOUT_PCIE_P_2

AD43

CLKOUT_PCIE_N_3

AD45

CLKOUT_PCIE_P_3

AF43

CLKOUT_PCIE_N_4

AF45

CLKOUT_PCIE_P_4

AE44

CLKOUT_PCIE_N5

AE42

CLKOUT_PCIE_P_5

AB40

CLKOUT_PCIE_N_6

AB39

CLKOUT_PCIE_P_6

AJ44

CLKOUT_PCIE_N_7

AJ42

CLKOUT_PCIE_P_7

AH43

CLKOUT_ITPXDP

AH45

CLKOUT_ITPXDP_P

AB1

PCIECLKRQ0#/GPIO73

AF1

PCIECLKRQ1#/GPIO18

AF3

PCIECLKRQ2#/GPIO20/SMI#

T3

PCIECLKRQ3#/GPIO25

V3

PCIECLKRQ4#/GPIO26

AA2

PCIECLKRQ5#/GPIO44

AE4

PCIECLKRQ6#/GPIO45

Y3

PCIECLKRQ7#/GPIO46

D17

CLKIN_33MHZLOOPBACK

D44

CLKOUT_33MHZ0

E44

CLKOUT_33MHZ1

B42

CLKOUT_33MHZ2

F41

CLKOUT_33MHZ3

A40

CLKOUT_33MHZ4

POINT

3

100MHz

33.3MHz

CLOCK SIGNAL

PEGA_CLKRQ#/GPIO47 PEGB_CLKRQ#/GPIO56

100MHz

135MHz

100MHz

96MHz

100MHz

14.318MHz

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

48MHz

25MHz

CLKOUT_PEG_A

CLKOUT_PEG_A_P

CLKOUT_PEG_B

CLKOUT_PEG_B_P

CLKOUT_DMI

CLKOUT_DMI_P

CLKOUT_DP

CLKOUT_DP_P

CLKOUT_DPNS

CLKOUT_DPNS_P

CLKIN_DMI

CLKIN_DMI_P

CLKIN_GND

CLKIN_GND_P

CLKIN_DOT96N CLKIN_DOT96P

CLKIN_SATA

CLKIN_SATA_P

REFCLK14IN

TP19 TP18

XTAL25_OUT

XTAL25_IN

2

AF6

(Native) (SUS)

U4

(Native) (SUS)

AB35 AB36

Y39

CLK_PCH _PEG_B_N

Y38

CLK_PCH _PEG_B_P

AF39 AF40

AJ40 AJ39

AF35 AF36

AY24

CLK_BUF _EXP_N

AW24

CLK_BUF _EXP_P

AR24

CLK_BUF _CPYCLK_N

AT24

CLK_BUF _CPYCLK_P

H33

CLK_BUF _DOT96_N

G33

CLK_BUF _DOT96_P

BE6

CLK_BUF _CKSSCD_N

BC6

CLK_BUF _CKSSCD_P

F45

CLK_BUF _REF14

AD39

PCH_TP1 9

AD38

PCH_TP1 8

C40

(Native) (CORE) IPD 20K

F38

(Native) (CORE) IPD 20K

F36

(Native) (CORE) IPD 20K

F39

(Native) (CORE) IPD 20K

AL44

XTAL_25 M_PCH_OUT

AM43

XTAL_25 M_PCH_IN

CLK_REQ _PEG_A# CLK_REQ _PEG_B#

1

ST86

1

ST85

SR47 10K

I

SR48 10K

I

SR49 10K

I

SR50 10K

I

SR51 10K

I

SR52 10K

I

SR53 10K

I

SR54 10K

I

SR55 10K

I

1

ST68

1

ST69

CLKOUTF LEX1

CLKOUTF LEX2

CLKOUTF LEX3

CK_48M_ SIO_R

12

I

SC12 10PF/50V

NPO 5%

GND GND

1 2

SR45 10K

I

1 2

SR46 10K

I

NOBOM NOBOM

1 2 1 2

1 2

NOBOM NOBOM

1

SR56 22

I

1 2

SR59 1M

I

Y12 25MHZ

1 3

2

GND

ST70

NOBOM

ST71

NOBOM

ST72

NOBOM

1 2

4

CK_100M _PE8# 53 CK_100M _PE8 53

CLK_DMI_N 9 CLK_DMI_P 9

CLK_DP_ N 9 CLK_DP_ P 9

CLK_DPN S_N 9 CLK_DPN S_P 9

1

+3P3VSB

CK_48M_ SIO1 36

12

NI

SC11 100PF/50 V

GND

25-MHz is required in:

1. FCIM

2. BTM for PCH Display Clock gereration in Integrated Graphics platforms

12

I

SC13 10PF/50V

NPO 5%

PEGATRON DT-MB RESTRICTED SECRET

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

5

4

3

2

Date: Sheet of

IMPLP-MS

Engineer:

1

PCH_CLOCK

Stonko_Chen

20 83Thursday, June 27, 2013

Rev

A00

5

4

3

2

1

I

SU1D

AL11

A20

C20

A18

C18

B21

D21

G20

AJ11

AH1

AH3

AJ4

AJ2

AJ7

AL7

AJ10

LYNX POINT

SERIRQ

LAD_0

LAD_1

LAD_2

LAD_3

LFRAME#

LDRQ0#

LDRQ1#/GPIO23

SPI_CLK

SPI_MOSI

SPI_MISO

SPI_IO2

SPI_IO3

SPI_CS0#

SPI_CS1#

SPI_CS2#

LPC

SPI

SMBus

SMBALERT#/GPIO11

SML0ALERT#/GPIO60

SML1ALERT#/PCHHOT#/GPIO74

SML1CLK/GPIO58

SML1DATA/GPIO75

C-Link

Thermal

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK

CL_DATA

CL_RST#

TP1

TP2

TP4

TP3

TD_IREF

N7

(Native) (SUS)

R10 U11

N8

(Native) (SUS)

U8 R7

H6

(Native) (SUS)

K6

(Native) (SUS)

N11

(Native) (SUS)

AF11

AF10

AF7

BA45

BC45

BE43

BE44

AY43

SMBALER T#

SML0ALE RT#

SML1ALE RT#

IPU 31.25K

IPD 100K

TP_PCH_ TP1

TP_PCH_ TP2

TP_PCH_ TP4

TP_PCH_ TP3

PCH_TD_ IREF

D D

SERIRQ36

LAD036,48

LAD136,48

LAD236,48

LAD336,48

LFRAME#36,48

C C

12

I

SR126 1K

SPI_CLK47

SPI_MOSI47

SPI_MISO47

B B

SPI_IO247

SPI_IO347

SPI_CS0#47

+3P3V+3P3 V

12

I

SR127 1K

I

+3P3V

12

I

SR60 10K

1 2

SR425 15

1 2

SR426 15

1 2

SR427 15

1 2

SR428 15

1 2

SR429 15

(Native) (CORE) IPU 20K

SPI_CLK_R

SPI_MOSI_R

SPI_MISO_R

SPI_IO2_R

SPI_IO3_R

12

NI

SC151 10PF/50V

NPO 5%

GND

IPU 20K

IPU or IPD 20K

IPU 20K

+3P3VSB

CL_RST# 33,34

1

ST53

1

ST41

1

ST42

1

ST43

12

I

SR70

8.2K

1%

12

I

SR63 10K

I

SR62 1K

I

SR61 10K

NOBOM

+3P3VSB +3P3VSB

12

GND GND

+3P3VSB

12

GND GND

12

GND G ND

I

SR69

2.2K

NI

SC14 150PF/50 V

NPO 5%

I

SR65

2.2K

NI

SC18 150PF/50 V

NPO 5%

NI

SC149 10PF/50V

NPO 5%

12

I

SR68

2.2K

12

NI

SC15 150PF/50 V

NPO 5%

+3P3VSB

12

I

SR64

2.2K

12

NI

SC19 150PF/50 V

NPO 5%

12

NI

SC150 10PF/50V

NPO 5%

+3P3VSB +3P3VSB

12

GND GND

I

SR67 499

1%

NI

SC16 150PF/50 V

NPO 5%

12

I

SR66 499

1%

12

NI

SC17 150PF/50 V

NPO 5%

CL_CLK 33,34

CL_DATA 33,34

SMB_CLK _RESUME 33,34,39,47

SMB_DAT A_RESUME 33,34,39,47

CRB: 499ohm 1% Checklist: 2.2Kohm 5%

SMB_CLK _SIO_RESUME 47 SMB_DAT A_SIO_RESUME 47

NOTE:

Reserve for Intel 8 Series Chipset Family SKUs

POINT

A A

5

4

3

GND

PEGATRON DT-MB RESTRICTED SECRET

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

2

Date: Sheet of

IMPLP-MS

Engineer:

PCH_LPC,SPI,SMB

Stonko_Chen

1

Rev

A00

21 83Thursday, June 27, 2013

A00

5

12

SJP1SHORT_P IN

VGA_BLU E49

VGA_GRE EN49

VGA_RED49

D D

VGA_DDC A_CLK49

VGA_DDC A_DATA49

VGA_HSYNC49

VGA_VSYNC49

NOBOM

12

SJP2SHORT_P IN

NOBOM

12

SJP3SHORT_P IN

NOBOM

SR74 22

NI

SR75 22

NI

Replace DACREFSET resistor

close to PCH within 500mils

C C

12

I

SR80

8.2K

B B

GPUPW _EN51,7 1,72

D

S

GND

I

3

SQ16 2N7002

1

G

2

LVDS_DE T_CBL1#30

GPU_PCIE_ RST#53

+3P3V

12

I

SR397

8.2K

I

SR79

8.2K

12

I

SR78

8.2K

I

SR399

8.2K

NI

SR409 100K

NOBOM

+3P3V+3P3V+3P3V+3P3V

+3P3V+3P3V

4

12

NI

SR71 150

1%

12

GND

ST73

ST74

ST75

12

I

SR77

8.2K

12

I

SR398

8.2K

DGPU_PW R_EN#

PCH_VGA _BLUE

PCH_VGA _GREEN

PCH_VGA _RED

12

NI

SR72 150

1%

GNDGNDGND

PCH_VGA _HSYNC

PCH_VGA _VSYNC

DACREFS ET

12

I

SR76 649

1%

1

EDP_BKL CTL

1

EDP_BKL TEN

1

EDP_BKL VDDEN

INT_PIRQA#

INT_PIRQB#

INT_PIRQC#

INT_PIRQD#

12

NI

SR73 150

1%

(GPI) (CORE)

GND

OD

T45

U44

V45

M43

M45

N42

N44

U40

U39

N36

K36

G36

H20

L20

K17

M20

C12

B13

A12

I

SU1E

LYNX POINT

POINT

VGA_BLUE

VGA_GREEN

VGA_RED

VGA_DDC_CLK

VGA_DDC_DATA

VGA_HSYNC

VGA_VSYNC

DAC_IREF

VGA_IRTN

EDP_BKLTCTL

EDP_BKLTEN

EDP_VDDEN

PIRQA#

PIRQB#

PIRQC#

PIRQD#

GPIO54

GPIO52

GPIO50

CRT

LVDS

PCI

3

DISPLAY

DDPB_HPD

DDPB_AUXN

DDPB_AUXP

DDPB_CTRLCLK

DDPB_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_HPD

DDPD_AUXN DDPD_AUXP

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_HPD

PIRQE#/GPIO2

PIRQF#/GPIO3

PIRQG#/GPIO4

PIRQH#/GPIO5

PME#

PLTRST#

GPIO51

GPIO53

GPIO55

K40

H45 H43

R40 R39

IPD 20K

K43 K45

R35 R36

IPD 20K

K38

J42 J44

N40 N38

IPD 20K

H39

G17

(GPI) (CORE)

F17

(GPI) (CORE)

L15

(GPI) (CORE)

M15

(GPI) (CORE)

AD10

IPU 20K

Y11

C10

(GPO) (CORE) IPU 20K

A10

(GPO) (CORE) IPU 20K

AL6

(GPO) (CORE) IPU 15K

DDPC_CT RL_CLK 28,2 9 DDPC_CT RL_DATA 28,29

PCI_PME#

Boot select straps

GPIO51 DescriptionGPIO19

2

DDPD_CT RL_CLK 32 DDPD_CT RL_DATA 32

+3P3V+3P3V +3P3V+3P3V

12

I

S1R18

S1R26

10K

1

ST50

PCH_GPIO5 1

PCH_GPIO5 3

PCH_GPIO5 5

+3P3V

12

I

S1R43 10K

NOBOM

GND

1

12

NI

SR83 1M

DDPC_HP D_HDMI 28

12

I

SR84 1M

+3P3V

12

I

SR81 1M

DDPD_HP D_HDMI 32

12

NI

SR82 1K

GND

12

I

S1R42 10K

LVDS_DE T_CBL2# 30

BL_DOW N# 2 8

AV_NOTE 28

VOLUME_ DOWN# 28

PLTRST# 3 6

1

ST76

NOBOM

1

ST77

NOBOM

1

ST78

NOBOM

A A

5

GND

4

3

0

1

0

1

LPC

SPI

2

PEGATRON DT-MB RESTRICTED SECRET

PCH_CRT,LVDS,PCI,DISP

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

IMPLP-MS

Engineer:

PCH_CRT,LVDS,PCI,DISP

1

Stonko_Chen

22 83Thursday, June 27, 2013

Rev

A00

5

4

3

2

1

+3P3V + 3P3V +3P3V+3P3V

12

D D

PC_NOTE28 FULL_DE T#34

DUAL_CO N_DET#3 0

PC_Normal28

BT_DISABL E#33,51

FULLCAR D_SEL3 4,51 USB_CAR D_DET#39,48

C C

HALF_DE T#33 SCL_FW _DATA28,29 SCL_FW _CLK28,29

SPK_DET ECT#44

DGPU_PW ROK72

LPC_PME #36 FULL_DISA BLE#34 BIST_ON28

Panel_SEL_128,30,51

B B

A A

Panel_SEL_228,30,51

HALF_US B_DET#33,51

GPIO16

NI NI

SR396 0 SR400 0

0 : PCIe 1

1 2 1 2

+3P3VSB

12

NI

SR95 10K

12

I

SR124 10K

GND

12

GND GND

I

SR431 10K

NI

SR131 10K

12

+3P3V+3P3V

12

+3P3V

12

GND

I

SR88 10K

+3P3V+3P3V +3P3VSB+3P3 VSB

I

SR90 10K

I

SR91 10K

I

SR430 10K

NI

SR132 10K

+3P3V

NI

SR99 10K

I

SR106 10K

GND

12

I

SR92 10K

I

SR89 10K

NI

SR100 10K

I

SR103 10K

UMA

SR98 10K

I_GPU

SR415 10K

12

I

SR87

SR86

10K

12

I

SR94 10K

NI

SR101 10K

I

SR123 10K

NI

SR414 10K

I

SR417 10K

I

SR93 10K

+3P3V+3P3V +3 P3V+3P3V

12

I

SR102 10K

12

I

SR410 10K

+3P3V+3P3V

12

NI

SR85 10K

PCBID1 PCBID2 MBID

12

I

SR416 10K

GNDGND

1 : SATA4

5

4

GPIO49

0 : PCIe 2

1 : SATA5

(GPI) (CORE) IPU 20K (GPI) (CORE) (Native) (CORE) (GPI) (CORE)

(GPO) (SUS) (GPO) (SUS) (GPO) (SUS) IPU 20K (Native) (DSW) (GPI) (CORE) IPU 20K (GPI) (CORE) IPU 20K

(GPI) (CORE) (GPI) (CORE) (GPI) (CORE) (GPI) (CORE) (GPI) (CORE) IPU 20K

+3VA+3P3VSB+3P 3V+3P3V

12

I

SR96 10K

(GPI) (DSW) IPD 20K (GPI) (SUS) IPU 20K (Native) (CORE) IPU 20K (GPO) (CORE) (GPI) (CORE) IPD 20K (GPI) (CORE) IPD 20K

(GPI) (CORE) IPU 20K (GPI) (CORE) IPU 20K (GPI) (CORE) (GPI) (CORE) IPU 20K (GPO) (SUS)

REV1.00

REV1.01

REV1.02

REV1.03

PCBID1

GPIO1

0 0

1

0

I

SU1F

LYNX POINT

G15

TACH3/GPIO7

AM3

SDATAOUT0/GPIO39

G13

TACH6/GPIO70

AN4

SDATAOUT1/GPIO48

AB11

GPIO15

AD11

GPIO28

Y1

GPIO8

K13

LAN_PHY_PWR_CTRL/GPIO12

AK3

SATA5GP/GPIO49

C16

TACH4/GPIO68

AT7

SLOAD/GPIO38

AT8

BMBUSY#/GPIO0

AN6

GPIO34

D13

TACH5/GPIO69

C14

TACH0/GPIO17

R11

GPIO27

U12

GPIO57

H15

TACH7/GPIO71

AP1

GPIO35/NMI#

AT3

SATA2GP/GPIO36

AK1

SATA3GP/GPIO37

F13

TACH1/GPIO1

A14

TACH2/GPIO6

BB4

SCLOCK/GPIO22

AN2

SATA4GP/GPIO16

Y10

GPIO24

POINT

PCBID2

GPIO6

GPU 0

UMA

0 1

11

GPIO

MBID GPIO22

1

3

CPU/Misc

NCTF

PLTRST_PROC#

TP14

RCIN#

PECI

THRMTRIP#

PROCPWRGD

VSS3 VSS22 VSS23 VSS24 VSS25

VSS4 VSS13 VSS14 VSS12 VSS11 VSS10 VSS21

VSS9

VSS1

VSS2

VSS8

VSS6

VSS7

VSS5 VSS20 VSS19 VSS18 VSS17 VSS16 VSS15

AU4

AN10

AT6

AY1

AV1

AV3

N10 A5 C45 BE5 BE41 A2 A41 A43 A44 B1 B2 B44 B45 BA1 BC1 BD1 BD2 BD44 BD45 BE2 BE3 D1 E1 E45 A4

GND

+1P05V_ PCH

12

NI

HR44 1K

12

NI

SC22 680PF/50 V

X7R 10%

GND

H_CPUPW RGD 9,5 0

PLTRST_ CPU# 9,50

A20GATE 3 6

RST_KB# 36

12

NI

SC20

0.1UF/16V

X7R 10%

GND

PECI_PCH

2

NI

SR407 0

1 2

I

SR4 390

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

PECI_SIO 9,3 6

H_THRMT RIP# 9

IMPLP-MS

Title :

Engineer:

1

PCH_GPIO,MISC

Stonko_Chen

23 83Thursday, June 27, 2013

Rev

A00

5

4

3

2

1

I

SU1I

D D

C C

CARD READER

LAN

HALF MINI-PCIE

B B

A A

PE3_RXN35

PE3_RXP35 PE3_TXN35 PE3_TXP35

RL_LAN_ RXN37

RL_LAN_ RXP37 RL_LAN_ TXN37 RL_LAN_ TXP37

PE5_RXN33 PE5_RXP33 PE5_TXN33 PE5_TXP33

5

1 2

SC27 0.1UF/16V X 7R 10%

I

1 2

SC28 0.1UF/16V X 7R 10%

I

1 2

SC29 0.1UF/16V X 7R 10%

I

1 2

SC30 0.1UF/16V X 7R 10%

I

NOBOM

ST79

ST80

12

I

SR111

7.5K

1%

4

PE3_TXN 1_C PE3_TXP 1_C

RL_LAN_ TXN_C RL_LAN_ TXP_C

+1P5V+ 1P5V

PCIE_RCOM P

1

PCH_TP1 1

1

PCH_TP6

AW31

AY31 BE32 BC32

AT31 AR31 BD33 BB33

AW33

AY33 BE34 BC34

AT33 AR33 BE36 BC36

AW36

AV36 BD37 BB37

AY38

AW38

BC38 BE38

AT40

AT39 BE40 BC40

AN38 AN39 BD42 BD41

BE30

BD29

BC30

BB29

LYNX POINT

PERN1/USB3RN3 PERP1/USB3RP3 PETN1/USB3TN3 PETP1/USB3TP3

PCIe/USB

PERN2/USB3RN4 PERP2/USB3RP4 PETN2/USB3TN4 PETP2/USB3TP4

PERN_3 PERP_3 PETN_3 PETP_3

PERN_4 PERP_4 PETN_4 PETP_4

PERN_5 PERP_5 PETN_5 PETP_5

PERN_6 PERP_6 PETN_6 PETP_6

PERN_7 PERP_7 PETN_7 PETP_7

PERN_8 PERP_8 PETN_8 PETP_8

PCIE_IREF

PCIE_RCOMP

TP11

TP6

POINT

PCIe

3

USB

USB2N0 USB2P0

USB2N1 USB2P1

USB2N2 USB2P2

USB2N3 USB2P3

USB2N4 USB2P4

USB2N5 USB2P5

USB2N6 USB2P6

USB2N7 USB2P7

USB2N8 USB2P8

USB2N9 USB2P9

USB2N10 USB2P10

USB2N11 USB2P11

USB2N12 USB2P12

USB2N13 USB2P13

USB3RN1 USB3RP1 USB3TN1 USB3TP1

USB3RN2 USB3RP2 USB3TN2 USB3TP2

USB3RN5 USB3RP5 USB3TN5 USB3TP5

USB3RN6 USB3RP6 USB3TN6 USB3TP6

TP24 TP23

OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43

OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14

USBRBIAS#

USBRBIAS

B37 D37

A38 C38

A36 C36

A34 C34

B33 D33

F31 G31

K31 L31

G29 H29

A32 C32

A30 C30

B29 D29

A28 C28

G26 F26

F24 G24

USB3 [T/R] [p/n] [6:1] IPD 15K

AR26 AP26 BE24

USB3_TX _N1_C

BD23

USB3_TX _P1_C

AW26 AV26 BD25

USB3_TX _N2_C

BC24

USB3_TX _P2_C

AW29 AV29 BE26

USB3_TX _N5_C

BC26

USB3_TX _P5_C

AR29 AP29 BD27

USB3_TX _N6_C

BE28

USB3_TX _P6_C

M33 L33

P3

(Native) (SUS)

V1

(Native) (SUS)

U2

(Native) (SUS)

P1

(Native) (SUS)

M3

(Native) (SUS)

T1

(Native) (SUS)

N2

(Native) (SUS)

M1

(Native) (SUS)

K24 K26

PCH_TP2 4 PCH_TP2 3

USB_BIAS

1 1

GND

12

USBN1 40 USBP1 40

USBN2 40 USBP2 40

USBN3 39 USBP3 39

USBN4 39 USBP4 39

USBN5 30 USBP5 30

USBN6 30 USBP6 30

USBN8 41 USBP8 41

USBN9 41 USBP9 41

USBN10 33 USBP10 33

USBN11 34 USBP11 34

SC33 0.1UF/16V X 7R 10%

I

SC37 0.1UF/16V X 7R 10%

I

SC34 0.1UF/16V X 7R 10%

I

SC38 0.1UF/16V X 7R 10%

I

SC158 0.1U F/16V X7R 10%

I

SC159 0.1U F/16V X7R 10%

I

SC160 0.1U F/16V X7R 10%

I

SC161 0.1U F/16V X7R 10%

I

ST81 ST82

I

SR112

22.6

1%

LEFT USB3.0

SMALL CARD USB3.0

TOUCH

WEBCAM

REAR USB2.0

Half MINI-PCIE

FULL MINI-PCIE

1 2 1 2

NOBOM NOBOM

+3P3VSB +3P3VSB

OC0# 40,51 OC1# 40,51 OC2# 39,51 OC3# 39,51 OC4# 41,51 OC5# 41,51

2

USB3_RX _N1 40 USB3_RX _P1 40

USB3_TX _N1 40 USB3_TX _P1 40

USB3_RX _N2 40 USB3_RX _P2 40

USB3_TX _N2 40 USB3_TX _P2 40

USB3_RX _N5 39

USB3_RX _P5 39 USB3_TX _N5 39 USB3_TX _P5 39

USB3_RX _N6 39 USB3_RX _P6 39

USB3_TX _N6 39 USB3_TX _P6 39

I

SR113 10K

12

I

SR114 10K

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Date: Sheet of

12

USB CONTROLLER

PORT

CTL

1

2

LEFT SIDE

SMALL CARD

OC6# 51 OC7# 51

Size Project Name

A3

IMPLP-MS

0

1

2

3

4

5

6

7

8

9

10

11

12

13

FUNCTION

LEFT USB

SMALL CARD USB

TOUCH

WEBCAM

REAR USB

Half MINI-PCIE

FULL MINI-PCIE

Title :

Engineer:

1

DBP

OC

YES

OC0#

OC1#

OC2#

OC3#

OC4#

YES

OC5#

PCH_USB,PCIE

Stonko_Chen

24 83Thursday, June 27, 2013

Rev

A00

5

+1P05V_ PCH

D D

12

GND

C C

B B

12

I

SC41 10UF/6.3V

X5R 10% mx_c0805

I

SC42 1UF/6.3V

X5R 10%

GND GND GND

+1P05V_ ME

12

I

SC45 22UF/6.3V

X5R 20% mx_c0805

GND

12

I

SC49 1UF/6.3V

X5R 10%

GND

12

I

SC43 1UF/6.3V

X5R 10%

12

I

SC46 1UF/6.3V

X5R 10%

GND GND

I

SR115

5.1

1%

12

DCPSUSB YPDCPSUSB YP_RC

I

SC44 1UF/6.3V

X5R 10%

I

SC47 1UF/6.3V

X5R 10%

+3P3V

12

GND

+3P3VSB

4

NI

SC48

0.1UF/16V

X7R 10%

GND

AA24 AA26 AD20 AD22 AD24 AD26 AD28 AE18 AE20 AE22 AE24 AE26 AG18 AG20 AG22 AG24

Y26

AA18

U18 U20 U22 U24 V18 V20 V22 V24 Y18 Y20 Y22

R32 R30

AJ32 AJ30

U14

P43

I

SU1G

LYNX POINT

VCC7 VCC8 VCC9 VCC11 VCC10 VCC12 VCC13 VCC1 VCC17 VCC2 VCC16 VCC15 VCC14 VCC6 VCC5 VCC4 VCC3

VCCASW12 VCCASW11 VCCASW1 VCCASW2 VCCASW3 VCCASW9 VCCASW10 VCCASW4 VCCASW5 VCCASW6 VCCASW7 VCCASW8

VCC3_3_R32 VCC3_3_R30

VCCSUS3_3_2 VCCSUS3_3_1

DCPSUSBYP

VSS26

VCCVRM1 VCCVRM2 VCCVRM3 VCCVRM4 VCCVRM5

VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8

VCCIO9 VCCIO10 VCCIO11

DCPSUS1

DCPSUS3_1 DCPSUS3_2

VCCADAC1_5

VCCADACBG3_3

3

+1P5V

AN11 BB44 AK26 AK28 BE22

AN34 AN35 AK20 AK18 AM22 AP22 AR22 AT22 AK22 AM20 AM18

Y12

AJ26 AJ28

P45

M31

12

GND GND GND GND GND

PCH_DCP SUS1

PCH_DCP SUS3

VCCADAC 1_5 VCCADA C_FILTER

12

GND G ND

VCCADAC BG3_3

I

SC50 1UF/6.3V

X5R 10%

I

SC56

0.01UF/25 V

X7R 10%

12

+1P05V_ME

12

I

SR404 0

I

SC51 1UF/6.3V

X5R 10%

NI

SR402 0

I

SC57

0.1UF/16V

X7R 10%

12

+1P05V_ME

12

GND

12

I

SC59

0.1UF/16V

X7R 10%

GND

I

SC52 1UF/6.3V

X5R 10%

NI

SR403 0

I

SC58 10UF/6.3V

X5R 10% mx_c0805

2 1

+3P3V

12

I

SC53 1UF/6.3V

X5R 10%

I

SL9 600Ohm/1 00Mhz/0.5A

mx_l0603

12

NI

SC60 1UF/16V

X7R 10% mx_c0603

GND

2

+1P05V_ PCH

I

SC54 1UF/6.3V

X5R 10%

12

I

SC55 10UF/6.3V

X5R 10% mx_c0805

GND

I

SR116 0

mx_r0603

+1P5V

12

1

POINT

A A

PEGATRON DT-MB RESTRICTED SECRET

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

5

4

3

2

Date: Sheet of

IMPLP-MS

Engineer:

PCH_POWER - 1

1

Stonko_Chen

25 83Thu rsday, June 27, 2013

Rev

A00

5

D D

+3P3VSB

C C

+3P3V

12

I

SC69 1UF/16V

X7R 10% mx_c0603

+1P05V_ PCH

12

B B

A A

GND

+1P05V_ PCH

5

12

I

SC74 1UF/6.3V

X5R 10%

I

SC75 1UF/6.3V

X5R 10%

GND GND GND GND GND GND GND

I

SR120 1

mx_r0805

1 2

GND

12

I

SC76

SC77

1UF/6.3V

X5R 10%

+1P05V_ XCKDCBFB +1 P05V_XCK_DCB

4

+1P05V_ PCH

12

I

SC62

0.1UF/16V

X7R 10%

GND

12

GND

12

I

SC64

0.1UF/16V

X7R 10%

GND GND GND

I

SC65

0.1UF/16V

X7R 10%

12

I

SC66

0.1UF/16V

X7R 10%

VCCCLK3_3 0.055 A

12

GND GND GND GND

12

1 2

I

SC70 1UF/16V

X7R 10% mx_c0603

I

SC78 1UF/6.3V

X5R 10%

I

SR405 0

mx_r0603

12

4

12

I

SC71 1UF/16V

X7R 10% mx_c0603

12

I

SC79 1UF/6.3V

X5R 10%

12

I

SC80 10UF/6.3V

X5R 10% mx_c0805

GND GND

I

SC72 1UF/16V

X7R 10% mx_c0603

I

SC73

0.1UF/16V

X7R 10%

12

I

SC81 1UF/6.3V

X5R 10%

+1P5V

12

GND

12

I

SC61 10UF/6.3V

X5R 10% mx_c0805

GND

I

SC63

0.1UF/16V

X7R 10%

I

SC67 1UF/16V

X7R 10% mx_c0603

12

NI

SC68

0.1UF/16V

X7R 10%

12

I

SC142

0.1UF/16V

X7R 10%

GND

AF34

AW40

U30 V30 V28 Y30 U35 U36

R26 R28 U26 R24 R20 R22

A26

M29

M26 U32 V32

AJ14 AJ12

Y32 AD34 AA30 AA32 AD35 AG30 AG32 AD36 AE30 AE32

AP45

M24

K8

L29 L26

I

SU1H

LYNX POINT

VCCVRM7 VCCVRM6

VCCIO12 VCCIO13 VCCIO14 VCCIO16 VCCUSBPLL VCCIO15

VCCSUS3_3_3 VCCSUS3_3_4 VCCSUS3_3_5 VCCSUS3_3_9 VCCSUS3_3_6 VCCSUS3_3_7 VCCSUS3_3_8 VCCSUSHDA

VCCCLK3_3_1 VCCCLK3_3_2 VCCCLK3_3_3 VCCCLK3_3_4 VCCCLK3_3_5 VCCCLK3_3_6

V_PROC_IO_2 V_PROC_IO_1 VCCCLK1 VCCCLK2 VCCCLK3 VCCCLK4 VCCCLK5 VCCCLK6 VCCCLK7 VCCCLK8 VCCCLK9 VCCCLK10

VCC20

POINT

VSS27

3

L24

VCC3_3_1

AE14

VCC3_3_2

AF12

VCC3_3_3

AG14

VCC3_3_4

AK30

VCC3_3_5

AK32

VCC3_3_6

P18

VCC18

P20

VCC19

+3VA

12

I

SC86

0.1UF/16V

X7R 10%

GND

12

I

SC87

0.1UF/16V

X7R 10%

GND

12

I

SC89 1UF/6.3V

X5R 10%

GND G ND

+3P3V_M E

12

I

SC92 1UF/6.3V

X5R 10%

GND

TP_PCH_ VCCSUS

12

I

SC94

0.1UF/16V

X7R 10%

GND

VCCRTC

VCCSPI

DCPSUS2

DCPRTC1 DCPRTC2

DCPSST

A16

A6

L17 R18

AD12

Y35

P14 P16

AA14

VCCDSW3_3

VCCASW13 VCCASW14

3

12

GND

2

GND

12

I

SC148

0.1UF/16V

X7R 10%

GND

I

SC90 1UF/6.3V

X5R 10%

I

SC93

0.1UF/16V

X7R 10%

2

12

I

SC82 1UF/16V

X7R 10% mx_c0603

+1P05V_ME

1 2

+BATT

12

GND

12

NI

SC91 22UF/6.3V

X5R 20% mx_c0805

GND

+1P05V_ME

12

GND

NI

SR128 0

mx_r0603

I

SR129 0

mx_r0603

I

SC88 1UF/16V

X7R 10% mx_c0603

NI

SR406 0

NI

SC95 1UF/16V

X7R 10% mx_c0603

1

+3P3V

+1P05V_ PCH

NOBOM

SR121 0

1 2

NOBOM

SR122 0

1 2

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

12

GND G ND GND

+1P05V_ PCH

+3P3V

IMPLP-MS

12

I

SC85

0.01UF/25 V

X7R 10%

VCCSPI 0.022 A

Engineer:

I

SC83

0.1UF/16V

X7R 10%

Title :

1

12

I

SC84

0.1UF/16V

X7R 10%

PCH_POWER - 2

Stonko_Chen

26 83Thu rsday, June 27, 2013

Rev

A00

5

D D

I

SU1J

LYNX POINT

AL34

VSS116

AL38

VSS115

AL8

VSS114

AM14

VSS113

AM24

VSS112

AM26

VSS111

AM28

VSS91

AM30

VSS90

AM32

VSS110

AM16

VSS118

AN36

VSS89

AN40

VSS88

AN42

VSS117

AN8

VSS109

AP13

VSS108

AP24

VSS87

AP31

VSS107

AP43

C C

B B

GND GNDGND GND

AR2

AK16

AT10 AT15 AT17 AT20 AT26 AT29 AT36 AT38

AV13 AV22 AV24 AV31 AV33 BB25 AV40

AV6

AW2

AY10 AY15 AY20 AY26 AY29

AY7

D42

F43

B11 B15

VSS86 VSS85 VSS84 VSS83 VSS82 VSS37 VSS36 VSS35 VSS38 VSS34 VSS80 VSS33 VSS32 VSS119 VSS39 VSS28 VSS31 VSS29 VSS30 VSS106 VSS105 VSS81 VSS104 VSS103 VSS102 VSS101 VSS100 VSS99 VSS98 VSS97

POINT

4

K39

VSS96

L2

VSS95

L44

VSS94

M17

VSS93

M22

VSS92

N12

VSS40

N35

VSS42

N39

VSS41

N6

VSS43

P22

VSS45

P24

VSS44

P26

VSS48

P28

VSS47

P30

VSS46

P32

VSS49

R12

VSS50

R14

VSS53

R16

VSS52

R2

VSS51

R34

VSS55

R38

VSS54

R44

VSS56

R8

VSS58

T43

VSS57

U10

VSS60

U16

VSS59

U28

VSS61

U34

VSS62

U38

VSS63

U42

VSS65

U6

VSS64

V14

VSS66

V16

VSS67

V26

VSS68

V43

VSS71

W2

VSS70

W44

VSS69

Y14

VSS73

Y16

VSS72

Y24

VSS74

Y28

VSS76

Y34

VSS75

Y36

VSS78

Y40

VSS77

Y8

VSS79

3

I

SU1K

LYNX POINT

AA16 AA20 AA22 AA28

AA4 AB12 AB34 AB38

AB8

AC2 AC44 AD14 AD16 AD18 AD30 AD32 AD40

AD6

AD8 AE16 AE28

AF38

AF8

AG16

AG2 AG26 AG28 AG44

AJ16 AJ18 AJ20 AJ22 AJ24 AJ34 AJ38

AK14 AK24 AK43 AK45

AL12

AL2 BC22 BB42

VSS136 VSS197 VSS196 VSS195 VSS194 VSS193 VSS192 VSS146 VSS128 VSS145 VSS191 VSS190 VSS189 VSS204 VSS203 VSS202 VSS209 VSS208 VSS188 VSS187 VSS186 VSS185 VSS184 VSS183 VSS201 VSS200 VSS199 VSS198 VSS182 VSS148 VSS147 VSS150 VSS149 VSS181 VSS180

AJ6

VSS179

AJ8

VSS178 VSS177 VSS176 VSS175 VSS174 VSS173 VSS172 VSS206 VSS205

POINT

VSS171 VSS170 VSS169 VSS168 VSS167 VSS166 VSS165 VSS164 VSS163 VSS162 VSS161 VSS160 VSS159 VSS129 VSS130 VSS131 VSS132 VSS144 VSS133 VSS143 VSS134 VSS142 VSS135 VSS121 VSS120 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS139 VSS140 VSS141 VSS138 VSS158 VSS137 VSS157 VSS156 VSS155 VSS154 VSS153 VSS152 VSS151 VSS207

B19 B23 B27 B31 B35 B39 B7 BA40 BD11 BD15 BD19 AY36 AT43 BD31 BD35 BD39 BD7 D25 AV7 F15 F20 F29 F33 BC16 D4 G2 G38 G44 G8 H10 H13 H17 H22 H24 H26 H31 H36 H40 H7 K10 K15 K20 K29 K33 BC28

2

NOBOM

H23 C138D13 8N

1

NOBOM

H22 C138D13 8N

NOBOM

H20 C138D13 8N

NOBOM

H21 C138D13 8N

1

A A

PEGATRON DT-MB RESTRICTED SECRET

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

5

4

3

2

Date: Sheet of

IMPLP-MS

Engineer:

1

PCH_VSS

Stonko_Chen

27 83Thu rsday, June 27, 2013

Rev

A00

5

I

+3P3V

D D

S1L2 30 Ohm/10 0Mhz

mx_l0603

21

+1P2V

12

I

S1C15 10UF/6.3V

X5R 10% mx_c0805_ small

GND GND GND

I

PR855 0

mx_r0603

1 2

*ALL RESISTOR ARE MX_R0402_SMALL FOOTPRINT

I

+3P3V

C C

+1P2V

I

S1L7

+3P3V

30Ohm/10 0Mhz

mx_l0603

21

12

I

S1C35 10UF/6.3V

X5R 10% mx_c0805_ small

B B

S1C35 can NI if power noise test pass

S1L4 30Ohm/10 0Mhz

mx_l0603

I

S1L5 30Ohm/10 0Mhz

mx_l0603

I

S1L6 30Ohm/10 0Mhz

mx_l0603

2 1

12

NI

S1C31

0.1UF/16V

X7R 10%

21

12

I

S1C28 10UF/6.3V

X5R 10% mx_c0805_ small

GND G ND GND

12

NI

S1C32

0.1UF/16V

X7R 10%

From External HDMI In

DDPC_HP D_HDMI22 DDPC_CT RL_CLK22,29 DDPC_CT RL_DATA22,29

From PCH

From Internal CPU HDMI In

A A

To LEVEL SHIFT

5

PC_Normal23 BIST_ON23

HDMIC_TMD SC_DATA0#8 HDMIC_TMD SC_DATA08 HDMIC_TMD SC_DATA1#8 HDMIC_TMD SC_DATA18 HDMIC_TMD SC_DATA2#8 HDMIC_TMD SC_DATA28 HDMIC_TMD SC_CLK#8 HDMIC_TMD SC_CLK8

HDMI_LS_C LK29 HDMI_LS_C LK#29 HDMI_LS_D 229 HDMI_LS_D 2#29 HDMI_LS_D 129 HDMI_LS_D 1#29 HDMI_LS_D 029 HDMI_LS_D 0#29

I I I I

1 2

S1C39 0.1UF/16 VIX7R 10%

1 2

S1C40 0.1UF/16 VIX7R 10%

1 2

S1C41 0.1UF/16 VIX7R 10%

1 2

S1C42 0.1UF/16 VIX7R 10%

1 2

S1C43 0.1UF/16 VIX7R 10%

1 2

S1C44 0.1UF/16 VIX7R 10%

1 2

S1C45 0.1UF/16 VIX7R 10%

1 2

S1C46 0.1UF/16 VIX7R 10%

4

Close to Scalar

12

I

S1C16

0.1UF/16V

X7R 10%

12

NI

S1C19 10UF/6.3V

X5R 10% mx_c0805_ small

GND G ND

PWRB TN#30,36,51

SCALAR_ PWRBTN_EN29

12

I

S1C23 10UF/6.3V

X5R 10% mx_c0805_ small

12

I

S1C26 10UF/6.3V

X5R 10% mx_c0805_ small

GND G ND

12

I

S1C29

0.1UF/16V

X7R 10%

12

I

S1C33

0.1UF/16V

X7R 10%

HDMI_IN_HPD31 SL_HDMIB_ IN_SCL31 SL_HDMIB_ IN_SDA31 SL_HDMIB_ IN_TX0 N31 SL_HDMIB_ IN_TX0 P31 SL_HDMIB_ IN_TX1 N31 SL_HDMIB_ IN_TX1 P31 SL_HDMIB_ IN_TX2 N31 SL_HDMIB_ IN_TX2 P31 SL_HDMIB_ IN_CLK N31 SL_HDMIB_ IN_CLK P31

1 2

S1R49 100

1 2

S1R50 100

1 2

S1R22 100

1 2

S1R39 100

4

12

I

S1C17

0.1UF/16V

X7R 10%

SADC_1P 2V

12

I

S1C20

0.1UF/16V

X7R 10%

1 2

12

I

S1C24

0.1UF/16V

X7R 10%

GNDGN D

SAVDD_E AR

12

I

S1C27

0.1UF/16V

X7R 10%

SVDDC_1 P2V

12

I

S1C30

0.1UF/16V

X7R 10%

SVDDP_3 P3V

12

I

S1C34

0.1UF/16V

X7R 10%

GNDGN DGN DG NDGND

S_DDPC_ CTRL_CLK S_DDPC_ CTRL_DATA S_PC_No rmal S_BIST_ON

GND

NI

S1R6 0

SAVDD_A U

I

S1U1

9

AVDD_33_1

24

AVDD_33_2

23

GND1

34

GND2

44

GND3

55

GND4

66

GND5

78

GND6

112

GND7

129

GND8

96

GND_BST

18

AVDDL_DVI

25

BIN0M

26

BIN0P

27

GIN0M

28

GIN0P

29

SOGIN0

30

RIN0M

31

RIN0P

32

HSYNC0

33

VSYNC0

38

LINE_IN_L/AUMUTE/GPIO_AU0

39

LINE_IN_R/AUSCK/GPIO_AU1

37

AVDD_AUSDM

47

AVDD_EAR

54

VDDC1

109

VDDC2

56

VDDP1

77

VDDP2

98

VDDP3

111

VDDP4

126

GPIO31

127

DDCD_CK/RS232_RX1/GPIO32

128

DDCD_DA/RS232_TX1/GPIO33

3

RXA0N

4

RXA0P

5

RXA1N

6

RXA1P

7

RXA2N

8

RXA2P

1

RXACN

2

RXACP

21

GPIO36

19

DDCDB_CK/GPIO34

20

DDCDB_DA/GPIO35

123

GPIO26

114

GPIO20

12

RXB0N

13

RXB0P

14

RXB1N

15

RXB1P

16

RXB2N

17

RXB2P

10

RXBCN

11

RXBCP

89

NC1

90

NC2

91

NC3

92

NC4

93

NC5

94

NC6

95

NC7

97

NC8

99

NC9

100

NC10

TSUMU88 BDC2-1

3

AUVAG/AUMCK/GPIO_AU4

AUVRM/SPDIFO/GPIO_AU5

LINE_OUT_R/AUWS/GPIO_AU3

LINE_OUT_L/AUSD/GPIO_AU2

EAR_OUT_L

EAR_OUT_R

NC19 NC18 NC17 NC16 NC15 NC14

RESET

NC13 NC12 NC11

SAR2/GPIO_SAR2 SAR1/GPIO_SAR1

GPIO25

CEC/GPIO27

GPIO21

GPIO37

GPIO30

GPIO00 SAR0/GPIO_SAR0 SAR3/GPIO_SAR3

GPIO24/PWM6

HOLDZ/GPIO11

GPIO22/PWM4 GPIO23/PWM5 GPIO02/PWM1

GPIO01/PWM0/SPDIFO

DDCA_CK/RS232_RX0/GPIO40 DDCA_DA/RS232_TX0/GPIO41

GPIO03

MIIC_SCL/GPIO04

MIIC_SDA/GPIO05

WPZ/GPIO10

SCK

SDO

CSZ

LVB0P

LVB0M

LVB1P

LVB1M

LVB2P

LVB2M

LVBCKP

LVBCKM

LVB3P

LVB3M

LVA0P

LVA0M

LVA1P

LVA1M

LVA2P

LVA2M

LVACKP

LVACKM

LVA3P

LVA3M

XOUT

3

SDI

XIN

42

AUVAGSAVDD_3 3

43

AUVRM

41

I_F_LIN1_RF

40

I_F_LIN1_LF

46 45

110 108 107 106 105 104

50

103 102 101

117

S_UP_DO WN#

116

S_Mode_b utton#

122

S_AV_NO TE

124

S_Panel_SEL_ 1

113

S_Panel_SEL_ 2

22

125

S_Scalar_mode

51

S_BL_UP #

115

S_BL_DO WN#

118

S_VOLUM E_UP#

121

S_VOLUM E_DOWN#

65

S_PC_NO TE

119

S_PANEL _BIST_ON

120

S_SCL_L CDEN

53

SCL_BL_ PWM_R

52

SCL_BL_ EN_R

35

DDCA_SC L

36

DDCA_SD A

57 58 59

64 63 62 61 60

88 87 86 85 84 83 82 81 80 79 76 75 74 73 72 71 70 69 68 67

48

X-OUT

49

X-IN

12

I

S1C3

4.7UF/10V

mx_c0603 X5R 10%

1 2

S1R4 0

I

1 2

S1R2 0

I

1

S1T1

1

S1T2

+5V

I

12

S1C21 10UF/6.3V

X5R 10% mx_c0805_ small

12

GND GNDGN D

12

I

S1C22

0.1UF/16V

X7R 10%

GNDGND

S1R27 100

I

S1R20 100

I

S1R30 100

I

S1R29 100

I

S1R40 100

I

S1R45 4.7K

NI

S1R51 4.7K

I

S1R21 100

I

S1R24 100

I

S1R23 100

I

S1R25 100

I

S1R28 100

I

S1R47 100

I

S1R19 100

I

S1R38 100

I

S1R17 100

I

S1R16 100

I

S1R48 4.7K

I

S1R11 0

I

S1R12 0

I

S1R14 0

I

S1R15 0

I

1 2

S1R31 0

I

1 2

S1R32 1M

NI

1 3

I

S1C36 22PF/50V

NPO 5%

12

I

S1C11 1UF/16V

mx_c0603 X7R 10%

NOBOM NOBOM

I

S1R13 10K

1%

1 2 1 2 1 2 1 2 1 2

1 2

1 2 1 2 1 2 1 2 1 2

1 2 1 2 1 2 1 2 1 2 1 2

1 2 1 2

EEPROM_ WP 29 DDPCTL_ CLK 29 DDPCTL_ DAT 2 9

SL_W P_N 29 SL_CLK 29 SL_SDIN 29 SL_SDOU T 29 SL_CS_N 29

LCD_O_IN0 P 30 LCD_O_IN0 N 30 LCD_O_IN1 P 30 LCD_O_IN1 N 30 LCD_O_IN2 P 30 LCD_O_IN2 N 30 LCD_O_C LKIN_P 30 LCD_O_C LKIN_N 3 0 LCD_O_IN3 P 30 LCD_O_IN3 N 30 LCD_E_IN0 P 30 LCD_E_IN0 N 30 LCD_E_IN1 P 30 LCD_E_IN1 N 30 LCD_E_IN2 P 30 LCD_E_IN2 N 30 LCD_E_C LKIN_P 30 LCD_E_C LKIN_N 3 0 LCD_E_IN3 P 30 LCD_E_IN3 N 30

I

2

4

Y1

14.318MH Z

2

NI

S1R1 0

12

I

S1C12 330PF/50 V

X7R 10%

1 2

+3P3V

12

I

S1R44

4.7K

1%

+3P3V

I

S1L1 60 ohm/3A

mx_l0805_h41

21

12

I

S1R3 220K

1%

GND

12

I

S1C13 330PF/50 V

X7R 10%

GND G NDGND G ND

UP_DOW N# 30 Mode_butto n# 20,30 AV_NOTE 22 Panel_SEL_1 23,30,51 Panel_SEL_2 23,30,51

DDPC_W P# 29,31

SCALAR_ MODE# 20,43,51 BL_UP# 18,51 BL_DOW N# 2 2 VOLUME_ UP# 18,51 VOLUME_ DOWN# 22

PC_NOTE 23 PANEL_B IST_ON 30 SCL_LCD EN 29 SCL_BL_ PWM 30 SCL_BL_ EN 30

SIO_TX0 36 SIO_RX0 36

SCL_FW _CLK 23,29 SCL_FW _DATA 23,29

12

I

S1R5 220K

1%

1

I_F_LIN1_RC 43 I_F_LIN1_LC 43

Close to Scalar

From LVDS & Dual CONN.

To PCH

To LVDS & Dual CONN.

To SIO

To Scalar Debug

To Scalar EEPROM

To Scalar SPI ROM

To LVDS CONN.

PEGATRON DT-MB RESTRICTED SECRET

12

I

S1C37 22PF/50V

NPO 5%

2

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

Engineer:

IMPLP-MS

Title :

1

SCALAR_TSUMU88BDC2 - 1

Stonko_Chen

28 83Thu rsday, June 27, 2013

Rev

A00

5

4

3

2

1

SCALAR SPI ROM SCALAR HDMI LEVEL SHIFT (Cost Reduce)

+3P3V

12

I

S1R34

D D

SL_CLK28 SL_SDIN28

8.2K

+3P3V

GND

12

I

S1C18

0.1UF/16V

X7R 10%

4Mbit

I

S1U4 SST SPI 4Mb

8

VCC

7

HOLD#

6

CLK

5

DIO

CS#

WP# GND

1 2

DO

3 4

GND

12

I

S1R33 100K

SL_CS_N 28 SL_SDOU T 28

SL_W P_N 28

SCALAR EEPROM

+3P3V

+3P3V+3P3V

C C

EEPROM_ WP28 DDPCTL_ CLK28 DDPCTL_ DAT28

B B

OSD Power Button wake up from Screen off

SCALAR_ PWRBTN_EN28

1 2

S1R9 100

I

1 2

S1R10 100

I

SCALAR_ PWRBTN#19

12

NI

S1R52

4.7K

I

S1R35

3.3K

NI

S1Q1 2N7002

D

3

12

I

S1R37

3.3K

1

12

I

S1R36 100K

I2C_MCL I2C_MDA

+3P3V+3VA

12

NI

S1R41

4.7K

S

2

G

+3P3V

8 7 6 5

12

I

S1C38

0.1UF/16V

X7R 10%

GND

SB_PW RBTN# 1 9,36

16Kbit

I

S1U5 EEPROM 1 6Kb

A0

VCC

A1

WP

A2

SCL

GND

SDA

1 2 3 4

GND

SCALAR DEBUG PORT

A A

SCL_FW _DATA23,28 SCL_FW _CLK23,28

5

GND

NI

S1J1 WtoB_ CON_1X3P

SIDE2

3

2

1

SIDE1

5

4

Cost Reduced Level Shifter Motherboard Topology for max data rate of 1.65 Gb/s Active Level Shifter Motherboard Topology for max data rate of 2.97 Gb/s

I

S1Q2 CBT3245 ABQ

VCC

HDMI_LS_D 2#28 HDMI_LS_D 228 HDMI_LS_D 1#28 HDMI_LS_D 128 HDMI_LS_D 0#28 HDMI_LS_D 028 HDMI_LS_C LK#28 HDMI_LS_C LK28

SCALAR LCD ENABLE

SCL_LCD EN28

12

GND

INTEL DISPLAY EDID

DDPC_CT RL_CLK22,28

DDPC_CT RL_DATA22,28

DDPC_W P#28,31

3

S1RN1A

I

S1RN1B

I

S1RN1C

I

S1RN1D

I

S1RN2A

I

S1RN2B

I

S1RN2C

I

S1RN2D

I

NI

S1R53 100K

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8

12

I

MR40

4.7K

1 2

680 680 680 680 680 680 680 680

I

MR17

2.2K

1

+5VSB

B

GND

+3P3V

2

HDMI_LS_R _D2# HDMI_LS_R _D2 HDMI_LS_R _D1# HDMI_LS_R _D1 HDMI_LS_R _D0# HDMI_LS_R _D0 HDMI_LS_R _CLK# HDMI_LS_R _CLK

12

I

S1R7 10K

3

C

I

S1Q5

E

PMBS390 4

2

12

I

MR15

2.2K

B

1

GND

+19V +5V

12

I

S1R8 10K

3 C

I

B

1

S1Q3 PMBS390 4

E 2

GND

+3P3V+3P3V

3

C

I

MQ7 PMBS390 4

E 2

2 3 4 5 6 7 8 9

1

GND

OE#

A1 A2 A3 A4 A5 A6 A7 A8

GND1 GND2 GND3

NC1

GND4

12

I

S1R46 15K

GND

12

I

+3P3V

MR13 100K

12

NI

MR14 100K

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

B1 B2 B3 B4 B5 B6 B7 B8

GND

20 19

18 17 16 15 14 13 12 11

10 21 22 23

12

I

MC14

0.1UF/16V

X7R 10%

+5V

HDMI_LS_O E#

GND

I

S1Q4 AP2306G N

S

D

3

2

G

1

12

I

S1C47 1UF/16V

X7R 10% mx_c0603

GND

2Kbit

I

MU5 EEPROM 2 Kb

8

A0

VCC

7

A1

WP

6

A2

SCL

5

GND

SDA

IMPLP-MS

12

NOBOM

MR38 0

GND

+5V_LCD

1 2 3 4

GND

Title :

Engineer:

1

SCALAR_TSUMU88BDC2 - 2

Stonko_Chen

83Thursday, June 27 , 2013

29

83Thursday, June 27 , 2013

Rev

A00

5

DUAL I/O CONNECTOR

12

I

GND G ND

I

UC18

4.7PF/50V

Mode_butto n#20,28

UP_DOW N#28

Panel_SEL_12 3,28,51 Panel_SEL_22 3,28,51

SCL_BL_ PWM28

DUAL_CO N_DET#2 3

C1 470PF/50 V

X7R 10%

+5VA

SCL_BL_ EN28

LP6+ LP6-

LP5+ LP5-

I

URN13A

1 2

USBP624

D D

USBN624

USBP524

USBN524

C C

B B

0

1 4

3 4

0

I

URN13B

I

URN14A

1 2

0

1 4

3 4

0

I

URN14B

2 3

NI

UL13 90OHM

NI

UL14 90OHM

I

UC19

4.7PF/50V

I

UC17

4.7PF/50V

12

GND GND

12

GND G ND

I

UC20

4.7PF/50V

12

CH4

VP

12

C7

AZ5125-0 1J

4

I

C2

0.1UF/16V

X7R 10%

I

UQ10 CM1213_ 04SO

6

5

I

C6

AZ5125-0 1J

GNDGND

GND

DMIC-CLK43 DMIC-DATA43

CH1

1

VN

2

CH2CH3

34

GND

+5V_DUA L

1 2

R9 8.4 5K 1%

I

1 2

R10 2 .49KI1%

12

I

NOBOM

12

I

S1C25

0.1UF/16V

X7R 10%

GND GND

+3P3V

T69

12

I

S1C1

0.1UF/16V

X7R 10%

+5V_DUA L

NI

I

UF9

1.1A/6V

1 2

GND

I

UF11

1.1A/6V

1 2

12

I

C4

0.1UF/16V

X7R 10%

GND

1 2

R11 0

UP# DOWN #

+19V_BL _F

1

GND

12

NI

S1C48 10PF/50V

NPO 5%

GND

3

I

J1 WTOB _CON_40P

GND

1 2 3 4

5 6 7 8

13 33 40

9 10 11 12

34 35 36 38 37

14 15 16 17 18 19 20 22 21 23 24 25 26

+3P3V

1

MIC_CLK

2

MIC_DATA

3

GND

4

MIC

+3P3V

5

D+

6

D-

7

GND

8

Webcam

13

NC

33

NC

40

NC

+5V

9

D+

10

D-

11

GND

12

Touch

NC

34

Mode_button

35

UP#

36

DOWN#

38

GND

37

OSD

+19V

14

+19V

15

+19V

16

+19V

17

N/A

18

Panel_ID1

19

Panel_ID2

20

CON_EN

22

SCR_PWM

21

GND

23

GND

24

GND

25

GND

26

PWR_LED+

PWR_LED-

+5V

PWRBTN#

Power

32

28

29

30

Convert

39

Cable

39

detect

41

SIDE1

42

SIDE2

43

SIDE3

44

SIDE4

45

SIDE5

27

GND

27

X00 DUAL CONNECTOR 12X171803000-->12X371972000

HDD_LED+

31

I

UF10

1.1A/6V

1 2

PWRB TN#_DUAL

PWR_ LED1_C

12

PWR_ LED2_C

HD_LED# _C

AZ5125-0 1J

HD_LED_POW ER

+5V

NI

R12 0

1 2

I

R14 0

NI

R13 0

1 2

12

C12

I

GND

C10

AZ5125-0 1J

GND

12

I

R15 0

GND

3

C

E 2

GND

+5VA

12

I

12

I

C11

0.1UF/16V

X7R 10%

B

I

O2Q7 PMBS390 4

2

1

2

3

1

HD_LED# _R

GND

I

D1 BAT54SW

12

3

C

E 2

GND

+5V_DUA L

12

3

C

E 2

GND

I

O2R34 150

mx_r0805

B

1

I

O2Q3 PMBS390 4

I

O2R30 150

mx_r0805

B

1

I

O2Q4 PMBS390 4

I

R1 33

1 2

P_LED1_ R

I

O2R44 1K

1 2

C5

AZ5125-0 1J

1 2

+3P3VSB

I

O2R49 10K

3 C

E 2

GND

12

I

GND

I

O2R42 1K

I

O2Q10 PMBS390 4

B

1

+3P3V

12

+3P3VSB+5V_DUA L

I

O2R45 1K

12

I

O2R43 1K

I

O2R35 1K

HD_LED# 18

PWRB TN# 28,36 ,51

PWR_LED1_C PWR_LED2_C Color S0 S3 S4/S5 Error(w/BIOS) W/O BIOS

PWR_LED1 PWR_LED2 S0 S3 S4/S5 Error(w/BIOS) W/O BIOS

PWR_ LED1 3 6

PIN29 (LED+)

PIN30 (LED-)

Power LED Cable

+3P3VSB

12

I

O2R37 1K

12

1

0

1

0101....

0

1010....

0

1

0

0101....

0

X

X 1

1010....

HW

White

PWR_ LED2 3 6,39

PIN31

OSD Card

Amber

Solid White Blinking White No light Blinking Amber Solid Amber

+5V

HD LED

White

LVDS CONNECTOR

PANEL_B IST_ON28

A A

5

I

O3R1 0

12

PANEL_B IST_ON_R

LCD_O_IN3 P28

LCD_O_IN3 N28 LCD_E_IN3 P28 LCD_E_IN3 N28

LCD_O_IN2 P28

LCD_O_IN2 N28 LCD_E_IN2 P28 LCD_E_IN2 N28

LCD_O_IN1 P28

LCD_O_IN1 N28 LCD_E_IN1 P28 LCD_E_IN1 N28

LCD_O_IN0 P28

LCD_O_IN0 N28 LCD_E_IN0 P28 LCD_E_IN0 N28

I

P170 WTOB _CON_30P

14

BIST

3

O_IN3+

4

O_IN3-

5

E_IN3+

6

E_IN3-

15

O_IN2+

16

O_IN2-

17

E_IN2+

18

E_IN2-

21

O_IN1+

22

O_IN1-

23

E_IN1+

24

E_IN1-

27

O_IN0+

27

28

O_IN0-

28

29

E_IN0+

29

30

E_IN0-

30

X00 LVDS CONNECTOR 12X171802000-->12X371971000

4

+5V +5V +5V

O_CLK+ O_CLK E_CLK+ E_CLKDET DET GND GND GND GND

SIDE1 SIDE2 SIDE3 SIDE4 SIDE5

10 11 12 25

13 19 20 26

+5V_LCD

1

2

8

9

10 11 12 25 7

7

13 19 20 26 31 32 33 34 35

GND

12

I

C8 100PF/50 V

NPO 5%

GND G ND

12

I

C9 100PF/50 V

NPO 5%

3

LCD_O_C LKIN_P 28 LCD_O_C LKIN_N 2 8 LCD_E_C LKIN_P 28 LCD_E_C LKIN_N 2 8 LVDS_DE T_CBL2# 22

LVDS_DE T_CBL1# 22

12

GND

NI

O3C7 10UF/10V

mx_c0805

12

NI

O3C1 10UF/10V

mx_c0805

2

GND GNDGNDGND

12

I

O3C6

0.1UF/16V

X7R 10%

GND

12

I

O3C4 10PF/50V

NPO 5%

12

NI

O3C3

2.2PF/50V

NPO 5%

12

NI

O3C5 10PF/50V

NPO 5%

PEGATRON DT-MB RESTRICTED SECRET

CABLE CONNECTOR

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

IMPLP-MS

Engineer:

CABLE CONNECTOR

1

Stonko_Chen

30 83Thu rsday, June 27, 2013

Rev

A00

5

I

MR45

SL_HDMIB_ IN_TX0 P28

D D

SL_HDMIB_ IN_TX0 N28

SL_HDMIB_ IN_TX1 P28

SL_HDMIB_ IN_TX1 N28

SL_HDMIB_ IN_TX2 P28

C C

SL_HDMIB_ IN_TX2 N28

SL_HDMIB_ IN_CLK P28

SL_HDMIB_ IN_CLK N28

1 2

0

I

MR46 0

I

MR47 0

I

MR48 0

I

MR49 0

I

MR50 0

I

MR51 0

I

MR52 0

HDMIB_IN_TX0 P_C

HDMIB_IN_TX0 N_C

HDMIB_IN_TX1 P_C

HDMIB_IN_TX1 N_C

HDMIB_IN_TX2 P_C

HDMIB_IN_TX2 N_C

HDMIB_IN_CLK P_C

HDMIB_IN_CLK N_C

1 4

14

1 4

14

I

MRN3B

0

I

MRN3A

I

MRN2A

0

I

MRN2B

I

MRN1B

0

I

MRN1A

I

MRN4A

0

I

MRN4B

2 3

23

2 3

23

4

34

NI

ML14 90OHM

12

NI

ML16 90OHM

34

NI

ML13 90OHM

12

NI

ML15 90OHM

34

GND

NI

MU6 CM1213_ 04SO

CH1

1

2

3 4

NI

MU7 CM1213_ 04SO

1

2

3 4

6

5

6

5

VN

CH2 CH3

CH1

VN

CH2 CH3

3

CH4

+5VA

VP

CH4

+5VA

VP

From Extenal HDMI-IN +5V Power

I

MJ1 HDMI_CON_ 19P

GND

7

D0+

9

D0-

4

D1+

6

D1-

1

D0_Shd

1

D2+

3

D1_Shd

3

D2-

D2_Shd

10

CLK+

12

CLK-

16

DDC_DATA

15

DDC_CLK

13

CEC

17

GND

14

NC

CLK_Shd

10 12

16 15

13 17

14

HDMIB_IN_TX0 P HDMIB_IN_TX0 N

HDMIB_IN_TX1 P HDMIB_IN_TX1 N

HDMIB_IN_TX2 P

HDMIB_IN_TX2 N

HDMIB_IN_CLK P HDMIB_IN_CLK N

HDMIB_IN_SDA

HDMIB_IN_SCL

+5V

HPD

P_GND1 P_GND2 P_GND3 P_GND4

18

8 5 2

11

19

2

+5V_HDM I_IN

18

8 5 2 11

19

20 21 22 23

GND

1 2

+5VA

2

3

I

MR6 0

1

GND

I

MD3 BAT54SW

+5V

1

2

+5V_HDM I_IN

12

I

MR37 1K

12

I

MR41 100K

GND

I

MD8 BAT54CW

3

C

E 2

GND

+5V_EDID

3

I

MR53 0

1 2

NI

MQ9 PMBS390 4

B

1

I

MR36 100

1 2

HDMI_IN_HPD 28

B B

SL_HDMIB_ IN_SDA28 SL_HDMIB_ IN_SCL28

A A

DDPC_W P#28,29

EXTERNAL HDMI IN EDID

I

MU1

EEPROM 2Kb

1 2

5

I

MR44

4.7K

1

GND

+5V_EDID

B

12

GND

I

MR12 10K

3

C

E 2

1 2 3 4

I

MQ5 PMBS390 4

A0 A1 A2 GND

2Kbit

VCC

SCL SDA

8 7

WP

6 5

+5V_EDID

12

I

MC1

0.1UF/16V

X7R 10%

GND

4

+5V_EDID

12

I

MR42

4.7K

+5V_EDID

12

I

MR43

4.7K

I

MR3 100

1 2 1 2

I

MR4 100

+5VA

2

1

NI

MD1

3

BAT54SW

GND

3

+5VA

2

1

3

GND

NI

MD2 BAT54SW

PEGATRON DT-MB RESTRICTED SECRET

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

2

Date: Sheet of

Engineer:

IMPLP-MS

1

HDMI_IN

Stonko_Chen

31 83Thu rsday, June 27, 2013

Rev

A00

5

I

MC3

Place those AC Caps near to HDMI connector.

0.1UF/16V

X7R 10%

HDMID_TMD SD_DATA28

HDMID_TMD SD_DATA2#8

D D

HDMID_TMD SD_DATA18

HDMID_TMD SD_DATA1#8

HDMID_TMD SD_DATA08

HDMID_TMD SD_DATA0#8

C C

HDMID_TMD SD_CLK8

HDMID_TMD SD_CLK#8

1 2

I

MC4

0.1UF/16V

X7R 10%

1 2

I

MC5

0.1UF/16V

X7R 10%

1 2

I

MC6

0.1UF/16V

X7R 10%

1 2

I

MC7

0.1UF/16V

X7R 10%

1 2

I

MC8

0.1UF/16V

X7R 10%

1 2

I

MC9

0.1UF/16V

X7R 10%

1 2

I

MC10

0.1UF/16V

X7R 10%

1 2

X00 680 to 470 For EA HDMIOUT 7-2 10X253680140 -->10X253470140

1 2

MRN10A

I

MRN10B

I

MRN10C

G

2

S

I

MQ8 2N7002

I

MRN10D

I

MRN9A

I

MRN9B

I

MRN9C

I

MRN9D

I

+3P3V

1

3

D

2

S

B B

+3P3V

12

DDPD_CT RL_DATA22

A A

DDPD_CT RL_CLK22

5

I

MR7

2.2K

I

MR8

2.2K

1

G

470

3 4

470

5 6

470

7 8

470

1 2

470

3 4

470

5 6

470

7 8

470

I

MQ6 2N7002

3

D

4

HDMI_TMDS D_DATA2_C

HDMI_TMDS D_DATA2#_C

HDMI_TMDS D_DATA1_C

HDMI_TMDS D_DATA1#_C

HDMI_TMDS D_DATA0_C

HDMI_TMDS D_DATA0#_C

HDMI_TMDS D_CLK_C

HDMI_TMDS D_CLK#_C

HDMI_SE_S TBY_OFF_D0 HDMI_SE_S TBY_OFF_D0# HDMI_SE_S TBY_OFF_D2 HDMI_SE_S TBY_OFF_D2# HDMI_SE_S TBY_OFF_CK HDMI_SE_S TBY_OFF_CK# HDMI_SE_S TBY_OFF_D1 HDMI_SE_S TBY_OFF_D1#

HDMI_OUT_ 5V_L1

HDMI_OUT_ 5V_L2

12

I

MR9

2.2K

I

MR10

2.2K

4

I

1

2

BAW5 6WPT

MD9

I

MRN5B

34

0

90OHM ML9

NI

1 4

2 3

12

0

I

MRN5A

I

MRN6A

12

0

14

23

NI

ML10 90OHM

34

0

I

MRN6B

I

MRN7B

34

0

90OHM ML11

NI

1 4

2 3

12

0

I

MRN7A

I

MRN8A

12

0

14

23

NI

ML12 90OHM

34

0

I

MRN8B

I

MU2 CBT3245 ABQ

2

A1

3

A2

4

A3

5

A4

6

A5

7

A6

8

A7

9

A8

1

NC1

+5V

3

HDMI_OUT_ DDC_DATA

HDMI_OUT_ DDC_CLK

VCC OE#

GND1 GND2 GND3 GND4

GND

+5V_HDM I

20 19

HDMI_SE_S TBY_OFF_OE#

18

B1

17

B2

16

B3

15

B4

14

B5

13

B6

12

B7

11

B8

10 21 22 23

GND

3

HDMI_OUT_ DATA0_P HDMI_OUT_ DATA0_N

NI

MU3 CM1213_ 04SO

CH1

1

VN

2

CH2 CH3

3 4

HDMI_OUT_ DATA1_P HDMI_OUT_ DATA1_N

HDMI_OUT_ DATA2_P

HDMI_OUT_ DATA2_N

NI

MU4 CM1213_ 04SO

CH1

1

VN

2

CH2 CH3

3 4

HDMI_OUT_ CLK_P HDMI_OUT_ CLK_N

12

NOBOM

MR39 0

GND

2

3

12

3

1

GND

NI

MD5 BAT54SW

NI

MC11 470PF/50 V

X7R 10%

CH4

6

5

CH4

6

5

NI

MR16 0

+5VA+5VA

VP

2

3

12

GNDGND

+5VA

+3P3V

12

1

GND

NI

MD6 BAT54SW

NI

MC12 470PF/50 V

X7R 10%

+5VA

GND

I

MJ2 HDMI_CON_ 19P

7

D0+

7

9

D0-

9

4

D1+

4

6

D1-

6

1

D2+

1

3

D2-

3

10

CLK+

10

12

CLK-

12

16

DDC_DATA

16

15

DDC_CLK

15

13

CEC

13

17

GND

17

14

NC

14

2

D0_Shd D1_Shd D2_Shd CLK_Shd

P_GND1 P_GND2 P_GND3 P_GND4

2

+5V

HPD

18

8 5 2

11

19

18

8 5 2 11

GND

19

HDMI_HOTP LUG_DET

20 21 22 23

GND

1

+5V

2

S

G

1

D

I

3

MQ3 30mOhm/1 0V

I

MQ4

1

G

2N7002

2

DDPD_HP D_HDMI 22

S

+5V_HDM I

12

GND

12

I

MC13

0.1UF/16V

X7R 10%

I

MR11 20K

I

MF1

1.1A/6V

+5VA

2

1

3

12

GND

NI

MD7 BAT54SW

NOTE:

12

NI

AL1 0

mx_r0603

HDMI_5VPW

+3P3V

3

D

HPDET status

High Plugged

GND

Low

Unplugged

PEGATRON DT-MB RESTRICTED SECRET

HDMI OUT

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

Engineer:

IMPLP-MS

1

Stonko_Chen

32 83Thu rsday, June 27, 2013

+19V

GND

12

I

MR55 10K

12

I

MR54 15K

Rev

A00

5

4

3

2

1

D D

+3V_W LAN

12

I

X3R1

I

X3R15 0

WAKE #19,34,37

CK_100M _PE1#20 CK_100M _PE120

C C

PE5_RXN24 PE5_RXP24

PE5_TXN24 PE5_TXP24

I

X3R6 0

BT_DISABL E#23,51

HALF_DE T#23

B B

1 2

I

X3R9 0

1 2

SC31 0.1UF/1 6V X7R 10%

I

1 2

SC32 0.1UF/1 6V X7R 10%

I

+3V_W LAN

12

NI

X3R5

8.2K

CL_CLK2 1,34

CL_DATA2 1,34

CL_RST#21,34

10K

CLKREQ# _HCARD

+3V_W LAN

HALF_PE 5_TXN HALF_PE 5_TXP_C

BT_DISABL E#_R

HALF SIZE MINI CARD

I

J60 MINI_PCI_LATCH _52P

GND

1 3 5 7

9 11 13 15

17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

53 54

WAKE# COEX1 COEX2 CLKREQ# GND2 REFCLKREFCLK+ GND9

UIM_IC_DM UIM_IC_DP GND10 PERn0 PERp0 GND11 GND12 PETn0 PETp0 GND13 GND8 +3.3Vaux_3 +3.3Vaux_4 GND1 Reserved1 Reserved2 Reserved3 W_DISABLE2#

GND6 GND7

UIM_RESET

W_DISABLE1#

+3.3Vaux_1

SMB_DATA

LED_WWAN#

LED_WLAN# LED_WPAN#

+3.3Vaux_2

3.3Vaux_1 GND14

1.5V_1

UIM_PWR

UIM_DATA

UIM_CLK

UIM_SPU

GND15

PERST#

GND16

+1.5V_1

SMB_CLK

GND3

USB_D-

USB_D+

GND4

+1.5V_2

GND5

NP_NC2 NP_NC1

2 4 6 8 10 12 14 16

18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

56 55

GND

LP10LP10+

12

+3V_W LAN

12

I

X3C1

0.1UF/16V

X7R 10%

GND

+1P5V

I

12

X3C3 10UF/6.3V

X5R 10% mx_c0805_ small

GND

WL_ DISABLE# 18

PCIE_RST# 34,35 ,36,37,53

SMB_CLK _RESUME 21,34,39,47

SMB_DAT A_RESUME 21,34,39,47

12

NI

X3C9

0.1UF/16V

X7R 10%

GND

I

X3R11 0

12

I

X3C2 10UF/6.3V

X5R 10% mx_c0805_ small

GND

1 2

NI

X3R10 0

I

X3Q1 FDN340P _NL

D

3

G

1

+3P3VSB +5VSB

S

2

12

I

X3R2 10K

I

3

X3Q2

D

2N7002

1

G

S

2

GND

I

X3RN1A

1 2

0

1 4

2 3

3 4

0

I

X3RN1B

HALF_US B_DET# 23,51

NI

X3L1 90OHM

SLP_W LAN# 19

USBN10 24

USBP10 24

GND

I

H1 CT217B6 3D47

GND G ND

A A

I

H2 CT217B6 3D47

PEGATRON DT-MB RESTRICTED SECRET

PCI-E X1 SLOT

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

IMPLP-MS

1

Stonko_Chen

33 83Thu rsday, June 27, 2013

Rev

A00

5

4

3

2

1

+3P3V

D D

I

X3R13 0

mx_r0603

+3V_FUL L

12

FULL SIZE MINI CARD

12

I

X3C6

0.1UF/16V

X7R 10%

NI

X3C8 10UF/6.3V

X5R 10% mx_c0805_ small

I

X3C7 10UF/6.3V

X5R 10% mx_c0805_ small

GND

FULL_DISA BLE# 23

PCIE_RST# 33,35 ,36,37,53

SMB_CLK _RESUME 21,33,39,47

SMB_DAT A_RESUME 21,33,39,47

I

X3RN2A

1 2

0

1 4

3 4

0

I

X3RN2B

2 3

NI

X3L2 90OHM

USBN11 24

USBP11 24

GND

+1P5V

12

NI

X3C10

0.1UF/16V

X7R 10%

12

GND

12

GND

LP11LP11+

+3V_FUL L

12

I

X3R3 10K

WAKE #19,33,37

CLKREQ# _FCARD

CK_100M _PE2#20 CK_100M _PE220

C C

SATA_RX P5/PERP218 SATA_RX N5/PERN218

1 2

X3C4 0.0 1UF/25V X7R 10%

SATA_TX N5/PETN218 SATA_TX P5/PETP218

FULL_DE T#23

FULLCAR D_SEL2 3,51

FULLCARD_SEL 1:mSATA 0:PCIE

B B

CL_CLK2 1,33

CL_DATA2 1,33

CL_RST#21,33

A A

I

1 2

X3C5 0.0 1UF/25V X7R 10%

I

1 2

X3R12 0

I

+5VSB

12

I

X3R7 10K

I

3

X3Q11

D

2N7002

1

G

S

2

GND

1

G

3

2

D

S

I

X3Q8 2N7002

1

G

3

2

D

S

I

X3Q9 2N7002

1

G

3

2

D

S

I

X3Q10 2N7002

+3V_FUL L

SATA_TX N1_C SATA_TX P1_C

CL_CLK_ FULL CL_DATA _FULL CL_RST_ FULL

I

J61 MINI_PCI_LATCH _52P

1

WAKE#

3

COEX1

5

COEX2

7

CLKREQ#

9

GND2

11

REFCLK-

13

REFCLK+

15

GND9

17

UIM_IC_DM

19

GND

UIM_IC_DP

21

GND10

23

PERn0

25

PERp0

27

GND11

29

GND12

31

PETn0

33

PETp0

35

GND13

37

GND8

39

+3.3Vaux_3

41

+3.3Vaux_4

43

GND1

45

Reserved1

47

Reserved2

49

Reserved3

51

W_DISABLE2#

53

GND6

54

GND7

W_DISABLE1#

wait new MX part

I

H3 CT217B6 3D47

3.3Vaux_1 GND14

1.5V_1

UIM_PWR

UIM_DATA

UIM_CLK

UIM_RESET

UIM_SPU

GND15

PERST#

+3.3Vaux_1

GND16

+1.5V_1

SMB_CLK

SMB_DATA

GND3

USB_D-

USB_D+

GND4

LED_WWAN#

LED_WLAN# LED_WPAN#

+1.5V_2

GND5

+3.3Vaux_2

NP_NC2 NP_NC1

GND

2 4 6 8 10 12 14 16

18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

56 55

GND

PEGATRON DT-MB RESTRICTED SECRET

FULL MINI-PCIE

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

IMPLP-MS

1

Stonko_Chen

34 83Thu rsday, June 27, 2013

Rev

A00

5

4

3

2

1

CARDREADER RST5209

IC OUTPUT FOR 1st LUN MEMORY CARD (all types memory cards)

12

1 2

I

OP1R2 0

1 2

I

OP1R3 0

+3P3V_C ARD

Output capability is 800mA. Current protection is 950mA.

CR_SD_C MD CR_SD_C D#

12

NI

OP1C12

0.1UF/16V

X7R 10%

GND

MS_CLKCR_SP14

12

NI

OP1C11

0.1UF/16V

X7R 10%

GND

+3P3V_C ARD

12

I

OP1C13 10UF/6.3V

X5R 10% mx_c0805_ small

12

GNDGND

+3P3V_C ARD

12

GND

I

O O

OP1U1 RTS5209 -GR

11 47

1 2 6 7

14 27

5 9

48

3 4

45

3V3_IN1 3V3_IN2

HSIP HSIN HSOP HSON

DV33_18 DV12_S

AV12 DV12 RREF

REFCLKP REFCLKN

PERST#

Card1_3V3

SD_D0 SD_D1 SD_D2 SD_D3

SD_CMD

SD_CD# SD_CLK

SP15

SP1 SP2 SP3 SP4 SP5 SP6 SP7 SP8

SP9 SP10 SP11 SP12 SP13 SP14

xD_CD#

10

CR_3V3

O

21 20 25 24

23 39 22 38

16 17 18 19 28 29 30 31 32 33 34 35 36 37

13

+3P3V

D D

PE3_TXP24 PE3_TXN24 PE3_RXP24 PE3_RXN24

C C

12

I

OP1C7

4.7UF/6.3V

X5R 10% mx_c0603

B B

12

I

OP1C1 10UF/6.3V

X5R 10% mx_c0805_ small

GND G ND

1 2

OP1C9 0.1UF /16V X7R 10%

I

1 2

OP1C10 0.1UF/16V X7R 10%

I

12

I

OP1C6

0.1UF/16V

X7R 10%

GND

1 2

NI

OP1R4 0

mx_r0603

GND

CK_100M _PE320 CK_100M _PE3#20

PCIE_RST#33,34,36,37 ,53

GND

12

I

OP1C2

0.1UF/16V

X7R 10%

12

I

OP1C4

4.7UF/6.3V

X5R 10% mx_c0603

I

OP1C8

0.1UF/16V

X7R 10%

12

GND

12

GND

12

GNDGND

I

OP1C3

0.1UF/16V

X7R 10%

PE3_RXP 1_C PE3_RXN 1_C

CR_DV33 _18

DV12_S

I

OP1C5

0.1UF/16V

X7R 10%

AV12 DV12 CR_RREF

I

OP1R1

6.2K

1%

I

O1R2 0

mx_r1206

CR_SD_D 0 CR_SD_D 1 CR_SD_D 2 CR_SD_D 3

CR_SD_C LK SD_CLK CR_SP15

CR_SP5

CR_SP7

CR_SP9 CR_SP10

CR_SP12

X00 Card Reader 12XC4CE42001-->12X341490000 R1.03 Card Reader 12X341490000-->12XC3C321000

I

OP1C14

0.1UF/16V

X7R 10%

I

OP1C16

0.1UF/16V

X7R 10%

I

J56 CARD_RE ADER_21P

10

SD_VCC

3

SD_DAT0

2

SD_DAT1

20

SD_DAT2

18

SD_DAT3

15

SD_CMD

21

SD_CD_SW

7

SD_CLK

1

SD_WP_SW

17

MS_VCC

6

MS_BS

8

MS_DATA1

9

MS_DATA0

11

MS_DATA2

14

MS_DATA3

16

MS_SCLK

22

NP_NC1

23

NP_NC2

8

GND1

15

GND2

26

GND3

GND

12

NI

OP1C20

0.1UF/16V

X7R 10%

GND

A A

5

46 44 43 42 41 12

CLK_REQ# EEDO EECS EESK GPIO/EEDI Card2_3V3

4

MS_INS#

40

CR_MS_INS #

GND

3

2

13

MS_INS

4

SD_GND

12

SD_GND1

5

MS_GND

19

MS_GND1

24

SIDE1

25

SIDE2

PEGATRON DT-MB RESTRICTED SECRET

CARDREADER RST5209

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

IMPLP-MS

Engineer:

CARDREADER RST5209

1

Stonko_Chen

35 83Thu rsday, June 27, 2013

Rev

A00

5

4

3

2

1

I

O2U1 F71808A U-LAB

25

O

I_VSB3V

NI

O2D1 1SS355P T

38

5VSB

48

3VSB

1

3VCC

37

VBAT

4

(IPU)

LFRAME#

5

(IPU)

LAD0

6

(IPU)

LAD1

7

(IPU)

LAD2

8

(IPU)

LAD3

3

(IPU)

SERIRQ

10

CLKIN

9

PCICLK

2

LRESET#

14

O.D.

KDAT/GPIO10/FANIN3

15

O.D.

KCLK/GPIO11/OVT#

16

O.D.

SUS_ACK#/MDAT/GPIO12

17

O.D.

SUS_WARN#/MCLK/GPIO13/CIRWB#

12

O.D.(IPU)

KBRST#

13

GA20

62

O.D.

FANCTL1

61

FANIN1

64

FANCTL2/GPIO34

63

FANIN2/GPIO35

19

GPIO21/OVT#/FANIN3

20

GPIO22/PWM/ERP_CTRL1#

26

ERP_CTRL0#

53

O.D.

DCD#/GPIO00/SDA

54

O.D.

RI#/GPIO01/OVT#/CIRWB#

55

O.D.

CTS#/GPIO02/CIR_LED

58

O.D.

DSR#/GPIO05/BEEP

60

O.D.

SIN/GPIO07/CIRWB#

57

RTS#/GPIO04/PWM/STRAP_PWOK

If you do not use the UART port, Pin 53/55/58/60: please pull-up these pin to +3P3V Pin 54: please pull-up these pin to +3P3VSB

RSMRST#

PSIN#/GPIO27

PSOUT#/GPIO14

PSON#

S3# S5#

DPWROK/GPIO23/WDTRST#/FANIN3

GPIO25/LEDVCC/WDTRST#

WDTRST#/RSTCON#/GPIO26/SLP_SUS#

SOUT/GPIO06/STRAP4E_2E

VDIMM/VIN3/SUS_WARN2#

VLDT_EN/GPIO31/SDA

VCORE_EN/GPIO30/SUS_ACK2#

PWOK

S3_GATE#

GPIO20/PME#

GPIO24/LEDVSB

DTR#/GPIO03/CIRTX

SCL/GPIO33

PECI/SDA/GPIO32

VREF

D1+

AGND/D-

D2+

CIRRX#

COPEN#

VLDT/VIN2

VCORE/VIN1

PCIRST1# PCIRST2#

GND1

3

36

31 32

34

33 30

21 35 24 18

22 23

27 56 59 52 51

42

41

39

40

43 44 45 46 47

28 29

50 49

11

12

+3P3V

I

O2R5

4.7K

CPUFAN_ PWM48 CPUFAN_ TACH48

12

GND

I

O2R11

4.7K

I_VSB3V

I

O2CB2 1000PF/5 0V

X7R 10%

LFRAME#21,48 LAD021,48 LAD121,48 LAD221,48 LAD321,48

+3P3V+3P3V+3P3V+3P 3V

12

GND

4

12

SIO_KDAT SIO_KCLK

+3P3V

12

I

O2R26

4.7K

O.D. (GPI) (DSW) O.D. (GPO) (DSW)

NI

O2R10

4.7K

DCD# OVT# CTS# DSR# SIN

STRAP_P WOK

I

O2R15 1K

+5VA

I

O2CB4

0.1UF/16V

X7R 10%

I

O2R3 10K

I

O2R51 10K

12

GND

12

I

O2R14

4.7K

12

I

O2R1 10

1%

12

I

O2CB3

0.1UF/16V

X7R 10%

SERIRQ21 CK_48M_ SIO120 CK_33M_ SIO120 PLTRST#22

I

O2R47

4.7K

12

+5VSB +5VS B+3P3V+3P3V

NI

O2R13

4.7K

12

NI

O2R6

4.7K

12

NI

O2R12

4.7K

RST_KB#23 A20GATE23

D

S

ME

Disable

SIO_RX028

+BATT

12

I

+3P3V

O2D3 1SS355P T

12

GND

I

3

O2Q11 2N7002

1

G

2

D

S

GND

12

I

O2CB5

0.1UF/16V

X7R 10%

Pin 3: SERIRQ Please check if this pin need be pull-up on chipset side!

3

2

I

O2CB1

0.1UF/16V

X7R 10%

GND

+5VSB +5VSB

12

I

O2R53

4.7K

+5VA+3P3 VSB

12

3

D

S

2

GND

+3P3V

NI

O2Q13 2N7002

1

G

5

D

S

GND

+3P3VSB

12

GND

12

I

O2R4 10K

I

+3VA

O2R50 10K

12

I

O2Q12 2N7002

1

G

PSID39

12

NI

O2R52 10K

3

NI

O2Q1 2N7002

1

G

2

1 : PWOK (pin 35) for AMD (Default) 0 : PWOK (pin 35) for Intel

D D

Pin 14/15/16/17:

1. Please check if this pin need be pull-up on chipset side!

2. If you do not use the KBC,

C C

please pull-up these pin to +5VSB.

HDA_SDO18

B B

PIN15

H EN

L

PROCHOT _SIO#9

A A

+3P3VSB +5VA+3VA+5 VA

O.D.

O.D. O.D.

O.D.

O.D. (GPO) (DSW) O.D. (GPO) (DSW)

O.D.

GND

D2+

COPEN#

O.D. O

O.D.

GND

12

+3VA

12

I

O2R17

O2R16

4.7K

+3P3V

12

I

NI

O2R20

O2R21

4.7K

12

NI

O2CB11

0.1UF/16V

X7R 10%

GND

SLP_SUS # 19,75

12

I

O2R24 100K

Avoid pre-bios floating

GND

NOBOM

S1 SHORTPIN

1 2

NOBOM

S2 SHORTPIN

I

O2R25 2M

PCIE_RST# 33,34 ,35,37,53

12

+3VA

12

+BATT

12

I

O2R18

4.7K

I

O2R9

4.7K

12

I_GPU

O2CB12 3300PF/5 0V

X7R 10%

12

I

O2CB13 3300PF/5 0V

X7R 10%

+3P3V

12

I

O2R19

4.7K

I

O2R27

4.7K

1 2

D2+_S

+3P3V

12

2

NI

O2D2 1SS355P T

+3P3VSB

12

GND

I

O2R29

4.7K

NI

O2R22 1K

I

O2R23 1K

RSMRST# 19,51

PWRB TN# 28,30 ,51 SB_PW RBTN# 19,29

PSON# 66,79

SLP_S3# 19,67,68 SLP_S4# 19,66,67,79

PWR_ LED2 3 0,39 PWR_ LED1 3 0

+3P3V

12

NI

O2R48

4.7K

ATX_PW RGD

PCH_DPW ROK 19,51 PWRO K 13,19

LPC_PME # 2 3

Pin 27: SIO invert internally SLP_SUS from PCH and output ERP_CTRL0# to control DSW.

Pin 59: 1 : Configuration Register I/O port is 4E/4F.(Default) 0 : Configuration Register I/O port is 2E/2F.

1

SMB_DAT A_SIO_MAIN 47,54

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Date: Sheet of

NI

3

O2Q9

D

2N7002

1

G

S

2

GND

GND G ND

SIO_TX0 28 SMB_CLK _SIO_MAIN 47,54 PECI_SIO 9,2 3

2 E

NI

O2Q5

B

PMBS390 6

C

3

C

I

B

O2Q6 PMBS390 6

E 2

Size Project Name

A3

IMPLP-MS

NI

12

NC182 1UF/16V

X7R 10% mx_c0603

D1+ 54

D1+_S 54

+3P3V

12

NI

O2R31

4.7K

NI

3

O2Q8

D

2N7002

1

G

S

2

GND

12

NI

NC181 1UF/16V

X7R 10% mx_c0603

For GPU Temp.

For SO-DIMM Temp.

Title :

Engineer:

1

SIO F71808A

Stonko_Chen

36 83Thu rsday, June 27, 2013

+19V

GND

12

NI

O2R32

3.3K

NI

O2R33 1K

Rev

A00

5

4

3

2

1

NOTE: +3P3VSB power trace must be wider than 40 mils

+3P3VSB

D D

12

I

LR1 200K

LAN_GAT E#

12

I

LR10 10K

GND

For RTL8151G(S)D

C C

* Place LC4 to LC8 close to each VDD10 pin-- 3, 8, 22, 30

B B

A A

5

I

LQ1 NTR4101 PT1G

D

S

2

3

12

I

LC1 1UF/16V

X7R 10%

NOTE: +1P05V_LAN power trace must be wider than 60 mils

G

1

RL_LAN_ TXP24 RL_LAN_ TXN24

RL_LAN_ RXP24 RL_LAN_ RXN24

RL_CK_1 00M_LAN20 RL_CK_1 00M_LAN#20

12

For RTL8151G(S)D * Place C1 and C2 close to each VDD33 pin-- 11, 32

12

I

LR4 0

mx_r1206

12

GNDGND GND

LC2

0.1UF/16V

X7R 10%

I

LC6

0.1UF/16V

X7R 10%

I

LC8

0.1UF/16V

X7R 10%

NOBOM

LR2 0

mx_r0603_sho rt

NOBOM

LR3 0

mx_r0603_sho rt

NOBOM

LR5 0

mx_r0603_sho rt

RTL8151GSD: Switching Regulator 1.0V Output RTL8151GD: LDO Regulator 1.0V Output

1 2

12

I

LC5

0.1UF/16V

X7R 10%

GND G ND GND

12

NI

LC9

0.1UF/16V

X7R 10%

Place close to PIN 22

12

LC10 0.1UF/16V X7R 10%

I I

GND GNDGND

12

LC11 0.1UF/16V X7R 10%

1 3

12

I

LC12 10PF/50V

NPO 5%

I

2

4

Y10 25MHZ

4

GNDGND

GND

12

I

LC3

0.1UF/16V

X7R 10%

12

I

LC4

0.1UF/16V

X7R 10%

12

I

LC7

0.1UF/16V

X7R 10%

12

I

LC168 1UF/16V

X7R 10% mx_c0603

12

RL_AVDD 33

VDDREG

RL_REGO UT+1P05V_ LAN

RL_AVDD 10

RL_EVDD 10

RL_LAN_ RXP_C RL_LAN_ RXN_C

RL_XTAL 1

RL_XTAL 2

I

LC13 10PF/50V

NPO 5%

I

LU1A RTL8151 GD-CG

11

AVDD33_1

32

AVDD33_2

23

VDDREG

24

REGOUT

3

AVDD10_1

8

AVDD10_2

30

AVDD10_3

22

DVDD10

13

HSIP

14

HSIN

17

HSOP

18

HSON

15

REFCLK_P

16

REFCLK_N

28

CKXTAL1

29

CKXTAL2

1

MDIP0

2

MDIN0

4

MDIP1

5

MDIN1

6

MDIP2

7

MDIN2

9

MDIP3

10

MDIN3

O.D.

12

CLKREQB

Input

20

ISOLATEB

Input

19

PERSTB

O.D.

LED0

LED1/GPO

LED2

RSET

GND

GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8

I

LU1B RTL8151 GD-CG

21

GND

27

26

25

Input

31

33

34 35 36 37 38 39 40 41

GND

LANWAKEB

3

LAN_MDI0_ P 38 LAN_MDI0_ N 38

LAN_MDI1_ P 38 LAN_MDI1_ N 38

LAN_MDI2_ P 38 LAN_MDI2_ N 38

LAN_MDI3_ P 38 LAN_MDI3_ N 38

12

CLKREQ#

ISOLATE#

PCIE_RST# 33,34 ,35,36,53

WAKE # 19 ,33,34

12

NI

LC169

0.1UF/16V

X7R 10%

LAN_LED 0_1G# 38

LAN_LED 1_100M# 38

LAN_LED 2_ACT# 38

RL_RSET

GND

+3P3V+3P3V

12

I

LR6 10K

12

GND

12

I

LR9

2.49K

1%

Close to LAN chip

Consider VCC33 may be connected to Main Power or chipset/bios's GPO, the pull-low

I

LR7 1K

I

LR8 15K

Please make sure WAKE# has been pulled up +3P3VSB through 10K on PCH side (Realtek recommendation).

2

resistor LR8 can be NC only when Main Power or chipset/bios's GPO can ensure to drive the ISOLATEB pin to a voltage level < 0.8V at the system state S1~S5. If the ISOLATEB pin can not be well-controlled to a voltage level < 0.8V at S1~S5, the pull-low resistor R14 is needed to make sure the LAN chip is well isolated.

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

IMPLP-MS

Title :

Engineer:

1

LAN RTL8151GD

Stonko_Chen

37 83Thu rsday, June 27, 2013

Rev

A00

5

D D

4

3

2

1

I

LR16 249

1%

LAN_LED 1_100M#37

I

LAN_MDI3_ P37

C C

B B

LAN_MDI3_ N37

LAN_MDI2_ P37

LAN_MDI2_ N37

LAN_MDI1_ P37

LAN_MDI1_ N37

LAN_MDI0_ P37

LAN_MDI0_ N37

3 4

14

1 2

I

3 4

14

1 2

I

3 4

14

1 2

I

3 4

14

1 2

I

LRN4B

0

23

NI

LL4 90OHM

CH1

1

VN

2

CH2 CH3

3 4

GND

CH1

1

VN

2

CH2 CH3

3 4

GND

I

LU3 CM1213_ 04SO

I

LU4 CM1213_ 04SO

CH4

6

+5VA

VP

5

LAN_MDI3_ P_C

LAN_MDI3_ N_C

LAN_MDI2_ P_C

LAN_MDI2_ N_C

LAN_MDI1_ P_C

LAN_MDI1_ N_C

LAN_MDI0_ P_C

LAN_MDI0_ N_C

CH4

6

+5VA

VP

5

I

LU2 GST5009 BMLF

TCT1

1 2

TD1+

3

TD1-

4

TCT2

5

TD2+

TD2-

6

TCT3

7 8

TD3+

9

TD3-

10

TCT4

11

TD4+

12 13

TD4-

SURGE_IN_C

I

12

LC14

0.01UF/25 V

X7R 10%

GND

SURGE

1:1

MX1+

MCT1

MX1MCT2

MX2+

MX2-

MCT3

MX3+

MX3-

MCT4

MX4+

MX4-

24 23

22 21 20

19 18 17

16 15 14

MCT3

LAN_MDI3_ P_L

LAN_MDI3_ N_L

MCT2

LAN_MDI2_ P_L

LAN_MDI2_ N_L

MCT1

LAN_MDI1_ P_L

LAN_MDI1_ N_L

MCT0

LAN_MDI0_ P_L

LAN_MDI0_ N_L

0

LRN4A

LRN3B

0

23

NI

LL3 90OHM

0

LRN3A

LRN2B

0

23

NI

LL2 90OHM

0

LRN2A

LRN1B

0

23

NI

LL1 90OHM

0

LRN1A

1 2

12

I

LR11 75

SURGE_O UT_C

12

I

LC15 1000PF/2 KV

X7R 20%

GND

12

I

LC16 1000PF/5 0V

X7R 10%

I

LR15 249

1%

12

I

LR12 75

GND

12

I

LC17 1000PF/5 0V

X7R 10%

GND

12

I

LR14

LR13

75

I

J7

11

LED2

12

LED1

7

BI_D4+

7

8

BI_D4-

8

4

BI_D3+

4

5

BI_D3-

5

3

RX_D2+

3

6

RX_D2-

6

1

TX_D1+

1

2

TX_D1-

2

LAN_JAC K_12P

LED3

O

Y

G

LED4

P_GND1

P_GND2

+3P3VSB

10

I

LR17 510

mx_r0603 1%

9

1 2

LAN_LED 2_ACT# 37LAN_LED 0_1G#37

13

14

GND

A A

PEGATRON DT-MB RESTRICTED SECRET

RJ45 CONN.

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

5

4

3

2

Date: Sheet of

IMPLP-MS

Engineer:

1

RJ45 CONN.

Stonko_Chen

38 83Thu rsday, June 27, 2013

Rev

A00

5

4

3

2

1

TO USB CARD CONNECTOR

I

UJ5

GND

21

22

SIDE1

SIDE2

WTOB _CON_20P

GND

1

3

5

7

9

11

13

15

17

19

USB3_TX _P6 24 USB3_TX _N6 2 4

USB3_RX _P6 24

USB3_RX _N6 24

USBP4 24

12

+

NI

UC4 100UF/6.3 V

USBN4 24

12

GND

+USB3_6

12

GNDGND

NI

UC3

0.1UF/16V

X7R 10%

GND G ND

I

UR4 10K

I

UR3 15K

I

UF2

1.1A/6V

+5V_DUA L

12

OC3# 24,51

D D

USB3_TX _P524 USB3_TX _N524

USB3_RX _P524

GND

USB3_RX _N524

USBP324 USBN324

USB_CAR D_DET#23,48

12

I

UR1 10K

I

UR2 15K

12

NI

+

UC1 100UF/6.3 V

GNDGND

12

NI

UC2

0.1UF/16V

X7R 10%

+USB3_5

+5V_DUA L

C C

I

UF1

1.1A/6V

1 2

OC2#2 4,51

2

4

6

8

10

12

14

16

18

20

PSID CIRCUIT

IF don't use PSID circuit Integrated PR167, NI Other

EC FOR ADAPTER PSID

IF use PSID circuit NI PR167

NI

EU1

NI

EC1

0.1UF/16V

X7R 10%

2

CY8C21223 -24LGXI

13

VDD

3

I2C_SCL/P1[7]

4

I2C_SDA/P1[5]

6

I2C_SCL/P1[1]

8

I2C_SDA/P1[0]

2

AI/P0[1]

1

AI/P0[3]

P1[3] P1[4] P1[6]

P0[5] P0[7]

P0[4] XRES

Title :

Engineer:

1

ET5

1 1

1

NOBOM

ET6

NOBOM

ET7

NOBOM

ET8

NOBOM

ET9

NOBOM

ET10

NOBOM

ET11

NOBOM

USB&AUDIO CARD&EC

Stonko_Chen

39 83Thu rsday, June 27, 2013

5

P1[3]

10

P1[4]

9

P1[6]

15

P0[5]/AI

14

P0[7]/AI

12

P0[4]/VREF

11

IPD

XRES

16

NC

7

Vss

GND

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

IMPLP-MS

Rev

A00

ET1 ET2

1 2 1 2

+3P3V

GND

1 1

P1[1] P1[0]

12

B B

PSID_IN65 PSID 36,39

12

NI

PR163 100K

1%

12

NI

PR164

GND

15K

1%

A A

5

D

3

NI

PQ72 2N7002

B

1

I

PR167 0

1 2

S

2

G

1

3

C

NI

PQ73 PMBS390 4

E 2

GND

NI

PR166 33

1 2

+5V

12

NI

PR165 10K

1%

+5V

GND

1

2

I

PD9 BAV99W -L

3

SMB_CLK _RESUME21,33,34,4 7

SMB_DAT A_RESUME21,33,34,4 7

NOBOM NOBOM

R3 0

PSID36,39

PWR_ LED23 0,36

4

3

NI

R8 0

NI

5

I

URN2B

3 4

USB3_RX _N124

D D

USB3_RX _P124

USB3_TX _N124

USB3_TX _P124

C C

0

14

1 2

0

I

URN2A

I

URN1B

3 4

0

14

1 2

0

I

URN1A

23

NI

UL2 90OHM

NI

UL1 90OHM

GND

I

UQ2 IP4284CZ1 0-TB

4

3 1 2

4

USB3_RX _H_N1

USB3_RX _H_P1

TMDS_CH2TMDS_CH2+5NC1 GND1 TMDS_CH1TMDS_CH1+

GND2

USB3_TX _H_N1

USB3_TX _H_P1

NC2

NC4 NC3

3

URN3A

I

1 2

0

1 4

3 4

0

URN3B

I

2 3

NI

UL3 90OHM

+5VA

12

I

UC21

4.7PF/50V

GND G ND

I

UQ1 CM1213_ 04SO

CH4

6

VP

5

12

I

UC22

4.7PF/50V

CH1

1

VN

2

CH2CH3

34

GND

USBP124

USBN124

7 6 8 10 9

2

I

UJ1 USB_CON _9P

12

P_GND3

10

P_GND1

5

4

6

3

L1+

L1-

12

I

UC5

0.1UF/16V

X7R 10%

GND G ND

GND

3

7

2

8

1

9

11

P_GND2

13

P_GND4

+

+USB3_1

12

I

UC6 100UF/6.3 V

1

I

+5V_DUA L

UF3

1.1A/6V

12

I

UR6 10K

12

I

UR5 15K

OC0# 24,51

I

URN4B

3 4

USB3_RX _N224

USB3_RX _P224

B B

USB3_TX _N224

USB3_TX _P224

A A

5

0

14

1 2

0

I

URN4A

I

URN5B

3 4

0

14

1 2

0

I

URN5A

23

NI

UL4 90OHM

NI

UL5 90OHM

GND

USB3_RX _H_N2

USB3_RX _H_P2

I

UQ3 IP4284CZ1 0-TB

4

TMDS_CH2TMDS_CH2+5NC1

3

GND1

1

TMDS_CH1-

2

TMDS_CH1+

USB3_TX _H_N2

USB3_TX _H_P2

NC2

GND2

NC4 NC3

I

UJ2 USB_CON _9P

12

P_GND3

10

P_GND1

5

GND

5

4

6

3

7

2

8

1

9

11

P_GND2

13

P_GND4

+USB3_2

12

+

I

UC8 100UF/6.3 V

2

URN6B

I

3 4

7 6 8 10 9

GND

4

USBP224

USBN224

0

14

1 2

0

URN6A

I

3

23

90OHM UL6

NI

12

I

UC23

4.7PF/50V

GND G ND

12

I

UC24

4.7PF/50V

L2+

L2-

12

I

UC7

0.1UF/16V

X7R 10%

GND G ND

GND

I

+5V_DUA L

UF4

1.1A/6V

12

I

UR8 10K

OC1# 24,51

PEGATRON DT-MB RESTRICTED SECRET

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

Engineer:

IMPLP-MS

1

GND

12

I

UR7 15K

LEFT USB3 CONN.

Stonko_Chen

40 83Thu rsday, June 27, 2013

Rev

A00

5

4

3

2

1

I

UR10 10K

I

UR9 15K

I

UR12 10K

I

UR11 15K

I

UF5

1.1A/6V

OC4# 24,51

I

UF6

1.1A/6V

OC5# 24,51

+5V_DUA L

12

+5V_DUA L

12

D D

+USB2_1

URN9A

I

1 2

USBN824

USBP824

C C

USBN924

B B

USBP924

0

1 4

3 4

0

URN9B

I

URN12B

I

3 4

0

14

1 2

0

URN12A

I

2 3

23

NI

UL9 90OHM

NI

UL12 90OHM

+5VA

12

I

UC25

4.7PF/50V

GND G ND

I

UQ5 CM1213_ 04SO

CH4

6

VP

5

12

I

UC27

4.7PF/50V

GND G ND

12

I

UC28

4.7PF/50V

I

UC26

4.7PF/50V

CH1

1

VN

2

CH2CH3

34

GND

L8L8+

L9L9+

GND

I

UJ3

1

+5V

1

2

D-

2

3

D+

3

4

GND

4

USB_CON _1X4P

I

UJ4

1

+5V

1

2

D-

2

3

D+

3

4

GND

4

USB_CON _1X4P

P_GND2

GND2

GND1

P_GND1

P_GND2

GND2

GND1

P_GND1

I

UC9

0.1UF/16V

X7R 10%

I

UC11

0.1UF/16V

X7R 10%

12

+

I

UC10 100UF/6.3 V

12

+

I

UC12 100UF/6.3 V

GND

+USB2_2

GND

12

GND G ND

12

GND G ND

8 6

5 7

8 6

5 7

12

GND

12

GND

A A

PEGATRON DT-MB RESTRICTED SECRET

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

IMPLP-MS

REAR USB2 CONN.

Stonko_Chen

1

Rev

A00

41 83Thu rsday, June 27, 2013

A00

5

D D

SATA_TX P018 SATA_TX N01 8

SATA_RX N018 SATA_RX P018

C C

4

1 2

TR1 0.01 UF/25V X7R 10%

I

1 2

TR2 0.01 UF/25V X7R 10%

I

1 2

TR3 0.01 UF/25V X7R 10%

I

1 2

TR4 0.01 UF/25V X7R 10%

I

+3P3V

12

I

TC4 10UF/6.3V

X5R 10% mx_c0805_ small

GND G ND

12

I

TC3

0.1UF/16V

X7R 10%

+5V

12

I

TC1 10UF/6.3V

X5R 10% mx_c0805_ small

GND G ND

SATA_TX P0_C SATA_TX N0_C

SATA_RX N0_C SATA_RX P0_C

12

I

TC2

0.1UF/16V

X7R 10%

GND

3

I

TJ1 SATA_CO N_22P

S1

S2

S3

S4

S5

S6

S7

P1

P2

P3

P4

P5

P6

P7

P8

P9

P10

P11

P12

P13

P14

P15

P_GND1

P_GND2

2

1

2

GND

1

GHS JACK 12X241667000 -->12X241998000

B B

A A

PEGATRON DT-MB RESTRICTED SECRET

SATA CONNECTOR

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

IMPLP-MS

1

Stonko_Chen

42 83Thu rsday, June 27, 2013

Rev

A00

5

4

3

2

1

ALC3661 CODEC

I

AR57

+3P3V

0

mx_r0603

1 2

I

12

AC6

D D

I

AR26 33

AZ_SDAT A_IN18

AZ_SDAT A_OUT18 AZ_SYNC18 AZ_RST#18,45 AZ_BITCLK18

C C

1 2

10UF/6.3V

X5R 10% mx_c0805_ small

GND G ND GND

12

NI

AC47 22PF/50V

NPO 5%

GND G ND

I

12

AC5

0.1UF/16V

X7R 10%

12

NI

AC48 22PF/50V

NPO 5%

AUDIO_SHU TDOWN#44

A_DVDD

I

12

AC4

0.1UF/16V

X7R 10%

SDATA_IN_ R

REGREF

I

12

AC49 10UF/6.3V

X5R 10% mx_c0805_ small

GND

1.8V

Close to Pin12

1 2

AR3 39

I

AC3 22PF/50V

NPO 5%

+3P3V

I

1 2

AR4 0

I

+5VSB

I

AR58 0

mx_r0603

1 2

I

AR56 0

mx_r0603

1 2

I

12

AC11 10UF/6.3V

X5R 10% mx_c0805_ small

AGND

SCALAR_ MODE#20,28,5 1

I

12

AC18 10UF/6.3V

X5R 10% mx_c0805_ small

AGND

I

12

AC10

0.1UF/16V

X7R 10%

4

DMIC-CLK30 DMIC-DATA30

NOBOM

B B

A A

S3 SHORTPIN

1 2

AC55 0.1 UF/16V

NI

1 2

AR59 0

I

GND AGN D

5

12

NI

AC2 22PF/50V

NPO 5%

GND GND

X7R 10%

12

R_DMIC-CLK R_DMIC-DAT A

Close to Pin39

A_LDO_IN

I

12

AC17

0.1UF/16V

X7R 10%

AGND

A_HDVDD

I

12

AC9

0.1UF/16V

X7R 10%

AGNDAGND

CPVEE

I

12

AC8

2.2UF/6.3V

X5R 10% mx_c0603

AGND

GND

AGND

I

AU1A ALC3661 -CG-A3

11

DVDD

7

DVDD-IO

49

GND

8

SDATA-IN

4

SDATA-OUT

9

SYNC

6

RESETB

5

BCLK

10

REGREF

14

EAPD

15

SPDIF-OUT

16

SPDIF-IN

2

PCBEEP

12

GPIO0/DMIC-CLK

13

GPIO1/DMIC-DATA

17

GPIO2/Combo-Jack1

3

GPIO3/Combo-Jack2

39

LDO-IN

42

AVSS2

23

HVDD

25

DVDD-IO-CP

22

AVSS1

20

CPVEE

28

CPVREF

SURR-R(PORT-A-R)

SURR-L(PORT-A-L)

MIC1-R(PORT-B-R)

MIC1-L(PORT-B-L)/MIC-CAP

LINE1-R(PORT-C-R)

LINE1-L(PORT-C-L)

FRONT-R(PORT-D-R)

FRONT-L(PORT-D-L)

LINE2-IN-R(PORT-E-R)/SLEEVE

LINE2-IN-L(PORT-E-L)/RING2

MIC2-VREFO

LFE(PORT-G-R) CEN(PORT-G-L)

SenseA

SenseB

MIC2-R(PORT-F-R)

MIC2-L(PORT-F-L)

LINE2-VREFO

MIC1-VREFO

CBP

CBN

JDREF

LDO-CAP

VREF

VRP

I

AU1B ALC3661 -CG-A3

GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8

3

27 26

HPOUT1_ R 45 HPOUT1_ L 45

To Global Headset

For MIC quality

37 36

MIC-CAP

46

I_F_LIN1_R

45

I_F_LIN1_L

44 43

1 2

AC16 10 UF/6.3V

I

1 2

AC51 4.7 UF/10V X5R 10%Imx_c0603

1 2

AC50 4.7 UF/10V X5R 10%Imx_c0603

mx_c0805_ smallX5R 10%

AGND

I_F_LIN1_RC 28 I_F_LIN1_LC 28

AMP_LINE_ OUTR 44 AMP_LINE_ OUTL 4 4

From Scalar

To Amplifier

Trace width > 50 mils

32 31

1

18 19

34

Close to Pin33

33

SENSE_B

48

MIC2-R-C

47

MIC2-L-C

29 30

24

CBP

21

CBN

35

JDREF

40

LDO-CAP

41

VREF

38

VRP

50 51 52 53 54 55 56 57

Close to Pin38 MUST use POSCAP or PL cap. For DELL performance and DAC/ADC performance in Codec.

GND

AR6 5.1K 1%

I

AR25 10K 1 %

I

AC61 4.7 UF/25V X5R 10%Imx_c0805 AC60 4.7 UF/25V X5R 10%Imx_c0805

4.5V

12

+

I

AC15 100UF/6.3 V

SMD

12 12

1 2 1 2

1 2

AC7 2.2UF/6 .3V X5R 10 % mx_c0603

I

12

AC12 10UF/6.3V

X5R 10% mx_c0805_ small

2

I

12

AC13 10UF/6.3V

X5R 10% mx_c0805_ small

AGND

AGNDA GND

PEGATRON-BU5 RESTRICTED SECRET

Pegatron Corp.

Date: Sheet of

SLEEVE 45 RING2 45

MIC2-VREFO -L 45

HPOUT2_ R 45 HPOUT2_ L 45

HPOUT1_ JD 45 HPOUT2_ JD 45

MIC2-R 45

MIC2-L 45 LINE2-VREF O 45 MIC2-VREFO -R 45

I

12

AC14

0.1UF/16V

X7R 10%

Close to Pin35

Size Project Name

A3

12

I

AR7 20K

1%

AGNDAGND

From Global Headset

To Global Headset

To Rear Headphone

From Global Headset

From Rear Headphone

From Global Headset

To Global Headset

Title :

Engineer:

IMPLP-MS

1

ALC3661 CODEC

Stonko_Chen

43 83Thu rsday, June 27, 2013

Rev

A00

5

AUDIO AMPLIFIER

4

3

2

1

AVCC

Input

I

AC25

0.1UF/16V

X7R 10%

I

AR70

10.2K

1%

O.D.

I

AU2 TPA3110 D2PWPR

7

AVCC

8

AGND

9

GVDD

10

PLIMIT

3

LINP

4

LINN

11

RINN

12

RINP

1

SD#

2

FAULT#

5

GAIN0

6

GAIN1

PVCCL2 PVCCL1 PVCCR2 PVCCR1

PGND1 PGND2

GND

BSPL

OUTPL

OUTNL

BSNL

BSNR

OUTNR

OUTPR

BSPR

PBTL

28 27 16 15

19 24

29

26 25

23 22

21 20

18 17

SD#: For the best power-off pop performance, place the amplifier in the shutdown mode prior to removing the power supply voltage.

13

NC

14

   

12

GND G ND GND G ND GND GND G ND GND

GND

BDPL

AC40 0.22UF /25V

I

SPK_L_P

SPK_L_N BSNL

AC39 0.22UF /25V

I

BDNR

AC38 0.22UF /25V

I

SPK_R_N

SPK_R_P BSPR

AC37 0.22UF /25V

I

AGND

I

AC29 1000PF/5 0V

X7R 10%

Close pin 27, 28

1 2

12

I

AC30

0.1UF/25V

X5R 10%

12

I

AC62 22UF/25V

X5R 10% mx_c1206

X7R 10% mx_c0603

12

I

AC63 22UF/25V

X5R 10% mx_c1206

12

I

AC64 22UF/25V

X5R 10% mx_c1206

12

I

AC34 1000PF/5 0V

X7R 10%

Close pin 15, 16

120Ohm/1 00Mhz

AL40

I

AL39

I

AL38

I

AL37

I

21

mx_l1206_h51

21

120Ohm/1 00Mhz

mx_l1206_h51

120Ohm/1 00Mhz

21

mx_l1206_h51

21

120Ohm/1 00Mhz

mx_l1206_h51

12

I

AC44 1000PF/5 0V

X7R 10%

GND G ND GND G ND GND

12

I

AC35

0.1UF/25V

X5R 10%

12

SPK_DET ECT#23

I

AC43 1000PF/5 0V

X7R 10%

+19V

12

NI

+

AC36 47UF/25V

TAN/Lf_T= 2000hrs_85c/+/-10% c7343_h 169

SPEAKER

AMP_SPK _LP

AMP_SPK _LN

AMP_SPK _RN

AMP_SPK _RP

I

AC42 1000PF/5 0V

X7R 10%

12

I

P72 WTOB _CON_1X6P

1

SIDE1

5

3

2

4

SIDE2

I

AC41 1000PF/5 0V

X7R 10%

7

6

8

I

AGND

AR16 10

mx_r1206

1 2

GVDD

PLIMIT

12

I

AR22 10K

1%

AGND

AMP_LINE_ OUTL_C

AMP_LINE_ OUTR_C

I

AR11 1K

1 2

I

12

AC26 1UF/25V

X5R 10% mx_c0603

AGND AG ND

12

AGND

12

AGND

Output/7V

I

AC28 1UF/16V

X7R 10% mx_c0603

12

I

AC24

0.1UF/16V

X7R 10%

12

I

AR69

10.5K

1%

AGND AG ND

AMP_GAN 0 AMP_GAN 1

NI

AC65 1UF/16V

X7R 10% mx_c0603

12

+19V



D D

  

PLIMIT 5W/4Ohm

12

AGND

1 2

AUDIO_SHU TDOWN#43

AR23 = 34k

1 2

I

AR23 34K

I

AC27

1%

1UF/16V

X7R 10% mx_c0603

AMP_LINE_OUT=1.2 V

1.2*1/(2+1)=0.4 V

0.4*10=4V (P.S. 10=AMP Gain) P=V*V/R=4*4/4=4 Watt

I

AC66 1UF/16V

X7R 10% mx_c0603

AMP_LINE_ OUTL43

C C

AMP_LINE_ OUTR43

PCBEEP18

B B

1 2

I

AC67 1UF/16V

X7R 10% mx_c0603

1 2

12

NI

AR17 10K

1%

12

I

AR19 10K

1%

AGND AGND

+3P3V+ 3P3V

I

AR53 1K

1 2

1%

12

NI

AR18 10K

1%

12

I

AR20 10K

1%

I

AR63

16.2K

1 2

1%

I

AR64 15K

1 2

1%

AC22 0.1UF/1 6VIX7R 10%

AR65 30K 1%

I

AC23 0.1UF/1 6VIX7R 10%

AR66 31.6K 1%

I

AC54 100PF /50V NPO 5%

I

AR68 1KNI1%

GAIN0 AMP GAIN (dB) INPUT IMPEDANCE(k Ohm)GAIN1

00 20dB (10) 60

10 26dB (20) 30

01 32dB (40) 15

11 36dB (80) 9

PBTL:

 

  

A A

PEGATRON DT-MB RESTRICTED SECRET

SPEAKER & SIDE MIC1

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

IMPLP-MS

1

Stonko_Chen

44 83Thu rsday, June 27, 2013

Rev

A00

5

REAR LINE-OUT

HPOUT2_ JD43



D D

HPOUT2_ R43

HPOUT2_ L43

4

+3P3V

12

I

3

I

D

AQ18 2N7002

1

G

S

2

AGND

AR10 10I1%

AR52 10I1%

1 2

AR67 100K

3

AGND AGND

I

AD1 AZ2025-0 1H

1 2

I

AD2 AZ2025-0 1H

12

I

AC52 100PF/50 V

NPO 5%

AGND AGND

2

1



I

AJ2 PHONE_J ACK_6P

5 4

12

3 6 2 1

P_GND

10

P_GND

9

P_GND

8

P_GND

7

S4 SHORTPIN

12

I

AC53 100PF/50 V

NPO 5%

HPOUT2_ R_C

HPOUT2_ L_C

1 2

12

AGNDAGNDAGNDAGND

AGND

I

AD5 AZ2025-0 1H

I

AC56 100PF/50 V

NPO 5%



I

AJ1 PHONE_J ACK_6P

4 3

R_HPOUT _R R_HPOUT _L

12

AGND

2 1

5 6 7

MS

8 9

NP_NC

10

S5 SHORTPIN

GHS JACK 12X141608000 -->12X141940000

12

NI

AR42

C C

+3P3V

+3VA

12

I

AR62

12

NI

AR61 10K

100K

3

D

1

I

G

AQ16

S

2

2N7002

AGND

GLOBAL HEAD SET CONNECTOR

1 2

AR76 75 1%

MIC2-L43 MIC2-R43

B B

A A

LINE2-VREF O43

SLEEVE43 RING243 HPOUT1_ R43 HPOUT1_ L43

HPOUT1_ JD43

MIC2-VREFO -R43 MIC2-VREFO -L43

I

1 2

AR77 75 1%

I



1 2

AR45 2.2K 1%

I

1 2

AR46 2.2K 1%

I

AR12 3 3 OHMI1% AR13 3 3 OHMI1%

1 2

AR47 2.2K 1%

I

1 2

AR48 2.2K 1%

I

R1.04

12

NI

AR74 10K

AGND AG ND

NI

AR75 10K

I

AR71 1K

AZ_RST#18,43

1 2

30K

AGND AGND

3

D

I

AQ17

1

2N7002

G

S

2

AGND

AGND AGND AGND AGND

1 2

12

I

AC59 100PF/50 V

NPO 5%

I

AD3 AZ2025-0 1H

12

NI

AR38 30K

  

1 2

12

I

AC58 100PF/50 V

NPO 5%

I

AD4 AZ2025-0 1H

1 2

12

I

AC57 100PF/50 V

NPO 5%

I

AD6 AZ2025-0 1H

PEGATRON DT-MB RESTRICTED SECRET

REAR HP-OUT & GHS CONN.

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

5

4

3

2

Date: Sheet of

IMPLP-MS

Engineer:

1

Stonko_Chen

45 83Thu rsday, June 27, 2013

Rev

A00

5

D D

C C

4

3

2

1

B B

A A

PEGATRON DT-MB RESTRICTED SECRET

AUDIO MUTE

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

5

4

3

2

Date: Sheet of

IMPLP-MS

Engineer:

1

Stonko_Chen

46 83Thu rsday, June 27, 2013

Rev

A00

5

Avoid leakage in S5

1 2

SR117 0

I

S

D D

SMB_DAT A_RESUME21,33,34,3 9 SMB_DAT A_SIO_MAIN 36,54

D

3

2

NI

G

1

SQ14 2N7002

GATE_SQ 14 GATE_SQ 14

1 2

SR118 0

I

D

3

NI

SQ15 2N7002

+3P3V + 3P3V

S

2

G

1

12

NI

SR408 15K

4

12

NI

SR107

2.7K

NI

SR23

8.2K

NI

SR108

2.7K

SMB_DAT A_MAIN 15 ,16,50,51

SMB_CLK _MAIN 15 ,16,50,51SMB_CLK _RESUME21,33,34,3 9

+19V

12

3

1 2

SR418 0

NI

SMB_DAT A_SIO_RESUME21

D

3

NI

SQ17 2N7002

2

+3P3V + 3P3V

12

NI

SR420

2.7K

S

2

G

1

1 2

SR419 0

NI

D

3

NI

SQ18 2N7002

S

2

G

1

12

NI

SR423 15K

NI

SR422

8.2K

NI

SR421

2.7K

SMB_CLK _SIO_MAIN 36,54SMB_CLK _SIO_RESUME21

+19V

12

1

GND

C C

GND

SPI ROM (Quad I/O Supported)

I

F3Q1 2N7002

S

D

3

SPI_CS0#21

SPI_MISO21

SPI_IO221

B B

A A

SPI_MOSI21 SPI_CLK21 SPI_IO321

+5V

12

I

F3R4 1K

5

2

G

1

4

SPI_CS#_E 16

+3P3V

GND

+3P3V

12

I

F3R13 1K

3

PROTO

F3J1

12

GND2

10

9

8

7

6

5

4

3

2

1

11

GND1

FPC_CON _10P

X00 SPI Header

GND

12X171803000-->12X67D41AW00



I

U19 W25 Q64FVSSIQ

1

CS#

2

DO(IO1) WP#(IO2) GND

HOLD#(IO3)

3 4

NOTE:

Making use of WP* and HOLD* for Quad I/O support

VCC

CLK

DI(IO0)

8 7 6 5

12

GND

I

F3CB3

0.1UF/16V

X7R 10%

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

2

Date: Sheet of

+3P3V

12

GND

I

F3CB4 1UF/16V

X7R 10% mx_c0603

Title :

Engineer:

IMPLP-MS

1

SM BUS & SPI ROM

Stonko_Chen

47 83Thu rsday, June 27, 2013

Rev

A00

5

4

3

2

1

LPC DEBUG SMD

+3P3V

LAD021,36

LFRAME#21,36

CK_33M_ DEBUG20

SRTCRST # 18

RTCRST# 18

CLPW D#

LAD121,36

LAD221,36

LAD321,36

Q82 2N7002

S

D

GND

12

PROTO

F2C1

0.1UF/16V

X7R 10%

GND

3

USB_CAR D_DET# 23,39

1

G

2

R1.04

D D

I

BR3 20K

1%

I

BATT1

C C

3V/220mA h

LITHIUM BATT

CR2032

I

XBT1 WTOB _CON_2P

SIDE1

2 1

SIDE2

3 2 1 4

GND

I

BR1 1K

1%

1 2

+3VA

R303_D8BAT

1

2

I

BQ1 BAT54CW

+BATT

3

12

I

BC1 1UF/16V

X7R 10% mx_c0603

1 2

I

BR2 20K

1%

1 2

12

I

BC2 1UF/16V

X7R 10% mx_c0603

GNDGNDGND

12

I

BC3 1UF/16V

X7R 10% mx_c0603

CLR CMOS CIRCUIT

1-3

Default

3-4

GND

PROTO

P13 FPC_CON _12P

12

11

SIDE2

10

9

8

7

6

5

4

3

2

SIDE1

1

NI

JE69:34 MINI_JUMPER

14

13

GND

PLACE NEAR DIMM

NI

E69 HEADER_ 2x2P

1

2

3 4

GND

E50 X01:12X061855000-->1206-01R2000 1206-01R1000 :small footprint hd_2x2p_50_pinrex 1206-01R2000 : Big foorprint hd_2x2p_50_jv

GND

CLPW D# 18,19

CLR PASSWORD CIRCUIT

PASSWORDCMOS RTC

2-4CLEAR

CLEAR

Default

3-4

B B

+3P3V + 3P3V

I

12

CPUFAN_ TACH36

CPUFAN_ PWM36

A A

5

I

O2R40

4.7K

I

O2R39

4.7K

O2R8

1.5K

1 2

NI

O2D4 BAW5 6WPT

3

4

1

2

1 2

I

O2R41 150

mx_r0805

CPUFAN_ TACH_C CPUFAN_ PWM_C

3

+5V

3

I

O2D5 BAT54CW

1

2

+5V

GND

12

I

O2CB8 10UF/10V

mx_c0805

GND

I

P70 WTOB _CON_1X4P

GND2

1

2

3

4

GND1

6

5

FAN CONNECTOR

GND

PEGATRON DT-MB RESTRICTED SECRET

RTC & LPC DEBUG & FAN

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

2

Date: Sheet of

Engineer:

IMPLP-MS

1

Stonko_Chen

48 83Thu rsday, June 27, 2013

Rev

A00

5

D D

VGA_RED22

12

NI

VR9 150

1%

VGA_GRE EN22

12

NI

VR8 150

C C

VGA_BLU E22

1%

GND G ND G ND

12

NI

VR10 150

1%

12

GNDGN D

12

NI

VC9

1.2PF/50V

NI

VC7

1.2PF/50V

NI

VC8

1.2PF/50V

NI

VL15

0.082UH/3 00mA

mx_l0603

21

NI

VL16

0.082UH/3 00mA

mx_l0603

21

NI

VL14

0.082UH/3 00mA

mx_l0603

21

12

GND

12

4

NI

VC15

3.3PF/50V

NPO 0.25P F

NI

VC13

3.3PF/50V

NPO 0.25P F

NI

VC10

3.3PF/50V

NPO 0.25P F

VGA_RED _LC

VGA_GRE EN_LC

VGA_BLU E_LC

3

X00 VGA Connector 12X341490000-->12X659528N00

+5V

NI

P69 WtoB_ CON_2X8P

13

15

16

14

1

5

4

8

9

SIDE1 SIDE2

12

11

17 18 2

2

3

6

7

10

VGA_DDC A_CLK_R

VGA_DDC A_DATA_R

GND

2

1

GNDGND

VGA_HSYNC22

B B

A A

VGA_VSYNC22

VR14 2.2K

NI

VR15 2.2K

NI

VGA_DDC A_DATA22

VGA_DDC A_CLK22

5

GND

+5V

+3P3V+3P 3V

12 12

G

2

S

4

1

G

3

2

S

1

3

D

NI

VQ5 2N7002

D

NI

VQ4 2N7002

VGA_DDC A_DATA_Q

VGA_DDC A_CLK_Q

+5V

12

NI

VR18

2.2K

NI

VR19

2.2K

3

NI

VR11 100

1 2

NI

VR12 100

1 2

PEGATRON DT-MB RESTRICTED SECRET

INTEGRATED VGA PORT

1

INTEGRATED VGA PORT

Stonko_Chen

49 83Thu rsday, June 27, 2013

Rev

A00

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

2

Date: Sheet of

IMPLP-MS

Engineer:

5

D D

4

3

2

1

INTEL CPU XDP DEBUG PORT

NI

XDP1

+1V_CPU IOOUT

12

NI

HCB20

0.1UF/16V

X7R 10%

GND

C C

B B

CPU_CFG [0..15]13

CPU_CFG 0 CPU_CFG 1 CPU_CFG 2 CPU_CFG 3

CPU_CFG 4 CPU_CFG 5 CPU_CFG 6 CPU_CFG 7

CPU_CFG 8 CPU_CFG 9 CPU_CFG 10 CPU_CFG 11

CPU_CFG 12 CPU_CFG 13 CPU_CFG 14 CPU_CFG 15

CK_100M _CPUXDP20 CK_100M _CPUXDP#20

SMB_DAT A_MAIN15,16,47,5 1 SMB_CLK _MAIN15,16,47,5 1

H_PREQ#9 H_PRDY#9

HR63 1K

NI

XDP_BPM 09 XDP_BPM 19

OBSFN_C 013 OBSFN_C 113

OBSFN_D 013 OBSFN_D 113

12

BtoB_CON _60P

43

VCC_OBS_AB

44

VCC_OBS_CD

40

ITPCLK/HOOK4

42

ITPCLK#/HOOK5

51

SDA

53

SCL

3

OBSFN_A0

5

OBSFN_A1

9

OBSDATA_A0

11

OBSDATA_A1

15

OBSDATA_A2

17

OBSDATA_A3

21

OBSFN_B0

23

OBSFN_B1

27

OBSDATA_B0

29

OBSDATA_B1

33

OBSDATA_B2

35

OBSDATA_B3

4

OBSFN_C0

6

OBSFN_C1

10

OBSDATA_C0

12

OBSDATA_C1

16

OBSDATA_C2

18

OBSDATA_C3

22

OBSFN_D0

24

OBSFN_D1

28

OBSDATA_D0

30

OBSDATA_D1

34

OBSDATA_D2

36

OBSDATA_D3

TCK1 TCK0

TDO

TRSTn

TDI

TMS

HOOK0

HOOK1 HOOK2 HOOK3

HOOK6/RESET#

HOOK7/DBR#

GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8

GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18

NP_NC1 NP_NC2

55 57 52 54 56 58

39

CPUXDP_ HOOK0

41

CPUXDP_ HOOK1

45 47

CPUXDP_ HOOK3

46

PLTRST_ CPU#_HOOK6

48

1 2 7 8 13 14 19 20 25 26 31 32 37 38 49 50 59 60 61 62

12

NI

HC31 470PF/50 V

GND

12

NI

HR81 1K

GND

12

NI

HC30

0.1UF/16V

X7R 10%

GND

CPUXDP_ PRESENT

TCK 9 TDO 9 TRST# 9 TDI 9 TMS 9

NOTE:

Place at 932,3881

NOTE:

TBD. PDG and DPDG is 1KΩ Follow PDG 0.9 is 1KΩ

HR93 0

NI

HR94 0

NI

HR95 1K

NI

12

NI

GND

HC32 470PF/50 V

NOTE:

Place at 323,7346

NI

HR123 1K

12

NI

HR62 1K

12

1 2

12

CPU_CFG 3 13

NOTE:

Place at 3714, 6223

12

NI

HC88 470PF/50 V

X7R 10%

GND

PCH_PW RBTN# 51 XDP_PW R_DEBUG 12 VRM_PW RGD 19,76 PLTRST_ CPU# 9,23 SYS_RESET # 9 ,19,51

H_CPUPW RGD 9,2 3

GND

A A

PEGATRON DT-MB RESTRICTED SECRET

CPU XDP DEBUG CONN.

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

5

4

3

2

Date: Sheet of

IMPLP-MS

Engineer:

1

Stonko_Chen

50 83Thu rsday, June 27, 2013

Rev

A00

5

4

3

2

1

NOTE:

Place strap resistors of TDO near to XDP connector,

INTEL PCH XDP DEBUG PORT

D D

+3P3VSB

+1P05V_ PCH

C C

12

NI

SR203 0

NOTE:

NI

SR350 0

1 2

12

NI

SCB110

0.1UF/16V

X7R 10%

GND

PCHXDP_ ITPCLK/HOOK4

PCHXDP_ VCC_OBS

OC0#2 4,40 OC1#2 4,40 OC2#2 4,39 OC3#2 4,39

OC4#2 4,41 OC5#2 4,41 OC6#24 OC7#24

Connecting ITPCLK/HOOK4 is optional; can be left floated

SMB_DAT A_MAIN15,16,47,5 0 SMB_CLK _MAIN15,16,47,5 0

BT_DISABL E#23,33

GPUPW _EN22 ,71,72 VOLUME_ UP#18,28 BL_UP#18,28 Panel_SEL_12 3,28,30

B B

Panel_SEL_22 3,28,30

HALF_US B_DET#23,33 FULLCAR D_SEL2 3,34 OBSDATA _D220 SCALAR_ MODE#20,28,43

NI

XDP2 BtoB_CON _60P

43

VCC_OBS_AB

44

VCC_OBS_CD

3

OBSFN_A0

5

OBSFN_A1

9

OBSDATA_A0

11

OBSDATA_A1

15

OBSDATA_A2

17

OBSDATA_A3

21

OBSFN_B0

23

OBSFN_B1

27

OBSDATA_B0

29

OBSDATA_B1

33

OBSDATA_B2

35

OBSDATA_B3

40

ITPCLK/HOOK4

42

ITPCLK#/HOOK5

51

SDA

53

SCL

4

OBSFN_C0

6

OBSFN_C1

10

OBSDATA_C0

12

OBSDATA_C1

16

OBSDATA_C2

18

OBSDATA_C3

22

OBSFN_D0

24

OBSFN_D1

28

OBSDATA_D0

30

OBSDATA_D1

34

OBSDATA_D2

36

OBSDATA_D3

TCK1 TCK0

TDO

TRSTn

TMS

HOOK0

HOOK1 HOOK2 HOOK3

HOOK6/RESET#

HOOK7/DBR#

GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8

GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18

NP_NC1 NP_NC2

55 57 52 54 56

TDI

58

39

41 45 47 46 48

1 2 7 8 13 14 19 20 25 26 31 32 37 38 49 50 59 60 61 62

PCH_JTA G_RST_R

PCHXDP_ HOOK0_PWR GD

PCHXDP_ HOOK1

PCHXDP_ HOOK6/RESET#

PCHXDP_ GND18

SR363 0

NI

+3P3VSB

12

NI

SR360 1K

12

NI

SR361 0

GND

1 2

12

NI

SR368 0

12

NI

SR362 1K

12

NI

SR365 0

SYS_RESET # 9 ,19,50

12

NI

SC140

0.1UF/16V

X7R 10%

GND GND

and TDI and TMS near to CPU.

+3P3VSB

12

I

SR351 210

12

I

SR353

SR352

51

100

GND

GND GND GND

RSMRST# 19,36,51

PCH_PW RBTN# 50

NI NI NI

12

SR390 0 SR392 1K SR389 0

I

SR354 210

I

SR355 100

I

SR356 210

12

I

SR357 100

12 12 12

12

NI

SC141 1UF/16V

X7R 10% mx_c0603

PCH_JTA G_TCK 18 PCH_JTA G_TDO 18 PCH_JTA G_RST 18 PCH_JTA G_TDI 18 PCH_JTA G_TMS 18

PWRB TN# 28,30 ,36

RSMRST# 19,36,51

PCH_DPW ROK 19,36

GND

A A

5

4

3

GND

PEGATRON DT-MB RESTRICTED SECRET

PCH XDP DEBUG CONN.

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

2

Date: Sheet of

IMPLP-MS

Engineer:

1

Stonko_Chen

51 83Thu rsday, June 27, 2013

Rev

A00

5

4

3

I

PCB1 PCB_BOA RD

2

I

LABEL2 PCB_LAB EL

1

IMPLP-MS

I

D D

AR78

NI

1 2

H4 C394D23 6

0

I

H15 C394D21 7

I

H5 C339D21 7

I

H6 C339D21 7

I

H7 C339D21 7

I

H14 C339D21 7

I

H13 C339D21 7

PCB

Proprietary

BIOS

LABEL

SGND AGN D

I

H24 DO228X1 50N

C C

1

SGND G ND GND G ND

I

H11 C394D39 4N

1

I

H12 C394D39 4N

1

NTPH

B B

+3P3VSB

1

I

H8 C315D18 9

1

GND

1

I

H9 CR339X3 15D217

1

GND G ND

1

I

H10 CR339X3 15D217

1

GND G NDGND

1

IMPLP-MS R0.1 BOM: 69M ==> 08M1-1BL1200 (PIOTEK) ==> 08M1-1BL1000 (YUANMAO) ==> 08M1-1BL1100 (HANNSTAR)

I

LABEL1 PCB_LAB EL

PPID LABEL

IMPLP-MS R1.00 BOM: 69M ==> 08M1-1BL0200 (PIOTEK) ==> 08M1-1BL0000 (YUANMAO) ==> 08M1-1BL0100 (HANNSTAR)

I

LABEL3 PCB_LAB EL

BLANK SN LABEL

12

NI

R5 300

mx_r0603

CR2_R

12

NI

+

CR2

GND

BLUE

PEGATRON DT-MB RESTRICTED SECRET

LED & PCB & Label & Screw

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

4

3

2

Date: Sheet of

IMPLP-MS

Engineer:

1

Stonko_Chen

52 83Thu rsday, June 27, 2013

Rev

A00

A A

5

Place AC Cap. close to CPU side.

D D

4

I_GPU

N1A SUN-XT-S3

3

2

1

1 2

N1C1 0.22UF/10 V

I_GPU

SU2 NC7SZ08 P5X

A

1

B

2

3

GND

I_GPU

N1C2 0.22UF/10 V

I_GPU

N1C3 0.22UF/10 V

I_GPU

N1C4 0.22UF/10 V

I_GPU

N1C5 0.22UF/10 V

I_GPU

N1C6 0.22UF/10 V

I_GPU

N1C7 0.22UF/10 V

I_GPU

N1C8 0.22UF/10 V

I_GPU

N1C9 0.22UF/10 V

I_GPU

N1C10 0.22UF/1 0V

I_GPU

N1C11 0.22UF/1 0V

I_GPU

N1C12 0.22UF/1 0V

I_GPU

N1C13 0.22UF/1 0V

I_GPU

N1C14 0.22UF/1 0V

I_GPU

N1C15 0.22UF/1 0V

I_GPU

N1C16 0.22UF/1 0V

I_GPU

+3P3V

5

VCC

4

Y

NI

N1R106 0

1 2

1 2 1 2

G_PCIE_RS T#_R

EXP_TXP 08 EXP_TXN 08

EXP_TXP 18 EXP_TXN 18

EXP_TXP 28 EXP_TXN 28

EXP_TXP 38 EXP_TXN 38

EXP_TXP 48 EXP_TXN 48

EXP_TXP 58 EXP_TXN 58

C C

B B

PCIE_RST#33,34,35,36,3 7

GPU_PCIE_ RST#22

A A

EXP_TXP 68 EXP_TXN 68

EXP_TXP 78 EXP_TXN 78

GND

5

4

X7R 10% X7R 10%

CK_100M _PE820 CK_100M _PE8#20

12

GND

PCIE_TXP0 PCIE_TXN0

PCIE_TXP1 PCIE_TXN1

PCIE_TXP2 PCIE_TXN2

PCIE_TXP3 PCIE_TXN3

PCIE_TXP4 PCIE_TXN4

PCIE_TXP5 PCIE_TXN5

PCIE_TXP6 PCIE_TXN6

PCIE_TXP7 PCIE_TXN7

NI

N1C33

0.1UF/16V

X7R 10%

12

GND

TEST_PG

I_GPU

N1R4 1K

1%

AF30

AE31

AE29 AD28

AD30 AC31

AC29 AB28

AB30 AA31

AA29

W31

W29

AK30 AK32

AL27

Y28

Y30

V28

V30 U31

U29 T28

T30 R31

R29 P28

P30 N31

N29 M28

M30

K30

N10

L31

L29

PCIE_RX0P PCIE_RX0N

PCIE_RX1P PCIE_RX1N

PCIE_RX2P PCIE_RX2N

PCIE_RX3P PCIE_RX3N

PCIE_RX4P PCIE_RX4N

PCIE_RX5P PCIE_RX5N

PCIE_RX6P PCIE_RX6N

PCIE_RX7P PCIE_RX7N

NC95 NC91

NC89 NC83

PCI EXPRESS INTERFACE

NC84 NC78

NC77 NC75

NC76 NC70

NC69 NC66

NC67 NC64

NC63 NC62

CLOCK

PCIE_REFCLKP PCIE_REFCLKN

PERSTB

TEST_PG

3

PCIE_TX0P PCIE_TX0N

PCIE_TX1P PCIE_TX1N

PCIE_TX2P PCIE_TX2N

PCIE_TX3P PCIE_TX3N

PCIE_TX4P PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

CALIBRATION

PCIE_CALR_TX

PCIE_CALR_RX

NC100

NC99

NC94 NC88

NC87 NC86

NC81 NC82

NC80 NC79

NC74 NC73

NC72 NC71

NC65 NC68

AH30 AG31

AG29 AF28

AF27 AF26

AD27 AD26

AC25 AB25

Y23 Y24

AB27 AB26

Y27 Y26

W24 W23

V27 U26

U24 U23

T26 T27

T24 T23

P27 P26

P24 P23

M27 N26

Y22

AA22

+0P95V_ GPU +0P 95V_GPU

PCIE_CALR _TX

PCIE_CALR _RX

12

I_GPU

N1R1

1.69K

1%

12

I_GPU

N1R2 1K

1%

EXP_RXP 0 8 EXP_RXN 0 8

EXP_RXP 1 8 EXP_RXN 1 8

EXP_RXP 2 8 EXP_RXN 2 8

EXP_RXP 3 8 EXP_RXN 3 8

EXP_RXP 4 8 EXP_RXN 4 8

EXP_RXP 5 8 EXP_RXN 5 8

EXP_RXP 6 8 EXP_RXN 6 8

EXP_RXP 7 8 EXP_RXN 7 8

2

PEGATRON DT-MB RESTRICTED SECRET

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

IMPLP-MS

Engineer:

1

SUN-XT_PCIE

Stonko_Chen

53 83Thu rsday, June 27, 2013

Rev

A00

5

Debug bus output data

D D

Add test points on SMB Bus and SDA/SCL for debug Access to SMB Bus ans SDA/SCL is mandatory on all designs

DisplayPort Power NC for Mars-S3

SMBUS is use for ASIC Temperature read if you doesn’t access the SMBUS for ASIC Temperature read, it can skip it by pull-up 3.3V through 45.3K-ohm only.

1 2

N1R48 0

SMB_DAT A_SIO_MAIN36,47

SMB_CLK _SIO_MAIN36,47

C C

B B

PIN STRAPS FOR THAMES/SEYMOUR. Mars does not support pin straps except for HSYNC and VSYNC. GPIO0/GPIO1/GPIO2/GPIO11/GPIO12/GPIO13/GPIO21 don't support pin straps for Mars and add test points to double check.

I_GPU

N1R47 0

I_GPU

1 2

No use: GPIO7/GPIO14/GPIO17/GPIO18/GPIO19

Use GPIO5/GPIO6/GPIO15/GPIO20/GPIO29/GPIO30 to VDDC VID controller for AMD recommendation Only use 5 VIDs (GPIO5 default NI).

Use GPIO11/GPIO12 to VDDCI controller for AMD recommendation Because the V-BIOS code is already verified (0.8/0.85/0.9/0.95V)

+1P8V_M XM

A A

5

I_GPU

NL1 120Ohm/1 00Mhz

+1P8V_MXM_TSVDD

21

+3P3V_GPU +3P3V_GPU

12

I_GPU

N1R6

4.7K

12

NI

N1C189 10PF/50V

NPO 5%

GPIO572

CTF72

Use external SIO /EC to access by D+/D- signals for ASIC temperature monitoring .

GND

12

I_GPU

N1C67 1UF/6.3V

X5R 10%

GND

12

NI

N1R61 100K

12

I_GPU

N1R39 10K

GNDGND

12

NI

N1C188 10PF/50V

NPO 5%

G_ROMSO5 5

G_ROMSI55 G_ROMSC K5 5 G_ROMCS #55

I_GPU

N1C35 1UF/6.3V

X5R 10%

12

GPIO672

GPIO1572 GPIO1671

GPIO2072

GPIO2972 GPIO3072

I_GPU

N1R5

4.7K

12

4

GPIO071

NOBOM

12

I_GPU

N1R108 10K

GND

H: MLPS Disable L: MLPS Enable

I_GPU

N1C34 10UF/6.3V

X5R 10% mx_c0805_ small

D1+36 D1+_S36

4

I2C

3

DPA

DPB

DPC

NC_AVSSN3

NC_AVSSN2

DAC1

NC_AVSSN1

NC_HSYNC NC_VSYNC

NC_RSET

NC_AVDD

NC_AVSSQ

NC_VDD1DI NC_VSS1DI

NC_DBG_VREFG

FutureASIC/SEYMOUR/PARK

PLL/CLOCK

DDC/AUX

CEC_1 NC_SVI2_2 NC_SVI2_3 NC_SVI2_1

NC_GENLK_CLK

NC_GENLK_VSYNC

NC_SWAPLOCKA NC_SWAPLOCKB

TESTEN

JTAG_TRSTB

JTAG_TDI

JTAG_TMS

JTAG_TDO

JTAG_TCK

XTALIN

XTALOUT

XO_IN2

NC_DDC1CLK

NC_DDC1DATA

NC_AUX1P NC_AUX1N

NC_DDC2CLK

NC_DDC2DATA

NC_AUX2P NC_AUX2N

NC_DDCVGACLK

NC_DDCVGADATA

3

NC25 NC28 NC37 NC38 NC44 NC43 NC51 NC50

NC52 NC56 NC53 NC57 NC48 NC46 NC54 NC55

NC96 NC92

NC101

NC93 NC105 NC102

NC2

NC104

NC61

NC_R

NC_G

NC_B

PS_0

PS_1

PS_2

PS_3

TS_A

XO_IN

NC11

NC6 NC17 NC10

AF2 AF4 AG3 AG5 AH3 AH1 AK3 AK1

AK5 AM3 AK6 AM5 AJ7 AH6 AK8 AL7

V4 U5 W3 V2 Y4 W5 AA3 Y2 J8

AM26 AK26 AL25 AJ25 AH24 AG25

AH26 AJ27

AD22

AG24 AE22

AE23 AD23

AC16

AM12 AK12 AL11 AJ11 AL13 AJ13

AG13 AH12

AC19 AD19 AE17 AE20 AE19

K7

L6 L5 L1 K4 L3

AM28 AK28

AC22 AB22

AE6 AE5 AD2 AD4

AC11 AC13 AD13 AD11

AD20 AC20 AE16 AD16 AC1 AC3

NI NI NI NI NI

TESTEN

XTALIN

DisplayPort interface For Thames/Seymour only Mars doesn't have these ports

Place MLPS circuit components as close to the ASIC PS_x balls as possible

PS_0 55 PS_1 55 PS_2 55 PS_3 55

1 2

N1R10 10K

1 2

N1R11 10K

1 2

N1R12 10K

1 2

N1R13 10K

1 2

N1R14 10K

I_GPU

N1R8 0

1 2

R_XTALO UTXTAOUT

I_GPU

N1B SUN-XT-S3

N9

DBG_DATA16

L9

DBG_DATA15

AE9

DBG_DATA14

Y11

DBG_DATA13

AE8

DBG_DATA12

AD9

DBG_DATA11

AC10

DBG_DATA10

AD7

DBG_DATA9

AC8

DBG_DATA8

AC7

DBG_DATA7

AB9

DBG_DATA6

AB8

DBG_DATA5

AB7

DBG_DATA4

AB4

DBG_DATA3

AB2

DBG_DATA2

Y8

DBG_DATA1

Y7

DBG_DATA0

W6

NC103

V6

NC97

AC6

NC9

AC5

NC8

AA5

NC3

AA6

NC4

U1

NC85

W1

NC98

U3

NC90

Y6

NC106

AA1

NC1

12

NI

N1R7 10K

GPIO28

I_GPU

N1R3 10K

R1

SCL

R3

SDA

GENERAL PURPOSE I/O

U6

GPIO_0

U10

NC_GPIO_1

T10

NC_GPIO_2

U8

SMBDATA

U7

SMBCLK

T9

GPIO_5_AC_BATT

T8

GPIO_6

T7

NC_GPIO_7

N6

NC_GPIO_11

N5

NC_GPIO_12

N3

NC_GPIO_13

Y9

NC_GPIO_14

N1

GPIO_15_PWRCNTL_0

M4

GPIO_16

R6

GPIO_17_THERMAL_INT

W10

NC_GPIO_18

M2

GPIO_19_CTF

P8

GPIO_20_PWRCNTL_1

P7

GPIO_21

AK10

GPIO_29

AM10

GPIO_30

N7

CLKREQB

P10

GPIO_8_ROMSO

P4

GPIO_9_ROMSI

P2

GPIO_10_ROMSCK

N8

GPIO_22_ROMCSB

AB16

PX_EN

AF24

NC26

AB13

NC_GENERICA

W8

NC_GENERICB

W9

NC_GENERICC

W7

NC_GENERICD

AD10

NC_GENERICE_HPD4

AJ9

NC49

AL9

DBG_CNTL0

AC14

NC_HPD1

R5

GPIO28_FDO

AD17

TSVDD

AC17

TSVSS

T4

DPLUS

T2

DMINUS

SCL SDA

SMBDATA SMBCLK

1

T65

1

GPIO21

T67

1

CLEREQ#

T68

1

PX_EN

T59

+3P3V_GPU

GND

DVO

SEYMOUR/FutureASIC

THERMAL

12

GND

+3P3V_GPU

I_GPU

N1C37 10PF/50V

NPO 5%

2

I_GPU

N1R9 1M

1 2

I_GPU

Y20 27MHZ

1 3

2

4

GNDGND

2

1

+3P3V_GPU

12

NI

N1R16

5.11K

12

I_GPU

N1R15

H: Reserve Provision

1K

L: Test Enable (Default)

GND

12

I_GPU

N1C38 10PF/50V

NPO 5%

GND

PEGATRON DT-MB RESTRICTED SECRET

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

IMPLP-MS

Engineer:

1

SUN-XT_IO

Stonko_Chen

54 83Thu rsday, June 27, 2013

Rev

A00

5

4

3

1MB (128Kbytes) is Hybrid V-BIOS which is requested to support SYS_BIOS at UEFI code and Legacy code for Win7/Win8 in parallel on same system . If your V-BIOS would like to implement it to SYS_BIOS together and then remove the EEPROM component in support. These Strap pin will be configured to Memory aperture size for VRAM allocation.

2

NOTE: Designs that do not inculde an EEPROM. must still provide access to the ROM interface signals for debug purposes.

1

D D

I_GPU_FOR_PROTO

1 2

N1R37 33

G_ROMCS #54

G_ROMSO5 4

C C

PROTO

N1R52 33

I_GPU_FOR_PROTO

1 2

+3P3V_GPU

12

GND

N1R53 0

NI

N1R54 0

12

PROTO

N1R36 10K

R_G_ROM CS# R_G_ROM SO R_G_W P#

12

NI

N1R107 10K

GND

1Mbit SPI ROM

I_GPU_FOR_PROTO

N1U1

1

CE#

VCC

2

SO

HOLD#

3

WP#

SCK

4

GND

SIO

GND

PM25LD0 10C-SCE

PS_0: 1 / 1 / 1 / 0 / 1

8 7 6 5

+3P3V_GPU+3 P3V_GPU

R_G_ROM SCK R_G_ROM SI

I_GPU_FOR_PROTO

12

N1C159

0.1UF/16V

X7R 10%

GND

1 2

N1R57 33

1 2

N1R58 33

PS_2: 1 / 1 / 1 / 1 / 1

G_ROMSC K 54 G_ROMSI 54

MLPS Straps

PS_054

+1P8V_M XM_VDDCT

12

I_GPU

N1R59

8.45K

1%

12

I_GPU

N1R60 2K

1%

12

GND

NI

N1C161

0.01UF/25 V

X7R 10%

Multi Level Pin Strap (MLPS)

1. Connect GPIO_28 to 10K pulldown to enable MLPS

2. PS_[3:0] cannot be tied directly to 1.8 V or ground on the PCB,or the ASIC will be damaged.

3. Never connect any of PS_[3:0] directly to power or ground. If any PS_x is not used, leave “no connect”

4. Trace capacitance should be less than 100pF. Resistors should be of +/-1% tolerance

5. Place MLPS circuit components as close to the ASIC PS_x balls as possible

External resistor dividers and capacitors are properly populated according to the following tables.

B B

PS_254

+1P8V_M XM_VDDCT

12

NI

N1R71

4.75K

1%

12

I_GPU

N1R70

4.75K

1%

12

GND

NI

N1C165

0.01UF/25 V

X7R 10%

PS_1: 1 / 1 / 0 / 0 / 1

+1P8V_M XM_VDDCT

12

I_GPU

N1R68

8.45K

1%

PS_154

A A

5

4

12

I_GPU

N1R69 2K

1%

12

GND

NI

N1C163

0.01UF/25 V

X7R 10%

3

PS_3: 1 / 1 / 0 / 1 / 0

+1P8V_M XM_VDDCT

PS_354

12

NI

N1R42

4.53K

1%

I_GPU

N1R43

4.75K

1%

12

GND

NI

N1C167

0.01UF/25 V

X7R 10%

2

PS_3

Auto detection

SAMSUNG

HYNIX

BIT3 BIT2 BIT1

0 0

0

1

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

IMPLP-MS

0

1

11

SUN-XT_VROM&STRAP

1

SUN-XT_VROM&STRAP

Stonko_Chen

55 83Thu rsday, June 27, 2013

Title :

Engineer:

Rev

A00

5

4

3

2

1

MAA0_9 NC For GDDR5 MAA0_9 Connect For DDR3 MAA1_9 NC For GDDR5 & DDR3

K27

H30 H32 G29

C30

A28 C28 E27 G26 D26

A25 C25 E25 D24 E23

D22

E21 D20

A19 D18

A17 C17 E17 D16

A15 D14

A13 C13 E11 A11 C11

K26

K25

J29

F28 F32 F30

F27

F25

F23

F21

F19

F17

F15

F13

F11

A9 C9 F9 D8 E7 A7 C7 F7 A5 E5 C3

E1 G7 G6 G1 G3

J6 J1 J3 J5

J26

J25

K8

L7

I_GPU

N1C SUN-XT-S3

DQA0_0 DQA0_1 DQA0_2 DQA0_3 DQA0_4 DQA0_5 DQA0_6 DQA0_7 DQA0_8 DQA0_9 DQA0_10 DQA0_11 DQA0_12 DQA0_13 DQA0_14 DQA0_15 DQA0_16 DQA0_17 DQA0_18 DQA0_19 DQA0_20 DQA0_21 DQA0_22 DQA0_23 DQA0_24 DQA0_25 DQA0_26 DQA0_27 DQA0_28 DQA0_29 DQA0_30 DQA0_31 DQA1_0 DQA1_1 DQA1_2 DQA1_3 DQA1_4 DQA1_5 DQA1_6 DQA1_7 DQA1_8 DQA1_9 DQA1_10 DQA1_11 DQA1_12 DQA1_13 DQA1_14 DQA1_15 DQA1_16 DQA1_17 DQA1_18 DQA1_19 DQA1_20 DQA1_21 DQA1_22 DQA1_23 DQA1_24 DQA1_25 DQA1_26 DQA1_27 DQA1_28 DQA1_29 DQA1_30 DQA1_31

MVREFDA MVREFSA

NC60 MEM_CALRP0

CLKTESTA CLKTESTB

GM_CHA_ MAA0_[0..8] 60 ,61

GDDR5/DDR3GDDR5/DDR3

WCKA0B_0

WCKA0B_1

WCKA1B_0

WCKA1B_1

MEMORY INTERFACE

MAA0_0 MAA0_1 MAA0_2 MAA0_3 MAA0_4 MAA0_5 MAA0_6 MAA0_7 MAA0_8 MAA0_9

MAA1_0 MAA1_1 MAA1_2 MAA1_3 MAA1_4 MAA1_5 MAA1_6 MAA1_7 MAA1_8 MAA1_9

WCKA0_0

WCKA0_1

WCKA1_0

WCKA1_1

EDCA0_0 EDCA0_1 EDCA0_2 EDCA0_3 EDCA1_0 EDCA1_1 EDCA1_2 EDCA1_3

DDBIA0_0 DDBIA0_1 DDBIA0_2 DDBIA0_3 DDBIA1_0 DDBIA1_1 DDBIA1_2 DDBIA1_3

ADBIA0 ADBIA1

CLKA0

CLKA0B

CLKA1

CLKA1B

RASA0B RASA1B

CASA0B CASA1B

CSA0B_0 CSA0B_1

CSA1B_0 CSA1B_1

CKEA0 CKEA1

WEA0B WEA1B

K17 J20 H23 G23 G24 H24 J19 K19 G20 L17

J14 K14 J11 J13 H11 G11 J16 L15 G14 L16

E32 E30 A21 C21 E13 D12 E3 F4

H28 C27 A23 E19 E15 D10 D6 G5

H27 A27 C23 C19 C15 E9 C5 H4

L18 K16

H26 H25

G9 H9

G22 G17

G19 G16

H22 J22

G13 K13

K20 J17

G25 H10

GM_CHA_ MAA0_0 GM_CHA_ MAA0_1 GM_CHA_ MAA0_2 GM_CHA_ MAA0_3 GM_CHA_ MAA0_4 GM_CHA_ MAA0_5 GM_CHA_ MAA0_6 GM_CHA_ MAA0_7 GM_CHA_ MAA0_8

GM_CHA_ MAA1_0 GM_CHA_ MAA1_1 GM_CHA_ MAA1_2 GM_CHA_ MAA1_3 GM_CHA_ MAA1_4 GM_CHA_ MAA1_5 GM_CHA_ MAA1_6 GM_CHA_ MAA1_7 GM_CHA_ MAA1_8

WCKA 0_0 60,61 WCKA 0#_0 60,6 1 WCKA 0_1 60,61 WCKA 0#_1 60,6 1 WCKA 1_0 62,63 WCKA 1#_0 62,6 3 WCKA 1_1 62,63 WCKA 1#_1 62,6 3

EDCA0_0 60 EDCA0_1 61 EDCA0_2 60 EDCA0_3 61 EDCA1_0 62 EDCA1_1 63 EDCA1_2 62 EDCA1_3 63

DDBIA0_0 60 DDBIA0_1 61 DDBIA0_2 60 DDBIA0_3 61 DDBIA1_0 62 DDBIA1_1 63 DDBIA1_2 62 DDBIA1_3 63

ADBIA0# 60,61 ADBIA1# 62,63

CLKA0 60,61 CLKA0# 60,61

CLKA1 62,63 CLKA1# 62,63

RASA0# 60,61 RASA1# 62,63

CASA0# 60,61 CASA1# 62,63

CSA0#_0 60,61

CSA1#_0 62,63

CKEA0 60,61 CKEA1 62,63

WEA0 # 60 ,61 WEA1 # 62 ,63

GM_CHA_ MAA1_[0..8] 62 ,63

GDDR5 's Differential CLK signal doesn't require Clock termination using CAP.

Place all these componets very close to GPU (within 25mm) and keep all components close to each other ** This basic topology should be used for DRAM_RAT for DDR3/GDDR5

These Capacitors and Resistor values arre an example only The series R and || cap values will depend on the DRAM loads and will have to be calculated for differrent Memory, DRAM loads and board to pass Reset Signal Spec

5mm (max) 25mm (max)25mm (max)

3

DRAM_RST

I_GPU

N1R27 10

I_GPU

N1R26

4.99K

1%

1 2

L10

GPU_DRA M_RST# R_DRAM_RST#

12

GND GND

2

12

I_GPU

N1C128 120PF/50 V

NPO 5%

I_GPU

N1R28

51.1

1%

1 2

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

DRAM_RS T# 60,61,6 2,63

IMPLP-MS

Title :

Engineer:

1

SUN-XT_MEM

Stonko_Chen

56 83Thu rsday, June 27, 2013

Rev

A00

GM_CHA0 _DQ[0..31]60,61

D D

C C

DQ bit swapping is allowed in a byte lane.

GM_CHA1 _DQ[0..31]62,63

Place MVREF dividers and Caps close to ASIC

B B

A A

+1P35V_GPU

12

I_GPU

N1R22

40.2

1%

12

I_GPU

N1R102 100

1%

I_GPU

12

N1C125 1UF/6.3V

X5R 10%

5

+1P35V_GPU

12

I_GPU

N1R21

40.2

1%

12

I_GPU

N1R20 100

1%

GNDGNDGND

12

NI

N1C127

0.1UF/16V

X7R 10%

12

NI

N1R25

51.1

1%

GND G ND

GND

I_GPU

12

N1C124 1UF/6.3V

X5R 10%

12

NI

N1C126

0.1UF/16V

X7R 10%

12

NI

N1R24

51.1

1%

4

GM_CHA0 _DQ0 GM_CHA0 _DQ1 GM_CHA0 _DQ2 GM_CHA0 _DQ3 GM_CHA0 _DQ4 GM_CHA0 _DQ5 GM_CHA0 _DQ6 GM_CHA0 _DQ7 GM_CHA0 _DQ8 GM_CHA0 _DQ9 GM_CHA0 _DQ10 GM_CHA0 _DQ11 GM_CHA0 _DQ12 GM_CHA0 _DQ13 GM_CHA0 _DQ14 GM_CHA0 _DQ15 GM_CHA0 _DQ16 GM_CHA0 _DQ17 GM_CHA0 _DQ18 GM_CHA0 _DQ19 GM_CHA0 _DQ20 GM_CHA0 _DQ21 GM_CHA0 _DQ22 GM_CHA0 _DQ23 GM_CHA0 _DQ24 GM_CHA0 _DQ25 GM_CHA0 _DQ26 GM_CHA0 _DQ27 GM_CHA0 _DQ28 GM_CHA0 _DQ29 GM_CHA0 _DQ30 GM_CHA0 _DQ31 GM_CHA1 _DQ0 GM_CHA1 _DQ1 GM_CHA1 _DQ2 GM_CHA1 _DQ3 GM_CHA1 _DQ4 GM_CHA1 _DQ5 GM_CHA1 _DQ6 GM_CHA1 _DQ7 GM_CHA1 _DQ8 GM_CHA1 _DQ9 GM_CHA1 _DQ10 GM_CHA1 _DQ11 GM_CHA1 _DQ12 GM_CHA1 _DQ13 GM_CHA1 _DQ14 GM_CHA1 _DQ15 GM_CHA1 _DQ16 GM_CHA1 _DQ17 GM_CHA1 _DQ18 GM_CHA1 _DQ19 GM_CHA1 _DQ20 GM_CHA1 _DQ21 GM_CHA1 _DQ22 GM_CHA1 _DQ23 GM_CHA1 _DQ24 GM_CHA1 _DQ25 GM_CHA1 _DQ26 GM_CHA1 _DQ27 GM_CHA1 _DQ28 GM_CHA1 _DQ29 GM_CHA1 _DQ30 GM_CHA1 _DQ31

MVREFDA MVREFSA

MEM_CAL RP0

I_GPU

N1R23 120

1%

GND

CLKTEST A CLKTEST B

Route CLKTESTA/B 50ohms single-ended 100ohms differential and keep short

5

+1P35V_GPU

I_GPU

12

N1C42 10UF/6.3V

X5R 10% mx_c0805_ small

D D

I_GPU

12

N1C47

2.2UF/6.3V

X5R 10% mx_c0603

+1P8V_M XM +1P8V_M XM_VDDCT

C C

+3P3V_GPU +3P3V_GP U_VDDR3

B B

A A

+1P8V_M XM +1P8V_M PLL_PVDD

+1P8V_M XM +1P8V_S PLL_PVDD GND

5

I_GPU

N1L2 120Ohm/1 00Mhz

21

I_GPU

N1L3 120Ohm/1 00Mhz

21

I_GPU

N1L5 120Ohm/1 00Mhz

21

I_GPU

N1L6 120Ohm/1 00Mhz

21

I_GPU

N1L7 120Ohm/1 00Mhz

21

I_GPU

12

N1C46

2.2UF/6.3V

X5R 10% mx_c0603

I_GPU

12

N1C54 1UF/16V

X7R 10% mx_c0603

I_GPU

12

N1C45

2.2UF/6.3V

X5R 10% mx_c0603

I_GPU

12

N1C50

0.1UF/16V

X7R 10%

I_GPU

12

N1C53 1UF/16V

X7R 10% mx_c0603

I_GPU

12

N1C59

0.1UF/16V

X7R 10%

I_GPU

12

N1C62

0.1UF/16V

X7R 10%

+0P95V_ GPU_SPLL_VDD C+0P95V_ GPU GND

I_GPU

12

N1C65

0.1UF/16V

X7R 10%

4

I_GPU

12

N1C41 10UF/6.3V

X5R 10% mx_c0805_ small

I_GPU

12

N1C44

2.2UF/6.3V

X5R 10% mx_c0603

12

I_GPU

N1C49 1UF/6.3V

X5R 10%

I_GPU

12

N1C52 1UF/16V

X7R 10% mx_c0603

I_GPU

12

N1C58 1UF/6.3V

X5R 10%

I_GPU

12

N1C61 1UF/6.3V

X5R 10%

I_GPU

12

N1C64 1UF/6.3V

X5R 10%

4

I_GPU

12

N1C40 10UF/6.3V

X5R 10% mx_c0805_ small

GND

I_GPU

12

N1C43

2.2UF/6.3V

X5R 10% mx_c0603

GND

I_GPU

12

N1C48 10UF/6.3V

X5R 10% mx_c0805_ small

GND

I_GPU

12

N1C51 10UF/6.3V

X5R 10% mx_c0805_ small

GND

I_GPU

12

N1C60 10UF/6.3V

X5R 10% mx_c0805_ small

I_GPU

12

N1C63 10UF/6.3V

X5R 10% mx_c0805_ small

I_GPU

12

N1C66 10UF/6.3V

X5R 10% mx_c0805_ small

GND

AA20 AA21 AB20 AB21

AA17 AA18 AB17 AB18

H13 H16 H19

K10 K23 K24

L11 L12 L13 L20 L21 L22

V12 Y12 U12

J10 J23 J24

J9

K9

L8

H7

H8

J7

I_GPU

N1D SUN-XT-S3

MEM I/O

VDDR1_1 VDDR1_2 VDDR1_3 VDDR1_4 VDDR1_5 VDDR1_6 VDDR1_7 VDDR1_8 VDDR1_9 VDDR1_10 VDDR1_11 VDDR1_12 VDDR1_13 VDDR1_14 VDDR1_15 VDDR1_16 VDDR1_17

LEVEL TRANSLATION

VDD_CT1 VDD_CT2 VDD_CT3 VDD_CT4

I/O

NC_VDDR4_2 NC_VDDR4_3 NC_VDDR4_1

VDDR3_1 VDDR3_2 VDDR3_3 VDDR3_4

PLL

MPLL_PVDD

SPLL_PVDD

SPLL_VDDC

SPLL_PVSS

3

PCIE_PVDD

PCIE

PCIE_VDDC1 PCIE_VDDC2 PCIE_VDDC3 PCIE_VDDC4 PCIE_VDDC5 PCIE_VDDC6 PCIE_VDDC7 PCIE_VDDC8

PCIE_VDDC9 PCIE_VDDC10 PCIE_VDDC11 PCIE_VDDC12

CORE

POWER

ISOLATED CORE I/O

3

NC5

NC7 NC12 NC18 NC19 NC20 NC27 NC36

BIF_VDDC1 BIF_VDDC2

VDDC2 VDDC5 VDDC6 VDDC7 VDDC8

VDDC9 VDDC25 VDDC10 VDDC11 VDDC12 VDDC13 VDDC15 VDDC16 VDDC17 VDDC21 VDDC18 VDDC19 VDDC20 VDDC22 VDDC23 VDDC24

VDDC1

VDDC3

VDDC4 VDDC14

VDDCI_1 VDDCI_2 VDDCI_3 VDDCI_4 VDDCI_5 VDDCI_6 VDDCI_7 VDDCI_8

AM30 AB23 AC23 AD24 AE24 AE25 AE26 AF25 AG26

L23 L24 L25 L26 M22 N22 N23 N24 R22 T22 U22 V22

R21 U21

AA15 N15 N17 R13 R16 R18 Y21 T12 T15 T17 T20 U13 U16 U18 V21 V15 V17 V20 Y13 Y16 Y18 AA12 M11 N12 U11

M13 M15 M16 M17 M18 M20 M21 N20

I_GPU

12

N1C267 10UF/6.3V

X5R 10% mx_c0805_ small

GND

I_GPU

12

N1C71 10UF/6.3V

X5R 10% mx_c0805_ small

GND

I_GPU

12

N1C80 10UF/6.3V

X5R 10% mx_c0805_ small

GND

I_GPU

12

N1C84 1UF/6.3V

X5R 10%

GND

I_GPU

12

N1C88 1UF/6.3V

X5R 10%

GND

I_GPU

12

N1C96 1UF/6.3V

X5R 10%

GND

I_GPU

12

N1C104 1UF/6.3V

X5R 10%

GND

I_GPU

12

N1C114 10UF/6.3V

X5R 10% mx_c0805_ small

GND

I_GPU

12

N1C68

1UF/6.3V

X5R 10%

I_GPU

12

N1C72 10UF/6.3V

X5R 10% mx_c0805_ small

+0P95V_ GPU

I_GPU

12

N1C81 10UF/6.3V

X5R 10% mx_c0805_ small

I_GPU

12

N1C85 1UF/6.3V

X5R 10%

I_GPU

12

N1C89 1UF/6.3V

X5R 10%

I_GPU

12

N1C97 1UF/6.3V

X5R 10%

I_GPU

12

N1C105 1UF/6.3V

X5R 10%

I_GPU

12

N1C115 1UF/6.3V

X5R 10%

2

I_GPU

12

N1C69

0.1UF/16V

X7R 10%

I_GPU

12

N1C73 1UF/6.3V

X5R 10%

I_GPU

12

N1C82 10UF/6.3V

X5R 10% mx_c0805_ small

I_GPU

12

N1C86 1UF/6.3V

X5R 10%

I_GPU

12

N1C90 1UF/6.3V

X5R 10%

I_GPU

12

N1C98 1UF/6.3V

X5R 10%

I_GPU

12

N1C106 1UF/6.3V

X5R 10%

I_GPU

12

N1C116 1UF/6.3V

X5R 10%

2

+1P8V_M XM

I_GPU

12

N1C70

0.01UF/25 V

X7R 10%

I_GPU

12

N1C74 1UF/6.3V

X5R 10%

+VDDC

I_GPU

12

N1C83 10UF/6.3V

X5R 10% mx_c0805_ small

I_GPU

12

N1C87 1UF/6.3V

X5R 10%

I_GPU

12

N1C91 1UF/6.3V

X5R 10%

I_GPU

12

N1C99 1UF/6.3V

X5R 10%

I_GPU

12

N1C107 1UF/6.3V

X5R 10%

+VDDCI

I_GPU

12

N1C117 1UF/6.3V

X5R 10%

1

+0P95V_ GPU

I_GPU

12

N1C75 1UF/6.3V

X5R 10%

I_GPU

12

N1C77 1UF/6.3V

X5R 10%

I_GPU

12

N1C112 1UF/6.3V

X5R 10%

I_GPU

12

N1C92 1UF/6.3V

X5R 10%

I_GPU

12

N1C100 1UF/6.3V

X5R 10%

I_GPU

12

N1C108 1UF/6.3V

X5R 10%

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

I_GPU

12

N1C76 1UF/6.3V

X5R 10%

I_GPU

12

N1C78 1UF/6.3V

X5R 10%

I_GPU

12

N1C113 1UF/6.3V

X5R 10%

I_GPU

12

N1C93 1UF/6.3V

X5R 10%

I_GPU

12

N1C101 1UF/6.3V

X5R 10%

I_GPU

12

N1C109 1UF/6.3V

X5R 10%

IMPLP-MS

I_GPU

12

N1C79 1UF/6.3V

X5R 10%

GND

I_GPU

12

N1C110 1UF/6.3V

X5R 10%

I_GPU

12

N1C94 1UF/6.3V

X5R 10%

I_GPU

12

N1C102 1UF/6.3V

X5R 10%

Title :

Engineer:

1

I_GPU

12

N1C111 1UF/6.3V

X5R 10%

I_GPU

12

N1C95 1UF/6.3V

X5R 10%

I_GPU

12

N1C103 1UF/6.3V

X5R 10%

SUN-XT_POWER

Stonko_Chen

57 83Thu rsday, June 27, 2013

Rev

A00

5

4

3

2

1

Some of voltage must connect to +1.8V even though there is no used on Display feature , such as AF14 pin (DP_VDDR1) and AD14(DP_VDDC1) in SUN XT ASIC.

D D

I_GPU

N1G SUN-XT-S3

NC/DP POWER

NC15 NC23 NC16 NC24 NC41 NC34

NC29 NC30 NC31 NC32

NC13 NC21 NC33 NC39 NC45 NC22 NC42 NC47 NC58 NC59 NC40 NC35

NC14

AE11 AF11 AE13 AF13 AG8 AG10

AF6 AF7 AF8 AF9

AE1 AE3 AG1 AG6 AH5 AF10 AG9 AH8 AM6 AM8 AG7 AG11

AE10

NC For Mars

AF16

AF14

AF22

AF23

AF19 AF20

DP POWER

NC_DP_VDDR2 NC_DP_VDDR3 NC_DP_VDDR1 NC_DP_VDDR4 NC_DP_VDDR5 NC_DP_VDDR6 DP_VDDR

NC_DP_VDDC2 NC_DP_VDDC3 NC_DP_VDDC1 NC_DP_VDDC4 DP_VDDC

NC_DP_VSSR4 NC_DP_VSSR6 NC_DP_VSSR7 NC_DP_VSSR8 NC_DP_VSSR9 NC_DP_VSSR3 NC_DP_VSSR5 NC_DP_VSSR10 NC_DP_VSSR11 NC_DP_VSSR12 NC_DP_VSSR1 NC_DP_VSSR2 DP_VSSR

AG15 AG16

+1P8V_M XM

I_GPU

12

N1C119

0.1UF/16V

X7R 10%

+0P95V_ GPU

C C

I_GPU

12

N1C122

0.1UF/16V

X7R 10%

12

I_GPU

N1C118 1UF/6.3V

X5R 10%

I_GPU

N1C121 1UF/6.3V

X5R 10%

I_GPU

12

N1C120 10UF/6.3V

X5R 10% mx_c0805_ small

GND

I_GPU

12

N1C123 10UF/6.3V

X5R 10% mx_c0805_ small

GND

AG17 AG18 AG19

AG20 AG21

AG22 AD14

AG14 AH14 AM14 AM16 AM18

AG23 AM20 AM22 AM24

AE14

B B

A A

5

4

GND

AF17

NC_UPHYAB_DP_CALR

PEGATRON DT-MB RESTRICTED SECRET

SUN-XT_DP_POWER

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

3

2

Date: Sheet of

IMPLP-MS

Engineer:

SUN-XT_DP_POWER

1

Stonko_Chen

58 83Thu rsday, June 27, 2013

Rev

A00

5

I_GPU

N1E

AA27 AB24 AB32 AC24 AC26 AC27 AD25 AD32 AE27 AF32 AG27 AH32

K28 K32 L27

M32

N25 N27 P25 P32 R27 T25 T32 U25 U27

V32 W25 W26 W27

Y25

Y32

N13

N16

N18

N21

R12

R15

R17

R20

T13

T16

T18

T21

U15

U17

U20

V13

V16

V18

Y10

Y15

Y17

Y20

R11

T11

AA11

M12

N11

V11

M6

P6 P9

T6

U9

SUN-XT-S3

GND6 GND9 GND10 GND12 GND13 GND14 GND16 GND17 GND20 GND22 GND24 GND27 GND68 GND69 GND71 GND73 GND80 GND81 GND82 GND83 GND91 GND97 GND98 GND103 GND104 GND110 GND111 GND112 GND113 GND118 GND119

GND74 GND76 GND77 GND78 GND79 GND84 GND85 GND87 GND88 GND89 GND90 GND93 GND94 GND95 GND96 GND99 GND100 GND101 GND102 GND105 GND107 GND108 GND109 GND114 GND115 GND116 GND117 GND86 GND92 GND3 GND72 GND75 GND106

GND

VSS_MECH1 VSS_MECH2 VSS_MECH3

D D

C C

B B

GND1 GND2 GND4 GND5 GND7

GND8 GND11 GND15 GND18 GND19 GND21 GND23 GND25 GND26 GND28 GND29 GND30 GND31 GND32 GND33 GND34 GND35 GND36 GND37 GND38 GND39 GND40 GND41 GND42 GND43 GND44 GND45 GND46 GND47 GND48 GND49 GND50 GND51 GND52 GND53 GND54 GND55 GND56 GND57 GND58 GND59 GND60 GND61 GND62 GND63 GND64 GND65 GND66 GND67 GND70

4

A3 A30 AA13 AA16 AB10 AB15 AB6 AC9 AD6 AD8 AE7 AG12 AH10 AH28 B10 B12 B14 B16 B18 B20 B22 B24 B26 B6 B8 C1 C32 E28 F10 F12 F14 F16 F18 F2 F20 F22 F24 F26 F6 F8 G10 G27 G31 G8 H14 H17 H2 H20 H6 J27 J31 K11 K2 K22 K6

A32 AM1 AM32

GND

3

I_GPU

N1F SUN-XT-S3

NC_UPHYAB_TMDPA_TX0N NC_UPHYAB_TMDPA_TX0P

NC_UPHYAB_TMDPA_TX1N NC_UPHYAB_TMDPA_TX1P

NC_UPHYAB_TMDPA_TX2N NC_UPHYAB_TMDPA_TX2P

NC_UPHYAB_TMDPA_TX3N NC_UPHYAB_TMDPA_TX3P

NC_UPHYAB_TMDPB_TX0N NC_UPHYAB_TMDPB_TX0P

NC_UPHYAB_TMDPB_TX1N NC_UPHYAB_TMDPB_TX1P

NC_UPHYAB_TMDPB_TX2N NC_UPHYAB_TMDPB_TX2P

NC_UPHYAB_TMDPB_TX3N NC_UPHYAB_TMDPB_TX3P

NC_VARY_BL

NC_DIGON

NC_TXOUT_L3P NC_TXOUT_L3N

TMDP

NC_TXOUT_U3P NC_TXOUT_U3N

AB11 AB12

AL15 AK14

AH16 AJ15

AL17 AK16

AH18 AJ17

AL19 AK18

AH20 AJ19

AL21 AK20

AH22 AJ21

AL23 AK22

AK24 AJ23

2

Mars only supports TMDPA and TMDPB

I_GPU

N1_BP

GPU

1

GND

A A

PEGATRON DT-MB RESTRICTED SECRET

SUN-XT_GND&TMDS

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

5

4

3

2

Date: Sheet of

IMPLP-MS

Engineer:

SUN-XT_GND&TMDS

1

Stonko_Chen

59 83Thu rsday, June 27, 2013

Rev

A00

5

4

3

2

1

CELL1 TOP X16 MODE (MF=0)

GDDR5 HYNIX 0315-011A0DE

I_GPU

GM_CHA0 _DQ[0..7]56

D D

The x16 mode is detected at power up on the pin at location C13 which is EDC1 when configured to MF=0

C C

GM_CHA0 _DQ[16..23]56

BYTE 0

EDCA0_056 DDBIA0_056

+1P35V_ GPU

WCKA 0_056,61 WCKA 0#_056,61 CLKA056,61

BYTE 2

EDCA0_256 DDBIA0_256

B B

WCKA 0_156,61 WCKA 0#_156,61

GM_CHA0 _DQ0 GM_CHA0 _DQ1 GM_CHA0 _DQ2 GM_CHA0 _DQ3 GM_CHA0 _DQ4 GM_CHA0 _DQ5 GM_CHA0 _DQ6 GM_CHA0 _DQ7

GND

GM_CHA0 _DQ16 GM_CHA0 _DQ17 GM_CHA0 _DQ18 GM_CHA0 _DQ19 GM_CHA0 _DQ20 GM_CHA0 _DQ21 GM_CHA0 _DQ22 GM_CHA0 _DQ23

+1P35V_ GPU

D5U1A

A4

DQ0/DQ24

A2

DQ1/DQ25

B4

DQ2/DQ26

B2

DQ3/DQ27

E4

DQ4/DQ28

E2

DQ5/DQ29

F4

DQ6/DQ30

F2

DQ7/DQ31

C2

EDC0/EDC3

D2

DBI0#/DBI3#

A11

DQ8/DQ16

A13

DQ9/DQ17

B11

DQ10/DQ18

B13

DQ11/DQ19

E11

DQ12/DQ20

E13

DQ13/DQ21

F11

DQ14/DQ22

F13

DQ15/DQ23

C13

EDC1/EDC2

D13

DBI1#/DBI2#

D4

WCK01/WCK23

D5

WCK01#/WCK23#

K4G4132 5FC_HC04

I_GPU

D5U1B

U11

DQ16/DQ8

U13

DQ17/DQ9

T11

DQ18/DQ10

T13

DQ19/DQ11

N11

DQ20/DQ12

N13

DQ21/DQ13

M11

DQ22/DQ14

M13

DQ23/DQ15

R13

EDC2/EDC1

P13

DBI2#/DBI1#

U4

DQ24/DQ0

U2

DQ25/DQ1

T4

DQ26/DQ2

T2

DQ27/DQ3

N4

DQ28/DQ4

N2

DQ29/DQ5

M4

DQ30/DQ6

M2

DQ31/DQ7

R2

EDC3/EDC0

P2

DBI3#/DBI0#

P4

WCK23/WCK01

P5

WCK23#/WCK01#

K4G4132 5FC_HC04

VREFD1

VREFD2

Samsung 0315-010U0DE

+1P35V_ GPU

12

A10

U10

NI

12

N1C148 1UF/6.3V

X5R 10%

D51_VRE FD1

I_GPU

12

N1C147 1UF/6.3V

X5R 10%

GND

NI

12

N1C150 1UF/6.3V

X5R 10%

D51_VRE FD2

I_GPU

12

N1C149 1UF/6.3V

X5R 10%

I_GPU

N1R30

2.37K

1%

12

I_GPU

N1R29

5.49K

1%

+1P35V_ GPU

12

I_GPU

N1R31

2.37K

1%

12

I_GPU

N1R32

5.49K

1%

Decoupling caps for clamshell configuration (2 chip at top and bottom) 1 X 10uf per 2 clamshell DRAMs 8 X 1uf per 2 clamshell DRAMs Note: it is recommended to use a clamshell placement of the two QDR II SRAM components to achieve minimal stub delays and optimum signal integrity. Clamshell placement is when two devices overlay each other by being placed on opposite sides of the PCB.

MF=0

I_GPU

D5U1C

D51_VRE FC

D51_ZQ

G3

RAS#/CAS#

L3

CAS#/RAS#

L12

WE#/CS#

G12

CS#/WE#

J4

ABI#

H4

A10/A0/A8/A7

H5

A9/A1/A11/A6

H11

BA0/A2/BA2/A4

H10

BA3/A3/BA1/A5

K11

BA2/A4/BA0/A2

K10

BA1/A5/BA3/A3

K5

A11/A6/A9/A1

K4

A8/A7/A10/A0

J5

A12/A13

J2

RESET#

J3

CKE#

J12

CK

J11

CK#

A5

NC1

U5

NC2

J14

VREFC

J13

ZQ

J10

SEN

K4G4132 5FC_HC04

GND

RASA0#56,6 1 CASA0#56,6 1 WEA0 #56,61 CSA0#_056 ,61

GM_CHA_ MAA0_[0..8]56,61

+1P35V_ GPU

I_GPU

N1R38 120

1%

CLKA0#56,61

NI

12

N1C152 1UF/6.3V

X5R 10%

I_GPU

12

N1C151 1UF/6.3V

X5R 10%

GND

I_GPU

N1R103 120

1%

+1P35V_ GPU

12

I_GPU

N1R33

2.37K

1%

12

I_GPU

N1R34

5.49K

1%

ADBIA0#56,61

DRAM_RS T#56,61,62,63

GNDGND

GM_CHA_ MAA0_0 GM_CHA_ MAA0_1 GM_CHA_ MAA0_2 GM_CHA_ MAA0_3 GM_CHA_ MAA0_4 GM_CHA_ MAA0_5 GM_CHA_ MAA0_6 GM_CHA_ MAA0_7 GM_CHA_ MAA0_8

CKEA056,6 1

I_GPU

N1R35 120

1%

GND

I_GPU

D5U1D

J1

MF

B10

VSS1

B5

VSS2

D10

VSS3

G10

VSS4

G5

VSS5

H1

VSS6

H14

VSS7

K1

VSS8

K14

VSS9

L10

VSS10

L5

VSS11

P10

VSS12

T10

VSS13

T5

VSS14

A1

VSSQ1

A12

VSSQ2

A14

VSSQ3

A3

VSSQ4

C1

VSSQ5

C11

VSSQ6

C12

VSSQ7

C14

VSSQ8

C3

VSSQ9

C4

VSSQ10

E1

VSSQ11

E12

VSSQ12

E14

VSSQ13

E3

VSSQ14

F10

VSSQ15

F5

VSSQ16

H13

VSSQ17

H2

VSSQ18

K13

VSSQ19

K2

VSSQ20

M10

VSSQ21

M5

VSSQ22

N1

VSSQ23

N12

VSSQ24

N14

VSSQ25

N3

VSSQ26

R1

VSSQ27

R11

VSSQ28

R12

VSSQ29

R14

VSSQ30

R3

VSSQ31

R4

VSSQ32

U1

VSSQ33

U12

VSSQ34

U14

VSSQ35

U3

VSSQ36

K4G4132 5FC_HC04

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VDDQ19 VDDQ20 VDDQ21 VDDQ22 VDDQ23 VDDQ24 VDDQ25 VDDQ26 VDDQ27 VDDQ28 VDDQ29 VDDQ30 VDDQ31 VDDQ32 VDDQ33 VDDQ34 VDDQ35 VDDQ36

+1P35V_ GPU

C10 C5 D11 G1 G11 G14 G4 L1 L11 L14 L4 P11 R10 R5

B1 B12 B14 B3 D1 D12 D14 D3 E10 E5 F1 F12 F14 F3 G13 G2 H12 H3 K12 K3 L13 L2 M1 M12 M14 M3 N10 N5 P1 P12 P14 P3 T1 T12 T14 T3

+1P35V_ GPU

I_GPU

12

N1C130 10UF/6.3V

X5R 10% mx_c0805_ small

A A

5

4

GND

Note: Stitching Caps OPTION for MEM signals that have a change of reference plane voltage Add stitching caps when required, one cap per three signals

12

I_GPU

N1C129 1UF/6.3V

X5R 10%

12

I_GPU

N1C131 1UF/6.3V

X5R 10%

12

I_GPU

N1C132 1UF/6.3V

X5R 10%

3

12

I_GPU

N1C133 1UF/6.3V

X5R 10%

12

I_GPU

N1C134 1UF/6.3V

X5R 10%

12

I_GPU

N1C135 1UF/6.3V

X5R 10%

12

I_GPU

N1C136 1UF/6.3V

X5R 10%

2

12

I_GPU

N1C137 1UF/6.3V

X5R 10%

PEGATRON DT-MB RESTRICTED SECRET

GDDR5 X16 XCELL1_TOP

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

IMPLP-MS

Engineer:

GDDR5 X16 XCELL1_TOP

1

Stonko_Chen

60 83Thu rsday, June 27, 2013

Rev

A00

5

4

3

2

1

CELL1 BOTTOM X16 MODE (MF=1)

I_GPU

GM_CHA0 _DQ[24..31]56

EDCA0_356 DDBIA0_356

WCKA 0_156,60 WCKA 0#_156,60

BYTE 3

+1P35V_ GPU

D D

C C

GM_CHA0 _DQ[8..15]5 6

BYTE 1

EDCA0_156 DDBIA0_156

The x16 mode is detected at power up on the pin at location R13 which is EDC1 when configured to MF=1

B B

WCKA 0_056,60 WCKA 0#_056,60

GM_CHA0 _DQ24 GM_CHA0 _DQ25 GM_CHA0 _DQ26 GM_CHA0 _DQ27 GM_CHA0 _DQ28 GM_CHA0 _DQ29 GM_CHA0 _DQ30 GM_CHA0 _DQ31

GND

GM_CHA0 _DQ8 GM_CHA0 _DQ9 GM_CHA0 _DQ10 GM_CHA0 _DQ11 GM_CHA0 _DQ12 GM_CHA0 _DQ13 GM_CHA0 _DQ14 GM_CHA0 _DQ15

+1P35V_ GPU

D5U2A

A4

DQ0/DQ24

A2

DQ1/DQ25

B4

DQ2/DQ26

B2

DQ3/DQ27

E4

DQ4/DQ28

E2

DQ5/DQ29

F4

DQ6/DQ30

F2

DQ7/DQ31

C2

EDC0/EDC3

D2

DBI0#/DBI3#

A11

DQ8/DQ16

A13

DQ9/DQ17

B11

DQ10/DQ18

B13

DQ11/DQ19

E11

DQ12/DQ20

E13

DQ13/DQ21

F11

DQ14/DQ22

F13

DQ15/DQ23

C13

EDC1/EDC2

D13

DBI1#/DBI2#

D4

WCK01/WCK23

D5

WCK01#/WCK23#

K4G4132 5FC_HC04

I_GPU

D5U2B

U11

DQ16/DQ8

U13

DQ17/DQ9

T11

DQ18/DQ10

T13

DQ19/DQ11

N11

DQ20/DQ12

N13

DQ21/DQ13

M11

DQ22/DQ14

M13

DQ23/DQ15

R13

EDC2/EDC1

P13

DBI2#/DBI1#

U4

DQ24/DQ0

U2

DQ25/DQ1

T4

DQ26/DQ2

T2

DQ27/DQ3

N4

DQ28/DQ4

N2

DQ29/DQ5

M4

DQ30/DQ6

M2

DQ31/DQ7

R2

EDC3/EDC0

P2

DBI3#/DBI0#

P4

WCK23/WCK01

P5

WCK23#/WCK01#

K4G4132 5FC_HC04

VREFD1

VREFD2

A10

U10

NI

12

N1C170 1UF/6.3V

X5R 10%

D52_VRE FD1

I_GPU

12

N1C173 1UF/6.3V

X5R 10%

GND

NI

12

N1C172 1UF/6.3V

X5R 10%

D52_VRE FD2

I_GPU

12

N1C171 1UF/6.3V

X5R 10%

+1P35V_ GPU

12

I_GPU

N1R73

2.37K

1%

12

I_GPU

N1R78

5.49K

1%

+1P35V_ GPU

12

I_GPU

N1R81

2.37K

1%

12

I_GPU

N1R74

5.49K

1%

I_GPU

D5U2C

D52_VRE FC

D52_ZQ

G3

RAS#/CAS#

L3

CAS#/RAS#

L12

WE#/CS#

G12

CS#/WE#

J4

ABI#

H4

A10/A0/A8/A7

H5

A9/A1/A11/A6

H11

BA0/A2/BA2/A4

H10

BA3/A3/BA1/A5

K11

BA2/A4/BA0/A2

K10

BA1/A5/BA3/A3

K5

A11/A6/A9/A1

K4

A8/A7/A10/A0

J5

A12/A13

J2

RESET#

J3

CKE#

J12

CK

J11

CK#

A5

NC1

U5

NC2

J14

VREFC

J13

ZQ

J10

SEN

K4G4132 5FC_HC04

GND

G10

M10

B10

D10

H14

K14 L10

P10 T10

A12 A14

C11 C12 C14

E12 E14

F10

H13

K13

N12 N14

R11 R12 R14

U12 U14

G5

M5

CASA0#56,6 0 RASA0#56,6 0 CSA0#_056 ,60 WEA0 #56,60

GM_CHA_ MAA0_[0..8]56,60

+1P35V_ GPU

I_GPU

N1R67 120

1%

CLKA056,60 CLKA0#56,60

NI

12

N1C169 1UF/6.3V

X5R 10%

I_GPU

12

N1C174 1UF/6.3V

X5R 10%

GND

I_GPU

N1R80 120

1%

+1P35V_ GPU

12

I_GPU

N1R83

2.37K

1%

12

I_GPU

N1R79

5.49K

1%

ADBIA0#56,60

DRAM_RS T#56,60,62,63

GNDGND

GM_CHA_ MAA0_7 GM_CHA_ MAA0_6 GM_CHA_ MAA0_4 GM_CHA_ MAA0_5 GM_CHA_ MAA0_2 GM_CHA_ MAA0_3 GM_CHA_ MAA0_1 GM_CHA_ MAA0_0 GM_CHA_ MAA0_8

CKEA056,6 0

I_GPU

N1R82 120

1%

GND

I_GPU

D5U2D

J1

MF VSS1

B5

VSS2 VSS3 VSS4 VSS5

H1

VSS6 VSS7

K1

VSS8 VSS9 VSS10

L5

VSS11 VSS12 VSS13

T5

VSS14

A1

VSSQ1 VSSQ2 VSSQ3

A3

VSSQ4

C1

VSSQ5 VSSQ6 VSSQ7 VSSQ8

C3

VSSQ9

C4

VSSQ10

E1

VSSQ11 VSSQ12 VSSQ13

E3

VSSQ14 VSSQ15

F5

VSSQ16 VSSQ17

H2

VSSQ18 VSSQ19

K2

VSSQ20 VSSQ21 VSSQ22

N1

VSSQ23 VSSQ24 VSSQ25

N3

VSSQ26

R1

VSSQ27 VSSQ28 VSSQ29 VSSQ30

R3

VSSQ31

R4

VSSQ32

U1

VSSQ33 VSSQ34 VSSQ35

U3

VSSQ36

K4G4132 5FC_HC04

MF=1

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VDDQ19 VDDQ20 VDDQ21 VDDQ22 VDDQ23 VDDQ24 VDDQ25 VDDQ26 VDDQ27 VDDQ28 VDDQ29 VDDQ30 VDDQ31 VDDQ32 VDDQ33 VDDQ34 VDDQ35 VDDQ36

C10 C5 D11 G1 G11 G14 G4 L1 L11 L14 L4 P11 R10 R5

B1 B12 B14 B3 D1 D12 D14 D3 E10 E5 F1 F12 F14 F3 G13 G2 H12 H3 K12 K3 L13 L2 M1 M12 M14 M3 N10 N5 P1 P12 P14 P3 T1 T12 T14 T3

+1P35V_ GPU+1P35V_ GPU

MF=0 MF=1 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

DQ16 DQ8 DQ17 DQ9 DQ18 DQ10

A A

5

DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15

MF=0 MF=1 WCK01/01# WCK23/23# WCK23/23# WCK01/01# DBI0# DBI3# DBI1# DBI2# DBI2# DBI1# DBI3# DBI0# EDC0 EDC3 EDC1 EDC2 EDC2 EDC1 EDC3 EDC0

4

MF=0 MF=1 A0 A7 A1 A6 A2 A4 A3 A5 A4 A2 A5 A3 A6 A1 A7 A0

MF=1 , RAS# / CAS# / WE# / CS# / ADDRESS will mirror. MF=0 MF=1 RAS# CAS# CAS# RAS# CS# WE# WE# CS#

3

PEGATRON DT-MB RESTRICTED SECRET

GDDR5 X16 XCELL1_BOT

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

2

Date: Sheet of

IMPLP-MS

Engineer:

GDDR5 X16 XCELL1_BOT

1

Stonko_Chen

61 83Thu rsday, June 27, 2013

Rev

A00

5

4

3

2

1

CELL2 TOP X16 MODE (MF=0)

I_GPU

GM_CHA1 _DQ[0..7]56

D D

The x16 mode is detected at power up on the pin at location C13 which is EDC1 when configured to MF=0

C C

GM_CHA1 _DQ[16..23]56

BYTE 0

EDCA1_056 DDBIA1_056

+1P35V_ GPU

WCKA 1_056,63 WCKA 1#_056,63 CLKA156,63

BYTE 2

EDCA1_256 DDBIA1_256

B B

WCKA 1_156,63 WCKA 1#_156,63

GM_CHA1 _DQ0 GM_CHA1 _DQ1 GM_CHA1 _DQ2 GM_CHA1 _DQ3 GM_CHA1 _DQ4 GM_CHA1 _DQ5 GM_CHA1 _DQ6 GM_CHA1 _DQ7

GND

GM_CHA1 _DQ16 GM_CHA1 _DQ17 GM_CHA1 _DQ18 GM_CHA1 _DQ19 GM_CHA1 _DQ20 GM_CHA1 _DQ21 GM_CHA1 _DQ22 GM_CHA1 _DQ23

+1P35V_ GPU

D5U3A

A4

DQ0/DQ24

A2

DQ1/DQ25

B4

DQ2/DQ26

B2

DQ3/DQ27

E4

DQ4/DQ28

E2

DQ5/DQ29

F4

DQ6/DQ30

F2

DQ7/DQ31

C2

EDC0/EDC3

D2

DBI0#/DBI3#

A11

DQ8/DQ16

A13

DQ9/DQ17

B11

DQ10/DQ18

B13

DQ11/DQ19

E11

DQ12/DQ20

E13

DQ13/DQ21

F11

DQ14/DQ22

F13

DQ15/DQ23

C13

EDC1/EDC2

D13

DBI1#/DBI2#

D4

WCK01/WCK23

D5

WCK01#/WCK23#

K4G4132 5FC_HC04

I_GPU

D5U3B

U11

DQ16/DQ8

U13

DQ17/DQ9

T11

DQ18/DQ10

T13

DQ19/DQ11

N11

DQ20/DQ12

N13

DQ21/DQ13

M11

DQ22/DQ14

M13

DQ23/DQ15

R13

EDC2/EDC1

P13

DBI2#/DBI1#

U4

DQ24/DQ0

U2

DQ25/DQ1

T4

DQ26/DQ2

T2

DQ27/DQ3

N4

DQ28/DQ4

N2

DQ29/DQ5

M4

DQ30/DQ6

M2

DQ31/DQ7

R2

EDC3/EDC0

P2

DBI3#/DBI0#

P4

WCK23/WCK01

P5

WCK23#/WCK01#

K4G4132 5FC_HC04

VREFD1

VREFD2

+1P35V_ GPU

12

NI

12

N1C154 1UF/6.3V

X5R 10%

A10

D53_VRE FD1

I_GPU

12

N1C157 1UF/6.3V

X5R 10%

GND

NI

12

N1C156 1UF/6.3V

X5R 10%

U10

D53_VRE FD2

I_GPU

12

N1C155 1UF/6.3V

X5R 10%

Decoupling caps for clamshell configuration (2 chip at top and bottom) 1 X 10uf per 2 clamshell DRAMs 8 X 1uf per 2 clamshell DRAMs Note: it is recommended to use a clamshell placement of the two QDR II SRAM components to achieve minimal stub delays and optimum signal integrity. Clamshell placement is when two devices overlay each other by being placed on opposite sides of the PCB.

I_GPU

N1R85

2.37K

1%

12

I_GPU

N1R87

5.49K

1%

+1P35V_ GPU

12

I_GPU

N1R90

2.37K

1%

12

I_GPU

N1R86

5.49K

1%

GM_CHA_ MAA1_[0..8]56,63

+1P35V_ GPU

I_GPU

N1R84 120

1%

CLKA1#56,63

NI

12

N1C153 1UF/6.3V

X5R 10%

I_GPU

12

N1C158 1UF/6.3V

X5R 10%

GND

I_GPU

N1R89 120

1%

+1P35V_ GPU

12

I_GPU

N1R92

2.37K

1%

12

I_GPU

N1R88

5.49K

1%

RASA1#56,6 3 CASA1#56,6 3 WEA1 #56,63 CSA1#_056 ,63

ADBIA1#56,63

DRAM_RS T#56,60,61,63

GNDGND

GM_CHA_ MAA1_0 GM_CHA_ MAA1_1 GM_CHA_ MAA1_2 GM_CHA_ MAA1_3 GM_CHA_ MAA1_4 GM_CHA_ MAA1_5 GM_CHA_ MAA1_6 GM_CHA_ MAA1_7 GM_CHA_ MAA1_8

CKEA156,6 3

I_GPU

N1R91 120

1%

D53_VRE FC

D53_ZQ

GND

I_GPU

D5U3C

G3

RAS#/CAS#

L3

CAS#/RAS#

L12

WE#/CS#

G12

CS#/WE#

J4

ABI#

H4

A10/A0/A8/A7

H5

A9/A1/A11/A6

H11

BA0/A2/BA2/A4

H10

BA3/A3/BA1/A5

K11

BA2/A4/BA0/A2

K10

BA1/A5/BA3/A3

K5

A11/A6/A9/A1

K4

A8/A7/A10/A0

J5

A12/A13

J2

RESET#

J3

CKE#

J12

CK

J11

CK#

A5

NC1

U5

NC2

J14

VREFC

J13

ZQ

J10

SEN

K4G4132 5FC_HC04

GND

G10

M10

B10

D10

H14

K14 L10

P10 T10

A12 A14

C11 C12 C14

E12 E14

F10

H13

K13

N12 N14

R11 R12 R14

U12 U14

G5

M5

I_GPU

D5U3D

J1

MF VSS1

B5

VSS2 VSS3 VSS4 VSS5

H1

VSS6 VSS7

K1

VSS8 VSS9 VSS10

L5

VSS11 VSS12 VSS13

T5

VSS14

A1

VSSQ1 VSSQ2 VSSQ3

A3

VSSQ4

C1

VSSQ5 VSSQ6 VSSQ7 VSSQ8

C3

VSSQ9

C4

VSSQ10

E1

VSSQ11 VSSQ12 VSSQ13

E3

VSSQ14 VSSQ15

F5

VSSQ16 VSSQ17

H2

VSSQ18 VSSQ19

K2

VSSQ20 VSSQ21 VSSQ22

N1

VSSQ23 VSSQ24 VSSQ25

N3

VSSQ26

R1

VSSQ27 VSSQ28 VSSQ29 VSSQ30

R3

VSSQ31

R4

VSSQ32

U1

VSSQ33 VSSQ34 VSSQ35

U3

VSSQ36

K4G4132 5FC_HC04

MF=0

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VDDQ19 VDDQ20 VDDQ21 VDDQ22 VDDQ23 VDDQ24 VDDQ25 VDDQ26 VDDQ27 VDDQ28 VDDQ29 VDDQ30 VDDQ31 VDDQ32 VDDQ33 VDDQ34 VDDQ35 VDDQ36

+1P35V_ GPU

C10 C5 D11 G1 G11 G14 G4 L1 L11 L14 L4 P11 R10 R5

B1 B12 B14 B3 D1 D12 D14 D3 E10 E5 F1 F12 F14 F3 G13 G2 H12 H3 K12 K3 L13 L2 M1 M12 M14 M3 N10 N5 P1 P12 P14 P3 T1 T12 T14 T3

+1P35V_ GPU

I_GPU

12

N1C139 10UF/6.3V

X5R 10% mx_c0805_ small

A A

5

GND

Note: Stitching Caps OPTION for MEM signals that have a change of reference plane voltage Add stitching caps when required, one cap per three signals

4

12

I_GPU

N1C138 1UF/6.3V

X5R 10%

12

I_GPU

N1C140 1UF/6.3V

X5R 10%

12

I_GPU

N1C141 1UF/6.3V

X5R 10%

3

12

I_GPU

N1C142 1UF/6.3V

X5R 10%

12

I_GPU

N1C143 1UF/6.3V

X5R 10%

12

I_GPU

N1C144 1UF/6.3V

X5R 10%

12

I_GPU

N1C145 1UF/6.3V

X5R 10%

I_GPU

12

N1C146 1UF/6.3V

X5R 10%

PEGATRON DT-MB RESTRICTED SECRET

GDDR5 X16 XCELL2_TOP

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

2

Date: Sheet of

IMPLP-MS

Engineer:

GDDR5 X16 XCELL2_TOP

1

Stonko_Chen

62 83Thu rsday, June 27, 2013

Rev

A00

5

4

3

2

1

CELL2 BOTTOM X16 MODE (MF=1)

I_GPU

GM_CHA1 _DQ[24..31]56

EDCA1_356 DDBIA1_356

WCKA 1_156,62 WCKA 1#_156,62

BYTE 3

+1P35V_ GPU

D D

C C

GM_CHA1 _DQ[8..15]5 6

BYTE 1

EDCA1_156 DDBIA1_156

The x16 mode is detected at power up on the pin at location R13 which is EDC1 when configured to MF=1

B B

WCKA 1_056,62 WCKA 1#_056,62

GM_CHA1 _DQ24 GM_CHA1 _DQ25 GM_CHA1 _DQ26 GM_CHA1 _DQ27 GM_CHA1 _DQ28 GM_CHA1 _DQ29 GM_CHA1 _DQ30 GM_CHA1 _DQ31

GND

GM_CHA1 _DQ8 GM_CHA1 _DQ9 GM_CHA1 _DQ10 GM_CHA1 _DQ11 GM_CHA1 _DQ12 GM_CHA1 _DQ13 GM_CHA1 _DQ14 GM_CHA1 _DQ15

+1P35V_ GPU

D5U4A

A4

DQ0/DQ24

A2

DQ1/DQ25

B4

DQ2/DQ26

B2

DQ3/DQ27

E4

DQ4/DQ28

E2

DQ5/DQ29

F4

DQ6/DQ30

F2

DQ7/DQ31

C2

EDC0/EDC3

D2

DBI0#/DBI3#

A11

DQ8/DQ16

A13

DQ9/DQ17

B11

DQ10/DQ18

B13

DQ11/DQ19

E11

DQ12/DQ20

E13

DQ13/DQ21

F11

DQ14/DQ22

F13

DQ15/DQ23

C13

EDC1/EDC2

D13

DBI1#/DBI2#

D4

WCK01/WCK23

D5

WCK01#/WCK23#

K4G4132 5FC_HC04

I_GPU

D5U4B

U11

DQ16/DQ8

U13

DQ17/DQ9

T11

DQ18/DQ10

T13

DQ19/DQ11

N11

DQ20/DQ12

N13

DQ21/DQ13

M11

DQ22/DQ14

M13

DQ23/DQ15

R13

EDC2/EDC1

P13

DBI2#/DBI1#

U4

DQ24/DQ0

U2

DQ25/DQ1

T4

DQ26/DQ2

T2

DQ27/DQ3

N4

DQ28/DQ4

N2

DQ29/DQ5

M4

DQ30/DQ6

M2

DQ31/DQ7

R2

EDC3/EDC0

P2

DBI3#/DBI0#

P4

WCK23/WCK01

P5

WCK23#/WCK01#

K4G4132 5FC_HC04

VREFD1

VREFD2

+1P35V_ GPU

12

NI

12

N1C176 1UF/6.3V

X5R 10%

A10

D54_VRE FD1

I_GPU

12

N1C180 1UF/6.3V

X5R 10%

GND

NI

12

N1C178 1UF/6.3V

X5R 10%

U10

D54_VRE FD2 D54_VRE FC

I_GPU

12

N1C177 1UF/6.3V

X5R 10%

I_GPU

N1R94

2.37K

1%

12

I_GPU

N1R96

5.49K

1%

+1P35V_ GPU

12

I_GPU

N1R99

2.37K

1%

12

I_GPU

N1R95

5.49K

1%

GM_CHA_ MAA1_[0..8]56,62

+1P35V_ GPU

I_GPU

N1R93 120

1%

CLKA156,62 CLKA1#56,62

NI

12

N1C175 1UF/6.3V

X5R 10%

I_GPU

12

N1C179 1UF/6.3V

X5R 10%

GND

I_GPU

N1R98 120

1%

+1P35V_ GPU

12

I_GPU

N1R101

2.37K

1%

12

I_GPU

N1R97

5.49K

1%

CASA1#56,6 2 RASA1#56,6 2 CSA1#_056 ,62 WEA1 #56,62

ADBIA1#56,62

DRAM_RS T#56,60,61,62

CKEA156,6 2

I_GPU

N1R100 120

1%

GNDGND

GM_CHA_ MAA1_7 GM_CHA_ MAA1_6 GM_CHA_ MAA1_4 GM_CHA_ MAA1_5 GM_CHA_ MAA1_2 GM_CHA_ MAA1_3 GM_CHA_ MAA1_1 GM_CHA_ MAA1_0 GM_CHA_ MAA1_8

D54_ZQ

GND

I_GPU

D5U4C K4G4132 5FC_HC04

G3

RAS#/CAS#

L3

CAS#/RAS#

L12

WE#/CS#

G12

CS#/WE#

J4

ABI#

H4

A10/A0/A8/A7

H5

A9/A1/A11/A6

H11

BA0/A2/BA2/A4

H10

BA3/A3/BA1/A5

K11

BA2/A4/BA0/A2

K10

BA1/A5/BA3/A3

K5

A11/A6/A9/A1

K4

A8/A7/A10/A0

J5

A12/A13

J2

RESET#

J3

CKE#

J12

CK

J11

CK#

A5

NC1

U5

NC2

J14

VREFC

J13

ZQ

J10

SEN

+1P35V_ GPU

GND

G10

M10

B10

D10

H14

K14 L10

P10 T10

A12 A14

C11 C12 C14

E12 E14

F10

H13

K13

N12 N14

R11 R12 R14

U12 U14

G5

M5

I_GPU

D5U4D K4G4132 5FC_HC04

J1

MF VSS1

B5

VSS2 VSS3 VSS4 VSS5

H1

VSS6 VSS7

K1

VSS8 VSS9 VSS10

L5

VSS11 VSS12 VSS13

T5

VSS14

A1

VSSQ1 VSSQ2 VSSQ3

A3

VSSQ4

C1

VSSQ5 VSSQ6 VSSQ7 VSSQ8

C3

VSSQ9

C4

VSSQ10

E1

VSSQ11 VSSQ12 VSSQ13

E3

VSSQ14 VSSQ15

F5

VSSQ16 VSSQ17

H2

VSSQ18 VSSQ19

K2

VSSQ20 VSSQ21 VSSQ22

N1

VSSQ23 VSSQ24 VSSQ25

N3

VSSQ26

R1

VSSQ27 VSSQ28 VSSQ29 VSSQ30

R3

VSSQ31

R4

VSSQ32

U1

VSSQ33 VSSQ34 VSSQ35

U3

VSSQ36

MF=1

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VDDQ19 VDDQ20 VDDQ21 VDDQ22 VDDQ23 VDDQ24 VDDQ25 VDDQ26 VDDQ27 VDDQ28 VDDQ29 VDDQ30 VDDQ31 VDDQ32 VDDQ33 VDDQ34 VDDQ35 VDDQ36

+1P35V_ GPU

C10 C5 D11 G1 G11 G14 G4 L1 L11 L14 L4 P11 R10 R5

B1 B12 B14 B3 D1 D12 D14 D3 E10 E5 F1 F12 F14 F3 G13 G2 H12 H3 K12 K3 L13 L2 M1 M12 M14 M3 N10 N5 P1 P12 P14 P3 T1 T12 T14 T3

MF=0 MF=1 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

DQ16 DQ8 DQ17 DQ9 DQ18 DQ10

A A

5

DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15

MF=0 MF=1 WCK01/01# WCK23/23# WCK23/23# WCK01/01# DBI0# DBI3# DBI1# DBI2# DBI2# DBI1# DBI3# DBI0# EDC0 EDC3 EDC1 EDC2 EDC2 EDC1 EDC3 EDC0

4

MF=0 MF=1 A0 A7 A1 A6 A2 A4 A3 A5 A4 A2 A5 A3 A6 A1 A7 A0

MF=1 , RAS# / CAS# / WE# / CS# / ADDRESS will mirror. MF=0 MF=1 RAS# CAS# CAS# RAS# CS# WE# WE# CS#

3

PEGATRON DT-MB RESTRICTED SECRET

GDDR5 X16 XCELL2_BOT

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

2

Date: Sheet of

IMPLP-MS

Engineer:

1

Stonko_Chen

63 83Thu rsday, June 27, 2013

Rev

A00

5

+5V

12

I

PD8 1SS355P T

D D

GND

12

I

PC263

0.1UF/16V

X7R 10%

GND

C C

NI

PR666 0

1 2

I

PC265 1000PF/5 0V

X7R 10%

1 2

I

PU14 INA199A3D CKR

V+3IN+

2

GND

1

REF

OUT

1 2

PR644 10 1%

I

12

I

PC264 1000PF/5 0V

4

PU14-4

5

PU14-5

IN-

6

PU14-6

X7R 10%

1 2

PR645 10 1%

I

1 2

PR648 1K 1 %

I

4

3

2

+3P3V

1

reserve the +5V ref.

1

3

G

2

GND

12

NI

PR658 10K

1%

PROCHOT #_R

D

I

PQ57 2N7002

S

SYS_CS_P 6 5

SYS_CS_N 65

12

NI

PR662

1.8K

1%

+2P5VRE F

12

GNDGN D

I

PR652 10K

1%

I

PC267

0.1UF/16V

X7R 10%

+5V

GND

12

I_GPU

NI

PR661 0

PR653 51KOHM

1%

I

PR649

49.9K

1%

1 2

I

PU15

LM393

CURRENT LIMIT_Ref_R CURRENT LIMIT_Ref

UMA

PR121

24.3KOHM

1%

1 2

PR653=51K ohm for 180W

GND

PR121=24.3K ohm for 150W

3

+IN1

2

-IN1

5

+IN2

6

-IN2

VCC OUT1 OUT2

VEE

+19V

12

I

GND

12

PR663 51KOHM

1%

A00

NI

PR664

4.7K

+19V

8 1 7 4

GND

12

GND

SYS_THROT TLE

I

PC266

0.1UF/25V

X5R 10%

+2P5VREF +3P3V +1V_CPUIOOUT

12

NI

PR669 0

ONESHOT _VCC

I

PU31C

14

GND

VCC

GND

VCC

GND

7

14

7

74LVC00 APW

8

I

PU31D 74LVC00 APW

11

ONESHOT _IN

6

I

PU31B 74LVC00 APW

14

VCC

GND

7

GND

B B

A A

9

10

12

13

4

5

14

VCC

1

2

GND

7

GND

ONESHOT _OUT_RC

I

PU31A 74LVC00 APW

3

I

PR668 0

ONESHOT _OUT

12

GND

I

PC106 1UF/6.3V

X5R 10%

I

PR853

16.2K

1%

12

I

PR657 10K

1%

3

D

I

PQ67

1

2N7002

G

S

2

GND

12

NI

PR854 0

PROCHOT # 9,76

PROCHOT# One shot circuit

PEGATRON DT-MB RESTRICTED SECRET

Title :

CURRENT LIMIT

Stonko_Chen

1

Stonko_Chen

64 83Thu rsday, June 27, 2013

Rev

A00

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

5

4

3

2

Date: Sheet of

IMPLP-MS

Engineer:

5

180/19.5=9.23A

I

PJ18 DC_POW ER_JACK_5P

D D

C C

(+)SPRING

SIGNAL

(-)SPRING

PGND

1 2 3

PSID_IN 39

4 5

6 7 8 9

GND

+19VA_V IN

12

GND

5*3*0.75=11.25A

mx_l1812_h67

1

G

21

mx_l1812_h67

21

mx_l1812_h67

21

3

D

S

2

GND

PL48 150Ohm /100Mhz/5A

I

PL49 150Ohm /100Mhz/5A

I

PL50 150Ohm /100Mhz/5A

I

PC8

0.1UF/50V

X7R 10% mx_c0603_ small

+19VA

12

I

PR15 100K

1%

I

PQ3 2N7002

4

+19VA

12

GND

I

PR14 100K

I

PR16

49.9K

1%

12

GND

I

PC446 22UF/25V

X5R 10% mx_c1206

GND

+19VA

I

12

PC11 1000PF/5 0V

X7R 10%

12

I

PC6

0.1UF/50V

X7R 10% mx_c0603_ small

GND

12

I

PR8 100

mx_r0603_small

12

I

PC9

2.2UF/25V

X5R 10% mx_c0603_ small

+19VA_S N_U_A

12

I

PC10

2.2UF/25V

X5R 10% mx_c0603_ small

GND

12

I

PR9 100

mx_r0603_small

3

12

NI

PR10 100

mx_r0603_small

12

NI

PR11 100

mx_r0603_small

+19VA_S N_A

12

+19VSB_ HB_C

OVP#

UVP#

I

PR12 200K

1%

1

G

1

G

I

12

PC7 1UF/16V

X7R 10% mx_c0603_ small

12

I

PR13 75K

1%

+19V_OV_A

3

D

I

PQ2 2N7002

S

2

+19V_UV _A

3

D

I

PQ4 2N7002

S

2

GND

2

I

PQ1 TPC8120

Id=-18A/Pd= 1.9W

2.6m@10V

S D

1 2 3 4

G

1

NI

PR287

1 2

NOBOM

PJP38 SHORTPIN

1m

1% mx_r1508_h 24

I

PR289 1m

1% mx_r1508_h 24

H/L

8 7 6 5

21

I

PD5 SS14

GND

SYS_CS_P64

SYS_CS_N64

12

+19VSB

12

NOBOM

PJP37 SHORTPIN

+19VA

1

2

I

PD1

B B

A A

BAT54AW

3

GND

OVP

~24V

12

I

PR17

40.2K

1%

12

I

PR24

4.7K

1%

I

PD2 BAT54AW

2

1

5

3

I

12

PC12 10UF/6.3V

X5R 10% mx_c0805_ small

GND

L/H

12

GND

I

PC13 1000PF/5 0V

X7R 10%

+2P5VRE F

12

GND

4

OVP_EN

OVP_REF

I

PC16 10UF/6.3V

X5R 10% mx_c0805_ small

GND

I

PU1 LM393

1

OUT1

2

-IN1

3

+IN1

4

VEE

VCC

OUT2

-IN2

+IN2

8 7 6 5

PU110_V CC_A UVP#

UVP_REF

12

I

PR18 100

mx_r0603_small

12

I

PC14 1UF/50V

X7R 10% mx_c0805_ small

GND

3

+19VA

12

NI

PR19 100

mx_r0603_small

12

H/L

1 2

PR22 243K 1%

I

+19VA

12

I

PR27 10K

1%

NI

PR28 10K

1%

23

I

1

PQ5 APL431B AC

GND

UVP

~15.2V

1 2

I

PR23 1K

1%

2

UVP1_RE F

+19VA+19VA_S N_A

12

GND

I

PR20 100K

1%

I

PR26

18.2K

1%

+19VA

12

GND

I

PR21 100K

1%

I

PC15 1000PF/5 0V

X7R 10%

GND

12

I

PR25

49.9K

1%

PEGATRON DT-MB RESTRICTED SECRET

POWER SUPPLY VIN

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

IMPLP-MS

Engineer:

POWER SUPPLY VIN

1

Stonko_Chen

65 83Thu rsday, June 27, 2013

Rev

A00

5

4

3

2

1

12

B

I

PQ12 P5103EM G

Id=-4.5A/Pd=1 .25W

I

PC104 1UF/16V

X7R 10% mx_c0603

4

C

5

C

5

S

2

D

G

1

PQ4704-P 6

3

I

PR102 10K

1%

1 2

+19V

GND

12

I

+19V / max=0.4A / TDC:0.28A

PR160 100K

For converter board

I

PQ69 IRF8707PB F

17.5mohm @4.5V

SD

GND

1 2 3 4

G

12

I

PR103 10K

1%

8 7 6 5

+5V_DUA L_ENPQ4704-P 4

12

NI

PR93 0

3

D

NI

1

PQ70

G

2N7002

S

2

GND

+5V_DUA L+5 VSB

12

I

PC361

0.1UF/25V

X7R 10% mx_c0603

I

3

2

GND

12

+19V_EN#

D

S

PQ7 SI4835DDY-T1-G E3

Id=-13A/Pd= 5.6W

1 2 3 4

I

PR158 75K

1%

I

PQ8 2N7002

8 7 6 5

DSG

+19V_BL

12

GND

+19VSB

12

D D

+5VSB

12

S3/S4/S5

PSON#

C C

S0/S1

PSON#3 6,79

12

NI

PC100 470PF/50 V

X7R 10%

GND

3

D

1

G

S

2

GND

I

PR156 200K

1%

I

PR159 100K

PS_ON_A

I

PQ9 2N7002

12

GND

I

PC98 1UF/16V

X7R 10% mx_c0603

+19V_BL _EN

1

I

PC99

0.1UF/16V

X7R 10%

G

+5V/Imax:3.5A/TDC:2.45A +3P3V / max:2.552A / TDC:1.786A

5-3.5*11.9m=4.95835V>5 *0.95=4.75V Vdroop: 3.5A*11.9mohm=4 1.65mV Pd=3.5^2*11.9m=145.775 mW

B B

+5VSB

+19V +19V +3P3V

12

I

PR460 10K

1%

12

I

PR469 10K

1%

19*10/(10+10)=9.5V

GND GND

I

PQ63 IRF8707PB F

11.9mohm @10V

8 7 6 5

+5V_EN +3P3V_E N

+5V

SD

1 2 3 4

G

12

I

PC331 1UF/16V

X7R 10% mx_c0603

3-11.9*2.552m=2.97V>3* 0.95=2.85V Vdroop: 2.552A*11.9 mohm=30.3688mV Pd=2.552^2*11.9m=77.5mW

+3P3VSB

12

I

PR461 10K

1%

12

I

PR470

4.7K

19*10/(10+10)=9.5V

GND GND

I

PQ64 IRF8707PB F

11.9mohm @10V

SD

8 7 6 5

G

1 2 3 4

12

I

PC330 1UF/16V

X7R 10% mx_c0603

I

PR157 100K

I

PF1

2.5A/32V

1 2

+19V_BL _F

+19V_BL / max=2.1A / TDC:1.47A For converter board

+5V_DUAL / Imax=9.3A/TDC=6.5A

SLP_S4#19,36,67,79

GND

+19VSB

12

I

PR161 200K

1%

+19V_EN

12

I

PR162 75K

1%

5-9.3*11.9m=4.88933V>5 *0.95=4.75V Vdroop = 9.3*11.9m = 11 0.67mV Pd=9.3^2*11.9m=1.02931 W

I

+19VSB

PQ68 RN47A4

E

3

2

1

GND

1

E

12

NI

PR101 100K

A A

5

4

S0/S1

1(3.3V)

0

S0:Low level S3:High level S5:Low level (default)

3

S3

S4/S5

GND

PEGATRON DT-MB RESTRICTED SECRET

+5V_DUAL / +5V / +3P3V

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

2

Date: Sheet of

IMPLP-MS

Engineer:

1

Stonko_Chen

66 83Thu rsday, June 27, 2013

Rev

A00

5

4

3

2

1

+1P35V_DUAL Imax=29.48A(12.57+1.43A DDR+9A VDDCI+6.48A 0P95GPU) TDC=20.636A

2 1

I

PL57

I

PL59

I

12

PL56

I

PC86

0.01UF/25 V

MLCC/+/-10 %

GNDGNDGND GN D GND

12

I

PC60 10UF/6.3V

X5R 10% mx_c0805_ small

I

PC290 22UF/6.3V

X5R 20% mx_c0805_ small

PJP63

NOBOM

SHORTPIN

1 2

IMPLP-MS

12

I

PC67

0.22UF/10 V

X7R 10% mx_c0603_ small

GND

I

PR73 0

mx_r0603

1 2

I

PR389 1

mx_r0603

1 2

I

PR89 0

mx_r0603

1 2

12

I

PC63 100PF/50 V

NPO 5%

GND

I

PR85 39

1 2

+1P35V_DUAL_BST1

12

I

PC58

0.1UF/25V

X7R 10% mx_c0603_small

+1P35V_ DUAL_R1_HG_D

12

I

PR78

8.2K

+1P35V_ DUAL_R1_LG_D

12

I

PC65 1UF/16V

X7R 10% mx_c0603_small

GND

3

Close to PU36A PIN2

I

PU36A FDMS360 0AS

4 D1

3 D1

D1

2

G1

1

I

PU36B FDMS360 0AS

17

12

NI

PC90 1000PF/5 0V

MLCC/+/-10 %

GND

Close to PU36A PIN4

+VTT_DD R

12

I

PC66 10UF/6.3V

X5R 10% mx_c0805_ small

GND

12

I

PC76 1000PF/5 0V

MLCC/+/-10 %

GND

PHASE(S1/D2)

12

S2

5

S2

6

S2

7

G2

8

9

PHASE(S1/D2)110PHASE(S1/D2)211PHASE(S1/D2)312PHASE(S1/D2)413PHASE(S1/D2)514PHASE(S1/D2)615PHASE(S1/D2)716PHASE(S1/D2)8

+VTT_DDR Imax=1A TDC=0.75A

TPS51216 VTTDDR=2A

2

+1P35V_ DUAL_Vin

I

PC365 10UF/25V

X5R 10% mx_c0805

12

GND

12

+1P35V_ DUAL_SUR

12

GND

1 2

12

I

PC364 10UF/25V

X5R 10% mx_c0805

2nd source(0903-03W9000),

I

test pass.

PL10

0.36uH

Isat=40A

I

PR79 1

mx_r1206

I

PC61 1000PF/5 0V

X7R 10% mx_c0603_ small

I

PR82 39

Trace W= 40 mils

I

PC57 10UF/25V

X5R 10% mx_c0805_ small

21

12

GND

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

I

GND

PU9 TPS5121 6RUKR

12

V5IN

17

S3

16

S5

19

MODE

20

PGOOD

18

TRIP

6

VREF

8

REFIN

7

GND1

21

GND2

22

GND3

23

GND4

15

SW

VTT

+1P35V_ DUAL_BST

14

+1P35V_ DUAL_HG

13

+1P35V_ DUAL_PHASE

11

+1P35V_ DUAL_LG

10

GND

9

+1P35V_ DUAL_SNS

2

3

4

GND

1

+VTT_DD R_VTTSNS

5

+VTTREF

VBST

DRVH

DRVL

PGND

VDDQSNS

VLDOIN

VTTGND

VTTSNS

VTTREF

4

12

I

PC59 1000PF/5 0V

X7R 10%

+1P35V_ DUAL_MODE

12

GND

12

GND

+1P35V_ DUAL_VREF

VREF=1.8V

1.8*10/(10+30)=1.35V

+1P35V_ DUAL_REFIN

12

I

PR84 30K

1%

GNDGND

+5VSB

12

I

PC56 1UF/16V

X7R 10% mx_c0603

GND

+1P35V_ DUAL_S3

+1P35V_ DUAL_S5

12

I

PC55 1000PF/5 0V

X7R 10%

GNDGND

I

PR77

Fsw=300K

100K

1%

+1P35V_ DUAL_TRIP

I

PR81 100K

1%

I

12

PC64

0.01UF/25 V

X7R 10%

GND

D D

I

PR74

1 2

300KHz

400KHz

12

I

PC62

0.1UF/16V

X7R 10%

5

200

1 2

I

PR75 200

I

PR83 10K

1%

+3P3V

12

NI

PR80 100K

SLP_S3#19,3 6,68

SLP_S4#19,36,66,79

C C

PR77 FSW

100K

200K

B B

A A

180Ohm/1 00Mhz

mx_l0805_h43

2 1

180Ohm/1 00Mhz

mx_l0805_h43

2 1

180Ohm/1 00Mhz

mx_l0805_h43

12

I

PC293 22UF/6.3V

X5R 20% mx_c0805_ small

GNDGND

Fsw=300KHz Iin=2.464A Iin,rms5.31A delta I=4.18A ESR=6/2=3mOhm OCP=35.376A@MAX*1.2 times H/S：0.476W( CSD8738 4 *1) L/S：1.37W ( CSD8738 4 *1)

12

I

PC222

2.2UF/6.3V

X5R 10% mx_c0603

GND

near controller IC

Title :

Engineer:

1

+19VSB

12

I

PC366

0.1UF/25V

X5R 10%

+1P35V_ DUAL

12

+

I

PCE12 330UF/2V

GND

1.35V_DUAL & VTT_DDR

Stonko_Chen

67 83Thu rsday, June 27, 2013

Rev

A00

5

4

3

2

1

I

+5V

D D

NI

PD7

SLP_S3#19,3 6,67

C C

B B

OCP=19.374*1.4=27.1236A delta I=4.76A, Rds(on)=14.5mOhm, Vtrip=(39.798-5.31/2)*8*2m=2.87V Rtrip=Vtrip/Itrip=0.603/10*10^-6=287K Ohm

A A

5

1SS355P T

+5V

12

GND

12

GND

12

NI

PR400 100K

I

PC315

0.1UF/16V

X7R 10%

I

PR401 470K

1%

12

GND

+3P3V

12

GND

4

I

PC445 1UF/16V

X7R 10% mx_c0603

I

PR411 100K

+1P5V_E N_A

I

PC360

0.1UF/16V

X7R 10%

+1P5V_P GOOD

+1P5V_T ST_B

+1P5V_T RIP_A

12

I

PR402 180K

1%

GND

PU5 TPS5121 1DSCR

7

V5IN

3

EN

1

PGOOD

5

TST

2

TRIP

VBST

DRVH

DRVL

VFB

GND GND1 GND2

SW

10

9

8

6

4

11 12 13

+1P5V_D RVL_B

+1P5V_V FB_B

GND

1 2

+1P5V_V BST_C

+1P5V_D RVH_B

+1P5V_S W_S

3

I

PR104 0

mx_r0805

12

I

PR406 15K

1%

GND

+1P5V_VBST_R_C

12

I

PC139

0.1UF/25V

X7R 10% mx_c0603

I

PR217 0

mx_r0805

1 2

I

PR216 0

mx_r0805

1 2

I

PR405

17.4K

1%

1 2

NI

PC345 680PF/50 V

+1P5V_D RVH_R_B

12

I

PR404

8.2K

+1P5V_D RVL_R_B

+19VSB

+1P5V Imax=19.374A Itdc=13.5618A (+1P5V+1P05PCH +1P5V_GPU+1P2V)

1.43A+8.46A+8.77A+0.714A

I

PC79 10UF/25V

X5R 10% mx_c0805_ small

I

PL62 1UH/18A

3m/Isat=36A

12

I

PR86 1

mx_r1206

+1P5V_S UR

12

I

PC81 1000PF/5 0V

X7R 10% mx_c0603_ small

GND

12

NI

PC94 1000PF/5 0V

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

Critical_Part = Y

I

PQ11 BSC0909 NS

Id=45A/Pd= 28W

14.5m@4.5 V

54

876

5 D

S

123

GND

12

GND

54

876

5

Critical_Part = Y

D

I

PQ6

S

123

Critical_Part = Y

I

PQ10 BSC0909 NS

Id=45A/Pd= 28W

14.5m@4.5 V

54

876

5 D

S

123

GND

12

NI

PC91 1000PF/5 0V

MLCC/+/-10 %

BSC0909 NS

Id=45A/Pd= 28W

G

GND G ND

Close to PQ10 PIN4 Close to PQ11 PIN4

2

Fsw=290KHz Iin=1.799A Iin,rms5.23A delta I=4.76A ESR=6/2=3mOhm OCP=27.1236A@MAX*1.4 times H/S：0.733W( BSC090 9NS *1) L/S：1.557W ( BSC09 09NS *2)

21

12

I

PC173 10UF/6.3V

X5R 10% mx_c0805_ small

GND G ND

IMPLP-MS

12

+

Title :

Engineer:

1

I

PCE31 330UF/2V

6m/3A

12

I

+

PCE36 330UF/2V

6m/3A

GND

+1P5V

Stonko_Chen

68 83Thu rsday, June 27, 2013

+1P5V

Rev

A00

5

4

3

2

1

+3P3V

+19V

D D

C C

12

NI

PR473 10K

+3P3V_G PU_EN

12

NI

PR474 10K

I_GPU

PR475 0

1 2

NI

PQ47 30mOhm/1 0V SOT-23

D

3

G

1

12

GNDGND

S

2

NI

PC359 1UF/16V

X7R 10% mx_c0603

+3P3V_G PU

+3P3V_GPU Imax=0.09A TDC=0.06A

3.3-30m*0.09=3.2973V>3 .3*0.95=3.135V Vdroop: 0.09A*30mohm=2. 7mV Pd=0.09^2*30m=0.243mW

19*10/(10+10)=9.5V

1.35-8.77*6m=1.29738V >1.35*0.95=1.2825V Vdroop: 8.77A*6mohm=52. 62mV Pd=8.77^2*6m=461.4774mW

NI

PQ66

+19V

3

D

NI

PQ241

1

NVVDD_P WRGD70,72

12

NI

PR479 1K

1%

12

GNDGND

NI

PC279

0.1UF/16V

X7R 10%

2N7002

G

S

2

GND

+1P35V_ DUAL

12

NI

PR471 10K

12

NI

PR472

53.6K

1%

NTMFS48 39NHT1G

GPU

5 4

+1P35V_ GPU_EN

8

1

7

2

S

6

3

D

5

G

+1P35V_ GPU

19*17.4/(17.4+10)=12.0 66V

12

NI

PC351 1UF/16V

X7R 10% mx_c0603

GNDGND

+1P35V_GPU/Imax:8.77A/TDC:6.139A

B B

A A

PEGATRON DT-MB RESTRICTED SECRET

+3P3V_GPU & +1P5V_GPU

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

IMPLP-MS

1

Stonko_Chen

69 83Thu rsday, June 27, 2013

Rev

A00

5

4

3

2

1

FEEBACK COMPENSATION

NI

PR442

D D

+3P3V

12

I_GPU

PR261

24.9K

1%

Vref=3.3*10/(24.9+10)=0.9 456V

NI

12

GND GND

C C

B B

+3P3V

12

GND

12

I_GPU

PR414 10K

1%

I_GPU

PR419 10K

1%

I_GPU

PR278 12K

1%

I_GPU

PC207

2.2UF/6.3V

X5R 10% mx_c0603

Vref=3.3*12/(12+10)=1.8V

12

I_GPU

PC202

2.2UF/6.3V

X5R 10% mx_c0603

GND

3

D

I_GPU

PQ240 2N7002

GPU_PW R_EN71

+3P3VSB

12

I_GPU

PR422

8.2K

1%

S

GND

G

2

1

G

GND

PC313 47PF/50V

3

D

I_GPU

PQ238 2N7002

S

2

14.7K

1%

1 2

I_GPU

12

PC203 820PF/50 V

X7R 10%

+0P95V_ GPU_C

12

I_GPU

PR420 15K

1%

+0P95V_ GPU_REF

+0P95V_ GPU_10

+1P8V_M XM_REF

+1P8V_M XM__FB_A

I_GPU

PR418

14.7K

1%

1 2

+0P95V_GPU Enable +1P8VMXM Enable

NVVDD_P WRGD69,72

12

NI

PR412 1K

1%

A A

5

12

GNDGND

I_GPU

PC191

0.1UF/16V

X7R 10%

3

D

I_GPU

PQ237

1

2N7002

G

S

2

GND

12

GND

NI

PC101 1000PF/5 0V

X7R 10%

4

1 2

NI

PC196 47PF/50V

NPO 5%

12

NI

PC195 1500PF/5 0V

X7R 10%

1 2

+0P95V_ GPU_25

I_GPU

PR413 1K

1%

1 2

I_GPU

PR417 1K

1%

1 2

NI

PR454

14.7K

1%

+0P95V_ GPU_R

I_GPU

PU11 LM358

A+

3

VCC

+

A-

AO

2

-

B+

5

+

BO

B-

6

-

GND

NI

PC192 47PF/50V

NPO 5%

12

+1P8V_M XM__FB_R_A

+1P8V_M XM__FB_R1_A +1P8V_M XM_FBR_A

NI

PC197 47PF/50V

NPO 5%

12

8 1

7 4

GND

I_GPU

PC193 1500PF/5 0V

X7R 10%

1 2

NI

PC198 1500PF/5 0V

X7R 10%

1 2

FEEBACK COMPENSATION

GND

3

12

I_GPU

PR416

4.7K

1%

GND

I_GPU

PR288 0

1 2

+19VSB

12

I_GPU

PC174

0.1UF/25V

X7R 10% mx_c0603

GND

+1P8V_M XM_GATE_A

I_GPU

PR415 0

1 2

+0P95V_ GPU_R1

12

GND

1 2

I_GPU

PR262

4.7K

NOBOM

PR120 0

NOBOM

PR275 0

+1P8V_M XM_GATE_R_A

+0P95V_ GPU_R1_25

NOBOM

PJP54 SHORTPIN

1 2

NOBOM

PJP39 SHORTPIN

1 2

2

+1P35V_ GPU

I_GPU

PQ24 BSC889N 03LS

54

876

5 D

S

G

+3P3V

54

G

5 D

GND

123

12

NI

PR273 33

mx_r0603 5%

GND

I_GPU

PQ32 BSC889N 03LS

876

S

GND

123

12

NI

PR281 33

mx_r0603

GND GND G ND

I_GPU

12

PC201 10UF/6.3V

X5R 10% mx_c0805

+0P95V_GPU Imax=6.48A/Tdc=4.56A

P=(1.35-0.95)*6.48=2.592 W

2.592*0.7=1.8144W

1.35-6.48*9m=1.29168V >1.35*0.95=1.2825V

+0P95V_ GPU

I_GPU

12

PC204 10UF/6.3V

X5R 10% mx_c0805

I_GPU

12

PC206 10UF/6.3V

X5R 10% mx_c0805

12

NI

PC205 10UF/6.3V

mx_c0805

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

I_GPU

PCE33 100UF/6.3 V

ESR=15m /Ir=2.7A

GNDGND

+1P8V_MXM Imax:1.94A/TDC=1.29A

P=(3.3-1.8)*1.94=2.91W

2.91*0.7=2.037W

3.3-1.94*9m=3.28254V>3 .3*0.95=3.135V

+1P8V_M XM

I_GPU

PCE34 100UF/6.3 V

ESR=15m /Ir=2.7A

Title :

Engineer:

IMPLP-MS

1

+1P8V & 0P95V_GPU

Stonko_Chen

70 83Thu rsday, June 27, 2013

Rev

A00

5

D D

Vref=3.3*8.45/(8.45+12. 1)=1.3569V

3

D

I_GPU

PQ71

1

GPU_PW R_EN70

C C

PU ON PCH SIDE

GPUPW _EN22 ,51,72

12

NI

PR441 1K

1%

GND GND

B B

GPIO0 GPIO16

0 0

0 1

1 0

1 1

GPIO054

A A

GPIO1654

VDDCI

0.95V

0.9V

0.85V

0.8V

NI

PR430 1K

1 2

NI

PR426 1K

1 2

5

NI

PC194

0.1UF/16V

X7R 10%

1

G

+3P3VSB

12

3

D

S

2

GND

PQ34-P1

12

GND

NI

PR462

8.2K

PQ238-P1

NI

PQ239 2N7002

1

PQ50-P1

NI

PC211

0.1UF/16V

X7R 10%

GND

B

NI

12

PC105

X7R 10%

1000PF/5 0V

3

C

E 2

GND

12

GND

NI

PQ34 PMBS390 4

NI

PC225

0.1UF/16V

X7R 10%

G

GND

1

G

PQ53-P1

1

2N7002

S

2

3

D

NI

PQ242 2N7002

S

2

GND

3

C

B

NI

PQ50

E

PMBS390 4

2

GND

4

FEEBACK COMPENSATION

+3P3V

12

I_GPU

PR440

12.1K

1%

12

GND GND

+3P3V

12

GND

12

I_GPU

PR468

8.45K

1%

NI

PR436 28K

1%

PC356

2.2UF/6.3V

X5R 10% mx_c0603

3.3*8.25/(8.25+28)=0.7 51V

NI

12

PR427

8.25K

1%

+5VSB

GND

12

NI

PR423 10K

12

NI

PC318

0.1UF/16V

X7R 10%

NI

PC224

2.2UF/6.3V

X5R 10% mx_c0603

GND

+5VSB

12

NI

PR431 10K

12

NI

PC226

0.1UF/16V

X7R 10%

GND

4

1

G

NI

PR456

14.7K

1%

1 2

I_GPU

12

PC355 820PF/50 V

X7R 10%

NI

12

PC332

+1P35V_ GPU_C

47PF/50V

12

I_GPU

PR467 15K

1%

+1P35V_ GPU_EN_A

+1P35V_ GPU_R2_A

+VDDCI_EN _A

+VDDCI_FB _A

NI

PR434

14.7K

1%

1 2

3.3*1.2k/(1.2k+1k)=1.8 V

D

S

NI

PR432

7.5K

1%

NI

PQ53 2N7002

12

PQ52-P3

3

1

G

2

GND

12

PQ53-P3

3

2

GND

1 2

NI

PR429 15K

1%

D

NI

PQ52 2N7002

S

NI

PC199 47PF/50V

NPO 5%

12

I_GPU

PR466 1K

+1P35V_ GPU_R

NI

PC209 47PF/50V

NPO 5%

+VDDCI_FB _R_A

12

NI

PR439 15K

1%

GND

NI

PC200 1500PF/5 0V

X7R 10%

1 2

+1P35V_ GPU_25

I_GPU

PU12 LM358

A+

3

+

A-

2

-

B+

5

+

B-

6

-

12

3

1 2

8

VCC

1

AO

BO

7 4

GND

NI

PC210 1500PF/5 0V

X7R 10%

1 2

NI

PR435 1K

1%

1 2

NI

PC319 470PF/50 V

NPO 5%

3

NOBOM

GND

12

I_GPU

PR464

4.7K

1%

I_GPU

PR337 0

GND

+19VSB

12

GNDGN D

+VDDCI_FB _R1_A +VDDCI_FB _R2_A

+VDDCI_FB _R1_A

1 2

+1P35V_ GPU_R1

I_GPU

PC208

0.1UF/25V

X7R 10% mx_c0603

+VDDCI_GA TE_A

12

NI

PR424

4.7K

GND

PR122 0

NI

PR433 0

1 2

NOBOM

PJP56 SHORTPIN

NI

PR123 0

1 2

+VDDC

+1P5V

G

54

5 D

2

I_GPU I_GPU

PQ25 BSC889N 03LS

S

2

12

PC120

10UF/6.3V

X5R 10%

mx_c0805

876

GND

123

+1P35V_ GPU

12

NI

12

PR338

I_GPU

33

PC358

mx_r0603

10UF/6.3V

X5R 10%

mx_c0805

GND

54

G

NI

PJP40 SHORTPIN

1 2

PJP62 1MM_OP EN_M1M2

NOBOM

PJP61 1MM_OP EN_M1M2

NOBOM

NI

PQ33

BSC889N 03LS

876

5 D

S

123

12

GND

GNDGND

NI

PR339 33

mx_r0603

112

1

+1P35V_GPU Imax=8.77A/TDC=6.14A

P=(1.5-1.35)*8.77=1.3155 W

1.3155*0.7=0.9208 5W

1.5-8.77*9m=1.42107V>1 .5*0.95=1.425V

12

I_GPU

+

PCE37 330UF/2V

mx_c7343d _h79

NI

PQ49 BSC889N 03LS

54

5 D

S

G

PR346 0NImx_r1206 PR342 0NImx_r1206 PR343 0NImx_r1206

PR344 0NImx_r1206 PR345 0NImx_r1206 PR371 0NImx_r1206

12

NI

PC316 10UF/6.3V

876

X5R 10% mx_c0805

GND

123

12 12 12

+1P35V_ DUAL+1P5 V

+VDDCI/1.15V Imax=9A/TDC=6A

P=(1.35-1.15)*9=1.8W

1.8*0.7=1.26W

1.35-9*(9m/2)=1.3095V>1.35 *0.95=1.2825V

+VDDCI

12

GND GND

2

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

NI

PC317 10UF/6.3V

X5R 10% mx_c0805

12

GND

IMPLP-MS

I_GPU

PC324 10UF/6.3V

X5R 10% mx_c0805

12

+

I_GPU

PCE8 330UF/2V

6m

Title :

Engineer:

1

1P35VGPU&VDDCI

Stonko_Chen

71 83Thu rsday, June 27, 2013

Rev

A00

5

4

3

2

1

I_GPU

PR305

2.2

mx_r0603_small

1 2

+VDDC_V CC_C

D D

C C

1 2

PR129 0

NI

I_GPU

PR324 1K

1%

1 2

PQ27-P1

12

NI

PC236

0.1UF/16V

X7R 10%

+VDDC_V IN

GPUPW _EN22 ,51,71

CTF54

NVVDD_P WRGD69,70

DGPU_PW ROK23

B B

+3P3V

I_GPU

PR328 1

1 2

I_GPU

PR307

7.5K

1%

1 2

I_GPU

PR309 24K

1%

1 2

NI

PR312 10K

1%

1 2

+3P3V

1

G

PR320 0

PR852 0

I_GPU

+VDDC_N TC_A

1 2

PR308 10K 1%

I_GPU

12

I_GPU

PR310 10K

1%

3

D

S

2

GNDGND

1 2

PC229 0.1UF/16 V X7R 10%

NI

1 2

PR311 10K 1%

I_GPU

1 2

PR315 0

I_GPU

NI

PQ27 2N7002

I_GPU

PR329 150K

1%

1 2

PC239 0.1U F/16V X7R 10%

VDDC VID TABLE (0.95V)

VID4 VID3 VID2 VID1VID5

30 29 20 15

6

GPIO

H L H H L

Level

1 2

PR94 0

GPIO654 GPIO3054 GPIO2954 GPIO2054 GPIO1554

A A

GPIO554

I_GPU

PR95 0

I_GPU

PR96 0

I_GPU

PR97 0

I_GPU

PR98 0

I_GPU

PR99 0

NI

5

1 2 1 2 1 2 1 2 1 2

12

GND

NI

PR351

PR349

1K

12

I_GPU

PR357

PR356

1K

GND GND GND GND GND GND

12

I_GPU

PR352 1K

NI

PR358 1K

12

I_GPU

NI

PR353

PR354

1K

12

NI

I_GPU

PR359

PR360

1K

4

+VDDC_V CC_C+5V

+VDDC_O CSET_A

PU13_DP RSLPVR_A

+VDDC_E N_A

+3P3V

12

I_GPU

PR319 10K

+VDDC_P GOOD_A

12

NI

PR321 10K

GND GND

+VDDC_T ON_A+VDDC_T ON_L_A

+3P3V+3P3V+3P3V+3P3V+3P3V+3P3V+3P3V

12

I_GPU

PR355 1K

12

NI

PR361 1K

12

I_GPU

PC228

2.2UF/6.3V

X5R 10% mx_c0603

GND

12

I_GPU

PC231 1000PF/5 0V

X7R 10%

GND

12

I_GPU

PC234

0.1UF/16V

X7R 10%

12

NI

PR350 1K

+VDDC_V ID6 +VDDC_V ID5 +VDDC_V ID4 +VDDC_V ID3 +VDDC_V ID2 +VDDC_V ID1 +VDDC_V ID0

12

I_GPU

PR362 1K

GND

I_GPU

PU13A RT8153C LGQW

7

VCC

1

NTC/OLL

2

OCSET

3

DPRSLPVR

4

VRON

5

PGOOD

6

CLKEN#

17

TON

32

VRTT#

25

VID6

26

VID5

27

VID4

28

VID3

29

VID2

30

VID1

31

VID0

33

GND

PVDD

BOOT

PHASE

UGATE

LGATE

PGND

ISEN

ISEN_N

COMP

VSEN

CMSET

CM/PM

RGND

SOFT

DPRSTP#/OFS

GND8 GND7 GND6 GND5 GND4 GND3 GND2 GND1

I_GPU

PU13B RT8153C LGQW

3

+5V

19

12

I_GPU

PC227

2.2UF/6.3V

X5R 10% mx_c0603

GND

24

+VDDC_B OOT_C +VDDC_BO OT_RC_C

22

23

20

21

GND

16

+VDDC_ISE N_A

15

14

+VDDC_C OMP_A

13

+VDDC_F B_A

FB

12

+VDDC_V SEN_A

11

+VDDC_C MSET_A

10

+VDDC_C M_A

9

+VDDC_R GND_A

8

+VDDC_S OFT_A

18

+VDDC_O FS_A

41 40 39 38 37 36 35 34

GND

I_GPU

PR306

2.2

mx_r0603

1 2

I_GPU

PR325 10K 1%

I_GPU

PRT2 10K 1%

I_GPU

PC240 0.01 UF/25V X7R 10%

NI

PR334 20K 1%

I_GPU

PR100 56.2 K

I_GPU

PC244 0.02 2UF/25V X7R 10 %

I_GPU

PC245 0.01 UF/25V X7R 10%

I_GPU

PC246 100 PF/50V NPO 5%

NI

GND

I_GPU

PC235 47PF/50V

NPO 5%

+VDDC_C OMP1_A

PR326 33 .2KOHM

1 2

12

PR347

30.9KOhm

I_GPU

PR348 10KOhm

I_GPU

PC230

0.1UF/25V

X7R 10% mx_c0603

1 2

+VDDC_F B_R1_A

1%

+VDDC_V CC_C

2

12

I_GPU

PR388

8.2K

1%

I_GPU

PC238 220PF/50 V

X7R 10%

1 2

GND

I_GPU

PR330

5.1K

1%

12

+VDDC_P HASE_C 73

+VDDC_U G_D 73

+VDDC_L G_D 73

I_GPU

PR313

8.2K

1%

NI

PC241

1000PF/5 0V

X7R 10%

NI

PC247

1000PF/5 0V

X7R 10%

I_GPU

12

NI

PC242

0.1UF/16V

X7R 10%

12

I_GPU

PC232

0.1UF/16V

X7R 10%

12

I_GPU

PC233

0.1UF/16V

X7R 10%

GND

1 2

I_GPU

PR333

0

PR335

1 2

0

1 2

+VDDC_V SEN_R_A

+VDDC_R GND_R_A

12

NI

PC243

0.1UF/16V

X7R 10%

+VDDC_ISE N+_A 73

+VDDC_ISE N-_A 73

PEGATRON DT-MB RESTRICTED SECRET

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

Engineer:

IMPLP-MS

1

NOBOM

PJP30 SHORTPIN

1 2

NOBOM

PJP31 SHORTPIN

1 2

VDDC CONTROLLER

Stonko_Chen

72 83Thu rsday, June 27, 2013

+VDDC

GND

Rev

A00

5

4

3

2

1

+VDDC_V IN

PJP34 1MM_OP EN_M1M2

NOBOM

I_GPU

PU37A FDMS360 0AS

D D

1 2

PR363 1

+VDDC_U G_D72

+VDDC_L G_D72

C C

I_GPU

1 2

PR387 0

I_GPU

12

NI

PC95 1000PF/5 0V

MLCC/+/-10 %

GND

mx_r0603

+VDDC_U GR_D

+VDDC_L GR_D

12

I_GPU

PR364

8.2K

I_GPU

X7R/+/-10%

GND

PC89 2200PF/5 0V

4 D1

3 D1

D1

2

G1

1

I_GPU

PU37B FDMS360 0AS

17

PHASE(S1/D2)

GND GND

S2

5

S2

6

S2

7

G2

8

9

I_GPU

PU38B FDMS360 0AS

PHASE(S1/D2)110PHASE(S1/D2)211PHASE(S1/D2)312PHASE(S1/D2)413PHASE(S1/D2)514PHASE(S1/D2)615PHASE(S1/D2)716PHASE(S1/D2)8

17

Close to PU37A PIN4Close to PU38A PIN8

+VDDC_P HASE_C72

I_GPU

PU38A FDMS360 0AS

4 D1

3 D1

D1

2

G1

1

12

PHASE(S1/D2)110PHASE(S1/D2)211PHASE(S1/D2)312PHASE(S1/D2)413PHASE(S1/D2)514PHASE(S1/D2)615PHASE(S1/D2)716PHASE(S1/D2)8

GND

PHASE(S1/D2)

I_GPU

PC248 1000PF/5 0V

X7R 10% mx_c0603_ small

+VDDC_S N

I_GPU

PR365 1

mx_r1206

+VDDC_ISE N+_A7 2 +VDDC_ISE N-_A72

S2

5

S2

6

S2

7

G2

8

9

12

GND

12

I_GPU

PC88 1000PF/5 0V

MLCC/+/-10 %

GND

Close to PU37A PIN2

I_GPU

PC249 680PF/50 V

X7R 10%

NOBOM

PJP35 SHORTPIN

1 2

12

GND

I_GPU

PL58

0.36UH

1mOhm/Imax=38.8 A GPU

PJP33 1MM_OP EN_M1M2

NOBOM

PJP32 1MM_OP EN_M1M2

NOBOM

I_GPU

PC282 10UF/25V

X5R 10% mx_c0805_ small

21

NOBOM

PJP36 SHORTPIN

1 2

12

+

112

I_GPU

PCE19 330UF/2V

6mohm

2

12

I_GPU

+

PCE20 330UF/2V

6mohm

+19VSB

+VDDC Imax=37.5A/TDC=25A GPU=37.5A

+VDDC

I_GPU

PCE21 330UF/2V

6mohm

12

+

12

+

GNDGNDGND GND G ND

NI

PCE23 330UF/2V

6mohm

12

I_GPU

+

PCE22 220UF/2V

ESR=9m/Ir=3A

B B

A A

+VDDC

12

I_GPU

PC250 22UF/6.3V

X5R 20% mx_c0805_ small

I_GPU

12

PC251 22UF/6.3V

X5R 20% mx_c0805_ small

I_GPU

12

PC252 22UF/6.3V

X5R 20% mx_c0805_ small

I_GPU

12

PC253 22UF/6.3V

X5R 20% mx_c0805_ small

GND

+VDDC

On Top Socket Cavity

I_GPU

12

PC254 22UF/6.3V

X5R 20% mx_c0805_ small

I_GPU

12

PC255 22UF/6.3V

X5R 20% mx_c0805_ small

GND

+VDDC

12

I_GPU

PC256 22UF/6.3V

X5R 20% mx_c0805_ small

On Bottom Socket eadgeOn Top Socket eadge On Bottom Socket Cavity

I_GPU

12

PC257 22UF/6.3V

X5R 20% mx_c0805_ small

I_GPU

12

PC258 22UF/6.3V

X5R 20% mx_c0805_ small

I_GPU

12

PC259 22UF/6.3V

X5R 20% mx_c0805_ small

GND

+VDDC

12

I_GPU

PC260 22UF/6.3V

X5R 20% mx_c0805_ small

I_GPU

12

PC261 22UF/6.3V

X5R 20% mx_c0805_ small

GND

PEGATRON DT-MB RESTRICTED SECRET

+VDDC CAP

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

IMPLP-MS

+VDDC CAP

Stonko_Chen

73 83Thu rsday, June 27, 2013

1

73 83Thu rsday, June 27, 2013

Rev

A00

5

+3P3V

D D

12

Vref=3.3*10/(17.4+10)=1.2 04V

3

D

I

PQ38

1

2N7002

G

S

2

GND

C C

+3P3VSB

+1P5V

12

I

PR327 1K

1%

PQ36_1_ A

12

I

PC277

0.1UF/16V

X7R 10%

B B

12

I

PR340 10K

3

C

B

1

I

PQ36

E

PMBS390 4

2

GNDGND

3.3*10k/(10k+21.5k)=1 .0476V

PQ37_1_ A

12

NI

PC340

0.1UF/16V

X7R 10%

GND

3

D

I

PQ37

1

2N7002

G

S

2

GND

12

GND GND

+3P3V

12

GND

I

PR407

17.4K

1%

I

PR448 10K

1%

I

PR453

21.5K

1%

I

PR444 10K

1%

12

GND

4

I

PC329

2.2UF/6.3V

X5R 10% mx_c0603

I

PC323

2.2UF/6.3V

X5R 10% mx_c0603

NI

12

PC341 47PF/50V

+1P2V_R EF

+1P2V_1 0

+1P05V_ PCH_REF

+1P05V_ PCH__FB_A

12

NI

PC320 47PF/50V

NPO 5%

NI

PR476

14.7K

1%

1 2

NI

PR457

14.7K

1%

1 2

3

2

5

6

NI

PC223 47PF/50V

NPO 5%

NI

PC219 47PF/50V

NPO 5%

12

I

12

PC325 680PF/50 V

X7R/+/-10%

+1P2V_S N

12

I

PR458 11K

1%

I

PU16 LM358

A+

8

VCC

+

1

A-

AO

-

B+

+

BO

7

B-

4

-

GND

+1P05V_ PCH_GATE_A

I

12

PC321 680PF/50 V

X7R/+/-10%

+1P05V_ PCH_C

12

I

PR451

14.7K

1%

1 2

12

NI

PC220 1500PF/5 0V

X7R 10%

1 2

3

NI

PC217 1500PF/5 0V

X7R 10%

1 2

GND

+1P2V_2 5

12

I

PR449

4.7K

1%

GND

I

PR408

4.7K

1 2

I

PR446 0

1 2

NOBOM

PR428 0

1 2

I

PR450 0

I

PR447 1K

I

PR452 1K

1%

1 2

+1P2V_R

+19VSB

12

I

PC218

0.1UF/25V

X7R 10% mx_c0603

GND

12

GND

+1P05V_ PCH__FB_R1_A +1P05V_ PCH_FBR_A

NOBOM

PR455 0

1 2

+1P2V_R 1_B

+1P05V_ PCH_GATE_R_A

+1P2V_R 2_25

1 2

NOBOM

PJP55 SHORTPIN

NOBOM

PJP41 SHORTPIN

1 2

2

+1P5V

I

PQ58 IRF8707PB F

11.9m@10 V

567

G

4

I

PQ56 BSC889N 03LS

9m@10V

54

5 D

S

G

GND

8

SD

123

12

876

123

NI

PR443 33

mx_r0603

12

I

PC322 10UF/6.3V

X5R 10% mx_c0805

GND

+1P2V Imax=0.714A/Tdc=0.5A

P=(1.5-1.2)*0.714=0.2142 W

0.2142*0.7=0.1499 4W

1.5-0.714*11.9m=1.491 5034V>1.5*0.95=1.4 25V

12

I

PQ65 BSC889N 03LS

9m@10V

54

5 D

S

G

123

12

GND G ND GND

I

PC326 10UF/6.3V

X5R 10% mx_c0805

876

NI

PR445 33

mx_r0603

GNDGND

12

I

PCE35 22UF/16V

X5R 20% mx_c1206

+1P5V

12

GND

12

1

+1P2V

12

I

PCE38 22UF/16V

X5R 20% mx_c1206

GND

I

PC327 10UF/6.3V

X5R 10% mx_c0805

+1P05V_PCH Imax:8.46A/TDC=5.921A

P=(1.5-1.05)*8.46=3.807W (3.807/2)*0.7=1.9035W

1.5-8.46*9m=1.46193V>1 .5*0.95=1.425V

+1P05V_ PCH

12

+

I

PC328 10UF/6.3V

X5R 10% mx_c0805

I

PCE10 330UF/2V

6m/3A

A A

5

4

GND

PEGATRON DT-MB RESTRICTED SECRET

+1P2V & +1P8V_MXM

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

3

2

Date: Sheet of

IMPLP-MS

Engineer:

1

Stonko_Chen

74 83Thu rsday, June 27, 2013

Rev

A00

5

I

+5VSB_IN

D D

+5VA IMAX=0.1A TDC=0.07A

+3P3VA IMAX=0.101A TDC=0.0707A

C C

GND

+5VA

GND

+3VA

GND

+5VSB_Fsw=300K +3V3PSB Fsw=350K

PR54

2.2

mx_r0603_small

1 2

12

I

PC33

0.1UF/16V

X7R 10%

12

PC35 1UF/10VImx_c0603_ small

12

I

PC39 1UF/16V

X7R 10% mx_c0603

+5V_3V_ VIN

X7R 10%

+3P3VSB

12

NI

PR59 10K

I

PU7 TPS5122 5CRUKR

12

VIN

13

VREG5

3

VREG3

7

PGOOD

4

VBST1

DRVH1

SW1

DRVL1

VO1

17

16

18

15

14

+5VSB_B ST

+5VSB_H G

+5VSB_P HASE

+5VSB_L G

+5VSB_V O

GND

I

PR55 0

mx_r0805

1 2

I

PR87 0

mx_r0805

1 2

Fsw=300KHz@5V Iin=3.963A Iin,rms5.67A delta I=3.72A ESR=55mOhm OCP=17.92A@MAX*1.4 times H/S：0.763W( BSC090 9NS *1) L/S：1.681W ( BSC09 09NS *1)

I

+5VSB_B ST1

+5VSB_R 1_HG

PC42 0.1 UF/16V X7R 10%

12

3

I

PC34

0.1UF/25V

X7R 10% mx_c0603

1 2

I

PR56 0

mx_r0805

1 2

NI

GND

Close to PQ62 PIN4

12

I

PR57

8.2K

54

G

+5VSB_R 1_LG

12

PC92 1000P F/50V

1 2

PR60 1Imx_r0603_small

5 D

S

+5VSB_IN

G

I

876

PQ62 BSC889N 03LS

Id=45A/Pd= 28W 9m@10V

123

54

5 D

S

123

12

876

GND

I

PQ61 BSC889N 03LS

I

PC40

4.7UF/25V

X5R 10% mx_c0805

12

I

PR58 1

mx_r1206

+5VSB_S N

12

I

PC41 1000PF/5 0V

X7R 10% mx_c0603_ small

GNDGN D

2

12

GND G ND GND

I

PL8

4.7UH

13.1m/13.2 A

11.2*10*4

I

PC44

4.7UF/25V

X5R 10% mx_c0805

21

12

GND

+

I

PCE14 100UF/6.3 V

55m/1.2A

12

I

PC68

4.7UF/25V

X5R 10% mx_c0805

12

I

PC69

4.7UF/25V

X5R 10% mx_c0805

12

I

PC43 10UF/6.3V

X5R 10% mx_c0805_ small

1

+19VSB

2 1

180Ohm/1 00Mhz

mx_l0805_h43

180Ohm/1 00Mhz

mx_l0805_h43

180Ohm/1 00Mhz

mx_l0805_h43

GND

12

I

PC353

0.1UF/25V

X5R 10%

I

PL51

I

PL52

I

PL53

+5VSB(Imax=0.5A) Imax=12.8A/TDC=6.3364A (0.351A+5VA+5V_DUAL+5V) (0.5+0.001+9.3+3=12.8A

I

PC74 10UF/6.3V

X5R 10% mx_c0805_ small

GND

+5VSB_V O1

12

+

I

PCE39 100UF/6.3 V

55m/1.2A

12

GNDGND

NOBOM

PJP42 SHORTPIN

+5VSB

12

GND

12

NOBOM

PJP43 SHORTPIN

NI

PC447 22UF/25V

X5R 10% mx_c1206

19

VCLK

OCP_5V=12.8*1.4=17.92A delta I=3.72A, Rds(on)=9mOhm, Vtrip=(17.92-3.72/2)*8*8m=1.156269V Rtrip=Vtrip/Itrip=1.156269/10*10^-6=115.6K

OCP_3V=8.325*1.4=11.655A delta I=2.33A, Rds(on)=9m Vtrip=(11.655-2.33/2)*8*9m=0.755365V Rtrip=Vtrip/Itrip=0.755365/10*10^-6=75.5K

B B

SLP_SUS #19,36

A A

GND

I

PR69 10K

1 2

NI

PR70 10K

1 2

5

I

PR65 120K

1%

1 2

I

PR66 82K

1%

1 2

12

I

PC50

0.1UF/16V

X7R 10%

GND

+3P3VSB _EN

12

NI

PC52

0.1UF/16V

X7R 10%

GND

+5VSB_C S

+3P3VSB _CS

12

I

SR358 0

GND

1

CS1

5

CS2

20

EN1

6

EN2

21

GND0

22

GND1

23

GND2

VFB1

VBST2

DRVH2

SW2

DRVL2

VFB2

4

2

+5VSB_F B

9

+3P3VSB _BST

10

+3P3VSB _HG

8

+3P3VSB _PHASE

11

4

+3P3VSB _FB

GND

+3P3VSB _LG

GND

PR62 10K 1%

I

PR64 0

mx_r0805

1 2

I

PR88 0

mx_r0805

1 2

Fsw=355KHz@3V Iin=1.7011A Iin,rms3.16A delta I=2.33A ESR=55mOhm OCP=11.655A@MAX*1.4 times H/S：0.347W( BSC090 9NS *1) L/S：1.082W ( BSC09 09NS *1)

12

+3P3VSB _BST1

+3P3VSB _R1_HG

GND

12

I

PR72 10K

(+3P3VSB+3P3VA+3P3V+3P3V_GPU+1P8V_MXM)

1%

(3.72+0.023+2.552+0.09+1.94=8.325A)

PR63 15.4KI1%

PC45 56PF/5 0V N PO 5%

NI

I

PC48

0.1UF/25V

X7R 10% mx_c0603

1 2

12

I

PR76 0

mx_r0805

1 2

PC93 1000P F/50V

NI

+3P3VSB _R1_LG

12

Close to PQ60 PIN4

PC53 56PF/5 0V N PO 5%

NI

3

I

PR67

8.2K

12

+3P3VSB _IN

I

PR71

6.49K

1%

12

GND

I

PC47

4.7UF/25V

X5R 10% mx_c0805

GND

12

I

PR68 1

mx_r1206

12

I

PC51 1000PF/5 0V

X7R 10% mx_c0603_ small

GND

2

54

876

5 D

S

G

123

I

PQ59 BSC889N 03LS

54

5 D

S

G

12

GND G ND GND GND GND

I

876

PQ60 BSC889N 03LS

Id=45A/Pd= 28W 9m@10V

123

GND

NI

PC46

0.1UF/16V

X7R 10%

I

PC70

4.7UF/25V

X5R 10% mx_c0805

I

PL9

3.3UH/6/13 .5A

28mOhm/Isat=13 .5A

7.3*6.6*3

+3P3VSB _SN+5VSB_E N

NI

PC54

0.1UF/16V

X7R 10%

12

I

PC71

4.7UF/25V

X5R 10% mx_c0805

I

PC72

4.7UF/25V

X5R 10% mx_c0805

21

12

I

PC49 10UF/6.3V

X5R 10% mx_c0805_ small

GND GND

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

+5VSB_F B1

2 1

180Ohm/1 00Mhz

mx_l0805_h43

180Ohm/1 00Mhz

mx_l0805_h43

12

I

PL55

I

PL54

+3P3VSB(I=3.72A) Imax=8.325A/TDC=5.8275A

12

I

PC75 10UF/6.3V

X5R 10% mx_c0805_ small

GND

+3P3VSB _FB1

12

+

IMPLP-MS

I

PCE11 100UF/6.3 V

55m/1.2A

Title :

Engineer:

1

12

I

+

PCE15 100UF/6.3 V

55m/1.2A

GND

3&5VA 3&5VSB

Stonko_Chen

75 83Thu rsday, June 27, 2013

+19VSB

I

PC73

0.1UF/25V

X5R 10%

+3P3VSB

12

NI

PC448 22UF/25V

X5R 10% mx_c1206

GND

NOBOM

PJP44 SHORTPIN

Rev

A00

5

+3P3V

+5V

D D

+3P3V

12

VRM_PW RGD1 9,50

C C

I

PR302

1.54K

1%

1 2

B B

+VCORE

VCC_SEN SE12

VSS_SEN SE14

A A

GND

5

+3P3V +1P05V_PC H

I

PR263 2K

GND

PR283 0

I

PR276 0

I

PLACE CLOSE TO CPU SOCKET

+19VSB_ CORE7 7

I

NI

I

PR314 10K

1%

I

PR264 10KI1%

PR282 0

NI

PR280 39K 1%

I

PRT10 100K 1%

I

PR293 9.09 K 1%

I

PC262 0.1U F/16VIX7R 10%

PR290 61.9 KNI1%

PR296 150 K 1 %

I

PR297 150 KI1%

PR292 75KI1%

PR300 169 K 1 %

I

PR291 150 KI1%

NOBOM

PJP46 SHORTPIN

1 2

NOBOM

PJP45 SHORTPIN

1 2

PR255 2.2Imx_r0603_small

1 2

PR256 2.2Imx_r0603_small

1 2

PR260 2K

1 2

PR259 2K

12

PC269 100 PF/50V

12

1 2

12

1 2

12

1 2

12

1 2

12

1 2

12

VRM_FB-_ A VRM_GFB_A

1 2

I

PC354 330PF/50 V

X7R 10%

12

I

PR303 100

1%

1 2

I

PR277 100

1%

4

I

PR258 10K

1%

4

12

I

PC213 1UF/16V

X7R 10% mx_c0603

GND

VRM_VBA T_A

VRM_EN_ A

12

I

PC216

0.1UF/16V

X7R 10%

VRM_DRO OP_A

VRM_COM P_A

VRM_VRE F_A

VRM_SLE WA_A

VRM_THE RM_A

VRM_B-RA MP_A

VRM_F-IMAX _A

VRM_O-US R_A

VRM_VFB _AVRM_FB+ _A

VRM_VDD _C

VRM_V5A _C

12

I

PC214 1UF/16V

X7R 10% mx_c0603

GND

12

I

PC215

0.1UF/16V

X7R 10%

GNDGND

12

I

PC272

0.33UF/10 V

X5R 10% mx_c0603

GND

I

PU33 TPS5163 1RSM

2

VDD

28

V5A

16

VBAT

8

VR_ON

3

PGOOD

25

DROOP

26

COMP

27

VREF

15

SLEWA

14

THERM

11

B-RAMP

10

F-IMAX

9

O-USR

24

VFB

23

GFB

VCLK

ALERT#

VDIO

VR_HOT#

SKIP#

PWM1 PWM2 PWM3

CSP1

CSN1

CSP2

CSN2

CSP3

CSN3

OCP-I

IMON

GND1 GND2 GND3 GND4 GND5 GND6

3

+1V_CPU IOOUT

12

I

PR251

54.9

1%

31

VRM_SCL K_A

32

VRM_ALE RT#_A

1

VRM_SDA _A

30

7

6 5 4

12

NI

PR265 0

GND

17

18

20

19

21

22

12

VRM_OCP -I_A

13

VRM_IMON_ A

29 33 34 35 36 37

GND

3

VRM_CSP 1_A

1 2

PR268 3.01 KI1%

VRM_CSP 2_A

1 2

PR272 3.01 KI1%

VRM_CSP 3_A

1 2

PR285 3.01 KI1%

I

12

PC268 4700PF/5 0V

NPO 10%

12

I

NI

PR253

PR254

130

56

1%

VRM_PW M1 7 7 VRM_PW M2 7 7 VRM_PW M3 7 8

1 2

PC270 0.1U F/25V X7R 10%

I

VRM_CSP 1_NTC_A

1 2

PR269 20KI1%

1 2

PC271 0.1U F/25V X7R 10%

I

VRM_CSP 2_NTC_A

1 2

PR274 20KI1%

PC221 0.1U F/25V X7R 10%

I

VRM_CSP 3_NTC_A

PR284 20KI1%

1 2

I

PR295

69.8K

1%

12

GND

I

PR267

2.32K

1%

1 2

I

PR331

2.32K

1%

1 2

I

PR279

2.32K

1%

1 2

12

GNDGND

2

NI

PC212

0.1UF/16V

X7R 10%

I

PR294 75K

1%

2

1 2

PR266 0

I

1 2

PR270 0

I

1 2

PR257 0

I

12

I

HR133 47PF/50V

NPO 5%

GND

mx_c0603

1 2

PRT7 10K 1%

I

mx_c0603

1 2

PRT8 10K 1%

I

mx_c0603

1 2

PRT9 10K 1%

I

1

VIDSCLK 12

VIDALERT# 12

VIDSOUT 12

PROCHOT # 9,64

VRM_SKIP# 77,78

HR133 mitigate the undershoots on Prochot signal.

VRM_CSP 1 77

VRM_CSN 1 77

VRM_CSP 2 77

VRM_CSN 2 77

VRM_CSP 3 78

VRM_CSN 3 78

PEGATRON DT-MB RESTRICTED SECRET

VCORE CONTROLLER

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

IMPLP-MS

Engineer:

1

Stonko_Chen

76 83Thu rsday, June 27, 2013

Rev

A00

5

4

3

2

1

+Vcore Imax=85A/TDC=27A Fsw=800KHz CSD97374CQ4M * 3

Fsw=800KHz Vo,boot=1.7V Imax=85A Iin=8.94 7A Iin,rms12.63A delta I=8.06A ESR=6mOhm OCP=102A@MAX*1.2 times H/S：0.742W( CSD8738 4 *1) L/S：1.796W ( CSD873 84 *1)

I

PL27

0.24uH

1.19mOhm /Isat=30A

7.05*6.6*2.8

21

12

NOBOM

PJP50 SHORTPIN

12

NOBOM

PJP48 SHORTPIN

+VCORE

12

I

PC275

0.1UF/16V

X7R 10%

GND

VSW

BOOT

PGND7 PGND8

PGND9 PGND10 PGND11

VIN

+VCORE_ IN

5

4

6

7

VRM_BST 1_RC_C

14 15 16 17 18

GND

+VCORE_ IN

12

GND

I

PC102 1000PF/5 0V

X7R 10%

GND

12

I

PC338 10UF/25V

X5R 10% mx_c0805

Close to PU26 PIN5

PR366 2.2Imx_r0603

PC274 0.1UF /25VIX7R 10% m x_c060 3

12

1 2

I

PC283 10UF/25V

X5R 10% mx_c0805

12

I

PC278 10UF/25V

X5R 10% mx_c0805

12

GND

VRM_BST 1_L1_RC_CVRM_BST 1_R1_RC_C

I

PC85

0.01UF/25 V

MLCC/+/-10 %

I

PL24

I

PL25

I

PL26

2 1

12

GND

150Ohm/1 00Mhz/5A

mx_l1812_h67

150Ohm/1 00Mhz/5A

mx_l1812_h67

150Ohm/1 00Mhz/5A

mx_l1812_h67

VRM4_SW 1_R

NI

PR370 1

mx_r1206

VRM4_SN 1_C

NI

PC281 1000PF/5 0V

X7R 10% mx_c0603

VRM_CSP 176 VRM_CSN 176

12

GND

NI

PC280 680PF/50 V

X7R 10%

+19VSB

12

GNDGNDGND

I

PC337

0.1UF/25V

X5R 10%

GND

NOBOM

PJP51 SHORTPIN

1 2

I

PU26A CSD9737 4Q4M

2

VDD

8

PWM

1

SKIP#

3

PGND1

9

PGND2

10

PGND3

11

PGND4

12

PGND5

13

PGND6

I

PU26B CSD9737 4Q4M

BOOT_R

D D

+19VSB_ CORE7 6

+5V

VRM_PW M176

VRM_SKIP#76,77 ,78

12

I

PC357

0.1UF/16V

X7R 10%

C C

GND

12

I

PC80 1000PF/5 0V

MLCC/+/-10 %

+5V

B B

VRM_PW M276

VRM_SKIP#76,77 ,78

12

I

PC273

0.1UF/16V

X7R 10%

GND

A A

5

GND

I

PU28A CSD9737 4Q4M

2

VDD

8

PWM

1

SKIP#

3

PGND1

9

PGND2

10

PGND3

11

PGND4

12

PGND5

13

PGND6

I

PU28B CSD9737 4Q4M

VSW

BOOT_R

BOOT

PGND7

PGND8

PGND9 PGND10 PGND11

4

VIN

5

4

6

7

VRM_BST 2_RC_C

14 15 16 17 18

GND

Close to PU28 PIN5

12

I

PC77 10UF/25V

X5R 10% mx_c0805_ small

1 2

PR367 2.2Imx_r0603

PC334 0.1U F/25VIX7R 10% m x_c060 3

12

I

PC78 10UF/25V

X5R 10% mx_c0805_ small

3

12

I

PC335 10UF/25V

X5R 10% mx_c0805

GNDGND GNDGND

VRM_SW 2_R

VRM_BST 2_L1_RC_CVRM_BST 2_R1_RC_C

12

GND

I

PR369 1

mx_r1206

VRM_SN2 _C

I

PC333 1000PF/5 0V

X7R 10% mx_c0603

12

I

PC276 680PF/50 V

X7R 10%

GND

VRM_CSP 276 VRM_CSN 276

2

I

PL28

0.24uH

1.19mOhm /Isat=30A

7.05*6.6*2.8

21

12

NOBOM

PJP47 SHORTPIN

PEGATRON DT-MB RESTRICTED SECRET

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

12

NOBOM

PJP49 SHORTPIN

IMPLP-MS

+VCORE

12

I

PC336

0.1UF/16V

X7R 10%

GND

Title :

Engineer:

1

VCORE DRIVER

Stonko_Chen

77 83Thu rsday, June 27, 2013

Rev

A00

5

D D

4

+VCORE_ IN

3

2

1

12

I

PC84 1000PF/5 0V

MLCC/+/-10 %

+5V

C C

VRM_PW M376

VRM_SKIP#76,77

12

I

PC297

0.1UF/16V

X7R 10%

GND

I

PU30A CSD9737 4Q4M

2

VDD

8

PWM

1

SKIP#

3

PGND1

9

PGND2

10

PGND3

11

PGND4

12

PGND5

13

PGND6

I

PU30B CSD9737 4Q4M

VSW

BOOT_R

BOOT

PGND7 PGND8

PGND9 PGND10 PGND11

VIN

5

4

6

7

VRM_BST 3_RC_C

14 15 16 17 18

GNDGND

Close to PU30 PIN5

Output CAP

B B

330 UF * 2

12

I

PC82 10UF/25V

X5R 10% mx_c0805_ small

GND G NDGND GND

1 2

PR376 2.2Imx_r0603

PC302 0.1U F/25VIX7R 10% m x_c060 3

12

I

PC83 10UF/25V

X5R 10% mx_c0805_ small

12

I

PC300 10UF/25V

X5R 10% mx_c0805

I

PL29

0.24uH

1.19mOhm /Isat=30A

7.05*6.6*2.8

VRM_SW 3_R

VRM_BST 3_L1_RC_CVRM_BST 3_R1_RC_C

12

GND

NI

PR380 1

mx_r1206

VRM_SN3 _C

NI

PC296 1000PF/5 0V

X7R 10% mx_c0603

12

NI

PC295 680PF/50 V

X7R 10%

GND

VRM_CSP 376 VRM_CSN 376

12

NOBOM

PJP53 SHORTPIN

21

12

NOBOM

PJP52 SHORTPIN

+VCORE

12

GND

I

PC298

0.1UF/16V

X7R 10%

22 UF * 30 pcs had checked with vendor put in page12

A A

PEGATRON DT-MB RESTRICTED SECRET

VCORE OUTPUT CAP

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

5

4

3

2

Date: Sheet of

IMPLP-MS

Engineer:

1

Stonko_Chen

78 83Thu rsday, June 27, 2013

Rev

A00

5

MAIN POWER DISCHARGE

4

3

2

1

D D

NI

PR643 0

1 2

C C

5V_DIS

+5V

12

NI

PR846 330

mx_r0603

5V_DIS_R

3

D

NI

PQ257

1

2N7002

G

S

2

GND

PSON#36 ,66,79PSON#36 ,66,79

NI

PR640 0

1 2

3P3V_DIS

DUAL POWER DISCHARGE

+5VSB

B B

1 2

PR851 10K

SLP_S4#19,36,66,67

NI

12

PC146 1000PF/5 0V

X7R 10%

SLP_S4# _R

12

NI

PR174 10K

3

D

NI

PQ227

1

2N7002

G

S

2

DUAL_PW R_DIS

NI

12

PC362 1000PF/5 0V

X7R 10%

NI

PR641 0

1 2

5VDUAL_ DIS

+3P3V

12

NI

PR849 330

mx_r0603

3P3V_DIS_ R

3

D

1

G

S

2

GND

+5V_DUAL

12

NI

PR850 330

mx_r0603

5VDUAL_ DIS_R

3

D

1

G

S

2

GND

+1P35V_ DUAL

NI

PQ254 2N7002

NI

PQ255 2N7002

GNDGNDGND

NI

A A

5

4

3

PR646 0

1 2

1P35VDU AL_DIS

12

NI

PR847 330

mx_r0603

1P35VDU AL_DIS_R

3

D

1

G

S

2

GND

NI

PQ262 2N7002

PEGATRON DT-MB RESTRICTED SECRET

DISCHARGE

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

2

Date: Sheet of

IMPLP-MS

Engineer:

1

Stonko_Chen

79 83Thu rsday, June 27, 2013

Rev

A00

5

4

3

2

1

+19VSB

1

T91

NOBOM

1

T93

NOBOM

1

T92

NOBOM

1

T94

NOBOM

1

T95

NOBOM

D D

C C

B B

+19V_BL

1 1

+19V

1

+VCORE

1 1 1 1 1

+1P5V

1

+1P35V_ GPU

1 1 1 1 1

+1P2V

1

+1P05V_ PCH

1 1 1 1 1

+1P35V_ DUAL

1 1 1 1 1

+VDDCI

1 1 1 1 1

T96 T97

T98

T99 T100 T101 T102 T103

T104

T105 T106 T107 T108 T109

T110

T111 T112 T113 T114 T115

T116 T118 T117 T120 T119

T122 T123 T124 T125 T126

NOBOM NOBOM

NOBOM

NOBOM NOBOM NOBOM NOBOM NOBOM

NOBOM

NOBOM NOBOM NOBOM NOBOM NOBOM

NOBOM

NOBOM NOBOM NOBOM NOBOM NOBOM

+0P95V_ GPU

1 1 1 1 1

+5VSB

1

+3P3VSB

1 1 1

+5VA

1

+3VA

1

+3P3V

1 1

+3P3V_G PU

1

+1P8V_M XM

1 1

+5V_DUA L

1 1 1 1 1

+VDDC

1 1 1 1 1

T127 T128 T129 T130 T131

T132

T133 T134 T135

T138

T139

T140 T141

T142

T143 T144

T147 T148 T149 T150 T151

T152 T153 T154 T155 T156

NOBOM NOBOM NOBOM NOBOM NOBOM

NOBOM

NOBOM NOBOM NOBOM

NOBOM

NOBOM NOBOM

NOBOM

NOBOM NOBOM

NOBOM NOBOM NOBOM NOBOM NOBOM

+BATT

GND

1

T157

NOBOM

1

T71

NOBOM

1

T72

NOBOM

1

T73

NOBOM

1

T74

NOBOM

1

T75

NOBOM

1

T76

NOBOM

1

T77

NOBOM

1

T78

NOBOM

1

T79

NOBOM

1

T80

NOBOM

1

T81

NOBOM

1

T82

NOBOM

1

T83

NOBOM

1

T84

NOBOM

1

T85

NOBOM

1

T86

NOBOM

1

T88

NOBOM

1

T87

NOBOM

1

T90

NOBOM

1

T89

NOBOM

A A

PEGATRON DT-MB RESTRICTED SECRET

TEST POINT

Title :

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

IMPLP-MS

1

Stonko_Chen

80 83Thu rsday, June 27, 2013

Rev

A00

5

SIC_USB3_ RX_N1_183

SIC_USB3_ RX_P1_18 3

D D

SIC_USB3_ TX_N1_183

SIC_USB3_ TX_P1_183

C C

SIC_USB3_ RX_N2_183

SIC_USB3_ RX_P2_18 3

B B

SIC_USB3_ TX_N2_183

SIC_USB3_ TX_P2_183

1

H101

CRT315X 315B315D217

USB_GND

H102

1 2 3 4

A A

NOBOM

1

H100

CRT315X 315B315D217

NOBOM

NP_NC

GND8

GND1

GND7

GND2

GND6

GND3

GND5 GND4

C315D18 9N

NOBOM

5

9 8 7 6 5

H103

DO67X14 6N

1

NOBOM

RN30A

1 2

0

1 4

3 4

0

RN30B

RN31A

1 2

0

1 4

3 4

0

RN31B

RN33B

3 4

0

14

1 2

0

RN33A

RN34B

3 4

0

14

1 2

0

RN34A

U100 LOGO

1

4

L100 90OHM/10 0MHZ/330mA

NI

2 3

USB_GND

L101 90OHM/10 0MHZ/330mA

NI

2 3

23

NI

90OHM/10 0MHZ/330mA L103

USB_GND

23

NI

90OHM/10 0MHZ/330mA L104

4

USB3_RX _H_N1_1

USB3_RX _H_P1_1

Q71

4

TMDS_CH2TMDS_CH2+5NC1

3

GND1

1

TMDS_CH1-

2

TMDS_CH1+

IP4284CZ1 0-TB

USB3_TX _H_N1_1

USB3_TX _H_P1_1

USB3_RX _H_N2_1

USB3_RX _H_P2_1

Q73

4

TMDS_CH2TMDS_CH2+5NC1

3

GND1

1

TMDS_CH1-

2

TMDS_CH1+

IP4284CZ1 0-TB

USB3_TX _H_N2_1

USB3_TX _H_P2_1

NC2

GND2

NC4 NC3

NC2

GND2

NC4 NC3

3

RN32A0I

USBP1_182

7 6 8 10 9

USBN1_182

USB_GND

USBP2_182

7 6 8 10 9

USBN2_182

USB_GND

1 2

3 4

+5V_DUA L_USB3

3 4

14

1 2

3

1 4

2 3

0

RN32B

RN35B

0

23

90OHM/10 0MHZ/330mA L105

RN35A0I

L102 90OHM/10 0MHZ/330mA

I

Q72

CM1213_ 04SO

CH4

6

VP

5

I

12

C717

4.7PF/50V

I

USB_GND U SB_GND

CH1

1

VN

2

CH2CH3

34

C713

4.7PF/50V

I

12

4.7PF/50V

I

USB_GND

12

4.7PF/50V

I

USB_GNDUSB_GN D

C718

C714

L1_1+

L1_1-

L2_1+

L2_1-

2

USB_GND

2

J100

12

P_GND3

10

P_GND1

5

4

6

3

7

2

8

1

9

11

P_GND2

13

P_GND4

USB_CON _9P

J101

12

P_GND3

10

P_GND1

5

4

6

3

7

2

8

1

9

11

P_GND2

13

P_GND4

USB_CON _9P

1

+5V_DUA L_USB3

12

C715

0.1UF/16V

X7R 10%

I

USB_GND

12

C711

0.1UF/16V

X7R 10%

I

USB_GND USB_GND

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

IMPLP-MS

+

C716 100UF/6.3 V

USB_GND

12

+

C712 100UF/6.3 V

Title :

Engineer:

1

+5V_DUA L_USB3

CARD USB3.0 X2

Stonko_Chen

81 81Thu rsday, June 27, 2013

Rev

A00

5

D D

C C

4

+5V_DUA L_USB3 +5V_DUAL _USB3

CON2

USB_GND

2

4

6

8

10

12

14

16

18

20

WTOB _CON_20P

USB3_TX _P1_183 USB3_TX _N1_183

USB3_RX _P1_183 USB3_RX _N1_18 3

USBP1_181 USBN1_181

21

SIDE1

SIDE2

22

USB_GND

3

USB_GND

1

3

5

7

9

11

13

15

17

19

USB_GND

USB3_TX _P2_1 83 USB3_TX _N2_1 8 3

USB3_RX _P2_1 83 USB3_RX _N2_1 83

USBP2_1 81

USBN2_1 81

2

1

B B

A A

Title :

USB3.0 CONNECTOR

Stonko_Chen

1

Stonko_Chen

82 82Thu rsday, June 27, 2013

Rev

A00

Engineer:

Pegatron Corp.

Size Project Name

A3

Date: Sheet of

5

4

3

2

Date: Sheet of

IMPLP-MS

Engineer:

5

4

3

2

1

SIC_USB3_ TX_N1_RE SIC_USB3_ TX_P1_RE

12

D D

C C

NI

R1000

4.7KOHM

12

NI

R1003

4.7KOHM

USB3_TX _N1_182 USB3_TX _P1_182 USB3_RX _N1_18 2 USB3_RX _P1_182

12

NI

R1014

4.7KOHM

12

NI

R1017

4.7KOHM

12

NI

R1001

4.7KOHM

12

NI

R1004

4.7KOHM

SC3 0.1UF/16VX7R 1 0%

I

SC4 0.1UF/16VX7R 1 0%

I

12

NI

R1015

4.7KOHM

12

NI

R1018

4.7KOHM

NI

R1002

4.7KOHM

12

NI

R1005

4.7KOHM

USB_GNDUSB_GNDUSB_GNDUSB_GND USB_GND U SB_GND USB_GNDUSB_GND

1 2 1 2

NI

R1016

4.7KOHM

12

NI

R1019

4.7KOHM

+3P3V_U SB1_1

EQ_11 DE_11 OS_11 EN_RXD1 CM1

NI

R1006

4.7KOHM

CONN_US B3_RX_N1_1 CONN_US B3_RX_P1_1

+3P3V_U SB2_1

EQ_22 EQ_23 DE_22 OS_22

NI

R1020

4.7KOHM

USB_GND

1

VCC1

2

EQ1

3

DE1

4

OS1

5

EN_RXD

6

GND1

U9398

USB_GND

1

VCC1

2

EQ1

3

DE1

4

OS1

5

EN_RXD

6

GND1

U9399

25

20

21

22

23

24

NC2

GND4

GND5

Device_TX1-

Device_TX1+

NC17Host_RX1-8Host_RX1+9GND210Host_TX2-11Host_TX2+

SIC_USB3_ TX_N2_RE SIC_USB3_ TX_P2_RE

20

21

22

23

24

NC2

GND4

GND5

Device_TX1-

Device_TX1+

NC17Host_RX1-8Host_RX1+9GND210Host_TX2-11Host_TX2+

19

SN65LVP E502A

GND3

EQ2 DE2

Device_RX2-

Device_RX2+

OS2 RSVD VCC2

12

19

SN65LVP E502A

GND3

EQ2

DE2

Device_RX2-

Device_RX2+

OS2 RSVD VCC2

12

18 17 16 15 14 13

1 2

SC166 0.1UF/16VX7R 10%

I

1 2

SC163 0.1UF/16VX7R 10%

I

USB_GND

EQ_12 DE_12 OS_12

+3P3V_U SB1_1

12

I

C1000

0.1UF/16V

mx_c0402_ small

USB_GND

1 2

SC164 0.1UF/16VX7R 10 %

I

1 2

SC167 0.1UF/16VX7R 10 %

I

USB_GND

DE_23 OS_23 CM2EN_RXD2

+3P3V_U SB2_1

12

I

C1002

0.1UF/16V

mx_c0402_ small

12

+3P3V_U SB1_1+3P3V_U SB1_1

NI

R1007

4.7KOHM

NI

R1011

4.7KOHM

+3P3V_U SB2_1+3P3V_U SB2_1

NI

R1021

4.7KOHM

NI

R1025

4.7KOHM

12

NI

R1008

4.7KOHM

I

R1012

4.7KOHM

I

R1022

4.7KOHM

NI

R1026

4.7KOHM

SIC_USB3_ TX_N1_1 81 SIC_USB3_ TX_P1_1 8 1 SIC_USB3_ RX_N1_1 81 SIC_USB3_ RX_P1_1 81

12

NI

R1009

R1010

4.7KOHM

12

NI

R1013

4.7KOHM

SIC_USB3_ TX_N2_1 81 SIC_USB3_ TX_P2_1 8 1 SIC_USB3_ RX_N2_1 81 SIC_USB3_ RX_P2_1 81

12

NI

R1023

R1024

4.7KOHM

12

NI

R1027

4.7KOHM

+3P3V_U SB1_1

12

I

C1003

0.1UF/16V

mx_c0402_ small

USB_GND

+3P3V_U SB2_1

12

USB_GND

I

SR437

mx_r0603

1 2

0 Ohm

I

SR436

1 2

0 Ohm

mx_r0603

I

C1004

0.1UF/16V

mx_c0402_ small

+3P3V_D UAL

B B

USB3_TX _N2_182 USB3_TX _P2_182 USB3_RX _N2_18 2 USB3_RX _P2_182

A A

5

SC162 0.1UF/16VX7R 10%

I

SC165 0.1UF/16VX7R 10%

I

USB_GNDUSB_GNDUSB_GNDUSB_GND USB_GND U SB_GND USB_GND

1 2 1 2

4

USB_GND

CONN_US B3_RX_N2_1 CONN_US B3_RX_P2_1

USB_GND

3

+5V_DUA L_USB3

12

C1005

2.2UF/6.3V

X5R 10%

USB_GND

2

+3P3V_D UAL

U9400

1

VIN

2

GND EN3NC

G9091-33 0TA1U

USB_GND

Pegatron Corp.

Date: Sheet of

5

VOUT

4

Size Project Name

A3

12

I

C1006

4.7UF/10V

X5R 10%

USB_GND

IMPLP-MS

Title :

Engineer:

1

USB3.0 DRIVER

Stonko_Chen

83 83Thu rsday, June 27, 2013

Rev

A00