PEGATRON H36Y Schematic

5

4

3

2

1

SYSTEM PAGE REF.

01. Block Diagram

02. System Setting

03. CPU(1)_DMI,PEG,FDI,CLK,MISC

04. CPU(2)_DDR3

05. CPU(3)_CFG,RSVD,GND

06. CPU(4)_PWR

07. CPU(5)_XDP

16. DDR3(1)_SO-DIMM0

D D

17. DDR3(2)_SO-DIMM1

18. DDR3(3)_CA/DQ Voltage

19. VID Controller

20. PCH(1)_SATA,IHDA,RTC,LPC

21. PCH(2)_PCIE,CLK,SMB,PEG

22. PCH(3)_FDI,DMI,SYS PWR

23. PCH(4)_DP,LVDS,CRT

24. PCH(5)_PCI,NVRAM,USB

25. PCH(6)_CPU,GPIO,MISC

26. PCH(7)_POWER,GND

27. PCH(8)_POWER,GND

28. PCH(9)_SPI,SMB

29. CLK_ICS9LPR362

30. EC_IT8512(1)

31. EC_IT8512(2)KB,TP,FP

32. RST_Reset Circuit

33. LAN_AR8131

34. LAN_RJ45

C C

36. AUD(1)_ALC663VD

37. AUD(2)_AMP,JACK

38. AUD(3)_FM2010

40. CB(1)_R5U230

43. CB(4)_NewCard

44. BUG_Debug

45. CRT(1)_LVDS

46. CRT(2)_D-Sub

47. CRT(3)_Display Port

48. TV(1)_HDMI

50. FAN_Fan,Sensor

51. XDD_HDD,ODD

52. USB_USB Port

53. MINICARD_WLAN

56. LED_Indicator

57. DSG_Discharge

60. DC_DC/BAT CONN

61. BT_Bluetooth

64. TUN_TV Tuner

B B

65. ME_CONN,Skew Hole

66. ESA_ESATA

69. OTH_GAME-LED

70. VGA(1)_MXM Slot

71. VGA(2)_LVDS Switch 80_PWR(1)_VCORE 81_PWR(2)_SYSTEM_+12VSUS 82_PWR(3)_VTT_CPUS & 1.05VS 83_PWR(4)_I/O_DDR & VTT 84_PWR(5)_**** 85_PWR(6)_+1.8VS 86_PWR(7)_+VGFX_CORE 88_PWR(9)_CHARGER 90_PWR(11)_DETECT 91_PWR(12)_LOAD SWITCH 92_PWR(13)_PROTECT 93_PWR(14)_SIGNAL 94_PWR(15)_FLOWCHART

A A

95. System History

98. Power On Sequence

99. Power On Timing

H36Y Schematics for Calpella Platform Rev. 2.2

BLOCK DIAGRAM

HDMI

Page 48

Page 46

Page 45

Page 37

Page 65

HDMIHDMI

SDVO

SPI ROM

Thermal Sensor

CardReader

Alcor AU4633

Azalia Codec

Discharge Circuit

Reset Circuit

Page 48

LVDS

LVDSLVDS CRT

CRT

CRTCRT

Debug Conn.

EC

ITE IT8512E

s

s u

u

u B

B

B M

M

Page 30

S

PWM Fan

Page 40~41

Realtek ALC269

PCIE x16

PCIE x16PCIE x16

Page 44

Page 30Page 31

SPI ROM

Page 28

Page 50

PCIEx1

PCIEx1PCIEx1

Azalia

AzaliaAzalia

Page 36

DC & BATT. Conn.

Page 57

Page 32

LPC

LPCLPC

Skew Holes

CPU

Arrandale

(DC)

4

4 x

x

x I

I

I D

D

D F

F

4

4 x

x

x I

I

I M

M

M D

D

PCH

Ibex Peak-M

A

s

T

u

A

B

S

M

M S

S

1

0

5

Clock Generator

ICS ICS9LRS3197

Page 60

Page 65

DDR3 1333MHz

DDR3 1333MHzDDR3 1333MHz

Page 3~7

Page 20~28

ODD

HDD(1)

eSATA

PCIEx1

PCIEx1PCIEx1

USB

USBUSB

Page 51

Page 66

Page 29

DDR3 SO-DIMM

9

4

5

0

1

2

12

13

MiniCard

2

WLAN

Shirley Peak/ Echo Peak

1

MiniCard

6

3

GigaLAN

ExpressCard

USB Port(1)

USB Port(2)

USB Port(3)

Bluetooth

CMOS Camera

HSPA (3G)

AR8131

Page 16~18

Page 53

Page 64

Page 33~34

Page 43

Page 52

Page 61

Page 45

RJ45

Page 34

Power

CPU_VCORE

System

+1.8VS

GFX_CORE

Charger

Load Switch

Power Protect

HDMI

CRT

LCD Panel

Touchpad Keyboard

Speaker

Audio Jack

Page 80

Page 81

VTT

Page 82

DDR

Page 83

Page 85

Page 86

Page 88

Detect

Page 90

Page 91

Page 92

Title :

Block Diagram

Kuansheng Yang

Engineer:

BG1\HW1

Size Project Name

C

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

H36Y_U30X10

1

Kuansheng Yang

1 99Monday, May 10, 2010

Rev

1.0

PCH_IBEX

5

GPIO

D D

C C

B B

A A

PCH_IBEX GPIO

GPIO 00 GPIO 01

GPIO [2:5]

GPIO 06 GPIO 07 GPIO 08 GPIO 09 GPIO 10 GPIO 11 GPIO 12 GPIO 13 GPIO 14 GPIO 15 GPIO 16 +3VS GPIO 17 +3VSGPIO 18 +3VS GPIO 19 +3VS GPIO 20 +3VS GPIO 21 GPIO 22 GPIO 23 GPIO 24 +3VSUS

GPIO 26 GPIO 27 GPIO 28 GPIO 29 GPIO 30 GPIO 31 GPIO 32 GPIO 33 GPIO 34 GPIO 35 GPIO 36 GPIO 37 GPIO 38 GPIO 39 +3VS GPIO 40 GPIO 41 GPIO 42 GPIO 43 GPIO 44 GPIO 45 GPIO 46 GPIO 47 GPIO 48 GPIO 49 GPIO 50 GPIO 51 GPIO 52 GPIO 53 GPIO 54 GPIO 55 GPIO 56 GPIO 57 GPIO 58 GPIO 59 GPIO 60 GPIO 61 GPIO 62 GPIO 63 GPIO 64 GPIO 65 GPIO 66 GPIO 67 GPIO 72 GPIO 73 GPIO 74 GPIO 75

5

-

Native

-

GPI Native Native USB_OC6#

GPI

-

Native

GPO

-

Native Native Native

GPO

-

NativeGPIO 25

- CLK_REQ4#

- VRM_EN

GPO Native ME_PM_SLP_LAN# Native Native Native Native Native

GPO CAP_RST#_ICH

-

GPI GPI

Native Native Native Native Native

-

- CLKREQ_PEG#

GPO

--PCI_REQ1#

-

Native Native

GPO

Native Native USB_OC0#

-

Native

-

Native

Signal NameUse As Power

GPIO0 DOCKING_DET# PCI_INT[E:H]# DGPU_PWR_EN XIDE_BAY_IN# EXT_SMI# USB_OC5#

EXT_SCI# PM_LANPHY_EN DGPU_PWR_EN_R USB_OC7# BT_LED DGPU_HOLD_RST# DGPU_PWR_OK CLK_REQ1# SATA1GP CLKREQ2_WLAN# SATA0GP WLAN_LED LPC_DRQ#1 OC_LAN_RST# CLKREQ3_NEWCARD#

WLAN_ON

ME_SUSPWRDNACK ME_AC_PRESENT PM_CLKRUN# HDA_DOCK_EN# STP_PCI#

DGPU_PWR_EN# DGPU_PRSNT# PCB_ID0 PCB_ID1 USB_OC1# USB_OC2# USB_OC3# USB_OC4# CLK_REQ5_LAN# CLK_REQ6# CLK_REQ7#

EMAIL_LED PCH_TEMP_ALERT#

PCI_GNT1# PCI_REQ2#PCI_GNT2# PCI_REQ3# PCI_GNT3# CLKREQ_GLAN#_R BT_ON SML1_CLK

RTLAN_DSM_EN PM_SUS_STAT# SUS_CLK SLP_S5# CLK_OUT0 CLK_OUT1 CLK_OUT2 CLK_USB48_CR PM_BATLOW# CLK_REQ0# SML1ALERT# SML1_DAT

4

Internal & External Pull-up/down

-

EXT PU

EXT PU & INT PU

EXT PU

-

EXT PU

INT PD

-

EXT PD & INT TBD

EXT PU(DNI)/PD

-

EXT PU(DNI)/PD

-

EXT PD

-

EXT PU

EXT PU(DNI)/PD

EXT PU(Not used)

INT WEAK PU

EXT PD

EXT PU(DNI)/PD(DNI)

EXT PU

-

EXT PU

EXT PU/PD(DNI)

EXT PU

EXT PD

EXT PU (Not used)

EXT PD

-

EXT PU (Not used)

INT PU

EXT PU

INT PU

EXT PU(DNI)/PD

EXT PU(DIODE)

EXT PU

EXT PU (Not used)

EXT PU

-

INT TBD

EXT PU (Not used)

EXT PU

4

+3VS +3VS +5VS +3VS +3VS +3VSUS +3VSUS +3VSUS +3VSUS +3VSUS +3VSUS +3VSUS +3VSUS

+3VS +3VS +3VS

+3VSUS +3VSUS +3VSUS +3VSUS +3VSUS +3VSUS +3VSUS +3VS +3VS +3VS +3VS +3VS +3VS +3VS

+3VSUS +3VSUS +3VSUS +3VSUS +3VSUS +3VSUS +3VSUS +3VSUS +3VS +3VS +5VS +3VS +5VS +3VS +5VS +3VS +3VSUS +3VSUS +3VSUS +3VSUS +3VSUS +3VSUS +3VSUS +3VSUS +3VS +3VS +3VS +3VS +3VSUS +3VSUS +3VSUS +3VSUS

EC IT8512

3

EC GPIO

Use As Signal Name

GPA0 GPA1 GPA2 GPA3 GPA4 GPA5 GPA6 GPA7 GPB0 GPB1 GPB2 GPB3 GPB4 GPB5 GPB6 GPB7 GPC0 GPC1 GPC2 GPC3 GPC4 GPC5 GPC6 GPC7 GPD0 GPD1 GPD2 GPD3 GPD4 GPD5 GPD6 GPD7 GPE0 GPE1 GPE2 GPE3 GPE4 GPE5 GPE6 GPE7 GPF0 GPF1 GPF2 GPF3 GPF4 GPF5 GPF6 GPF7 GPG0 GPG1 GPG2 GPG6 GPH0 GPH1 GPH2 GPH3 GPH4 GPH5 GPH6 CAP_LED# GPI0 GPI1 GPI2 GPI3 GPI4 GPI5 GPI6 GPI7 GPJ0 GPJ1 GPJ2

GPJ4 GPJ5 GFX_VR

PWR_LED#

O

CHG_LED#

O

-

LCD_BL_PWM

O

FAN_PWM

O

-

SMB0_CLK

IO

SMB0_DAT

IO

A20GATE

O

RCIN#

O

PM_RSMRST#

O

SMB1_CLK

IO

SMB1_DAT

IO

PM_PWRBTN#

O

AC_IN_OC#

I

OP_SD#

O

BAT1_IN_OC#

I

RFON_SW#

I

PWRLIMIT#

I

PM_SUSC#

I

BUF_PLT_RST#

I

EXT_SCI#

O

EXT_SMI#

O

LCD_BACKOFF#

O

FAN0_TACH

I

VSUS_ON

O

SUSC_EC#

O

SUSB_EC#

O O

CPU_VRON PWR_SW#

I

LID_SW#

I

CAP_ACK#

I

-

DISTP#

I

TP_CLK

I

TP_DAT

IO

THRO_CPU

O

ME_AC_PRESENT

O

KB_ID0

O

PM_SUSB#

I

-

PM_CLKRUN#

IO

3G_ON

I

GFX_VR_ON

O

-

O

PCH_TEMP_ALERT#

I

SUS_PWRGD

I

ALL_SYSTEM_PWRGD

I

VRM_PWRGD

I

ME_PM_SLP_LAN#

I

ME_PM_SLP_M#

I

ME_SUSPWRDNACK

I

CAP_RST#_EC

O

PM_PWROK

O

KB_ID1

O

-GPJ3 TP_LED

O I

3

2

EC IT8301

2

1

GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37

Signal NameUse AsEC GPIO

-

SM_BUS ADDRESS :

SM-Bus Device

Clock Generator

SO-DIMM 0

SO-DIMM 1

CPU Thermal IC(G780)

VGA Thermal IC(G781-1)

VGA Thermal Sensor(NB9E-GE1) 1001111x ( 9Eh )

VID Controller ASM8272 0011011x ( 36h )

PCIE 1

N/A

PCIE 2

Minicard WLAN

PCIE 3

Newcard

PCIE 4

N/A

PCIE 5

N/A

PCIE 6

GLAN

PCIE 7

N/A

PCIE 8

N/A

SATA0

SATA HDD

SATA1

SATA ODD

SATA2

N/A

SATA3

N/A

N/ASATA4

SATA5 eSATA

BG1\HW1

Size Project Name

C

Date: Sheet of

SM-Bus Address

1101001x ( D2h )

1010000x ( A0h )

1010001x ( A4h )

1001100x ( 98h )

1001101x ( 9Ah )

USB 0

USB Port (1)

USB 1

USB Port (2)

USB 2

USB Port (3)

USB 3

N/A

USB 4

USB 5

Newcard

Card Reader

USB 6

USB 7

3G

N/A

USB 8

WLAN

USB 9

USB 10

N/A

USB 11

N/A

Bluetooth

USB 12

USB 13

CMOS Camera

Engineer:

H36Y_U30X10

1

Title :

System Setting

Kuansheng Yang

2 99Monday, May 10, 2010

Rev

1.0

5

U0301A

FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7

FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7

A24

DMI_RX#[0]

C23

DMI_RX#[1]

B22

DMI_RX#[2]

A21

DMI_RX#[3]

B24

DMI_RX[0]

D23

DMI_RX[1]

B23

DMI_RX[2]

A22

DMI_RX[3]

D24

DMI_TX#[0]

G24

DMI_TX#[1]

F23

DMI_TX#[2]

H23

DMI_TX#[3]

D25

DMI_TX[0]

F24

DMI_TX[1]

E23

DMI_TX[2]

G23

DMI_TX[3]

E22

FDI_TX#[0]

D21

FDI_TX#[1]

D19

FDI_TX#[2]

D18

FDI_TX#[3]

G21

FDI_TX#[4]

E19

FDI_TX#[5]

F21

FDI_TX#[6]

G18

FDI_TX#[7]

D22

FDI_TX[0]

C21

FDI_TX[1]

D20

FDI_TX[2]

C18

FDI_TX[3]

G22

FDI_TX[4]

E20

FDI_TX[5]

F20

FDI_TX[6]

G19

FDI_TX[7]

F17

FDI_FSYNC[0]

E17

FDI_FSYNC[1]

C17

FDI_INT

F18

FDI_LSYNC[0]

D17

FDI_LSYNC[1]

SOCKET989

1201-0017000

DMI_TXN0<22> DMI_TXN1<22> DMI_TXN2<22> DMI_TXN3<22>

DMI_TXP0<22> DMI_TXP1<22> DMI_TXP2<22> DMI_TXP3<22>

DMI_RXN0<22> DMI_RXN1<22> DMI_RXN2<22>

D D

C C

DMI_RXN3<22>

DMI_RXP0<22> DMI_RXP1<22> DMI_RXP2<22> DMI_RXP3<22>

FDI_TXN[7:0]<22>

FDI_TXP[7:0]<22>

FDI_FSYNC0<22> FDI_FSYNC1<22>

FDI_INT<22>

FDI_LSYNC0<22> FDI_LSYNC1<22>

For Intel GFX display

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RBIAS

PEG_RX#[0] PEG_RX#[1] PEG_RX#[2]

DMI Intel(R) FDI

PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]

PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]

PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]

PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13]

PCI EXPRESS -- GRAPHICS

PEG_TX#[14] PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

B26 A26 B27 A25

K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31

J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30

L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26

L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25

PEG_IRCOMP_R

EXP_RBIAS

4

R0301 49.9Ohm1%R0301 49.9Ohm1%

1 2

R0302 750OHM1%R0302 750OHM1%

1 2

3

SKTOCC#:pulled to ground on processor. may use to determine if CPU is present

U0301B

AT23

AT24

AT26

AH24

AK14

AT15

AN26

AK15

AP26

AL15

AN14

AN27

AK13

AM15

AM26

AL14

G16

U0301B

COMP3

COMP2

COMP1

COMP0

SKTOCC#

CATERR#

PECI

PROCHOT#

THERMTRIP#

RESET_OBS#

PM_SYNC

VCCPWRGOOD_1

VCCPWRGOOD_0

SM_DRAMPWROK

VTTPWRGOOD

TAPPWRGOOD

RSTIN#

SOCKET989

H_COMP3

R030320Ohm 1% R030320Ohm 1%

12

H_COMP2

R030420Ohm 1% R030420Ohm 1%

12

H_COMP1

R030549.9Ohm 1% R030549.9Ohm 1%

12

H_COMP0

R030649.9Ohm 1% R030649.9Ohm 1%

12

TP_SKTOCC#

T0301T0301

1

R030749.9Ohm 1% R030749.9Ohm 1%

@

R0322

68Ohm

1

R0318

1.5KOHM

12

H_PECI_ISO

12

H_PROCHOT_S#_R

12

H_THRMTRIP#_R

12

H_CPURST#

PM_SYNC#_R

12

VCCPWRGOOD_1_R

12

VCCPWRGOOD_0_R

12

VDDPWRGOOD_R

12

H_VTTPWRGD_R

H_PWRGD_XDP

PLT_RST#_R

12

R0319

R0319 750OHM

750OHM

+VTT_CPU

H_CATERR#

R0317 0Ohm

THRO_CPU

H_PECI<25>

SP0301 R0402SP0301 R0402

+VTT_CPU

H_PROCHOT_S#

H_THRMTRIP#<25,32>

PM_SYNC#<22>

H_CPUPWRGD<25>

H_DRAM_PWRGD<22>

H_VTTPWRGD< 92>

BUF_PLT_RST#<24,30,32,33,43,53,54>

SP0302 R0402SP0302 R0402

SP0303 R0402SP0303 R0402

T0303T0303

SP0304 R0402SP0304 R0402

SP0305 R0402SP0305 R0402

SP0306 R0402SP0306 R0402

SP0307 R0402SP0307 R0402

T0302T0302

1 2

2

MISC

CLOCKS

THERMAL PWR MANAGEMENT

DDR3

MISC

DDR3

MISC

JTAG & MBP

BCLK#

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

PM_EXT_TS#[0] PM_EXT_TS#[1]

PRDY#

PREQ#

TRST#

TDI_M

TDO_M

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

+VTT_CPU

BCLK

TCK TMS

TDI

TDO

DBR#

+1.5V

A16 B16

AR30 AT30

E16 D16

A18 A17

F6

AL1 AM1 AN1

AN15 AP15

+VTT_CPU

AT28 AP27

AN28 AP28 AT27

AT29 AR27 AR29 AP29

AN25

AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23

CLK_CPU_BCLK CLK_CPU_BCLK#

CLK_EXP_P CLK_EXP_N

CLKDREF CLKDREF#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

RN0301A

RN0301A RN0301B

RN0301B

+VTT_CPU <6,25,26,32,57,82>

+1.5V <6,16,57,83>

R0323 0OhmR0323 0Ohm R0324 0OhmR0324 0Ohm

R0331 100Ohm1%R0331 100Ohm1%

1 2

R0332 24.9Ohm1%R0332 24.9Ohm1%

1 2

R0333 130Ohm1%R0333 130Ohm1%

1 2

PM_EXTTS#1

10KOHM

10KOHM 10KOHM

10KOHM

XDP_PRDY#

1

H_PREQ#

H_TCK H_TMS H_TRST#

H_TDI H_TDO H_TDI_M H_TDO_M

H_DBR#

XDP_BPM#0

1 XDP_BPM#1 XDP_BPM#2

1 XDP_BPM#3

1 XDP_BPM#4

1 XDP_BPM#5

1 XDP_BPM#6

1 XDP_BPM#7

1

1 2 1 2

12 34

T0309T0309

T0310T0310

T0311T0311 T0304T0304 T0305T0305 T0306T0306 T0307T0307 T0308T0308

1

CLK selection

M_DRAMRST# <16,17>

120MHz from PCH. IF NOT USED, PULL-LOW FOR POWER SAVING.

PM_EXTTS#0 <16,17>

BCLK_CPU_P_PCH<25>

B B

BCLK_CPU_N_PCH<25>

CLK_DMI_PCH<21> CLK_DMI#_PCH<21>

SP0313 R0402SP0313 R0402 SP0314 R0402SP0314 R0402

SP0315 R0402SP0315 R0402 SP0316 R0402SP0316 R0402

12 12

FDI disable: (For discrete graphic)

1. NC:

FDI_TX#[0:7],FDI_TX[0:7],FDI_RX#[0:7],FDI_RX[0:7]

VCC_AXGSENSE,VSS_AXGSENSE

2. Pull-down to GND via 1KΩ ± 5% resistor:

FDI_FSYNC[0:1],FDI_LSYNC[0:1],FDI_INT,GFX_IMON

~15mW power saving.(DG R0.8 P.70)

A A

3. Connected to GND:

VCCAXG,DPLL_REF_CLK,DPLL_REF_CLK#

4. Can be connected to GND directly:

DPLL_REF_CLK,DPLL_REF_CLK#

5. Connect to +V1.05S rail:

VCCFDIPLL

5

CLK_CPU_BCLK CLK_CPU_BCLK#

CLK_EXP_P CLK_EXP_N

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

FDI_INT

R0364 1KOhm@R0364 1KOhm@

1 2

R0361 1KOhm@R0361 1KOhm@

1 2

R0365 1KOhm@R0365 1KOhm@

1 2

R0362 1KOhm@R0362 1KOhm@

1 2

R0363 1KOhm@R0363 1KOhm@

1 2

4

H_CPURST#

R0313 68Ohm@R0313 68Ohm@

1 2

DRAMPWROK: (WW35 MoW)

Choose either one solution: -->Choose solution 2

1. This pin should have an external pull-up of 1K Ohms to 10K Ohms to a rail of 1.05/1.1V which is ON in S0-S3

2. Connect this pin through a voltage divider circuit;

recommend 4.75K Ohms pull-up to DDR3 Power Rail (VDDQ) of +V1.5U and a 12K Ohms pull-down to ground to convert to processor’s VTT level.

+VTT_CPU

3

VDDPWRGOOD_R

+1.5V

R0320

1.1KOhm

1 2

12

R0321

3.01KOHM

R1.4--1

WW14_2009_WOM

H_PROCHOT_S#

D0301

PWRLIMIT#<30,90>

D0301

RB751V-40

@

Default Strapping When Not Used

XDP_BPM#1

R0328 51Ohm @R0328 51Ohm @

H_PREQ#

R0329 51Ohm /boundary scanR0329 51Ohm /boundary scan

H_TDI

R0330 51Ohm @R0330 51Ohm @

H_TDO

R0336 51Ohm /boundary scanR0336 51Ohm /boundary scan

H_TMS

R0337 51Ohm @R0337 51Ohm @

H_TDO_M

R0314 0Ohm /boundary scanR0314 0Ohm /boundary scan

H_DBR#

R0338 1KOhm @R0338 1KOhm @

H_TCK

R0334 51Ohm @R0334 51Ohm @

H_TRST#

R0335 51Ohm /boundary scanR0335 51Ohm /boundary scan

2

12

1 2 1 2 1 2 1 2 1 2

1 2

3

D

Q0301

Q0301 2N7002

2N7002

1

THRO_CPU

G

S

2

+VTT_CPU

H_TDI_M

12

THRO_CPU <30>

Adding layout test point for boundary sc an Jervis 2009/1 1/09

CLK_CPU_BCLK H_VTTPWRGD_R VCCPWRGOOD_0_R VCCPWRGOOD_1_R PLT_RST#_R H_TRST# H_TCK H_TMS H_TDI H_TDO H_TDI_M

+3VS

BG1\HW1

Size Project Name

C

Date: Sheet of

H_TDO_M

Title :

Engineer:

H36Y_U30X10

1

CPU(1)_DMI,PEG,FDI,CLK,MISC

T0312T0312

1

T0313T0313

1

T0314T0314

1

T0315T0315

1

T0316T0316

1

T0317T0317

1

T0318T0318

1

T0319T0319

1

T0320T0320

1

T0321T0321

1

T0322T0322

1

T0323T0323

1

Kuansheng Yang

3 99Monday, May 10, 2010

Rev

1.0

5

U0301C

D D

U0301C

4

3

U0301D

2

1

AA6

SA_CK[0]

M_A_DQ[63:0]<16>

C C

B B

M_A_DQ0

A10

AK12

AK11

AM10 AR11

AT11 AP12 AM12 AN12 AM13 AT14 AT12

AR14 AP14

AJ10

AL10

AL11

AL13

SA_DQ[0]

C10

SA_DQ[1]

C7

SA_DQ[2]

A7

SA_DQ[3]

B10

SA_DQ[4]

D10

SA_DQ[5]

E10

SA_DQ[6]

A8

SA_DQ[7]

D8

SA_DQ[8]

F10

SA_DQ[9]

E6

SA_DQ[10]

F7

SA_DQ[11]

E9

SA_DQ[12]

B7

SA_DQ[13]

E7

SA_DQ[14]

C6

SA_DQ[15]

H10

SA_DQ[16]

G8

SA_DQ[17]

K7

SA_DQ[18]

J8

SA_DQ[19]

G7

SA_DQ[20]

G10

SA_DQ[21]

J7

SA_DQ[22]

J10

SA_DQ[23]

L7

SA_DQ[24]

M6

SA_DQ[25]

M8

SA_DQ[26]

L9

SA_DQ[27]

L6

SA_DQ[28]

K8

SA_DQ[29]

N8

SA_DQ[30]

P9

SA_DQ[31]

AH5

SA_DQ[32]

AF5

SA_DQ[33]

AK6

SA_DQ[34]

AK7

SA_DQ[35]

AF6

SA_DQ[36]

AG5

SA_DQ[37]

AJ7

SA_DQ[38]

AJ6

SA_DQ[39] SA_DQ[40]

AJ9

SA_DQ[41] SA_DQ[42] SA_DQ[43]

AK8

SA_DQ[44]

AL7

SA_DQ[45] SA_DQ[46]

AL8

SA_DQ[47]

AN8

SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51]

AM9

SA_DQ[52]

AN9

SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

AC3

SA_BS[0]

AB2

SA_BS[1]

U7

SA_BS[2]

AE1

SA_CAS#

AB3

SA_RAS#

AE9

SA_WE#

DDR SYSTEM MEMORY A

M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M_A_BS0<16> M_A_BS1<16> M_A_BS2<16>

M_A_CAS#<16> M_A_RAS#<16> M_A_WE#<16>

SA_CK#[0] SA_CKE[0]

SA_CK[1] SA_CK#[1] SA_CKE[1]

SA_CS#[0] SA_CS#[1]

SA_ODT[0] SA_ODT[1]

SA_DM[0]

SA_DM[1]

SA_DM[2]

SA_DM[3]

SA_DM[4]

SA_DM[5]

SA_DM[6]

SA_DM[7]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

SA_MA[0]

SA_MA[1]

SA_MA[2]

SA_MA[3]

SA_MA[4]

SA_MA[5]

SA_MA[6]

SA_MA[7]

SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

AA7 P7

Y6 Y5 P6

AE2 AE8

AD8 AF9

B9 D7 H7 M7 AG6 AM7 AN10 AN13

C9 F8 J9 N9 AH7 AK9 AP11 AT13

C8 F9 H9 M9 AH8 AK10 AN11 AR13

Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9

M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_CLK_DDR0 <16> M_CLK_DDR#0 <16> M_CKE0 <16>

M_CLK_DDR1 <16> M_CLK_DDR#1 <16> M_CKE1 <16>

M_CS#0 <16> M_CS#1 <16>

M_ODT0 <16> M_ODT1 <16>

M_A_DM[7:0] <16>

M_A_DQS#[7:0] <16>

M_A_DQS[7:0] <16>

M_A_A[15:0] <16>

M_B_DQ[63:0]<17>

M_B_DQ0

B5

AR10 AT10

SB_DQ[0]

A5

SB_DQ[1]

C3

SB_DQ[2]

B3

SB_DQ[3]

E4

SB_DQ[4]

A6

SB_DQ[5]

A4

SB_DQ[6]

C4

SB_DQ[7]

D1

SB_DQ[8]

D2

SB_DQ[9]

F2

SB_DQ[10]

F1

SB_DQ[11]

C2

SB_DQ[12]

F5

SB_DQ[13]

F3

SB_DQ[14]

G4

SB_DQ[15]

H6

SB_DQ[16]

G2

SB_DQ[17]

J6

SB_DQ[18]

J3

SB_DQ[19]

G1

SB_DQ[20]

G5

SB_DQ[21]

J2

SB_DQ[22]

J1

SB_DQ[23]

J5

SB_DQ[24]

K2

SB_DQ[25]

L3

SB_DQ[26]

M1

SB_DQ[27]

K5

SB_DQ[28]

K4

SB_DQ[29]

M4

SB_DQ[30]

N5

SB_DQ[31]

AF3

SB_DQ[32]

AG1

SB_DQ[33]

AJ3

SB_DQ[34]

AK1

SB_DQ[35]

AG4

SB_DQ[36]

AG3

SB_DQ[37]

AJ4

SB_DQ[38]

AH4

SB_DQ[39]

AK3

SB_DQ[40]

AK4

SB_DQ[41]

AM6

SB_DQ[42]

AN2

SB_DQ[43]

AK5

SB_DQ[44]

AK2

SB_DQ[45]

AM4

SB_DQ[46]

AM3

SB_DQ[47]

AP3

SB_DQ[48]

AN5

SB_DQ[49]

AT4

SB_DQ[50]

AN6

SB_DQ[51]

AN4

SB_DQ[52]

AN3

SB_DQ[53]

AT5

SB_DQ[54]

AT6

SB_DQ[55]

AN7

SB_DQ[56]

AP6

SB_DQ[57]

AP8

SB_DQ[58]

AT9

SB_DQ[59]

AT7

SB_DQ[60]

AP9

SB_DQ[61] SB_DQ[62] SB_DQ[63]

AB1

SB_BS[0]

W5

SB_BS[1]

R7

SB_BS[2]

AC5

SB_CAS#

Y7

SB_RAS#

AC6

SB_WE#

DDR SYSTEM MEMORY - B

M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_BS0<17> M_B_BS1<17> M_B_BS2<17>

M_B_CAS#<17> M_B_RAS#<17> M_B_WE#<17>

SB_CK[0] SB_CK#[0] SB_CKE[0]

SB_CK[1] SB_CK#[1] SB_CKE[1]

SB_CS#[0] SB_CS#[1]

SB_ODT[0] SB_ODT[1]

SB_DM[0]

SB_DM[1]

SB_DM[2]

SB_DM[3]

SB_DM[4]

SB_DM[5]

SB_DM[6]

SB_DM[7]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

SB_MA[0]

SB_MA[1]

SB_MA[2]

SB_MA[3]

SB_MA[4]

SB_MA[5]

SB_MA[6]

SB_MA[7]

SB_MA[8]

SB_MA[9]

SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

W8 W9 M3

V7 V6 M2

AB8 AD6

AC7 AD1

M_B_DM0

D4

M_B_DM1

E1

M_B_DM2

H3

M_B_DM3

K1

M_B_DM4

AH1

M_B_DM5

AL2

M_B_DM6

AR4

M_B_DM7

AT8

M_B_DQS#0

D5

M_B_DQS#1

F4

M_B_DQS#2

J4

M_B_DQS#3

L4

M_B_DQS#4

AH2

M_B_DQS#5

AL4

M_B_DQS#6

AR5

M_B_DQS#7

AR8

M_B_DQS0

C5

M_B_DQS1

E3

M_B_DQS2

H4

M_B_DQS3

M5

M_B_DQS4

AG2

M_B_DQS5

AL5

M_B_DQS6

AP5

M_B_DQS7

AR7

M_B_A0

U5

M_B_A1

V2

M_B_A2

T5

M_B_A3

V3

M_B_A4

R1

M_B_A5

T8

M_B_A6

R2

M_B_A7

R6

M_B_A8

R4

M_B_A9

R5

M_B_A10

AB5

M_B_A11

P3

M_B_A12

R3

M_B_A13

AF7

M_B_A14

P5

M_B_A15

N1

M_CLK_DDR2 <17> M_CLK_DDR#2 <17> M_CKE2 <17>

M_CLK_DDR3 <17> M_CLK_DDR#3 <17> M_CKE3 <17>

M_CS#2 <17> M_CS#3 <17>

M_ODT2 <17> M_ODT3 <17>

M_B_DM[7:0] <17>

M_B_DQS#[7:0] <17>

M_B_DQS[7:0] <17>

M_B_A[15:0] <17>

SOCKET989

A A

Title :

CPU(2)_DDR3

Kuansheng Yang

Engineer:

BG1\HW1

Size Project Name

C

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

H36Y_U30X10

1

Kuansheng Yang

4 99Monday, May 10, 2010

Rev

1.0

5

4

3

2

1

D D

CFG0

1

CFG1

1

CFG2

1

CFG3

1

CFG4

1

CFG5

1

CFG6

1

CFG7

1

CFG8

1

CFG9

1

CFG10

1

CFG11

1

CFG12

1

CFG13

1

CFG14

1

CFG15

1

CFG16

1

CFG17

1

CFG18

1

SP0501 R0402SP0501 R0402

SP0502 R0402SP0502 R0402

T0513T0513 T0510T0510

T0511T0511 T0512T0512

T0514T0514 T0515T0515

10mil trace 10mil trace

H_RSVD17_R

12

H_RSVD18_R

12

1 1

DIMM0_VREF_DQ<18> DIMM1_VREF_DQ<18>

T0578T0578 T0567T0567 T0566T0566 T0565T0565 T0569T0569 T0568T0568 T0571T0571 T0572T0572 T0574T0574 T0570T0570

C C

B B

T0575T0575 T0573T0573 T0576T0576 T0577T0577 T0592T0592 T0581T0581 T0580T0580 T0579T0579 T0583T0583

AP25

AL25 AL24 AL22 AJ33

AM30 AM28 AP31

AL32

AL30 AM31 AN29 AM32 AK32 AK31 AK28

AJ28 AN30 AN32

AJ32

AJ29

AJ30 AK30

AG9 M27 L28

J17 H17 G25 G17 E31 E30

H16

B19 A19

A20 B20

U9

T9

AC9 AB9

C1

A3

J29

J28

A34 A33

C35 B35

U0301E

RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] RSVD_TP_86

RSVD15 RSVD16

RSVD17 RSVD18

RSVD19 RSVD20

RSVD21 RSVD22

RSVD_NCTF_23 RSVD_NCTF_24

RSVD26 RSVD27

RSVD_NCTF_28 RSVD_NCTF_29

RSVD_NCTF_30 RSVD_NCTF_31

SOCKET989

RSVD_NCTF_37

RSVD_NCTF_40 RSVD_NCTF_41

RSVD_NCTF_42 RSVD_NCTF_43

RSVD_NCTF_54 RSVD_NCTF_55 RSVD_NCTF_56 RSVD_NCTF_57

RSVD_TP_59 RSVD_TP_60

RESERVED

RSVD_TP_66 RSVD_TP_67 RSVD_TP_68 RSVD_TP_69 RSVD_TP_70 RSVD_TP_71 RSVD_TP_72 RSVD_TP_73 RSVD_TP_74 RSVD_TP_75

RSVD_TP_76 RSVD_TP_77 RSVD_TP_78 RSVD_TP_79 RSVD_TP_80 RSVD_TP_81 RSVD_TP_82 RSVD_TP_83 RSVD_TP_84 RSVD_TP_85

RSVD32 RSVD33

RSVD34 RSVD35

RSVD36

RSVD38 RSVD39

RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 RSVD53

RSVD58

RSVD62 RSVD63 RSVD64 RSVD65

U0301H

AJ13 AJ12

AH25 AK26

AL26

T0504T0504

AR2

1

AJ26 AJ27

T0501T0501

AP1

1

T0506T0506

AT2

1

T0507T0507

AT3

1

T0503T0503

AR1

1

AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33

T0508T0508

1

AT33

T0509T0509

AT34

1

T0502T0502

AP35

1

T0505T0505

AR35

1

AR32

E15 F15 A2

KEY

D15 C15 AJ15 AH15

AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3

V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9

AP34

VSS

RSVD64_R RSVD65_R

SP0503 R0402SP0503 R0402

SP0504 R0402SP0504 R0402

12 12

AT20 AT17 AR31 AR28 AR26 AR24 AR23 AR20 AR17 AR15 AR12

AP20 AP17 AP13 AP10

AN34 AN31 AN23 AN20 AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11

AL34 AL31 AL23 AL20 AL17 AL12

AK29 AK27 AK25 AK20 AK17

AJ31 AJ23 AJ20 AJ17 AJ14 AJ11

AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13

AG10

AE35

AR9 AR6 AR3

AP7 AP4 AP2

AM8 AM5 AM2

AL9 AL6 AL3

AJ8 AJ5 AJ2

AH9 AH6 AH3

AF8 AF4 AF2

U0301H

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80

SOCKET989

VSS

VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30

K27

K9 K6

K3 J32 J30 J21 J19 H35 H32 H28 H26 H24 H22 H18 H15 H13 H11

H8 H5

H2 G34 G31 G20

G9

G6

G3 F30 F27 F25 F22 F19 F16 E35 E32 E29 E24 E21 E18 E13 E11

E8 E5

E2 D33 D30 D26

D9 D6

D3 C34 C32 C29 C28 C24 C22 C20 C19 C16 B31 B25 B21 B18 B17 B13 B11

B8 B6

B4 A29 A27 A23

A9

U0301I

VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233

SOCKET989

VSS

NCTF

VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7

TP_MCP_VSS_NCTF1

AT35

TP_MCP_VSS_NCTF2

AT1 AR34 B34 B2

TP_MCP_VSS_NCTF6

B1

TP_MCP_VSS_NCTF7

A35

T0564T0564

1

T0561T0561

1

T0563T0563

1

T0562T0562

1

CFG strapping information:

CFG[1:0]: PCI Express Port Bifurcation:(Clarksfield Only)

- 11 = 1 x 16 PEG (Default)

- 10 = 2 x 8 PEG

CFG[3]: PCIE Static Numbering Lane Reversal.(Auburndale Only)

- 1:Normal Operation (Default)

- 0:Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

CFG[4]: Embedded DisplayPort Detection.(Auburndale Only)

- 1:Disabled - No Physical Display Port attached to Embedded DisplayPort

- 0:Enabled - An external Display Port device is connected to the Embedded Display Port

CFG[7]: Fixed for PCI Express 2.0 jitter specifications.(Clarksfi eld)

Clarksfield (only for early samples pre-ES1) - Connect to GND with 3.01K Ohm /5% resistor For a common motherboard design (for AUB and CFD),

A A

the pull-down resistor should be used. Does not impact AUB functionality. Unmount if Intel has fixed this issue.

Note: (Auburndale)Hardware Straps are sampled on the asserting edge of VCCPWRGOOD_0 and VCCPWRGOOD_1 and latched inside the processor.

Note: (Clarksfield)Hardware Straps are sampled after RSTIN# de-assertion.

5

4

CFG0

CFG3

CFG4

CFG7

R0535 3.01KOHM@R0535 3.01KOHM@

R0536 3.01KOHM@R0536 3.01KOHM@

R0537 3.01KOHM@R0537 3.01KOHM@

R0538 3.01KOHM@R0538 3.01KOHM@

12

Title :

CPU(3)_CFG,RSVD,GND

Kuansheng Yang

Engineer:

BG1\HW1

Size Project Name

C

Date: Sheet of

3

2

Date: Sheet of

Engineer:

H36Y_U30X10

1

Kuansheng Yang

5 99Monday, May 10, 2010

Rev

1.0

5

4

3

2

1

U0301F

+VCORE

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

D D

C C

B B

AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26

VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

1.1V RAIL POWER

CPU CORE SUPPLY

POWER

PROC_DPRSLPVR

CPU VIDS

VSS_SENSE_VTT

SENSE LINES

VTT0_1 VTT0_2 VTT0_3 VTT0_4 VTT0_5 VTT0_6 VTT0_7 VTT0_8

VTT0_9 VTT0_10 VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32

VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

VTT_SELECT

ISENSE

VCC_SENSE VSS_SENSE

VTT_SENSE

PSI#

AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15

AN33

CPU_VID0

AK35

CPU_VID1

AK33

CPU_VID2

AK34

CPU_VID3

AL35

CPU_VID4

AL33

CPU_VID5

AM33

CPU_VID6

AM35

PM_DPRSLPVR_R

AM34

G15

VTT_TEST TBD

AN35

AJ34 AJ35

B15 A15

I_MON <80>

VCCSENSE VSSSENSE

VTT_SENSE TP_VSS_SENSE_VTT

C060410UF/6.3V C060410UF/6.3V

C060110UF/6.3V C060110UF/6.3V

C060210UF/6.3V C060210UF/6.3V

12

C068710UF/6.3V@C068710UF/6.3V 12

@

12

C061722UF/6.3V C061722UF/6.3V

Intel use 22u

SP0601 R0402SP0601 R0402

SP0602 R0402SP0602 R0402

T0632T0632

1

T0631T0631

1

C060610UF/6.3V C060610UF/6.3V 12

+VTT_CPU

C068810UF/6.3V@C068810UF/6.3V 12

@

12

C061822UF/6.3V C061822UF/6.3V

+VCORE

C060810UF/6.3V C060810UF/6.3V 12

C068910UF/6.3V@C068910UF/6.3V 12 @

12

1 2

12

C061110UF/6.3V@C061110UF/6.3V 12 @

R0602

R0602 100Ohm

100Ohm 1%

1%

R0603

R0603 100Ohm

100Ohm 1%

1%

C061510UF/6.3V@C061510UF/6.3V

C061310UF/6.3V@C061310UF/6.3V

12

@

+VTT_CPU

VCCSENSE <80> VSSSENSE <80>

+VTT_CPU

C061610UF/6.3V@C061610UF/6.3V 12 @

C0690

C0691

12

@

1500PF/50V

reserve for emi

R1.4--5

PM_PSI# <80>

CPU_VID[0:6] <19>

PM_DPRSLPVR <80>

+VGFX_CORE

C0693

C0695

C0692

C0695

C0694

C0696

12

@

1500PF/50V

12

+

@

CE0601

330UF/2.5V

1500PF/50V

CE0601

12

12 C065022UF/6.3V@C065022UF/6.3V

@

12

C064922UF/6.3V C 064922UF/6.3V

C061910UF/6.3V C 061910UF/6.3V

C065122UF/6.3V@C065122UF/6.3V

C064822UF/6.3V C 064822UF/6.3V

@

DG R0.8,P368

+VTT_CPU

12

C065422UF/6.3V C 065422UF/6.3V

C065522UF/6.3V@C065522UF/6.3V

@

+VTT_CPU

+VCORE

Intel use 22u

12

C065922UF/6.3V@C065922UF/6.3V

C065722UF/6.3V C 065722UF/6.3V

C065622UF/6.3V C 065622UF/6.3V

C065822UF/6.3V@C065822UF/6.3V

@

Intel use 22u

Decoupling guide from Intel

VCORE 22uF * 16pcs

10uF * 16pcs 470uF * 6pcs (2 no stuff)

12

C0632

C0633

22UF/6.3V

10UF/6.3V

+VTT_CPU

+VCORE

+1.8VS

+VGFX_CORE

U0301G

AT21 AT19 AT18

AT16 12 C062010UF/6.3V C 062010UF/6.3V

AR21

AR19

AR18

AR16

AP21

AP19

AP18

AP16

AN21

AN19

AN18

AN16

AM21

AM19

AM18

AM16

AL21 AL19 AL18

AL16 AK21 AK19 AK18 AK16

AJ21

AJ19

AJ18

AJ16 AH21 AH19 AH18 AH16

J24 J23

H25

K26

J27 J26

J25 H27 G28 G27 G26 F26 E26 E25

SOCKET989

12

C0634

C0634 22UF/6.3V

22UF/6.3V

+1.5V

VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36

VTT1_45 VTT1_46 VTT1_47

VTT1_48 VTT1_49 VTT1_50 VTT1_51 VTT1_52 VTT1_53 VTT1_54 VTT1_55 VTT1_56 VTT1_57 VTT1_58

12

C0635

C0635 10UF/6.3V

10UF/6.3V

+VTT_CPU <3,25,26,32,57,82>

+1.5V <3,16,57,83>

+VCORE <57,80>

+1.8VS <26,57,85>

+VGFX_CORE <57,86,91>

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

GRAPHICS

GFX_DPRSLPVR

GRAPHICS VIDs

FDI PEG & DMI

12

C0636

C0636 22UF/6.3V

22UF/6.3V

DDR3 - 1.5V RAILS

POWER

1.1V1.8V

12

C0637

C0637 22UF/6.3V

22UF/6.3V

VAXG_SENSE

GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6]

GFX_VR_EN

GFX_IMON

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18

VTT0_59 VTT0_60 VTT0_61 VTT0_62

VTT1_63 VTT1_64 VTT1_65 VTT1_66 VTT1_67 VTT1_68

VCCPLL1 VCCPLL2 VCCPLL3

12

C0638

C0638 22UF/6.3V

22UF/6.3V

AR22 AT22

GVR_VID0

AM22

GVR_VID1

AP22

GVR_VID2

AN22

GVR_VID3

AP23

GVR_VID4

AM23

GVR_VID5

AP24

GVR_VID6

AN24

GFX_VRON_EN

AR25

GFXVR_DPRSLPVR_R

AT25 AM24

AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1

P10 N10 L10 K10

J22 J20 J18 H21 H20 H19

L26 L27 M26

12

C0639

C0639 22UF/6.3V

22UF/6.3V

VCC_AXG_SENSE < 86> VSS_AXG_SENSE <86>

GVR_VID[0:6] <86>

R0618 10KOhmR0618 10KOhm

1 2

R0605 4.7KOhm@R0605 4.7KOhm@

1 2

SP0603 R0402SP0603 R0402

SP0604 R0402SP0604 R0402

GVR_PWR_MON <86>

C06211UF/10V C06211UF/10V

C06221UF/10V C06221UF/10V

12

C0627

C0626

10UF/6.3V

@

12

C0664

C0665

22UF/6.3V

@

Intel use 22u

12

C06291UF/10V@C06291UF/10V

C06672.2UF/10V C 06672.2UF/10V

C06281UF/10V C06281UF/10V

@

+VTT_CPU

R1.2--11

12

follow EC Team suggestion 09-14 kurt

12

R0606 4.7KOhmR0606 4.7KOhm

C06241UF/10V@C06241UF/10V

C06231UF/10V C06231UF/10V

12

C06684.7UF/6.3V@C06684.7UF/6.3V

C068522UF/6.3V@C068522UF/6.3V

C06251UF/10V@C06251UF/10V

12

@

DG R0.8,P367 1xbuck Stuffing option

+VTT_CPU

+1.8VS

Intel 1.8V CAP.

C066622UF/6.3V C 066622UF/6.3V

1u: 2/2

2.2u: 1/1

4.7u: 1/1 330u:1/1

GFX_VR_ON <30,91>

1 2

+1.5V

12

C068622UF/6.3V C068622UF/6.3V

+

12

CE0604330UF/2V+CE0604330UF/2V

GFXVR_DPRSLPVR <86>

12

C0641

C0641 22UF/6.3V

22UF/6.3V

12

C0670

C0670 22UF/6.3V

22UF/6.3V

12

C0678

C0678 22UF/6.3V

22UF/6.3V

3

12

C0642

C0642 22UF/6.3V

22UF/6.3V

@

12

C0671

C0671 10UF/6.3V

10UF/6.3V

12

C0679

C0679 22UF/6.3V

22UF/6.3V

12

C0643

C0643 22UF/6.3V

22UF/6.3V

C0672

C0672 22UF/6.3V

22UF/6.3V

C0680

C0680 10UF/6.3V

10UF/6.3V

12

C0644

C0644 10UF/6.3V

10UF/6.3V

C0673

C0673 22UF/6.3V

22UF/6.3V

C0681

C0681 22UF/6.3V

22UF/6.3V

12

C0640

12

C0640 22UF/6.3V

22UF/6.3V

C0669

C0669 22UF/6.3V

22UF/6.3V

C0677

C0677 10UF/6.3V

10UF/6.3V @

@

SOCKET989

A A

5

4

12

C0645

C0645 22UF/6.3V

22UF/6.3V

C0674

C0674 22UF/6.3V

22UF/6.3V

C0682

C0682 10UF/6.3V

10UF/6.3V

12

C0647

C0647 10UF/6.3V

10UF/6.3V

C0675

C0675 22UF/6.3V

22UF/6.3V

C0683

C0683 22UF/6.3V

22UF/6.3V

12

C0676

C0676 22UF/6.3V

22UF/6.3V

12

C0684

C0684 10UF/6.3V

10UF/6.3V @

@

2

BG1\HW1

Size Project Name

C

H36Y_U30X10

Date: Sheet of

H36Y_U30X10

Title :

Engineer:

1

CPU(4)_PWR

Kuansheng Yang

6 99Monday, May 10, 2010

Rev

1.0

5

D D

C C

4

3

2

1

B B

A A

Title :

CPU(5)_XDP

Kuansheng Yang

Engineer:

BG1\HW1

Size Project Name

C

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

H36Y_U30X10

1

Kuansheng Yang

7 99Monday, May 10, 2010

Rev

1.0

5

D D

C C

4

3

2

1

B B

A A

Title :

NB(1)_****

Kuansheng Yang

1

Kuansheng Yang

8 99Monday, May 10, 2010

Rev

1.0

Engineer:

BG1\HW 1

Size Project Name

Custom

Date: Sheet of

5

4

3

2

Date: Sheet of

H36Y_U30X10

Engineer:

5

D D

C C

4

3

2

1

B B

A A

Title :

NB(2)_****

Kuansheng Yang

1

Kuansheng Yang

9 99Monday, May 10, 2010

Rev

1.0

Engineer:

BG1\HW 1

Size Project Name

Custom

Date: Sheet of

5

4

3

2

Date: Sheet of

H36Y_U30X10

Engineer:

5

D D

C C

4

3

2

1

B B

A A

Title :

NB(3)_****

Kuansheng Yang

1

Kuansheng Yang

10 99Monday, May 10, 2010

Rev

1.0

Engineer:

BG1\HW 1

Size Project Name

Custom

Date: Sheet of

5

4

3

2

Date: Sheet of

H36Y_U30X10

Engineer:

5

D D

C C

4

3

2

1

B B

A A

Title :

NB(4)_****

Kuansheng Yang

1

Kuansheng Yang

11 99Monday, May 10, 2010

Rev

1.0

Engineer:

BG1\HW 1

Size Project Name

Custom

Date: Sheet of

5

4

3

2

Date: Sheet of

H36Y_U30X10

Engineer:

5

D D

C C

4

3

2

1

B B

A A

Title :

NB(5)_****

Kuansheng Yang

1

Kuansheng Yang

12 99Monday, May 10, 2010

Rev

1.0

Engineer:

BG1\HW 1

Size Project Name

Custom

Date: Sheet of

5

4

3

2

Date: Sheet of

H36Y_U30X10

Engineer:

5

D D

C C

4

3

2

1

B B

A A

Title :

NB(6)_****

Kuansheng Yang

1

Kuansheng Yang

13 99Monday, May 10, 2010

Rev

1.0

Engineer:

BG1\HW 1

Size Project Name

Custom

Date: Sheet of

5

4

3

2

Date: Sheet of

H36Y_U30X10

Engineer:

5

D D

C C

4

3

2

1

B B

A A

Title :

Engineer:

BG1\HW1

Size Project Name

A

Date: Sheet of

5

4

3

Date: Sheet of

H36Y_U30X10

2

Engineer:

NB(7)_****

Kuansheng Yang

14 99Monday, May 10, 2010

1

Rev

1.0

5

D D

C C

4

3

2

1

B B

A A

Title :

Engineer:

BG1\HW1

Size Project Name

A

Date: Sheet of

5

4

3

Date: Sheet of

H36Y_U30X10

2

Engineer:

NB(8)_****

Kuansheng Yang

15 99Monday, May 10, 2010

1

Rev

1.0

5

D D

M_A_A[15:0]<4>

M_CLK_DDR0

M_CLK_DDR#0

M_CLK_DDR1

M_CLK_DDR#1

C C

PLACE CLOSE TO SODIMM

SMBus Slave Address: A0H

B B

12

C1621

C1621 10PF/50V

10PF/50V @

@

C1626

C1626 10PF/50V

10PF/50V @

@

12

1%

R1603

R1603 150Ohm

150Ohm

12

R1604

R1604 150Ohm

150Ohm

M_A_DQS[7:0]<4>

M_A_DQS#[7:0]<4>

@

1%

@

M_A_DM[7:0]<4>

M_CLK_DDR1<4>

M_CLK_DDR#1<4>

M_CLK_DDR0<4>

M_CLK_DDR#0<4>

M_A_WE#<4> M_A_RAS#< 4> M_A_CAS#< 4>

M_A_BS2<4> M_A_BS1<4> M_A_BS0<4>

RN1601A

RN1601A RN1601B

RN1601B

JP1601

JP1601 3MM_OPEN_5MIL

3MM_OPEN_5MIL

2

112

M_CS#1<4> M_CS#0<4>

M_ODT1<4> M_ODT0<4>

M_CKE1<4> M_CKE0<4>

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

12

10KOHM

34

10KOHM

M_A_DQS7 M_A_DQS#7 M_A_DQS6 M_A_DQS#6 M_A_DQS5 M_A_DQS#5 M_A_DQS4 M_A_DQS#4 M_A_DQS3 M_A_DQS#3 M_A_DQS2 M_A_DQS#2 M_A_DQS1 M_A_DQS#1 M_A_DQS0 M_A_DQS#0

M_A_DM7 M_A_DM6 M_A_DM5 M_A_DM4 M_A_DM3 M_A_DM2 M_A_DM1 M_A_DM0

SMB_CLK_S<17,28,29,44,53> M_DRAMRST# <3,17> SMB_DAT_S<17,28,29,44,53>

+1.5V_DDR3+1.5V

+1.5V_DDR3

12

J1601A

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12/BC#

119

A13

80

A14

78

A15

102

CK1

104

CK1#

101

CK0

103

CK0#

121

S1#

114

S0#

120

ODT1

116

ODT0

113

WE#

110

RAS#

115

CAS#

79

BA2

108

BA1

109

BA0

74

CKE1

73

CKE0

201

SA1

197

SA0

188

DQS7

186

DQS#7

171

DQS6

169

DQS#6

154

DQS5

152

DQS#5

137

DQS4

135

DQS#4

64

DQS3

62

DQS#3

47

DQS2

45

DQS#2

29

DQS1

27

DQS#1

12

DQS0

10

DQS#0

187

DM7

170

DM6

153

DM5

136

DM4

63

DM3

46

DM2

28

DM1

11

DM0

202

SCL

200

SDA

DDR3_DIMM_204P

1202-002O000

H:9.2mm

+

CE1603

@

CE1603

@

220UF/4V

220UF/4V ESR=40mOhm/Ir=1.9A

ESR=40mOhm/Ir=1.9A

4

M_A_DQ[63:0] <4>

0

1

2

3

4

5

6

7

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

RESET#

M_A_DQ5

5

DQ0

M_A_DQ1

7

DQ1

M_A_DQ7

15

DQ2

M_A_DQ6

17

DQ3

M_A_DQ0

4

DQ4

M_A_DQ4

6

DQ5

M_A_DQ3

16

DQ6

M_A_DQ2

18

DQ7

M_A_DQ12

21

DQ8

M_A_DQ8

23

DQ9

M_A_DQ10

33

M_A_DQ15

35

M_A_DQ13

22

M_A_DQ9

24

M_A_DQ14

34

M_A_DQ11

36

M_A_DQ16

39

M_A_DQ17

41

M_A_DQ18

51

M_A_DQ22

53

M_A_DQ21

40

M_A_DQ20

42

M_A_DQ23

50

M_A_DQ19

52

M_A_DQ24

57

M_A_DQ25

59

M_A_DQ30

67

M_A_DQ31

69

M_A_DQ28

56

M_A_DQ29

58

M_A_DQ27

68

M_A_DQ26

70

M_A_DQ36

129

M_A_DQ33

131

M_A_DQ39

141

M_A_DQ38

143

M_A_DQ37

130

M_A_DQ32

132

M_A_DQ34

140

M_A_DQ35

142

M_A_DQ41

147

M_A_DQ44

149

M_A_DQ45

157

M_A_DQ46

159

M_A_DQ43

146

M_A_DQ40

148

M_A_DQ42

158

M_A_DQ47

160

M_A_DQ53

163

M_A_DQ49

165

M_A_DQ55

175

M_A_DQ50

177

M_A_DQ52

164

M_A_DQ48

166

M_A_DQ54

174

M_A_DQ51

176

M_A_DQ61

181

M_A_DQ60

183

M_A_DQ63

191

M_A_DQ58

193

M_A_DQ56

180

M_A_DQ57

182

M_A_DQ59

192

M_A_DQ62

194

30

3

+1.5V_DDR3

Layout Note: Place these caps near SO DIMM 0

PM_EXTTS#0<3,17>

M_VREFCA_DIMM0

M_VREFDQ_DIMM0

12

C1605

0.1UF/10V

C1624

2.2UF/10V

2.2UF/10V @

@

C1622

2.2UF/10V

2.2UF/10V @

@

R1602

0Ohm

12

C1606

0.1UF/10V

12

@

12

C1623

0.1UF/10V

12

C1625

0.1UF/10V

2

+1.5V_DDR3

M_VREFCA_DIMM0

M_VREFDQ_DIMM0

J1601B

75

VDD1 VDD381VDD4 VDD587VDD6 VDD793VDD8

99

VDD9

105

VDD11

111

VDD13

117

VDD15

123

VDD17

2

VSS1

8

VSS3

13

VSS5

19

VSS7

25

VSS9

31

VSS11

37

VSS13

43

VSS15

48

VSS17

54

VSS19

60

VSS21

65

VSS23

71

VSS25

127

VSS27

133

VSS29

138

VSS31

144

VSS33

150

VSS35

155

VSS37

161

VSS39

167

VSS41

172

VSS43

178

VSS45

184

VSS47

189

VSS49

195

VSS51

198

EVENT#

125

TEST

77

NC1

122

NC2

126

VREFCA

1

VREFDQ

DDR3_DIMM_204P

+0.75VS

12

+1.5V

+1.5V <3,6,57,83>

+1.5V_DDR3 <17,18>

+0.75VS <17,57,83>

+3VS

+3VS <3,17,20,21,22,23,24,25,26,27,28,29,30,32,36,37,43,44,45,46,48,50,51,53, 56,57,66,80,86,91,92>

M_VREFCA_DIMM0 <18>

M_VREFDQ_DIMM0 <18>

12

C1607

0.1UF/10V

C1619

C1619 1UF/6.3V

1UF/6.3V @

@

+3VS

12

+1.5V_DDR3

12

C1614

2.2UF/10V

2.2UF/10V @

@

C1608

0.1UF/10V

C1616

C1616 1UF/6.3V

1UF/6.3V

VDD2

VDD10 VDD12 VDD14 VDD16 VDD18

VSS2 VSS4 VSS6

VSS8 VSS10 VSS12 VSS14 VSS16 VSS18 VSS20 VSS22 VSS24 VSS26 VSS28 VSS30 VSS32 VSS34 VSS36 VSS38 VSS40 VSS42 VSS44 VSS46 VSS48 VSS50 VSS52

GND1 GND2

NP_NC1 NP_NC2

VTT1

VTT2

VDDSPD

12

76 82 88 94 100 106 112 118 124

3 9 14 20 26 32 38 44 49 55 61 66 72 128 134 139 145 151 156 162 168 173 179 185 190 196

207 208

205 206

203 204

199

C1617

C1617 1UF/6.3V

1UF/6.3V

12

C1618

C1618 1UF/6.3V

1UF/6.3V @

@

+0.75VS

C1615

0.1UF/10V

12

1

+1.5V_DDR3

Layout Note: Place these caps near SO DIMM 0

12

C1609

C1609 10UF/6.3V

10UF/6.3V

A A

5

12

C1610

C1610 10UF/6.3V

10UF/6.3V

4

12

C1611

C1611 10UF/6.3V

10UF/6.3V

12

C1612

C1612 10UF/6.3V

10UF/6.3V @

@

12

C1613

C1613 10UF/6.3V

10UF/6.3V @

@

12

C1620

C1620 10UF/6.3V

10UF/6.3V @

@

Title :

DDR3(1)_SO-DIMM0

Kuansheng Yang

Engineer:

BG1\HW1

Size Project Name

C

Date: Sheet of

3

2

Date: Sheet of

Engineer:

H36Y_U30X10

1

Kuansheng Yang

16 99Monday, May 10, 2010

Rev

1.0

5

4

3

2

1

+1.5V

+1.5V_DDR3

+0.75VS

M_VREFCA_DIMM1

M_VREFDQ_DIMM1

D D

M_B_A[15:0]<4>

M_CLK_DDR2

M_CLK_DDR#2

M_CLK_DDR3

C C

M_CLK_DDR#3

PLACE CLOSE TO SODIMM

SMBus Slave Address: A4H

B B

12

C1720

C1720 10PF/50V

10PF/50V @

@

C1721

C1721 10PF/50V

10PF/50V @

@

12

1%

R1707

R1707 150Ohm

150Ohm

12

R1708

R1708 150Ohm

150Ohm

M_B_DQS[7:0]<4>

M_B_DQS#[7:0]<4>

@

1%

@

+3VS

M_B_DM[7:0]<4>

M_CLK_DDR3<4>

M_CLK_DDR#3<4>

M_CLK_DDR2<4>

M_CLK_DDR#2<4>

M_B_RAS#< 4> M_B_CAS#< 4>

M_B_BS2<4> M_B_BS1<4> M_B_BS0<4>

RN1701A

RN1701A RN1701B

RN1701B

+1.5V_DDR3

12

+

CE1703

CE1703 220UF/4V

220UF/4V @

@

ESR=40mOhm/Ir=1.9A

M_CS#3<4> M_CS#2<4>

M_ODT3<4> M_ODT2<4>

M_B_WE#<4>

M_CKE3<4> M_CKE2<4>

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

12

10KOHM

34

10KOHM

M_B_DQS7 M_B_DQS#7 M_B_DQS6 M_B_DQS#6 M_B_DQS5 M_B_DQS#5 M_B_DQS4 M_B_DQS#4 M_B_DQS3 M_B_DQS#3 M_B_DQS2 M_B_DQS#2 M_B_DQS1 M_B_DQS#1 M_B_DQS0 M_B_DQS#0

M_B_DM7 M_B_DM6 M_B_DM5 M_B_DM4 M_B_DM3 M_B_DM2 M_B_DM1 M_B_DM0

SMB_CLK_S<16,28,29,44,53> SMB_DAT_S<16,28,29,44,53>

J1701A

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12/BC#

119

A13

80

A14

78

A15

102

CK1

104

CK1#

101

CK0

103

CK0#

121

S1#

114

S0#

120

ODT1

116

ODT0

113

WE#

110

RAS#

115

CAS#

79

BA2

108

BA1

109

BA0

74

CKE1

73

CKE0

201

SA1

197

SA0

188

DQS7

186

DQS#7

171

DQS6

169

DQS#6

154

DQS5

152

DQS#5

137

DQS4

135

DQS#4

64

DQS3

62

DQS#3

47

DQS2

45

DQS#2

29

DQS1

27

DQS#1

12

DQS0

10

DQS#0

187

DM7

170

DM6

153

DM5

136

DM4

63

DM3

46

DM2

28

DM1

11

DM0

202

SCL

200

SDA

DDR3_DIMM_204P

1202-002H000

H:5.2mm

0

1

2

3

4

5

6

7

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

RESET#

M_B_DQ1

5

DQ0

M_B_DQ0

7

DQ1

M_B_DQ6

15

DQ2

M_B_DQ3

17

DQ3

M_B_DQ4

4

DQ4

M_B_DQ5

6

DQ5

M_B_DQ7

16

DQ6

M_B_DQ2

18

DQ7

M_B_DQ12

21

DQ8

M_B_DQ9

23

DQ9

M_B_DQ13

33

M_B_DQ15

35

M_B_DQ8

22

M_B_DQ10

24

M_B_DQ14

34

M_B_DQ11

36

M_B_DQ16

39

M_B_DQ21

41

M_B_DQ23

51

M_B_DQ22

53

M_B_DQ20

40

M_B_DQ17

42

M_B_DQ19

50

M_B_DQ18

52

M_B_DQ24

57

M_B_DQ25

59

M_B_DQ26

67

M_B_DQ31

69

M_B_DQ29

56

M_B_DQ28

58

M_B_DQ27

68

M_B_DQ30

70

M_B_DQ33

129

M_B_DQ37

131

M_B_DQ35

141

M_B_DQ38

143

M_B_DQ36

130

M_B_DQ32

132

M_B_DQ39

140

M_B_DQ34

142

M_B_DQ41

147

M_B_DQ44

149

M_B_DQ46

157

M_B_DQ47

159

M_B_DQ45

146

M_B_DQ40

148

M_B_DQ43

158

M_B_DQ42

160

M_B_DQ53

163

M_B_DQ50

165

M_B_DQ54

175

M_B_DQ55

177

M_B_DQ48

164

M_B_DQ52

166

M_B_DQ51

174

M_B_DQ49

176

M_B_DQ60

181

M_B_DQ57

183

M_B_DQ63

191

M_B_DQ62

193

M_B_DQ58

180

M_B_DQ56

182

M_B_DQ59

192

M_B_DQ61

194

30

M_B_DQ[63:0] <4>

Layout Note: Place these caps near SO DIMM 1

M_DRAMRST# <3,16>

+1.5V_DDR3

PM_EXTTS#0<3,16>

+1.5V <3,6,16,57,83>

+1.5V_DDR3 <16,18>

+0.75VS <16,57,83>

+3VS

+3VS <3,16,20,21,22,23,24,25,26,27,28,29,30,32,36,37,43,44,45,46,48,50,51,53, 56,57,66,80,86,91,92>

M_VREFCA_DIMM1 <18>

M_VREFDQ_DIMM1 <18>

J1701B

75

VDD1

12

C1705

0.1UF/10V

M_VREFCA_DIMM1

12

C1724

2.2UF/10V

2.2UF/10V @

@

M_VREFDQ_DIMM1

12

C1722

2.2UF/10V

2.2UF/10V @

@

12

C1706

0.1UF/10V

@

R1704 0Ohm

12

C1723

0.1UF/10V

C1725

0.1UF/10V

99 105 111 117 123

2

8 13 19 25 31 37 43 48 54 60 65 71

127 133 138 144 150 155 161 167 172 178 184 189 195

198 125

77

122

126

1

DDR3_DIMM_204P

VDD2 VDD381VDD4 VDD587VDD6 VDD793VDD8

VDD10

VDD9 VDD11

VDD12

VDD13

VDD14

VDD15

VDD16

VDD17

VDD18

VSS2

VSS1

VSS4

VSS3

VSS6

VSS5

VSS8

VSS7 VSS9

VSS10 VSS12

VSS11

VSS14

VSS13

VSS16

VSS15

VSS18

VSS17

VSS20

VSS19

VSS22

VSS21

VSS24

VSS23

VSS26

VSS25

VSS28

VSS27

VSS30

VSS29

VSS32

VSS31

VSS34

VSS33

VSS36

VSS35

VSS38

VSS37

VSS40

VSS39

VSS42

VSS41

VSS44

VSS43

VSS46

VSS45

VSS48

VSS47

VSS50

VSS49

VSS52

VSS51

GND1 EVENT#

GND2 TEST

NP_NC1

NC1

NP_NC2

NC2

VTT1 VTT2

VREFCA

VDDSPD

VREFDQ

+0.75VS

12

C1716

C1716 1UF/6.3V

1UF/6.3V

+1.5V_DDR3

76 82 88 94 100 106 112 118 124

3 9 14 20 26 32 38 44 49 55 61 66 72 128 134 139 145 151 156 162 168 173 179 185 190 196

207 208

205 206

203 204

199

12

C1717

C1717 1UF/6.3V

1UF/6.3V

12

C1707

0.1UF/10V

+0.75VS

12

C1715

0.1UF/10V

C1718

C1718 1UF/6.3V

1UF/6.3V @

@

12

C1708

0.1UF/10V

+3VS

12

C1714

2.2UF/10V

2.2UF/10V @

@

12

C1719

C1719 1UF/6.3V

1UF/6.3V @

@

+1.5V_DDR3

Layout Note: Place these caps near SO DIMM 1

12

C1710

C1710 10UF/6.3V

10UF/6.3V

12

C1711

C1711 10UF/6.3V

10UF/6.3V

12

C1709

C1709 10UF/6.3V

10UF/6.3V

A A

5

12

C1712

C1712 10UF/6.3V

10UF/6.3V @

@

12

C1713

C1713 10UF/6.3V

10UF/6.3V @

@

4

12

C1726

C1726 10UF/6.3V

10UF/6.3V @

@

Title :

DDR3(2)_SO-DIMM1

Kuansheng Yang

Engineer:

BG1\HW1

Size Project Name

C

Date: Sheet of

3

2

Date: Sheet of

Engineer:

H36Y_U30X10

1

Kuansheng Yang

17 99Monday, May 10, 2010

Rev

1.0

5

DDR3 Vref

Intel Document Number: 400755 Calpella Clarksfield DDR3 SO-DIMM VREFDQ

D D

Platform Design Guide Change Details

4

3

+1.5V_DDR3

M_VREFCA_DIMM0

M_VREFDQ_DIMM0

M_VREFCA_DIMM1

M_VREFDQ_DIMM1

0.75V_VTT_REF_R

+1.5V_DDR3 <16,17>

M_VREFCA_DIMM0 <16>

M_VREFDQ_DIMM0 <16>

M_VREFCA_DIMM1 <17>

M_VREFDQ_DIMM1 <17>

+3V

+3V <24,33,40,43,45,53,54,56,57,61,91>

0.75V_VTT_REF_R <83>

2

1

12

M1

+1.5V_DDR3

C1801

0.1UF/10V

0.1UF/10V @

@

1 2

12

R1807

R1807 1KOHM

1KOHM 1%

1% @

@

R1808

R1808 1KOHM

1KOHM 1%

1% @

@

1 2

R1809 0OhmR1809 0Ohm

M_VREF_DDR30.75V_VTT_REF_R

For DDR3_VREF command & address.

R1802,R1803 are always mount.

DIMM0_VREF_DQ<5>

DIMM1_VREF_DQ<5>

SP1801 R0603SP1801 R0603

SP1802 R0603SP1802 R0603

SP1803 R0603SP1803 R0603

SP1804 R0603SP1804 R0603

R1805 0Ohm@R1805 0Ohm@

R1806 0Ohm@R1806 0Ohm@

1 2

M_VREFCA_DIMM0

M_VREFDQ_DIMM0

M_VREFCA_DIMM1

M_VREFDQ_DIMM1

Default

M1: Fixed SO-DIMM VREF_DQ (Default Stuffing)

*Option: Mount=R1801,R1802,R1803,R1804,R1809

Unmount=R1805,R1806,R1807,R1808,C1801

C C

M2 M3

M2: Programmable SO-DIMM VREFDQ on

motherboard– New Requirement

*Option: Mount=R1801,R1802,R1803,R1804,R1807,R1808,C1801

Unmount=R1805,R1806,R1809

*Range from 600 to 900 mV

*Default startup value needs to adhere to JEDEC spec.

(power sequencing and +/-1% of Vdd/2)

Note: Use voltage divider instead of I2C solution.

B B

M3: Processor Generated SO-DIMM VREFDQ

– New Requirement

Option: Mount=R1802,R1803,R1805,R1806

Unmount=R1801,R1804,R1809,R1807,R1808,C1801

A A

Title :

DDR3(3)_CA/DQ Voltage

Kuansheng Yang

Engineer:

BG1\HW1

Size Project Name

C

Date: Sheet

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

H36Y_U30X10

1

Kuansheng Yang

of

18 99Monday, May 10, 2010

Rev

1.0

5

Block Diagram

4

3

SMB_CLK_S3 SMB_DAT_S3

2

1

SB

D D

CPU

CPU_VID0~6

ASM8272

VR_ID0~6

Voltage Regulator

UCOC

CLK Gen.

OC/UC pin Inter nal Pull Down

Reserved 0 ohm R to bypass

C C

+VTT_CPU

CPU_VID6<6> CPU_VID5<6> CPU_VID4<6> CPU_VID3<6> CPU_VID2<6> CPU_VID1<6> CPU_VID0<6>

CPU_VID5 CPU_VID4 CPU_VID3 CPU_VID2 CPU_VID1 CPU_VID0

SP1901 R0402SP1901 R0402 SP1902 R0402SP1902 R0402 SP1903 R0402SP1903 R0402 SP1904 R0402SP1904 R0402 SP1905 R0402SP1905 R0402 SP1906 R0402SP1906 R0402 SP1907 R0402SP1907 R0402

VR_VID6CPU_VID6

12

VR_VID5

12

VR_VID4

12

VR_VID3

12

VR_VID2

12

VR_VID1

12

VR_VID0

12

VR_VID6 <80> VR_VID5 <80> VR_VID4 <80> VR_VID3 <80> VR_VID2 <80> VR_VID1 <80> VR_VID0 <80>

+VTT_CPU <3,6,25,26,32,57,82>

+3VS

+3VS <3,16,17,20,21,22,23,24,25,26,27,28,29,30,32,36,37,43,44,45,46,48,50,51,53,56,57,66, 80,86,91,92>

B B

A A

R1.4--2

Title :

VID Controller

Kuansheng Yang

Engineer:

BG1\HW1

Size Project Name

C

Date: Sheet of

5

4

3

2

Date: Sheet

Engineer:

H36Y_U30X10

1

Kuansheng Yang

of

19 99Monday, May 10, 2010

Rev

1.0

5

4

3

2

1

RTC battery

+RTC_BAT

12

R2001 1KOhmR2001 1KOhm

12

J2001

BATT_HOLDER_2P

1220-004B000

D D

+VCC_RTC

R2004 20KOhmR2004 20KOhm

R2005

1MOhm

1 2

C C

B B

Strap information:

HDA_SPKR: No reboot strap

HDA_DOCK_EN#:

A A

SPI_MOSI: iTPM strap.

GND

RTCRST# RC delay should be 18ms~25ms

12

R2003 20KOhmR 2003 20KOhm

GND GND

12

TPM Settings

Clear ME RTC

Registers Keep ME RTC Registers

ACZ_BCLK_AUD<36> ACZ_SYNC_AUD<36> ACZ_RST#_AUD<36,37>

ACZ_SDOUT_AUD<36>

PCH_SPI_OV<30,44>

Low: Disable. High:Enable

1.Flash descriptor security: Sampled low: override Sampled high: in effect.

2.GPIO33 low on the rising edg e of PWROK, Will also disable Intel ME.

Mount R2015: Enable Unmount R2015: Disable(defaul t)

12

C2004

1UF/10V

C2005

1UF/10V

1

2

1

JRST2002

1

2

SGL_JUMP

SGL_JUMP @

@

2

GNDGND

JRST2002

Shunt

Open (Default)

JRST2001

SGL_JUMP

SGL_JUMP @

@

1

G

+3VS

GND

1 2

3

D

S

2

1 2

33OHM

3 4

33OHM

5 6

33OHM

7 8

33OHM

R3037

R3037 10KOhm

10KOhm @

@

Q2001

2N7002ET1G

Connector Type 1217-001L000

Request by CSC for CMOS clear function

CMOS Settings

D2001

1

2

BAT54C

Clear CMOS

Keep CMOS

RN2001A

RN2001A RN2001B

RN2001B RN2001C

RN2001C RN2001D

RN2001D

HDA_DOCK_EN#

+VCC_RTC+3VA+RTCBAT

3

12

C2003

1UF/10V

GND

JRST2001

Shunt Open (Default)

Adding layout test point for boundary scan Jervis 2009/11/09

HDA_SYNC: Select VCCVRM 1.5V o r 1.8V

ACZ_BCLK ACZ_SYNC ACZ_RST# ACZ_SDOUT

@

1 2

R2029 100KOHM

GND

T2011T2011

T2012T2012

T2013T2013

+3VM_SPI

1

SB_SPKR<36>

C2001

GND

18PF/50V

C2002

GND

18PF/50V

R2020

1 2

+3VS

1KOhm @

ACZ_SDIN0_AUD<36>

SPI_CLK<28,44>

SPI_CS#0<28,44>

SPI_CS#1<28,44>

SPI_SI<28,44>

@

R2015 1KOhm

12

14

X2001

2

3

32.768Khz

12

+VCC_RTC

SP2001 R0402SP2001 R0402

1 2

SP2002 R0402SP2002 R0402

1 2

12

T2002T2002

T2003T2003

T2004T2004

T2008T2008

T2009T2009

T2010T2010

1

SPI_SO<28,44>

12

R2002

10MOhm

R2006

12

330KOhm

HDA_DOCK_EN#

DGPU_PWR_EN_R

PCH_JTAG_TCK_BUF

SB_SPICLK

SB_SPICS0#

SB_SPICS1#

SPI_MOSI

X1_RTC X2_RTC

RTCRST#

SRTCRST#

SM_INTRUDER#

SM_INTVRMEN

ACZ_BCLK

ACZ_SYNC

ACZ_RST#

ACZ_SDOUT

+VTT_PCH_VCCIO

U2001A

B13

RTCX1

D13

RTCX2

C14

RTCRST#

D17

SRTCRST#

A16

INTRUDER#

A14

INTVRMEN

A30

HDA_BCLK

D29

HDA_SYNC

P1

SPKR

C30

HDA_RST#

G30

HDA_SDIN0

F30

HDA_SDIN1

E32

HDA_SDIN2

F32

HDA_SDIN3

B29

HDA_SDO

H32

HDA_DOCK_EN#/GPIO33

J30

HDA_DOCK_RST#/GPIO13

M3

JTAG_TCK

K3

JTAG_TMS

K1

JTAG_TDI

J2

JTAG_TDO

J4

TRST#

BA2

SPI_CLK

AV3

SPI_CS0#

AY3

SPI_CS1#

AY1

SPI_MOSI

AV1

SPI_MISO

IBEXPEAK-M

+1.05VS

+VCC_RTC

+1.05VM_ORG

+3VM_SPI

+1.05VS <26,27,29,57,80,82>

+VCC_RTC <27>

+3VS

+3VS <3,16,17,21,22,23,24,25,26,27,28,29,30,32,36,37,43,44,45,46,48,50,51,53,56,57,66,80, 86,91,92>

+1.05VM_ORG <27>

+VTT_PCH_VCCIO <26,27>

+3VM_SPI <28,44>

D33

FWH0/LAD0

B33

FWH1/LAD1

C32

FWH2/LAD2

A32

FWH3/LAD3

RTCIHD A

SPI JTAG

FWH4/LFRAME#

LDRQ1#/GPIO23

LPC

SATA

SATA0GP/GPIO21

SATA1GP/GPIO19

LDRQ0#

SERIRQ

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1RXN SATA1RXP SATA1TXN SATA1TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATAICOMPO

SATAICOMPI

SATALED#

C34

PCH_DRQ#0

A34

LPC_DRQ#1

F34

AB9

AK7 AK6 AK11 AK9

AH6 AH5 AH9 AH8

AF11 AF9 AF7 AF6

EDS 1.0: SATA port2,port3 may not be available in all PCH SKUs.

AH3 AH1 AF3 AF1

AD9 AD8 AD6 AD5

AD3 AD1 AB3 AB1

AF16

AF15

T3

Y9

V1

SATA_COMP

1 2

R2007 37.4OhmR2007 37.4Ohm

1 2

R2025 10KOhmR2025 10KOhm

SATA0GP

SATA1GP

INT_SERIRQ

SATA0GP

SATA1GP

Pull up to +3VS per 395136_Checklist V1.6

1 2

R2026 10KOhmR2026 10KOhm

1 2

R2027 10KOhm

@

1 2

R2028 10KOhm

@

1 1

+VTT_PCH_VCCIO

+3VS

LPC_AD0 <30,44> LPC_AD1 <30,44> LPC_AD2 <30,44> LPC_AD3 <30,44>

LPC_FRAME# <30,44>

T2005T2005 T2006T2006

INT_SERIRQ < 30,44>

SATA_RXN0 <51> SATA_RXP0 <51> SATA_TXN0 <51> SATA_TXP0 <51>

SATA_RXN1 <51> SATA_RXP1 <51> SATA_TXN1 <51> SATA_TXP1 <51>

SATA_RXN5 <66> SATA_RXP5 <66> SATA_TXN5 <66> SATA_TXP5 <66>

SATA_LED# <56>

HDD1

ODD

ESATA

Title :

PCH(1)_SATA,IHDA,RTC,LPC

Kuansheng Yang

Engineer:

BG1\HW1

Size Project Name

C

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

H36Y_U30X10

1

Kuansheng Yang

20 99Monday, May 10, 2010

Rev

1.0

5

PCIE5: PCIE-->CB

D D

PCIE_RXN2_WLAN<53>

PCIE_RXP2_WLAN<53> PCIE_TXN2_WLAN<53> PCIE_TXP2_WLAN<53>

PCIE_RXN3_NEWCARD<43>

PCIE_RXP3_NEWCARD<43> PCIE_TXN3_NEWCARD<43> PCIE_TXP3_NEWCARD<43>

PCIE_RXN4_USB30<54>

PCIE_RXP4_USB30<54> PCIE_TXN4_USB30<54> PCIE_TXP4_USB30<54>

C2103 0.1UF/16VC2103 0.1UF/16V

1 2

C2104 0.1UF/16VC2104 0.1UF/16V

1 2

C2105 0.1UF/16VC2105 0.1UF/16V

1 2

C2106 0.1UF/16VC2106 0.1UF/16V

1 2

C2110 0.1UF/16VC2110 0.1UF/16V

1 2

C2111 0.1UF/16VC2111 0.1UF/16V

1 2

PCIE_TXN2_WLAN_C PCIE_TXP2_WLAN_C

PCIE_TXN3_NEWCARD_C PCIE_TXP3_NEWCARD_C

PCIE_TXN4_USB30_C PCIE_TXP4_USB30_C

Ken 0318

PCIE_RXN6_GLAN<33>

PCIE_RXP6_GLAN<33> PCIE_TXN6_GLAN<33> PCIE_TXP6_GLAN<33>

EDS 1.0: PCIE7,8 may not be availiable in all PCH SKUs.

C C

CLK_PCIE_WLAN#_PCH<53>

CLK_PCIE_WLAN_PCH<53>

CLKREQ2_WLAN#<53>

CLK_PCIE_NEWCARD#_PCH<43>

CLK_PCIE_NEWCARD_PCH<43>

CLKREQ3_NEWCARD#<43,44>

CLK_PCIE_USB30#_PCH<54>

CLK_PCIE_USB30_PCH<54>

CLK_REQ4_USB30#<54> +VTT_PCH_ORG

Ken 0318

CLK_PCIE_LAN#<33>

CLK_PCIE_LAN<33>

CLK_REQ5_LAN#<33>

B B

A A

C2108 0.1UF/16VC2108 0.1UF/16V

1 2

C2109 0.1UF/16VC2109 0.1UF/16V

1 2

T2101T2101

1

T2102T2102

1

SP2101 R0402SP2101 R0402

1 2

SP2102 R0402SP2102 R0402

1 2

SP2103 R0402SP2103 R0402

1 2

SP2104 R0402SP2104 R0402

1 2

SP2105 R0402SP2105 R0402

1 2

SP2106 R0402SP2106 R0402

1 2

SP2112 R0402SP2112 R0402

1 2

SP2111 R0402SP2111 R0402

1 2

SP2113 R0402SP2113 R0402

1 2

SP2107 R0402SP2107 R0402

1 2

SP2108 R0402SP2108 R0402

1 2

T2104T2104

1

PCIE_TXN6_GLAN_C PCIE_TXP6_GLAN_C

CLK_REQ0#

CLK_REQ1#

CLK_PCH_SRC2_N CLK_PCH_SRC2_P

CLK_PCH_SRC3_N CLK_PCH_SRC3_P

CLK_PCH_SRC4_N

CLK_PCH_SRC4_P

CLK_REQ4#

CLK_PCH_SRC5_N CLK_PCH_SRC5_P

CLKREQ_GLAN#_R

U2001B

BG30

PERn1

BJ30

PERp1

BF29

PETn1

BH29

PETp1

AW30

PERn2

BA30

PERp2

BC30

PETn2

BD30

PETp2

AU30

PERn3

AT30

PERp3

AU32

PETn3

AV32

PETp3

BA32

PERn4

BB32

PERp4

BD32

PETn4

BE32

PETp4

BF33

PERn5

BH33

PERp5

BG32

PETn5

BJ32

PETp5

BA34

PERn6

AW34

PERp6

BC34

PETn6

BD34

PETp6

AT34

PERn7

AU34

PERp7

AU36

PETn7

AV36

PETp7

BG34

PERn8

BJ34

PERp8

BG36

PETn8

BJ36

PETp8

AK48

CLKOUT_PCIE0N

AK47

CLKOUT_PCIE0P

P9

PCIECLKRQ0#/GPIO73

AM43

CLKOUT_PCIE1N

AM45

CLKOUT_PCIE1P

U4

PCIECLKRQ1#/GPIO18

AM47

CLKOUT_PCIE2N

AM48

CLKOUT_PCIE2P

N4

PCIECLKRQ2#/GPIO20

AH42

CLKOUT_PCIE3N

AH41

CLKOUT_PCIE3P

A8

PCIECLKRQ3#/GPIO25

AM51

CLKOUT_PCIE4N

AM53

CLKOUT_PCIE4P

M9

PCIECLKRQ4#/GPIO26

AJ50

CLKOUT_PCIE5N

AJ52

CLKOUT_PCIE5P

H6

PCIECLKRQ5#/GPIO44

AK53

CLKOUT_PEG_B_N

AK51

CLKOUT_PEG_B_P

P13

PEG_B_CLKRQ#/GPIO56

IBEXPEAK-M

4

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

CLKIN_DMI_N CLKIN_DMI_P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

B9

H14

C8

J14

C6

G8

M14

E10

G12

T13

T11

T9

H1

AD43 AD45

AN4 AN2

AT1 AT3

AW24 BA24

AP3 AP1

F18 E18

AH13 AH12

P41

J42

AH51 AH53

AF38

T45

P43

T42

N50

SMBALERT#/GPIO11

SML0ALERT#/GPIO60

SMBus

SML1ALERT#/GPIO74

SML1CLK/GPIO58

SML1DATA/GPIO75

PCI-E*

C-Link

PEG_A_CLKRQ#/GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N

PEG

CLKOUT_DMI_P

CLKOUT_DP_N/CLKOUT_BCLK1_N CLKOUT_DP_P/CLKOUT_BCLK1_P

CLKIN_BCLK_N

CLKIN_BCLK_P

CLKIN_DOT_96N

CLKIN_DOT_96P

CLKIN_SATA_N/CKSSCD_N CLKIN_SATA_P/CKSSCD_P

CLKIN_PCILOOPBACK

Clock Inputs from CLK BUFFER

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

Clock Flex

EXT_SCI#

SCL_3A

SDA_3A

RTLAN_DSM_EN

SML0_CLK

SML0_DAT

SML1ALERT#

SML1_CLK

SML1_DAT

CLKREQ_PEG#

CLK_PCIE_PEG#_PCH_L CLK_PCIE_PEG_PCH_L

T2115T2115

1

T2116T2116

1

Adding layout test point for boundary scan Jervis 2009/11/09

XCLK_COMP

R2117 90.9OhmR2117 90.9Ohm

CLK_OUT0

CLK_OUT1

CLK_OUT2

CLK_OUT3

3

T2106T2106

1

T2107T2107

1

T2108T2108

1

T2105T2105

1

SP2109

SP2109 1 2 1 2

SP2110

T2117T2117

1

1 2

T2111T2111

1

T2112T2112

1

T2109T2109

1

R2118 22OhmR2118 22Ohm

1 2

GND

12

R0402

R0402 R0402

R0402

C2107

C2107 10PF/50V

10PF/50V

EXT_SCI# <30>

SCL_3A <28>

SDA_3A <28>

SML1_CLK <28,56>

SML1_DAT <28,56>

CL_CLK <53>

CL_DATA <53>

CL_RST# <53>

T2110T2110

1

T2113T2113

1

T2114T2114

1

CLK_DMI#_PCH <3> CLK_DMI_PCH <3>

CLK_DMI# <29> CLK_DMI <29>

CLK_PCH_BCLK# <29> CLK_PCH_BCLK <29>

CLK_DOT96# <29>

CLK_DOT96 <29>

CLK_SATA# <29> CLK_SATA <29>

CLK_ICH14 <29>

CLK_PCI_FB < 24>

+VTT_PCH_ORG

+3VSUS_ORG

To EC

R2120 0Ohm

@

R2151

1MOhm

1 2

05061930 KEN xtal co-lay

CLK_USB48_CR <40>

12

+3VSUS

1 2

2

+3VSUS <27,30,33,34,81,92>

+3VS

+3VS <3,16,17,20,22,23,24,25,26,27,28,29,30,32,36,37,43,44,45,46,48,50,51,53,56,57,66,80, 86,91,92>

+VTT_PCH_ORG <22,26,27>

+3VSUS_ORG <22,24,25,27>

EXT_SCI#

SCL_3A

SDA_3A

RTLAN_DSM_EN

SML0_CLK

SML0_DAT

SML1_CLK

SML1_DAT

SML1ALERT#

PCH CLKREQ Setting:

Not connected to device.

CLK_REQ0#

CLK_REQ4_USB30#

Connected to device.

Default : Clock free run. (PD 10K). Reserver 10K PU for power saving purpose.

CLK_REQ1#

CLKREQ2_WLAN#

CLKREQ3_NEWCARD#

CLKREQ_GLAN#_R

CLK_REQ5_LAN#

CLKREQ2_WLAN#

CLKREQ3_NEWCARD#

CLKREQ_PEG#

CLK_REQ4_USB30#

X2102

25Mhz

GND

C2101

1 2

27PF/50V

4

X2101 25Mhz

2

C2102

1 3

1 2

27PF/50V

@

05052100 KEN

GND

1

+3VSUS_ORG

R2130 10KOhmR2130 10KOhm

1 2

R2132 2.2KOhmR2132 2.2KOhm

1 2

R2133 2.2KOhmR2133 2.2KOhm

1 2

R2131 10KOhmR2131 10KOhm

1 2

R2140 2.2KOhm@R2140 2.2KOhm@

1 2

R2138 2.2KOhm@R2138 2.2KOhm@

1 2

R2136 4.7KOhmR2136 4.7KOhm

1 2

R2137 4.7KOhmR2137 4.7KOhm

1 2

R2142 10KOhmR2142 10KOhm

1 2

R2126 10KOhmR2126 10KOhm

1 2

R2135 10KOhmR2135 10KOhm

1 2

R2125 10KOhmR2125 10KOhm

1 2

R2123 10KOhm@R2123 10KOhm@

1 2

R2124 10KOhm@R2124 10KOhm@

1 2

R2129 10KOhmR2129 10KOhm

1 2

R2128 10KOhm@R2128 10KOhm@

1 2

R2134 10KOhm@R2134 10KOhm@

1 2

R2144 10KOhmR2144 10KOhm

1 2

R2143 10KOhmR2143 10KOhm

1 2

R2139 10KOhmR2139 10KOhm

1 2

R2127 10KOhm@R2127 10KOhm@

1 2

+3VSUS_ORG

+3VS

+3VSUS_ORG

GND

Title :

PCH(2)_PCIE,CLK,SMB,PEG

Kuansheng Yang

Engineer:

BG1\HW1

Size Project Name

C

Date: Sheet of

5

4

3

2

Date: Sheet

Engineer:

H36Y_U30X10

1

Kuansheng Yang

of

21 99Monday, May 10, 2010

Rev

1.0

5

+3VS

D D

C C

PM_CLKRUN#

PM_PWROK

PM_RI#

PM_BATLOW#

PCIE_WAKE#

ME_PM_SLP_M#

ME_SUSPWRDNACK

ME_AC_PRESENT

ME_PM_SLP_LAN#

1 2

R2248 8.2KOhmR2248 8.2KOhm

1 2

R2259 10KOhmR2259 10KOhm

1 2

R2251 10KOhmR2251 10KOhm

1 2

R2252 8.2KOhmR2252 8.2KOhm

1 2

R2253 1KOhmR2253 1KOhm

@

1 2

R2254 10KOhm

1 2

R2265 10KOhmR2265 10KOhm

1 2

R2264 10KOhmR2264 10KOhm

@

1 2

R2266 10KOhm

GND

+3VSUS_ORG

STUFF for IAMT

4

Adding layout t est point for boundary s can Jervis 2009/11/ 09

PM_RSMRST#_R PM_PWROK PM_MEPWROK LAN_RST# PM_PWROK_R

3

pre-ES1 not sup port Reversal Featur e

DMI_RXN0<3> DMI_RXN1<3> DMI_RXN2<3> DMI_RXN3<3>

DMI_RXP0<3> DMI_RXP1<3> DMI_RXP2<3> DMI_RXP3<3>

DMI_TXN0<3> DMI_TXN1<3> DMI_TXN2<3> DMI_TXN3<3>

DMI_TXP0<3> DMI_TXP1<3> DMI_TXP2<3> DMI_TXP3<3>

DMI_COMP

+VTT_PCH_ORG

T2210T2210

1

T2211T2211

1

T2212T2212

1

T2213T2213

1

T2214T2214

1

ALL_SYSTEM_PWRGD<30,92>

PM_PWROK<30>

H_DRAM_PWRGD<3>

PM_RSMRST#<30>

ME_SUSPWRDNACK<30>

PM_PWRBTN#<30>

ME_AC_PRESENT<30>

12

R2203 49.9OhmR2203 49.9Ohm

R2258 0Ohm@R2258 0Ohm@

SP2201 R0402SP2201 R0402

SP2213 R0402SP2213 R0402

R2267 0Ohm

GND

R2255 10KOhmR 2255 10KOhm

SP2202 R0402SP2202 R0402

SP2203 R0402SP2203 R0402

SP2204 R0402SP2204 R0402

SP2214 R0402SP2214 R0402

1 2

@

1 2

T2201T2201

T2202T2202

+3VS

R2256

1KOhm

1 2

SYS_RESET#

PM_PWROK_R

12

PM_MEPWROK

12

LAN_RST#

12

PM_RSMRST#_R

ACPRESENT_R

PM_BATLOW#

1

PM_RI#

1

U2001C

BC24

DMI0RXN

BJ22

DMI1RXN

AW20

DMI2RXN

BJ20

DMI3RXN

BD24

DMI0RXP

BG22

DMI1RXP

BA20

DMI2RXP

BG20

DMI3RXP

BE22

DMI0TXN

BF21

DMI1TXN

BD20

DMI2TXN

BE18

DMI3TXN

BD22

DMI0TXP

BH21

DMI1TXP

BC20

DMI2TXP

BD18

DMI3TXP

BH25

DMI_ZCOMP

BF25

DMI_IRCOMP

T6

SYS_RESET#

M6

SYS_PWROK

B17

PWROK

K5

MEPWROK

A10

LAN_RST#

D9

DRAMPWROK

C16

RSMRST#

M1

SUS_PWR_DN_ACK/GPIO30

P5

PWRBTN#

P7

ACPRESENT/GPIO31

A6

BATLOW#/GPIO72

F14

RI#

IBEXPEAK-M

2

BA18

FDI_RXN0

BH17

FDI_RXN1

BD16

FDI_RXN2

BJ16

FDI_RXN3

BA16

FDI_RXN4

BE14

FDI_RXN5

BA14

FDI_RXN6

BC12

FDI_RXN7

BB18

FDI_RXP0

BF17

FDI_RXP1

BC16

FDI_RXP2

BG16

FDI_RXP3

AW16

FDI_RXP4

BD14

FDI_RXP5

BB14

FDI_RXP6

BD12

FDI_RXP7

BJ14

FDI_INT

BF13

FDI_FSYNC0

DMI

FDI

DMI

FDI

CLKRUN#/GPIO32

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

System Power Management

SLP_LAN#/GPIO29

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

WAKE#

SLP_S4#

SLP_S3#

SLP_M#

TP23

PMSYNCH

BH13

BJ12

BG14

J12

Y1

P8

F3

E4

H7

P12

K8

N2

BJ10

F6

SLP_LAN#_R

FDI_INT_R

FDI_FSYNC0_R

FDI_FSYNC1_R

FDI_LSYNC0_R

FDI_LSYNC1_R

PM_SUS_STAT#

SUS_CLK

SLP_S5#

SLP_S4#_R

SLP_S3#_R

SLP_M#_R

PM_SLP_DSW#

SP2205 R0402SP2205 R0402

1 2

SP2206 R0402SP2206 R0402

1 2

SP2207 R0402SP2207 R0402

1 2

SP2208 R0402SP2208 R0402

1 2

SP2209 R0402SP2209 R0402

1 2

SP2210 R0402SP2210 R0402

1 2

SP2211 R0402SP2211 R0402

1 2

SP2212 R0402SP2212 R0402

1 2

SP2215 R0402SP2215 R0402

1 2

1

FDI_TXN0 <3> FDI_TXN1 <3> FDI_TXN2 <3> FDI_TXN3 <3> FDI_TXN4 <3> FDI_TXN5 <3> FDI_TXN6 <3> FDI_TXN7 <3>

FDI_TXP0 <3> FDI_TXP1 <3> FDI_TXP2 <3> FDI_TXP3 <3> FDI_TXP4 <3> FDI_TXP5 <3> FDI_TXP6 <3> FDI_TXP7 <3>

FDI_INT <3>

FDI_FSYNC0 <3>

FDI_FSYNC1 <3>

FDI_LSYNC0 <3>

FDI_LSYNC1 <3>

PCIE_WAKE# <33,44,53, 54>

PM_CLKRUN# <30>

T2203T2203

1

T2204T2204

1

T2205T2205

1

PM_SUSC# <30>

PM_SUSB# <30>

ME_PM_SLP_M# <30>

T2206T2206

1

PM_SYNC# <3>

ME_PM_SLP_LAN# <30>

B B

+3VSUS_ORG

+VTT_PCH_ORG

A A

5

4

3

+3VSUS_ORG <21,24,25,27>

+3VS

+3VS <3,16,17,20,21,23,24,25,26,27,28,29,30,32,36,37,43,44,45,46,48,50,51,53,56,57,66,80, 86,91,92>

+VTT_PCH_ORG <21,26,27>

2

Title :

PCH(3)_FDI,DMI,SYS PWR

Kuansheng Yang

Engineer:

BG1\HW1

Size Project Name

C

Date: Sheet of

Engineer:

H36Y_U30X10

1

Kuansheng Yang

22 99Monday, May 10, 2010

Rev

1.0

5

LCD_BKEN_PCH<45>

D D

+3VS

L_CTRL_CLK

L_CTRL_DATA

C C

1 2

R2322 10KOhmR2322 10KOhm

1 2

R2323 10KOhmR2323 10KOhm

12

R2312

150Ohm

12

R2317

R2316

150Ohm

GND

L_VDDEN_PCH<45>

L_BKLT_CTRL<45>

EDID_CLK_PCH<45>

EDID_DATA_PCH<45>

LVDS_LCLKN_PCH<45> LVDS_LCLKP_PCH<45>

LVDS_L0N_PCH<45> LVDS_L1N_PCH<45> LVDS_L2N_PCH<45>

LVDS_L0P_PCH<45> LVDS_L1P_PCH<45> LVDS_L2P_PCH<45>

LVDS_UCLKN_PCH<45> LVDS_UCLKP_PCH<45>

LVDS_U0N_PCH< 45> LVDS_U1N_PCH< 45> LVDS_U2N_PCH< 45>

LVDS_U0P_PCH<45> LVDS_U1P_PCH<45> LVDS_U2P_PCH<45>

DDC_CLK_PCH<46>

DDC_DATA_PCH<46>

CRT_HSYNC_PCH<46>

CRT_VSYNC_PCH<46>

CRB0.9 Change

4

SP2301 R0402SP2301 R0402

1 2

SP2302 R0402SP2302 R0402

1 2

T2301T2301 T2302T2302

SP2303 R0402SP2303 R0402

GND

CRB R0.9,DG R0.8: 1K+/-0.5% Intel checklist recommand:

1.02K PD resistor to 0.5%

L_CTRL_CLK

1

L_CTRL_DATA

1

R2301 2.37KOHMR2301 2.37KOHM

12

R2302 0Ohm@R2302 0Ohm@

12

1 2

B_PCH G_PCH R_PCH

SP2304 R0402SP2304 R0402

1 2

SP2305 R0402SP2305 R0402

1 2

12

R2321

R2321 1KOHM

1KOHM

0.5%

GND GND

AB48

AB46

AP39 AP41

AT43 AT42

AV53 AV51

BB47 BA52 AY48 AV47

BB48 BA50 AY49 AV48

AP48 AP47

AY53 AT49 AU52 AT53

AY51 AT48 AU50 AT51

AA52 AB53 AD53

AD48 AB51

T48 T47

Y48

Y45

V48

V51 V53

Y53 Y51

U2001D

L_BKLTEN L_VDD_EN

L_BKLTCTL

L_DDC_CLK L_DDC_DATA

L_CTRL_CLK L_CTRL_DATA

LVD_IBG LVD_VBG

LVD_VREFH LVD_VREFL

LVDSA_CLK# LVDSA_CLK

LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3

LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3

LVDSB_CLK# LVDSB_CLK

LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3

LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3

CRT_BLUE CRT_GREEN CRT_RED

CRT_DDC_CLK CRT_DDC_DATA

CRT_HSYNC CRT_VSYNC

DAC_IREF CRT_IRTN

IBEXPEAK-M

3

+3VS

+3VS <3,16,17,20,21,22,24,25,26,27,28,29,30,32,36,37,43,44,45,46,48,50,51,53,56,57,66,80, 86,91,92>

SDVO_INTN SDVO_INTP

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_AUXN DDPD_AUXP

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

BJ46 BG46

BJ48 BG48

BF45 BH45

DDPB_HPD: Vil2 max=0.8V,

T51 T53

BG44 BJ44 AU38

DDPB_0N

BD42

DDPB_0P

BC42

DDPB_1N

BJ42

DDPB_1P

BG42

DDPB_2N

BB40

DDPB_2P

BA40

DDPB_3N

AW38

DDPB_3P

BA38

Y49 AB49

BE44 BD44 AV40

BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36

U50 U52

BC46 BD46 AT38

BJ40 BG40 BJ38 BG38 BF37 BH37 BE36 BD36

Vih2 min=2V

C2304 0.1UF/16VC2304 0.1UF/16V C2305 0.1UF/16VC2305 0.1UF/16V C2306 0.1UF/16VC2306 0.1UF/16V C2307 0.1UF/16VC2307 0.1UF/16V C2308 0.1UF/16VC2308 0.1UF/16V C2309 0.1UF/16VC2309 0.1UF/16V C2310 0.1UF/16VC2310 0.1UF/16V C2311 0.1UF/16VC2311 0.1UF/16V

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

CRT

DisPlay Port Disable: (For discrete graphic)

1. NC:

ALL

HDMI_DDC_CLK_PCH <48> HDMI_DDC_DATA_PCH <48>

12 12 12 12 12 12 12 12

2

HDMI_HPD_PCH <48>

HDMI_TXN2_PCH <48> HDMI_TXP2_PCH <48> HDMI_TXN1_PCH <48> HDMI_TXP1_PCH <48> HDMI_TXN0_PCH <48> HDMI_TXP0_PCH <48> HDMI_CLKN_PCH <48> HDMI_CLKP_PCH <48>

1

SDVO

Display Port BDisplay Port CDisplay Port D

B B

CRT_B_PCH<46>

CRT_G_PCH<46>

CRT_R_PCH<46>

CRT_B_PCH

CRT_G_PCH

CRT_R_PCH

JP2301

SHORT_PIN

SHORT_PIN JP2302

JP2302

SHORT_PIN

SHORT_PIN JP2303

JP2303

SHORT_PIN

B_PCH

12

G_PCH

12

R_PCH

12

LVDS Disable: (For discrete graphic)

1. NC:

LVDSA_DATA [3:0], LVDSA_DATA# [3:0],

LVDSA_CLK, LVDSA_CLK#, LVDSB_DATA [3:0],

LVDSB_DATA# [3:0], LVDSB_CLK, LVDSB_CLK#

L_VDD_EN, L_BKLTEN, L_BKLTCTL, LVD_VREFH

LVD_VREFL, LVD_IBG, LVD_VBG

2. Connected to GND:

VccALVDS,VccTX_LVDS

CRT Disable: (For discrete graphic)

1. NC:

CRT_RED,CRT_GREEN,CRT_BLUE

CRT_HSYCN,CRT_VSYNC

2. 1-kΩ ±0.5% pull-down to GND:

A A

5

4

3

DAC_IREF

3. Connected to GND:

CRT_ITRN

4. Connect to +V3.3:

VCCADAC

Title :

PCH(4)_DP,LVDS,CRT

Kuansheng Yang

Engineer:

BG1\HW1

Size Project Name

C

Date: Sheet

Date: Sheet of

2

Date: Sheet of

Engineer:

H36Y_U30X10

1

Kuansheng Yang

of

23 99Monday, May 10, 2010

Rev

1.0

5

4

3

2

1

+3VSUS

U2001E

H40

AD0

N34

AD1

C44

AD2

A38

AD3

C36

AD4

J34

AD5

A40

AD6

D45

AD7

PLT_RST#

E36 H48 E40 C40 M48 M45 F53 M40 M43 J36 K48 F40 C42 K46 M51 J52 K51 L34 F42 J40 G46 F44 M47 H36

J50 G42 H47 G34

G38 H51 B37 A44

F51 A46 B45 M53

F48 K45 F36 H53

B41 K53 A36 A48

K6

E44 E50

A42 H44 F46 C46

D49

D41 C48

M7

D5

N52 P53 P46 P51 P48

AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31

C/BE0# C/BE1# C/BE2# C/BE3#

PIRQA# PIRQB# PIRQC# PIRQD#

REQ0# REQ1#/GPIO50 REQ2#/GPIO52 REQ3#/GPIO54

GNT0# GNT1#/GPIO51 GNT2#/GPIO53 GNT3#/GPIO55

PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5

PCIRST#

SERR# PERR#

IRDY# PAR DEVSEL# FRAME#

PLOCK#

STOP# TRDY#

PME#

PLTRST#

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4

IBEXPEAK-M

PCI

NV_DQ0/NV_IO0 NV_DQ1/NV_IO1 NV_DQ2/NV_IO2 NV_DQ3/NV_IO3 NV_DQ4/NV_IO4 NV_DQ5/NV_IO5 NV_DQ6/NV_IO6 NV_DQ7/NV_IO7 NV_DQ8/NV_IO8 NV_DQ9/NV_IO9

NV_DQ10/NV_IO10

NVRAM

NV_DQ11/NV_IO11 NV_DQ12/NV_IO12 NV_DQ13/NV_IO13 NV_DQ14/NV_IO14 NV_DQ15/NV_IO15

NV_WR#0_RE# NV_WR#1_RE#

USB

D D

PCI_INTA# PCI_INTB# PCI_INTC# PCI_INTD#

PCI_REQ0# PCI_REQ1# PCI_REQ2#

C C

change to PCI_CLK4 to sync ICS364

R240422Ohm R240422Ohm

CLK_PCI_FB<21>

CLK_KBCPCI_PCH<30>

CLK_DEBUG<44>

B B

CLK_DBGPCI2<44>

C2403

C2403 10PF/50V

10PF/50V

1 2

12

R240522Ohm R240522Ohm

12

R240622Ohm R240622Ohm

12

R240722Ohm R240722Ohm

12

PCI_REQ3#

PCI_GNT0# PCI_GNT1#

T2403T2403

PCI_GNT2#

1

PCI_GNT3#

PCI_INTE# PCI_INTF# PCI_INTG# PCI_INTH#

PCI_SERR# PCI_PERR#

PCI_IRDY#

PCI_DEVSEL# PCI_FRAME#

PCI_LOCK#

PCI_STOP# PCI_TRDY# USBRBIAS_PN

CLK_PCI_FB_R CLK_KBCPCI_PCH_R CLK_DEBUG_R CLK_DBG_R

NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3

NV_DQS0 NV_DQS1

NV_ALE NV_CLE

NV_RCOMP

NV_RB#

NV_WE#_CK0 NV_WE#_CK1

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P

USBP10N

USBP10P

USBP11N

USBP11P

USBP12N

USBP12P

USBP13N

USBP13P

USBRBIAS#

USBRBIAS

OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43

OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14

AY9 BD1 AP15 BD8

AV9 BG8

AP7 AP6 AT6 AT9 BB1 AV6 BB3 BA4 BE4 BB6 BD6 BB7 BC8 BJ8 BJ6 BG6

BD3 AY6

AU2

AV7

AY8 AY5

AV11 BF5

H18 J18 A18 C18 N20 P20 J20 L20 F20 G20 A20 C20 M22 N22 B21 D21 H22 J22 E22 F22 A22 C22 G24 H24 L24 M24 A24 C24

B25

D25

N16 J16 F16 L16 E14 G16 F12 T15

USB_PN3 USB_PP3 USB_PN4 USB_PP4

USB_PN6 USB_PP6 USB_PN7 USB_PP7

1 1 1 1

T2416T2416 T2417T2417 T2414T2414 T2415T2415

T2410T2410 T2411T2411 T2412T2412 T2413T2413

1 2

Ken 100319

R2411

22.6Ohm

USB_PN0 <52> USB_PP0 <52> USB_PN1 <52> USB_PP1 <52> USB20_PN2 <54> USB20_PP2 <54>

USB_PN5 <43> USB_PP5 <43>

USB_PN8 <40> USB_PP8 <40> USB_PN9 <53> USB_PP9 <53> USB_PN10 <53> USB_PP10 <53> USB_PN11 <52> USB_PP11 <52> USB_PN12 <61> USB_PP12 <61> USB_PN13 <52> USB_PP13 <52>

GND

+3VSUS_ORG

USB 2.0 port

USB 3.0 port

Newcard

Card Reader

WiFi/WiMax

3G

X10

BT

Camera

Place within 500 mils of PCH

3 4

10KOHM

7 8

10KOHM

1 2

10KOHM

5 6

10KOHM

5 6

10KOHM

3 4

10KOHM

7 8

10KOHM

1 2

10KOHM

+3VSUS <27,30,33,34,81,92>

+3VS

+3VS <3,16,17,20,21,22,23,25,26,27,28,29,30,32,36,37,43,44,45,46,48,50,51,53, 56,57,66,80,86,91,92>

+3V

+3V <33,40,43,45,53,54,56,57,61,91>

+3VSUS_ORG <21,22,25,27>

swap Kurt 09-15

+3VSUS_ORG

RN2408B

RN2408B RN2408D

RN2408D RN2407A

RN2407A RN2408C

RN2408C RN2407C

RN2407C RN2407B

RN2407B RN2407D

RN2407D RN2408A

RN2408A

PCI_INTG# PCI_INTC# PCI_INTA# PCI_INTE# PCI_PERR# PCI_LOCK# PCI_DEVSEL# PCI_SERR# PCI_IRDY# PCI_STOP# PCI_INTD# PCI_REQ2# PCI_REQ0# PCI_INTB# PCI_INTF# PCI_REQ3# PCI_REQ1# PCI_FRAME# PCI_TRDY# PCI_INTH#

1 2

8.2KOHM

3 4

8.2KOHM

5 6

8.2KOHM

7 8

8.2KOHM

1 2

8.2KOHM

3 4

8.2KOHM

5 6

8.2KOHM

7 8

8.2KOHM

1 2

8.2KOHM

3 4

8.2KOHM

5 6

8.2KOHM

7 8

8.2KOHM

1 2

8.2KOHM

3 4

8.2KOHM

5 6

8.2KOHM

7 8

8.2KOHM

1 2

8.2KOHM

3 4

8.2KOHM

5 6

8.2KOHM

7 8

8.2KOHM

RN2401A

RN2401A RN2401B

RN2401B RN2401C

RN2401C RN2401D

RN2401D RN2402A

RN2402A RN2402B

RN2402B RN2402C

RN2402C RN2402D

RN2402D RN2403A

RN2403A RN2403B

RN2403B RN2403C

RN2403C RN2403D

RN2403D RN2404A

RN2404A RN2404B

RN2404B RN2404C

RN2404C RN2404D

RN2404D RN2405A

RN2405A RN2405B

RN2405B RN2405C

RN2405C RN2405D

RN2405D

+3VS

GND

GNT0#,GNT1#: Boot BIOS Strap. GNT3#:

Boot BIOS Strap

PCI_GNT0#PCI_GNT1# Boot BIOS Location

0 0

0 1

1 0

1 1 SPI

Sampled on rising edge of PWROK.

A A

PCI_GNT0#<44>

PCI_GNT1#< 44>

PCI_GNT1#

5

LPC

PCI

Reserved

@

1 2

R2440 1KOhm

1 2

R2441 1KOhm

@

(PCH)

GND

A16 swap override Strap/ Top-Block swap override jumper

Low=Enabled A16 swap override/

Top-Block swap override

High=Default

PCI_GNT3#PCI_GNT0#

@

1 2

R2444 1KOhm

4

+3V

U2401

A

1

5

VCC

B

GND

R2413 0Ohm

B

2

3 4

GND

NC7SZ08P5X_NL

@

1 2

Y

BUF_PLT_RST# <3,30,32,33,43,53,54>

2

Title :

PCH(5)_PCI,NVRAM,USB

Kuansheng Yang

Engineer:

BG1\HW1

Size Project Name

C

Date: Sheet

Date: Sheet of

Engineer:

H36Y_U30X10

1

Kuansheng Yang

24 99Monday, May 10, 2010

Rev

1.0

of

GND

PLT_RST#

3

5

ID0 ID1 SKU

+3VS

12

D D

12

@

GND

C C

EXT_SMI#

PM_LANPHY_EN

R2532 10KOhmR2532 10KOhm

@

R2534 10KOhm

Pull up to +3VS per 395136_Checklist V1.6

STP_PCI#

GPIO0

EMAIL_LED

DOCKING_DET#

XIDE_BAY_IN#

DGPU_PWR_EN

DGPU_HOLD_RST#

DGPU_PRSNT#

DGPU_PWR_OK

B B

PCH_TEMP_ALERT#

DGPU_PWR_EN#

R2548 10KOhm

R2546 10KOhm

R2545 10KOhm

R2542 10KOhm

R2541 10KOhm

R2539 10KOhm

R2540 10KOhm

R2543 10KOhm

R2547 10KOhm

R2550 10KOhmR2550 10KOhm

R2549 10KOhm

R2544 10KOhm

R2536

10KOhm

R2535

10KOhm

@

R2538

@

10KOhm

12

R2537

10KOhm

GND

+3VSUS_ORG

12

+3VS

12

GND

------------------------------0 0 CFD_Non-IAMT 0 1 CFD_IAMT 1 0 AUB_Non-IAMT 1 1 AUB_IAMT

PCB_ID0

PCB_ID1

GPIO 27:Enable VCCVRM,Low=disable.

Default internal pull up.

Remove PWR_OK_VGA net

4

+3VSUS

GPIO0

1

DOCKING_DET#

1

DGPU_PWR_EN

1

XIDE_BAY_IN#

1

PM_LANPHY_EN

1

DGPU_HOLD_RST#

DGPU_PWR_OK

VRM_EN

1

STP_PCI#

1

SATA_CLK_REQ#

DGPU_PWR_EN#

DGPU_PRSNT#

PCB_ID0

PCB_ID1

CLK_REQ6#

1

CLK_REQ7#

1

EMAIL_LED

1

PCH_TEMP_ALERT#

T2531T2531

1

T2532T2532

1

T2533T2533

1

T2534T2534

1

T2535T2535

1

T2536T2536

1

T2537T2537

1

T2538T2538

1

T2540T2540

1

T2541T2541

1

T2542T2542

1

T2543T2543

1

T2544T2544

1

T2545T2545

1

T2549T2549

1

T2550T2550

1

T2551T2551

1

T2552T2552

1

T2553T2553

1

T2554T2554

1

T2555T2555

1

T2556T2556

1

T2557T2557

1

T2558T2558

1

T2559T2559

1

T2560T2560

1

T2562T2562

1

T2561T2561

1

+3VS

+3VS <3,16,17,20,21,22,23,24,26,27,28,29,30,32,36,37,43,44,45,46,48,50,51,53, 56,57,66,80,86,91,92>

+3VSUS <27,30,33,34,81,92>

+VTT_CPU <3,6,26,32,57,82>

+3VSUS_ORG <21,22,24,27>

T2593T2593

T2590T2590

T2502T2502

T2592T2592

EXT_SMI#<30,44,54>

T2594T2594

BT_LED<56>

WLAN_LED<56>

USB_SEL<54>

T2595T2595

WLAN_ON<53>

T2501T2501

CAP_RST#_ICH<56>

T2597T2597

T2598T2598

T2599T2599

PCH_TEMP_ALERT#<30>

BT_ON<61>

+VTT_CPU

+3VSUS_ORG

TP_VSS_NCTF1 TP_VSS_NCTF2 TP_VSS_NCTF3 TP_VSS_NCTF4 TP_VSS_NCTF5 TP_VSS_NCTF6 TP_VSS_NCTF7 TP_VSS_NCTF8

TP_VSS_NCTF10 TP_VSS_NCTF11 TP_VSS_NCTF12 TP_VSS_NCTF13 TP_VSS_NCTF14 TP_VSS_NCTF15

TP_VSS_NCTF18 TP_VSS_NCTF19 TP_VSS_NCTF20 TP_VSS_NCTF21 TP_VSS_NCTF22 TP_VSS_NCTF23 TP_VSS_NCTF24 TP_VSS_NCTF25 TP_VSS_NCTF26 TP_VSS_NCTF27 TP_VSS_NCTF28 TP_VSS_NCTF29 TP_VSS_NCTF30 TP_VSS_NCTF31

3

U2001F

Y3

BMBUSY#/GPIO0

C38

TACH1/GPIO1

D37

TACH2/GPIO6

J32

TACH3/GPIO7

F10

GPIO8

K9

LAN_PHY_PWR_CTRL/GPIO12

T7

GPIO15

AA2

SATA4GP/GPIO16

F38

TACH0/GPIO17

Y7

SCLOCK/GPIO22

H10

GPIO24

AB12

GPIO27

V13

GPIO28

M11

STP_PCI#/GPIO34

V6

GPIO35

AB7

SATA2GP/GPIO36

AB13

SATA3GP/GPIO37

V3

SLOAD/GPIO38

P3

SDATAOUT0/GPIO39

H3

PCIECLKRQ6#/GPIO45

F1

PCIECLKRQ7#/GPIO46

AB6

SDATAOUT1/GPIO48

AA4

SATA5GP/GPIO49/TEMP_ALERT#

F8

GPIO57

A4

Vss_NCTF_1

A49

Vss_NCTF_2

A5

Vss_NCTF_3

A50

Vss_NCTF_4

A52

Vss_NCTF_5

A53

Vss_NCTF_6

B2

Vss_NCTF_7

B4

Vss_NCTF_8

B52

Vss_NCTF_9

B53

Vss_NCTF_10

BE1

Vss_NCTF_11

BE53

Vss_NCTF_12

BF1

Vss_NCTF_13

BF53

Vss_NCTF_14

BH1

Vss_NCTF_15

BH2

Vss_NCTF_16

BH52

Vss_NCTF_17

BH53

Vss_NCTF_18

BJ1

Vss_NCTF_19

BJ2

Vss_NCTF_20

BJ4

Vss_NCTF_21

BJ49

Vss_NCTF_22

BJ5

Vss_NCTF_23

BJ50

Vss_NCTF_24

BJ52

Vss_NCTF_25

BJ53

Vss_NCTF_26

D1

Vss_NCTF_27

D2

Vss_NCTF_28

D53

Vss_NCTF_29

E1

Vss_NCTF_30

E53

Vss_NCTF_31

IBEXPEAK-M

CLKOUT_BCLK0_N/CLKOUT_PCIE8N

CLKOUT_BCLK0_P/CLKOUT_PCIE8P

GPIO

NCTF

RSVD

MISC

CPU

CLKOUT_PCIE6N CLKOUT_PCIE6P

CLKOUT_PCIE7N CLKOUT_PCIE7P

A20GATE

RCIN#

PROCPWRGD

THRMTRIP#

TP18

TP10

TP11

TP19

NC_1

NC_2

NC_3

NC_4

NC_5

INIT3_3V#

TP24

PECI

TP14

TP15

TP16

TP17

TP12

TP13

TP1

TP2

TP3

TP4

TP5

TP6

TP7

TP8

TP9

AH45 AH46

AF48 AF47

U2

AM3

AM1

BG10

T1

BE10

BD10

BA22

AW22

BB22

AY45

AY46

AV43

AV45

H12

M32

N32

M30

N30

AF13

M18

N18

AK41

AK42

AJ24

AA23

AB45

AB38

AB42

AB41

T39

P6

C10

PECI

PM_THRMTRIP#

TP9_PCH

TP10_PCH

TP11_PCH

TP14_PCH

TP15_PCH

TP16_PCH

TP17_PCH

TP18_PCH

TP19_PCH

TP_PCH_NC1

TP_PCH_NC2

TP_PCH_NC3

TP_PCH_NC4

TP_PCH_NC5

INT3_3V#

TP_PCH_SST

2

SP2501 R0402SP2501 R0402

1 2

T2588T2588

1

T2589T2589

1

T2582T2582

1

T2584T2584

1

T2583T2583

1

T2585T2585

1

T2587T2587

1

T2586T2586

1

T2563T2563

1

T2564T2564

1

T2566T2566

1

T2580T2580

1

T2581T2581

1

T2565T2565

1

T2567T2567

1

T2568T2568

1

T2569T2569

1

T2570T2570

1

T2571T2571

1

T2572T2572

1

T2573T2573

1

T2574T2574

1

T2575T2575

1

T2576T2576

1

T2579T2579

1

T2577T2577

1

A20GATE <30>

BCLK_CPU_N_PCH <3>

BCLK_CPU_P_PCH <3>

H_PECI <3>

RCIN# <30>

H_CPUPWRGD <3>

1 2

R2501 56OhmR2501 56Ohm

+VTT_CPU

R2525

56Ohm

1 2

close to U2001.BD10

1

H_THRMTRIP# <3,32>

DGPU_PWR_OK

SATA_CLK_REQ#

08'WW50 MoW

R1.4--1

A A

@

12

R2533 10KOhm

12

R2531 10KOhmR2531 10KOhm

5

GND

Title :

PCH(6)_CPU,GPIO,MISC

Kuansheng Yang

Engineer:

BG1\HW1

Size Project Name

C

Date: Sheet

Date: Sheet of

4

3

2

Date: Sheet of

Engineer:

H36Y_U30X10

1

Kuansheng Yang

of

25 99Monday, May 10, 2010

Rev

1.0

5

U2001H

AB16

Vss_355

AA19

Vss_3

AA20

Vss_4

AA22

Vss_5

AM19

Vss_94

AA24

Vss_6

AA26

Vss_7

AA28

Vss_8

AA30

Vss_9

AA31

Vss_10

AA32

Vss_11

AB11

Vss_13

AB15

Vss_14

AB23

Vss_15

D D

C C

B B

AB30

Vss_16

AB31

Vss_17

AB32

Vss_18

AB39

Vss_19

AB43

Vss_20

AB47

Vss_21

AB5

Vss_22

AB8

Vss_23

AC2

Vss_24

AC52

Vss_25

AD11

Vss_26

AD12

Vss_357

AD16

Vss_28

AD23

Vss_29

AD30

Vss_31

AD31

Vss_32

AD32

Vss_33

AD34

Vss_34

AU22

Vss_1

AD42

Vss_35

AD46

Vss_36

AD49

Vss_38

AD7

Vss_40

AE2

Vss_41

AE4

Vss_42

AF12

Vss_43

Y13

Vss_340

AH49

Vss_61

AU4

Vss_138

AF35

Vss_44

AP13

Vss_119

AN34

Vss_356

AF45

Vss_46

AF46

Vss_47

AF49

Vss_48

AF5

Vss_49

AF8

Vss_50

AG2

Vss_51

AG52

Vss_52

AH11

Vss_53

AH15

Vss_54

AH16

Vss_55

AH24

Vss_56

AH32

Vss_57

AV18

Vss_2

AH43

Vss_58

AH47

Vss_59

AH7

Vss_62

AJ19

Vss_63

AJ2

Vss_64

AJ20

Vss_65

AJ22

Vss_66

AJ23

Vss_67

AJ26

Vss_68

AJ28

Vss_69

AJ32

Vss_70

AJ34

Vss_71

AT5

Vss_134

AJ4

Vss_72

AK12

Vss_73

AM41

Vss_107

AN19

Vss_114

AK26

Vss_76

AK22

Vss_74

AK23

Vss_75

AK28

Vss_77

IBEXPEAK-M

GND GND

+VTT_PCH_1.5VS_1.8VS+1.5VS

@

12

R2619 0Ohm

SP2607

1 2

R0402

R2619 0Ohm

SP2604

1 2

R0402

@

R2646 0Ohm

R1.4--5

12

+1.8VS

+VTT_PCH_ORG

+1.8VS +V_NVRAM_VCCQ

Vss_78 Vss_79 Vss_80 Vss_81 Vss_82 Vss_83 Vss_85 Vss_87 Vss_88 Vss_89 Vss_90 Vss_91 Vss_92 Vss_93

Vss_185

Vss_30 Vss_95 Vss_96 Vss_97 Vss_98

Vss_99 Vss_175 Vss_100 Vss_101 Vss_102 Vss_103 Vss_104 Vss_105 Vss_106 Vss_108 Vss_137 Vss_109 Vss_143 Vss_110 Vss_113

Vss_12 Vss_176 Vss_115 Vss_116 Vss_117 Vss_118 Vss_120 Vss_121 Vss_122 Vss_123 Vss_124 Vss_125 Vss_126 Vss_127 Vss_174

Vss_60 Vss_130 Vss_131 Vss_132 Vss_133 Vss_135 Vss_139 Vss_141 Vss_142 Vss_144 Vss_145 Vss_146 Vss_147 Vss_148 Vss_149 Vss_150 Vss_151 Vss_152 Vss_153 Vss_154 Vss_155 Vss_217 Vss_156 Vss_157 Vss_158 Vss_159 Vss_160 Vss_161 Vss_162

AK30 AK31 AK32 AK34 AK35 AK38 AK43 AK46 AK49 AK5 AK8 AL2 AL52 AM11 BB44 AD24 AM20 AM22 AM24 AM26 AM28 BA42 AM30 AM31 AM32 AM34 AM35 AM38 AM39 AM42 AU20 AM46 AV22 AM49 AM7 AA50 BB10 AN32 AN50 AN52 AP12 AP42 AP46 AP49 AP5 AP8 AR2 AR52 AT11 BA12 AH48 AT32 AT36 AT41 AT47 AT7 AV12 AV16 AV20 AV24 AV30 AV34 AV38 AV42 AV46 AV49 AV5 AV8 AW14 AW18 AW2 BF9 AW32 AW36 AW40 AW52 AY11 AY43 AY47

SP2605

1 2

R0402

R0402 SP2606

SP2606

1 2

R0402

+1.05VS

+VTT_PCH_ORG

2

+VCCAFDI_VRM

+1.8VS_VCCADMI_VRM

JP2601

2

112

3MM_OPEN_5MIL

JP2602

112

1MM_OPEN_5MIL

JP2603

2

112

2MM_OPEN_5MIL

+VTT_PCH_VCCIO

4

5.172A

1.524A S0 max

3.208A S0 max

+VTT_PCH_ORG

+VTT_PCH_VCC

+VTT_PCH_VCCIO

2 1

1KOhm/100Mhz

SP2603

1 2

R0402

R1.2--11

+VTT_PCH_ORG

L2605

@

1 2

2 1

12

C2607

10UF/6.3V

+VTT_PCH_VCCAPLL_FDI

12

C2608

10UF/6.3V

@

GND

+VTT_PCH_VCCDPLL_FDI

+VTT_PCH_VCC

+VTT_PCH_VCCDPLL_EXP

SP2601R0402 SP2601R0402

L2601

@

1KOhm/100Mhz

+VTT_PCH_VCCAPLL_EXP

+VTT_PCH_VCC_EXP

12

C2606

C2605

1UF/6.3V

@

+VCCAFDI_VRM

+1.05VS

+VTT_PCH_VCCIO

+VTT_PCH_ORG

+VTT_CPU

3

GND

+VTT_PCH_VCCDPLL_EXP

12

@

+3VS

+1.8VS

+1.5VS

+3VS

1.524A S0 max

12

C2650

C2601

10UF/6.3V

1UF/6.3V

GND

2mA S0 idle

12

C2602

@

10UF/6.3V

GND

12

C2603

C2604

1UF/6.3V

@

GND

+3VS_VCCA3GBG

SP2602

1 2

R0402

+1.05VS <27,29,57,80,82>

+VTT_PCH_VCCIO <20,27>

+VTT_PCH_ORG <21,22,27>

+VTT_CPU <3,6,25,32,57,82>

+1.8VS <6,57,85>

+1.5VS <43,53,57,91>

+3VS <3,16,17,20,21,22,23,24,25,27,28,29,30,32,36,37,43,44,45,46,48,50,51,53,56,57,66,80, 86,91,92>

AB24 AB26 AB28 AD26 AD28 AF26 AF28 AF30 AF31 AH26 AH28 AH30 AH31

AJ30 AJ31

AK24

BJ24

AN20 AN22 AN23 AN24 AN26 AN28

BJ26

BJ28 AT26 AT28 AU26 AU28 AV26 AV28

AW26 AW28

BA26 BA28 BB26 BB28 BC26 BC28 BD26 BD28 BE26 BE28 BG26 BG28 BH27

AN30 AN31

AN35

AT22

BJ18

AM23

U2001G

IBEXPEAK-M

VccCore_1 VccCore_2 VccCore_3 VccCore_4 VccCore_5 VccCore_6 VccCore_7 VccCore_8 VccCore_9 VccCore_10 VccCore_11 VccCore_12 VccCore_13 VccCore_14 VccCore_15

VccIO_37

VccAPLLEXP

VccIO_30 VccIO_31 VccIO_3 VccIO_4 VccIO_5 VccIO_6 VccIO_28 VccIO_29 VccIO_7 VccIO_8 VccIO_9 VccIO_10 VccIO_11 VccIO_12 VccIO_13 VccIO_14 VccIO_15 VccIO_16 VccIO_17 VccIO_18 VccIO_19 VccIO_20 VccIO_21 VccIO_22 VccIO_23 VccIO_24 VccIO_25 VccIO_26 VccIO_27

VccIO_1 VccIO_2

Vcc3_3_4

VccVRM_2

VccFDIPLL

VccIO_38

POWER

VCC CORE

PCI E*

FDI

VssA_DAC_2

CRTLVDS

VssA_DAC_1

VccTX_LVDS_1 VccTX_LVDS_2 VccTX_LVDS_4 VccTX_LVDS_3

HVCMOS

DMI

VccPNAND_9 VccPNAND_3 VccPNAND_5 VccPNAND_4 VccPNAND_2 VccPNAND_1 VccPNAND_6 VccPNAND_7 VccPNAND_8

NAND / SPI

2

VccADAC_1

VccADAC_2

VccALVDS

VssA_LVDS

Vcc3_3_1

Vcc3_3_2

Vcc3_3_3

VccVRM_1

VccDMI_1

VccDMI_2

VccME3_3_1 VccME3_3_2 VccME3_3_3 VccME3_3_4

AE50

AE52

AF53

AF51

GND

AH38

AH39

GND

AP43 AP45 AT46 AT45

AB34

357mA

AB35

S0 max

AD35

+1.8VS_VCCADMI_VRM

AT24

61mA

AT16

S0 max

AU16

AM16 AK16 AK20 AK19

156mA

AK15 AK13

S0 max

AM12 AM13 AM15

85mA

AM8 AM9

S0 max

AP11 AP9

+VCCA_DAC_1_2

69mA S0 max

12

C2609

0.01UF/16V

GND

+3VS_VCCA_LVDS

300mA S0 max

59mA S0 max

12

C2611

C2612

0.01UF/16V

GND

+3VS_VCC_GIO

12

C2613

0.1UF/10V

GND

+VTT_CPU_VCC_DMI

12

C2648

1UF/6.3V

GND

+V_NVRAM_VCCPNAND +V_NVRAM_VCCQ

12

C2614

0.1UF/10V

GND

+3VM_VCCPEP

12

C2615

0.1UF/10V

GND

C2616

0.1UF/10V

SP2612

1 2

R0402

SP2611

1 2

R0402

SP2608

1 2

R0402

SP2609

1 2

R0402

SP2610

1 2

R0402

12

C2610

10UF/6.3V

GNDGND

395136_Checklist V1.6

+1.8VS_VCCT_LVD

12

C2649

22UF/6.3V

GND

+3VS

DELETE R2643 09-15

Must be powered even not using NAND interface.

1

+VTT_CPU

+3VS

L2609

21

1KOhm/100Mhz

L2610

21

1KOhm/100Mhz

@

+3VS

L2608

1KOhm/100Mhz

+3VS

+1.5VS

+1.8VS

21

A A

Title :

PCH(7)_POWER,GND

Kuansheng Yang

Engineer:

BG1\HW1

Size Project Name

C

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

H36Y_U30X10

1

Kuansheng Yang

26 99Monday, May 10, 2010

Rev

1.0

+VTT_PCH_VCCA_A_DPL

12

R2748

@

0Ohm

+VTT_PCH_VCCA_B_DPL

5

H49

Vss_267

H5

Vss_268

J24

Vss_269

K11

Vss_270

K43

Vss_271

K47

Vss_272

K7

Vss_273

L14

Vss_274

L18

Vss_275

L2

Vss_276

L22

Vss_277

L32

Vss_278

L36

Vss_279

L40

Vss_280

L52

Vss_281

M12

Vss_282

M16

Vss_283

M20

Vss_284

N38

Vss_293

M34

Vss_285

M38

Vss_286

M42

Vss_287

M46

Vss_288

M49

Vss_289

M5

Vss_290

M8

Vss_291

N24

Vss_292

P11

Vss_294

AD15

Vss_27

P22

Vss_296

P30

Vss_297

P32

Vss_298

P34

Vss_299

P42

Vss_301

P45

Vss_302

P47

Vss_303

R2

Vss_305

R52

Vss_306

T12

Vss_307

T41

Vss_308

T46

Vss_310

T49

Vss_311

T5

Vss_312

T8

Vss_313

U30

Vss_314

U31

Vss_315

U32

Vss_316

U34

Vss_317

P38

Vss_300

V11

Vss_318

P16

Vss_295

V19

Vss_319

V20

Vss_320

V22

Vss_321

V30

Vss_322

V31

Vss_323

V32

Vss_324

V34

Vss_325

V35

Vss_326

V38

Vss_327

V43

Vss_328

V45

Vss_329

V46

Vss_330

V47

Vss_331

V49

Vss_332

V5

Vss_333

V7

Vss_334

V8

Vss_335

W2

Vss_336

W52

Vss_337

Y11

Vss_338

Y12

Vss_339

Y15

Vss_341

Y19

Vss_342

Y23

Vss_343

Y28

Vss_344

Y30

Vss_345

Y31

Vss_346

Y32

Vss_347

Y38

Vss_348

Y43

Vss_349

Y46

Vss_350

P49

Vss_304

Y5

Vss_352

Y6

Vss_353

Y8

Vss_354

P24

Vss_358

T43

Vss_309

AD51

Vss_39

AT8

Vss_136

AD47

Vss_37

Y47

Vss_351

AT12

Vss_128

AM6

Vss_112

AT13

Vss_129

AM5

Vss_111

AK45

Vss_86

AK39

Vss_84

AV14

Vss_140

GNDGND

L2706

12

+

C2746

1UF/6.3V

C2747

1UF/6.3V

+

CE2703

@

220UF/4V

GNDGND

12

+

CE2704

@

220UF/4V

GNDGND

12

5

21

1KOhm/100Mhz

L2707

21

1KOhm/100Mhz

1.998A+344mA S0 max

+1.05VS +1.05VM_ORG

JP2701

2

112

2MM_OPEN_5MIL

+3VS +3VS_VCC3_3

JP2702

2

112

1MM_OPEN_5MIL

+3VSUS +3VSUS_ORG

JP2703

2

112

1MM_OPEN_5MIL

+5VSUS +5VSUS_ORG

JP2704

2

112

1MM_OPEN_5MIL

1 2

R2742 0OhmR2742 0Ohm

Replace +VTT_CPU to +VTT_PCH_ORG 09-15

+VTT_PCH_ORG

U2001I

AY7

Vss_163

B11

Vss_164

B15

Vss_165

B19

Vss_166

B23

Vss_167

B31

Vss_168

B35

Vss_169

B39

Vss_170

B43

Vss_171

B47

Vss_172

B7

Vss_173

BG12

Vss_218

BB12

Vss_177

BB16

Vss_178

BB20

Vss_179

BB24

Vss_180

BB30

D D

C C

B B

A A

Vss_181

BB34

Vss_182

BB38

Vss_183

BB42

Vss_184

BB49

Vss_186

BB5

Vss_187

BC10

Vss_188

BC14

Vss_189

BC18

Vss_190

BC2

Vss_191

BC22

Vss_192

BC32

Vss_193

BC36

Vss_194

BC40

Vss_195

BC44

Vss_196

BC52

Vss_197

BH9

Vss_233

BD48

Vss_198

BD49

Vss_199

BD5

Vss_200

BE12

Vss_201

BE16

Vss_202

BE20

Vss_203

BE24

Vss_204

BE30

Vss_205

BE34

Vss_206

BE38

Vss_207

BE42

Vss_208

BE46

Vss_209

BE48

Vss_210

BE50

Vss_211

BE6

Vss_212

BE8

Vss_213

BF3

Vss_214

BF49

Vss_215

BF51

Vss_216

BG18

Vss_219

BG24

Vss_220

BG4

Vss_221

BG50

Vss_222

BH11

Vss_223

BH15

Vss_224

BH19

Vss_225

BH23

Vss_226

BH31

Vss_227

BH35

Vss_228

BH39

Vss_229

BH43

Vss_230

BH47

Vss_231

BH7

Vss_232

C12

Vss_234

C50

Vss_235

D51

Vss_236

E12

Vss_237

E16

Vss_238

E20

Vss_239

E24

Vss_240

E30

Vss_241

E34

Vss_242

E38

Vss_243

E42

Vss_244

E46

Vss_245

E48

Vss_246

E6

Vss_247

E8

Vss_248

F49

Vss_249

F5

Vss_250

G10

Vss_251

G14

Vss_252

G18

Vss_253

G2

Vss_254

G22

Vss_255

G32

Vss_256

G36

Vss_257

G40

Vss_258

G44

Vss_259

G52

Vss_260

AF39

Vss_45

H16

Vss_261

H20

Vss_262

H30

Vss_263

H34

Vss_264

H38

Vss_265

H42

Vss_266

IBEXPEAK-M

+VTT_PCH_VCCA_A_DPL

+VTT_PCH_VCCA_B_DPL

357mA S0 max

4

12

C2701

22UF/6.3V

22UF/6.3V @

@

C2752

4.7UF/6.3V

4.7UF/6.3V @

@

12

C2718

@

10UF/6.3V

GND

12

C2719

1UF/6.3V

1UF/6.3V @

@

GND

+1.1VM_VCCEPW

GNDGND

GND

12

C2729

1UF/6.3V

GND

SP2702

1 2

R0603

+3VS_VCCPCORE

>1mA S0 max

2mA S0 max

52mA S0 max

344mA S0 max

12

L2704

+VTT_PCH_ORG

+1.05VM_ORG

2 1

@

1KOhm/100Mhz

@

1 2

R2743 0Ohm

Can pull down if Intel LAN is disabled.

+VTT_PCH_1.5VS_1.8VS

+VTT_PCH_VCCA_A_DPL

+VTT_PCH_VCCA_B_DPL

+VTT_PCH_SSCVCC

+VTT_PCH_VCCIO

+3VSUS_ORG

+3VS_VCC3_3

+VTT_CPU_VCCPCPU

SP2703

1 2

R0603

S0 max

12

GND

+VCC_RTC

+1.05VM_ORG

+VTT_PCH_1.5VS_1.8VS+VCCPLLVRM

+VTT_PCH_ORG

4

12

@

GND

C2702

10UF/6.3V

GND

C2723

1UF/6.3V

GND

+3VA_VCCPSUS

12

C2731

0.1UF/10V

0.1UF/10V @

@

GND

12

C2733

0.1UF/10V

0.1UF/10V @

@

GND

3

+VTT_PCH_VCCA_CLK

C2717

1UF/6.3V

+1.05VM_VCCAUX

R2744

0Ohm

1 2

12

GND

12

GND

12

GND

C2722 0.1UF/10VC2722 0.1UF/10V

72mA S0 max

73mA S0 max

12

C2724

1UF/6.3V

GND

C2725

12

0.1UF/10V

C2726

+V1.05A_INT_VCCSUS

12

0.1UF/10V

12

C2727

0.1UF/10V

GND

12

C2728

0.1UF/10V

GND

12

GND

12

GND

3

TP_PCH_VCCDSW

C2751

0.1UF/10V

C2720

1UF/6.3V

C2721

1UF/6.3V

DCPRTC

12

+VCCSST

C2730

0.1UF/10V

C2732

0.1UF/10V

U2001J

AP51

VccAClk_1

AP53

VccAClk_2

AF23

VccLAN_1

AF24

VccLAN_2

Y20

DcpSusByp

AD38

VccME_1

AD39

VccME_2

AD41

VccME_3

AF43

VccME_6

AF41

VccME_4

AF42

VccME_5

V39

VccME_11

V41

VccME_12

V42

VccME_13

Y39

VccME_14

Y41

VccME_15

Y42

VccME_16

V9

DcpRTC

AU24

VccVRM_4

BB51

VccADPLLA_1

BB53

VccADPLLA_2

BD51

VccADPLLB_1

BD53

VccADPLLB_2

AH23

VccIO_33

AJ35

VccIO_35

AH35

VccIO_34

AF34

VccIO_51

AH34

VccIO_52

AF32

VccIO_50

V12

DcpSST

Y22

DcpSus

P18

VccSus3_3_2

U19

VccSus3_3_3

U20

VccSus3_3_4

U22

VccSus3_3_5

V15

Vcc3_3_6

V16

Vcc3_3_7

Y16

Vcc3_3_8

AT18

V_CPU_IO_1

AU18

V_CPU_IO_2

A12

VccRTC

IBEXPEAK-M

+VTT_PCH_ORG

+VTT_CPU

+VTT_PCH_VCCIO

+VCC_RTC

+3VSUS_ORG

POWER

USB

Clock and Miscellaneous

PCI/GPIO/LPC

SATA

CPU

RTC PCI/GPIO/LPC

HDA

+1.05VS

+3VSUS

+5VSUS

+1.05VS <26,29,57,80,82>

+3VS

+3VS <3,16,17,20,21,22,23,24,25,26,28,29,30,32,36,37,43,44,45,46,48,50,51,53,56,57,66,80, 86,91,92>

+VTT_PCH_ORG <21,22,26>

+VTT_CPU <3,6,25,26,32,57,82>

+VTT_PCH_VCCIO <20,26>

+3VSUS <30,33,34,81,92>

+VCC_RTC <20>

+5VSUS <81,91>

+5VS

+5VS <30,31,36,37,46,48,50,51,56,57,80,86,91>

+3VSUS_ORG <21,22,24,25>

VccIO_53 VccIO_54 VccIO_55 VccIO_56

VccSus3_3_32 VccSus3_3_31 VccSus3_3_30 VccSus3_3_29 VccSus3_3_28 VccSus3_3_27 VccSus3_3_26 VccSus3_3_25 VccSus3_3_24 VccSus3_3_23 VccSus3_3_22 VccSus3_3_21 VccSus3_3_20 VccSus3_3_19 VccSus3_3_18 VccSus3_3_17 VccSus3_3_16 VccSus3_3_15 VccSus3_3_14 VccSus3_3_13 VccSus3_3_12 VccSus3_3_11 VccSus3_3_10

VccSus3_3_9 VccSus3_3_8 VccSus3_3_7 VccSus3_3_6

VccSus3_3_1

VccIO_32

V5REF_Sus

V5REF

Vcc3_3_9

Vcc3_3_10

Vcc3_3_11

Vcc3_3_12

Vcc3_3_13

Vcc3_3_14

Vcc3_3_5

VccSATAPLL_2 VccSATAPLL_1

VccIO_36

VccVRM_3

VccIO_45

VccIO_43

VccIO_47

VccIO_42 VccIO_46 VccIO_49 VccIO_48

VccIO_39 VccIO_40 VccIO_41 VccIO_44

VccME_7 VccME_8 VccME_9

VccME_10

VccSusHDA

2

V24 V26 Y24 Y26

V28 U28 U26 U24 P28 P26 N28 N26 M28 M26 L28 L26 J28 J26 H28 H26 G28 G26 F28 F26 E28 E26 C28 C26 B27 A28 A26

U23

V23

F24

K49

J38

L38

M36

N36

P36

U35

AD13

AK3 AK1

AH22

AT20

AF19

AD20

AF22

AD19 AF20 AH19 AH20

AB19 AB20 AB22 AD22

+1.05VM_ORG_R1

AA34

+1.05VM_ORG_R2

Y34

+1.05VM_ORG_R3

Y35

+1.05VM_ORG_R4

AA35

L30

2

+VCCPLLVRM

10mil trace

+VTT_PCH_VCCUSBCORE

12

C2734

1UF/6.3V

+3VSUS_VCCPUSB

GND

163mA S0 max

12

C2735

0.1UF/10V

GND

12

C2737

0.1UF/10V

+VTT_PCH_VCCIO

GND

+5VSUS_PCH_VCC5REFSUS

+5VS_PCH_VCC5REF

12

C2739

1UF/6.3V

12

C2740

0.1UF/10V

12

C2741

0.1UF/10V

+VTT_PCH_VCCAPLL

+VTT_PCH_VCC_SATA

SP2704 R0603SP2704 R0603

1 2

SP2705 R0603SP2705 R0603

1 2

SP2706 R0603SP2706 R0603

1 2

SP2707 R0603SP2707 R0603

1 2

12

C2745

1UF/6.3V

+VTT_PCH_VCCIO

SP2709 R0603SP2709 R0603

1 2

+3VSUS_ORG

1

2

D2701

BAT54C

3

+5VSUS_ORG

1 2

R2731 100OhmR2731 100Ohm 12

C2738

1UF/6.3V

GND

+3VS_VCCPPCI

12

C2743

@

10UF/6.3V

GND

12

C2744

1UF/6.3V

GND

+3VS_VCC3_3

L2705

21

@

12

C2742

1KOhm/100Mhz

@

10UF/6.3V

GND

+3VSUS_HDA

SP2708 R0603SP2708 R0603

1 2

BG1\HW1

Size Project Name

C

H36Y_U30X10

Date: Sheet of

H36Y_U30X10

1

+3VSUS_ORG

+VTT_PCH_ORG

+VTT_PCH_VCCIO

+1.05VM_ORG

+3VSUS_ORG

Title :

Engineer:

1

+3VS

1

2

D2702

BAT54C

3

1 2

R2732 100OhmR2732 100Ohm

PCH(8)_POWER,GND

Kuansheng Yang

27 99Monday, May 10, 2010

+5VS

Rev

1.0

5

PCH SPI ROM

R2833

D D

SPI_CS#0<20,44>

SPI_SO<20,44>

SPI_CS#1<20,44>

C C

SPI FROM EC

SP2801

SPI_SO

SP2802

@

For EC request.

R2833

3.3KOhm

1 2

12

+3VM_SPI_0

R0402

2nd source : 0500-0025000

R2834

3.3KOhm

1 2

@

12

+3VM_SPI_1

R0402

2nd source : 0500-0025000

1 2 3

U2802

1

CE#

2

SO

3

WP# VSS4SI

SST25VF032B

(32Mb)

@

U2801

CE# SO

HOLD# WP# VSS4SI

SST25VF032B

(32Mb)

VDD

HOLD#

SCK

8

VDD

7 6

SCK

5

+3VM_SPI+3VM_SPI

8 7 6 5

+3VM_SPI+3VM_SPI

+3VM_SPI_HOLD

R2832

3.3KOhm

1 2

@

1 2

4

R2831

3.3KOhm

12

@

12

SPISI

C2803

0.1UF/16V

+3VS +3VM_SPI

C2802

0.1UF/16V

D2801

@

1

3

2

BAT54C

12

R2847 0OhmR2847 0Ohm

SPI-M_HOLD# <44> SPI_CLK <20,44> SPI_SI <20,44>

3

+3VS

+12VS

+12VSUS

+3VM_SPI

+3VS <3,16,17,20,21,22,23,24,25,26,27,29,30,32,36,37,43,44,45,46,48,50,51,53,56,57,66,80, 86,91,92>

+12VS <45,48,91>

+12VSUS <81,91>

+3VM_SPI <20,44>

SCL_3A<21>

PCH

SDA_3A<21>

Q2801A

UM6K1N

6 1

2

SMBUS Link device

SPD

+3VS

+12VS

RN2801B

RN2801A

4.7KOHM

3 4

5

1 2

@

1 2

R2801 0Ohm

1 2

R2802 0OhmR2802 0Ohm

2

Q2801B

UM6K1N

3 4

CLKGEN DEBUG WLAN CPU XDP PCH XDP VID CONTROLLER DSP FM2010 GAME LED

SMB_CLK_S <16,17,29,44,53>

SMB_DAT_S <16,17,29,44,53>

+12VSUS

+12VS

1

2

Q2802A

UM6K1N

Q2803A

UM6K1N

6 1

@

UM6K1N

61

2

UM6K1N

Q2803B

5

+12VS

3 4

@

5

Q2802B

UM6K1N

34

+3VS

@

1 2

R2803 0Ohm

@

1 2

R2804 0Ohm

5 6

RN2801C

4.7KOHM@

RN2801D

@

4.7KOHM

7 8

CPU,VGA Thermal

SML1_CLK <21,56>

PCH

SML1_DAT <21,56>

SMB1_CLK_S <50>

SMB1_DAT_S <50>

SPI FLASH CON

SMB1_CLK<30>

EC

SMB1_DAT<30>

B B

SPI Setting for layout:

Branch as short as possible.

PCH

U2001

A

Flash CON

B

C

A A

PCH SPI

U2801

U2802J2801

EC 8512

U3001

Title :

PCH(9)_SPI,SMB

Kuansheng Yang

Engineer:

BG1\HW1

Size Project Name

C

Date: Sheet of

5

4

3

2

Date: Sheet of

Engineer:

H36Y_U30X10

1

Kuansheng Yang

28 99Monday, May 10, 2010

Rev

1.0

5

D D

+1.05VS

L2903

VDD_IO

120Ohm/100Mhz

+3VS

120Ohm/100Mhz

R2907

R2907 0Ohm

0Ohm

C2908

27PF/50V

21

L2901

21

1 2

X2901 14.31818MhzX2901 14.31818Mhz

1 3

12

2

C2905

C2905 10UF/10V

10UF/10V @

@

VDD_3.3

C2924

C2924 10UF/10V

10UF/10V @

@

4

12

C2906

0.1UF/16V

C2901

0.1UF/16V

X2_CLK

X1_CLK

C2907

27PF/50V

12

C2926

0.1UF/16V

0.1UF/16V @

@

C2902

0.1UF/16V

12

C2925

0.1UF/16V

12

C2928

0.1UF/16V

0.1UF/16V @

@

20mA

C C

B B

150mA

4

U2901B

34

GND2

35

GND3

36

GND4

37

GND5

38

GND6

39

GND7

40

GND8

41

GND9

42

GND10

43

GND11

44

GND12

45

GND13

ICS9LRS3197AKLFT

add thermal pad --11-12

12

C2929

0.1UF/16V

0.1UF/16V @

@

Reserved for Wireless team

C2930 10PF/50V

1 2

@

CLK_ICH14<21> SMB_DAT_S<16,17,28,44,53> SMB_CLK_S<16,17,28,44,53>

@

CLK_PWRGD

X2_CLK X1_CLK

VDD_3.3 R2901 33OhmR2901 33Ohm SP2901 R0402SP2901 R0402 SP2902 R0402SP2902 R0402

C2916 10PF/50V @C2916 10PF/50V @

C2936 10PF/50V @C2936 10PF/50V @

FSLC

12 12 12

1 2

3

VDD_3.3

U2901A

25

CLKPWRGD/PD#_3.3

26

GNDREF

27

X2

28

X1

29

VDDREF_3.3

30

ICS9LRS3197AKLFT

REF_3L/FSLC_3.3**

31

SDATA_3.3

32

SCLK_3.3

33

GND1

VDD_3.3

T2900T2900

T2901T2901

1

19

22

24

21

20

23

GNDCPU

CPUT1_LPR

CPUT0_LPR

CPUC0_LPR

VDDCPU_3.3

VDDDOT96MHz_3.31GNDDOT96MHz2DOT96T_LPR3DOT96C_LPR4VDD_27MHz527MHz_nonSS627MHz_SS7GND27MHz

CLK_PCH_BCLK <21>

CLK_PCH_BCLK# <21>

VDD_IO

18

17

VDDCPU_IO

CPUC1_LPR

VDDSRC_3.3

CPU_STOP#

VDDSRC_IO SRCC1_LPR SRCT1_LPR

GNDSRC SATAC_LPR SATAT_LPR

GNDSATA

8

2

FSLC

BCLK

133 0

100 1

FSLC

+3VS

12

R2916

R2916 1KOhm

1KOhm @

@

12

R2917

R2917 1KOhm

1KOhm

+3VS

R2906

R2906 10KOhm

10KOhm

1 2 1 2

1 2

CLK_DMI# <21> CLK_DMI <21>

CLK_SATA# <21> CLK_SATA <21>

STP_CPU#

16

VDD_IO

15 14 13 12 11 10 9

C2714 10PF/50V @C2714 10PF/50V @ C2715 10PF/50V @C2715 10PF/50V @

1

Reserved 3.3PF for Wireless team

+3VS

R2905

R2905 10KOhm

10KOhm

CLK_PWRGD

1 2

3

D

Q2901

Q2901 2N7002

2N7002

1

G

S

2

CLK_EN# <80>

CLK_DOT96# <21> CLK_DOT96 <21>

C2712 10PF/50V @C2712 10PF/50V @

1 2

C2713 10PF/50V @C2713 10PF/50V @

1 2

Reserved 3.3PF for Wireless team

R1.4--3

+3VS

A A

5

+1.05VS

+3VS <3,16,17,20,21,22,23,24,25,26,27,28,30,32,36,37,43,44,45,46,48,50,51,53,56,57,66,80, 86,91,92>

+1.05VS <26,27,57,80,82>

4

3

Title :

CLK_ICS9LRS3197

Kuansheng Yang

Engineer:

BG1\HW1

Size Project Name

C

Date: Sheet of

2

Date: Sheet of

Engineer:

H36Y_U30X10

1

Kuansheng Yang

29 99Monday, May 10, 2010

Rev

1.0

5

+3VA_EC

114

121

U3001

KB_ID0 SCK_EC BAT2_CNT2#

SI_EC SCE#_EC BAT1_CNT2#

EC_XIN EC_XOUT

U3001

10

LAD0

9

LAD1

8

LAD2

7

LAD3

13

LPCCLK

6

LFRAME#

22

LPCRST#/WUI4/GPD2

5

SERIRQ

15

ECSMI#/GPD4

23

ECSCI#/GPD3

126

GA20/GPB5

4

KBRST#/GPB6

14

WRST#

106

GPG0

105

FSCK

104

GPG6

103

FMISO

102

FMOSI

101

FSCE#

100

GPG2

58

KSI0/STB#

59

KSI1/AFD#

60

KSI2/INIT#

61

KSI3/SLIN#

62

KSI4

63

KSI5

64

KSI6

65

KSI7

36

KSO0/PD0

37

KSO1/PD1

38

KSO2/PD2

39

KSO3/PD3

40

KSO4/PD4

41

KSO5/PD5

42

KSO6/PD6

43

KSO7/PD7

44

KSO8/ACK#

45

KSO9/BUSY

46

KSO10/PE

51

KSO11/ERR#

52

KSO12/SLCT

53

KSO13

54

KSO14

55

KSO15

56

KSO16/GPC3

57

KSO17/GPC5

128

CK32K

2

CK32KE

85

PS2CLK0/GPF0

86

PS2DAT0/GPF1

87

PS2CLK1/GPF2

88

PS2DAT1/GPF3

89

PS2CLK2/WUI20/GPF4

90

PS2DAT2/WUI21/GPF5

110

SMCLK0/GPB3

111

SMDAT0/GPB4

115

SMCLK1/GPC1

116

SMDAT1/GPC2

117

SMCLK2/WUI22/GPF6

118

SMDAT2/WUI23/GPF7

IT8502E-L

RNX3004D

LPC_AD0<20,44> LPC_AD1<20,44> LPC_AD2<20,44> LPC_AD3<20,44>

CLK_KBCPCI_PCH<24>

LPC_FRAME#<20,44>

KB_ID0<31>

Thermal sensor

BUF_PLT_RST#<3,24,32,33,43,53,54>

SCK

SO SI SCE#

Battery

D D

C C

B B

7 8 5 6 3 4 1 2

INT_SERIRQ<20,44>

EXT_SMI#<25,44,54> EXT_SCI#<21> A20GATE<25> RCIN#<25>

EC_RST#<32>

SP3003 R0402SP3003 R0402

SP3004 R0402SP3004 R0402 SP3005 R0402SP3005 R0402

ME_AC_PRESENT<22>

12

T3028T3028

12 12

T3029T3029

KSI0<31> KSI1<31> KSI2<31> KSI3<31> KSI4<31> KSI5<31> KSI6<31> KSI7<31>

KSO0<31> KSO1<31> KSO2<31> KSO3<31> KSO4<31> KSO5<31> KSO6<31> KSO7<31> KSO8<31> KSO9<31> KSO10<31> KSO11<31> KSO12<31> KSO13<31> KSO14<31> KSO15<31>

PM_PWRBTN#<22>

OP_SD#<37>

T3027T3027 T3030T3030 T3021T3021

DISTP#<56> TP_CLK<31>

TP_DAT<31>

SMB0_CLK<60,88> SMB0_DAT<60,88> SMB1_CLK<28> SMB1_DAT<28> THRO_CPU<3>

47OHM

47OHM 47OHM

47OHM

1 1 1

RNX3004C

RNX3004C RNX3004B

RNX3004B RNX3004A

RNX3004A

CLK_KBCPCI

BUF_PLT_RST#

EXT_SMI# EXT_SCI# A20GATE RCIN# EC_RST#

1

PM_PWRBTN# OP_SD#

PS2CLK0 PS2DAT0 PS2CLK1 DISTP# TP_CLK TP_DAT

SMB0_CLK SMB0_DAT SMB1_CLK SMB1_DAT THRO_CPU ME_AC_PRESENT

127

VSTBY6

VSTBY_126VSTBY_250VSTBY_392VSTBY_4

VSTBY_5

LPC

RING#/PWRFAIL#/LPCRST#/GPB7

FLASH ROM

KBMX

SMBusPS/2

VSS_11VCORE12VSS_227VSS_349VSS_491VSS_5

12

GND

4

+3VACC

+3VS

74

3

11

PWM0/GPA0

VCC

VBAT

C3010

0.1UF/10V

PWM1/GPA1

AVCC

PWM2/GPA2 PWM3/GPA3 PWM4/GPA4 PWM5/GPA5 PWM6/GPA6 PWM7/GPA7

RXD/GPB0 TXD/GPB1

GPB2

GPC0

TMRI0/WUI2/GPC4

TMRI1/WUI3/GPC6

PWUREQ#/GPC7

RI1#/WUI0/GPD0 RI2#/WUI1/GPD1

GINT/GPD5 TACH0/GPD6 TACH1/GPD7

L80HLAT/GPE0

EGAD/GPE1 EGCS#/GPE2 EGCLK/GPE3

PWRSW/GPE4

WUI5/GPE5

GPIO

LPCPD#/WUI6/GPE6 L80LLAT/WUI7/GPE7

GPG1/ID7

CLKRUN#/WUI16/GPH0/ID0

WUI17/GPH1/ID1 WUI18/GPH2/ID2 WUI19/GPH3/ID3

GPH4/ID4 GPH5/ID5 GPH6/ID6

ADC0/GPI0 ADC1/GPI1 ADC2/GPI2 ADC3/GPI3 ADC4/GPI4 ADC5/GPI5 ADC6/GPI6 ADC7/GPI7

DAC0/GPJ0 DAC1/GPJ1 DAC2/GPJ2 DAC3/GPJ3 DAC4/GPJ4 DAC5/GPJ5

VSS_6

AVSS

75

113

122

delete pin 81 net follow EC Team suggestion 09-14

EC_AGNDGND

kurt

R3011 for IT8512BX & IT8512CX C3009 & C3008 for IT8512DX

PWR_LED#

24

CHG_LED#

25

BATSEL_3S#

28

GPA3

29

LCD_BL_PWM

30

FAN_PWM

31

BAT1_CNT1#

32

BAT2_CNT1#

34

CHG_EN#

108

PRECHG

109

CTX0

123

PM_RSMRST#

112

CRX0

119

AC_IN_OC#

120

BAT1_IN_OC#

124

RFON_SW#

16

PWRLIMIT#

18

PM_SUSC#

21

LCD_BACKOFF#

33

FAN0_TACH

47

COLOREN#

48

VSUS_ON

19

SUSC_EC#

82

SUSB_EC#

83

CPU_VRON

84

PWR_SW#

125

BAT2_IN_OC#

35

LID_SW#

17

CAP_ACK#

20

107

PM_CLKRUN#

93

3G_ON

94

GFX_VR_ON_C

95

BAT_LEARN

96

SCRL_LED#

97

NUM_LED#

98

CAP_LED#

99

PCH_TEMP_ALERT#

66

SUS_PWRGD

67

ALL_SYSTEM_PWRGD

68

VRM_PWRGD

69

ME_PM_SLP_LAN#

70

ALS_AD

71

ME_PM_SLP_M#

72

ME_SUSPWRDNACK

73

CAP_RST#_EC

76

PM_PWROK

77

KB_ID1

78

BATSEL_2P#

79

TP_LED#

80 81

T3013T3013

1

T3014T3014

1

T3015T3015

1

T3007T3007

1

R3084 0Ohm@R3084 0Ohm@

1

T3018T3018

PWR_LED# <56> CHG_LED# <56>

LCD_BL_PWM <45> FAN_PWM <50>

T3009T3009

1

T3011T3011

1

T3008T3008

PM_RSMRST# <22>

T3010T3010

AC_IN_OC# <90>

BAT1_IN_OC# <90> RFON_SW# <56>

PWRLIMIT# <3,90> PM_SUSC# <22> LCD_BACKOFF# <45> FAN0_TACH <50>

T3053T3053

VSUS_ON <81,93> SUSC_EC# <57, 91> SUSB_EC# <43,57,91,92> CPU_VRON <80> PWR_SW# <56>

LID_SW# <37,45> CAP_ACK# <56>

PM_SUSB# <22>

12 1 1 1

PCH_TEMP_ALERT# <25> SUS_PWRGD <81,92> ALL_SYSTEM_PWRGD <22,92> VRM_PWRGD <80,92> ME_PM_SLP_LAN# <22>

T3020T3020

ME_PM_SLP_M# <22> ME_SUSPWRDNACK <22>

CAP_RST#_EC <56> PM_PWROK <22> KB_ID1 <31>

TP_LED# <56> PCH_SPI_OV <20,44>

PM_CLKRUN# <22>

T3012T3012 T3016T3016 T3055T3055

CAP_LED# <56>

3G_ON# <53> GFX_VR_ON <6,91>

3

For IT8752 Power

+3VA_EC

L3001

120Ohm/100Mhz

R3035 10KOhmR 3035 10KOhm

1 2

+3VA_EC+3VA

21

LID_SW#

12

C3003

C3003 10UF/10V

10UF/10V

For PU / PD

+3VA_EC

+3VS

R3021 47KOhmR3021 47KOhm

1 2

R3023 47KOhmR3023 47KOhm

1 2

RN3001A

1 2

RN3001B

3 4

RN3001C

5 6

RN3001D

7 8

PM_SUSB# PM_SUSC#

VSUS_ON CPU_VRON

CAP_ACK#

PM_RSMRST#

Note: EXT_SMI#, EXT_SCI#, PU power plane depend on ICH9 GPIO.

For X'tal

EC_XIN

R3046

R3046 10MOhm @

10MOhm @

X3001 32.768KhzX3001 32.768Khz

1 4

C3016

15PF/50V

1 2

BAT1_IN_OC#

BAT2_IN_OC#

SMB0_CLK

4.7KOHM

4.7KOHM SMB0_DAT

4.7KOHM

4.7KOHM SMB1_CLK

4.7KOHM

4.7KOHM SMB1_DAT

4.7KOHM

R3029 100KOHMR3029 100KOHM

1 2

R3004 100KOHMR3004 100KOHM

1 2

R3031 100KOHMR3031 100KOHM

1 2

R3005 100KOHMR3005 100KOHM

1 2

R3006 100KOHM@R3006 100KOHM@

1 2

R3022 10KOhmR3022 10KOhm

1 2

Note:

Cload=12.5PF place close to EC

EC_XOUT

12

2

3

C3017

C3017 15PF/50V

15PF/50V

1 2

2

+3VA_EC

12

C3004

0.1UF/10V

R3009

1 2

0Ohm

12

EC_AGND

+3VA_EC

+5VS

C3005

0.1UF/10V

+3VS

R3036 10KOhmR 3036 10KOhm

1 2

R3028 10KOhmR 3028 10KOhm

1 2

R3030 10KOhmR 3030 10KOhm

1 2

R3032 10KOhmR 3032 10KOhm

1 2

R3034 10KOhmR 3034 10KOhm

1 2

RN3002A

RN3002A RN3002B

RN3002B RN3005A

RN3005A RN3005B

RN3005B

GND

+3VSUS

1 2

R3024 10KOhm

Reserved as no-stuff. PCH internally pull up.

12

C3006

C3006 10UF/10V

10UF/10V

12

C3002

0.1UF/10V

1 2

4.7KOHM

3 4

4.7KOHM

1 2

4.7KOHM

3 4

4.7KOHM

R3025 10KOhmR 3025 10KOhm

1 2

R3026 10KOhmR 3026 10KOhm

1 2

R3033 10KOhmR 3033 10KOhm

1 2

@

PM_PWRBTN#

R3007

1 2

0Ohm

CAP_ACK#

PWRLIMIT#

AC_IN_OC#

RFON_SW#

PWR_SW#

TP_CLK TP_DAT SUSB_EC# SUSC_EC#

A20GATE

RCIN#

DISTP#

12

C3007

0.1UF/10V

+3VACC

12

C3001

0.1UF/10V

EC_AGND

R1.2_Jervis091113

For +3VPLL Put beside pin 121

iAMT EC strapping need to check

For EC Hardware Strap

I/O Base Address

Note: It can be programmable by EC fireware

Share Memory

Note: It can be programmable by EC fireware.

PP Enable

Note: Default Int. Pull-Low

For iAMT pin name

AC_PRESENT PM_S4_STATE# S4_STATE_ON PM_SLP_M# SLP_M_ON EC_WLAN_PWR MP_PWRGD AC_PRESENT LAN_WOL_EN +3VM_PG +1.5VM_+3VMCLK_PG SUSPWR_ACK

+3VA_EC

1

510 ken

T3003T3003

T3002T3002

1

GND

+3VA_EC

R3053

3.3KOhm

SCE#

SP3006 R0402SP3006 R0402

A A

+3VA_EC

+3VSUS

+3VA_EC <32>

+3VS

+3VS <3,16,17,20,21,22,23,24,25,26,27,28,29,32,36,37,43,44,45,46,48,50,51,53, 56,57,66,80,86,91,92>

+3VSUS <27,33,34,81, 92>

5

4

3

1 2

SO_ROMSO

12

ROM_WP#

U3003

U3003 1 2 3 4

GND

CS#

VCC

SO

HOLD#

WP#

SCK

GND

MX25L512MC-12G

(512Kb)

8

ROM_HD#

7

SCK

6

SI

5

SI

2nd source : 0500-001L000

2

+3VA_EC

12

R3043

C3019

3.3KOhm

0.1UF/16V

1 2

BG1\HW1

Size Project Name

C

H36Y_U30X10

Date: Sheet of

H36Y_U30X10

Title :

Engineer:

1

EC_IT8512(1)

Kuansheng Yang

30 99Monday, May 10, 2010

Rev

1.0

PEGATRON H36Y Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual