![](/html/7b/7b29/7b295d7cf1f5032b572350a101f30ee08efd2d28641afcad05bffa1a6ea27b41/bg2.png)
70
67
13
62
56
55
68
+B2
SQCK
SUBQ
80
14
15
48
53
41
52
DSLF2
47
46
44
+B2
76
78
MLD
MCLK MCLK
MDATA
+B2
STAT
9
7
8
45
17
79
54
49
61
IOSEL
CRC
BLKCK
/CLDCK
SBCK
SUBC
DEMPH
SSEL
SQCK
SUBQ
PLLF
PCK
PLLF2
384FS
DSLF
DRF
ARF
RSEL
PSEL
MLD
MDATA
IREF
STAT
MSEL
VCOF2
VCOF
BYTCK
buffer
Subcode
DSL / PLL VCO
VCO
69
66
CLVS
RESY
buffer
CD-text
Sync interpolation
EFM demodulation /
Subcode demodulation
Micro computer
interface
Timing
generator
pitch control
MN662790RSA1
+B2
DISCK
DI DATA
DILRCK
SERVOPROCESSOR / DIGITAL SIGNAL PROCESSOR
+B2
DIGITAL FILTER / D/A CONVERTER
IC702
+B2
79 8078
DIDATA
DILRCK
72 71
DISCK
450
/TEST
DVDD1
AVDD1
Digital deemphasis
16k
SRAM
deinterleave
Circ error correction/
77
60
DD2
VDD
IOVDD
AV
digital filter
8 times oversampling/
Digital audio
interface
Digital audio
interface
Interporation/
soft muting/
digital attenuation
Servo CPU
5745157
DVss1
AVss1
AVss2
(L)
PWM
1 bit DAC
PWM logics
(R)
PWM
Vss
D/A
converter
Output
port
73
OUTL
75
OUTR
65
FLAG
64
IPFLAG
TX
ECM ECM
ECS ECS
PC PC
LRCK
SRDATA
BCLK
DMUTE
DSLF2 DSLF2
KICK
TRV
VREF VREF
TVD TVD
TRD TRD
FOD FOD
TBAL TBAL
FBAL FBAL
/TLOCK
/FLOCK
IPFLAG
6
24
25
23
2
3
SRDATA
1
16
42
26
21
29
22
27
28
31
30
12
11
Rch
LRCK
BCLK
A/D converter Input port
CSEL
FCLK
20
X2 OUT
59 58
X701
(16.9344MHZ)
X1 IN
FE
32 33 34
FE
TE
TE
SMCK
19
63
RFENV
RFENV
TRCRS
VDET
37 35 39
BDO
BDO
Servo
timing generator
OFT
/RFDET
38 36
/RFDET
OFT
WVEL
SENSE
10 43 40
LDONLDON
/RST
18
/RST
![](/html/7b/7b29/7b295d7cf1f5032b572350a101f30ee08efd2d28641afcad05bffa1a6ea27b41/bg3.png)
+B4
32 16
1,6,
22
+B4
23,39,
44
TC7W04FUT2L
IC1003
INVERTER
TC7W14FUTE1L
IC1004
INVERTER
BCLK
LRCK
SRDATA
IPFLAG
/CLDCK
ISRDATA
ILRCK
IBCLK
TC7W14FTC12L
IC403
INVERTER
X1000
(27MHz)
106
117
3
5
4
86
6
123
110
108
111
122
Vcc
A0~10
5~12,2326,
27
44~46,
48,
54,
50~52
56~58
VCK
MA0~10
HCK
CD BCK
CD LRCK
CD DATA
DA XCK
CD C2PO
CDG-VFSY
DA-DATA
DA-LRCK
DA-BCK
CDG-SDATA
LH532KU1
IC1001
2M ROM
GND
A11~17/
D0~7
17~21,
2~4,
25,28~30
13~15
10~15,
21,
17,19,
23~29
MD0~15
MN89103M2
MPEG VIDEO AUDIO DECODER
IC1000
OE
M44260CTP7
15
WE
CE
2224
37
MCE
18~
21
38
MWE
Vcc
A0~8
24~
28
IC1002
4M DRAM
DQ1
2~5,
35~38,
7~10
40~43
COMPOS-OUT
CLK SEL(0)
CLK SEL(1)
CLK SEL(2)
CLK SEL(3)
VDDMAX-IN
VDDMAX-OUT
~16
RAS0
CAS
Y-OUT
C-OUT
VGAIN
VREF
Vss
42
40
69
75
72
73
67
77
78
79
81
61
109
OE
29
RAS
UCAS
16 30 31
+B4
+B4
LCAS
+B5
+B3
HCK
114
HINT
HINT
107
DA-EMP
121
EMPH
HSEL
119
HSEL
HD-IN
112
HDIO
HDO-OUT
HRDY
113
60
HRDY
RESET
VRST
2,16,39,
47,53,80,
99,104,
116,
D606
()
Vss
I/O Vss
20
68,
71,
76,
85
AGND
14 15
10 11 12
LD DATA
18,22,41,
49,55,82,
102,118,
120
PLAY
DATA
+B3
LD CLK
VDD3
66,70,
74,87
STOP
CLK
AVDD
+B5
D601~605
(DCSC1~5)
1~4,
6~9,
16,17
DISC1~5
1~5PLAY/
/STB
LD STB
Vss
VDD
NJU3713GTE1
IC601
LED DRIVE
5
18
+B6
![](/html/7b/7b29/7b295d7cf1f5032b572350a101f30ee08efd2d28641afcad05bffa1a6ea27b41/bg4.png)
/RST
MCLK
MDATA
MLD
VIDEO
OUT
69
71
72
70
+B8
+B6
+B7
+B4
SRVRST
MCLK
MDATA
MLD
+B1
+B3
+B5
41
Q16,17
Regulator
Q14,15
Regulator
UPC29M33HB
IC11
Regulator+B2
Q20,21
Regulator
Q18,19
Regulator
A.GND D.GND V.GND CT.GND
EMPH
42
EMPH
HCK
HRDY
46
45
HCK
HRDY
CSEL
23
47
HDI
SUBQ
16
HDIO
HDO
BLKCK
HINT
HSEL
HINT
STAT
7778
D17,18
446843
HSEL
REST
SW
21
VRST
VRST
LD DATA
5
LD DATA
SQCK
Q13,12
Regulator
Switching
Q11
LD STB
LD CLK
7
6
13
LD STB
LD CLK
KEY1~3
1~367
D11~13
D405
+B6
12
73
74
VREF
PWCNT
M38067MC412F
IC401
SYSTEM CONTROL
8
VCC
REQ
SW5
15
19
+B6
25
65
CS
HALT
SW118SW2
Q402
TEST
20
Inter-
face
9
SW3
CLK
24
+10V
Q403,
404
10DI11
SW4
Inter-
face
DO
39
HALF
40CW38
30
Rch
(8MHz)
CFI
X401
CCW
31
32 7526
JK401
27
CFO
SS
V
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20 NC
RESET
CNVS
SYNC1
CD REQ
CT.GND
CS
+B(10V)
D.GND
SCLK
DATA
NC
V.GND
NC
NC
NC
NC
NC
CD Rch OUT
A.GND
CD Lch OUT
NC
To SOUND
PROCESSOR/
CASSETTE
DECK
BLOCK DIAGRAM
Q404
Reset +B6
VREF-
PLG
37
17
PSTN
TC74HCT7007A
CONVERTER
(3.3V To5V)
SUBQ
BLKCK
STAT
+B2
(REST)
SQCK
IC402
S701
Q405,
+B6
14
Vcc
1
11
9
GND
7
+B6
KEY SWITCH
1213
Y5A5
2
Y0A0
10
Y4A4
8
Y3A3
(S601~623)
TA7291S
MOTORDRIVE
(LOADING
MOTOR)
IC1
M
RM1
S5
2
10
(BOTTOM)
4
1
7,8
S2
S3
(OPEN DET.)
S4
Q1
Motor
drive
(CLAMP)
S1
(TRAYPOSITION 1
DET.)
DET.)
(TRAYPOSITION 2
D2
5
(POSITION
6
SENSOR)
+B8
PLUNGER
D1
406
Plunger
drive
+B6
+B7
Note:
: CD-DA//VCD(audio&video) signal : CD-DA/VCD(audio) signal
:VCD(video) signal
![](/html/7b/7b29/7b295d7cf1f5032b572350a101f30ee08efd2d28641afcad05bffa1a6ea27b41/bg5.png)
SCHEMATIC DIAGRAM 1
NOTE:
The number which noted at the connectors
on the schematic diagram as
"SCHEMATICDIAGRAM
"SCHEMATICDIAGRAM
indicates fhe schematic diagram
serial number located on the left corner
in the schematic diagram.
OPTICAL PICKUP
0.1
8
3
LD
11
12
2
10
5
4
9
6
1 2 3 4
Vcc
BIN
GND
NBOUT
GND
NAOUT
8 7 6 5
AIN
VREF
1" or
2"
1K
680P
680P
0.047
1
2
3
4
5
6
7
8
9
10
11
13
14
15
LD.GND
VREF
Vcc
PDF
PDE
LD
GND
NB
GND
NA
LPD
GND
T+
T
F+
F
CD SERVO CIRCUIT
A
Q701
2SB709STX
LASER POWER
DRIVE
C750
0.1
R752
0
A
B
C
D
E
10
1212
13
14
15
1616
1
2
3
4
5
6
7
8
9
11
CN701
C751
0.1
4.7
C701
(2.5V)
3V
1.7V 3.3V1.7V 1.7V 1.7V
PDF
PDE
FBAL
TBAL
3.3V
(2.5V)
D
E
C
A
B
C712
0.1
C711
0.1
R701
1V
6.3V33
0.1
C704
Vcc
PDA
VREF
FEN
C747
180P
R744
120K
C749
1800P
C742 0.027
C703
PLAY
6.3V100
0.5 s. 0.2V/DIV.
(0.2V)0V(2.5V)3V(1.5V)
LPD
PDB
FEOUT
TEOUT
C710
10K
R702
120P
R705
LD
TEN
150K
:POSITIVE VOLTAGELINE
DA/VCD(AUDIO & VIDEO)SIGNALLINE
:CD
5V
3.3V
0.8V
TJ701
P P
(RF) TP30
TP29
0.1
C707
0.027
C706
C702
2700P
1V 0.7V 2.1V
RF
NC
(2.3V)
1.8V 0V
CSBRT
ENV
CEA
NC
1.7V1.7V1.7V1.7V1.7V1.7V1.7V1.7V1.7V
RFIN
NC
1.7V 1.7V 0V 3.2V
C716
820P
IC701
AN8839NSBE2
SERVOAMP
(3.2V)
0V
BDO
LDON
OFTR
PDOWN
1413121110987654321
GND
/RFDET
1516171819202122232425262728
(0V)
B
A
M702
SPINDLE
MOTOR
M701
TRAVERSE
MOTOR
TRACKING
COIL
FOCUS
COIL
M
M
C737
TP35
TP38
C736
TP37
CB A
D
0.1
0.1
C713
BADC
(0.4V) (0.2V) (0.1V) (0.4V)0V(0.2V)
0V 0V 0V 0V 7.8V 7.8V 1.7V 1.7V 1.7V
14 15 16 17 18 19 20
D3+
D3
D2+
13 12 11 10 9 8 7
A
0.1
B
C
0.1
D
C735
0V 0V 0V 0V
(0.1V) (0.7V) (0.6V)
AB CD
0.1
C734
10V220
D4
D1+
D2
D4+
D1
22K
R708
TP42
I
TJ702
(VREF)
IC703
C714
6.3V100
AN8739SBE2
FOCUS COIL/
TRACKING COIL/
TRAVERSEMOTOR/
SPINDLE MOTOR DRIVE
NC
PGND2
PGND1
NC
22K
R707
HGFEDC
PVcc2
PVcc1
7.8V
GND
GND
1K
R706
2ms. 0.1V/DIV.
21 22 23 24 25 26
NC
PC1
6 5 4 3 2 1
6.8K
R723
PLAY
Vcc
IN1
TP33
R736
100
VREF
NC
1K
R704
0.2V
P P
BA
IN4
PC2
(0V)
100
R724
R735
IN3
IN2
18K
PLAY
2ms. 0.1V/DIV.
RSTIN
NC
1.7V1.7V3.2V1.7V1.7V
R725
390
1K
R715
NC
/RST
0.6V
P
C715
2700P
P
AB
R729
3.9K
R727
C752
C739
7.7V
7.8V
3.9K
1500P
1500P
C738
0.01
R749
4.7K
R728
3.9K
R731
6.8K
C
A
B
D
E
F
G
![](/html/7b/7b29/7b295d7cf1f5032b572350a101f30ee08efd2d28641afcad05bffa1a6ea27b41/bg6.png)
SCHEMATIC DIAGRAM 2
:POSITIVE VOLTAGELINE :CD DA/VCD(AUDIO & VIDEO) SIGNALLINE :CD DA/VCD(AUDIO) SIGNAL LINE
R711
C717
120K
0.1
F=16.9344MHz
C722
10P
C721
10P
47K
R709
C744
5600P
0.1
C724
X701
(16.9344MHz)
120
R714
E
B
L
A
R741 47K
R742
220K
2.4V
P
P
R710
10
C723
10V220
(0.1V)
(1.2V)0.2V
470
R712
0.47
C718
2ms. 0.1V/DIV.
C732
PLAY
6.3V220
PLAY
F=7.35Hz
3.3V
1.6V
1.6V
0V
3.2V
2.4V
3.3V
0V
1.7V
1.7V
1V
1.7V
1.7V
0.6V
P
0.1
C733
NM
10
R716
3.3V
0V
3.3V
5V(0V)
61
62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
CLVS
FCLK
FLAG
BYTCK
DD
V
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P
X2 OUT
X1 IN
Vss
SBCK
SUBC
VCOF2
PCK
384FS
AVss2
DD2
AV
VCOF
PLLF
DSLF
DRF
IREF
ARF
WVEL
DSLF2
PLLF2
IPFLAG
/CLDCK
F=16.9344MHz
IC702
MN662790RSA1
SERVO PROCESSOR/
DIGITALSIGNALPROCESSOR/
DIGITALFILTER/
D/A CONVERTER
PLAY
0.8V
BDO
/RFDET
3.2V(0V)
TRCRS
P
VDET
OFTR
0V
DF
0.5 s. 0.2V/DIV.
LDON
0V(3.2V)
0V
P
1.7V
CRC
0.3V
P
C731
6.3V220
RESY
DEMPH
P
PLAY
T 13.3ms.
T 26.6ms.
FETERFENV
1.7V
1.7V
R721
C730
0.1
/TEST
IOSEL
T 13.3ms.
PLAY
FBAL
TBAL
1.7V
1.7V
100
3V
1.6V3V1.6V
3V
DD1
OUTL
AVss1
AV
PLAY
5V
0V
PLAY
T 13.3ms.
0V
TRD
FOD
VREF
1.7V
1.7V
1.7V
PLAY
1kHz, 0dB
3V
RSEL
OUTR
5V
0V
5V
0V
3.3V
ECS
NC
1.7V
5.1V
IOVDD
ECM
1.7V
(1.3V)0V
3.2V(0V)
R717
2.2V
P P
R718
2.5V
DIDATA
PC
1.7V
GFEDCBAABC E GH I
100
100
2.5V
DISCK
DILRCK
SRDATA
DVDD1
DVss1
MCLK
MDATA
SENSE
/FLOCK
/TLOCK
BLKCK
SQCK
SUBQ
DMUTE
SMCK
NC
TVD
2122232425262728293031323334353637383940
BCLK
LRCK
STAT
CSEL
C725
1000P
C726
1000P
1
2
3
4
5
TX
6
7
8
MLD
9
10
11
12
13
14
15
16
17
/RST
18
19
20
PLAY
2ms. 0.1V/DIV.
R719
R720
5.1V
5.1V
2.4V
2.5V
0V
(2.4V)
3.3V
0V
(3.9V)
4.8V
(4V)
4.8V
4.8V
0V
4.9V
3.3V
0V(3.3V)
4.9V
0
0
0.2V
P
TP21
TP23
PLAY
F=44.1kHz
P
R753
C745
10
1000P
4.6V
0V
3.3V
5V
A
B
V
U
T
S
PLAY
R
P
Q
0.2 s. 1V/DIV.
O
K
J
I
H
G
F
D
C
4.8V
0V
TP16
S701
(REST)
7.8V
D
TP4
TP2
1
32 4 5 6 7 8 9 10 11 12 13
/RST
SUBC
STAT
SBCK
SQCK
SUBQ
VCOF
REST SW
BLKCK
MLD
KJIHGFECBA
LM
TP14TP13TP12TP8TP7TP6TP5TP3TP1
TP15
C743
MCLK
384FS
P.GND
MDATA
G
To MAIN CIRCUIT(CN402)
on SCHEMATIC DIAGRAM 7
N
TP18
L701
100
R713
+B(1)
IPFLAG
TP20
CLDCK
0.1
PQR STUV
O
TP17
L704
L702
L703
TP19
23 24 25 26 27 28 29
TX
LRCK
D.GND
+B(2)
BCLK
SRDATA
DISCK
DILRCK
C753
470P
3.3V
IOVDD
Rch OUT
A.GND
DIDATA
B
A
CN702
3021 2220191817161514
Lch OUT