Panasonic MN6152U Datasheet
For Communications Equipment
MN6152U
PLL LSI with Built-In Prescaler
Overview
The MN6152U is a CMOS LSI for a phase-locked loop
(PLL) frequency synthesizer with serial data input.
It consists of a two-coefficient prescaler, variable
frequency divider, phase comparator, and charge pump.
It offers high-speed operation on a low power supply
voltage (1.8 to 2.5 V) and low power consumption (5 mW
for V
=2.0 V, FIN=100 MHz).
DD
Other features include intermittent operation by the
power save (PS) control signal and high-speed pull-in that
rapidly corrects the phase differences occurring at the start
of operation.
Features
Low power supply voltage: VDD=1.8 to 2.5V
Low power consumption: 5mW (VDD=2.0V,
F
=100MHz)
IN
High-speed operation: FIN=175MHz
Frequency dividing ratios in reference frequency
dividing stage: 5 to 131,071
Frequency dividing ratios in comparator stage: 272 to
262,143
Lock detector output pin
Two types of phase comparator output
- Internal charge pump output
- Output for external charge pump
Output monitor pins for both comparator and refer-
ence frequency dividing stages
Pin Assignment
X
X
OUT
FV
V
D
V
LD
F
DD
1
IN
2
3
4
5
OP
6
SS
7
8
IN
SSOP016-P-0225
(TOP VIEW)
OR
16
OV
15
LC
14
FR
13
PS
12
LE
11
DATA
10
CLK
9
MN6152U For Communications Equipment
Block Diagram
FR
13
LC
14
Phase comparator
17-bit latch
17-bit programmable counter
Control
18-bit shift register
16
OR
OP
D
5
FV
3
14-bit programmable
counter
LD
OV
7
15
18-bit latch
Phase
matching
Amplifier
1
IN
X
Swallow
counter
Data control
Prescaler and
phase matching
Amplifier
2
OUT
X
9
CLK
10
DATA
11
LE
12
PS
8
IN
F
For Communications Equipment MN6152U
Pin Descriptions
Pin No. Symbol Function Description
1X
2X
IN
OUT
3FV
4VDDPower supply
Crystal oscillator connection pins:
XIN =Oscillator circuit input pin;
X
=Oscillator circuit output pin.
OUT
Frequency divider output signal in comparator stage.
Phase comparator input monitor.
5D
OP
Low-pass filter connection pin. Use a passive filter.
6VSSGround
7LD
Phase comparator output pin:
"H" level for locked; "L"level for unlocked.
8FINFrequency divider input pin in comparating stage.
9 CLK
Shift register clock input pin.
The chip latches data at the rising edge of the CLK signal.
Shift register data input pin.
10 DATA
The final two bits in the data select the write latch:
"11" for R-latch; "01" for N-latch.
Load enable signal input pin.
11 LE
This is the latch-write-enable signal. It is at "H" level for write.
Power save control signal input pin.
"H" level input starts the frequency divider and places the chip in operational mode.
12 PS
"L" level input places the chip in standby mode, which saves power.
The chip switches the internal charge pump output to the H-z state and the loop
is opened.
13 FR
Reference frequency divider output signal.
Phase comparator input monitor.
Charge pump control signal output pin.
14 LC
When frequency divider operation is stopped, this pin is at "L" level, the
internal charge pump output is in the high-impedance state, and the loop is opened.
15 OV
16 OR
Phase comparator output pin for external charge pump.
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